drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  49
  50 #define I40E_CLEAR_PXE_WAIT_MS     200
  51 #define I40E_VSI_TSR_QINQ_STRIP         0x4010
  52 #define I40E_VSI_TSR(_i)        (0x00050800 + ((_i) * 4))
  53
  54 /* Maximun number of capability elements */
  55 #define I40E_MAX_CAP_ELE_NUM       128
  56
  57 /* Wait count and interval */
  58 #define I40E_CHK_Q_ENA_COUNT       1000
  59 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  60
  61 /* Maximun number of VSI */
  62 #define I40E_MAX_NUM_VSIS          (384UL)
  63
  64 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  65
  66 /* Flow control default timer */
  67 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  68
  69 /* Flow control enable fwd bit */
  70 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  71
  72 /* Receive Packet Buffer size */
  73 #define I40E_RXPBSIZE (968 * 1024)
  74
  75 /* Kilobytes shift */
  76 #define I40E_KILOSHIFT 10
  77
  78 /* Flow control default high water */
  79 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Flow control default low water */
  82 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  83
  84 /* Receive Average Packet Size in Byte*/
  85 #define I40E_PACKET_AVERAGE_SIZE 128
  86
  87 /* Mask of PF interrupt causes */
  88 #define I40E_PFINT_ICR0_ENA_MASK ( \
  89                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  93                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  94                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  96                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  97                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  98
  99 #define I40E_FLOW_TYPES ( \
 100         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 105         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 108         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 109         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 110         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 111
 112 /* Additional timesync values. */
 113 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 114 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 115 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 116 #define I40E_PRTTSYN_TSYNENA     0x80000000
 117 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 118 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 119
 120 /**
 121  * Below are values for writing un-exposed registers suggested
 122  * by silicon experts
 123  */
 124 /* Destination MAC address */
 125 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 126 /* Source MAC address */
 127 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 128 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 129 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 130 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 131 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 132 /* Single VLAN tag in the inner L2 header */
 133 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 134 /* Source IPv4 address */
 135 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 136 /* Destination IPv4 address */
 137 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 138 /* Source IPv4 address for X722 */
 139 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 140 /* Destination IPv4 address for X722 */
 141 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 142 /* IPv4 Protocol for X722 */
 143 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 144 /* IPv4 Time to Live for X722 */
 145 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 146 /* IPv4 Type of Service (TOS) */
 147 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 148 /* IPv4 Protocol */
 149 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 150 /* IPv4 Time to Live */
 151 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 152 /* Source IPv6 address */
 153 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 154 /* Destination IPv6 address */
 155 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 156 /* IPv6 Traffic Class (TC) */
 157 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 158 /* IPv6 Next Header */
 159 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 160 /* IPv6 Hop Limit */
 161 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 162 /* Source L4 port */
 163 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 164 /* Destination L4 port */
 165 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 166 /* SCTP verification tag */
 167 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 168 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 169 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 170 /* Source port of tunneling UDP */
 171 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 172 /* Destination port of tunneling UDP */
 173 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 174 /* UDP Tunneling ID, NVGRE/GRE key */
 175 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 176 /* Last ether type */
 177 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 178 /* Tunneling outer destination IPv4 address */
 179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 180 /* Tunneling outer destination IPv6 address */
 181 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 182 /* 1st word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 184 /* 2nd word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 186 /* 3rd word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 188 /* 4th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 190 /* 5th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 192 /* 6th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 194 /* 7th word of flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 196 /* 8th word of flex payload */
 197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 198 /* all 8 words flex payload */
 199 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 200 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 201
 202 #define I40E_TRANSLATE_INSET 0
 203 #define I40E_TRANSLATE_REG   1
 204
 205 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 206 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 207 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 208 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 209 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 210 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 211
 212 /* PCI offset for querying capability */
 213 #define PCI_DEV_CAP_REG            0xA4
 214 /* PCI offset for enabling/disabling Extended Tag */
 215 #define PCI_DEV_CTRL_REG           0xA8
 216 /* Bit mask of Extended Tag capability */
 217 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 218 /* Bit shift of Extended Tag enable/disable */
 219 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 220 /* Bit mask of Extended Tag enable/disable */
 221 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 222
 223 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 224 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 225 static int i40e_dev_configure(struct rte_eth_dev *dev);
 226 static int i40e_dev_start(struct rte_eth_dev *dev);
 227 static void i40e_dev_stop(struct rte_eth_dev *dev);
 228 static void i40e_dev_close(struct rte_eth_dev *dev);
 229 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 230 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 231 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 232 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 233 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 234 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 235 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 236 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 237                                struct rte_eth_stats *stats);
 238 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 239                                struct rte_eth_xstat *xstats, unsigned n);
 240 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 241                                      struct rte_eth_xstat_name *xstats_names,
 242                                      unsigned limit);
 243 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 245                                 char *fw_version, size_t fw_size);
 246 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 247                              struct rte_eth_dev_info *dev_info);
 248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 249                                 uint16_t vlan_id,
 250                                 int on);
 251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 252                               enum rte_vlan_type vlan_type,
 253                               uint16_t tpid);
 254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                                       uint16_t queue,
 257                                       int on);
 258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 264                               struct rte_eth_fc_conf *fc_conf);
 265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 266                                        struct rte_eth_pfc_conf *pfc_conf);
 267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 268                             struct rte_ether_addr *mac_addr,
 269                             uint32_t index,
 270                             uint32_t pool);
 271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 273                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                     uint16_t reta_size);
 275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 276                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 277                                    uint16_t reta_size);
 278
 279 static int i40e_get_cap(struct i40e_hw *hw);
 280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 281 static int i40e_pf_setup(struct i40e_pf *pf);
 282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 286                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 287 static void i40e_stat_update_48(struct i40e_hw *hw,
 288                                uint32_t hireg,
 289                                uint32_t loreg,
 290                                bool offset_loaded,
 291                                uint64_t *offset,
 292                                uint64_t *stat);
 293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 294 static void i40e_dev_interrupt_handler(void *param);
 295 static void i40e_dev_alarm_handler(void *param);
 296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 297                                 uint32_t base, uint32_t num);
 298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 300                         uint32_t base);
 301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 302                         uint16_t num);
 303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 304 static int i40e_veb_release(struct i40e_veb *veb);
 305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 306                                                 struct i40e_vsi *vsi);
 307 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 308 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 309                                              struct i40e_macvlan_filter *mv_f,
 310                                              int num,
 311                                              uint16_t vlan);
 312 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 313 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 314                                     struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 316                                       struct rte_eth_rss_conf *rss_conf);
 317 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 320                                         struct rte_eth_udp_tunnel *udp_tunnel);
 321 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 322 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 326                                 enum rte_filter_type filter_type,
 327                                 enum rte_filter_op filter_op,
 328                                 void *arg);
 329 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                   struct rte_eth_dcb_info *dcb_info);
 331 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 332 static void i40e_configure_registers(struct i40e_hw *hw);
 333 static void i40e_hw_init(struct rte_eth_dev *dev);
 334 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 335 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 336                                                      uint16_t seid,
 337                                                      uint16_t rule_type,
 338                                                      uint16_t *entries,
 339                                                      uint16_t count,
 340                                                      uint16_t rule_id);
 341 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 342                         struct rte_eth_mirror_conf *mirror_conf,
 343                         uint8_t sw_id, uint8_t on);
 344 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 345
 346 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 347 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 348 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp,
 350                                            uint32_t flags);
 351 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 352                                            struct timespec *timestamp);
 353 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 354
 355 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 356
 357 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 358                                    struct timespec *timestamp);
 359 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 360                                     const struct timespec *timestamp);
 361
 362 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 363                                          uint16_t queue_id);
 364 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 365                                           uint16_t queue_id);
 366
 367 static int i40e_get_regs(struct rte_eth_dev *dev,
 368                          struct rte_dev_reg_info *regs);
 369
 370 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 371
 372 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 373                            struct rte_dev_eeprom_info *eeprom);
 374
 375 static int i40e_get_module_info(struct rte_eth_dev *dev,
 376                                 struct rte_eth_dev_module_info *modinfo);
 377 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 378                                   struct rte_dev_eeprom_info *info);
 379
 380 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 381                                       struct rte_ether_addr *mac_addr);
 382
 383 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 384
 385 static int i40e_ethertype_filter_convert(
 386         const struct rte_eth_ethertype_filter *input,
 387         struct i40e_ethertype_filter *filter);
 388 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 389                                    struct i40e_ethertype_filter *filter);
 390
 391 static int i40e_tunnel_filter_convert(
 392         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 393         struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 395                                 struct i40e_tunnel_filter *tunnel_filter);
 396 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 397
 398 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 399 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 400 static void i40e_filter_restore(struct i40e_pf *pf);
 401 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 402 static int i40e_pf_config_rss(struct i40e_pf *pf);
 403
 404 static const char *const valid_keys[] = {
 405         ETH_I40E_FLOATING_VEB_ARG,
 406         ETH_I40E_FLOATING_VEB_LIST_ARG,
 407         ETH_I40E_SUPPORT_MULTI_DRIVER,
 408         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 409         ETH_I40E_USE_LATEST_VEC,
 410         ETH_I40E_VF_MSG_CFG,
 411         NULL};
 412
 413 static const struct rte_pci_id pci_id_i40e_map[] = {
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 440         { .vendor_id = 0, /* sentinel */ },
 441 };
 442
 443 static const struct eth_dev_ops i40e_eth_dev_ops = {
 444         .dev_configure                = i40e_dev_configure,
 445         .dev_start                    = i40e_dev_start,
 446         .dev_stop                     = i40e_dev_stop,
 447         .dev_close                    = i40e_dev_close,
 448         .dev_reset                    = i40e_dev_reset,
 449         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 450         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 451         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 452         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 453         .dev_set_link_up              = i40e_dev_set_link_up,
 454         .dev_set_link_down            = i40e_dev_set_link_down,
 455         .link_update                  = i40e_dev_link_update,
 456         .stats_get                    = i40e_dev_stats_get,
 457         .xstats_get                   = i40e_dev_xstats_get,
 458         .xstats_get_names             = i40e_dev_xstats_get_names,
 459         .stats_reset                  = i40e_dev_stats_reset,
 460         .xstats_reset                 = i40e_dev_stats_reset,
 461         .fw_version_get               = i40e_fw_version_get,
 462         .dev_infos_get                = i40e_dev_info_get,
 463         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 464         .vlan_filter_set              = i40e_vlan_filter_set,
 465         .vlan_tpid_set                = i40e_vlan_tpid_set,
 466         .vlan_offload_set             = i40e_vlan_offload_set,
 467         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 468         .vlan_pvid_set                = i40e_vlan_pvid_set,
 469         .rx_queue_start               = i40e_dev_rx_queue_start,
 470         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 471         .tx_queue_start               = i40e_dev_tx_queue_start,
 472         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 473         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 474         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 475         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 476         .rx_queue_release             = i40e_dev_rx_queue_release,
 477         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 478         .tx_queue_release             = i40e_dev_tx_queue_release,
 479         .dev_led_on                   = i40e_dev_led_on,
 480         .dev_led_off                  = i40e_dev_led_off,
 481         .flow_ctrl_get                = i40e_flow_ctrl_get,
 482         .flow_ctrl_set                = i40e_flow_ctrl_set,
 483         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 484         .mac_addr_add                 = i40e_macaddr_add,
 485         .mac_addr_remove              = i40e_macaddr_remove,
 486         .reta_update                  = i40e_dev_rss_reta_update,
 487         .reta_query                   = i40e_dev_rss_reta_query,
 488         .rss_hash_update              = i40e_dev_rss_hash_update,
 489         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 490         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 491         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 492         .filter_ctrl                  = i40e_dev_filter_ctrl,
 493         .rxq_info_get                 = i40e_rxq_info_get,
 494         .txq_info_get                 = i40e_txq_info_get,
 495         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 496         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 497         .mirror_rule_set              = i40e_mirror_rule_set,
 498         .mirror_rule_reset            = i40e_mirror_rule_reset,
 499         .timesync_enable              = i40e_timesync_enable,
 500         .timesync_disable             = i40e_timesync_disable,
 501         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 502         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 503         .get_dcb_info                 = i40e_dev_get_dcb_info,
 504         .timesync_adjust_time         = i40e_timesync_adjust_time,
 505         .timesync_read_time           = i40e_timesync_read_time,
 506         .timesync_write_time          = i40e_timesync_write_time,
 507         .get_reg                      = i40e_get_regs,
 508         .get_eeprom_length            = i40e_get_eeprom_length,
 509         .get_eeprom                   = i40e_get_eeprom,
 510         .get_module_info              = i40e_get_module_info,
 511         .get_module_eeprom            = i40e_get_module_eeprom,
 512         .mac_addr_set                 = i40e_set_default_mac_addr,
 513         .mtu_set                      = i40e_dev_mtu_set,
 514         .tm_ops_get                   = i40e_tm_ops_get,
 515         .tx_done_cleanup              = i40e_tx_done_cleanup,
 516 };
 517
 518 /* store statistics names and its offset in stats structure */
 519 struct rte_i40e_xstats_name_off {
 520         char name[RTE_ETH_XSTATS_NAME_SIZE];
 521         unsigned offset;
 522 };
 523
 524 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 525         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 526         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 527         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 528         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 529         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 530                 rx_unknown_protocol)},
 531         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 532         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 533         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 534         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 535 };
 536
 537 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 538                 sizeof(rte_i40e_stats_strings[0]))
 539
 540 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 541         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 542                 tx_dropped_link_down)},
 543         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 544         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 545                 illegal_bytes)},
 546         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 547         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 548                 mac_local_faults)},
 549         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 550                 mac_remote_faults)},
 551         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_length_errors)},
 553         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 554         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 555         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 556         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 557         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 558         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 559                 rx_size_127)},
 560         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_255)},
 562         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_511)},
 564         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_1023)},
 566         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_1522)},
 568         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_big)},
 570         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 571                 rx_undersize)},
 572         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_oversize)},
 574         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 575                 mac_short_packet_dropped)},
 576         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 577                 rx_fragments)},
 578         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 579         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 580         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 581                 tx_size_127)},
 582         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_255)},
 584         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_511)},
 586         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_1023)},
 588         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_1522)},
 590         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_big)},
 592         {"rx_flow_director_atr_match_packets",
 593                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 594         {"rx_flow_director_sb_match_packets",
 595                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 596         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 597                 tx_lpi_status)},
 598         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 599                 rx_lpi_status)},
 600         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 601                 tx_lpi_count)},
 602         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 603                 rx_lpi_count)},
 604 };
 605
 606 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 607                 sizeof(rte_i40e_hw_port_strings[0]))
 608
 609 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 610         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 611                 priority_xon_rx)},
 612         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 613                 priority_xoff_rx)},
 614 };
 615
 616 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 617                 sizeof(rte_i40e_rxq_prio_strings[0]))
 618
 619 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 620         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xon_tx)},
 622         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xoff_tx)},
 624         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xon_2_xoff)},
 626 };
 627
 628 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 629                 sizeof(rte_i40e_txq_prio_strings[0]))
 630
 631 static int
 632 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 633         struct rte_pci_device *pci_dev)
 634 {
 635         char name[RTE_ETH_NAME_MAX_LEN];
 636         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 637         int i, retval;
 638
 639         if (pci_dev->device.devargs) {
 640                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 641                                 &eth_da);
 642                 if (retval)
 643                         return retval;
 644         }
 645
 646         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 647                 sizeof(struct i40e_adapter),
 648                 eth_dev_pci_specific_init, pci_dev,
 649                 eth_i40e_dev_init, NULL);
 650
 651         if (retval || eth_da.nb_representor_ports < 1)
 652                 return retval;
 653
 654         /* probe VF representor ports */
 655         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 656                 pci_dev->device.name);
 657
 658         if (pf_ethdev == NULL)
 659                 return -ENODEV;
 660
 661         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 662                 struct i40e_vf_representor representor = {
 663                         .vf_id = eth_da.representor_ports[i],
 664                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 665                                 pf_ethdev->data->dev_private)->switch_domain_id,
 666                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 667                                 pf_ethdev->data->dev_private)
 668                 };
 669
 670                 /* representor port net_bdf_port */
 671                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 672                         pci_dev->device.name, eth_da.representor_ports[i]);
 673
 674                 retval = rte_eth_dev_create(&pci_dev->device, name,
 675                         sizeof(struct i40e_vf_representor), NULL, NULL,
 676                         i40e_vf_representor_init, &representor);
 677
 678                 if (retval)
 679                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 680                                 "representor %s.", name);
 681         }
 682
 683         return 0;
 684 }
 685
 686 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 687 {
 688         struct rte_eth_dev *ethdev;
 689
 690         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 691         if (!ethdev)
 692                 return 0;
 693
 694         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 695                 return rte_eth_dev_pci_generic_remove(pci_dev,
 696                                         i40e_vf_representor_uninit);
 697         else
 698                 return rte_eth_dev_pci_generic_remove(pci_dev,
 699                                                 eth_i40e_dev_uninit);
 700 }
 701
 702 static struct rte_pci_driver rte_i40e_pmd = {
 703         .id_table = pci_id_i40e_map,
 704         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 705         .probe = eth_i40e_pci_probe,
 706         .remove = eth_i40e_pci_remove,
 707 };
 708
 709 static inline void
 710 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 711                          uint32_t reg_val)
 712 {
 713         uint32_t ori_reg_val;
 714         struct rte_eth_dev *dev;
 715
 716         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 717         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 718         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 719         if (ori_reg_val != reg_val)
 720                 PMD_DRV_LOG(WARNING,
 721                             "i40e device %s changed global register [0x%08x]."
 722                             " original: 0x%08x, new: 0x%08x",
 723                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 724 }
 725
 726 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 727 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 728 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 729
 730 #ifndef I40E_GLQF_ORT
 731 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 732 #endif
 733 #ifndef I40E_GLQF_PIT
 734 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 735 #endif
 736 #ifndef I40E_GLQF_L3_MAP
 737 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 738 #endif
 739
 740 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 741 {
 742         /*
 743          * Initialize registers for parsing packet type of QinQ
 744          * This should be removed from code once proper
 745          * configuration API is added to avoid configuration conflicts
 746          * between ports of the same device.
 747          */
 748         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 749         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 750 }
 751
 752 static inline void i40e_config_automask(struct i40e_pf *pf)
 753 {
 754         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 755         uint32_t val;
 756
 757         /* INTENA flag is not auto-cleared for interrupt */
 758         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 759         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 760                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 761
 762         /* If support multi-driver, PF will use INT0. */
 763         if (!pf->support_multi_driver)
 764                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 765
 766         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 767 }
 768
 769 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 770
 771 /*
 772  * Add a ethertype filter to drop all flow control frames transmitted
 773  * from VSIs.
 774 */
 775 static void
 776 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 777 {
 778         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 779         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 780                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 781                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 782         int ret;
 783
 784         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 785                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 786                                 pf->main_vsi_seid, 0,
 787                                 TRUE, NULL, NULL);
 788         if (ret)
 789                 PMD_INIT_LOG(ERR,
 790                         "Failed to add filter to drop flow control frames from VSIs.");
 791 }
 792
 793 static int
 794 floating_veb_list_handler(__rte_unused const char *key,
 795                           const char *floating_veb_value,
 796                           void *opaque)
 797 {
 798         int idx = 0;
 799         unsigned int count = 0;
 800         char *end = NULL;
 801         int min, max;
 802         bool *vf_floating_veb = opaque;
 803
 804         while (isblank(*floating_veb_value))
 805                 floating_veb_value++;
 806
 807         /* Reset floating VEB configuration for VFs */
 808         for (idx = 0; idx < I40E_MAX_VF; idx++)
 809                 vf_floating_veb[idx] = false;
 810
 811         min = I40E_MAX_VF;
 812         do {
 813                 while (isblank(*floating_veb_value))
 814                         floating_veb_value++;
 815                 if (*floating_veb_value == '\0')
 816                         return -1;
 817                 errno = 0;
 818                 idx = strtoul(floating_veb_value, &end, 10);
 819                 if (errno || end == NULL)
 820                         return -1;
 821                 while (isblank(*end))
 822                         end++;
 823                 if (*end == '-') {
 824                         min = idx;
 825                 } else if ((*end == ';') || (*end == '\0')) {
 826                         max = idx;
 827                         if (min == I40E_MAX_VF)
 828                                 min = idx;
 829                         if (max >= I40E_MAX_VF)
 830                                 max = I40E_MAX_VF - 1;
 831                         for (idx = min; idx <= max; idx++) {
 832                                 vf_floating_veb[idx] = true;
 833                                 count++;
 834                         }
 835                         min = I40E_MAX_VF;
 836                 } else {
 837                         return -1;
 838                 }
 839                 floating_veb_value = end + 1;
 840         } while (*end != '\0');
 841
 842         if (count == 0)
 843                 return -1;
 844
 845         return 0;
 846 }
 847
 848 static void
 849 config_vf_floating_veb(struct rte_devargs *devargs,
 850                        uint16_t floating_veb,
 851                        bool *vf_floating_veb)
 852 {
 853         struct rte_kvargs *kvlist;
 854         int i;
 855         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 856
 857         if (!floating_veb)
 858                 return;
 859         /* All the VFs attach to the floating VEB by default
 860          * when the floating VEB is enabled.
 861          */
 862         for (i = 0; i < I40E_MAX_VF; i++)
 863                 vf_floating_veb[i] = true;
 864
 865         if (devargs == NULL)
 866                 return;
 867
 868         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 869         if (kvlist == NULL)
 870                 return;
 871
 872         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 873                 rte_kvargs_free(kvlist);
 874                 return;
 875         }
 876         /* When the floating_veb_list parameter exists, all the VFs
 877          * will attach to the legacy VEB firstly, then configure VFs
 878          * to the floating VEB according to the floating_veb_list.
 879          */
 880         if (rte_kvargs_process(kvlist, floating_veb_list,
 881                                floating_veb_list_handler,
 882                                vf_floating_veb) < 0) {
 883                 rte_kvargs_free(kvlist);
 884                 return;
 885         }
 886         rte_kvargs_free(kvlist);
 887 }
 888
 889 static int
 890 i40e_check_floating_handler(__rte_unused const char *key,
 891                             const char *value,
 892                             __rte_unused void *opaque)
 893 {
 894         if (strcmp(value, "1"))
 895                 return -1;
 896
 897         return 0;
 898 }
 899
 900 static int
 901 is_floating_veb_supported(struct rte_devargs *devargs)
 902 {
 903         struct rte_kvargs *kvlist;
 904         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 905
 906         if (devargs == NULL)
 907                 return 0;
 908
 909         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 910         if (kvlist == NULL)
 911                 return 0;
 912
 913         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 914                 rte_kvargs_free(kvlist);
 915                 return 0;
 916         }
 917         /* Floating VEB is enabled when there's key-value:
 918          * enable_floating_veb=1
 919          */
 920         if (rte_kvargs_process(kvlist, floating_veb_key,
 921                                i40e_check_floating_handler, NULL) < 0) {
 922                 rte_kvargs_free(kvlist);
 923                 return 0;
 924         }
 925         rte_kvargs_free(kvlist);
 926
 927         return 1;
 928 }
 929
 930 static void
 931 config_floating_veb(struct rte_eth_dev *dev)
 932 {
 933         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936
 937         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 938
 939         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 940                 pf->floating_veb =
 941                         is_floating_veb_supported(pci_dev->device.devargs);
 942                 config_vf_floating_veb(pci_dev->device.devargs,
 943                                        pf->floating_veb,
 944                                        pf->floating_veb_list);
 945         } else {
 946                 pf->floating_veb = false;
 947         }
 948 }
 949
 950 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 951 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 952
 953 static int
 954 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 955 {
 956         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 957         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 958         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 959         int ret;
 960
 961         struct rte_hash_parameters ethertype_hash_params = {
 962                 .name = ethertype_hash_name,
 963                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 964                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 965                 .hash_func = rte_hash_crc,
 966                 .hash_func_init_val = 0,
 967                 .socket_id = rte_socket_id(),
 968         };
 969
 970         /* Initialize ethertype filter rule list and hash */
 971         TAILQ_INIT(&ethertype_rule->ethertype_list);
 972         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 973                  "ethertype_%s", dev->device->name);
 974         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 975         if (!ethertype_rule->hash_table) {
 976                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 977                 return -EINVAL;
 978         }
 979         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 980                                        sizeof(struct i40e_ethertype_filter *) *
 981                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 982                                        0);
 983         if (!ethertype_rule->hash_map) {
 984                 PMD_INIT_LOG(ERR,
 985                              "Failed to allocate memory for ethertype hash map!");
 986                 ret = -ENOMEM;
 987                 goto err_ethertype_hash_map_alloc;
 988         }
 989
 990         return 0;
 991
 992 err_ethertype_hash_map_alloc:
 993         rte_hash_free(ethertype_rule->hash_table);
 994
 995         return ret;
 996 }
 997
 998 static int
 999 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1000 {
1001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1002         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1003         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1004         int ret;
1005
1006         struct rte_hash_parameters tunnel_hash_params = {
1007                 .name = tunnel_hash_name,
1008                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1009                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1010                 .hash_func = rte_hash_crc,
1011                 .hash_func_init_val = 0,
1012                 .socket_id = rte_socket_id(),
1013         };
1014
1015         /* Initialize tunnel filter rule list and hash */
1016         TAILQ_INIT(&tunnel_rule->tunnel_list);
1017         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1018                  "tunnel_%s", dev->device->name);
1019         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1020         if (!tunnel_rule->hash_table) {
1021                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1022                 return -EINVAL;
1023         }
1024         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1025                                     sizeof(struct i40e_tunnel_filter *) *
1026                                     I40E_MAX_TUNNEL_FILTER_NUM,
1027                                     0);
1028         if (!tunnel_rule->hash_map) {
1029                 PMD_INIT_LOG(ERR,
1030                              "Failed to allocate memory for tunnel hash map!");
1031                 ret = -ENOMEM;
1032                 goto err_tunnel_hash_map_alloc;
1033         }
1034
1035         return 0;
1036
1037 err_tunnel_hash_map_alloc:
1038         rte_hash_free(tunnel_rule->hash_table);
1039
1040         return ret;
1041 }
1042
1043 static int
1044 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1045 {
1046         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1047         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1048         struct i40e_fdir_info *fdir_info = &pf->fdir;
1049         char fdir_hash_name[RTE_HASH_NAMESIZE];
1050         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1051         uint32_t best = hw->func_caps.fd_filters_best_effort;
1052         struct rte_bitmap *bmp = NULL;
1053         uint32_t bmp_size;
1054         void *mem = NULL;
1055         uint32_t i = 0;
1056         int ret;
1057
1058         struct rte_hash_parameters fdir_hash_params = {
1059                 .name = fdir_hash_name,
1060                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1061                 .key_len = sizeof(struct i40e_fdir_input),
1062                 .hash_func = rte_hash_crc,
1063                 .hash_func_init_val = 0,
1064                 .socket_id = rte_socket_id(),
1065         };
1066
1067         /* Initialize flow director filter rule list and hash */
1068         TAILQ_INIT(&fdir_info->fdir_list);
1069         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1070                  "fdir_%s", dev->device->name);
1071         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1072         if (!fdir_info->hash_table) {
1073                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1074                 return -EINVAL;
1075         }
1076
1077         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1078                                           sizeof(struct i40e_fdir_filter *) *
1079                                           I40E_MAX_FDIR_FILTER_NUM,
1080                                           0);
1081         if (!fdir_info->hash_map) {
1082                 PMD_INIT_LOG(ERR,
1083                              "Failed to allocate memory for fdir hash map!");
1084                 ret = -ENOMEM;
1085                 goto err_fdir_hash_map_alloc;
1086         }
1087
1088         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1089                         sizeof(struct i40e_fdir_filter) *
1090                         I40E_MAX_FDIR_FILTER_NUM,
1091                         0);
1092
1093         if (!fdir_info->fdir_filter_array) {
1094                 PMD_INIT_LOG(ERR,
1095                              "Failed to allocate memory for fdir filter array!");
1096                 ret = -ENOMEM;
1097                 goto err_fdir_filter_array_alloc;
1098         }
1099
1100         fdir_info->fdir_space_size = alloc + best;
1101         fdir_info->fdir_actual_cnt = 0;
1102         fdir_info->fdir_guarantee_total_space = alloc;
1103         fdir_info->fdir_guarantee_free_space =
1104                 fdir_info->fdir_guarantee_total_space;
1105
1106         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1107
1108         fdir_info->fdir_flow_pool.pool =
1109                         rte_zmalloc("i40e_fdir_entry",
1110                                 sizeof(struct i40e_fdir_entry) *
1111                                 fdir_info->fdir_space_size,
1112                                 0);
1113
1114         if (!fdir_info->fdir_flow_pool.pool) {
1115                 PMD_INIT_LOG(ERR,
1116                              "Failed to allocate memory for bitmap flow!");
1117                 ret = -ENOMEM;
1118                 goto err_fdir_bitmap_flow_alloc;
1119         }
1120
1121         for (i = 0; i < fdir_info->fdir_space_size; i++)
1122                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1123
1124         bmp_size =
1125                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1126         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1127         if (mem == NULL) {
1128                 PMD_INIT_LOG(ERR,
1129                              "Failed to allocate memory for fdir bitmap!");
1130                 ret = -ENOMEM;
1131                 goto err_fdir_mem_alloc;
1132         }
1133         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1134         if (bmp == NULL) {
1135                 PMD_INIT_LOG(ERR,
1136                              "Failed to initialization fdir bitmap!");
1137                 ret = -ENOMEM;
1138                 goto err_fdir_bmp_alloc;
1139         }
1140         for (i = 0; i < fdir_info->fdir_space_size; i++)
1141                 rte_bitmap_set(bmp, i);
1142
1143         fdir_info->fdir_flow_pool.bitmap = bmp;
1144
1145         return 0;
1146
1147 err_fdir_bmp_alloc:
1148         rte_free(mem);
1149 err_fdir_mem_alloc:
1150         rte_free(fdir_info->fdir_flow_pool.pool);
1151 err_fdir_bitmap_flow_alloc:
1152         rte_free(fdir_info->fdir_filter_array);
1153 err_fdir_filter_array_alloc:
1154         rte_free(fdir_info->hash_map);
1155 err_fdir_hash_map_alloc:
1156         rte_hash_free(fdir_info->hash_table);
1157
1158         return ret;
1159 }
1160
1161 static void
1162 i40e_init_customized_info(struct i40e_pf *pf)
1163 {
1164         int i;
1165
1166         /* Initialize customized pctype */
1167         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1168                 pf->customized_pctype[i].index = i;
1169                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1170                 pf->customized_pctype[i].valid = false;
1171         }
1172
1173         pf->gtp_support = false;
1174         pf->esp_support = false;
1175 }
1176
1177 static void
1178 i40e_init_filter_invalidation(struct i40e_pf *pf)
1179 {
1180         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1181         struct i40e_fdir_info *fdir_info = &pf->fdir;
1182         uint32_t glqf_ctl_reg = 0;
1183
1184         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1185         if (!pf->support_multi_driver) {
1186                 fdir_info->fdir_invalprio = 1;
1187                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1188                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1189                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1190         } else {
1191                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1192                         fdir_info->fdir_invalprio = 1;
1193                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1194                 } else {
1195                         fdir_info->fdir_invalprio = 0;
1196                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1197                 }
1198         }
1199 }
1200
1201 void
1202 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1203 {
1204         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1206         struct i40e_queue_regions *info = &pf->queue_region;
1207         uint16_t i;
1208
1209         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1210                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1211
1212         memset(info, 0, sizeof(struct i40e_queue_regions));
1213 }
1214
1215 static int
1216 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1217                                const char *value,
1218                                void *opaque)
1219 {
1220         struct i40e_pf *pf;
1221         unsigned long support_multi_driver;
1222         char *end;
1223
1224         pf = (struct i40e_pf *)opaque;
1225
1226         errno = 0;
1227         support_multi_driver = strtoul(value, &end, 10);
1228         if (errno != 0 || end == value || *end != 0) {
1229                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1230                 return -(EINVAL);
1231         }
1232
1233         if (support_multi_driver == 1 || support_multi_driver == 0)
1234                 pf->support_multi_driver = (bool)support_multi_driver;
1235         else
1236                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1237                             "enable global configuration by default."
1238                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1239         return 0;
1240 }
1241
1242 static int
1243 i40e_support_multi_driver(struct rte_eth_dev *dev)
1244 {
1245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1246         struct rte_kvargs *kvlist;
1247         int kvargs_count;
1248
1249         /* Enable global configuration by default */
1250         pf->support_multi_driver = false;
1251
1252         if (!dev->device->devargs)
1253                 return 0;
1254
1255         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1256         if (!kvlist)
1257                 return -EINVAL;
1258
1259         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1260         if (!kvargs_count) {
1261                 rte_kvargs_free(kvlist);
1262                 return 0;
1263         }
1264
1265         if (kvargs_count > 1)
1266                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1267                             "the first invalid or last valid one is used !",
1268                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1269
1270         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1271                                i40e_parse_multi_drv_handler, pf) < 0) {
1272                 rte_kvargs_free(kvlist);
1273                 return -EINVAL;
1274         }
1275
1276         rte_kvargs_free(kvlist);
1277         return 0;
1278 }
1279
1280 static int
1281 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1282                                     uint32_t reg_addr, uint64_t reg_val,
1283                                     struct i40e_asq_cmd_details *cmd_details)
1284 {
1285         uint64_t ori_reg_val;
1286         struct rte_eth_dev *dev;
1287         int ret;
1288
1289         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1290         if (ret != I40E_SUCCESS) {
1291                 PMD_DRV_LOG(ERR,
1292                             "Fail to debug read from 0x%08x",
1293                             reg_addr);
1294                 return -EIO;
1295         }
1296         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1297
1298         if (ori_reg_val != reg_val)
1299                 PMD_DRV_LOG(WARNING,
1300                             "i40e device %s changed global register [0x%08x]."
1301                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1302                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1303
1304         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1305 }
1306
1307 static int
1308 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1309                                 const char *value,
1310                                 void *opaque)
1311 {
1312         struct i40e_adapter *ad = opaque;
1313         int use_latest_vec;
1314
1315         use_latest_vec = atoi(value);
1316
1317         if (use_latest_vec != 0 && use_latest_vec != 1)
1318                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1319
1320         ad->use_latest_vec = (uint8_t)use_latest_vec;
1321
1322         return 0;
1323 }
1324
1325 static int
1326 i40e_use_latest_vec(struct rte_eth_dev *dev)
1327 {
1328         struct i40e_adapter *ad =
1329                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1330         struct rte_kvargs *kvlist;
1331         int kvargs_count;
1332
1333         ad->use_latest_vec = false;
1334
1335         if (!dev->device->devargs)
1336                 return 0;
1337
1338         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1339         if (!kvlist)
1340                 return -EINVAL;
1341
1342         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1343         if (!kvargs_count) {
1344                 rte_kvargs_free(kvlist);
1345                 return 0;
1346         }
1347
1348         if (kvargs_count > 1)
1349                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1350                             "the first invalid or last valid one is used !",
1351                             ETH_I40E_USE_LATEST_VEC);
1352
1353         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1354                                 i40e_parse_latest_vec_handler, ad) < 0) {
1355                 rte_kvargs_free(kvlist);
1356                 return -EINVAL;
1357         }
1358
1359         rte_kvargs_free(kvlist);
1360         return 0;
1361 }
1362
1363 static int
1364 read_vf_msg_config(__rte_unused const char *key,
1365                                const char *value,
1366                                void *opaque)
1367 {
1368         struct i40e_vf_msg_cfg *cfg = opaque;
1369
1370         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1371                         &cfg->ignore_second) != 3) {
1372                 memset(cfg, 0, sizeof(*cfg));
1373                 PMD_DRV_LOG(ERR, "format error! example: "
1374                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1375                 return -EINVAL;
1376         }
1377
1378         /*
1379          * If the message validation function been enabled, the 'period'
1380          * and 'ignore_second' must greater than 0.
1381          */
1382         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1383                 memset(cfg, 0, sizeof(*cfg));
1384                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1385                                 " number must be greater than 0!",
1386                                 ETH_I40E_VF_MSG_CFG);
1387                 return -EINVAL;
1388         }
1389
1390         return 0;
1391 }
1392
1393 static int
1394 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1395                 struct i40e_vf_msg_cfg *msg_cfg)
1396 {
1397         struct rte_kvargs *kvlist;
1398         int kvargs_count;
1399         int ret = 0;
1400
1401         memset(msg_cfg, 0, sizeof(*msg_cfg));
1402
1403         if (!dev->device->devargs)
1404                 return ret;
1405
1406         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1407         if (!kvlist)
1408                 return -EINVAL;
1409
1410         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1411         if (!kvargs_count)
1412                 goto free_end;
1413
1414         if (kvargs_count > 1) {
1415                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1416                                 ETH_I40E_VF_MSG_CFG);
1417                 ret = -EINVAL;
1418                 goto free_end;
1419         }
1420
1421         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1422                         read_vf_msg_config, msg_cfg) < 0)
1423                 ret = -EINVAL;
1424
1425 free_end:
1426         rte_kvargs_free(kvlist);
1427         return ret;
1428 }
1429
1430 #define I40E_ALARM_INTERVAL 50000 /* us */
1431
1432 static int
1433 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1434 {
1435         struct rte_pci_device *pci_dev;
1436         struct rte_intr_handle *intr_handle;
1437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1439         struct i40e_vsi *vsi;
1440         int ret;
1441         uint32_t len, val;
1442         uint8_t aq_fail = 0;
1443
1444         PMD_INIT_FUNC_TRACE();
1445
1446         dev->dev_ops = &i40e_eth_dev_ops;
1447         dev->rx_queue_count = i40e_dev_rx_queue_count;
1448         dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1449         dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1450         dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1451         dev->rx_pkt_burst = i40e_recv_pkts;
1452         dev->tx_pkt_burst = i40e_xmit_pkts;
1453         dev->tx_pkt_prepare = i40e_prep_pkts;
1454
1455         /* for secondary processes, we don't initialise any further as primary
1456          * has already done this work. Only check we don't need a different
1457          * RX function */
1458         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1459                 i40e_set_rx_function(dev);
1460                 i40e_set_tx_function(dev);
1461                 return 0;
1462         }
1463         i40e_set_default_ptype_table(dev);
1464         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1465         intr_handle = &pci_dev->intr_handle;
1466
1467         rte_eth_copy_pci_info(dev, pci_dev);
1468
1469         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1470         pf->adapter->eth_dev = dev;
1471         pf->dev_data = dev->data;
1472
1473         hw->back = I40E_PF_TO_ADAPTER(pf);
1474         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1475         if (!hw->hw_addr) {
1476                 PMD_INIT_LOG(ERR,
1477                         "Hardware is not available, as address is NULL");
1478                 return -ENODEV;
1479         }
1480
1481         hw->vendor_id = pci_dev->id.vendor_id;
1482         hw->device_id = pci_dev->id.device_id;
1483         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1484         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1485         hw->bus.device = pci_dev->addr.devid;
1486         hw->bus.func = pci_dev->addr.function;
1487         hw->adapter_stopped = 0;
1488         hw->adapter_closed = 0;
1489
1490         /* Init switch device pointer */
1491         hw->switch_dev = NULL;
1492
1493         /*
1494          * Switch Tag value should not be identical to either the First Tag
1495          * or Second Tag values. So set something other than common Ethertype
1496          * for internal switching.
1497          */
1498         hw->switch_tag = 0xffff;
1499
1500         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1501         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1502                 PMD_INIT_LOG(ERR, "\nERROR: "
1503                         "Firmware recovery mode detected. Limiting functionality.\n"
1504                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1505                         "User Guide for details on firmware recovery mode.");
1506                 return -EIO;
1507         }
1508
1509         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1510         /* Check if need to support multi-driver */
1511         i40e_support_multi_driver(dev);
1512         /* Check if users want the latest supported vec path */
1513         i40e_use_latest_vec(dev);
1514
1515         /* Make sure all is clean before doing PF reset */
1516         i40e_clear_hw(hw);
1517
1518         /* Reset here to make sure all is clean for each PF */
1519         ret = i40e_pf_reset(hw);
1520         if (ret) {
1521                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1522                 return ret;
1523         }
1524
1525         /* Initialize the shared code (base driver) */
1526         ret = i40e_init_shared_code(hw);
1527         if (ret) {
1528                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1529                 return ret;
1530         }
1531
1532         /* Initialize the parameters for adminq */
1533         i40e_init_adminq_parameter(hw);
1534         ret = i40e_init_adminq(hw);
1535         if (ret != I40E_SUCCESS) {
1536                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1537                 return -EIO;
1538         }
1539         /* Firmware of SFP x722 does not support adminq option */
1540         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1541                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1542
1543         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1544                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1545                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1546                      ((hw->nvm.version >> 12) & 0xf),
1547                      ((hw->nvm.version >> 4) & 0xff),
1548                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1549
1550         /* Initialize the hardware */
1551         i40e_hw_init(dev);
1552
1553         i40e_config_automask(pf);
1554
1555         i40e_set_default_pctype_table(dev);
1556
1557         /*
1558          * To work around the NVM issue, initialize registers
1559          * for packet type of QinQ by software.
1560          * It should be removed once issues are fixed in NVM.
1561          */
1562         if (!pf->support_multi_driver)
1563                 i40e_GLQF_reg_init(hw);
1564
1565         /* Initialize the input set for filters (hash and fd) to default value */
1566         i40e_filter_input_set_init(pf);
1567
1568         /* initialise the L3_MAP register */
1569         if (!pf->support_multi_driver) {
1570                 ret = i40e_aq_debug_write_global_register(hw,
1571                                                    I40E_GLQF_L3_MAP(40),
1572                                                    0x00000028,  NULL);
1573                 if (ret)
1574                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1575                                      ret);
1576                 PMD_INIT_LOG(DEBUG,
1577                              "Global register 0x%08x is changed with 0x28",
1578                              I40E_GLQF_L3_MAP(40));
1579         }
1580
1581         /* Need the special FW version to support floating VEB */
1582         config_floating_veb(dev);
1583         /* Clear PXE mode */
1584         i40e_clear_pxe_mode(hw);
1585         i40e_dev_sync_phy_type(hw);
1586
1587         /*
1588          * On X710, performance number is far from the expectation on recent
1589          * firmware versions. The fix for this issue may not be integrated in
1590          * the following firmware version. So the workaround in software driver
1591          * is needed. It needs to modify the initial values of 3 internal only
1592          * registers. Note that the workaround can be removed when it is fixed
1593          * in firmware in the future.
1594          */
1595         i40e_configure_registers(hw);
1596
1597         /* Get hw capabilities */
1598         ret = i40e_get_cap(hw);
1599         if (ret != I40E_SUCCESS) {
1600                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1601                 goto err_get_capabilities;
1602         }
1603
1604         /* Initialize parameters for PF */
1605         ret = i40e_pf_parameter_init(dev);
1606         if (ret != 0) {
1607                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1608                 goto err_parameter_init;
1609         }
1610
1611         /* Initialize the queue management */
1612         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1613         if (ret < 0) {
1614                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1615                 goto err_qp_pool_init;
1616         }
1617         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1618                                 hw->func_caps.num_msix_vectors - 1);
1619         if (ret < 0) {
1620                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1621                 goto err_msix_pool_init;
1622         }
1623
1624         /* Initialize lan hmc */
1625         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1626                                 hw->func_caps.num_rx_qp, 0, 0);
1627         if (ret != I40E_SUCCESS) {
1628                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1629                 goto err_init_lan_hmc;
1630         }
1631
1632         /* Configure lan hmc */
1633         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1634         if (ret != I40E_SUCCESS) {
1635                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1636                 goto err_configure_lan_hmc;
1637         }
1638
1639         /* Get and check the mac address */
1640         i40e_get_mac_addr(hw, hw->mac.addr);
1641         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1642                 PMD_INIT_LOG(ERR, "mac address is not valid");
1643                 ret = -EIO;
1644                 goto err_get_mac_addr;
1645         }
1646         /* Copy the permanent MAC address */
1647         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1648                         (struct rte_ether_addr *)hw->mac.perm_addr);
1649
1650         /* Disable flow control */
1651         hw->fc.requested_mode = I40E_FC_NONE;
1652         i40e_set_fc(hw, &aq_fail, TRUE);
1653
1654         /* Set the global registers with default ether type value */
1655         if (!pf->support_multi_driver) {
1656                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1657                                          RTE_ETHER_TYPE_VLAN);
1658                 if (ret != I40E_SUCCESS) {
1659                         PMD_INIT_LOG(ERR,
1660                                      "Failed to set the default outer "
1661                                      "VLAN ether type");
1662                         goto err_setup_pf_switch;
1663                 }
1664         }
1665
1666         /* PF setup, which includes VSI setup */
1667         ret = i40e_pf_setup(pf);
1668         if (ret) {
1669                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1670                 goto err_setup_pf_switch;
1671         }
1672
1673         vsi = pf->main_vsi;
1674
1675         /* Disable double vlan by default */
1676         i40e_vsi_config_double_vlan(vsi, FALSE);
1677
1678         /* Disable S-TAG identification when floating_veb is disabled */
1679         if (!pf->floating_veb) {
1680                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1681                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1682                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1683                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1684                 }
1685         }
1686
1687         if (!vsi->max_macaddrs)
1688                 len = RTE_ETHER_ADDR_LEN;
1689         else
1690                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1691
1692         /* Should be after VSI initialized */
1693         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1694         if (!dev->data->mac_addrs) {
1695                 PMD_INIT_LOG(ERR,
1696                         "Failed to allocated memory for storing mac address");
1697                 goto err_mac_alloc;
1698         }
1699         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1700                                         &dev->data->mac_addrs[0]);
1701
1702         /* Pass the information to the rte_eth_dev_close() that it should also
1703          * release the private port resources.
1704          */
1705         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1706
1707         /* Init dcb to sw mode by default */
1708         ret = i40e_dcb_init_configure(dev, TRUE);
1709         if (ret != I40E_SUCCESS) {
1710                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1711                 pf->flags &= ~I40E_FLAG_DCB;
1712         }
1713         /* Update HW struct after DCB configuration */
1714         i40e_get_cap(hw);
1715
1716         /* initialize pf host driver to setup SRIOV resource if applicable */
1717         i40e_pf_host_init(dev);
1718
1719         /* register callback func to eal lib */
1720         rte_intr_callback_register(intr_handle,
1721                                    i40e_dev_interrupt_handler, dev);
1722
1723         /* configure and enable device interrupt */
1724         i40e_pf_config_irq0(hw, TRUE);
1725         i40e_pf_enable_irq0(hw);
1726
1727         /* enable uio intr after callback register */
1728         rte_intr_enable(intr_handle);
1729
1730         /* By default disable flexible payload in global configuration */
1731         if (!pf->support_multi_driver)
1732                 i40e_flex_payload_reg_set_default(hw);
1733
1734         /*
1735          * Add an ethertype filter to drop all flow control frames transmitted
1736          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1737          * frames to wire.
1738          */
1739         i40e_add_tx_flow_control_drop_filter(pf);
1740
1741         /* Set the max frame size to 0x2600 by default,
1742          * in case other drivers changed the default value.
1743          */
1744         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1745
1746         /* initialize mirror rule list */
1747         TAILQ_INIT(&pf->mirror_list);
1748
1749         /* initialize RSS rule list */
1750         TAILQ_INIT(&pf->rss_config_list);
1751
1752         /* initialize Traffic Manager configuration */
1753         i40e_tm_conf_init(dev);
1754
1755         /* Initialize customized information */
1756         i40e_init_customized_info(pf);
1757
1758         /* Initialize the filter invalidation configuration */
1759         i40e_init_filter_invalidation(pf);
1760
1761         ret = i40e_init_ethtype_filter_list(dev);
1762         if (ret < 0)
1763                 goto err_init_ethtype_filter_list;
1764         ret = i40e_init_tunnel_filter_list(dev);
1765         if (ret < 0)
1766                 goto err_init_tunnel_filter_list;
1767         ret = i40e_init_fdir_filter_list(dev);
1768         if (ret < 0)
1769                 goto err_init_fdir_filter_list;
1770
1771         /* initialize queue region configuration */
1772         i40e_init_queue_region_conf(dev);
1773
1774         /* initialize RSS configuration from rte_flow */
1775         memset(&pf->rss_info, 0,
1776                 sizeof(struct i40e_rte_flow_rss_conf));
1777
1778         /* reset all stats of the device, including pf and main vsi */
1779         i40e_dev_stats_reset(dev);
1780
1781         return 0;
1782
1783 err_init_fdir_filter_list:
1784         rte_free(pf->tunnel.hash_table);
1785         rte_free(pf->tunnel.hash_map);
1786 err_init_tunnel_filter_list:
1787         rte_free(pf->ethertype.hash_table);
1788         rte_free(pf->ethertype.hash_map);
1789 err_init_ethtype_filter_list:
1790         rte_free(dev->data->mac_addrs);
1791         dev->data->mac_addrs = NULL;
1792 err_mac_alloc:
1793         i40e_vsi_release(pf->main_vsi);
1794 err_setup_pf_switch:
1795 err_get_mac_addr:
1796 err_configure_lan_hmc:
1797         (void)i40e_shutdown_lan_hmc(hw);
1798 err_init_lan_hmc:
1799         i40e_res_pool_destroy(&pf->msix_pool);
1800 err_msix_pool_init:
1801         i40e_res_pool_destroy(&pf->qp_pool);
1802 err_qp_pool_init:
1803 err_parameter_init:
1804 err_get_capabilities:
1805         (void)i40e_shutdown_adminq(hw);
1806
1807         return ret;
1808 }
1809
1810 static void
1811 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1812 {
1813         struct i40e_ethertype_filter *p_ethertype;
1814         struct i40e_ethertype_rule *ethertype_rule;
1815
1816         ethertype_rule = &pf->ethertype;
1817         /* Remove all ethertype filter rules and hash */
1818         if (ethertype_rule->hash_map)
1819                 rte_free(ethertype_rule->hash_map);
1820         if (ethertype_rule->hash_table)
1821                 rte_hash_free(ethertype_rule->hash_table);
1822
1823         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1824                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1825                              p_ethertype, rules);
1826                 rte_free(p_ethertype);
1827         }
1828 }
1829
1830 static void
1831 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1832 {
1833         struct i40e_tunnel_filter *p_tunnel;
1834         struct i40e_tunnel_rule *tunnel_rule;
1835
1836         tunnel_rule = &pf->tunnel;
1837         /* Remove all tunnel director rules and hash */
1838         if (tunnel_rule->hash_map)
1839                 rte_free(tunnel_rule->hash_map);
1840         if (tunnel_rule->hash_table)
1841                 rte_hash_free(tunnel_rule->hash_table);
1842
1843         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1844                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1845                 rte_free(p_tunnel);
1846         }
1847 }
1848
1849 static void
1850 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1851 {
1852         struct i40e_fdir_filter *p_fdir;
1853         struct i40e_fdir_info *fdir_info;
1854
1855         fdir_info = &pf->fdir;
1856
1857         /* Remove all flow director rules */
1858         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1859                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1860 }
1861
1862 static void
1863 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1864 {
1865         struct i40e_fdir_info *fdir_info;
1866
1867         fdir_info = &pf->fdir;
1868
1869         /* flow director memory cleanup */
1870         if (fdir_info->hash_map)
1871                 rte_free(fdir_info->hash_map);
1872         if (fdir_info->hash_table)
1873                 rte_hash_free(fdir_info->hash_table);
1874         if (fdir_info->fdir_flow_pool.bitmap)
1875                 rte_free(fdir_info->fdir_flow_pool.bitmap);
1876         if (fdir_info->fdir_flow_pool.pool)
1877                 rte_free(fdir_info->fdir_flow_pool.pool);
1878         if (fdir_info->fdir_filter_array)
1879                 rte_free(fdir_info->fdir_filter_array);
1880 }
1881
1882 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1883 {
1884         /*
1885          * Disable by default flexible payload
1886          * for corresponding L2/L3/L4 layers.
1887          */
1888         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1889         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1890         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1891 }
1892
1893 static int
1894 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1895 {
1896         struct i40e_hw *hw;
1897
1898         PMD_INIT_FUNC_TRACE();
1899
1900         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1901                 return 0;
1902
1903         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904
1905         if (hw->adapter_closed == 0)
1906                 i40e_dev_close(dev);
1907
1908         return 0;
1909 }
1910
1911 static int
1912 i40e_dev_configure(struct rte_eth_dev *dev)
1913 {
1914         struct i40e_adapter *ad =
1915                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1916         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1918         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1919         int i, ret;
1920
1921         ret = i40e_dev_sync_phy_type(hw);
1922         if (ret)
1923                 return ret;
1924
1925         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1926          * bulk allocation or vector Rx preconditions we will reset it.
1927          */
1928         ad->rx_bulk_alloc_allowed = true;
1929         ad->rx_vec_allowed = true;
1930         ad->tx_simple_allowed = true;
1931         ad->tx_vec_allowed = true;
1932
1933         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1934                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1935
1936         /* Only legacy filter API needs the following fdir config. So when the
1937          * legacy filter API is deprecated, the following codes should also be
1938          * removed.
1939          */
1940         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1941                 ret = i40e_fdir_setup(pf);
1942                 if (ret != I40E_SUCCESS) {
1943                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1944                         return -ENOTSUP;
1945                 }
1946                 ret = i40e_fdir_configure(dev);
1947                 if (ret < 0) {
1948                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1949                         goto err;
1950                 }
1951         } else
1952                 i40e_fdir_teardown(pf);
1953
1954         ret = i40e_dev_init_vlan(dev);
1955         if (ret < 0)
1956                 goto err;
1957
1958         /* VMDQ setup.
1959          *  General PMD driver call sequence are NIC init, configure,
1960          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1961          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1962          *  applicable. So, VMDQ setting has to be done before
1963          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1964          *  For RSS setting, it will try to calculate actual configured RX queue
1965          *  number, which will be available after rx_queue_setup(). dev_start()
1966          *  function is good to place RSS setup.
1967          */
1968         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1969                 ret = i40e_vmdq_setup(dev);
1970                 if (ret)
1971                         goto err;
1972         }
1973
1974         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1975                 ret = i40e_dcb_setup(dev);
1976                 if (ret) {
1977                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1978                         goto err_dcb;
1979                 }
1980         }
1981
1982         TAILQ_INIT(&pf->flow_list);
1983
1984         return 0;
1985
1986 err_dcb:
1987         /* need to release vmdq resource if exists */
1988         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1989                 i40e_vsi_release(pf->vmdq[i].vsi);
1990                 pf->vmdq[i].vsi = NULL;
1991         }
1992         rte_free(pf->vmdq);
1993         pf->vmdq = NULL;
1994 err:
1995         /* Need to release fdir resource if exists.
1996          * Only legacy filter API needs the following fdir config. So when the
1997          * legacy filter API is deprecated, the following code should also be
1998          * removed.
1999          */
2000         i40e_fdir_teardown(pf);
2001         return ret;
2002 }
2003
2004 void
2005 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2006 {
2007         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011         uint16_t msix_vect = vsi->msix_intr;
2012         uint16_t i;
2013
2014         for (i = 0; i < vsi->nb_qps; i++) {
2015                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2016                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2017                 rte_wmb();
2018         }
2019
2020         if (vsi->type != I40E_VSI_SRIOV) {
2021                 if (!rte_intr_allow_others(intr_handle)) {
2022                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2023                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2024                         I40E_WRITE_REG(hw,
2025                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2026                                        0);
2027                 } else {
2028                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2029                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2030                         I40E_WRITE_REG(hw,
2031                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2032                                                        msix_vect - 1), 0);
2033                 }
2034         } else {
2035                 uint32_t reg;
2036                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2037                         vsi->user_param + (msix_vect - 1);
2038
2039                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2040                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2041         }
2042         I40E_WRITE_FLUSH(hw);
2043 }
2044
2045 static void
2046 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2047                        int base_queue, int nb_queue,
2048                        uint16_t itr_idx)
2049 {
2050         int i;
2051         uint32_t val;
2052         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2053         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2054
2055         /* Bind all RX queues to allocated MSIX interrupt */
2056         for (i = 0; i < nb_queue; i++) {
2057                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2058                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2059                         ((base_queue + i + 1) <<
2060                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2061                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2062                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2063
2064                 if (i == nb_queue - 1)
2065                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2066                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2067         }
2068
2069         /* Write first RX queue to Link list register as the head element */
2070         if (vsi->type != I40E_VSI_SRIOV) {
2071                 uint16_t interval =
2072                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2073
2074                 if (msix_vect == I40E_MISC_VEC_ID) {
2075                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2076                                        (base_queue <<
2077                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2078                                        (0x0 <<
2079                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2080                         I40E_WRITE_REG(hw,
2081                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2082                                        interval);
2083                 } else {
2084                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2085                                        (base_queue <<
2086                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2087                                        (0x0 <<
2088                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2089                         I40E_WRITE_REG(hw,
2090                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2091                                                        msix_vect - 1),
2092                                        interval);
2093                 }
2094         } else {
2095                 uint32_t reg;
2096
2097                 if (msix_vect == I40E_MISC_VEC_ID) {
2098                         I40E_WRITE_REG(hw,
2099                                        I40E_VPINT_LNKLST0(vsi->user_param),
2100                                        (base_queue <<
2101                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2102                                        (0x0 <<
2103                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2104                 } else {
2105                         /* num_msix_vectors_vf needs to minus irq0 */
2106                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2107                                 vsi->user_param + (msix_vect - 1);
2108
2109                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2110                                        (base_queue <<
2111                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2112                                        (0x0 <<
2113                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2114                 }
2115         }
2116
2117         I40E_WRITE_FLUSH(hw);
2118 }
2119
2120 int
2121 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2122 {
2123         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2124         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2126         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2127         uint16_t msix_vect = vsi->msix_intr;
2128         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2129         uint16_t queue_idx = 0;
2130         int record = 0;
2131         int i;
2132
2133         for (i = 0; i < vsi->nb_qps; i++) {
2134                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2135                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2136         }
2137
2138         /* VF bind interrupt */
2139         if (vsi->type == I40E_VSI_SRIOV) {
2140                 if (vsi->nb_msix == 0) {
2141                         PMD_DRV_LOG(ERR, "No msix resource");
2142                         return -EINVAL;
2143                 }
2144                 __vsi_queues_bind_intr(vsi, msix_vect,
2145                                        vsi->base_queue, vsi->nb_qps,
2146                                        itr_idx);
2147                 return 0;
2148         }
2149
2150         /* PF & VMDq bind interrupt */
2151         if (rte_intr_dp_is_en(intr_handle)) {
2152                 if (vsi->type == I40E_VSI_MAIN) {
2153                         queue_idx = 0;
2154                         record = 1;
2155                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2156                         struct i40e_vsi *main_vsi =
2157                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2158                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2159                         record = 1;
2160                 }
2161         }
2162
2163         for (i = 0; i < vsi->nb_used_qps; i++) {
2164                 if (vsi->nb_msix == 0) {
2165                         PMD_DRV_LOG(ERR, "No msix resource");
2166                         return -EINVAL;
2167                 } else if (nb_msix <= 1) {
2168                         if (!rte_intr_allow_others(intr_handle))
2169                                 /* allow to share MISC_VEC_ID */
2170                                 msix_vect = I40E_MISC_VEC_ID;
2171
2172                         /* no enough msix_vect, map all to one */
2173                         __vsi_queues_bind_intr(vsi, msix_vect,
2174                                                vsi->base_queue + i,
2175                                                vsi->nb_used_qps - i,
2176                                                itr_idx);
2177                         for (; !!record && i < vsi->nb_used_qps; i++)
2178                                 intr_handle->intr_vec[queue_idx + i] =
2179                                         msix_vect;
2180                         break;
2181                 }
2182                 /* 1:1 queue/msix_vect mapping */
2183                 __vsi_queues_bind_intr(vsi, msix_vect,
2184                                        vsi->base_queue + i, 1,
2185                                        itr_idx);
2186                 if (!!record)
2187                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2188
2189                 msix_vect++;
2190                 nb_msix--;
2191         }
2192
2193         return 0;
2194 }
2195
2196 void
2197 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2198 {
2199         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2200         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2201         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2202         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2203         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2204         uint16_t msix_intr, i;
2205
2206         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2207                 for (i = 0; i < vsi->nb_msix; i++) {
2208                         msix_intr = vsi->msix_intr + i;
2209                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2210                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2211                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2212                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2213                 }
2214         else
2215                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2216                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2217                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2218                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2219
2220         I40E_WRITE_FLUSH(hw);
2221 }
2222
2223 void
2224 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2225 {
2226         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2227         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2228         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2229         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2230         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2231         uint16_t msix_intr, i;
2232
2233         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2234                 for (i = 0; i < vsi->nb_msix; i++) {
2235                         msix_intr = vsi->msix_intr + i;
2236                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2237                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2238                 }
2239         else
2240                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2241                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2242
2243         I40E_WRITE_FLUSH(hw);
2244 }
2245
2246 static inline uint8_t
2247 i40e_parse_link_speeds(uint16_t link_speeds)
2248 {
2249         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2250
2251         if (link_speeds & ETH_LINK_SPEED_40G)
2252                 link_speed |= I40E_LINK_SPEED_40GB;
2253         if (link_speeds & ETH_LINK_SPEED_25G)
2254                 link_speed |= I40E_LINK_SPEED_25GB;
2255         if (link_speeds & ETH_LINK_SPEED_20G)
2256                 link_speed |= I40E_LINK_SPEED_20GB;
2257         if (link_speeds & ETH_LINK_SPEED_10G)
2258                 link_speed |= I40E_LINK_SPEED_10GB;
2259         if (link_speeds & ETH_LINK_SPEED_1G)
2260                 link_speed |= I40E_LINK_SPEED_1GB;
2261         if (link_speeds & ETH_LINK_SPEED_100M)
2262                 link_speed |= I40E_LINK_SPEED_100MB;
2263
2264         return link_speed;
2265 }
2266
2267 static int
2268 i40e_phy_conf_link(struct i40e_hw *hw,
2269                    uint8_t abilities,
2270                    uint8_t force_speed,
2271                    bool is_up)
2272 {
2273         enum i40e_status_code status;
2274         struct i40e_aq_get_phy_abilities_resp phy_ab;
2275         struct i40e_aq_set_phy_config phy_conf;
2276         enum i40e_aq_phy_type cnt;
2277         uint8_t avail_speed;
2278         uint32_t phy_type_mask = 0;
2279
2280         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2281                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2282                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2283                         I40E_AQ_PHY_FLAG_LOW_POWER;
2284         int ret = -ENOTSUP;
2285
2286         /* To get phy capabilities of available speeds. */
2287         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2288                                               NULL);
2289         if (status) {
2290                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2291                                 status);
2292                 return ret;
2293         }
2294         avail_speed = phy_ab.link_speed;
2295
2296         /* To get the current phy config. */
2297         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2298                                               NULL);
2299         if (status) {
2300                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2301                                 status);
2302                 return ret;
2303         }
2304
2305         /* If link needs to go up and it is in autoneg mode the speed is OK,
2306          * no need to set up again.
2307          */
2308         if (is_up && phy_ab.phy_type != 0 &&
2309                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2310                      phy_ab.link_speed != 0)
2311                 return I40E_SUCCESS;
2312
2313         memset(&phy_conf, 0, sizeof(phy_conf));
2314
2315         /* bits 0-2 use the values from get_phy_abilities_resp */
2316         abilities &= ~mask;
2317         abilities |= phy_ab.abilities & mask;
2318
2319         phy_conf.abilities = abilities;
2320
2321         /* If link needs to go up, but the force speed is not supported,
2322          * Warn users and config the default available speeds.
2323          */
2324         if (is_up && !(force_speed & avail_speed)) {
2325                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2326                 phy_conf.link_speed = avail_speed;
2327         } else {
2328                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2329         }
2330
2331         /* PHY type mask needs to include each type except PHY type extension */
2332         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2333                 phy_type_mask |= 1 << cnt;
2334
2335         /* use get_phy_abilities_resp value for the rest */
2336         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2337         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2338                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2339                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2340         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2341         phy_conf.eee_capability = phy_ab.eee_capability;
2342         phy_conf.eeer = phy_ab.eeer_val;
2343         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2344
2345         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2346                     phy_ab.abilities, phy_ab.link_speed);
2347         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2348                     phy_conf.abilities, phy_conf.link_speed);
2349
2350         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2351         if (status)
2352                 return ret;
2353
2354         return I40E_SUCCESS;
2355 }
2356
2357 static int
2358 i40e_apply_link_speed(struct rte_eth_dev *dev)
2359 {
2360         uint8_t speed;
2361         uint8_t abilities = 0;
2362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363         struct rte_eth_conf *conf = &dev->data->dev_conf;
2364
2365         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2366                      I40E_AQ_PHY_LINK_ENABLED;
2367
2368         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2369                 conf->link_speeds = ETH_LINK_SPEED_40G |
2370                                     ETH_LINK_SPEED_25G |
2371                                     ETH_LINK_SPEED_20G |
2372                                     ETH_LINK_SPEED_10G |
2373                                     ETH_LINK_SPEED_1G |
2374                                     ETH_LINK_SPEED_100M;
2375
2376                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2377         } else {
2378                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2379         }
2380         speed = i40e_parse_link_speeds(conf->link_speeds);
2381
2382         return i40e_phy_conf_link(hw, abilities, speed, true);
2383 }
2384
2385 static int
2386 i40e_dev_start(struct rte_eth_dev *dev)
2387 {
2388         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2389         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390         struct i40e_vsi *main_vsi = pf->main_vsi;
2391         int ret, i;
2392         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2393         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2394         uint32_t intr_vector = 0;
2395         struct i40e_vsi *vsi;
2396         uint16_t nb_rxq, nb_txq;
2397
2398         hw->adapter_stopped = 0;
2399
2400         rte_intr_disable(intr_handle);
2401
2402         if ((rte_intr_cap_multiple(intr_handle) ||
2403              !RTE_ETH_DEV_SRIOV(dev).active) &&
2404             dev->data->dev_conf.intr_conf.rxq != 0) {
2405                 intr_vector = dev->data->nb_rx_queues;
2406                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2407                 if (ret)
2408                         return ret;
2409         }
2410
2411         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2412                 intr_handle->intr_vec =
2413                         rte_zmalloc("intr_vec",
2414                                     dev->data->nb_rx_queues * sizeof(int),
2415                                     0);
2416                 if (!intr_handle->intr_vec) {
2417                         PMD_INIT_LOG(ERR,
2418                                 "Failed to allocate %d rx_queues intr_vec",
2419                                 dev->data->nb_rx_queues);
2420                         return -ENOMEM;
2421                 }
2422         }
2423
2424         /* Initialize VSI */
2425         ret = i40e_dev_rxtx_init(pf);
2426         if (ret != I40E_SUCCESS) {
2427                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2428                 return ret;
2429         }
2430
2431         /* Map queues with MSIX interrupt */
2432         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2433                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2434         ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2435         if (ret < 0)
2436                 return ret;
2437         i40e_vsi_enable_queues_intr(main_vsi);
2438
2439         /* Map VMDQ VSI queues with MSIX interrupt */
2440         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2441                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2442                 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2443                                                 I40E_ITR_INDEX_DEFAULT);
2444                 if (ret < 0)
2445                         return ret;
2446                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2447         }
2448
2449         /* Enable all queues which have been configured */
2450         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2451                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2452                 if (ret)
2453                         goto rx_err;
2454         }
2455
2456         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2457                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2458                 if (ret)
2459                         goto tx_err;
2460         }
2461
2462         /* Enable receiving broadcast packets */
2463         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2464         if (ret != I40E_SUCCESS)
2465                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2466
2467         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2468                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2469                                                 true, NULL);
2470                 if (ret != I40E_SUCCESS)
2471                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2472         }
2473
2474         /* Enable the VLAN promiscuous mode. */
2475         if (pf->vfs) {
2476                 for (i = 0; i < pf->vf_num; i++) {
2477                         vsi = pf->vfs[i].vsi;
2478                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2479                                                      true, NULL);
2480                 }
2481         }
2482
2483         /* Enable mac loopback mode */
2484         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2485             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2486                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2487                 if (ret != I40E_SUCCESS) {
2488                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2489                         goto tx_err;
2490                 }
2491         }
2492
2493         /* Apply link configure */
2494         ret = i40e_apply_link_speed(dev);
2495         if (I40E_SUCCESS != ret) {
2496                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2497                 goto tx_err;
2498         }
2499
2500         if (!rte_intr_allow_others(intr_handle)) {
2501                 rte_intr_callback_unregister(intr_handle,
2502                                              i40e_dev_interrupt_handler,
2503                                              (void *)dev);
2504                 /* configure and enable device interrupt */
2505                 i40e_pf_config_irq0(hw, FALSE);
2506                 i40e_pf_enable_irq0(hw);
2507
2508                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2509                         PMD_INIT_LOG(INFO,
2510                                 "lsc won't enable because of no intr multiplex");
2511         } else {
2512                 ret = i40e_aq_set_phy_int_mask(hw,
2513                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2514                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2515                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2516                 if (ret != I40E_SUCCESS)
2517                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2518
2519                 /* Call get_link_info aq commond to enable/disable LSE */
2520                 i40e_dev_link_update(dev, 0);
2521         }
2522
2523         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2524                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2525                                   i40e_dev_alarm_handler, dev);
2526         } else {
2527                 /* enable uio intr after callback register */
2528                 rte_intr_enable(intr_handle);
2529         }
2530
2531         i40e_filter_restore(pf);
2532
2533         if (pf->tm_conf.root && !pf->tm_conf.committed)
2534                 PMD_DRV_LOG(WARNING,
2535                             "please call hierarchy_commit() "
2536                             "before starting the port");
2537
2538         return I40E_SUCCESS;
2539
2540 tx_err:
2541         for (i = 0; i < nb_txq; i++)
2542                 i40e_dev_tx_queue_stop(dev, i);
2543 rx_err:
2544         for (i = 0; i < nb_rxq; i++)
2545                 i40e_dev_rx_queue_stop(dev, i);
2546
2547         return ret;
2548 }
2549
2550 static void
2551 i40e_dev_stop(struct rte_eth_dev *dev)
2552 {
2553         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2554         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555         struct i40e_vsi *main_vsi = pf->main_vsi;
2556         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2557         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2558         int i;
2559
2560         if (hw->adapter_stopped == 1)
2561                 return;
2562
2563         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2564                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2565                 rte_intr_enable(intr_handle);
2566         }
2567
2568         /* Disable all queues */
2569         for (i = 0; i < dev->data->nb_tx_queues; i++)
2570                 i40e_dev_tx_queue_stop(dev, i);
2571
2572         for (i = 0; i < dev->data->nb_rx_queues; i++)
2573                 i40e_dev_rx_queue_stop(dev, i);
2574
2575         /* un-map queues with interrupt registers */
2576         i40e_vsi_disable_queues_intr(main_vsi);
2577         i40e_vsi_queues_unbind_intr(main_vsi);
2578
2579         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2580                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2581                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2582         }
2583
2584         /* Clear all queues and release memory */
2585         i40e_dev_clear_queues(dev);
2586
2587         /* Set link down */
2588         i40e_dev_set_link_down(dev);
2589
2590         if (!rte_intr_allow_others(intr_handle))
2591                 /* resume to the default handler */
2592                 rte_intr_callback_register(intr_handle,
2593                                            i40e_dev_interrupt_handler,
2594                                            (void *)dev);
2595
2596         /* Clean datapath event and queue/vec mapping */
2597         rte_intr_efd_disable(intr_handle);
2598         if (intr_handle->intr_vec) {
2599                 rte_free(intr_handle->intr_vec);
2600                 intr_handle->intr_vec = NULL;
2601         }
2602
2603         /* reset hierarchy commit */
2604         pf->tm_conf.committed = false;
2605
2606         hw->adapter_stopped = 1;
2607
2608         pf->adapter->rss_reta_updated = 0;
2609 }
2610
2611 static void
2612 i40e_dev_close(struct rte_eth_dev *dev)
2613 {
2614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2617         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2618         struct i40e_mirror_rule *p_mirror;
2619         struct i40e_filter_control_settings settings;
2620         struct rte_flow *p_flow;
2621         uint32_t reg;
2622         int i;
2623         int ret;
2624         uint8_t aq_fail = 0;
2625         int retries = 0;
2626
2627         PMD_INIT_FUNC_TRACE();
2628
2629         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2630         if (ret)
2631                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2632
2633
2634         i40e_dev_stop(dev);
2635
2636         /* Remove all mirror rules */
2637         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2638                 ret = i40e_aq_del_mirror_rule(hw,
2639                                               pf->main_vsi->veb->seid,
2640                                               p_mirror->rule_type,
2641                                               p_mirror->entries,
2642                                               p_mirror->num_entries,
2643                                               p_mirror->id);
2644                 if (ret < 0)
2645                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2646                                     "status = %d, aq_err = %d.", ret,
2647                                     hw->aq.asq_last_status);
2648
2649                 /* remove mirror software resource anyway */
2650                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2651                 rte_free(p_mirror);
2652                 pf->nb_mirror_rule--;
2653         }
2654
2655         i40e_dev_free_queues(dev);
2656
2657         /* Disable interrupt */
2658         i40e_pf_disable_irq0(hw);
2659         rte_intr_disable(intr_handle);
2660
2661         /*
2662          * Only legacy filter API needs the following fdir config. So when the
2663          * legacy filter API is deprecated, the following code should also be
2664          * removed.
2665          */
2666         i40e_fdir_teardown(pf);
2667
2668         /* shutdown and destroy the HMC */
2669         i40e_shutdown_lan_hmc(hw);
2670
2671         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2672                 i40e_vsi_release(pf->vmdq[i].vsi);
2673                 pf->vmdq[i].vsi = NULL;
2674         }
2675         rte_free(pf->vmdq);
2676         pf->vmdq = NULL;
2677
2678         /* release all the existing VSIs and VEBs */
2679         i40e_vsi_release(pf->main_vsi);
2680
2681         /* shutdown the adminq */
2682         i40e_aq_queue_shutdown(hw, true);
2683         i40e_shutdown_adminq(hw);
2684
2685         i40e_res_pool_destroy(&pf->qp_pool);
2686         i40e_res_pool_destroy(&pf->msix_pool);
2687
2688         /* Disable flexible payload in global configuration */
2689         if (!pf->support_multi_driver)
2690                 i40e_flex_payload_reg_set_default(hw);
2691
2692         /* force a PF reset to clean anything leftover */
2693         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2694         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2695                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2696         I40E_WRITE_FLUSH(hw);
2697
2698         dev->dev_ops = NULL;
2699         dev->rx_pkt_burst = NULL;
2700         dev->tx_pkt_burst = NULL;
2701
2702         /* Clear PXE mode */
2703         i40e_clear_pxe_mode(hw);
2704
2705         /* Unconfigure filter control */
2706         memset(&settings, 0, sizeof(settings));
2707         ret = i40e_set_filter_control(hw, &settings);
2708         if (ret)
2709                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2710                                         ret);
2711
2712         /* Disable flow control */
2713         hw->fc.requested_mode = I40E_FC_NONE;
2714         i40e_set_fc(hw, &aq_fail, TRUE);
2715
2716         /* uninitialize pf host driver */
2717         i40e_pf_host_uninit(dev);
2718
2719         do {
2720                 ret = rte_intr_callback_unregister(intr_handle,
2721                                 i40e_dev_interrupt_handler, dev);
2722                 if (ret >= 0 || ret == -ENOENT) {
2723                         break;
2724                 } else if (ret != -EAGAIN) {
2725                         PMD_INIT_LOG(ERR,
2726                                  "intr callback unregister failed: %d",
2727                                  ret);
2728                 }
2729                 i40e_msec_delay(500);
2730         } while (retries++ < 5);
2731
2732         i40e_rm_ethtype_filter_list(pf);
2733         i40e_rm_tunnel_filter_list(pf);
2734         i40e_rm_fdir_filter_list(pf);
2735
2736         /* Remove all flows */
2737         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2738                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2739                 /* Do not free FDIR flows since they are static allocated */
2740                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2741                         rte_free(p_flow);
2742         }
2743
2744         /* release the fdir static allocated memory */
2745         i40e_fdir_memory_cleanup(pf);
2746
2747         /* Remove all Traffic Manager configuration */
2748         i40e_tm_conf_uninit(dev);
2749
2750         hw->adapter_closed = 1;
2751 }
2752
2753 /*
2754  * Reset PF device only to re-initialize resources in PMD layer
2755  */
2756 static int
2757 i40e_dev_reset(struct rte_eth_dev *dev)
2758 {
2759         int ret;
2760
2761         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2762          * its VF to make them align with it. The detailed notification
2763          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2764          * To avoid unexpected behavior in VF, currently reset of PF with
2765          * SR-IOV activation is not supported. It might be supported later.
2766          */
2767         if (dev->data->sriov.active)
2768                 return -ENOTSUP;
2769
2770         ret = eth_i40e_dev_uninit(dev);
2771         if (ret)
2772                 return ret;
2773
2774         ret = eth_i40e_dev_init(dev, NULL);
2775
2776         return ret;
2777 }
2778
2779 static int
2780 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2781 {
2782         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784         struct i40e_vsi *vsi = pf->main_vsi;
2785         int status;
2786
2787         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2788                                                      true, NULL, true);
2789         if (status != I40E_SUCCESS) {
2790                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2791                 return -EAGAIN;
2792         }
2793
2794         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2795                                                         TRUE, NULL);
2796         if (status != I40E_SUCCESS) {
2797                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2798                 /* Rollback unicast promiscuous mode */
2799                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2800                                                     false, NULL, true);
2801                 return -EAGAIN;
2802         }
2803
2804         return 0;
2805 }
2806
2807 static int
2808 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2809 {
2810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812         struct i40e_vsi *vsi = pf->main_vsi;
2813         int status;
2814
2815         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2816                                                      false, NULL, true);
2817         if (status != I40E_SUCCESS) {
2818                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2819                 return -EAGAIN;
2820         }
2821
2822         /* must remain in all_multicast mode */
2823         if (dev->data->all_multicast == 1)
2824                 return 0;
2825
2826         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2827                                                         false, NULL);
2828         if (status != I40E_SUCCESS) {
2829                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2830                 /* Rollback unicast promiscuous mode */
2831                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2832                                                     true, NULL, true);
2833                 return -EAGAIN;
2834         }
2835
2836         return 0;
2837 }
2838
2839 static int
2840 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2841 {
2842         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844         struct i40e_vsi *vsi = pf->main_vsi;
2845         int ret;
2846
2847         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2848         if (ret != I40E_SUCCESS) {
2849                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2850                 return -EAGAIN;
2851         }
2852
2853         return 0;
2854 }
2855
2856 static int
2857 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2858 {
2859         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2860         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861         struct i40e_vsi *vsi = pf->main_vsi;
2862         int ret;
2863
2864         if (dev->data->promiscuous == 1)
2865                 return 0; /* must remain in all_multicast mode */
2866
2867         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2868                                 vsi->seid, FALSE, NULL);
2869         if (ret != I40E_SUCCESS) {
2870                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2871                 return -EAGAIN;
2872         }
2873
2874         return 0;
2875 }
2876
2877 /*
2878  * Set device link up.
2879  */
2880 static int
2881 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2882 {
2883         /* re-apply link speed setting */
2884         return i40e_apply_link_speed(dev);
2885 }
2886
2887 /*
2888  * Set device link down.
2889  */
2890 static int
2891 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2892 {
2893         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2894         uint8_t abilities = 0;
2895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896
2897         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2898         return i40e_phy_conf_link(hw, abilities, speed, false);
2899 }
2900
2901 static __rte_always_inline void
2902 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2903 {
2904 /* Link status registers and values*/
2905 #define I40E_PRTMAC_LINKSTA             0x001E2420
2906 #define I40E_REG_LINK_UP                0x40000080
2907 #define I40E_PRTMAC_MACC                0x001E24E0
2908 #define I40E_REG_MACC_25GB              0x00020000
2909 #define I40E_REG_SPEED_MASK             0x38000000
2910 #define I40E_REG_SPEED_0                0x00000000
2911 #define I40E_REG_SPEED_1                0x08000000
2912 #define I40E_REG_SPEED_2                0x10000000
2913 #define I40E_REG_SPEED_3                0x18000000
2914 #define I40E_REG_SPEED_4                0x20000000
2915         uint32_t link_speed;
2916         uint32_t reg_val;
2917
2918         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2919         link_speed = reg_val & I40E_REG_SPEED_MASK;
2920         reg_val &= I40E_REG_LINK_UP;
2921         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2922
2923         if (unlikely(link->link_status == 0))
2924                 return;
2925
2926         /* Parse the link status */
2927         switch (link_speed) {
2928         case I40E_REG_SPEED_0:
2929                 link->link_speed = ETH_SPEED_NUM_100M;
2930                 break;
2931         case I40E_REG_SPEED_1:
2932                 link->link_speed = ETH_SPEED_NUM_1G;
2933                 break;
2934         case I40E_REG_SPEED_2:
2935                 if (hw->mac.type == I40E_MAC_X722)
2936                         link->link_speed = ETH_SPEED_NUM_2_5G;
2937                 else
2938                         link->link_speed = ETH_SPEED_NUM_10G;
2939                 break;
2940         case I40E_REG_SPEED_3:
2941                 if (hw->mac.type == I40E_MAC_X722) {
2942                         link->link_speed = ETH_SPEED_NUM_5G;
2943                 } else {
2944                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2945
2946                         if (reg_val & I40E_REG_MACC_25GB)
2947                                 link->link_speed = ETH_SPEED_NUM_25G;
2948                         else
2949                                 link->link_speed = ETH_SPEED_NUM_40G;
2950                 }
2951                 break;
2952         case I40E_REG_SPEED_4:
2953                 if (hw->mac.type == I40E_MAC_X722)
2954                         link->link_speed = ETH_SPEED_NUM_10G;
2955                 else
2956                         link->link_speed = ETH_SPEED_NUM_20G;
2957                 break;
2958         default:
2959                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2960                 break;
2961         }
2962 }
2963
2964 static __rte_always_inline void
2965 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2966         bool enable_lse, int wait_to_complete)
2967 {
2968 #define CHECK_INTERVAL             100  /* 100ms */
2969 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2970         uint32_t rep_cnt = MAX_REPEAT_TIME;
2971         struct i40e_link_status link_status;
2972         int status;
2973
2974         memset(&link_status, 0, sizeof(link_status));
2975
2976         do {
2977                 memset(&link_status, 0, sizeof(link_status));
2978
2979                 /* Get link status information from hardware */
2980                 status = i40e_aq_get_link_info(hw, enable_lse,
2981                                                 &link_status, NULL);
2982                 if (unlikely(status != I40E_SUCCESS)) {
2983                         link->link_speed = ETH_SPEED_NUM_NONE;
2984                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2985                         PMD_DRV_LOG(ERR, "Failed to get link info");
2986                         return;
2987                 }
2988
2989                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2990                 if (!wait_to_complete || link->link_status)
2991                         break;
2992
2993                 rte_delay_ms(CHECK_INTERVAL);
2994         } while (--rep_cnt);
2995
2996         /* Parse the link status */
2997         switch (link_status.link_speed) {
2998         case I40E_LINK_SPEED_100MB:
2999                 link->link_speed = ETH_SPEED_NUM_100M;
3000                 break;
3001         case I40E_LINK_SPEED_1GB:
3002                 link->link_speed = ETH_SPEED_NUM_1G;
3003                 break;
3004         case I40E_LINK_SPEED_10GB:
3005                 link->link_speed = ETH_SPEED_NUM_10G;
3006                 break;
3007         case I40E_LINK_SPEED_20GB:
3008                 link->link_speed = ETH_SPEED_NUM_20G;
3009                 break;
3010         case I40E_LINK_SPEED_25GB:
3011                 link->link_speed = ETH_SPEED_NUM_25G;
3012                 break;
3013         case I40E_LINK_SPEED_40GB:
3014                 link->link_speed = ETH_SPEED_NUM_40G;
3015                 break;
3016         default:
3017                 if (link->link_status)
3018                         link->link_speed = ETH_SPEED_NUM_UNKNOWN;
3019                 else
3020                         link->link_speed = ETH_SPEED_NUM_NONE;
3021                 break;
3022         }
3023 }
3024
3025 int
3026 i40e_dev_link_update(struct rte_eth_dev *dev,
3027                      int wait_to_complete)
3028 {
3029         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030         struct rte_eth_link link;
3031         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3032         int ret;
3033
3034         memset(&link, 0, sizeof(link));
3035
3036         /* i40e uses full duplex only */
3037         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3038         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3039                         ETH_LINK_SPEED_FIXED);
3040
3041         if (!wait_to_complete && !enable_lse)
3042                 update_link_reg(hw, &link);
3043         else
3044                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3045
3046         if (hw->switch_dev)
3047                 rte_eth_linkstatus_get(hw->switch_dev, &link);
3048
3049         ret = rte_eth_linkstatus_set(dev, &link);
3050         i40e_notify_all_vfs_link_status(dev);
3051
3052         return ret;
3053 }
3054
3055 static void
3056 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3057                           uint32_t loreg, bool offset_loaded, uint64_t *offset,
3058                           uint64_t *stat, uint64_t *prev_stat)
3059 {
3060         i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3061         /* enlarge the limitation when statistics counters overflowed */
3062         if (offset_loaded) {
3063                 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3064                         *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3065                 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3066         }
3067         *prev_stat = *stat;
3068 }
3069
3070 /* Get all the statistics of a VSI */
3071 void
3072 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3073 {
3074         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3075         struct i40e_eth_stats *nes = &vsi->eth_stats;
3076         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3077         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3078
3079         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3080                                   vsi->offset_loaded, &oes->rx_bytes,
3081                                   &nes->rx_bytes, &vsi->prev_rx_bytes);
3082         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3083                             vsi->offset_loaded, &oes->rx_unicast,
3084                             &nes->rx_unicast);
3085         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3086                             vsi->offset_loaded, &oes->rx_multicast,
3087                             &nes->rx_multicast);
3088         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3089                             vsi->offset_loaded, &oes->rx_broadcast,
3090                             &nes->rx_broadcast);
3091         /* exclude CRC bytes */
3092         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3093                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3094
3095         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3096                             &oes->rx_discards, &nes->rx_discards);
3097         /* GLV_REPC not supported */
3098         /* GLV_RMPC not supported */
3099         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3100                             &oes->rx_unknown_protocol,
3101                             &nes->rx_unknown_protocol);
3102         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3103                                   vsi->offset_loaded, &oes->tx_bytes,
3104                                   &nes->tx_bytes, &vsi->prev_tx_bytes);
3105         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3106                             vsi->offset_loaded, &oes->tx_unicast,
3107                             &nes->tx_unicast);
3108         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3109                             vsi->offset_loaded, &oes->tx_multicast,
3110                             &nes->tx_multicast);
3111         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3112                             vsi->offset_loaded,  &oes->tx_broadcast,
3113                             &nes->tx_broadcast);
3114         /* GLV_TDPC not supported */
3115         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3116                             &oes->tx_errors, &nes->tx_errors);
3117         vsi->offset_loaded = true;
3118
3119         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3120                     vsi->vsi_id);
3121         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3122         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3123         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3124         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3125         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3126         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3127                     nes->rx_unknown_protocol);
3128         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3129         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3130         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3131         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3132         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3133         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3134         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3135                     vsi->vsi_id);
3136 }
3137
3138 static void
3139 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3140 {
3141         unsigned int i;
3142         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3143         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3144
3145         /* Get rx/tx bytes of internal transfer packets */
3146         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3147                                   I40E_GLV_GORCL(hw->port),
3148                                   pf->offset_loaded,
3149                                   &pf->internal_stats_offset.rx_bytes,
3150                                   &pf->internal_stats.rx_bytes,
3151                                   &pf->internal_prev_rx_bytes);
3152         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3153                                   I40E_GLV_GOTCL(hw->port),
3154                                   pf->offset_loaded,
3155                                   &pf->internal_stats_offset.tx_bytes,
3156                                   &pf->internal_stats.tx_bytes,
3157                                   &pf->internal_prev_tx_bytes);
3158         /* Get total internal rx packet count */
3159         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3160                             I40E_GLV_UPRCL(hw->port),
3161                             pf->offset_loaded,
3162                             &pf->internal_stats_offset.rx_unicast,
3163                             &pf->internal_stats.rx_unicast);
3164         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3165                             I40E_GLV_MPRCL(hw->port),
3166                             pf->offset_loaded,
3167                             &pf->internal_stats_offset.rx_multicast,
3168                             &pf->internal_stats.rx_multicast);
3169         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3170                             I40E_GLV_BPRCL(hw->port),
3171                             pf->offset_loaded,
3172                             &pf->internal_stats_offset.rx_broadcast,
3173                             &pf->internal_stats.rx_broadcast);
3174         /* Get total internal tx packet count */
3175         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3176                             I40E_GLV_UPTCL(hw->port),
3177                             pf->offset_loaded,
3178                             &pf->internal_stats_offset.tx_unicast,
3179                             &pf->internal_stats.tx_unicast);
3180         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3181                             I40E_GLV_MPTCL(hw->port),
3182                             pf->offset_loaded,
3183                             &pf->internal_stats_offset.tx_multicast,
3184                             &pf->internal_stats.tx_multicast);
3185         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3186                             I40E_GLV_BPTCL(hw->port),
3187                             pf->offset_loaded,
3188                             &pf->internal_stats_offset.tx_broadcast,
3189                             &pf->internal_stats.tx_broadcast);
3190
3191         /* exclude CRC size */
3192         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3193                 pf->internal_stats.rx_multicast +
3194                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3195
3196         /* Get statistics of struct i40e_eth_stats */
3197         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3198                                   I40E_GLPRT_GORCL(hw->port),
3199                                   pf->offset_loaded, &os->eth.rx_bytes,
3200                                   &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3201         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3202                             I40E_GLPRT_UPRCL(hw->port),
3203                             pf->offset_loaded, &os->eth.rx_unicast,
3204                             &ns->eth.rx_unicast);
3205         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3206                             I40E_GLPRT_MPRCL(hw->port),
3207                             pf->offset_loaded, &os->eth.rx_multicast,
3208                             &ns->eth.rx_multicast);
3209         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3210                             I40E_GLPRT_BPRCL(hw->port),
3211                             pf->offset_loaded, &os->eth.rx_broadcast,
3212                             &ns->eth.rx_broadcast);
3213         /* Workaround: CRC size should not be included in byte statistics,
3214          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3215          * packet.
3216          */
3217         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3218                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3219
3220         /* exclude internal rx bytes
3221          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3222          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3223          * value.
3224          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3225          */
3226         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3227                 ns->eth.rx_bytes = 0;
3228         else
3229                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3230
3231         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3232                 ns->eth.rx_unicast = 0;
3233         else
3234                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3235
3236         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3237                 ns->eth.rx_multicast = 0;
3238         else
3239                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3240
3241         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3242                 ns->eth.rx_broadcast = 0;
3243         else
3244                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3245
3246         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3247                             pf->offset_loaded, &os->eth.rx_discards,
3248                             &ns->eth.rx_discards);
3249         /* GLPRT_REPC not supported */
3250         /* GLPRT_RMPC not supported */
3251         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3252                             pf->offset_loaded,
3253                             &os->eth.rx_unknown_protocol,
3254                             &ns->eth.rx_unknown_protocol);
3255         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3256                                   I40E_GLPRT_GOTCL(hw->port),
3257                                   pf->offset_loaded, &os->eth.tx_bytes,
3258                                   &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3259         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3260                             I40E_GLPRT_UPTCL(hw->port),
3261                             pf->offset_loaded, &os->eth.tx_unicast,
3262                             &ns->eth.tx_unicast);
3263         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3264                             I40E_GLPRT_MPTCL(hw->port),
3265                             pf->offset_loaded, &os->eth.tx_multicast,
3266                             &ns->eth.tx_multicast);
3267         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3268                             I40E_GLPRT_BPTCL(hw->port),
3269                             pf->offset_loaded, &os->eth.tx_broadcast,
3270                             &ns->eth.tx_broadcast);
3271         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3272                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3273
3274         /* exclude internal tx bytes
3275          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3276          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3277          * value.
3278          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3279          */
3280         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3281                 ns->eth.tx_bytes = 0;
3282         else
3283                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3284
3285         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3286                 ns->eth.tx_unicast = 0;
3287         else
3288                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3289
3290         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3291                 ns->eth.tx_multicast = 0;
3292         else
3293                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3294
3295         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3296                 ns->eth.tx_broadcast = 0;
3297         else
3298                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3299
3300         /* GLPRT_TEPC not supported */
3301
3302         /* additional port specific stats */
3303         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3304                             pf->offset_loaded, &os->tx_dropped_link_down,
3305                             &ns->tx_dropped_link_down);
3306         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3307                             pf->offset_loaded, &os->crc_errors,
3308                             &ns->crc_errors);
3309         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3310                             pf->offset_loaded, &os->illegal_bytes,
3311                             &ns->illegal_bytes);
3312         /* GLPRT_ERRBC not supported */
3313         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3314                             pf->offset_loaded, &os->mac_local_faults,
3315                             &ns->mac_local_faults);
3316         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3317                             pf->offset_loaded, &os->mac_remote_faults,
3318                             &ns->mac_remote_faults);
3319         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3320                             pf->offset_loaded, &os->rx_length_errors,
3321                             &ns->rx_length_errors);
3322         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3323                             pf->offset_loaded, &os->link_xon_rx,
3324                             &ns->link_xon_rx);
3325         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3326                             pf->offset_loaded, &os->link_xoff_rx,
3327                             &ns->link_xoff_rx);
3328         for (i = 0; i < 8; i++) {
3329                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3330                                     pf->offset_loaded,
3331                                     &os->priority_xon_rx[i],
3332                                     &ns->priority_xon_rx[i]);
3333                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3334                                     pf->offset_loaded,
3335                                     &os->priority_xoff_rx[i],
3336                                     &ns->priority_xoff_rx[i]);
3337         }
3338         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3339                             pf->offset_loaded, &os->link_xon_tx,
3340                             &ns->link_xon_tx);
3341         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3342                             pf->offset_loaded, &os->link_xoff_tx,
3343                             &ns->link_xoff_tx);
3344         for (i = 0; i < 8; i++) {
3345                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3346                                     pf->offset_loaded,
3347                                     &os->priority_xon_tx[i],
3348                                     &ns->priority_xon_tx[i]);
3349                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3350                                     pf->offset_loaded,
3351                                     &os->priority_xoff_tx[i],
3352                                     &ns->priority_xoff_tx[i]);
3353                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3354                                     pf->offset_loaded,
3355                                     &os->priority_xon_2_xoff[i],
3356                                     &ns->priority_xon_2_xoff[i]);
3357         }
3358         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3359                             I40E_GLPRT_PRC64L(hw->port),
3360                             pf->offset_loaded, &os->rx_size_64,
3361                             &ns->rx_size_64);
3362         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3363                             I40E_GLPRT_PRC127L(hw->port),
3364                             pf->offset_loaded, &os->rx_size_127,
3365                             &ns->rx_size_127);
3366         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3367                             I40E_GLPRT_PRC255L(hw->port),
3368                             pf->offset_loaded, &os->rx_size_255,
3369                             &ns->rx_size_255);
3370         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3371                             I40E_GLPRT_PRC511L(hw->port),
3372                             pf->offset_loaded, &os->rx_size_511,
3373                             &ns->rx_size_511);
3374         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3375                             I40E_GLPRT_PRC1023L(hw->port),
3376                             pf->offset_loaded, &os->rx_size_1023,
3377                             &ns->rx_size_1023);
3378         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3379                             I40E_GLPRT_PRC1522L(hw->port),
3380                             pf->offset_loaded, &os->rx_size_1522,
3381                             &ns->rx_size_1522);
3382         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3383                             I40E_GLPRT_PRC9522L(hw->port),
3384                             pf->offset_loaded, &os->rx_size_big,
3385                             &ns->rx_size_big);
3386         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3387                             pf->offset_loaded, &os->rx_undersize,
3388                             &ns->rx_undersize);
3389         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3390                             pf->offset_loaded, &os->rx_fragments,
3391                             &ns->rx_fragments);
3392         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3393                             pf->offset_loaded, &os->rx_oversize,
3394                             &ns->rx_oversize);
3395         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3396                             pf->offset_loaded, &os->rx_jabber,
3397                             &ns->rx_jabber);
3398         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3399                             I40E_GLPRT_PTC64L(hw->port),
3400                             pf->offset_loaded, &os->tx_size_64,
3401                             &ns->tx_size_64);
3402         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3403                             I40E_GLPRT_PTC127L(hw->port),
3404                             pf->offset_loaded, &os->tx_size_127,
3405                             &ns->tx_size_127);
3406         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3407                             I40E_GLPRT_PTC255L(hw->port),
3408                             pf->offset_loaded, &os->tx_size_255,
3409                             &ns->tx_size_255);
3410         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3411                             I40E_GLPRT_PTC511L(hw->port),
3412                             pf->offset_loaded, &os->tx_size_511,
3413                             &ns->tx_size_511);
3414         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3415                             I40E_GLPRT_PTC1023L(hw->port),
3416                             pf->offset_loaded, &os->tx_size_1023,
3417                             &ns->tx_size_1023);
3418         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3419                             I40E_GLPRT_PTC1522L(hw->port),
3420                             pf->offset_loaded, &os->tx_size_1522,
3421                             &ns->tx_size_1522);
3422         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3423                             I40E_GLPRT_PTC9522L(hw->port),
3424                             pf->offset_loaded, &os->tx_size_big,
3425                             &ns->tx_size_big);
3426         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3427                            pf->offset_loaded,
3428                            &os->fd_sb_match, &ns->fd_sb_match);
3429         /* GLPRT_MSPDC not supported */
3430         /* GLPRT_XEC not supported */
3431
3432         pf->offset_loaded = true;
3433
3434         if (pf->main_vsi)
3435                 i40e_update_vsi_stats(pf->main_vsi);
3436 }
3437
3438 /* Get all statistics of a port */
3439 static int
3440 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3441 {
3442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3443         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3445         struct i40e_vsi *vsi;
3446         unsigned i;
3447
3448         /* call read registers - updates values, now write them to struct */
3449         i40e_read_stats_registers(pf, hw);
3450
3451         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3452                         pf->main_vsi->eth_stats.rx_multicast +
3453                         pf->main_vsi->eth_stats.rx_broadcast -
3454                         pf->main_vsi->eth_stats.rx_discards;
3455         stats->opackets = ns->eth.tx_unicast +
3456                         ns->eth.tx_multicast +
3457                         ns->eth.tx_broadcast;
3458         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3459         stats->obytes   = ns->eth.tx_bytes;
3460         stats->oerrors  = ns->eth.tx_errors +
3461                         pf->main_vsi->eth_stats.tx_errors;
3462
3463         /* Rx Errors */
3464         stats->imissed  = ns->eth.rx_discards +
3465                         pf->main_vsi->eth_stats.rx_discards;
3466         stats->ierrors  = ns->crc_errors +
3467                         ns->rx_length_errors + ns->rx_undersize +
3468                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3469
3470         if (pf->vfs) {
3471                 for (i = 0; i < pf->vf_num; i++) {
3472                         vsi = pf->vfs[i].vsi;
3473                         i40e_update_vsi_stats(vsi);
3474
3475                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3476                                         vsi->eth_stats.rx_multicast +
3477                                         vsi->eth_stats.rx_broadcast -
3478                                         vsi->eth_stats.rx_discards);
3479                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3480                         stats->oerrors  += vsi->eth_stats.tx_errors;
3481                         stats->imissed  += vsi->eth_stats.rx_discards;
3482                 }
3483         }
3484
3485         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3486         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3487         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3488         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3489         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3490         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3491         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3492                     ns->eth.rx_unknown_protocol);
3493         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3494         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3495         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3496         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3497         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3498         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3499
3500         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3501                     ns->tx_dropped_link_down);
3502         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3503         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3504                     ns->illegal_bytes);
3505         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3506         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3507                     ns->mac_local_faults);
3508         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3509                     ns->mac_remote_faults);
3510         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3511                     ns->rx_length_errors);
3512         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3513         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3514         for (i = 0; i < 8; i++) {
3515                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3516                                 i, ns->priority_xon_rx[i]);
3517                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3518                                 i, ns->priority_xoff_rx[i]);
3519         }
3520         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3521         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3522         for (i = 0; i < 8; i++) {
3523                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3524                                 i, ns->priority_xon_tx[i]);
3525                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3526                                 i, ns->priority_xoff_tx[i]);
3527                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3528                                 i, ns->priority_xon_2_xoff[i]);
3529         }
3530         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3531         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3532         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3533         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3534         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3535         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3536         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3537         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3538         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3539         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3540         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3541         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3542         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3543         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3544         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3545         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3546         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3547         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3548         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3549                         ns->mac_short_packet_dropped);
3550         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3551                     ns->checksum_error);
3552         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3553         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3554         return 0;
3555 }
3556
3557 /* Reset the statistics */
3558 static int
3559 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3560 {
3561         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3562         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3563
3564         /* Mark PF and VSI stats to update the offset, aka "reset" */
3565         pf->offset_loaded = false;
3566         if (pf->main_vsi)
3567                 pf->main_vsi->offset_loaded = false;
3568
3569         /* read the stats, reading current register values into offset */
3570         i40e_read_stats_registers(pf, hw);
3571
3572         return 0;
3573 }
3574
3575 static uint32_t
3576 i40e_xstats_calc_num(void)
3577 {
3578         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3579                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3580                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3581 }
3582
3583 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3584                                      struct rte_eth_xstat_name *xstats_names,
3585                                      __rte_unused unsigned limit)
3586 {
3587         unsigned count = 0;
3588         unsigned i, prio;
3589
3590         if (xstats_names == NULL)
3591                 return i40e_xstats_calc_num();
3592
3593         /* Note: limit checked in rte_eth_xstats_names() */
3594
3595         /* Get stats from i40e_eth_stats struct */
3596         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3597                 strlcpy(xstats_names[count].name,
3598                         rte_i40e_stats_strings[i].name,
3599                         sizeof(xstats_names[count].name));
3600                 count++;
3601         }
3602
3603         /* Get individiual stats from i40e_hw_port struct */
3604         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3605                 strlcpy(xstats_names[count].name,
3606                         rte_i40e_hw_port_strings[i].name,
3607                         sizeof(xstats_names[count].name));
3608                 count++;
3609         }
3610
3611         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3612                 for (prio = 0; prio < 8; prio++) {
3613                         snprintf(xstats_names[count].name,
3614                                  sizeof(xstats_names[count].name),
3615                                  "rx_priority%u_%s", prio,
3616                                  rte_i40e_rxq_prio_strings[i].name);
3617                         count++;
3618                 }
3619         }
3620
3621         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3622                 for (prio = 0; prio < 8; prio++) {
3623                         snprintf(xstats_names[count].name,
3624                                  sizeof(xstats_names[count].name),
3625                                  "tx_priority%u_%s", prio,
3626                                  rte_i40e_txq_prio_strings[i].name);
3627                         count++;
3628                 }
3629         }
3630         return count;
3631 }
3632
3633 static int
3634 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3635                     unsigned n)
3636 {
3637         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3638         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639         unsigned i, count, prio;
3640         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3641
3642         count = i40e_xstats_calc_num();
3643         if (n < count)
3644                 return count;
3645
3646         i40e_read_stats_registers(pf, hw);
3647
3648         if (xstats == NULL)
3649                 return 0;
3650
3651         count = 0;
3652
3653         /* Get stats from i40e_eth_stats struct */
3654         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3655                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3656                         rte_i40e_stats_strings[i].offset);
3657                 xstats[count].id = count;
3658                 count++;
3659         }
3660
3661         /* Get individiual stats from i40e_hw_port struct */
3662         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3663                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3664                         rte_i40e_hw_port_strings[i].offset);
3665                 xstats[count].id = count;
3666                 count++;
3667         }
3668
3669         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3670                 for (prio = 0; prio < 8; prio++) {
3671                         xstats[count].value =
3672                                 *(uint64_t *)(((char *)hw_stats) +
3673                                 rte_i40e_rxq_prio_strings[i].offset +
3674                                 (sizeof(uint64_t) * prio));
3675                         xstats[count].id = count;
3676                         count++;
3677                 }
3678         }
3679
3680         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3681                 for (prio = 0; prio < 8; prio++) {
3682                         xstats[count].value =
3683                                 *(uint64_t *)(((char *)hw_stats) +
3684                                 rte_i40e_txq_prio_strings[i].offset +
3685                                 (sizeof(uint64_t) * prio));
3686                         xstats[count].id = count;
3687                         count++;
3688                 }
3689         }
3690
3691         return count;
3692 }
3693
3694 static int
3695 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3696 {
3697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698         u32 full_ver;
3699         u8 ver, patch;
3700         u16 build;
3701         int ret;
3702
3703         full_ver = hw->nvm.oem_ver;
3704         ver = (u8)(full_ver >> 24);
3705         build = (u16)((full_ver >> 8) & 0xffff);
3706         patch = (u8)(full_ver & 0xff);
3707
3708         ret = snprintf(fw_version, fw_size,
3709                  "%d.%d%d 0x%08x %d.%d.%d",
3710                  ((hw->nvm.version >> 12) & 0xf),
3711                  ((hw->nvm.version >> 4) & 0xff),
3712                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3713                  ver, build, patch);
3714
3715         ret += 1; /* add the size of '\0' */
3716         if (fw_size < (u32)ret)
3717                 return ret;
3718         else
3719                 return 0;
3720 }
3721
3722 /*
3723  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3724  * the Rx data path does not hang if the FW LLDP is stopped.
3725  * return true if lldp need to stop
3726  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3727  */
3728 static bool
3729 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3730 {
3731         double nvm_ver;
3732         char ver_str[64] = {0};
3733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3734
3735         i40e_fw_version_get(dev, ver_str, 64);
3736         nvm_ver = atof(ver_str);
3737         if ((hw->mac.type == I40E_MAC_X722 ||
3738              hw->mac.type == I40E_MAC_X722_VF) &&
3739              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3740                 return true;
3741         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3742                 return true;
3743
3744         return false;
3745 }
3746
3747 static int
3748 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3749 {
3750         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3752         struct i40e_vsi *vsi = pf->main_vsi;
3753         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3754
3755         dev_info->max_rx_queues = vsi->nb_qps;
3756         dev_info->max_tx_queues = vsi->nb_qps;
3757         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3758         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3759         dev_info->max_mac_addrs = vsi->max_macaddrs;
3760         dev_info->max_vfs = pci_dev->max_vfs;
3761         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3762         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3763         dev_info->rx_queue_offload_capa = 0;
3764         dev_info->rx_offload_capa =
3765                 DEV_RX_OFFLOAD_VLAN_STRIP |
3766                 DEV_RX_OFFLOAD_QINQ_STRIP |
3767                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3768                 DEV_RX_OFFLOAD_UDP_CKSUM |
3769                 DEV_RX_OFFLOAD_TCP_CKSUM |
3770                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3771                 DEV_RX_OFFLOAD_KEEP_CRC |
3772                 DEV_RX_OFFLOAD_SCATTER |
3773                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3774                 DEV_RX_OFFLOAD_VLAN_FILTER |
3775                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3776                 DEV_RX_OFFLOAD_RSS_HASH;
3777
3778         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3779         dev_info->tx_offload_capa =
3780                 DEV_TX_OFFLOAD_VLAN_INSERT |
3781                 DEV_TX_OFFLOAD_QINQ_INSERT |
3782                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3783                 DEV_TX_OFFLOAD_UDP_CKSUM |
3784                 DEV_TX_OFFLOAD_TCP_CKSUM |
3785                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3786                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3787                 DEV_TX_OFFLOAD_TCP_TSO |
3788                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3789                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3790                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3791                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3792                 DEV_TX_OFFLOAD_MULTI_SEGS |
3793                 dev_info->tx_queue_offload_capa;
3794         dev_info->dev_capa =
3795                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3796                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3797
3798         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3799                                                 sizeof(uint32_t);
3800         dev_info->reta_size = pf->hash_lut_size;
3801         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3802
3803         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3804                 .rx_thresh = {
3805                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3806                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3807                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3808                 },
3809                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3810                 .rx_drop_en = 0,
3811                 .offloads = 0,
3812         };
3813
3814         dev_info->default_txconf = (struct rte_eth_txconf) {
3815                 .tx_thresh = {
3816                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3817                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3818                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3819                 },
3820                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3821                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3822                 .offloads = 0,
3823         };
3824
3825         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3826                 .nb_max = I40E_MAX_RING_DESC,
3827                 .nb_min = I40E_MIN_RING_DESC,
3828                 .nb_align = I40E_ALIGN_RING_DESC,
3829         };
3830
3831         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3832                 .nb_max = I40E_MAX_RING_DESC,
3833                 .nb_min = I40E_MIN_RING_DESC,
3834                 .nb_align = I40E_ALIGN_RING_DESC,
3835                 .nb_seg_max = I40E_TX_MAX_SEG,
3836                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3837         };
3838
3839         if (pf->flags & I40E_FLAG_VMDQ) {
3840                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3841                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3842                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3843                                                 pf->max_nb_vmdq_vsi;
3844                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3845                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3846                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3847         }
3848
3849         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3850                 /* For XL710 */
3851                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3852                 dev_info->default_rxportconf.nb_queues = 2;
3853                 dev_info->default_txportconf.nb_queues = 2;
3854                 if (dev->data->nb_rx_queues == 1)
3855                         dev_info->default_rxportconf.ring_size = 2048;
3856                 else
3857                         dev_info->default_rxportconf.ring_size = 1024;
3858                 if (dev->data->nb_tx_queues == 1)
3859                         dev_info->default_txportconf.ring_size = 1024;
3860                 else
3861                         dev_info->default_txportconf.ring_size = 512;
3862
3863         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3864                 /* For XXV710 */
3865                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3866                 dev_info->default_rxportconf.nb_queues = 1;
3867                 dev_info->default_txportconf.nb_queues = 1;
3868                 dev_info->default_rxportconf.ring_size = 256;
3869                 dev_info->default_txportconf.ring_size = 256;
3870         } else {
3871                 /* For X710 */
3872                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3873                 dev_info->default_rxportconf.nb_queues = 1;
3874                 dev_info->default_txportconf.nb_queues = 1;
3875                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3876                         dev_info->default_rxportconf.ring_size = 512;
3877                         dev_info->default_txportconf.ring_size = 256;
3878                 } else {
3879                         dev_info->default_rxportconf.ring_size = 256;
3880                         dev_info->default_txportconf.ring_size = 256;
3881                 }
3882         }
3883         dev_info->default_rxportconf.burst_size = 32;
3884         dev_info->default_txportconf.burst_size = 32;
3885
3886         return 0;
3887 }
3888
3889 static int
3890 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3891 {
3892         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3893         struct i40e_vsi *vsi = pf->main_vsi;
3894         PMD_INIT_FUNC_TRACE();
3895
3896         if (on)
3897                 return i40e_vsi_add_vlan(vsi, vlan_id);
3898         else
3899                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3900 }
3901
3902 static int
3903 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3904                                 enum rte_vlan_type vlan_type,
3905                                 uint16_t tpid, int qinq)
3906 {
3907         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3908         uint64_t reg_r = 0;
3909         uint64_t reg_w = 0;
3910         uint16_t reg_id = 3;
3911         int ret;
3912
3913         if (qinq) {
3914                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3915                         reg_id = 2;
3916         }
3917
3918         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3919                                           &reg_r, NULL);
3920         if (ret != I40E_SUCCESS) {
3921                 PMD_DRV_LOG(ERR,
3922                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3923                            reg_id);
3924                 return -EIO;
3925         }
3926         PMD_DRV_LOG(DEBUG,
3927                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3928                     reg_id, reg_r);
3929
3930         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3931         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3932         if (reg_r == reg_w) {
3933                 PMD_DRV_LOG(DEBUG, "No need to write");
3934                 return 0;
3935         }
3936
3937         ret = i40e_aq_debug_write_global_register(hw,
3938                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3939                                            reg_w, NULL);
3940         if (ret != I40E_SUCCESS) {
3941                 PMD_DRV_LOG(ERR,
3942                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3943                             reg_id);
3944                 return -EIO;
3945         }
3946         PMD_DRV_LOG(DEBUG,
3947                     "Global register 0x%08x is changed with value 0x%08x",
3948                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3949
3950         return 0;
3951 }
3952
3953 static int
3954 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3955                    enum rte_vlan_type vlan_type,
3956                    uint16_t tpid)
3957 {
3958         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3960         int qinq = dev->data->dev_conf.rxmode.offloads &
3961                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3962         int ret = 0;
3963
3964         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3965              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3966             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3967                 PMD_DRV_LOG(ERR,
3968                             "Unsupported vlan type.");
3969                 return -EINVAL;
3970         }
3971
3972         if (pf->support_multi_driver) {
3973                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3974                 return -ENOTSUP;
3975         }
3976
3977         /* 802.1ad frames ability is added in NVM API 1.7*/
3978         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3979                 if (qinq) {
3980                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3981                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3982                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3983                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3984                 } else {
3985                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3986                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3987                 }
3988                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3989                 if (ret != I40E_SUCCESS) {
3990                         PMD_DRV_LOG(ERR,
3991                                     "Set switch config failed aq_err: %d",
3992                                     hw->aq.asq_last_status);
3993                         ret = -EIO;
3994                 }
3995         } else
3996                 /* If NVM API < 1.7, keep the register setting */
3997                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3998                                                       tpid, qinq);
3999
4000         return ret;
4001 }
4002
4003 /* Configure outer vlan stripping on or off in QinQ mode */
4004 static int
4005 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
4006 {
4007         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4008         int ret = I40E_SUCCESS;
4009         uint32_t reg;
4010
4011         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
4012                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
4013                 return -EINVAL;
4014         }
4015
4016         /* Configure for outer VLAN RX stripping */
4017         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4018
4019         if (on)
4020                 reg |= I40E_VSI_TSR_QINQ_STRIP;
4021         else
4022                 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4023
4024         ret = i40e_aq_debug_write_register(hw,
4025                                                    I40E_VSI_TSR(vsi->vsi_id),
4026                                                    reg, NULL);
4027         if (ret < 0) {
4028                 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4029                                     vsi->vsi_id);
4030                 return I40E_ERR_CONFIG;
4031         }
4032
4033         return ret;
4034 }
4035
4036 static int
4037 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4038 {
4039         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4040         struct i40e_vsi *vsi = pf->main_vsi;
4041         struct rte_eth_rxmode *rxmode;
4042
4043         rxmode = &dev->data->dev_conf.rxmode;
4044         if (mask & ETH_VLAN_FILTER_MASK) {
4045                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4046                         i40e_vsi_config_vlan_filter(vsi, TRUE);
4047                 else
4048                         i40e_vsi_config_vlan_filter(vsi, FALSE);
4049         }
4050
4051         if (mask & ETH_VLAN_STRIP_MASK) {
4052                 /* Enable or disable VLAN stripping */
4053                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4054                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
4055                 else
4056                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
4057         }
4058
4059         if (mask & ETH_VLAN_EXTEND_MASK) {
4060                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4061                         i40e_vsi_config_double_vlan(vsi, TRUE);
4062                         /* Set global registers with default ethertype. */
4063                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4064                                            RTE_ETHER_TYPE_VLAN);
4065                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4066                                            RTE_ETHER_TYPE_VLAN);
4067                 }
4068                 else
4069                         i40e_vsi_config_double_vlan(vsi, FALSE);
4070         }
4071
4072         if (mask & ETH_QINQ_STRIP_MASK) {
4073                 /* Enable or disable outer VLAN stripping */
4074                 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4075                         i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4076                 else
4077                         i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4078         }
4079
4080         return 0;
4081 }
4082
4083 static void
4084 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4085                           __rte_unused uint16_t queue,
4086                           __rte_unused int on)
4087 {
4088         PMD_INIT_FUNC_TRACE();
4089 }
4090
4091 static int
4092 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4093 {
4094         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4095         struct i40e_vsi *vsi = pf->main_vsi;
4096         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4097         struct i40e_vsi_vlan_pvid_info info;
4098
4099         memset(&info, 0, sizeof(info));
4100         info.on = on;
4101         if (info.on)
4102                 info.config.pvid = pvid;
4103         else {
4104                 info.config.reject.tagged =
4105                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4106                 info.config.reject.untagged =
4107                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4108         }
4109
4110         return i40e_vsi_vlan_pvid_set(vsi, &info);
4111 }
4112
4113 static int
4114 i40e_dev_led_on(struct rte_eth_dev *dev)
4115 {
4116         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4117         uint32_t mode = i40e_led_get(hw);
4118
4119         if (mode == 0)
4120                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4121
4122         return 0;
4123 }
4124
4125 static int
4126 i40e_dev_led_off(struct rte_eth_dev *dev)
4127 {
4128         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129         uint32_t mode = i40e_led_get(hw);
4130
4131         if (mode != 0)
4132                 i40e_led_set(hw, 0, false);
4133
4134         return 0;
4135 }
4136
4137 static int
4138 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4139 {
4140         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4142
4143         fc_conf->pause_time = pf->fc_conf.pause_time;
4144
4145         /* read out from register, in case they are modified by other port */
4146         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4147                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4148         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4149                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4150
4151         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4152         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4153
4154          /* Return current mode according to actual setting*/
4155         switch (hw->fc.current_mode) {
4156         case I40E_FC_FULL:
4157                 fc_conf->mode = RTE_FC_FULL;
4158                 break;
4159         case I40E_FC_TX_PAUSE:
4160                 fc_conf->mode = RTE_FC_TX_PAUSE;
4161                 break;
4162         case I40E_FC_RX_PAUSE:
4163                 fc_conf->mode = RTE_FC_RX_PAUSE;
4164                 break;
4165         case I40E_FC_NONE:
4166         default:
4167                 fc_conf->mode = RTE_FC_NONE;
4168         };
4169
4170         return 0;
4171 }
4172
4173 static int
4174 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4175 {
4176         uint32_t mflcn_reg, fctrl_reg, reg;
4177         uint32_t max_high_water;
4178         uint8_t i, aq_failure;
4179         int err;
4180         struct i40e_hw *hw;
4181         struct i40e_pf *pf;
4182         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4183                 [RTE_FC_NONE] = I40E_FC_NONE,
4184                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4185                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4186                 [RTE_FC_FULL] = I40E_FC_FULL
4187         };
4188
4189         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4190
4191         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4192         if ((fc_conf->high_water > max_high_water) ||
4193                         (fc_conf->high_water < fc_conf->low_water)) {
4194                 PMD_INIT_LOG(ERR,
4195                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4196                         max_high_water);
4197                 return -EINVAL;
4198         }
4199
4200         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4202         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4203
4204         pf->fc_conf.pause_time = fc_conf->pause_time;
4205         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4206         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4207
4208         PMD_INIT_FUNC_TRACE();
4209
4210         /* All the link flow control related enable/disable register
4211          * configuration is handle by the F/W
4212          */
4213         err = i40e_set_fc(hw, &aq_failure, true);
4214         if (err < 0)
4215                 return -ENOSYS;
4216
4217         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4218                 /* Configure flow control refresh threshold,
4219                  * the value for stat_tx_pause_refresh_timer[8]
4220                  * is used for global pause operation.
4221                  */
4222
4223                 I40E_WRITE_REG(hw,
4224                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4225                                pf->fc_conf.pause_time);
4226
4227                 /* configure the timer value included in transmitted pause
4228                  * frame,
4229                  * the value for stat_tx_pause_quanta[8] is used for global
4230                  * pause operation
4231                  */
4232                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4233                                pf->fc_conf.pause_time);
4234
4235                 fctrl_reg = I40E_READ_REG(hw,
4236                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4237
4238                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4239                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4240                 else
4241                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4242
4243                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4244                                fctrl_reg);
4245         } else {
4246                 /* Configure pause time (2 TCs per register) */
4247                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4248                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4249                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4250
4251                 /* Configure flow control refresh threshold value */
4252                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4253                                pf->fc_conf.pause_time / 2);
4254
4255                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4256
4257                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4258                  *depending on configuration
4259                  */
4260                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4261                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4262                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4263                 } else {
4264                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4265                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4266                 }
4267
4268                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4269         }
4270
4271         if (!pf->support_multi_driver) {
4272                 /* config water marker both based on the packets and bytes */
4273                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4274                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4275                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4276                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4277                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4278                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4279                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4280                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4281                                   << I40E_KILOSHIFT);
4282                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4283                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4284                                    << I40E_KILOSHIFT);
4285         } else {
4286                 PMD_DRV_LOG(ERR,
4287                             "Water marker configuration is not supported.");
4288         }
4289
4290         I40E_WRITE_FLUSH(hw);
4291
4292         return 0;
4293 }
4294
4295 static int
4296 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4297                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4298 {
4299         PMD_INIT_FUNC_TRACE();
4300
4301         return -ENOSYS;
4302 }
4303
4304 /* Add a MAC address, and update filters */
4305 static int
4306 i40e_macaddr_add(struct rte_eth_dev *dev,
4307                  struct rte_ether_addr *mac_addr,
4308                  __rte_unused uint32_t index,
4309                  uint32_t pool)
4310 {
4311         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4312         struct i40e_mac_filter_info mac_filter;
4313         struct i40e_vsi *vsi;
4314         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4315         int ret;
4316
4317         /* If VMDQ not enabled or configured, return */
4318         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4319                           !pf->nb_cfg_vmdq_vsi)) {
4320                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4321                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4322                         pool);
4323                 return -ENOTSUP;
4324         }
4325
4326         if (pool > pf->nb_cfg_vmdq_vsi) {
4327                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4328                                 pool, pf->nb_cfg_vmdq_vsi);
4329                 return -EINVAL;
4330         }
4331
4332         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4333         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4334                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4335         else
4336                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4337
4338         if (pool == 0)
4339                 vsi = pf->main_vsi;
4340         else
4341                 vsi = pf->vmdq[pool - 1].vsi;
4342
4343         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4344         if (ret != I40E_SUCCESS) {
4345                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4346                 return -ENODEV;
4347         }
4348         return 0;
4349 }
4350
4351 /* Remove a MAC address, and update filters */
4352 static void
4353 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4354 {
4355         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4356         struct i40e_vsi *vsi;
4357         struct rte_eth_dev_data *data = dev->data;
4358         struct rte_ether_addr *macaddr;
4359         int ret;
4360         uint32_t i;
4361         uint64_t pool_sel;
4362
4363         macaddr = &(data->mac_addrs[index]);
4364
4365         pool_sel = dev->data->mac_pool_sel[index];
4366
4367         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4368                 if (pool_sel & (1ULL << i)) {
4369                         if (i == 0)
4370                                 vsi = pf->main_vsi;
4371                         else {
4372                                 /* No VMDQ pool enabled or configured */
4373                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4374                                         (i > pf->nb_cfg_vmdq_vsi)) {
4375                                         PMD_DRV_LOG(ERR,
4376                                                 "No VMDQ pool enabled/configured");
4377                                         return;
4378                                 }
4379                                 vsi = pf->vmdq[i - 1].vsi;
4380                         }
4381                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4382
4383                         if (ret) {
4384                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4385                                 return;
4386                         }
4387                 }
4388         }
4389 }
4390
4391 /* Set perfect match or hash match of MAC and VLAN for a VF */
4392 static int
4393 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4394                  struct rte_eth_mac_filter *filter,
4395                  bool add)
4396 {
4397         struct i40e_hw *hw;
4398         struct i40e_mac_filter_info mac_filter;
4399         struct rte_ether_addr old_mac;
4400         struct rte_ether_addr *new_mac;
4401         struct i40e_pf_vf *vf = NULL;
4402         uint16_t vf_id;
4403         int ret;
4404
4405         if (pf == NULL) {
4406                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4407                 return -EINVAL;
4408         }
4409         hw = I40E_PF_TO_HW(pf);
4410
4411         if (filter == NULL) {
4412                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4413                 return -EINVAL;
4414         }
4415
4416         new_mac = &filter->mac_addr;
4417
4418         if (rte_is_zero_ether_addr(new_mac)) {
4419                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4420                 return -EINVAL;
4421         }
4422
4423         vf_id = filter->dst_id;
4424
4425         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4426                 PMD_DRV_LOG(ERR, "Invalid argument.");
4427                 return -EINVAL;
4428         }
4429         vf = &pf->vfs[vf_id];
4430
4431         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4432                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4433                 return -EINVAL;
4434         }
4435
4436         if (add) {
4437                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4438                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4439                                 RTE_ETHER_ADDR_LEN);
4440                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4441                                  RTE_ETHER_ADDR_LEN);
4442
4443                 mac_filter.filter_type = filter->filter_type;
4444                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4445                 if (ret != I40E_SUCCESS) {
4446                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4447                         return -1;
4448                 }
4449                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4450         } else {
4451                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4452                                 RTE_ETHER_ADDR_LEN);
4453                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4454                 if (ret != I40E_SUCCESS) {
4455                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4456                         return -1;
4457                 }
4458
4459                 /* Clear device address as it has been removed */
4460                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4461                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4462         }
4463
4464         return 0;
4465 }
4466
4467 /* MAC filter handle */
4468 static int
4469 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4470                 void *arg)
4471 {
4472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4473         struct rte_eth_mac_filter *filter;
4474         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4475         int ret = I40E_NOT_SUPPORTED;
4476
4477         filter = (struct rte_eth_mac_filter *)(arg);
4478
4479         switch (filter_op) {
4480         case RTE_ETH_FILTER_NOP:
4481                 ret = I40E_SUCCESS;
4482                 break;
4483         case RTE_ETH_FILTER_ADD:
4484                 i40e_pf_disable_irq0(hw);
4485                 if (filter->is_vf)
4486                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4487                 i40e_pf_enable_irq0(hw);
4488                 break;
4489         case RTE_ETH_FILTER_DELETE:
4490                 i40e_pf_disable_irq0(hw);
4491                 if (filter->is_vf)
4492                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4493                 i40e_pf_enable_irq0(hw);
4494                 break;
4495         default:
4496                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4497                 ret = I40E_ERR_PARAM;
4498                 break;
4499         }
4500
4501         return ret;
4502 }
4503
4504 static int
4505 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4506 {
4507         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4508         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4509         uint32_t reg;
4510         int ret;
4511
4512         if (!lut)
4513                 return -EINVAL;
4514
4515         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4516                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4517                                           vsi->type != I40E_VSI_SRIOV,
4518                                           lut, lut_size);
4519                 if (ret) {
4520                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4521                         return ret;
4522                 }
4523         } else {
4524                 uint32_t *lut_dw = (uint32_t *)lut;
4525                 uint16_t i, lut_size_dw = lut_size / 4;
4526
4527                 if (vsi->type == I40E_VSI_SRIOV) {
4528                         for (i = 0; i <= lut_size_dw; i++) {
4529                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4530                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4531                         }
4532                 } else {
4533                         for (i = 0; i < lut_size_dw; i++)
4534                                 lut_dw[i] = I40E_READ_REG(hw,
4535                                                           I40E_PFQF_HLUT(i));
4536                 }
4537         }
4538
4539         return 0;
4540 }
4541
4542 int
4543 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4544 {
4545         struct i40e_pf *pf;
4546         struct i40e_hw *hw;
4547         int ret;
4548
4549         if (!vsi || !lut)
4550                 return -EINVAL;
4551
4552         pf = I40E_VSI_TO_PF(vsi);
4553         hw = I40E_VSI_TO_HW(vsi);
4554
4555         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4556                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4557                                           vsi->type != I40E_VSI_SRIOV,
4558                                           lut, lut_size);
4559                 if (ret) {
4560                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4561                         return ret;
4562                 }
4563         } else {
4564                 uint32_t *lut_dw = (uint32_t *)lut;
4565                 uint16_t i, lut_size_dw = lut_size / 4;
4566
4567                 if (vsi->type == I40E_VSI_SRIOV) {
4568                         for (i = 0; i < lut_size_dw; i++)
4569                                 I40E_WRITE_REG(
4570                                         hw,
4571                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4572                                         lut_dw[i]);
4573                 } else {
4574                         for (i = 0; i < lut_size_dw; i++)
4575                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4576                                                lut_dw[i]);
4577                 }
4578                 I40E_WRITE_FLUSH(hw);
4579         }
4580
4581         return 0;
4582 }
4583
4584 static int
4585 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4586                          struct rte_eth_rss_reta_entry64 *reta_conf,
4587                          uint16_t reta_size)
4588 {
4589         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4590         uint16_t i, lut_size = pf->hash_lut_size;
4591         uint16_t idx, shift;
4592         uint8_t *lut;
4593         int ret;
4594
4595         if (reta_size != lut_size ||
4596                 reta_size > ETH_RSS_RETA_SIZE_512) {
4597                 PMD_DRV_LOG(ERR,
4598                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4599                         reta_size, lut_size);
4600                 return -EINVAL;
4601         }
4602
4603         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4604         if (!lut) {
4605                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4606                 return -ENOMEM;
4607         }
4608         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4609         if (ret)
4610                 goto out;
4611         for (i = 0; i < reta_size; i++) {
4612                 idx = i / RTE_RETA_GROUP_SIZE;
4613                 shift = i % RTE_RETA_GROUP_SIZE;
4614                 if (reta_conf[idx].mask & (1ULL << shift))
4615                         lut[i] = reta_conf[idx].reta[shift];
4616         }
4617         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4618
4619         pf->adapter->rss_reta_updated = 1;
4620
4621 out:
4622         rte_free(lut);
4623
4624         return ret;
4625 }
4626
4627 static int
4628 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4629                         struct rte_eth_rss_reta_entry64 *reta_conf,
4630                         uint16_t reta_size)
4631 {
4632         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4633         uint16_t i, lut_size = pf->hash_lut_size;
4634         uint16_t idx, shift;
4635         uint8_t *lut;
4636         int ret;
4637
4638         if (reta_size != lut_size ||
4639                 reta_size > ETH_RSS_RETA_SIZE_512) {
4640                 PMD_DRV_LOG(ERR,
4641                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4642                         reta_size, lut_size);
4643                 return -EINVAL;
4644         }
4645
4646         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4647         if (!lut) {
4648                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4649                 return -ENOMEM;
4650         }
4651
4652         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4653         if (ret)
4654                 goto out;
4655         for (i = 0; i < reta_size; i++) {
4656                 idx = i / RTE_RETA_GROUP_SIZE;
4657                 shift = i % RTE_RETA_GROUP_SIZE;
4658                 if (reta_conf[idx].mask & (1ULL << shift))
4659                         reta_conf[idx].reta[shift] = lut[i];
4660         }
4661
4662 out:
4663         rte_free(lut);
4664
4665         return ret;
4666 }
4667
4668 /**
4669  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4670  * @hw:   pointer to the HW structure
4671  * @mem:  pointer to mem struct to fill out
4672  * @size: size of memory requested
4673  * @alignment: what to align the allocation to
4674  **/
4675 enum i40e_status_code
4676 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4677                         struct i40e_dma_mem *mem,
4678                         u64 size,
4679                         u32 alignment)
4680 {
4681         const struct rte_memzone *mz = NULL;
4682         char z_name[RTE_MEMZONE_NAMESIZE];
4683
4684         if (!mem)
4685                 return I40E_ERR_PARAM;
4686
4687         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4688         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4689                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4690         if (!mz)
4691                 return I40E_ERR_NO_MEMORY;
4692
4693         mem->size = size;
4694         mem->va = mz->addr;
4695         mem->pa = mz->iova;
4696         mem->zone = (const void *)mz;
4697         PMD_DRV_LOG(DEBUG,
4698                 "memzone %s allocated with physical address: %"PRIu64,
4699                 mz->name, mem->pa);
4700
4701         return I40E_SUCCESS;
4702 }
4703
4704 /**
4705  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4706  * @hw:   pointer to the HW structure
4707  * @mem:  ptr to mem struct to free
4708  **/
4709 enum i40e_status_code
4710 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4711                     struct i40e_dma_mem *mem)
4712 {
4713         if (!mem)
4714                 return I40E_ERR_PARAM;
4715
4716         PMD_DRV_LOG(DEBUG,
4717                 "memzone %s to be freed with physical address: %"PRIu64,
4718                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4719         rte_memzone_free((const struct rte_memzone *)mem->zone);
4720         mem->zone = NULL;
4721         mem->va = NULL;
4722         mem->pa = (u64)0;
4723
4724         return I40E_SUCCESS;
4725 }
4726
4727 /**
4728  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4729  * @hw:   pointer to the HW structure
4730  * @mem:  pointer to mem struct to fill out
4731  * @size: size of memory requested
4732  **/
4733 enum i40e_status_code
4734 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4735                          struct i40e_virt_mem *mem,
4736                          u32 size)
4737 {
4738         if (!mem)
4739                 return I40E_ERR_PARAM;
4740
4741         mem->size = size;
4742         mem->va = rte_zmalloc("i40e", size, 0);
4743
4744         if (mem->va)
4745                 return I40E_SUCCESS;
4746         else
4747                 return I40E_ERR_NO_MEMORY;
4748 }
4749
4750 /**
4751  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4752  * @hw:   pointer to the HW structure
4753  * @mem:  pointer to mem struct to free
4754  **/
4755 enum i40e_status_code
4756 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4757                      struct i40e_virt_mem *mem)
4758 {
4759         if (!mem)
4760                 return I40E_ERR_PARAM;
4761
4762         rte_free(mem->va);
4763         mem->va = NULL;
4764
4765         return I40E_SUCCESS;
4766 }
4767
4768 void
4769 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4770 {
4771         rte_spinlock_init(&sp->spinlock);
4772 }
4773
4774 void
4775 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4776 {
4777         rte_spinlock_lock(&sp->spinlock);
4778 }
4779
4780 void
4781 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4782 {
4783         rte_spinlock_unlock(&sp->spinlock);
4784 }
4785
4786 void
4787 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4788 {
4789         return;
4790 }
4791
4792 /**
4793  * Get the hardware capabilities, which will be parsed
4794  * and saved into struct i40e_hw.
4795  */
4796 static int
4797 i40e_get_cap(struct i40e_hw *hw)
4798 {
4799         struct i40e_aqc_list_capabilities_element_resp *buf;
4800         uint16_t len, size = 0;
4801         int ret;
4802
4803         /* Calculate a huge enough buff for saving response data temporarily */
4804         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4805                                                 I40E_MAX_CAP_ELE_NUM;
4806         buf = rte_zmalloc("i40e", len, 0);
4807         if (!buf) {
4808                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4809                 return I40E_ERR_NO_MEMORY;
4810         }
4811
4812         /* Get, parse the capabilities and save it to hw */
4813         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4814                         i40e_aqc_opc_list_func_capabilities, NULL);
4815         if (ret != I40E_SUCCESS)
4816                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4817
4818         /* Free the temporary buffer after being used */
4819         rte_free(buf);
4820
4821         return ret;
4822 }
4823
4824 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4825
4826 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4827                 const char *value,
4828                 void *opaque)
4829 {
4830         struct i40e_pf *pf;
4831         unsigned long num;
4832         char *end;
4833
4834         pf = (struct i40e_pf *)opaque;
4835         RTE_SET_USED(key);
4836
4837         errno = 0;
4838         num = strtoul(value, &end, 0);
4839         if (errno != 0 || end == value || *end != 0) {
4840                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4841                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4842                 return -(EINVAL);
4843         }
4844
4845         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4846                 pf->vf_nb_qp_max = (uint16_t)num;
4847         else
4848                 /* here return 0 to make next valid same argument work */
4849                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4850                             "power of 2 and equal or less than 16 !, Now it is "
4851                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4852
4853         return 0;
4854 }
4855
4856 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4857 {
4858         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4859         struct rte_kvargs *kvlist;
4860         int kvargs_count;
4861
4862         /* set default queue number per VF as 4 */
4863         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4864
4865         if (dev->device->devargs == NULL)
4866                 return 0;
4867
4868         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4869         if (kvlist == NULL)
4870                 return -(EINVAL);
4871
4872         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4873         if (!kvargs_count) {
4874                 rte_kvargs_free(kvlist);
4875                 return 0;
4876         }
4877
4878         if (kvargs_count > 1)
4879                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4880                             "the first invalid or last valid one is used !",
4881                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4882
4883         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4884                            i40e_pf_parse_vf_queue_number_handler, pf);
4885
4886         rte_kvargs_free(kvlist);
4887
4888         return 0;
4889 }
4890
4891 static int
4892 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4893 {
4894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4895         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4896         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4897         uint16_t qp_count = 0, vsi_count = 0;
4898
4899         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4900                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4901                 return -EINVAL;
4902         }
4903
4904         i40e_pf_config_vf_rxq_number(dev);
4905
4906         /* Add the parameter init for LFC */
4907         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4908         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4909         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4910
4911         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4912         pf->max_num_vsi = hw->func_caps.num_vsis;
4913         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4914         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4915
4916         /* FDir queue/VSI allocation */
4917         pf->fdir_qp_offset = 0;
4918         if (hw->func_caps.fd) {
4919                 pf->flags |= I40E_FLAG_FDIR;
4920                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4921         } else {
4922                 pf->fdir_nb_qps = 0;
4923         }
4924         qp_count += pf->fdir_nb_qps;
4925         vsi_count += 1;
4926
4927         /* LAN queue/VSI allocation */
4928         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4929         if (!hw->func_caps.rss) {
4930                 pf->lan_nb_qps = 1;
4931         } else {
4932                 pf->flags |= I40E_FLAG_RSS;
4933                 if (hw->mac.type == I40E_MAC_X722)
4934                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4935                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4936         }
4937         qp_count += pf->lan_nb_qps;
4938         vsi_count += 1;
4939
4940         /* VF queue/VSI allocation */
4941         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4942         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4943                 pf->flags |= I40E_FLAG_SRIOV;
4944                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4945                 pf->vf_num = pci_dev->max_vfs;
4946                 PMD_DRV_LOG(DEBUG,
4947                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4948                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4949         } else {
4950                 pf->vf_nb_qps = 0;
4951                 pf->vf_num = 0;
4952         }
4953         qp_count += pf->vf_nb_qps * pf->vf_num;
4954         vsi_count += pf->vf_num;
4955
4956         /* VMDq queue/VSI allocation */
4957         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4958         pf->vmdq_nb_qps = 0;
4959         pf->max_nb_vmdq_vsi = 0;
4960         if (hw->func_caps.vmdq) {
4961                 if (qp_count < hw->func_caps.num_tx_qp &&
4962                         vsi_count < hw->func_caps.num_vsis) {
4963                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4964                                 qp_count) / pf->vmdq_nb_qp_max;
4965
4966                         /* Limit the maximum number of VMDq vsi to the maximum
4967                          * ethdev can support
4968                          */
4969                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4970                                 hw->func_caps.num_vsis - vsi_count);
4971                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4972                                 ETH_64_POOLS);
4973                         if (pf->max_nb_vmdq_vsi) {
4974                                 pf->flags |= I40E_FLAG_VMDQ;
4975                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4976                                 PMD_DRV_LOG(DEBUG,
4977                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4978                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4979                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4980                         } else {
4981                                 PMD_DRV_LOG(INFO,
4982                                         "No enough queues left for VMDq");
4983                         }
4984                 } else {
4985                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4986                 }
4987         }
4988         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4989         vsi_count += pf->max_nb_vmdq_vsi;
4990
4991         if (hw->func_caps.dcb)
4992                 pf->flags |= I40E_FLAG_DCB;
4993
4994         if (qp_count > hw->func_caps.num_tx_qp) {
4995                 PMD_DRV_LOG(ERR,
4996                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4997                         qp_count, hw->func_caps.num_tx_qp);
4998                 return -EINVAL;
4999         }
5000         if (vsi_count > hw->func_caps.num_vsis) {
5001                 PMD_DRV_LOG(ERR,
5002                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
5003                         vsi_count, hw->func_caps.num_vsis);
5004                 return -EINVAL;
5005         }
5006
5007         return 0;
5008 }
5009
5010 static int
5011 i40e_pf_get_switch_config(struct i40e_pf *pf)
5012 {
5013         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5014         struct i40e_aqc_get_switch_config_resp *switch_config;
5015         struct i40e_aqc_switch_config_element_resp *element;
5016         uint16_t start_seid = 0, num_reported;
5017         int ret;
5018
5019         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
5020                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
5021         if (!switch_config) {
5022                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
5023                 return -ENOMEM;
5024         }
5025
5026         /* Get the switch configurations */
5027         ret = i40e_aq_get_switch_config(hw, switch_config,
5028                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
5029         if (ret != I40E_SUCCESS) {
5030                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
5031                 goto fail;
5032         }
5033         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
5034         if (num_reported != 1) { /* The number should be 1 */
5035                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
5036                 goto fail;
5037         }
5038
5039         /* Parse the switch configuration elements */
5040         element = &(switch_config->element[0]);
5041         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
5042                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
5043                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
5044         } else
5045                 PMD_DRV_LOG(INFO, "Unknown element type");
5046
5047 fail:
5048         rte_free(switch_config);
5049
5050         return ret;
5051 }
5052
5053 static int
5054 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
5055                         uint32_t num)
5056 {
5057         struct pool_entry *entry;
5058
5059         if (pool == NULL || num == 0)
5060                 return -EINVAL;
5061
5062         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
5063         if (entry == NULL) {
5064                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
5065                 return -ENOMEM;
5066         }
5067
5068         /* queue heap initialize */
5069         pool->num_free = num;
5070         pool->num_alloc = 0;
5071         pool->base = base;
5072         LIST_INIT(&pool->alloc_list);
5073         LIST_INIT(&pool->free_list);
5074
5075         /* Initialize element  */
5076         entry->base = 0;
5077         entry->len = num;
5078
5079         LIST_INSERT_HEAD(&pool->free_list, entry, next);
5080         return 0;
5081 }
5082
5083 static void
5084 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5085 {
5086         struct pool_entry *entry, *next_entry;
5087
5088         if (pool == NULL)
5089                 return;
5090
5091         for (entry = LIST_FIRST(&pool->alloc_list);
5092                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5093                         entry = next_entry) {
5094                 LIST_REMOVE(entry, next);
5095                 rte_free(entry);
5096         }
5097
5098         for (entry = LIST_FIRST(&pool->free_list);
5099                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5100                         entry = next_entry) {
5101                 LIST_REMOVE(entry, next);
5102                 rte_free(entry);
5103         }
5104
5105         pool->num_free = 0;
5106         pool->num_alloc = 0;
5107         pool->base = 0;
5108         LIST_INIT(&pool->alloc_list);
5109         LIST_INIT(&pool->free_list);
5110 }
5111
5112 static int
5113 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5114                        uint32_t base)
5115 {
5116         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5117         uint32_t pool_offset;
5118         uint16_t len;
5119         int insert;
5120
5121         if (pool == NULL) {
5122                 PMD_DRV_LOG(ERR, "Invalid parameter");
5123                 return -EINVAL;
5124         }
5125
5126         pool_offset = base - pool->base;
5127         /* Lookup in alloc list */
5128         LIST_FOREACH(entry, &pool->alloc_list, next) {
5129                 if (entry->base == pool_offset) {
5130                         valid_entry = entry;
5131                         LIST_REMOVE(entry, next);
5132                         break;
5133                 }
5134         }
5135
5136         /* Not find, return */
5137         if (valid_entry == NULL) {
5138                 PMD_DRV_LOG(ERR, "Failed to find entry");
5139                 return -EINVAL;
5140         }
5141
5142         /**
5143          * Found it, move it to free list  and try to merge.
5144          * In order to make merge easier, always sort it by qbase.
5145          * Find adjacent prev and last entries.
5146          */
5147         prev = next = NULL;
5148         LIST_FOREACH(entry, &pool->free_list, next) {
5149                 if (entry->base > valid_entry->base) {
5150                         next = entry;
5151                         break;
5152                 }
5153                 prev = entry;
5154         }
5155
5156         insert = 0;
5157         len = valid_entry->len;
5158         /* Try to merge with next one*/
5159         if (next != NULL) {
5160                 /* Merge with next one */
5161                 if (valid_entry->base + len == next->base) {
5162                         next->base = valid_entry->base;
5163                         next->len += len;
5164                         rte_free(valid_entry);
5165                         valid_entry = next;
5166                         insert = 1;
5167                 }
5168         }
5169
5170         if (prev != NULL) {
5171                 /* Merge with previous one */
5172                 if (prev->base + prev->len == valid_entry->base) {
5173                         prev->len += len;
5174                         /* If it merge with next one, remove next node */
5175                         if (insert == 1) {
5176                                 LIST_REMOVE(valid_entry, next);
5177                                 rte_free(valid_entry);
5178                                 valid_entry = NULL;
5179                         } else {
5180                                 rte_free(valid_entry);
5181                                 valid_entry = NULL;
5182                                 insert = 1;
5183                         }
5184                 }
5185         }
5186
5187         /* Not find any entry to merge, insert */
5188         if (insert == 0) {
5189                 if (prev != NULL)
5190                         LIST_INSERT_AFTER(prev, valid_entry, next);
5191                 else if (next != NULL)
5192                         LIST_INSERT_BEFORE(next, valid_entry, next);
5193                 else /* It's empty list, insert to head */
5194                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5195         }
5196
5197         pool->num_free += len;
5198         pool->num_alloc -= len;
5199
5200         return 0;
5201 }
5202
5203 static int
5204 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5205                        uint16_t num)
5206 {
5207         struct pool_entry *entry, *valid_entry;
5208
5209         if (pool == NULL || num == 0) {
5210                 PMD_DRV_LOG(ERR, "Invalid parameter");
5211                 return -EINVAL;
5212         }
5213
5214         if (pool->num_free < num) {
5215                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5216                             num, pool->num_free);
5217                 return -ENOMEM;
5218         }
5219
5220         valid_entry = NULL;
5221         /* Lookup  in free list and find most fit one */
5222         LIST_FOREACH(entry, &pool->free_list, next) {
5223                 if (entry->len >= num) {
5224                         /* Find best one */
5225                         if (entry->len == num) {
5226                                 valid_entry = entry;
5227                                 break;
5228                         }
5229                         if (valid_entry == NULL || valid_entry->len > entry->len)
5230                                 valid_entry = entry;
5231                 }
5232         }
5233
5234         /* Not find one to satisfy the request, return */
5235         if (valid_entry == NULL) {
5236                 PMD_DRV_LOG(ERR, "No valid entry found");
5237                 return -ENOMEM;
5238         }
5239         /**
5240          * The entry have equal queue number as requested,
5241          * remove it from alloc_list.
5242          */
5243         if (valid_entry->len == num) {
5244                 LIST_REMOVE(valid_entry, next);
5245         } else {
5246                 /**
5247                  * The entry have more numbers than requested,
5248                  * create a new entry for alloc_list and minus its
5249                  * queue base and number in free_list.
5250                  */
5251                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5252                 if (entry == NULL) {
5253                         PMD_DRV_LOG(ERR,
5254                                 "Failed to allocate memory for resource pool");
5255                         return -ENOMEM;
5256                 }
5257                 entry->base = valid_entry->base;
5258                 entry->len = num;
5259                 valid_entry->base += num;
5260                 valid_entry->len -= num;
5261                 valid_entry = entry;
5262         }
5263
5264         /* Insert it into alloc list, not sorted */
5265         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5266
5267         pool->num_free -= valid_entry->len;
5268         pool->num_alloc += valid_entry->len;
5269
5270         return valid_entry->base + pool->base;
5271 }
5272
5273 /**
5274  * bitmap_is_subset - Check whether src2 is subset of src1
5275  **/
5276 static inline int
5277 bitmap_is_subset(uint8_t src1, uint8_t src2)
5278 {
5279         return !((src1 ^ src2) & src2);
5280 }
5281
5282 static enum i40e_status_code
5283 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5284 {
5285         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5286
5287         /* If DCB is not supported, only default TC is supported */
5288         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5289                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5290                 return I40E_NOT_SUPPORTED;
5291         }
5292
5293         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5294                 PMD_DRV_LOG(ERR,
5295                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5296                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5297                 return I40E_NOT_SUPPORTED;
5298         }
5299         return I40E_SUCCESS;
5300 }
5301
5302 int
5303 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5304                                 struct i40e_vsi_vlan_pvid_info *info)
5305 {
5306         struct i40e_hw *hw;
5307         struct i40e_vsi_context ctxt;
5308         uint8_t vlan_flags = 0;
5309         int ret;
5310
5311         if (vsi == NULL || info == NULL) {
5312                 PMD_DRV_LOG(ERR, "invalid parameters");
5313                 return I40E_ERR_PARAM;
5314         }
5315
5316         if (info->on) {
5317                 vsi->info.pvid = info->config.pvid;
5318                 /**
5319                  * If insert pvid is enabled, only tagged pkts are
5320                  * allowed to be sent out.
5321                  */
5322                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5323                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5324         } else {
5325                 vsi->info.pvid = 0;
5326                 if (info->config.reject.tagged == 0)
5327                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5328
5329                 if (info->config.reject.untagged == 0)
5330                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5331         }
5332         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5333                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5334         vsi->info.port_vlan_flags |= vlan_flags;
5335         vsi->info.valid_sections =
5336                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5337         memset(&ctxt, 0, sizeof(ctxt));
5338         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5339         ctxt.seid = vsi->seid;
5340
5341         hw = I40E_VSI_TO_HW(vsi);
5342         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5343         if (ret != I40E_SUCCESS)
5344                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5345
5346         return ret;
5347 }
5348
5349 static int
5350 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5351 {
5352         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5353         int i, ret;
5354         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5355
5356         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5357         if (ret != I40E_SUCCESS)
5358                 return ret;
5359
5360         if (!vsi->seid) {
5361                 PMD_DRV_LOG(ERR, "seid not valid");
5362                 return -EINVAL;
5363         }
5364
5365         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5366         tc_bw_data.tc_valid_bits = enabled_tcmap;
5367         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5368                 tc_bw_data.tc_bw_credits[i] =
5369                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5370
5371         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5372         if (ret != I40E_SUCCESS) {
5373                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5374                 return ret;
5375         }
5376
5377         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5378                                         sizeof(vsi->info.qs_handle));
5379         return I40E_SUCCESS;
5380 }
5381
5382 static enum i40e_status_code
5383 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5384                                  struct i40e_aqc_vsi_properties_data *info,
5385                                  uint8_t enabled_tcmap)
5386 {
5387         enum i40e_status_code ret;
5388         int i, total_tc = 0;
5389         uint16_t qpnum_per_tc, bsf, qp_idx;
5390
5391         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5392         if (ret != I40E_SUCCESS)
5393                 return ret;
5394
5395         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5396                 if (enabled_tcmap & (1 << i))
5397                         total_tc++;
5398         if (total_tc == 0)
5399                 total_tc = 1;
5400         vsi->enabled_tc = enabled_tcmap;
5401
5402         /* Number of queues per enabled TC */
5403         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5404         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5405         bsf = rte_bsf32(qpnum_per_tc);
5406
5407         /* Adjust the queue number to actual queues that can be applied */
5408         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5409                 vsi->nb_qps = qpnum_per_tc * total_tc;
5410
5411         /**
5412          * Configure TC and queue mapping parameters, for enabled TC,
5413          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5414          * default queue will serve it.
5415          */
5416         qp_idx = 0;
5417         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5418                 if (vsi->enabled_tc & (1 << i)) {
5419                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5420                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5421                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5422                         qp_idx += qpnum_per_tc;
5423                 } else
5424                         info->tc_mapping[i] = 0;
5425         }
5426
5427         /* Associate queue number with VSI */
5428         if (vsi->type == I40E_VSI_SRIOV) {
5429                 info->mapping_flags |=
5430                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5431                 for (i = 0; i < vsi->nb_qps; i++)
5432                         info->queue_mapping[i] =
5433                                 rte_cpu_to_le_16(vsi->base_queue + i);
5434         } else {
5435                 info->mapping_flags |=
5436                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5437                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5438         }
5439         info->valid_sections |=
5440                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5441
5442         return I40E_SUCCESS;
5443 }
5444
5445 static int
5446 i40e_veb_release(struct i40e_veb *veb)
5447 {
5448         struct i40e_vsi *vsi;
5449         struct i40e_hw *hw;
5450
5451         if (veb == NULL)
5452                 return -EINVAL;
5453
5454         if (!TAILQ_EMPTY(&veb->head)) {
5455                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5456                 return -EACCES;
5457         }
5458         /* associate_vsi field is NULL for floating VEB */
5459         if (veb->associate_vsi != NULL) {
5460                 vsi = veb->associate_vsi;
5461                 hw = I40E_VSI_TO_HW(vsi);
5462
5463                 vsi->uplink_seid = veb->uplink_seid;
5464                 vsi->veb = NULL;
5465         } else {
5466                 veb->associate_pf->main_vsi->floating_veb = NULL;
5467                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5468         }
5469
5470         i40e_aq_delete_element(hw, veb->seid, NULL);
5471         rte_free(veb);
5472         return I40E_SUCCESS;
5473 }
5474
5475 /* Setup a veb */
5476 static struct i40e_veb *
5477 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5478 {
5479         struct i40e_veb *veb;
5480         int ret;
5481         struct i40e_hw *hw;
5482
5483         if (pf == NULL) {
5484                 PMD_DRV_LOG(ERR,
5485                             "veb setup failed, associated PF shouldn't null");
5486                 return NULL;
5487         }
5488         hw = I40E_PF_TO_HW(pf);
5489
5490         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5491         if (!veb) {
5492                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5493                 goto fail;
5494         }
5495
5496         veb->associate_vsi = vsi;
5497         veb->associate_pf = pf;
5498         TAILQ_INIT(&veb->head);
5499         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5500
5501         /* create floating veb if vsi is NULL */
5502         if (vsi != NULL) {
5503                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5504                                       I40E_DEFAULT_TCMAP, false,
5505                                       &veb->seid, false, NULL);
5506         } else {
5507                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5508                                       true, &veb->seid, false, NULL);
5509         }
5510
5511         if (ret != I40E_SUCCESS) {
5512                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5513                             hw->aq.asq_last_status);
5514                 goto fail;
5515         }
5516         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5517
5518         /* get statistics index */
5519         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5520                                 &veb->stats_idx, NULL, NULL, NULL);
5521         if (ret != I40E_SUCCESS) {
5522                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5523                             hw->aq.asq_last_status);
5524                 goto fail;
5525         }
5526         /* Get VEB bandwidth, to be implemented */
5527         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5528         if (vsi)
5529                 vsi->uplink_seid = veb->seid;
5530
5531         return veb;
5532 fail:
5533         rte_free(veb);
5534         return NULL;
5535 }
5536
5537 int
5538 i40e_vsi_release(struct i40e_vsi *vsi)
5539 {
5540         struct i40e_pf *pf;
5541         struct i40e_hw *hw;
5542         struct i40e_vsi_list *vsi_list;
5543         void *temp;
5544         int ret;
5545         struct i40e_mac_filter *f;
5546         uint16_t user_param;
5547
5548         if (!vsi)
5549                 return I40E_SUCCESS;
5550
5551         if (!vsi->adapter)
5552                 return -EFAULT;
5553
5554         user_param = vsi->user_param;
5555
5556         pf = I40E_VSI_TO_PF(vsi);
5557         hw = I40E_VSI_TO_HW(vsi);
5558
5559         /* VSI has child to attach, release child first */
5560         if (vsi->veb) {
5561                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5562                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5563                                 return -1;
5564                 }
5565                 i40e_veb_release(vsi->veb);
5566         }
5567
5568         if (vsi->floating_veb) {
5569                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5570                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5571                                 return -1;
5572                 }
5573         }
5574
5575         /* Remove all macvlan filters of the VSI */
5576         i40e_vsi_remove_all_macvlan_filter(vsi);
5577         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5578                 rte_free(f);
5579
5580         if (vsi->type != I40E_VSI_MAIN &&
5581             ((vsi->type != I40E_VSI_SRIOV) ||
5582             !pf->floating_veb_list[user_param])) {
5583                 /* Remove vsi from parent's sibling list */
5584                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5585                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5586                         return I40E_ERR_PARAM;
5587                 }
5588                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5589                                 &vsi->sib_vsi_list, list);
5590
5591                 /* Remove all switch element of the VSI */
5592                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5593                 if (ret != I40E_SUCCESS)
5594                         PMD_DRV_LOG(ERR, "Failed to delete element");
5595         }
5596
5597         if ((vsi->type == I40E_VSI_SRIOV) &&
5598             pf->floating_veb_list[user_param]) {
5599                 /* Remove vsi from parent's sibling list */
5600                 if (vsi->parent_vsi == NULL ||
5601                     vsi->parent_vsi->floating_veb == NULL) {
5602                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5603                         return I40E_ERR_PARAM;
5604                 }
5605                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5606                              &vsi->sib_vsi_list, list);
5607
5608                 /* Remove all switch element of the VSI */
5609                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5610                 if (ret != I40E_SUCCESS)
5611                         PMD_DRV_LOG(ERR, "Failed to delete element");
5612         }
5613
5614         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5615
5616         if (vsi->type != I40E_VSI_SRIOV)
5617                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5618         rte_free(vsi);
5619
5620         return I40E_SUCCESS;
5621 }
5622
5623 static int
5624 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5625 {
5626         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5627         struct i40e_aqc_remove_macvlan_element_data def_filter;
5628         struct i40e_mac_filter_info filter;
5629         int ret;
5630
5631         if (vsi->type != I40E_VSI_MAIN)
5632                 return I40E_ERR_CONFIG;
5633         memset(&def_filter, 0, sizeof(def_filter));
5634         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5635                                         ETH_ADDR_LEN);
5636         def_filter.vlan_tag = 0;
5637         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5638                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5639         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5640         if (ret != I40E_SUCCESS) {
5641                 struct i40e_mac_filter *f;
5642                 struct rte_ether_addr *mac;
5643
5644                 PMD_DRV_LOG(DEBUG,
5645                             "Cannot remove the default macvlan filter");
5646                 /* It needs to add the permanent mac into mac list */
5647                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5648                 if (f == NULL) {
5649                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5650                         return I40E_ERR_NO_MEMORY;
5651                 }
5652                 mac = &f->mac_info.mac_addr;
5653                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5654                                 ETH_ADDR_LEN);
5655                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5656                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5657                 vsi->mac_num++;
5658
5659                 return ret;
5660         }
5661         rte_memcpy(&filter.mac_addr,
5662                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5663         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5664         return i40e_vsi_add_mac(vsi, &filter);
5665 }
5666
5667 /*
5668  * i40e_vsi_get_bw_config - Query VSI BW Information
5669  * @vsi: the VSI to be queried
5670  *
5671  * Returns 0 on success, negative value on failure
5672  */
5673 static enum i40e_status_code
5674 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5675 {
5676         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5677         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5678         struct i40e_hw *hw = &vsi->adapter->hw;
5679         i40e_status ret;
5680         int i;
5681         uint32_t bw_max;
5682
5683         memset(&bw_config, 0, sizeof(bw_config));
5684         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5685         if (ret != I40E_SUCCESS) {
5686                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5687                             hw->aq.asq_last_status);
5688                 return ret;
5689         }
5690
5691         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5692         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5693                                         &ets_sla_config, NULL);
5694         if (ret != I40E_SUCCESS) {
5695                 PMD_DRV_LOG(ERR,
5696                         "VSI failed to get TC bandwdith configuration %u",
5697                         hw->aq.asq_last_status);
5698                 return ret;
5699         }
5700
5701         /* store and print out BW info */
5702         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5703         vsi->bw_info.bw_max = bw_config.max_bw;
5704         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5705         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5706         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5707                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5708                      I40E_16_BIT_WIDTH);
5709         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5710                 vsi->bw_info.bw_ets_share_credits[i] =
5711                                 ets_sla_config.share_credits[i];
5712                 vsi->bw_info.bw_ets_credits[i] =
5713                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5714                 /* 4 bits per TC, 4th bit is reserved */
5715                 vsi->bw_info.bw_ets_max[i] =
5716                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5717                                   RTE_LEN2MASK(3, uint8_t));
5718                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5719                             vsi->bw_info.bw_ets_share_credits[i]);
5720                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5721                             vsi->bw_info.bw_ets_credits[i]);
5722                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5723                             vsi->bw_info.bw_ets_max[i]);
5724         }
5725
5726         return I40E_SUCCESS;
5727 }
5728
5729 /* i40e_enable_pf_lb
5730  * @pf: pointer to the pf structure
5731  *
5732  * allow loopback on pf
5733  */
5734 static inline void
5735 i40e_enable_pf_lb(struct i40e_pf *pf)
5736 {
5737         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5738         struct i40e_vsi_context ctxt;
5739         int ret;
5740
5741         /* Use the FW API if FW >= v5.0 */
5742         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5743                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5744                 return;
5745         }
5746
5747         memset(&ctxt, 0, sizeof(ctxt));
5748         ctxt.seid = pf->main_vsi_seid;
5749         ctxt.pf_num = hw->pf_id;
5750         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5751         if (ret) {
5752                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5753                             ret, hw->aq.asq_last_status);
5754                 return;
5755         }
5756         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5757         ctxt.info.valid_sections =
5758                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5759         ctxt.info.switch_id |=
5760                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5761
5762         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5763         if (ret)
5764                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5765                             hw->aq.asq_last_status);
5766 }
5767
5768 /* Setup a VSI */
5769 struct i40e_vsi *
5770 i40e_vsi_setup(struct i40e_pf *pf,
5771                enum i40e_vsi_type type,
5772                struct i40e_vsi *uplink_vsi,
5773                uint16_t user_param)
5774 {
5775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5776         struct i40e_vsi *vsi;
5777         struct i40e_mac_filter_info filter;
5778         int ret;
5779         struct i40e_vsi_context ctxt;
5780         struct rte_ether_addr broadcast =
5781                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5782
5783         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5784             uplink_vsi == NULL) {
5785                 PMD_DRV_LOG(ERR,
5786                         "VSI setup failed, VSI link shouldn't be NULL");
5787                 return NULL;
5788         }
5789
5790         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5791                 PMD_DRV_LOG(ERR,
5792                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5793                 return NULL;
5794         }
5795
5796         /* two situations
5797          * 1.type is not MAIN and uplink vsi is not NULL
5798          * If uplink vsi didn't setup VEB, create one first under veb field
5799          * 2.type is SRIOV and the uplink is NULL
5800          * If floating VEB is NULL, create one veb under floating veb field
5801          */
5802
5803         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5804             uplink_vsi->veb == NULL) {
5805                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5806
5807                 if (uplink_vsi->veb == NULL) {
5808                         PMD_DRV_LOG(ERR, "VEB setup failed");
5809                         return NULL;
5810                 }
5811                 /* set ALLOWLOOPBACk on pf, when veb is created */
5812                 i40e_enable_pf_lb(pf);
5813         }
5814
5815         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5816             pf->main_vsi->floating_veb == NULL) {
5817                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5818
5819                 if (pf->main_vsi->floating_veb == NULL) {
5820                         PMD_DRV_LOG(ERR, "VEB setup failed");
5821                         return NULL;
5822                 }
5823         }
5824
5825         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5826         if (!vsi) {
5827                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5828                 return NULL;
5829         }
5830         TAILQ_INIT(&vsi->mac_list);
5831         vsi->type = type;
5832         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5833         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5834         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5835         vsi->user_param = user_param;
5836         vsi->vlan_anti_spoof_on = 0;
5837         vsi->vlan_filter_on = 0;
5838         /* Allocate queues */
5839         switch (vsi->type) {
5840         case I40E_VSI_MAIN  :
5841                 vsi->nb_qps = pf->lan_nb_qps;
5842                 break;
5843         case I40E_VSI_SRIOV :
5844                 vsi->nb_qps = pf->vf_nb_qps;
5845                 break;
5846         case I40E_VSI_VMDQ2:
5847                 vsi->nb_qps = pf->vmdq_nb_qps;
5848                 break;
5849         case I40E_VSI_FDIR:
5850                 vsi->nb_qps = pf->fdir_nb_qps;
5851                 break;
5852         default:
5853                 goto fail_mem;
5854         }
5855         /*
5856          * The filter status descriptor is reported in rx queue 0,
5857          * while the tx queue for fdir filter programming has no
5858          * such constraints, can be non-zero queues.
5859          * To simplify it, choose FDIR vsi use queue 0 pair.
5860          * To make sure it will use queue 0 pair, queue allocation
5861          * need be done before this function is called
5862          */
5863         if (type != I40E_VSI_FDIR) {
5864                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5865                         if (ret < 0) {
5866                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5867                                                 vsi->seid, ret);
5868                                 goto fail_mem;
5869                         }
5870                         vsi->base_queue = ret;
5871         } else
5872                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5873
5874         /* VF has MSIX interrupt in VF range, don't allocate here */
5875         if (type == I40E_VSI_MAIN) {
5876                 if (pf->support_multi_driver) {
5877                         /* If support multi-driver, need to use INT0 instead of
5878                          * allocating from msix pool. The Msix pool is init from
5879                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5880                          * to 1 without calling i40e_res_pool_alloc.
5881                          */
5882                         vsi->msix_intr = 0;
5883                         vsi->nb_msix = 1;
5884                 } else {
5885                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5886                                                   RTE_MIN(vsi->nb_qps,
5887                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5888                         if (ret < 0) {
5889                                 PMD_DRV_LOG(ERR,
5890                                             "VSI MAIN %d get heap failed %d",
5891                                             vsi->seid, ret);
5892                                 goto fail_queue_alloc;
5893                         }
5894                         vsi->msix_intr = ret;
5895                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5896                                                RTE_MAX_RXTX_INTR_VEC_ID);
5897                 }
5898         } else if (type != I40E_VSI_SRIOV) {
5899                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5900                 if (ret < 0) {
5901                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5902                         if (type != I40E_VSI_FDIR)
5903                                 goto fail_queue_alloc;
5904                         vsi->msix_intr = 0;
5905                         vsi->nb_msix = 0;
5906                 } else {
5907                         vsi->msix_intr = ret;
5908                         vsi->nb_msix = 1;
5909                 }
5910         } else {
5911                 vsi->msix_intr = 0;
5912                 vsi->nb_msix = 0;
5913         }
5914
5915         /* Add VSI */
5916         if (type == I40E_VSI_MAIN) {
5917                 /* For main VSI, no need to add since it's default one */
5918                 vsi->uplink_seid = pf->mac_seid;
5919                 vsi->seid = pf->main_vsi_seid;
5920                 /* Bind queues with specific MSIX interrupt */
5921                 /**
5922                  * Needs 2 interrupt at least, one for misc cause which will
5923                  * enabled from OS side, Another for queues binding the
5924                  * interrupt from device side only.
5925                  */
5926
5927                 /* Get default VSI parameters from hardware */
5928                 memset(&ctxt, 0, sizeof(ctxt));
5929                 ctxt.seid = vsi->seid;
5930                 ctxt.pf_num = hw->pf_id;
5931                 ctxt.uplink_seid = vsi->uplink_seid;
5932                 ctxt.vf_num = 0;
5933                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5934                 if (ret != I40E_SUCCESS) {
5935                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5936                         goto fail_msix_alloc;
5937                 }
5938                 rte_memcpy(&vsi->info, &ctxt.info,
5939                         sizeof(struct i40e_aqc_vsi_properties_data));
5940                 vsi->vsi_id = ctxt.vsi_number;
5941                 vsi->info.valid_sections = 0;
5942
5943                 /* Configure tc, enabled TC0 only */
5944                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5945                         I40E_SUCCESS) {
5946                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5947                         goto fail_msix_alloc;
5948                 }
5949
5950                 /* TC, queue mapping */
5951                 memset(&ctxt, 0, sizeof(ctxt));
5952                 vsi->info.valid_sections |=
5953                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5954                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5955                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5956                 rte_memcpy(&ctxt.info, &vsi->info,
5957                         sizeof(struct i40e_aqc_vsi_properties_data));
5958                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5959                                                 I40E_DEFAULT_TCMAP);
5960                 if (ret != I40E_SUCCESS) {
5961                         PMD_DRV_LOG(ERR,
5962                                 "Failed to configure TC queue mapping");
5963                         goto fail_msix_alloc;
5964                 }
5965                 ctxt.seid = vsi->seid;
5966                 ctxt.pf_num = hw->pf_id;
5967                 ctxt.uplink_seid = vsi->uplink_seid;
5968                 ctxt.vf_num = 0;
5969
5970                 /* Update VSI parameters */
5971                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5972                 if (ret != I40E_SUCCESS) {
5973                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5974                         goto fail_msix_alloc;
5975                 }
5976
5977                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5978                                                 sizeof(vsi->info.tc_mapping));
5979                 rte_memcpy(&vsi->info.queue_mapping,
5980                                 &ctxt.info.queue_mapping,
5981                         sizeof(vsi->info.queue_mapping));
5982                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5983                 vsi->info.valid_sections = 0;
5984
5985                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5986                                 ETH_ADDR_LEN);
5987
5988                 /**
5989                  * Updating default filter settings are necessary to prevent
5990                  * reception of tagged packets.
5991                  * Some old firmware configurations load a default macvlan
5992                  * filter which accepts both tagged and untagged packets.
5993                  * The updating is to use a normal filter instead if needed.
5994                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5995                  * The firmware with correct configurations load the default
5996                  * macvlan filter which is expected and cannot be removed.
5997                  */
5998                 i40e_update_default_filter_setting(vsi);
5999                 i40e_config_qinq(hw, vsi);
6000         } else if (type == I40E_VSI_SRIOV) {
6001                 memset(&ctxt, 0, sizeof(ctxt));
6002                 /**
6003                  * For other VSI, the uplink_seid equals to uplink VSI's
6004                  * uplink_seid since they share same VEB
6005                  */
6006                 if (uplink_vsi == NULL)
6007                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
6008                 else
6009                         vsi->uplink_seid = uplink_vsi->uplink_seid;
6010                 ctxt.pf_num = hw->pf_id;
6011                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
6012                 ctxt.uplink_seid = vsi->uplink_seid;
6013                 ctxt.connection_type = 0x1;
6014                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6015
6016                 /* Use the VEB configuration if FW >= v5.0 */
6017                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
6018                         /* Configure switch ID */
6019                         ctxt.info.valid_sections |=
6020                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6021                         ctxt.info.switch_id =
6022                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6023                 }
6024
6025                 /* Configure port/vlan */
6026                 ctxt.info.valid_sections |=
6027                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6028                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6029                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6030                                                 hw->func_caps.enabled_tcmap);
6031                 if (ret != I40E_SUCCESS) {
6032                         PMD_DRV_LOG(ERR,
6033                                 "Failed to configure TC queue mapping");
6034                         goto fail_msix_alloc;
6035                 }
6036
6037                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
6038                 ctxt.info.valid_sections |=
6039                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6040                 /**
6041                  * Since VSI is not created yet, only configure parameter,
6042                  * will add vsi below.
6043                  */
6044
6045                 i40e_config_qinq(hw, vsi);
6046         } else if (type == I40E_VSI_VMDQ2) {
6047                 memset(&ctxt, 0, sizeof(ctxt));
6048                 /*
6049                  * For other VSI, the uplink_seid equals to uplink VSI's
6050                  * uplink_seid since they share same VEB
6051                  */
6052                 vsi->uplink_seid = uplink_vsi->uplink_seid;
6053                 ctxt.pf_num = hw->pf_id;
6054                 ctxt.vf_num = 0;
6055                 ctxt.uplink_seid = vsi->uplink_seid;
6056                 ctxt.connection_type = 0x1;
6057                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6058
6059                 ctxt.info.valid_sections |=
6060                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6061                 /* user_param carries flag to enable loop back */
6062                 if (user_param) {
6063                         ctxt.info.switch_id =
6064                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6065                         ctxt.info.switch_id |=
6066                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6067                 }
6068
6069                 /* Configure port/vlan */
6070                 ctxt.info.valid_sections |=
6071                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6072                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6073                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6074                                                 I40E_DEFAULT_TCMAP);
6075                 if (ret != I40E_SUCCESS) {
6076                         PMD_DRV_LOG(ERR,
6077                                 "Failed to configure TC queue mapping");
6078                         goto fail_msix_alloc;
6079                 }
6080                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6081                 ctxt.info.valid_sections |=
6082                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6083         } else if (type == I40E_VSI_FDIR) {
6084                 memset(&ctxt, 0, sizeof(ctxt));
6085                 vsi->uplink_seid = uplink_vsi->uplink_seid;
6086                 ctxt.pf_num = hw->pf_id;
6087                 ctxt.vf_num = 0;
6088                 ctxt.uplink_seid = vsi->uplink_seid;
6089                 ctxt.connection_type = 0x1;     /* regular data port */
6090                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6091                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6092                                                 I40E_DEFAULT_TCMAP);
6093                 if (ret != I40E_SUCCESS) {
6094                         PMD_DRV_LOG(ERR,
6095                                 "Failed to configure TC queue mapping.");
6096                         goto fail_msix_alloc;
6097                 }
6098                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6099                 ctxt.info.valid_sections |=
6100                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6101         } else {
6102                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6103                 goto fail_msix_alloc;
6104         }
6105
6106         if (vsi->type != I40E_VSI_MAIN) {
6107                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6108                 if (ret != I40E_SUCCESS) {
6109                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6110                                     hw->aq.asq_last_status);
6111                         goto fail_msix_alloc;
6112                 }
6113                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6114                 vsi->info.valid_sections = 0;
6115                 vsi->seid = ctxt.seid;
6116                 vsi->vsi_id = ctxt.vsi_number;
6117                 vsi->sib_vsi_list.vsi = vsi;
6118                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6119                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6120                                           &vsi->sib_vsi_list, list);
6121                 } else {
6122                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6123                                           &vsi->sib_vsi_list, list);
6124                 }
6125         }
6126
6127         /* MAC/VLAN configuration */
6128         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6129         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
6130
6131         ret = i40e_vsi_add_mac(vsi, &filter);
6132         if (ret != I40E_SUCCESS) {
6133                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6134                 goto fail_msix_alloc;
6135         }
6136
6137         /* Get VSI BW information */
6138         i40e_vsi_get_bw_config(vsi);
6139         return vsi;
6140 fail_msix_alloc:
6141         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6142 fail_queue_alloc:
6143         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6144 fail_mem:
6145         rte_free(vsi);
6146         return NULL;
6147 }
6148
6149 /* Configure vlan filter on or off */
6150 int
6151 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6152 {
6153         int i, num;
6154         struct i40e_mac_filter *f;
6155         void *temp;
6156         struct i40e_mac_filter_info *mac_filter;
6157         enum rte_mac_filter_type desired_filter;
6158         int ret = I40E_SUCCESS;
6159
6160         if (on) {
6161                 /* Filter to match MAC and VLAN */
6162                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6163         } else {
6164                 /* Filter to match only MAC */
6165                 desired_filter = RTE_MAC_PERFECT_MATCH;
6166         }
6167
6168         num = vsi->mac_num;
6169
6170         mac_filter = rte_zmalloc("mac_filter_info_data",
6171                                  num * sizeof(*mac_filter), 0);
6172         if (mac_filter == NULL) {
6173                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6174                 return I40E_ERR_NO_MEMORY;
6175         }
6176
6177         i = 0;
6178
6179         /* Remove all existing mac */
6180         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6181                 mac_filter[i] = f->mac_info;
6182                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6183                 if (ret) {
6184                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6185                                     on ? "enable" : "disable");
6186                         goto DONE;
6187                 }
6188                 i++;
6189         }
6190
6191         /* Override with new filter */
6192         for (i = 0; i < num; i++) {
6193                 mac_filter[i].filter_type = desired_filter;
6194                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6195                 if (ret) {
6196                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6197                                     on ? "enable" : "disable");
6198                         goto DONE;
6199                 }
6200         }
6201
6202 DONE:
6203         rte_free(mac_filter);
6204         return ret;
6205 }
6206
6207 /* Configure vlan stripping on or off */
6208 int
6209 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6210 {
6211         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6212         struct i40e_vsi_context ctxt;
6213         uint8_t vlan_flags;
6214         int ret = I40E_SUCCESS;
6215
6216         /* Check if it has been already on or off */
6217         if (vsi->info.valid_sections &
6218                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6219                 if (on) {
6220                         if ((vsi->info.port_vlan_flags &
6221                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6222                                 return 0; /* already on */
6223                 } else {
6224                         if ((vsi->info.port_vlan_flags &
6225                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6226                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6227                                 return 0; /* already off */
6228                 }
6229         }
6230
6231         if (on)
6232                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6233         else
6234                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6235         vsi->info.valid_sections =
6236                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6237         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6238         vsi->info.port_vlan_flags |= vlan_flags;
6239         ctxt.seid = vsi->seid;
6240         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6241         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6242         if (ret)
6243                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6244                             on ? "enable" : "disable");
6245
6246         return ret;
6247 }
6248
6249 static int
6250 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6251 {
6252         struct rte_eth_dev_data *data = dev->data;
6253         int ret;
6254         int mask = 0;
6255
6256         /* Apply vlan offload setting */
6257         mask = ETH_VLAN_STRIP_MASK |
6258                ETH_QINQ_STRIP_MASK |
6259                ETH_VLAN_FILTER_MASK |
6260                ETH_VLAN_EXTEND_MASK;
6261         ret = i40e_vlan_offload_set(dev, mask);
6262         if (ret) {
6263                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6264                 return ret;
6265         }
6266
6267         /* Apply pvid setting */
6268         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6269                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6270         if (ret)
6271                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6272
6273         return ret;
6274 }
6275
6276 static int
6277 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6278 {
6279         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6280
6281         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6282 }
6283
6284 static int
6285 i40e_update_flow_control(struct i40e_hw *hw)
6286 {
6287 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6288         struct i40e_link_status link_status;
6289         uint32_t rxfc = 0, txfc = 0, reg;
6290         uint8_t an_info;
6291         int ret;
6292
6293         memset(&link_status, 0, sizeof(link_status));
6294         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6295         if (ret != I40E_SUCCESS) {
6296                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6297                 goto write_reg; /* Disable flow control */
6298         }
6299
6300         an_info = hw->phy.link_info.an_info;
6301         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6302                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6303                 ret = I40E_ERR_NOT_READY;
6304                 goto write_reg; /* Disable flow control */
6305         }
6306         /**
6307          * If link auto negotiation is enabled, flow control needs to
6308          * be configured according to it
6309          */
6310         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6311         case I40E_LINK_PAUSE_RXTX:
6312                 rxfc = 1;
6313                 txfc = 1;
6314                 hw->fc.current_mode = I40E_FC_FULL;
6315                 break;
6316         case I40E_AQ_LINK_PAUSE_RX:
6317                 rxfc = 1;
6318                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6319                 break;
6320         case I40E_AQ_LINK_PAUSE_TX:
6321                 txfc = 1;
6322                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6323                 break;
6324         default:
6325                 hw->fc.current_mode = I40E_FC_NONE;
6326                 break;
6327         }
6328
6329 write_reg:
6330         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6331                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6332         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6333         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6334         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6335         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6336
6337         return ret;
6338 }
6339
6340 /* PF setup */
6341 static int
6342 i40e_pf_setup(struct i40e_pf *pf)
6343 {
6344         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6345         struct i40e_filter_control_settings settings;
6346         struct i40e_vsi *vsi;
6347         int ret;
6348
6349         /* Clear all stats counters */
6350         pf->offset_loaded = FALSE;
6351         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6352         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6353         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6354         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6355
6356         ret = i40e_pf_get_switch_config(pf);
6357         if (ret != I40E_SUCCESS) {
6358                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6359                 return ret;
6360         }
6361
6362         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6363         if (ret)
6364                 PMD_INIT_LOG(WARNING,
6365                         "failed to allocate switch domain for device %d", ret);
6366
6367         if (pf->flags & I40E_FLAG_FDIR) {
6368                 /* make queue allocated first, let FDIR use queue pair 0*/
6369                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6370                 if (ret != I40E_FDIR_QUEUE_ID) {
6371                         PMD_DRV_LOG(ERR,
6372                                 "queue allocation fails for FDIR: ret =%d",
6373                                 ret);
6374                         pf->flags &= ~I40E_FLAG_FDIR;
6375                 }
6376         }
6377         /*  main VSI setup */
6378         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6379         if (!vsi) {
6380                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6381                 return I40E_ERR_NOT_READY;
6382         }
6383         pf->main_vsi = vsi;
6384
6385         /* Configure filter control */
6386         memset(&settings, 0, sizeof(settings));
6387         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6388                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6389         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6390                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6391         else {
6392                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6393                         hw->func_caps.rss_table_size);
6394                 return I40E_ERR_PARAM;
6395         }
6396         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6397                 hw->func_caps.rss_table_size);
6398         pf->hash_lut_size = hw->func_caps.rss_table_size;
6399
6400         /* Enable ethtype and macvlan filters */
6401         settings.enable_ethtype = TRUE;
6402         settings.enable_macvlan = TRUE;
6403         ret = i40e_set_filter_control(hw, &settings);
6404         if (ret)
6405                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6406                                                                 ret);
6407
6408         /* Update flow control according to the auto negotiation */
6409         i40e_update_flow_control(hw);
6410
6411         return I40E_SUCCESS;
6412 }
6413
6414 int
6415 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6416 {
6417         uint32_t reg;
6418         uint16_t j;
6419
6420         /**
6421          * Set or clear TX Queue Disable flags,
6422          * which is required by hardware.
6423          */
6424         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6425         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6426
6427         /* Wait until the request is finished */
6428         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6429                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6430                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6431                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6432                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6433                                                         & 0x1))) {
6434                         break;
6435                 }
6436         }
6437         if (on) {
6438                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6439                         return I40E_SUCCESS; /* already on, skip next steps */
6440
6441                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6442                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6443         } else {
6444                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6445                         return I40E_SUCCESS; /* already off, skip next steps */
6446                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6447         }
6448         /* Write the register */
6449         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6450         /* Check the result */
6451         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6452                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6453                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6454                 if (on) {
6455                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6456                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6457                                 break;
6458                 } else {
6459                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6460                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6461                                 break;
6462                 }
6463         }
6464         /* Check if it is timeout */
6465         if (j >= I40E_CHK_Q_ENA_COUNT) {
6466                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6467                             (on ? "enable" : "disable"), q_idx);
6468                 return I40E_ERR_TIMEOUT;
6469         }
6470
6471         return I40E_SUCCESS;
6472 }
6473
6474 int
6475 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6476 {
6477         uint32_t reg;
6478         uint16_t j;
6479
6480         /* Wait until the request is finished */
6481         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6482                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6483                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6484                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6485                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6486                         break;
6487         }
6488
6489         if (on) {
6490                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6491                         return I40E_SUCCESS; /* Already on, skip next steps */
6492                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6493         } else {
6494                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6495                         return I40E_SUCCESS; /* Already off, skip next steps */
6496                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6497         }
6498
6499         /* Write the register */
6500         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6501         /* Check the result */
6502         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6503                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6504                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6505                 if (on) {
6506                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6507                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6508                                 break;
6509                 } else {
6510                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6511                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6512                                 break;
6513                 }
6514         }
6515
6516         /* Check if it is timeout */
6517         if (j >= I40E_CHK_Q_ENA_COUNT) {
6518                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6519                             (on ? "enable" : "disable"), q_idx);
6520                 return I40E_ERR_TIMEOUT;
6521         }
6522
6523         return I40E_SUCCESS;
6524 }
6525
6526 /* Initialize VSI for TX */
6527 static int
6528 i40e_dev_tx_init(struct i40e_pf *pf)
6529 {
6530         struct rte_eth_dev_data *data = pf->dev_data;
6531         uint16_t i;
6532         uint32_t ret = I40E_SUCCESS;
6533         struct i40e_tx_queue *txq;
6534
6535         for (i = 0; i < data->nb_tx_queues; i++) {
6536                 txq = data->tx_queues[i];
6537                 if (!txq || !txq->q_set)
6538                         continue;
6539                 ret = i40e_tx_queue_init(txq);
6540                 if (ret != I40E_SUCCESS)
6541                         break;
6542         }
6543         if (ret == I40E_SUCCESS)
6544                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6545                                      ->eth_dev);
6546
6547         return ret;
6548 }
6549
6550 /* Initialize VSI for RX */
6551 static int
6552 i40e_dev_rx_init(struct i40e_pf *pf)
6553 {
6554         struct rte_eth_dev_data *data = pf->dev_data;
6555         int ret = I40E_SUCCESS;
6556         uint16_t i;
6557         struct i40e_rx_queue *rxq;
6558
6559         i40e_pf_config_rss(pf);
6560         for (i = 0; i < data->nb_rx_queues; i++) {
6561                 rxq = data->rx_queues[i];
6562                 if (!rxq || !rxq->q_set)
6563                         continue;
6564
6565                 ret = i40e_rx_queue_init(rxq);
6566                 if (ret != I40E_SUCCESS) {
6567                         PMD_DRV_LOG(ERR,
6568                                 "Failed to do RX queue initialization");
6569                         break;
6570                 }
6571         }
6572         if (ret == I40E_SUCCESS)
6573                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6574                                      ->eth_dev);
6575
6576         return ret;
6577 }
6578
6579 static int
6580 i40e_dev_rxtx_init(struct i40e_pf *pf)
6581 {
6582         int err;
6583
6584         err = i40e_dev_tx_init(pf);
6585         if (err) {
6586                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6587                 return err;
6588         }
6589         err = i40e_dev_rx_init(pf);
6590         if (err) {
6591                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6592                 return err;
6593         }
6594
6595         return err;
6596 }
6597
6598 static int
6599 i40e_vmdq_setup(struct rte_eth_dev *dev)
6600 {
6601         struct rte_eth_conf *conf = &dev->data->dev_conf;
6602         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6603         int i, err, conf_vsis, j, loop;
6604         struct i40e_vsi *vsi;
6605         struct i40e_vmdq_info *vmdq_info;
6606         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6607         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6608
6609         /*
6610          * Disable interrupt to avoid message from VF. Furthermore, it will
6611          * avoid race condition in VSI creation/destroy.
6612          */
6613         i40e_pf_disable_irq0(hw);
6614
6615         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6616                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6617                 return -ENOTSUP;
6618         }
6619
6620         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6621         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6622                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6623                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6624                         pf->max_nb_vmdq_vsi);
6625                 return -ENOTSUP;
6626         }
6627
6628         if (pf->vmdq != NULL) {
6629                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6630                 return 0;
6631         }
6632
6633         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6634                                 sizeof(*vmdq_info) * conf_vsis, 0);
6635
6636         if (pf->vmdq == NULL) {
6637                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6638                 return -ENOMEM;
6639         }
6640
6641         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6642
6643         /* Create VMDQ VSI */
6644         for (i = 0; i < conf_vsis; i++) {
6645                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6646                                 vmdq_conf->enable_loop_back);
6647                 if (vsi == NULL) {
6648                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6649                         err = -1;
6650                         goto err_vsi_setup;
6651                 }
6652                 vmdq_info = &pf->vmdq[i];
6653                 vmdq_info->pf = pf;
6654                 vmdq_info->vsi = vsi;
6655         }
6656         pf->nb_cfg_vmdq_vsi = conf_vsis;
6657
6658         /* Configure Vlan */
6659         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6660         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6661                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6662                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6663                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6664                                         vmdq_conf->pool_map[i].vlan_id, j);
6665
6666                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6667                                                 vmdq_conf->pool_map[i].vlan_id);
6668                                 if (err) {
6669                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6670                                         err = -1;
6671                                         goto err_vsi_setup;
6672                                 }
6673                         }
6674                 }
6675         }
6676
6677         i40e_pf_enable_irq0(hw);
6678
6679         return 0;
6680
6681 err_vsi_setup:
6682         for (i = 0; i < conf_vsis; i++)
6683                 if (pf->vmdq[i].vsi == NULL)
6684                         break;
6685                 else
6686                         i40e_vsi_release(pf->vmdq[i].vsi);
6687
6688         rte_free(pf->vmdq);
6689         pf->vmdq = NULL;
6690         i40e_pf_enable_irq0(hw);
6691         return err;
6692 }
6693
6694 static void
6695 i40e_stat_update_32(struct i40e_hw *hw,
6696                    uint32_t reg,
6697                    bool offset_loaded,
6698                    uint64_t *offset,
6699                    uint64_t *stat)
6700 {
6701         uint64_t new_data;
6702
6703         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6704         if (!offset_loaded)
6705                 *offset = new_data;
6706
6707         if (new_data >= *offset)
6708                 *stat = (uint64_t)(new_data - *offset);
6709         else
6710                 *stat = (uint64_t)((new_data +
6711                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6712 }
6713
6714 static void
6715 i40e_stat_update_48(struct i40e_hw *hw,
6716                    uint32_t hireg,
6717                    uint32_t loreg,
6718                    bool offset_loaded,
6719                    uint64_t *offset,
6720                    uint64_t *stat)
6721 {
6722         uint64_t new_data;
6723
6724         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6725         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6726                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6727
6728         if (!offset_loaded)
6729                 *offset = new_data;
6730
6731         if (new_data >= *offset)
6732                 *stat = new_data - *offset;
6733         else
6734                 *stat = (uint64_t)((new_data +
6735                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6736
6737         *stat &= I40E_48_BIT_MASK;
6738 }
6739
6740 /* Disable IRQ0 */
6741 void
6742 i40e_pf_disable_irq0(struct i40e_hw *hw)
6743 {
6744         /* Disable all interrupt types */
6745         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6746                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6747         I40E_WRITE_FLUSH(hw);
6748 }
6749
6750 /* Enable IRQ0 */
6751 void
6752 i40e_pf_enable_irq0(struct i40e_hw *hw)
6753 {
6754         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6755                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6756                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6757                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6758         I40E_WRITE_FLUSH(hw);
6759 }
6760
6761 static void
6762 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6763 {
6764         /* read pending request and disable first */
6765         i40e_pf_disable_irq0(hw);
6766         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6767         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6768                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6769
6770         if (no_queue)
6771                 /* Link no queues with irq0 */
6772                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6773                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6774 }
6775
6776 static void
6777 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6778 {
6779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6781         int i;
6782         uint16_t abs_vf_id;
6783         uint32_t index, offset, val;
6784
6785         if (!pf->vfs)
6786                 return;
6787         /**
6788          * Try to find which VF trigger a reset, use absolute VF id to access
6789          * since the reg is global register.
6790          */
6791         for (i = 0; i < pf->vf_num; i++) {
6792                 abs_vf_id = hw->func_caps.vf_base_id + i;
6793                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6794                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6795                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6796                 /* VFR event occurred */
6797                 if (val & (0x1 << offset)) {
6798                         int ret;
6799
6800                         /* Clear the event first */
6801                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6802                                                         (0x1 << offset));
6803                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6804                         /**
6805                          * Only notify a VF reset event occurred,
6806                          * don't trigger another SW reset
6807                          */
6808                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6809                         if (ret != I40E_SUCCESS)
6810                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6811                 }
6812         }
6813 }
6814
6815 static void
6816 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6817 {
6818         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6819         int i;
6820
6821         for (i = 0; i < pf->vf_num; i++)
6822                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6823 }
6824
6825 static void
6826 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6827 {
6828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6829         struct i40e_arq_event_info info;
6830         uint16_t pending, opcode;
6831         int ret;
6832
6833         info.buf_len = I40E_AQ_BUF_SZ;
6834         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6835         if (!info.msg_buf) {
6836                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6837                 return;
6838         }
6839
6840         pending = 1;
6841         while (pending) {
6842                 ret = i40e_clean_arq_element(hw, &info, &pending);
6843
6844                 if (ret != I40E_SUCCESS) {
6845                         PMD_DRV_LOG(INFO,
6846                                 "Failed to read msg from AdminQ, aq_err: %u",
6847                                 hw->aq.asq_last_status);
6848                         break;
6849                 }
6850                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6851
6852                 switch (opcode) {
6853                 case i40e_aqc_opc_send_msg_to_pf:
6854                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6855                         i40e_pf_host_handle_vf_msg(dev,
6856                                         rte_le_to_cpu_16(info.desc.retval),
6857                                         rte_le_to_cpu_32(info.desc.cookie_high),
6858                                         rte_le_to_cpu_32(info.desc.cookie_low),
6859                                         info.msg_buf,
6860                                         info.msg_len);
6861                         break;
6862                 case i40e_aqc_opc_get_link_status:
6863                         ret = i40e_dev_link_update(dev, 0);
6864                         if (!ret)
6865                                 rte_eth_dev_callback_process(dev,
6866                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6867                         break;
6868                 default:
6869                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6870                                     opcode);
6871                         break;
6872                 }
6873         }
6874         rte_free(info.msg_buf);
6875 }
6876
6877 static void
6878 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6879 {
6880 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6881 #define I40E_MDD_CLEAR16 0xFFFF
6882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6884         bool mdd_detected = false;
6885         struct i40e_pf_vf *vf;
6886         uint32_t reg;
6887         int i;
6888
6889         /* find what triggered the MDD event */
6890         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6891         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6892                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6893                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6894                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6895                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6896                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6897                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6898                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6899                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6900                                         hw->func_caps.base_queue;
6901                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6902                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6903                                 event, queue, pf_num, vf_num, dev->data->name);
6904                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6905                 mdd_detected = true;
6906         }
6907         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6908         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6909                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6910                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6911                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6912                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6913                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6914                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6915                                         hw->func_caps.base_queue;
6916
6917                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6918                                 "queue %d of function 0x%02x device %s\n",
6919                                         event, queue, func, dev->data->name);
6920                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6921                 mdd_detected = true;
6922         }
6923
6924         if (mdd_detected) {
6925                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6926                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6927                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6928                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6929                 }
6930                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6931                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6932                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6933                                         I40E_MDD_CLEAR16);
6934                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6935                 }
6936         }
6937
6938         /* see if one of the VFs needs its hand slapped */
6939         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6940                 vf = &pf->vfs[i];
6941                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6942                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6943                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6944                                         I40E_MDD_CLEAR16);
6945                         vf->num_mdd_events++;
6946                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6947                                         PRIu64 "times\n",
6948                                         i, vf->num_mdd_events);
6949                 }
6950
6951                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6952                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6953                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6954                                         I40E_MDD_CLEAR16);
6955                         vf->num_mdd_events++;
6956                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6957                                         PRIu64 "times\n",
6958                                         i, vf->num_mdd_events);
6959                 }
6960         }
6961 }
6962
6963 /**
6964  * Interrupt handler triggered by NIC  for handling
6965  * specific interrupt.
6966  *
6967  * @param handle
6968  *  Pointer to interrupt handle.
6969  * @param param
6970  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6971  *
6972  * @return
6973  *  void
6974  */
6975 static void
6976 i40e_dev_interrupt_handler(void *param)
6977 {
6978         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6979         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6980         uint32_t icr0;
6981
6982         /* Disable interrupt */
6983         i40e_pf_disable_irq0(hw);
6984
6985         /* read out interrupt causes */
6986         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6987
6988         /* No interrupt event indicated */
6989         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6990                 PMD_DRV_LOG(INFO, "No interrupt event");
6991                 goto done;
6992         }
6993         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6994                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6995         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6996                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6997                 i40e_handle_mdd_event(dev);
6998         }
6999         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
7000                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
7001         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
7002                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
7003         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
7004                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
7005         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
7006                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
7007         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
7008                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
7009
7010         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
7011                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
7012                 i40e_dev_handle_vfr_event(dev);
7013         }
7014         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
7015                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7016                 i40e_dev_handle_aq_msg(dev);
7017         }
7018
7019 done:
7020         /* Enable interrupt */
7021         i40e_pf_enable_irq0(hw);
7022 }
7023
7024 static void
7025 i40e_dev_alarm_handler(void *param)
7026 {
7027         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7028         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7029         uint32_t icr0;
7030
7031         /* Disable interrupt */
7032         i40e_pf_disable_irq0(hw);
7033
7034         /* read out interrupt causes */
7035         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
7036
7037         /* No interrupt event indicated */
7038         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
7039                 goto done;
7040         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
7041                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
7042         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
7043                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
7044                 i40e_handle_mdd_event(dev);
7045         }
7046         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
7047                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
7048         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
7049                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
7050         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
7051                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
7052         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
7053                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
7054         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
7055                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
7056
7057         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
7058                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
7059                 i40e_dev_handle_vfr_event(dev);
7060         }
7061         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
7062                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7063                 i40e_dev_handle_aq_msg(dev);
7064         }
7065
7066 done:
7067         /* Enable interrupt */
7068         i40e_pf_enable_irq0(hw);
7069         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
7070                           i40e_dev_alarm_handler, dev);
7071 }
7072
7073 int
7074 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
7075                          struct i40e_macvlan_filter *filter,
7076                          int total)
7077 {
7078         int ele_num, ele_buff_size;
7079         int num, actual_num, i;
7080         uint16_t flags;
7081         int ret = I40E_SUCCESS;
7082         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7083         struct i40e_aqc_add_macvlan_element_data *req_list;
7084
7085         if (filter == NULL  || total == 0)
7086                 return I40E_ERR_PARAM;
7087         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7088         ele_buff_size = hw->aq.asq_buf_size;
7089
7090         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7091         if (req_list == NULL) {
7092                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7093                 return I40E_ERR_NO_MEMORY;
7094         }
7095
7096         num = 0;
7097         do {
7098                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7099                 memset(req_list, 0, ele_buff_size);
7100
7101                 for (i = 0; i < actual_num; i++) {
7102                         rte_memcpy(req_list[i].mac_addr,
7103                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7104                         req_list[i].vlan_tag =
7105                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7106
7107                         switch (filter[num + i].filter_type) {
7108                         case RTE_MAC_PERFECT_MATCH:
7109                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7110                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7111                                 break;
7112                         case RTE_MACVLAN_PERFECT_MATCH:
7113                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7114                                 break;
7115                         case RTE_MAC_HASH_MATCH:
7116                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7117                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7118                                 break;
7119                         case RTE_MACVLAN_HASH_MATCH:
7120                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7121                                 break;
7122                         default:
7123                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7124                                 ret = I40E_ERR_PARAM;
7125                                 goto DONE;
7126                         }
7127
7128                         req_list[i].queue_number = 0;
7129
7130                         req_list[i].flags = rte_cpu_to_le_16(flags);
7131                 }
7132
7133                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7134                                                 actual_num, NULL);
7135                 if (ret != I40E_SUCCESS) {
7136                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7137                         goto DONE;
7138                 }
7139                 num += actual_num;
7140         } while (num < total);
7141
7142 DONE:
7143         rte_free(req_list);
7144         return ret;
7145 }
7146
7147 int
7148 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7149                             struct i40e_macvlan_filter *filter,
7150                             int total)
7151 {
7152         int ele_num, ele_buff_size;
7153         int num, actual_num, i;
7154         uint16_t flags;
7155         int ret = I40E_SUCCESS;
7156         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7157         struct i40e_aqc_remove_macvlan_element_data *req_list;
7158
7159         if (filter == NULL  || total == 0)
7160                 return I40E_ERR_PARAM;
7161
7162         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7163         ele_buff_size = hw->aq.asq_buf_size;
7164
7165         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7166         if (req_list == NULL) {
7167                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7168                 return I40E_ERR_NO_MEMORY;
7169         }
7170
7171         num = 0;
7172         do {
7173                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7174                 memset(req_list, 0, ele_buff_size);
7175
7176                 for (i = 0; i < actual_num; i++) {
7177                         rte_memcpy(req_list[i].mac_addr,
7178                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7179                         req_list[i].vlan_tag =
7180                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7181
7182                         switch (filter[num + i].filter_type) {
7183                         case RTE_MAC_PERFECT_MATCH:
7184                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7185                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7186                                 break;
7187                         case RTE_MACVLAN_PERFECT_MATCH:
7188                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7189                                 break;
7190                         case RTE_MAC_HASH_MATCH:
7191                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7192                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7193                                 break;
7194                         case RTE_MACVLAN_HASH_MATCH:
7195                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7196                                 break;
7197                         default:
7198                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7199                                 ret = I40E_ERR_PARAM;
7200                                 goto DONE;
7201                         }
7202                         req_list[i].flags = rte_cpu_to_le_16(flags);
7203                 }
7204
7205                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7206                                                 actual_num, NULL);
7207                 if (ret != I40E_SUCCESS) {
7208                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7209                         goto DONE;
7210                 }
7211                 num += actual_num;
7212         } while (num < total);
7213
7214 DONE:
7215         rte_free(req_list);
7216         return ret;
7217 }
7218
7219 /* Find out specific MAC filter */
7220 static struct i40e_mac_filter *
7221 i40e_find_mac_filter(struct i40e_vsi *vsi,
7222                          struct rte_ether_addr *macaddr)
7223 {
7224         struct i40e_mac_filter *f;
7225
7226         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7227                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7228                         return f;
7229         }
7230
7231         return NULL;
7232 }
7233
7234 static bool
7235 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7236                          uint16_t vlan_id)
7237 {
7238         uint32_t vid_idx, vid_bit;
7239
7240         if (vlan_id > ETH_VLAN_ID_MAX)
7241                 return 0;
7242
7243         vid_idx = I40E_VFTA_IDX(vlan_id);
7244         vid_bit = I40E_VFTA_BIT(vlan_id);
7245
7246         if (vsi->vfta[vid_idx] & vid_bit)
7247                 return 1;
7248         else
7249                 return 0;
7250 }
7251
7252 static void
7253 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7254                        uint16_t vlan_id, bool on)
7255 {
7256         uint32_t vid_idx, vid_bit;
7257
7258         vid_idx = I40E_VFTA_IDX(vlan_id);
7259         vid_bit = I40E_VFTA_BIT(vlan_id);
7260
7261         if (on)
7262                 vsi->vfta[vid_idx] |= vid_bit;
7263         else
7264                 vsi->vfta[vid_idx] &= ~vid_bit;
7265 }
7266
7267 void
7268 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7269                      uint16_t vlan_id, bool on)
7270 {
7271         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7272         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7273         int ret;
7274
7275         if (vlan_id > ETH_VLAN_ID_MAX)
7276                 return;
7277
7278         i40e_store_vlan_filter(vsi, vlan_id, on);
7279
7280         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7281                 return;
7282
7283         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7284
7285         if (on) {
7286                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7287                                        &vlan_data, 1, NULL);
7288                 if (ret != I40E_SUCCESS)
7289                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7290         } else {
7291                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7292                                           &vlan_data, 1, NULL);
7293                 if (ret != I40E_SUCCESS)
7294                         PMD_DRV_LOG(ERR,
7295                                     "Failed to remove vlan filter");
7296         }
7297 }
7298
7299 /**
7300  * Find all vlan options for specific mac addr,
7301  * return with actual vlan found.
7302  */
7303 int
7304 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7305                            struct i40e_macvlan_filter *mv_f,
7306                            int num, struct rte_ether_addr *addr)
7307 {
7308         int i;
7309         uint32_t j, k;
7310
7311         /**
7312          * Not to use i40e_find_vlan_filter to decrease the loop time,
7313          * although the code looks complex.
7314           */
7315         if (num < vsi->vlan_num)
7316                 return I40E_ERR_PARAM;
7317
7318         i = 0;
7319         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7320                 if (vsi->vfta[j]) {
7321                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7322                                 if (vsi->vfta[j] & (1 << k)) {
7323                                         if (i > num - 1) {
7324                                                 PMD_DRV_LOG(ERR,
7325                                                         "vlan number doesn't match");
7326                                                 return I40E_ERR_PARAM;
7327                                         }
7328                                         rte_memcpy(&mv_f[i].macaddr,
7329                                                         addr, ETH_ADDR_LEN);
7330                                         mv_f[i].vlan_id =
7331                                                 j * I40E_UINT32_BIT_SIZE + k;
7332                                         i++;
7333                                 }
7334                         }
7335                 }
7336         }
7337         return I40E_SUCCESS;
7338 }
7339
7340 static inline int
7341 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7342                            struct i40e_macvlan_filter *mv_f,
7343                            int num,
7344                            uint16_t vlan)
7345 {
7346         int i = 0;
7347         struct i40e_mac_filter *f;
7348
7349         if (num < vsi->mac_num)
7350                 return I40E_ERR_PARAM;
7351
7352         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7353                 if (i > num - 1) {
7354                         PMD_DRV_LOG(ERR, "buffer number not match");
7355                         return I40E_ERR_PARAM;
7356                 }
7357                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7358                                 ETH_ADDR_LEN);
7359                 mv_f[i].vlan_id = vlan;
7360                 mv_f[i].filter_type = f->mac_info.filter_type;
7361                 i++;
7362         }
7363
7364         return I40E_SUCCESS;
7365 }
7366
7367 static int
7368 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7369 {
7370         int i, j, num;
7371         struct i40e_mac_filter *f;
7372         struct i40e_macvlan_filter *mv_f;
7373         int ret = I40E_SUCCESS;
7374
7375         if (vsi == NULL || vsi->mac_num == 0)
7376                 return I40E_ERR_PARAM;
7377
7378         /* Case that no vlan is set */
7379         if (vsi->vlan_num == 0)
7380                 num = vsi->mac_num;
7381         else
7382                 num = vsi->mac_num * vsi->vlan_num;
7383
7384         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7385         if (mv_f == NULL) {
7386                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7387                 return I40E_ERR_NO_MEMORY;
7388         }
7389
7390         i = 0;
7391         if (vsi->vlan_num == 0) {
7392                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7393                         rte_memcpy(&mv_f[i].macaddr,
7394                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7395                         mv_f[i].filter_type = f->mac_info.filter_type;
7396                         mv_f[i].vlan_id = 0;
7397                         i++;
7398                 }
7399         } else {
7400                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7401                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7402                                         vsi->vlan_num, &f->mac_info.mac_addr);
7403                         if (ret != I40E_SUCCESS)
7404                                 goto DONE;
7405                         for (j = i; j < i + vsi->vlan_num; j++)
7406                                 mv_f[j].filter_type = f->mac_info.filter_type;
7407                         i += vsi->vlan_num;
7408                 }
7409         }
7410
7411         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7412 DONE:
7413         rte_free(mv_f);
7414
7415         return ret;
7416 }
7417
7418 int
7419 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7420 {
7421         struct i40e_macvlan_filter *mv_f;
7422         int mac_num;
7423         int ret = I40E_SUCCESS;
7424
7425         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7426                 return I40E_ERR_PARAM;
7427
7428         /* If it's already set, just return */
7429         if (i40e_find_vlan_filter(vsi,vlan))
7430                 return I40E_SUCCESS;
7431
7432         mac_num = vsi->mac_num;
7433
7434         if (mac_num == 0) {
7435                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7436                 return I40E_ERR_PARAM;
7437         }
7438
7439         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7440
7441         if (mv_f == NULL) {
7442                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7443                 return I40E_ERR_NO_MEMORY;
7444         }
7445
7446         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7447
7448         if (ret != I40E_SUCCESS)
7449                 goto DONE;
7450
7451         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7452
7453         if (ret != I40E_SUCCESS)
7454                 goto DONE;
7455
7456         i40e_set_vlan_filter(vsi, vlan, 1);
7457
7458         vsi->vlan_num++;
7459         ret = I40E_SUCCESS;
7460 DONE:
7461         rte_free(mv_f);
7462         return ret;
7463 }
7464
7465 int
7466 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7467 {
7468         struct i40e_macvlan_filter *mv_f;
7469         int mac_num;
7470         int ret = I40E_SUCCESS;
7471
7472         /**
7473          * Vlan 0 is the generic filter for untagged packets
7474          * and can't be removed.
7475          */
7476         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7477                 return I40E_ERR_PARAM;
7478
7479         /* If can't find it, just return */
7480         if (!i40e_find_vlan_filter(vsi, vlan))
7481                 return I40E_ERR_PARAM;
7482
7483         mac_num = vsi->mac_num;
7484
7485         if (mac_num == 0) {
7486                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7487                 return I40E_ERR_PARAM;
7488         }
7489
7490         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7491
7492         if (mv_f == NULL) {
7493                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7494                 return I40E_ERR_NO_MEMORY;
7495         }
7496
7497         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7498
7499         if (ret != I40E_SUCCESS)
7500                 goto DONE;
7501
7502         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7503
7504         if (ret != I40E_SUCCESS)
7505                 goto DONE;
7506
7507         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7508         if (vsi->vlan_num == 1) {
7509                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7510                 if (ret != I40E_SUCCESS)
7511                         goto DONE;
7512
7513                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7514                 if (ret != I40E_SUCCESS)
7515                         goto DONE;
7516         }
7517
7518         i40e_set_vlan_filter(vsi, vlan, 0);
7519
7520         vsi->vlan_num--;
7521         ret = I40E_SUCCESS;
7522 DONE:
7523         rte_free(mv_f);
7524         return ret;
7525 }
7526
7527 int
7528 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7529 {
7530         struct i40e_mac_filter *f;
7531         struct i40e_macvlan_filter *mv_f;
7532         int i, vlan_num = 0;
7533         int ret = I40E_SUCCESS;
7534
7535         /* If it's add and we've config it, return */
7536         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7537         if (f != NULL)
7538                 return I40E_SUCCESS;
7539         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7540                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7541
7542                 /**
7543                  * If vlan_num is 0, that's the first time to add mac,
7544                  * set mask for vlan_id 0.
7545                  */
7546                 if (vsi->vlan_num == 0) {
7547                         i40e_set_vlan_filter(vsi, 0, 1);
7548                         vsi->vlan_num = 1;
7549                 }
7550                 vlan_num = vsi->vlan_num;
7551         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7552                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7553                 vlan_num = 1;
7554
7555         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7556         if (mv_f == NULL) {
7557                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7558                 return I40E_ERR_NO_MEMORY;
7559         }
7560
7561         for (i = 0; i < vlan_num; i++) {
7562                 mv_f[i].filter_type = mac_filter->filter_type;
7563                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7564                                 ETH_ADDR_LEN);
7565         }
7566
7567         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7568                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7569                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7570                                         &mac_filter->mac_addr);
7571                 if (ret != I40E_SUCCESS)
7572                         goto DONE;
7573         }
7574
7575         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7576         if (ret != I40E_SUCCESS)
7577                 goto DONE;
7578
7579         /* Add the mac addr into mac list */
7580         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7581         if (f == NULL) {
7582                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7583                 ret = I40E_ERR_NO_MEMORY;
7584                 goto DONE;
7585         }
7586         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7587                         ETH_ADDR_LEN);
7588         f->mac_info.filter_type = mac_filter->filter_type;
7589         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7590         vsi->mac_num++;
7591
7592         ret = I40E_SUCCESS;
7593 DONE:
7594         rte_free(mv_f);
7595
7596         return ret;
7597 }
7598
7599 int
7600 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7601 {
7602         struct i40e_mac_filter *f;
7603         struct i40e_macvlan_filter *mv_f;
7604         int i, vlan_num;
7605         enum rte_mac_filter_type filter_type;
7606         int ret = I40E_SUCCESS;
7607
7608         /* Can't find it, return an error */
7609         f = i40e_find_mac_filter(vsi, addr);
7610         if (f == NULL)
7611                 return I40E_ERR_PARAM;
7612
7613         vlan_num = vsi->vlan_num;
7614         filter_type = f->mac_info.filter_type;
7615         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7616                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7617                 if (vlan_num == 0) {
7618                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7619                         return I40E_ERR_PARAM;
7620                 }
7621         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7622                         filter_type == RTE_MAC_HASH_MATCH)
7623                 vlan_num = 1;
7624
7625         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7626         if (mv_f == NULL) {
7627                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7628                 return I40E_ERR_NO_MEMORY;
7629         }
7630
7631         for (i = 0; i < vlan_num; i++) {
7632                 mv_f[i].filter_type = filter_type;
7633                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7634                                 ETH_ADDR_LEN);
7635         }
7636         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7637                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7638                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7639                 if (ret != I40E_SUCCESS)
7640                         goto DONE;
7641         }
7642
7643         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7644         if (ret != I40E_SUCCESS)
7645                 goto DONE;
7646
7647         /* Remove the mac addr into mac list */
7648         TAILQ_REMOVE(&vsi->mac_list, f, next);
7649         rte_free(f);
7650         vsi->mac_num--;
7651
7652         ret = I40E_SUCCESS;
7653 DONE:
7654         rte_free(mv_f);
7655         return ret;
7656 }
7657
7658 /* Configure hash enable flags for RSS */
7659 uint64_t
7660 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7661 {
7662         uint64_t hena = 0;
7663         int i;
7664
7665         if (!flags)
7666                 return hena;
7667
7668         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7669                 if (flags & (1ULL << i))
7670                         hena |= adapter->pctypes_tbl[i];
7671         }
7672
7673         return hena;
7674 }
7675
7676 /* Parse the hash enable flags */
7677 uint64_t
7678 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7679 {
7680         uint64_t rss_hf = 0;
7681
7682         if (!flags)
7683                 return rss_hf;
7684         int i;
7685
7686         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7687                 if (flags & adapter->pctypes_tbl[i])
7688                         rss_hf |= (1ULL << i);
7689         }
7690         return rss_hf;
7691 }
7692
7693 /* Disable RSS */
7694 static void
7695 i40e_pf_disable_rss(struct i40e_pf *pf)
7696 {
7697         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7698
7699         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7700         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7701         I40E_WRITE_FLUSH(hw);
7702 }
7703
7704 int
7705 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7706 {
7707         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7708         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7709         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7710                            I40E_VFQF_HKEY_MAX_INDEX :
7711                            I40E_PFQF_HKEY_MAX_INDEX;
7712         int ret = 0;
7713
7714         if (!key || key_len == 0) {
7715                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7716                 return 0;
7717         } else if (key_len != (key_idx + 1) *
7718                 sizeof(uint32_t)) {
7719                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7720                 return -EINVAL;
7721         }
7722
7723         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7724                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7725                         (struct i40e_aqc_get_set_rss_key_data *)key;
7726
7727                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7728                 if (ret)
7729                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7730         } else {
7731                 uint32_t *hash_key = (uint32_t *)key;
7732                 uint16_t i;
7733
7734                 if (vsi->type == I40E_VSI_SRIOV) {
7735                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7736                                 I40E_WRITE_REG(
7737                                         hw,
7738                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7739                                         hash_key[i]);
7740
7741                 } else {
7742                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7743                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7744                                                hash_key[i]);
7745                 }
7746                 I40E_WRITE_FLUSH(hw);
7747         }
7748
7749         return ret;
7750 }
7751
7752 static int
7753 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7754 {
7755         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7756         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7757         uint32_t reg;
7758         int ret;
7759
7760         if (!key || !key_len)
7761                 return 0;
7762
7763         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7764                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7765                         (struct i40e_aqc_get_set_rss_key_data *)key);
7766                 if (ret) {
7767                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7768                         return ret;
7769                 }
7770         } else {
7771                 uint32_t *key_dw = (uint32_t *)key;
7772                 uint16_t i;
7773
7774                 if (vsi->type == I40E_VSI_SRIOV) {
7775                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7776                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7777                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7778                         }
7779                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7780                                    sizeof(uint32_t);
7781                 } else {
7782                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7783                                 reg = I40E_PFQF_HKEY(i);
7784                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7785                         }
7786                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7787                                    sizeof(uint32_t);
7788                 }
7789         }
7790         return 0;
7791 }
7792
7793 static int
7794 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7795 {
7796         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7797         uint64_t hena;
7798         int ret;
7799
7800         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7801                                rss_conf->rss_key_len);
7802         if (ret)
7803                 return ret;
7804
7805         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7806         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7807         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7808         I40E_WRITE_FLUSH(hw);
7809
7810         return 0;
7811 }
7812
7813 static int
7814 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7815                          struct rte_eth_rss_conf *rss_conf)
7816 {
7817         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7818         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7819         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7820         uint64_t hena;
7821
7822         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7823         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7824
7825         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7826                 if (rss_hf != 0) /* Enable RSS */
7827                         return -EINVAL;
7828                 return 0; /* Nothing to do */
7829         }
7830         /* RSS enabled */
7831         if (rss_hf == 0) /* Disable RSS */
7832                 return -EINVAL;
7833
7834         return i40e_hw_rss_hash_set(pf, rss_conf);
7835 }
7836
7837 static int
7838 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7839                            struct rte_eth_rss_conf *rss_conf)
7840 {
7841         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7843         uint64_t hena;
7844         int ret;
7845
7846         if (!rss_conf)
7847                 return -EINVAL;
7848
7849         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7850                          &rss_conf->rss_key_len);
7851         if (ret)
7852                 return ret;
7853
7854         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7855         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7856         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7857
7858         return 0;
7859 }
7860
7861 static int
7862 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7863 {
7864         switch (filter_type) {
7865         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7866                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7867                 break;
7868         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7869                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7870                 break;
7871         case RTE_TUNNEL_FILTER_IMAC_TENID:
7872                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7873                 break;
7874         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7875                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7876                 break;
7877         case ETH_TUNNEL_FILTER_IMAC:
7878                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7879                 break;
7880         case ETH_TUNNEL_FILTER_OIP:
7881                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7882                 break;
7883         case ETH_TUNNEL_FILTER_IIP:
7884                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7885                 break;
7886         default:
7887                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7888                 return -EINVAL;
7889         }
7890
7891         return 0;
7892 }
7893
7894 /* Convert tunnel filter structure */
7895 static int
7896 i40e_tunnel_filter_convert(
7897         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7898         struct i40e_tunnel_filter *tunnel_filter)
7899 {
7900         rte_ether_addr_copy((struct rte_ether_addr *)
7901                         &cld_filter->element.outer_mac,
7902                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7903         rte_ether_addr_copy((struct rte_ether_addr *)
7904                         &cld_filter->element.inner_mac,
7905                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7906         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7907         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7908              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7909             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7910                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7911         else
7912                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7913         tunnel_filter->input.flags = cld_filter->element.flags;
7914         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7915         tunnel_filter->queue = cld_filter->element.queue_number;
7916         rte_memcpy(tunnel_filter->input.general_fields,
7917                    cld_filter->general_fields,
7918                    sizeof(cld_filter->general_fields));
7919
7920         return 0;
7921 }
7922
7923 /* Check if there exists the tunnel filter */
7924 struct i40e_tunnel_filter *
7925 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7926                              const struct i40e_tunnel_filter_input *input)
7927 {
7928         int ret;
7929
7930         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7931         if (ret < 0)
7932                 return NULL;
7933
7934         return tunnel_rule->hash_map[ret];
7935 }
7936
7937 /* Add a tunnel filter into the SW list */
7938 static int
7939 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7940                              struct i40e_tunnel_filter *tunnel_filter)
7941 {
7942         struct i40e_tunnel_rule *rule = &pf->tunnel;
7943         int ret;
7944
7945         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7946         if (ret < 0) {
7947                 PMD_DRV_LOG(ERR,
7948                             "Failed to insert tunnel filter to hash table %d!",
7949                             ret);
7950                 return ret;
7951         }
7952         rule->hash_map[ret] = tunnel_filter;
7953
7954         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7955
7956         return 0;
7957 }
7958
7959 /* Delete a tunnel filter from the SW list */
7960 int
7961 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7962                           struct i40e_tunnel_filter_input *input)
7963 {
7964         struct i40e_tunnel_rule *rule = &pf->tunnel;
7965         struct i40e_tunnel_filter *tunnel_filter;
7966         int ret;
7967
7968         ret = rte_hash_del_key(rule->hash_table, input);
7969         if (ret < 0) {
7970                 PMD_DRV_LOG(ERR,
7971                             "Failed to delete tunnel filter to hash table %d!",
7972                             ret);
7973                 return ret;
7974         }
7975         tunnel_filter = rule->hash_map[ret];
7976         rule->hash_map[ret] = NULL;
7977
7978         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7979         rte_free(tunnel_filter);
7980
7981         return 0;
7982 }
7983
7984 int
7985 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7986                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7987                         uint8_t add)
7988 {
7989         uint16_t ip_type;
7990         uint32_t ipv4_addr, ipv4_addr_le;
7991         uint8_t i, tun_type = 0;
7992         /* internal varialbe to convert ipv6 byte order */
7993         uint32_t convert_ipv6[4];
7994         int val, ret = 0;
7995         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7996         struct i40e_vsi *vsi = pf->main_vsi;
7997         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7998         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7999         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8000         struct i40e_tunnel_filter *tunnel, *node;
8001         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8002
8003         cld_filter = rte_zmalloc("tunnel_filter",
8004                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8005         0);
8006
8007         if (NULL == cld_filter) {
8008                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8009                 return -ENOMEM;
8010         }
8011         pfilter = cld_filter;
8012
8013         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8014                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8015         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8016                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8017
8018         pfilter->element.inner_vlan =
8019                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8020         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
8021                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8022                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8023                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8024                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8025                                 &ipv4_addr_le,
8026                                 sizeof(pfilter->element.ipaddr.v4.data));
8027         } else {
8028                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8029                 for (i = 0; i < 4; i++) {
8030                         convert_ipv6[i] =
8031                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
8032                 }
8033                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8034                            &convert_ipv6,
8035                            sizeof(pfilter->element.ipaddr.v6.data));
8036         }
8037
8038         /* check tunneled type */
8039         switch (tunnel_filter->tunnel_type) {
8040         case RTE_TUNNEL_TYPE_VXLAN:
8041                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8042                 break;
8043         case RTE_TUNNEL_TYPE_NVGRE:
8044                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8045                 break;
8046         case RTE_TUNNEL_TYPE_IP_IN_GRE:
8047                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8048                 break;
8049         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8050                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
8051                 break;
8052         default:
8053                 /* Other tunnel types is not supported. */
8054                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8055                 rte_free(cld_filter);
8056                 return -EINVAL;
8057         }
8058
8059         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8060                                        &pfilter->element.flags);
8061         if (val < 0) {
8062                 rte_free(cld_filter);
8063                 return -EINVAL;
8064         }
8065
8066         pfilter->element.flags |= rte_cpu_to_le_16(
8067                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8068                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8069         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8070         pfilter->element.queue_number =
8071                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8072
8073         /* Check if there is the filter in SW list */
8074         memset(&check_filter, 0, sizeof(check_filter));
8075         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8076         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8077         if (add && node) {
8078                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8079                 rte_free(cld_filter);
8080                 return -EINVAL;
8081         }
8082
8083         if (!add && !node) {
8084                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8085                 rte_free(cld_filter);
8086                 return -EINVAL;
8087         }
8088
8089         if (add) {
8090                 ret = i40e_aq_add_cloud_filters(hw,
8091                                         vsi->seid, &cld_filter->element, 1);
8092                 if (ret < 0) {
8093                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8094                         rte_free(cld_filter);
8095                         return -ENOTSUP;
8096                 }
8097                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8098                 if (tunnel == NULL) {
8099                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8100                         rte_free(cld_filter);
8101                         return -ENOMEM;
8102                 }
8103
8104                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8105                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8106                 if (ret < 0)
8107                         rte_free(tunnel);
8108         } else {
8109                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8110                                                    &cld_filter->element, 1);
8111                 if (ret < 0) {
8112                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8113                         rte_free(cld_filter);
8114                         return -ENOTSUP;
8115                 }
8116                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8117         }
8118
8119         rte_free(cld_filter);
8120         return ret;
8121 }
8122
8123 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8124 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
8125 #define I40E_TR_GENEVE_KEY_MASK                 0x8
8126 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
8127 #define I40E_TR_GRE_KEY_MASK                    0x400
8128 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
8129 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
8130 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8131 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8132 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8133 #define I40E_DIRECTION_INGRESS_KEY              0x8000
8134 #define I40E_TR_L4_TYPE_TCP                     0x2
8135 #define I40E_TR_L4_TYPE_UDP                     0x4
8136 #define I40E_TR_L4_TYPE_SCTP                    0x8
8137
8138 static enum
8139 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8140 {
8141         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8142         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8143         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8144         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8145         enum i40e_status_code status = I40E_SUCCESS;
8146
8147         if (pf->support_multi_driver) {
8148                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8149                 return I40E_NOT_SUPPORTED;
8150         }
8151
8152         memset(&filter_replace, 0,
8153                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8154         memset(&filter_replace_buf, 0,
8155                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8156
8157         /* create L1 filter */
8158         filter_replace.old_filter_type =
8159                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8160         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8161         filter_replace.tr_bit = 0;
8162
8163         /* Prepare the buffer, 3 entries */
8164         filter_replace_buf.data[0] =
8165                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8166         filter_replace_buf.data[0] |=
8167                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8168         filter_replace_buf.data[2] = 0xFF;
8169         filter_replace_buf.data[3] = 0xFF;
8170         filter_replace_buf.data[4] =
8171                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8172         filter_replace_buf.data[4] |=
8173                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8174         filter_replace_buf.data[7] = 0xF0;
8175         filter_replace_buf.data[8]
8176                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8177         filter_replace_buf.data[8] |=
8178                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8179         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8180                 I40E_TR_GENEVE_KEY_MASK |
8181                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8182         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8183                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8184                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8185
8186         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8187                                                &filter_replace_buf);
8188         if (!status && (filter_replace.old_filter_type !=
8189                         filter_replace.new_filter_type))
8190                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8191                             " original: 0x%x, new: 0x%x",
8192                             dev->device->name,
8193                             filter_replace.old_filter_type,
8194                             filter_replace.new_filter_type);
8195
8196         return status;
8197 }
8198
8199 static enum
8200 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8201 {
8202         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8203         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8204         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8205         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8206         enum i40e_status_code status = I40E_SUCCESS;
8207
8208         if (pf->support_multi_driver) {
8209                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8210                 return I40E_NOT_SUPPORTED;
8211         }
8212
8213         /* For MPLSoUDP */
8214         memset(&filter_replace, 0,
8215                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8216         memset(&filter_replace_buf, 0,
8217                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8218         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8219                 I40E_AQC_MIRROR_CLOUD_FILTER;
8220         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8221         filter_replace.new_filter_type =
8222                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8223         /* Prepare the buffer, 2 entries */
8224         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8225         filter_replace_buf.data[0] |=
8226                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8227         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8228         filter_replace_buf.data[4] |=
8229                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8230         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8231                                                &filter_replace_buf);
8232         if (status < 0)
8233                 return status;
8234         if (filter_replace.old_filter_type !=
8235             filter_replace.new_filter_type)
8236                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8237                             " original: 0x%x, new: 0x%x",
8238                             dev->device->name,
8239                             filter_replace.old_filter_type,
8240                             filter_replace.new_filter_type);
8241
8242         /* For MPLSoGRE */
8243         memset(&filter_replace, 0,
8244                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8245         memset(&filter_replace_buf, 0,
8246                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8247
8248         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8249                 I40E_AQC_MIRROR_CLOUD_FILTER;
8250         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8251         filter_replace.new_filter_type =
8252                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8253         /* Prepare the buffer, 2 entries */
8254         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8255         filter_replace_buf.data[0] |=
8256                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8257         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8258         filter_replace_buf.data[4] |=
8259                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8260
8261         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8262                                                &filter_replace_buf);
8263         if (!status && (filter_replace.old_filter_type !=
8264                         filter_replace.new_filter_type))
8265                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8266                             " original: 0x%x, new: 0x%x",
8267                             dev->device->name,
8268                             filter_replace.old_filter_type,
8269                             filter_replace.new_filter_type);
8270
8271         return status;
8272 }
8273
8274 static enum i40e_status_code
8275 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8276 {
8277         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8278         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8279         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8280         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8281         enum i40e_status_code status = I40E_SUCCESS;
8282
8283         if (pf->support_multi_driver) {
8284                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8285                 return I40E_NOT_SUPPORTED;
8286         }
8287
8288         /* For GTP-C */
8289         memset(&filter_replace, 0,
8290                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8291         memset(&filter_replace_buf, 0,
8292                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8293         /* create L1 filter */
8294         filter_replace.old_filter_type =
8295                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8296         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8297         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8298                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8299         /* Prepare the buffer, 2 entries */
8300         filter_replace_buf.data[0] =
8301                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8302         filter_replace_buf.data[0] |=
8303                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8304         filter_replace_buf.data[2] = 0xFF;
8305         filter_replace_buf.data[3] = 0xFF;
8306         filter_replace_buf.data[4] =
8307                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8308         filter_replace_buf.data[4] |=
8309                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8310         filter_replace_buf.data[6] = 0xFF;
8311         filter_replace_buf.data[7] = 0xFF;
8312         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8313                                                &filter_replace_buf);
8314         if (status < 0)
8315                 return status;
8316         if (filter_replace.old_filter_type !=
8317             filter_replace.new_filter_type)
8318                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8319                             " original: 0x%x, new: 0x%x",
8320                             dev->device->name,
8321                             filter_replace.old_filter_type,
8322                             filter_replace.new_filter_type);
8323
8324         /* for GTP-U */
8325         memset(&filter_replace, 0,
8326                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8327         memset(&filter_replace_buf, 0,
8328                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8329         /* create L1 filter */
8330         filter_replace.old_filter_type =
8331                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8332         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8333         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8334                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8335         /* Prepare the buffer, 2 entries */
8336         filter_replace_buf.data[0] =
8337                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8338         filter_replace_buf.data[0] |=
8339                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8340         filter_replace_buf.data[2] = 0xFF;
8341         filter_replace_buf.data[3] = 0xFF;
8342         filter_replace_buf.data[4] =
8343                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8344         filter_replace_buf.data[4] |=
8345                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8346         filter_replace_buf.data[6] = 0xFF;
8347         filter_replace_buf.data[7] = 0xFF;
8348
8349         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8350                                                &filter_replace_buf);
8351         if (!status && (filter_replace.old_filter_type !=
8352                         filter_replace.new_filter_type))
8353                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8354                             " original: 0x%x, new: 0x%x",
8355                             dev->device->name,
8356                             filter_replace.old_filter_type,
8357                             filter_replace.new_filter_type);
8358
8359         return status;
8360 }
8361
8362 static enum
8363 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8364 {
8365         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8366         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8367         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8368         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8369         enum i40e_status_code status = I40E_SUCCESS;
8370
8371         if (pf->support_multi_driver) {
8372                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8373                 return I40E_NOT_SUPPORTED;
8374         }
8375
8376         /* for GTP-C */
8377         memset(&filter_replace, 0,
8378                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8379         memset(&filter_replace_buf, 0,
8380                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8381         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8382         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8383         filter_replace.new_filter_type =
8384                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8385         /* Prepare the buffer, 2 entries */
8386         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8387         filter_replace_buf.data[0] |=
8388                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8389         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8390         filter_replace_buf.data[4] |=
8391                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8392         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8393                                                &filter_replace_buf);
8394         if (status < 0)
8395                 return status;
8396         if (filter_replace.old_filter_type !=
8397             filter_replace.new_filter_type)
8398                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8399                             " original: 0x%x, new: 0x%x",
8400                             dev->device->name,
8401                             filter_replace.old_filter_type,
8402                             filter_replace.new_filter_type);
8403
8404         /* for GTP-U */
8405         memset(&filter_replace, 0,
8406                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8407         memset(&filter_replace_buf, 0,
8408                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8409         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8410         filter_replace.old_filter_type =
8411                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8412         filter_replace.new_filter_type =
8413                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8414         /* Prepare the buffer, 2 entries */
8415         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8416         filter_replace_buf.data[0] |=
8417                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8418         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8419         filter_replace_buf.data[4] |=
8420                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8421
8422         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8423                                                &filter_replace_buf);
8424         if (!status && (filter_replace.old_filter_type !=
8425                         filter_replace.new_filter_type))
8426                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8427                             " original: 0x%x, new: 0x%x",
8428                             dev->device->name,
8429                             filter_replace.old_filter_type,
8430                             filter_replace.new_filter_type);
8431
8432         return status;
8433 }
8434
8435 static enum i40e_status_code
8436 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8437                             enum i40e_l4_port_type l4_port_type)
8438 {
8439         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8440         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8441         enum i40e_status_code status = I40E_SUCCESS;
8442         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8443         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8444
8445         if (pf->support_multi_driver) {
8446                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8447                 return I40E_NOT_SUPPORTED;
8448         }
8449
8450         memset(&filter_replace, 0,
8451                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8452         memset(&filter_replace_buf, 0,
8453                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8454
8455         /* create L1 filter */
8456         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8457                 filter_replace.old_filter_type =
8458                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8459                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8460                 filter_replace_buf.data[8] =
8461                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8462         } else {
8463                 filter_replace.old_filter_type =
8464                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8465                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8466                 filter_replace_buf.data[8] =
8467                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8468         }
8469
8470         filter_replace.tr_bit = 0;
8471         /* Prepare the buffer, 3 entries */
8472         filter_replace_buf.data[0] =
8473                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8474         filter_replace_buf.data[0] |=
8475                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8476         filter_replace_buf.data[2] = 0x00;
8477         filter_replace_buf.data[3] =
8478                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8479         filter_replace_buf.data[4] =
8480                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8481         filter_replace_buf.data[4] |=
8482                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8483         filter_replace_buf.data[5] = 0x00;
8484         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8485                 I40E_TR_L4_TYPE_TCP |
8486                 I40E_TR_L4_TYPE_SCTP;
8487         filter_replace_buf.data[7] = 0x00;
8488         filter_replace_buf.data[8] |=
8489                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8490         filter_replace_buf.data[9] = 0x00;
8491         filter_replace_buf.data[10] = 0xFF;
8492         filter_replace_buf.data[11] = 0xFF;
8493
8494         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8495                                                &filter_replace_buf);
8496         if (!status && filter_replace.old_filter_type !=
8497             filter_replace.new_filter_type)
8498                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8499                             " original: 0x%x, new: 0x%x",
8500                             dev->device->name,
8501                             filter_replace.old_filter_type,
8502                             filter_replace.new_filter_type);
8503
8504         return status;
8505 }
8506
8507 static enum i40e_status_code
8508 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8509                                enum i40e_l4_port_type l4_port_type)
8510 {
8511         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8512         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8513         enum i40e_status_code status = I40E_SUCCESS;
8514         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8515         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8516
8517         if (pf->support_multi_driver) {
8518                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8519                 return I40E_NOT_SUPPORTED;
8520         }
8521
8522         memset(&filter_replace, 0,
8523                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8524         memset(&filter_replace_buf, 0,
8525                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8526
8527         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8528                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8529                 filter_replace.new_filter_type =
8530                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8531                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8532         } else {
8533                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8534                 filter_replace.new_filter_type =
8535                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8536                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8537         }
8538
8539         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8540         filter_replace.tr_bit = 0;
8541         /* Prepare the buffer, 2 entries */
8542         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8543         filter_replace_buf.data[0] |=
8544                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8545         filter_replace_buf.data[4] |=
8546                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8547         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8548                                                &filter_replace_buf);
8549
8550         if (!status && filter_replace.old_filter_type !=
8551             filter_replace.new_filter_type)
8552                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8553                             " original: 0x%x, new: 0x%x",
8554                             dev->device->name,
8555                             filter_replace.old_filter_type,
8556                             filter_replace.new_filter_type);
8557
8558         return status;
8559 }
8560
8561 int
8562 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8563                       struct i40e_tunnel_filter_conf *tunnel_filter,
8564                       uint8_t add)
8565 {
8566         uint16_t ip_type;
8567         uint32_t ipv4_addr, ipv4_addr_le;
8568         uint8_t i, tun_type = 0;
8569         /* internal variable to convert ipv6 byte order */
8570         uint32_t convert_ipv6[4];
8571         int val, ret = 0;
8572         struct i40e_pf_vf *vf = NULL;
8573         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8574         struct i40e_vsi *vsi;
8575         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8576         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8577         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8578         struct i40e_tunnel_filter *tunnel, *node;
8579         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8580         uint32_t teid_le;
8581         bool big_buffer = 0;
8582
8583         cld_filter = rte_zmalloc("tunnel_filter",
8584                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8585                          0);
8586
8587         if (cld_filter == NULL) {
8588                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8589                 return -ENOMEM;
8590         }
8591         pfilter = cld_filter;
8592
8593         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8594                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8595         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8596                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8597
8598         pfilter->element.inner_vlan =
8599                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8600         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8601                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8602                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8603                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8604                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8605                                 &ipv4_addr_le,
8606                                 sizeof(pfilter->element.ipaddr.v4.data));
8607         } else {
8608                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8609                 for (i = 0; i < 4; i++) {
8610                         convert_ipv6[i] =
8611                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8612                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8613                 }
8614                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8615                            &convert_ipv6,
8616                            sizeof(pfilter->element.ipaddr.v6.data));
8617         }
8618
8619         /* check tunneled type */
8620         switch (tunnel_filter->tunnel_type) {
8621         case I40E_TUNNEL_TYPE_VXLAN:
8622                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8623                 break;
8624         case I40E_TUNNEL_TYPE_NVGRE:
8625                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8626                 break;
8627         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8628                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8629                 break;
8630         case I40E_TUNNEL_TYPE_MPLSoUDP:
8631                 if (!pf->mpls_replace_flag) {
8632                         i40e_replace_mpls_l1_filter(pf);
8633                         i40e_replace_mpls_cloud_filter(pf);
8634                         pf->mpls_replace_flag = 1;
8635                 }
8636                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8637                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8638                         teid_le >> 4;
8639                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8640                         (teid_le & 0xF) << 12;
8641                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8642                         0x40;
8643                 big_buffer = 1;
8644                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8645                 break;
8646         case I40E_TUNNEL_TYPE_MPLSoGRE:
8647                 if (!pf->mpls_replace_flag) {
8648                         i40e_replace_mpls_l1_filter(pf);
8649                         i40e_replace_mpls_cloud_filter(pf);
8650                         pf->mpls_replace_flag = 1;
8651                 }
8652                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8653                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8654                         teid_le >> 4;
8655                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8656                         (teid_le & 0xF) << 12;
8657                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8658                         0x0;
8659                 big_buffer = 1;
8660                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8661                 break;
8662         case I40E_TUNNEL_TYPE_GTPC:
8663                 if (!pf->gtp_replace_flag) {
8664                         i40e_replace_gtp_l1_filter(pf);
8665                         i40e_replace_gtp_cloud_filter(pf);
8666                         pf->gtp_replace_flag = 1;
8667                 }
8668                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8669                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8670                         (teid_le >> 16) & 0xFFFF;
8671                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8672                         teid_le & 0xFFFF;
8673                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8674                         0x0;
8675                 big_buffer = 1;
8676                 break;
8677         case I40E_TUNNEL_TYPE_GTPU:
8678                 if (!pf->gtp_replace_flag) {
8679                         i40e_replace_gtp_l1_filter(pf);
8680                         i40e_replace_gtp_cloud_filter(pf);
8681                         pf->gtp_replace_flag = 1;
8682                 }
8683                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8684                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8685                         (teid_le >> 16) & 0xFFFF;
8686                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8687                         teid_le & 0xFFFF;
8688                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8689                         0x0;
8690                 big_buffer = 1;
8691                 break;
8692         case I40E_TUNNEL_TYPE_QINQ:
8693                 if (!pf->qinq_replace_flag) {
8694                         ret = i40e_cloud_filter_qinq_create(pf);
8695                         if (ret < 0)
8696                                 PMD_DRV_LOG(DEBUG,
8697                                             "QinQ tunnel filter already created.");
8698                         pf->qinq_replace_flag = 1;
8699                 }
8700                 /*      Add in the General fields the values of
8701                  *      the Outer and Inner VLAN
8702                  *      Big Buffer should be set, see changes in
8703                  *      i40e_aq_add_cloud_filters
8704                  */
8705                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8706                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8707                 big_buffer = 1;
8708                 break;
8709         case I40E_CLOUD_TYPE_UDP:
8710         case I40E_CLOUD_TYPE_TCP:
8711         case I40E_CLOUD_TYPE_SCTP:
8712                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8713                         if (!pf->sport_replace_flag) {
8714                                 i40e_replace_port_l1_filter(pf,
8715                                                 tunnel_filter->l4_port_type);
8716                                 i40e_replace_port_cloud_filter(pf,
8717                                                 tunnel_filter->l4_port_type);
8718                                 pf->sport_replace_flag = 1;
8719                         }
8720                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8721                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8722                                 I40E_DIRECTION_INGRESS_KEY;
8723
8724                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8725                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8726                                         I40E_TR_L4_TYPE_UDP;
8727                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8728                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8729                                         I40E_TR_L4_TYPE_TCP;
8730                         else
8731                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8732                                         I40E_TR_L4_TYPE_SCTP;
8733
8734                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8735                                 (teid_le >> 16) & 0xFFFF;
8736                         big_buffer = 1;
8737                 } else {
8738                         if (!pf->dport_replace_flag) {
8739                                 i40e_replace_port_l1_filter(pf,
8740                                                 tunnel_filter->l4_port_type);
8741                                 i40e_replace_port_cloud_filter(pf,
8742                                                 tunnel_filter->l4_port_type);
8743                                 pf->dport_replace_flag = 1;
8744                         }
8745                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8746                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8747                                 I40E_DIRECTION_INGRESS_KEY;
8748
8749                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8750                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8751                                         I40E_TR_L4_TYPE_UDP;
8752                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8753                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8754                                         I40E_TR_L4_TYPE_TCP;
8755                         else
8756                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8757                                         I40E_TR_L4_TYPE_SCTP;
8758
8759                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8760                                 (teid_le >> 16) & 0xFFFF;
8761                         big_buffer = 1;
8762                 }
8763
8764                 break;
8765         default:
8766                 /* Other tunnel types is not supported. */
8767                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8768                 rte_free(cld_filter);
8769                 return -EINVAL;
8770         }
8771
8772         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8773                 pfilter->element.flags =
8774                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8775         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8776                 pfilter->element.flags =
8777                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8778         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8779                 pfilter->element.flags =
8780                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8781         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8782                 pfilter->element.flags =
8783                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8784         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8785                 pfilter->element.flags |=
8786                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8787         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8788                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8789                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8790                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8791                         pfilter->element.flags |=
8792                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8793                 else
8794                         pfilter->element.flags |=
8795                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8796         } else {
8797                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8798                                                 &pfilter->element.flags);
8799                 if (val < 0) {
8800                         rte_free(cld_filter);
8801                         return -EINVAL;
8802                 }
8803         }
8804
8805         pfilter->element.flags |= rte_cpu_to_le_16(
8806                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8807                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8808         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8809         pfilter->element.queue_number =
8810                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8811
8812         if (!tunnel_filter->is_to_vf)
8813                 vsi = pf->main_vsi;
8814         else {
8815                 if (tunnel_filter->vf_id >= pf->vf_num) {
8816                         PMD_DRV_LOG(ERR, "Invalid argument.");
8817                         rte_free(cld_filter);
8818                         return -EINVAL;
8819                 }
8820                 vf = &pf->vfs[tunnel_filter->vf_id];
8821                 vsi = vf->vsi;
8822         }
8823
8824         /* Check if there is the filter in SW list */
8825         memset(&check_filter, 0, sizeof(check_filter));
8826         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8827         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8828         check_filter.vf_id = tunnel_filter->vf_id;
8829         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8830         if (add && node) {
8831                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8832                 rte_free(cld_filter);
8833                 return -EINVAL;
8834         }
8835
8836         if (!add && !node) {
8837                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8838                 rte_free(cld_filter);
8839                 return -EINVAL;
8840         }
8841
8842         if (add) {
8843                 if (big_buffer)
8844                         ret = i40e_aq_add_cloud_filters_bb(hw,
8845                                                    vsi->seid, cld_filter, 1);
8846                 else
8847                         ret = i40e_aq_add_cloud_filters(hw,
8848                                         vsi->seid, &cld_filter->element, 1);
8849                 if (ret < 0) {
8850                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8851                         rte_free(cld_filter);
8852                         return -ENOTSUP;
8853                 }
8854                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8855                 if (tunnel == NULL) {
8856                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8857                         rte_free(cld_filter);
8858                         return -ENOMEM;
8859                 }
8860
8861                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8862                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8863                 if (ret < 0)
8864                         rte_free(tunnel);
8865         } else {
8866                 if (big_buffer)
8867                         ret = i40e_aq_rem_cloud_filters_bb(
8868                                 hw, vsi->seid, cld_filter, 1);
8869                 else
8870                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8871                                                 &cld_filter->element, 1);
8872                 if (ret < 0) {
8873                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8874                         rte_free(cld_filter);
8875                         return -ENOTSUP;
8876                 }
8877                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8878         }
8879
8880         rte_free(cld_filter);
8881         return ret;
8882 }
8883
8884 static int
8885 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8886 {
8887         uint8_t i;
8888
8889         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8890                 if (pf->vxlan_ports[i] == port)
8891                         return i;
8892         }
8893
8894         return -1;
8895 }
8896
8897 static int
8898 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8899 {
8900         int  idx, ret;
8901         uint8_t filter_idx = 0;
8902         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8903
8904         idx = i40e_get_vxlan_port_idx(pf, port);
8905
8906         /* Check if port already exists */
8907         if (idx >= 0) {
8908                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8909                 return -EINVAL;
8910         }
8911
8912         /* Now check if there is space to add the new port */
8913         idx = i40e_get_vxlan_port_idx(pf, 0);
8914         if (idx < 0) {
8915                 PMD_DRV_LOG(ERR,
8916                         "Maximum number of UDP ports reached, not adding port %d",
8917                         port);
8918                 return -ENOSPC;
8919         }
8920
8921         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8922                                         &filter_idx, NULL);
8923         if (ret < 0) {
8924                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8925                 return -1;
8926         }
8927
8928         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8929                          port,  filter_idx);
8930
8931         /* New port: add it and mark its index in the bitmap */
8932         pf->vxlan_ports[idx] = port;
8933         pf->vxlan_bitmap |= (1 << idx);
8934
8935         if (!(pf->flags & I40E_FLAG_VXLAN))
8936                 pf->flags |= I40E_FLAG_VXLAN;
8937
8938         return 0;
8939 }
8940
8941 static int
8942 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8943 {
8944         int idx;
8945         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8946
8947         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8948                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8949                 return -EINVAL;
8950         }
8951
8952         idx = i40e_get_vxlan_port_idx(pf, port);
8953
8954         if (idx < 0) {
8955                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8956                 return -EINVAL;
8957         }
8958
8959         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8960                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8961                 return -1;
8962         }
8963
8964         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8965                         port, idx);
8966
8967         pf->vxlan_ports[idx] = 0;
8968         pf->vxlan_bitmap &= ~(1 << idx);
8969
8970         if (!pf->vxlan_bitmap)
8971                 pf->flags &= ~I40E_FLAG_VXLAN;
8972
8973         return 0;
8974 }
8975
8976 /* Add UDP tunneling port */
8977 static int
8978 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8979                              struct rte_eth_udp_tunnel *udp_tunnel)
8980 {
8981         int ret = 0;
8982         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8983
8984         if (udp_tunnel == NULL)
8985                 return -EINVAL;
8986
8987         switch (udp_tunnel->prot_type) {
8988         case RTE_TUNNEL_TYPE_VXLAN:
8989                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8990                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8991                 break;
8992         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8993                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8994                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8995                 break;
8996         case RTE_TUNNEL_TYPE_GENEVE:
8997         case RTE_TUNNEL_TYPE_TEREDO:
8998                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8999                 ret = -1;
9000                 break;
9001
9002         default:
9003                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
9004                 ret = -1;
9005                 break;
9006         }
9007
9008         return ret;
9009 }
9010
9011 /* Remove UDP tunneling port */
9012 static int
9013 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
9014                              struct rte_eth_udp_tunnel *udp_tunnel)
9015 {
9016         int ret = 0;
9017         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9018
9019         if (udp_tunnel == NULL)
9020                 return -EINVAL;
9021
9022         switch (udp_tunnel->prot_type) {
9023         case RTE_TUNNEL_TYPE_VXLAN:
9024         case RTE_TUNNEL_TYPE_VXLAN_GPE:
9025                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
9026                 break;
9027         case RTE_TUNNEL_TYPE_GENEVE:
9028         case RTE_TUNNEL_TYPE_TEREDO:
9029                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
9030                 ret = -1;
9031                 break;
9032         default:
9033                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
9034                 ret = -1;
9035                 break;
9036         }
9037
9038         return ret;
9039 }
9040
9041 /* Calculate the maximum number of contiguous PF queues that are configured */
9042 static int
9043 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
9044 {
9045         struct rte_eth_dev_data *data = pf->dev_data;
9046         int i, num;
9047         struct i40e_rx_queue *rxq;
9048
9049         num = 0;
9050         for (i = 0; i < pf->lan_nb_qps; i++) {
9051                 rxq = data->rx_queues[i];
9052                 if (rxq && rxq->q_set)
9053                         num++;
9054                 else
9055                         break;
9056         }
9057
9058         return num;
9059 }
9060
9061 /* Configure RSS */
9062 static int
9063 i40e_pf_config_rss(struct i40e_pf *pf)
9064 {
9065         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9066         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9067         struct rte_eth_rss_conf rss_conf;
9068         uint32_t i, lut = 0;
9069         uint16_t j, num;
9070
9071         /*
9072          * If both VMDQ and RSS enabled, not all of PF queues are configured.
9073          * It's necessary to calculate the actual PF queues that are configured.
9074          */
9075         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
9076                 num = i40e_pf_calc_configured_queues_num(pf);
9077         else
9078                 num = pf->dev_data->nb_rx_queues;
9079
9080         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
9081         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
9082                         num);
9083
9084         if (num == 0) {
9085                 PMD_INIT_LOG(ERR,
9086                         "No PF queues are configured to enable RSS for port %u",
9087                         pf->dev_data->port_id);
9088                 return -ENOTSUP;
9089         }
9090
9091         if (pf->adapter->rss_reta_updated == 0) {
9092                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
9093                         if (j == num)
9094                                 j = 0;
9095                         lut = (lut << 8) | (j & ((0x1 <<
9096                                 hw->func_caps.rss_table_entry_width) - 1));
9097                         if ((i & 3) == 3)
9098                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
9099                                                rte_bswap32(lut));
9100                 }
9101         }
9102
9103         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
9104         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
9105             !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
9106                 i40e_pf_disable_rss(pf);
9107                 return 0;
9108         }
9109         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
9110                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
9111                 /* Random default keys */
9112                 static uint32_t rss_key_default[] = {0x6b793944,
9113                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
9114                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9115                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9116
9117                 rss_conf.rss_key = (uint8_t *)rss_key_default;
9118                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9119                                                         sizeof(uint32_t);
9120         }
9121
9122         return i40e_hw_rss_hash_set(pf, &rss_conf);
9123 }
9124
9125 static int
9126 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9127                                struct rte_eth_tunnel_filter_conf *filter)
9128 {
9129         if (pf == NULL || filter == NULL) {
9130                 PMD_DRV_LOG(ERR, "Invalid parameter");
9131                 return -EINVAL;
9132         }
9133
9134         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9135                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9136                 return -EINVAL;
9137         }
9138
9139         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9140                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9141                 return -EINVAL;
9142         }
9143
9144         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9145                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9146                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9147                 return -EINVAL;
9148         }
9149
9150         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9151                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9152                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9153                 return -EINVAL;
9154         }
9155
9156         return 0;
9157 }
9158
9159 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9160 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
9161 int
9162 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9163 {
9164         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9165         uint32_t val, reg;
9166         int ret = -EINVAL;
9167
9168         if (pf->support_multi_driver) {
9169                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9170                 return -ENOTSUP;
9171         }
9172
9173         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9174         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9175
9176         if (len == 3) {
9177                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9178         } else if (len == 4) {
9179                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9180         } else {
9181                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9182                 return ret;
9183         }
9184
9185         if (reg != val) {
9186                 ret = i40e_aq_debug_write_global_register(hw,
9187                                                    I40E_GL_PRS_FVBM(2),
9188                                                    reg, NULL);
9189                 if (ret != 0)
9190                         return ret;
9191                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9192                             "with value 0x%08x",
9193                             I40E_GL_PRS_FVBM(2), reg);
9194         } else {
9195                 ret = 0;
9196         }
9197         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9198                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9199
9200         return ret;
9201 }
9202
9203 static int
9204 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9205 {
9206         int ret = -EINVAL;
9207
9208         if (!hw || !cfg)
9209                 return -EINVAL;
9210
9211         switch (cfg->cfg_type) {
9212         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9213                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9214                 break;
9215         default:
9216                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9217                 break;
9218         }
9219
9220         return ret;
9221 }
9222
9223 static int
9224 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9225                                enum rte_filter_op filter_op,
9226                                void *arg)
9227 {
9228         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9229         int ret = I40E_ERR_PARAM;
9230
9231         switch (filter_op) {
9232         case RTE_ETH_FILTER_SET:
9233                 ret = i40e_dev_global_config_set(hw,
9234                         (struct rte_eth_global_cfg *)arg);
9235                 break;
9236         default:
9237                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9238                 break;
9239         }
9240
9241         return ret;
9242 }
9243
9244 static int
9245 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9246                           enum rte_filter_op filter_op,
9247                           void *arg)
9248 {
9249         struct rte_eth_tunnel_filter_conf *filter;
9250         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9251         int ret = I40E_SUCCESS;
9252
9253         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9254
9255         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9256                 return I40E_ERR_PARAM;
9257
9258         switch (filter_op) {
9259         case RTE_ETH_FILTER_NOP:
9260                 if (!(pf->flags & I40E_FLAG_VXLAN))
9261                         ret = I40E_NOT_SUPPORTED;
9262                 break;
9263         case RTE_ETH_FILTER_ADD:
9264                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9265                 break;
9266         case RTE_ETH_FILTER_DELETE:
9267                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9268                 break;
9269         default:
9270                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9271                 ret = I40E_ERR_PARAM;
9272                 break;
9273         }
9274
9275         return ret;
9276 }
9277
9278 /* Get the symmetric hash enable configurations per port */
9279 static void
9280 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9281 {
9282         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9283
9284         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9285 }
9286
9287 /* Set the symmetric hash enable configurations per port */
9288 static void
9289 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9290 {
9291         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9292
9293         if (enable > 0) {
9294                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9295                         PMD_DRV_LOG(INFO,
9296                                 "Symmetric hash has already been enabled");
9297                         return;
9298                 }
9299                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9300         } else {
9301                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9302                         PMD_DRV_LOG(INFO,
9303                                 "Symmetric hash has already been disabled");
9304                         return;
9305                 }
9306                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9307         }
9308         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9309         I40E_WRITE_FLUSH(hw);
9310 }
9311
9312 /*
9313  * Get global configurations of hash function type and symmetric hash enable
9314  * per flow type (pctype). Note that global configuration means it affects all
9315  * the ports on the same NIC.
9316  */
9317 static int
9318 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9319                                    struct rte_eth_hash_global_conf *g_cfg)
9320 {
9321         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9322         uint32_t reg;
9323         uint16_t i, j;
9324
9325         memset(g_cfg, 0, sizeof(*g_cfg));
9326         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9327         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9328                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9329         else
9330                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9331         PMD_DRV_LOG(DEBUG, "Hash function is %s",
9332                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9333
9334         /*
9335          * As i40e supports less than 64 flow types, only first 64 bits need to
9336          * be checked.
9337          */
9338         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9339                 g_cfg->valid_bit_mask[i] = 0ULL;
9340                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9341         }
9342
9343         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9344
9345         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9346                 if (!adapter->pctypes_tbl[i])
9347                         continue;
9348                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9349                      j < I40E_FILTER_PCTYPE_MAX; j++) {
9350                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9351                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9352                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9353                                         g_cfg->sym_hash_enable_mask[0] |=
9354                                                                 (1ULL << i);
9355                                 }
9356                         }
9357                 }
9358         }
9359
9360         return 0;
9361 }
9362
9363 static int
9364 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9365                               const struct rte_eth_hash_global_conf *g_cfg)
9366 {
9367         uint32_t i;
9368         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9369
9370         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9371                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9372                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9373                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9374                                                 g_cfg->hash_func);
9375                 return -EINVAL;
9376         }
9377
9378         /*
9379          * As i40e supports less than 64 flow types, only first 64 bits need to
9380          * be checked.
9381          */
9382         mask0 = g_cfg->valid_bit_mask[0];
9383         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9384                 if (i == 0) {
9385                         /* Check if any unsupported flow type configured */
9386                         if ((mask0 | i40e_mask) ^ i40e_mask)
9387                                 goto mask_err;
9388                 } else {
9389                         if (g_cfg->valid_bit_mask[i])
9390                                 goto mask_err;
9391                 }
9392         }
9393
9394         return 0;
9395
9396 mask_err:
9397         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9398
9399         return -EINVAL;
9400 }
9401
9402 /*
9403  * Set global configurations of hash function type and symmetric hash enable
9404  * per flow type (pctype). Note any modifying global configuration will affect
9405  * all the ports on the same NIC.
9406  */
9407 static int
9408 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9409                                    struct rte_eth_hash_global_conf *g_cfg)
9410 {
9411         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9412         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9413         int ret;
9414         uint16_t i, j;
9415         uint32_t reg;
9416         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9417
9418         if (pf->support_multi_driver) {
9419                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9420                 return -ENOTSUP;
9421         }
9422
9423         /* Check the input parameters */
9424         ret = i40e_hash_global_config_check(adapter, g_cfg);
9425         if (ret < 0)
9426                 return ret;
9427
9428         /*
9429          * As i40e supports less than 64 flow types, only first 64 bits need to
9430          * be configured.
9431          */
9432         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9433                 if (mask0 & (1UL << i)) {
9434                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9435                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9436
9437                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9438                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9439                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9440                                         i40e_write_global_rx_ctl(hw,
9441                                                           I40E_GLQF_HSYM(j),
9442                                                           reg);
9443                         }
9444                 }
9445         }
9446
9447         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9448         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9449                 /* Toeplitz */
9450                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9451                         PMD_DRV_LOG(DEBUG,
9452                                 "Hash function already set to Toeplitz");
9453                         goto out;
9454                 }
9455                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9456         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9457                 /* Simple XOR */
9458                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9459                         PMD_DRV_LOG(DEBUG,
9460                                 "Hash function already set to Simple XOR");
9461                         goto out;
9462                 }
9463                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9464         } else
9465                 /* Use the default, and keep it as it is */
9466                 goto out;
9467
9468         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9469
9470 out:
9471         I40E_WRITE_FLUSH(hw);
9472
9473         return 0;
9474 }
9475
9476 /**
9477  * Valid input sets for hash and flow director filters per PCTYPE
9478  */
9479 static uint64_t
9480 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9481                 enum rte_filter_type filter)
9482 {
9483         uint64_t valid;
9484
9485         static const uint64_t valid_hash_inset_table[] = {
9486                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9487                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9488                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9489                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9490                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9491                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9492                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9493                         I40E_INSET_FLEX_PAYLOAD,
9494                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9495                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9496                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9497                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9498                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9499                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9500                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9501                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9502                         I40E_INSET_FLEX_PAYLOAD,
9503                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9504                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9505                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9506                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9507                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9508                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9509                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9510                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9511                         I40E_INSET_FLEX_PAYLOAD,
9512                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9513                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9514                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9515                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9516                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9517                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9518                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9519                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9520                         I40E_INSET_FLEX_PAYLOAD,
9521                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9522                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9523                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9524                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9525                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9526                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9527                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9528                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9529                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9530                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9531                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9532                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9533                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9534                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9535                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9536                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9537                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9538                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9539                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9540                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9541                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9542                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9543                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9544                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9545                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9546                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9547                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9548                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9549                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9550                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9551                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9552                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9553                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9554                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9555                         I40E_INSET_FLEX_PAYLOAD,
9556                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9557                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9558                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9559                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9560                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9561                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9562                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9563                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9564                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9565                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9566                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9567                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9568                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9569                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9570                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9571                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9572                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9573                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9574                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9575                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9576                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9577                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9578                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9579                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9580                         I40E_INSET_FLEX_PAYLOAD,
9581                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9582                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9583                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9584                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9585                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9586                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9587                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9588                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9589                         I40E_INSET_FLEX_PAYLOAD,
9590                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9591                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9592                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9593                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9594                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9595                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9596                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9597                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9598                         I40E_INSET_FLEX_PAYLOAD,
9599                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9600                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9601                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9602                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9603                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9604                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9605                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9606                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9607                         I40E_INSET_FLEX_PAYLOAD,
9608                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9609                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9610                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9611                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9612                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9613                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9614                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9615                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9616                         I40E_INSET_FLEX_PAYLOAD,
9617                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9618                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9619                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9620                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9621                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9622                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9623                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9624                         I40E_INSET_FLEX_PAYLOAD,
9625                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9626                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9627                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9628                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9629                         I40E_INSET_FLEX_PAYLOAD,
9630         };
9631
9632         /**
9633          * Flow director supports only fields defined in
9634          * union rte_eth_fdir_flow.
9635          */
9636         static const uint64_t valid_fdir_inset_table[] = {
9637                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9638                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9639                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9640                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9641                 I40E_INSET_IPV4_TTL,
9642                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9643                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9644                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9645                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9646                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9647                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9648                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9649                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9650                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9651                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9652                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9653                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9654                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9655                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9656                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9657                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9658                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9659                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9660                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9661                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9662                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9663                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9664                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9665                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9666                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9667                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9668                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9669                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9670                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9671                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9672                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9673                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9674                 I40E_INSET_SCTP_VT,
9675                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9676                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9677                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9678                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9679                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9680                 I40E_INSET_IPV4_TTL,
9681                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9682                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9683                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9684                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9685                 I40E_INSET_IPV6_HOP_LIMIT,
9686                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9687                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9688                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9689                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9690                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9691                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9692                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9693                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9694                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9695                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9696                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9697                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9698                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9699                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9700                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9701                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9702                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9703                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9704                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9705                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9706                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9707                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9708                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9709                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9710                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9711                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9712                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9713                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9714                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9715                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9716                 I40E_INSET_SCTP_VT,
9717                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9718                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9719                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9720                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9721                 I40E_INSET_IPV6_HOP_LIMIT,
9722                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9723                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9724                 I40E_INSET_LAST_ETHER_TYPE,
9725         };
9726
9727         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9728                 return 0;
9729         if (filter == RTE_ETH_FILTER_HASH)
9730                 valid = valid_hash_inset_table[pctype];
9731         else
9732                 valid = valid_fdir_inset_table[pctype];
9733
9734         return valid;
9735 }
9736
9737 /**
9738  * Validate if the input set is allowed for a specific PCTYPE
9739  */
9740 int
9741 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9742                 enum rte_filter_type filter, uint64_t inset)
9743 {
9744         uint64_t valid;
9745
9746         valid = i40e_get_valid_input_set(pctype, filter);
9747         if (inset & (~valid))
9748                 return -EINVAL;
9749
9750         return 0;
9751 }
9752
9753 /* default input set fields combination per pctype */
9754 uint64_t
9755 i40e_get_default_input_set(uint16_t pctype)
9756 {
9757         static const uint64_t default_inset_table[] = {
9758                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9759                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9760                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9761                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9762                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9763                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9764                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9765                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9766                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9767                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9768                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9769                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9770                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9771                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9772                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9773                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9774                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9775                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9776                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9777                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9778                         I40E_INSET_SCTP_VT,
9779                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9780                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9781                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9782                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9783                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9784                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9785                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9786                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9787                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9788                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9789                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9790                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9791                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9792                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9793                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9794                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9795                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9796                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9797                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9798                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9799                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9800                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9801                         I40E_INSET_SCTP_VT,
9802                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9803                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9804                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9805                         I40E_INSET_LAST_ETHER_TYPE,
9806         };
9807
9808         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9809                 return 0;
9810
9811         return default_inset_table[pctype];
9812 }
9813
9814 /**
9815  * Parse the input set from index to logical bit masks
9816  */
9817 static int
9818 i40e_parse_input_set(uint64_t *inset,
9819                      enum i40e_filter_pctype pctype,
9820                      enum rte_eth_input_set_field *field,
9821                      uint16_t size)
9822 {
9823         uint16_t i, j;
9824         int ret = -EINVAL;
9825
9826         static const struct {
9827                 enum rte_eth_input_set_field field;
9828                 uint64_t inset;
9829         } inset_convert_table[] = {
9830                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9831                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9832                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9833                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9834                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9835                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9836                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9837                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9838                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9839                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9840                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9841                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9842                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9843                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9844                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9845                         I40E_INSET_IPV6_NEXT_HDR},
9846                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9847                         I40E_INSET_IPV6_HOP_LIMIT},
9848                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9849                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9850                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9851                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9852                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9853                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9854                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9855                         I40E_INSET_SCTP_VT},
9856                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9857                         I40E_INSET_TUNNEL_DMAC},
9858                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9859                         I40E_INSET_VLAN_TUNNEL},
9860                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9861                         I40E_INSET_TUNNEL_ID},
9862                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9863                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9864                         I40E_INSET_FLEX_PAYLOAD_W1},
9865                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9866                         I40E_INSET_FLEX_PAYLOAD_W2},
9867                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9868                         I40E_INSET_FLEX_PAYLOAD_W3},
9869                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9870                         I40E_INSET_FLEX_PAYLOAD_W4},
9871                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9872                         I40E_INSET_FLEX_PAYLOAD_W5},
9873                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9874                         I40E_INSET_FLEX_PAYLOAD_W6},
9875                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9876                         I40E_INSET_FLEX_PAYLOAD_W7},
9877                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9878                         I40E_INSET_FLEX_PAYLOAD_W8},
9879         };
9880
9881         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9882                 return ret;
9883
9884         /* Only one item allowed for default or all */
9885         if (size == 1) {
9886                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9887                         *inset = i40e_get_default_input_set(pctype);
9888                         return 0;
9889                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9890                         *inset = I40E_INSET_NONE;
9891                         return 0;
9892                 }
9893         }
9894
9895         for (i = 0, *inset = 0; i < size; i++) {
9896                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9897                         if (field[i] == inset_convert_table[j].field) {
9898                                 *inset |= inset_convert_table[j].inset;
9899                                 break;
9900                         }
9901                 }
9902
9903                 /* It contains unsupported input set, return immediately */
9904                 if (j == RTE_DIM(inset_convert_table))
9905                         return ret;
9906         }
9907
9908         return 0;
9909 }
9910
9911 /**
9912  * Translate the input set from bit masks to register aware bit masks
9913  * and vice versa
9914  */
9915 uint64_t
9916 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9917 {
9918         uint64_t val = 0;
9919         uint16_t i;
9920
9921         struct inset_map {
9922                 uint64_t inset;
9923                 uint64_t inset_reg;
9924         };
9925
9926         static const struct inset_map inset_map_common[] = {
9927                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9928                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9929                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9930                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9931                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9932                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9933                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9934                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9935                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9936                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9937                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9938                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9939                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9940                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9941                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9942                 {I40E_INSET_TUNNEL_DMAC,
9943                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9944                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9945                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9946                 {I40E_INSET_TUNNEL_SRC_PORT,
9947                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9948                 {I40E_INSET_TUNNEL_DST_PORT,
9949                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9950                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9951                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9952                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9953                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9954                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9955                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9956                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9957                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9958                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9959         };
9960
9961     /* some different registers map in x722*/
9962         static const struct inset_map inset_map_diff_x722[] = {
9963                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9964                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9965                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9966                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9967         };
9968
9969         static const struct inset_map inset_map_diff_not_x722[] = {
9970                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9971                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9972                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9973                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9974         };
9975
9976         if (input == 0)
9977                 return val;
9978
9979         /* Translate input set to register aware inset */
9980         if (type == I40E_MAC_X722) {
9981                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9982                         if (input & inset_map_diff_x722[i].inset)
9983                                 val |= inset_map_diff_x722[i].inset_reg;
9984                 }
9985         } else {
9986                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9987                         if (input & inset_map_diff_not_x722[i].inset)
9988                                 val |= inset_map_diff_not_x722[i].inset_reg;
9989                 }
9990         }
9991
9992         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9993                 if (input & inset_map_common[i].inset)
9994                         val |= inset_map_common[i].inset_reg;
9995         }
9996
9997         return val;
9998 }
9999
10000 int
10001 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
10002 {
10003         uint8_t i, idx = 0;
10004         uint64_t inset_need_mask = inset;
10005
10006         static const struct {
10007                 uint64_t inset;
10008                 uint32_t mask;
10009         } inset_mask_map[] = {
10010                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
10011                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
10012                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
10013                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
10014                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
10015                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
10016                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
10017                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
10018         };
10019
10020         if (!inset || !mask || !nb_elem)
10021                 return 0;
10022
10023         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10024                 /* Clear the inset bit, if no MASK is required,
10025                  * for example proto + ttl
10026                  */
10027                 if ((inset & inset_mask_map[i].inset) ==
10028                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
10029                         inset_need_mask &= ~inset_mask_map[i].inset;
10030                 if (!inset_need_mask)
10031                         return 0;
10032         }
10033         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10034                 if ((inset_need_mask & inset_mask_map[i].inset) ==
10035                     inset_mask_map[i].inset) {
10036                         if (idx >= nb_elem) {
10037                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
10038                                 return -EINVAL;
10039                         }
10040                         mask[idx] = inset_mask_map[i].mask;
10041                         idx++;
10042                 }
10043         }
10044
10045         return idx;
10046 }
10047
10048 void
10049 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10050 {
10051         uint32_t reg = i40e_read_rx_ctl(hw, addr);
10052
10053         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
10054         if (reg != val)
10055                 i40e_write_rx_ctl(hw, addr, val);
10056         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
10057                     (uint32_t)i40e_read_rx_ctl(hw, addr));
10058 }
10059
10060 void
10061 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10062 {
10063         uint32_t reg = i40e_read_rx_ctl(hw, addr);
10064         struct rte_eth_dev *dev;
10065
10066         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
10067         if (reg != val) {
10068                 i40e_write_rx_ctl(hw, addr, val);
10069                 PMD_DRV_LOG(WARNING,
10070                             "i40e device %s changed global register [0x%08x]."
10071                             " original: 0x%08x, new: 0x%08x",
10072                             dev->device->name, addr, reg,
10073                             (uint32_t)i40e_read_rx_ctl(hw, addr));
10074         }
10075 }
10076
10077 static void
10078 i40e_filter_input_set_init(struct i40e_pf *pf)
10079 {
10080         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10081         enum i40e_filter_pctype pctype;
10082         uint64_t input_set, inset_reg;
10083         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10084         int num, i;
10085         uint16_t flow_type;
10086
10087         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
10088              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
10089                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
10090
10091                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
10092                         continue;
10093
10094                 input_set = i40e_get_default_input_set(pctype);
10095
10096                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10097                                                    I40E_INSET_MASK_NUM_REG);
10098                 if (num < 0)
10099                         return;
10100                 if (pf->support_multi_driver && num > 0) {
10101                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10102                         return;
10103                 }
10104                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
10105                                         input_set);
10106
10107                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10108                                       (uint32_t)(inset_reg & UINT32_MAX));
10109                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10110                                      (uint32_t)((inset_reg >>
10111                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
10112                 if (!pf->support_multi_driver) {
10113                         i40e_check_write_global_reg(hw,
10114                                             I40E_GLQF_HASH_INSET(0, pctype),
10115                                             (uint32_t)(inset_reg & UINT32_MAX));
10116                         i40e_check_write_global_reg(hw,
10117                                              I40E_GLQF_HASH_INSET(1, pctype),
10118                                              (uint32_t)((inset_reg >>
10119                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
10120
10121                         for (i = 0; i < num; i++) {
10122                                 i40e_check_write_global_reg(hw,
10123                                                     I40E_GLQF_FD_MSK(i, pctype),
10124                                                     mask_reg[i]);
10125                                 i40e_check_write_global_reg(hw,
10126                                                   I40E_GLQF_HASH_MSK(i, pctype),
10127                                                   mask_reg[i]);
10128                         }
10129                         /*clear unused mask registers of the pctype */
10130                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10131                                 i40e_check_write_global_reg(hw,
10132                                                     I40E_GLQF_FD_MSK(i, pctype),
10133                                                     0);
10134                                 i40e_check_write_global_reg(hw,
10135                                                   I40E_GLQF_HASH_MSK(i, pctype),
10136                                                   0);
10137                         }
10138                 } else {
10139                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10140                 }
10141                 I40E_WRITE_FLUSH(hw);
10142
10143                 /* store the default input set */
10144                 if (!pf->support_multi_driver)
10145                         pf->hash_input_set[pctype] = input_set;
10146                 pf->fdir.input_set[pctype] = input_set;
10147         }
10148 }
10149
10150 int
10151 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10152                          struct rte_eth_input_set_conf *conf)
10153 {
10154         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10155         enum i40e_filter_pctype pctype;
10156         uint64_t input_set, inset_reg = 0;
10157         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10158         int ret, i, num;
10159
10160         if (!conf) {
10161                 PMD_DRV_LOG(ERR, "Invalid pointer");
10162                 return -EFAULT;
10163         }
10164         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10165             conf->op != RTE_ETH_INPUT_SET_ADD) {
10166                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10167                 return -EINVAL;
10168         }
10169
10170         if (pf->support_multi_driver) {
10171                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10172                 return -ENOTSUP;
10173         }
10174
10175         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10176         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10177                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10178                 return -EINVAL;
10179         }
10180
10181         if (hw->mac.type == I40E_MAC_X722) {
10182                 /* get translated pctype value in fd pctype register */
10183                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10184                         I40E_GLQF_FD_PCTYPES((int)pctype));
10185         }
10186
10187         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10188                                    conf->inset_size);
10189         if (ret) {
10190                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10191                 return -EINVAL;
10192         }
10193
10194         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10195                 /* get inset value in register */
10196                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10197                 inset_reg <<= I40E_32_BIT_WIDTH;
10198                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10199                 input_set |= pf->hash_input_set[pctype];
10200         }
10201         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10202                                            I40E_INSET_MASK_NUM_REG);
10203         if (num < 0)
10204                 return -EINVAL;
10205
10206         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10207
10208         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10209                                     (uint32_t)(inset_reg & UINT32_MAX));
10210         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10211                                     (uint32_t)((inset_reg >>
10212                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
10213
10214         for (i = 0; i < num; i++)
10215                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10216                                             mask_reg[i]);
10217         /*clear unused mask registers of the pctype */
10218         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10219                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10220                                             0);
10221         I40E_WRITE_FLUSH(hw);
10222
10223         pf->hash_input_set[pctype] = input_set;
10224         return 0;
10225 }
10226
10227 int
10228 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10229                          struct rte_eth_input_set_conf *conf)
10230 {
10231         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10232         enum i40e_filter_pctype pctype;
10233         uint64_t input_set, inset_reg = 0;
10234         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10235         int ret, i, num;
10236
10237         if (!hw || !conf) {
10238                 PMD_DRV_LOG(ERR, "Invalid pointer");
10239                 return -EFAULT;
10240         }
10241         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10242             conf->op != RTE_ETH_INPUT_SET_ADD) {
10243                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10244                 return -EINVAL;
10245         }
10246
10247         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10248
10249         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10250                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10251                 return -EINVAL;
10252         }
10253
10254         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10255                                    conf->inset_size);
10256         if (ret) {
10257                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10258                 return -EINVAL;
10259         }
10260
10261         /* get inset value in register */
10262         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10263         inset_reg <<= I40E_32_BIT_WIDTH;
10264         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10265
10266         /* Can not change the inset reg for flex payload for fdir,
10267          * it is done by writing I40E_PRTQF_FD_FLXINSET
10268          * in i40e_set_flex_mask_on_pctype.
10269          */
10270         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10271                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10272         else
10273                 input_set |= pf->fdir.input_set[pctype];
10274         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10275                                            I40E_INSET_MASK_NUM_REG);
10276         if (num < 0)
10277                 return -EINVAL;
10278         if (pf->support_multi_driver && num > 0) {
10279                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10280                 return -ENOTSUP;
10281         }
10282
10283         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10284
10285         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10286                               (uint32_t)(inset_reg & UINT32_MAX));
10287         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10288                              (uint32_t)((inset_reg >>
10289                              I40E_32_BIT_WIDTH) & UINT32_MAX));
10290
10291         if (!pf->support_multi_driver) {
10292                 for (i = 0; i < num; i++)
10293                         i40e_check_write_global_reg(hw,
10294                                                     I40E_GLQF_FD_MSK(i, pctype),
10295                                                     mask_reg[i]);
10296                 /*clear unused mask registers of the pctype */
10297                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10298                         i40e_check_write_global_reg(hw,
10299                                                     I40E_GLQF_FD_MSK(i, pctype),
10300                                                     0);
10301         } else {
10302                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10303         }
10304         I40E_WRITE_FLUSH(hw);
10305
10306         pf->fdir.input_set[pctype] = input_set;
10307         return 0;
10308 }
10309
10310 static int
10311 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10312 {
10313         int ret = 0;
10314
10315         if (!hw || !info) {
10316                 PMD_DRV_LOG(ERR, "Invalid pointer");
10317                 return -EFAULT;
10318         }
10319
10320         switch (info->info_type) {
10321         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10322                 i40e_get_symmetric_hash_enable_per_port(hw,
10323                                         &(info->info.enable));
10324                 break;
10325         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10326                 ret = i40e_get_hash_filter_global_config(hw,
10327                                 &(info->info.global_conf));
10328                 break;
10329         default:
10330                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10331                                                         info->info_type);
10332                 ret = -EINVAL;
10333                 break;
10334         }
10335
10336         return ret;
10337 }
10338
10339 static int
10340 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10341 {
10342         int ret = 0;
10343
10344         if (!hw || !info) {
10345                 PMD_DRV_LOG(ERR, "Invalid pointer");
10346                 return -EFAULT;
10347         }
10348
10349         switch (info->info_type) {
10350         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10351                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10352                 break;
10353         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10354                 ret = i40e_set_hash_filter_global_config(hw,
10355                                 &(info->info.global_conf));
10356                 break;
10357         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10358                 ret = i40e_hash_filter_inset_select(hw,
10359                                                &(info->info.input_set_conf));
10360                 break;
10361
10362         default:
10363                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10364                                                         info->info_type);
10365                 ret = -EINVAL;
10366                 break;
10367         }
10368
10369         return ret;
10370 }
10371
10372 /* Operations for hash function */
10373 static int
10374 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10375                       enum rte_filter_op filter_op,
10376                       void *arg)
10377 {
10378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10379         int ret = 0;
10380
10381         switch (filter_op) {
10382         case RTE_ETH_FILTER_NOP:
10383                 break;
10384         case RTE_ETH_FILTER_GET:
10385                 ret = i40e_hash_filter_get(hw,
10386                         (struct rte_eth_hash_filter_info *)arg);
10387                 break;
10388         case RTE_ETH_FILTER_SET:
10389                 ret = i40e_hash_filter_set(hw,
10390                         (struct rte_eth_hash_filter_info *)arg);
10391                 break;
10392         default:
10393                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10394                                                                 filter_op);
10395                 ret = -ENOTSUP;
10396                 break;
10397         }
10398
10399         return ret;
10400 }
10401
10402 /* Convert ethertype filter structure */
10403 static int
10404 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10405                               struct i40e_ethertype_filter *filter)
10406 {
10407         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10408                 RTE_ETHER_ADDR_LEN);
10409         filter->input.ether_type = input->ether_type;
10410         filter->flags = input->flags;
10411         filter->queue = input->queue;
10412
10413         return 0;
10414 }
10415
10416 /* Check if there exists the ehtertype filter */
10417 struct i40e_ethertype_filter *
10418 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10419                                 const struct i40e_ethertype_filter_input *input)
10420 {
10421         int ret;
10422
10423         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10424         if (ret < 0)
10425                 return NULL;
10426
10427         return ethertype_rule->hash_map[ret];
10428 }
10429
10430 /* Add ethertype filter in SW list */
10431 static int
10432 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10433                                 struct i40e_ethertype_filter *filter)
10434 {
10435         struct i40e_ethertype_rule *rule = &pf->ethertype;
10436         int ret;
10437
10438         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10439         if (ret < 0) {
10440                 PMD_DRV_LOG(ERR,
10441                             "Failed to insert ethertype filter"
10442                             " to hash table %d!",
10443                             ret);
10444                 return ret;
10445         }
10446         rule->hash_map[ret] = filter;
10447
10448         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10449
10450         return 0;
10451 }
10452
10453 /* Delete ethertype filter in SW list */
10454 int
10455 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10456                              struct i40e_ethertype_filter_input *input)
10457 {
10458         struct i40e_ethertype_rule *rule = &pf->ethertype;
10459         struct i40e_ethertype_filter *filter;
10460         int ret;
10461
10462         ret = rte_hash_del_key(rule->hash_table, input);
10463         if (ret < 0) {
10464                 PMD_DRV_LOG(ERR,
10465                             "Failed to delete ethertype filter"
10466                             " to hash table %d!",
10467                             ret);
10468                 return ret;
10469         }
10470         filter = rule->hash_map[ret];
10471         rule->hash_map[ret] = NULL;
10472
10473         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10474         rte_free(filter);
10475
10476         return 0;
10477 }
10478
10479 /*
10480  * Configure ethertype filter, which can director packet by filtering
10481  * with mac address and ether_type or only ether_type
10482  */
10483 int
10484 i40e_ethertype_filter_set(struct i40e_pf *pf,
10485                         struct rte_eth_ethertype_filter *filter,
10486                         bool add)
10487 {
10488         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10489         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10490         struct i40e_ethertype_filter *ethertype_filter, *node;
10491         struct i40e_ethertype_filter check_filter;
10492         struct i40e_control_filter_stats stats;
10493         uint16_t flags = 0;
10494         int ret;
10495
10496         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10497                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10498                 return -EINVAL;
10499         }
10500         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10501                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10502                 PMD_DRV_LOG(ERR,
10503                         "unsupported ether_type(0x%04x) in control packet filter.",
10504                         filter->ether_type);
10505                 return -EINVAL;
10506         }
10507         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10508                 PMD_DRV_LOG(WARNING,
10509                         "filter vlan ether_type in first tag is not supported.");
10510
10511         /* Check if there is the filter in SW list */
10512         memset(&check_filter, 0, sizeof(check_filter));
10513         i40e_ethertype_filter_convert(filter, &check_filter);
10514         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10515                                                &check_filter.input);
10516         if (add && node) {
10517                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10518                 return -EINVAL;
10519         }
10520
10521         if (!add && !node) {
10522                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10523                 return -EINVAL;
10524         }
10525
10526         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10527                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10528         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10529                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10530         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10531
10532         memset(&stats, 0, sizeof(stats));
10533         ret = i40e_aq_add_rem_control_packet_filter(hw,
10534                         filter->mac_addr.addr_bytes,
10535                         filter->ether_type, flags,
10536                         pf->main_vsi->seid,
10537                         filter->queue, add, &stats, NULL);
10538
10539         PMD_DRV_LOG(INFO,
10540                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10541                 ret, stats.mac_etype_used, stats.etype_used,
10542                 stats.mac_etype_free, stats.etype_free);
10543         if (ret < 0)
10544                 return -ENOSYS;
10545
10546         /* Add or delete a filter in SW list */
10547         if (add) {
10548                 ethertype_filter = rte_zmalloc("ethertype_filter",
10549                                        sizeof(*ethertype_filter), 0);
10550                 if (ethertype_filter == NULL) {
10551                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10552                         return -ENOMEM;
10553                 }
10554
10555                 rte_memcpy(ethertype_filter, &check_filter,
10556                            sizeof(check_filter));
10557                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10558                 if (ret < 0)
10559                         rte_free(ethertype_filter);
10560         } else {
10561                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10562         }
10563
10564         return ret;
10565 }
10566
10567 /*
10568  * Handle operations for ethertype filter.
10569  */
10570 static int
10571 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10572                                 enum rte_filter_op filter_op,
10573                                 void *arg)
10574 {
10575         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10576         int ret = 0;
10577
10578         if (filter_op == RTE_ETH_FILTER_NOP)
10579                 return ret;
10580
10581         if (arg == NULL) {
10582                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10583                             filter_op);
10584                 return -EINVAL;
10585         }
10586
10587         switch (filter_op) {
10588         case RTE_ETH_FILTER_ADD:
10589                 ret = i40e_ethertype_filter_set(pf,
10590                         (struct rte_eth_ethertype_filter *)arg,
10591                         TRUE);
10592                 break;
10593         case RTE_ETH_FILTER_DELETE:
10594                 ret = i40e_ethertype_filter_set(pf,
10595                         (struct rte_eth_ethertype_filter *)arg,
10596                         FALSE);
10597                 break;
10598         default:
10599                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10600                 ret = -ENOSYS;
10601                 break;
10602         }
10603         return ret;
10604 }
10605
10606 static int
10607 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10608                      enum rte_filter_type filter_type,
10609                      enum rte_filter_op filter_op,
10610                      void *arg)
10611 {
10612         int ret = 0;
10613
10614         if (dev == NULL)
10615                 return -EINVAL;
10616
10617         switch (filter_type) {
10618         case RTE_ETH_FILTER_NONE:
10619                 /* For global configuration */
10620                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10621                 break;
10622         case RTE_ETH_FILTER_HASH:
10623                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10624                 break;
10625         case RTE_ETH_FILTER_MACVLAN:
10626                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10627                 break;
10628         case RTE_ETH_FILTER_ETHERTYPE:
10629                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10630                 break;
10631         case RTE_ETH_FILTER_TUNNEL:
10632                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10633                 break;
10634         case RTE_ETH_FILTER_FDIR:
10635                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10636                 break;
10637         case RTE_ETH_FILTER_GENERIC:
10638                 if (filter_op != RTE_ETH_FILTER_GET)
10639                         return -EINVAL;
10640                 *(const void **)arg = &i40e_flow_ops;
10641                 break;
10642         default:
10643                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10644                                                         filter_type);
10645                 ret = -EINVAL;
10646                 break;
10647         }
10648
10649         return ret;
10650 }
10651
10652 /*
10653  * Check and enable Extended Tag.
10654  * Enabling Extended Tag is important for 40G performance.
10655  */
10656 static void
10657 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10658 {
10659         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10660         uint32_t buf = 0;
10661         int ret;
10662
10663         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10664                                       PCI_DEV_CAP_REG);
10665         if (ret < 0) {
10666                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10667                             PCI_DEV_CAP_REG);
10668                 return;
10669         }
10670         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10671                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10672                 return;
10673         }
10674
10675         buf = 0;
10676         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10677                                       PCI_DEV_CTRL_REG);
10678         if (ret < 0) {
10679                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10680                             PCI_DEV_CTRL_REG);
10681                 return;
10682         }
10683         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10684                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10685                 return;
10686         }
10687         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10688         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10689                                        PCI_DEV_CTRL_REG);
10690         if (ret < 0) {
10691                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10692                             PCI_DEV_CTRL_REG);
10693                 return;
10694         }
10695 }
10696
10697 /*
10698  * As some registers wouldn't be reset unless a global hardware reset,
10699  * hardware initialization is needed to put those registers into an
10700  * expected initial state.
10701  */
10702 static void
10703 i40e_hw_init(struct rte_eth_dev *dev)
10704 {
10705         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10706
10707         i40e_enable_extended_tag(dev);
10708
10709         /* clear the PF Queue Filter control register */
10710         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10711
10712         /* Disable symmetric hash per port */
10713         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10714 }
10715
10716 /*
10717  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10718  * however this function will return only one highest pctype index,
10719  * which is not quite correct. This is known problem of i40e driver
10720  * and needs to be fixed later.
10721  */
10722 enum i40e_filter_pctype
10723 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10724 {
10725         int i;
10726         uint64_t pctype_mask;
10727
10728         if (flow_type < I40E_FLOW_TYPE_MAX) {
10729                 pctype_mask = adapter->pctypes_tbl[flow_type];
10730                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10731                         if (pctype_mask & (1ULL << i))
10732                                 return (enum i40e_filter_pctype)i;
10733                 }
10734         }
10735         return I40E_FILTER_PCTYPE_INVALID;
10736 }
10737
10738 uint16_t
10739 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10740                         enum i40e_filter_pctype pctype)
10741 {
10742         uint16_t flowtype;
10743         uint64_t pctype_mask = 1ULL << pctype;
10744
10745         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10746              flowtype++) {
10747                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10748                         return flowtype;
10749         }
10750
10751         return RTE_ETH_FLOW_UNKNOWN;
10752 }
10753
10754 /*
10755  * On X710, performance number is far from the expectation on recent firmware
10756  * versions; on XL710, performance number is also far from the expectation on
10757  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10758  * mode is enabled and port MAC address is equal to the packet destination MAC
10759  * address. The fix for this issue may not be integrated in the following
10760  * firmware version. So the workaround in software driver is needed. It needs
10761  * to modify the initial values of 3 internal only registers for both X710 and
10762  * XL710. Note that the values for X710 or XL710 could be different, and the
10763  * workaround can be removed when it is fixed in firmware in the future.
10764  */
10765
10766 /* For both X710 and XL710 */
10767 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10768 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10769 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10770
10771 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10772 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10773
10774 /* For X722 */
10775 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10776 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10777
10778 /* For X710 */
10779 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10780 /* For XL710 */
10781 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10782 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10783
10784 /*
10785  * GL_SWR_PM_UP_THR:
10786  * The value is not impacted from the link speed, its value is set according
10787  * to the total number of ports for a better pipe-monitor configuration.
10788  */
10789 static bool
10790 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10791 {
10792 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10793                 .device_id = (dev),   \
10794                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10795
10796 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10797                 .device_id = (dev),   \
10798                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10799
10800         static const struct {
10801                 uint16_t device_id;
10802                 uint32_t val;
10803         } swr_pm_table[] = {
10804                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10805                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10806                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10807                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10808                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10809
10810                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10811                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10812                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10813                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10814                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10815                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10816                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10817         };
10818         uint32_t i;
10819
10820         if (value == NULL) {
10821                 PMD_DRV_LOG(ERR, "value is NULL");
10822                 return false;
10823         }
10824
10825         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10826                 if (hw->device_id == swr_pm_table[i].device_id) {
10827                         *value = swr_pm_table[i].val;
10828
10829                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10830                                     "value - 0x%08x",
10831                                     hw->device_id, *value);
10832                         return true;
10833                 }
10834         }
10835
10836         return false;
10837 }
10838
10839 static int
10840 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10841 {
10842         enum i40e_status_code status;
10843         struct i40e_aq_get_phy_abilities_resp phy_ab;
10844         int ret = -ENOTSUP;
10845         int retries = 0;
10846
10847         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10848                                               NULL);
10849
10850         while (status) {
10851                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10852                         status);
10853                 retries++;
10854                 rte_delay_us(100000);
10855                 if  (retries < 5)
10856                         status = i40e_aq_get_phy_capabilities(hw, false,
10857                                         true, &phy_ab, NULL);
10858                 else
10859                         return ret;
10860         }
10861         return 0;
10862 }
10863
10864 static void
10865 i40e_configure_registers(struct i40e_hw *hw)
10866 {
10867         static struct {
10868                 uint32_t addr;
10869                 uint64_t val;
10870         } reg_table[] = {
10871                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10872                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10873                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10874         };
10875         uint64_t reg;
10876         uint32_t i;
10877         int ret;
10878
10879         for (i = 0; i < RTE_DIM(reg_table); i++) {
10880                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10881                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10882                                 reg_table[i].val =
10883                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10884                         else /* For X710/XL710/XXV710 */
10885                                 if (hw->aq.fw_maj_ver < 6)
10886                                         reg_table[i].val =
10887                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10888                                 else
10889                                         reg_table[i].val =
10890                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10891                 }
10892
10893                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10894                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10895                                 reg_table[i].val =
10896                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10897                         else /* For X710/XL710/XXV710 */
10898                                 reg_table[i].val =
10899                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10900                 }
10901
10902                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10903                         uint32_t cfg_val;
10904
10905                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10906                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10907                                             "GL_SWR_PM_UP_THR value fixup",
10908                                             hw->device_id);
10909                                 continue;
10910                         }
10911
10912                         reg_table[i].val = cfg_val;
10913                 }
10914
10915                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10916                                                         &reg, NULL);
10917                 if (ret < 0) {
10918                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10919                                                         reg_table[i].addr);
10920                         break;
10921                 }
10922                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10923                                                 reg_table[i].addr, reg);
10924                 if (reg == reg_table[i].val)
10925                         continue;
10926
10927                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10928                                                 reg_table[i].val, NULL);
10929                 if (ret < 0) {
10930                         PMD_DRV_LOG(ERR,
10931                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10932                                 reg_table[i].val, reg_table[i].addr);
10933                         break;
10934                 }
10935                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10936                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10937         }
10938 }
10939
10940 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10941 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10942 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10943 static int
10944 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10945 {
10946         uint32_t reg;
10947         int ret;
10948
10949         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10950                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10951                 return -EINVAL;
10952         }
10953
10954         /* Configure for double VLAN RX stripping */
10955         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10956         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10957                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10958                 ret = i40e_aq_debug_write_register(hw,
10959                                                    I40E_VSI_TSR(vsi->vsi_id),
10960                                                    reg, NULL);
10961                 if (ret < 0) {
10962                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10963                                     vsi->vsi_id);
10964                         return I40E_ERR_CONFIG;
10965                 }
10966         }
10967
10968         /* Configure for double VLAN TX insertion */
10969         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10970         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10971                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10972                 ret = i40e_aq_debug_write_register(hw,
10973                                                    I40E_VSI_L2TAGSTXVALID(
10974                                                    vsi->vsi_id), reg, NULL);
10975                 if (ret < 0) {
10976                         PMD_DRV_LOG(ERR,
10977                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10978                                 vsi->vsi_id);
10979                         return I40E_ERR_CONFIG;
10980                 }
10981         }
10982
10983         return 0;
10984 }
10985
10986 /**
10987  * i40e_aq_add_mirror_rule
10988  * @hw: pointer to the hardware structure
10989  * @seid: VEB seid to add mirror rule to
10990  * @dst_id: destination vsi seid
10991  * @entries: Buffer which contains the entities to be mirrored
10992  * @count: number of entities contained in the buffer
10993  * @rule_id:the rule_id of the rule to be added
10994  *
10995  * Add a mirror rule for a given veb.
10996  *
10997  **/
10998 static enum i40e_status_code
10999 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
11000                         uint16_t seid, uint16_t dst_id,
11001                         uint16_t rule_type, uint16_t *entries,
11002                         uint16_t count, uint16_t *rule_id)
11003 {
11004         struct i40e_aq_desc desc;
11005         struct i40e_aqc_add_delete_mirror_rule cmd;
11006         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
11007                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
11008                 &desc.params.raw;
11009         uint16_t buff_len;
11010         enum i40e_status_code status;
11011
11012         i40e_fill_default_direct_cmd_desc(&desc,
11013                                           i40e_aqc_opc_add_mirror_rule);
11014         memset(&cmd, 0, sizeof(cmd));
11015
11016         buff_len = sizeof(uint16_t) * count;
11017         desc.datalen = rte_cpu_to_le_16(buff_len);
11018         if (buff_len > 0)
11019                 desc.flags |= rte_cpu_to_le_16(
11020                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
11021         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11022                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11023         cmd.num_entries = rte_cpu_to_le_16(count);
11024         cmd.seid = rte_cpu_to_le_16(seid);
11025         cmd.destination = rte_cpu_to_le_16(dst_id);
11026
11027         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11028         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
11029         PMD_DRV_LOG(INFO,
11030                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
11031                 hw->aq.asq_last_status, resp->rule_id,
11032                 resp->mirror_rules_used, resp->mirror_rules_free);
11033         *rule_id = rte_le_to_cpu_16(resp->rule_id);
11034
11035         return status;
11036 }
11037
11038 /**
11039  * i40e_aq_del_mirror_rule
11040  * @hw: pointer to the hardware structure
11041  * @seid: VEB seid to add mirror rule to
11042  * @entries: Buffer which contains the entities to be mirrored
11043  * @count: number of entities contained in the buffer
11044  * @rule_id:the rule_id of the rule to be delete
11045  *
11046  * Delete a mirror rule for a given veb.
11047  *
11048  **/
11049 static enum i40e_status_code
11050 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
11051                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
11052                 uint16_t count, uint16_t rule_id)
11053 {
11054         struct i40e_aq_desc desc;
11055         struct i40e_aqc_add_delete_mirror_rule cmd;
11056         uint16_t buff_len = 0;
11057         enum i40e_status_code status;
11058         void *buff = NULL;
11059
11060         i40e_fill_default_direct_cmd_desc(&desc,
11061                                           i40e_aqc_opc_delete_mirror_rule);
11062         memset(&cmd, 0, sizeof(cmd));
11063         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
11064                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
11065                                                           I40E_AQ_FLAG_RD));
11066                 cmd.num_entries = count;
11067                 buff_len = sizeof(uint16_t) * count;
11068                 desc.datalen = rte_cpu_to_le_16(buff_len);
11069                 buff = (void *)entries;
11070         } else
11071                 /* rule id is filled in destination field for deleting mirror rule */
11072                 cmd.destination = rte_cpu_to_le_16(rule_id);
11073
11074         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11075                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11076         cmd.seid = rte_cpu_to_le_16(seid);
11077
11078         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11079         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
11080
11081         return status;
11082 }
11083
11084 /**
11085  * i40e_mirror_rule_set
11086  * @dev: pointer to the hardware structure
11087  * @mirror_conf: mirror rule info
11088  * @sw_id: mirror rule's sw_id
11089  * @on: enable/disable
11090  *
11091  * set a mirror rule.
11092  *
11093  **/
11094 static int
11095 i40e_mirror_rule_set(struct rte_eth_dev *dev,
11096                         struct rte_eth_mirror_conf *mirror_conf,
11097                         uint8_t sw_id, uint8_t on)
11098 {
11099         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11101         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11102         struct i40e_mirror_rule *parent = NULL;
11103         uint16_t seid, dst_seid, rule_id;
11104         uint16_t i, j = 0;
11105         int ret;
11106
11107         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
11108
11109         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
11110                 PMD_DRV_LOG(ERR,
11111                         "mirror rule can not be configured without veb or vfs.");
11112                 return -ENOSYS;
11113         }
11114         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
11115                 PMD_DRV_LOG(ERR, "mirror table is full.");
11116                 return -ENOSPC;
11117         }
11118         if (mirror_conf->dst_pool > pf->vf_num) {
11119                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11120                                  mirror_conf->dst_pool);
11121                 return -EINVAL;
11122         }
11123
11124         seid = pf->main_vsi->veb->seid;
11125
11126         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11127                 if (sw_id <= it->index) {
11128                         mirr_rule = it;
11129                         break;
11130                 }
11131                 parent = it;
11132         }
11133         if (mirr_rule && sw_id == mirr_rule->index) {
11134                 if (on) {
11135                         PMD_DRV_LOG(ERR, "mirror rule exists.");
11136                         return -EEXIST;
11137                 } else {
11138                         ret = i40e_aq_del_mirror_rule(hw, seid,
11139                                         mirr_rule->rule_type,
11140                                         mirr_rule->entries,
11141                                         mirr_rule->num_entries, mirr_rule->id);
11142                         if (ret < 0) {
11143                                 PMD_DRV_LOG(ERR,
11144                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
11145                                         ret, hw->aq.asq_last_status);
11146                                 return -ENOSYS;
11147                         }
11148                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11149                         rte_free(mirr_rule);
11150                         pf->nb_mirror_rule--;
11151                         return 0;
11152                 }
11153         } else if (!on) {
11154                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11155                 return -ENOENT;
11156         }
11157
11158         mirr_rule = rte_zmalloc("i40e_mirror_rule",
11159                                 sizeof(struct i40e_mirror_rule) , 0);
11160         if (!mirr_rule) {
11161                 PMD_DRV_LOG(ERR, "failed to allocate memory");
11162                 return I40E_ERR_NO_MEMORY;
11163         }
11164         switch (mirror_conf->rule_type) {
11165         case ETH_MIRROR_VLAN:
11166                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11167                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11168                                 mirr_rule->entries[j] =
11169                                         mirror_conf->vlan.vlan_id[i];
11170                                 j++;
11171                         }
11172                 }
11173                 if (j == 0) {
11174                         PMD_DRV_LOG(ERR, "vlan is not specified.");
11175                         rte_free(mirr_rule);
11176                         return -EINVAL;
11177                 }
11178                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11179                 break;
11180         case ETH_MIRROR_VIRTUAL_POOL_UP:
11181         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11182                 /* check if the specified pool bit is out of range */
11183                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11184                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
11185                         rte_free(mirr_rule);
11186                         return -EINVAL;
11187                 }
11188                 for (i = 0, j = 0; i < pf->vf_num; i++) {
11189                         if (mirror_conf->pool_mask & (1ULL << i)) {
11190                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11191                                 j++;
11192                         }
11193                 }
11194                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11195                         /* add pf vsi to entries */
11196                         mirr_rule->entries[j] = pf->main_vsi_seid;
11197                         j++;
11198                 }
11199                 if (j == 0) {
11200                         PMD_DRV_LOG(ERR, "pool is not specified.");
11201                         rte_free(mirr_rule);
11202                         return -EINVAL;
11203                 }
11204                 /* egress and ingress in aq commands means from switch but not port */
11205                 mirr_rule->rule_type =
11206                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11207                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11208                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11209                 break;
11210         case ETH_MIRROR_UPLINK_PORT:
11211                 /* egress and ingress in aq commands means from switch but not port*/
11212                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11213                 break;
11214         case ETH_MIRROR_DOWNLINK_PORT:
11215                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11216                 break;
11217         default:
11218                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11219                         mirror_conf->rule_type);
11220                 rte_free(mirr_rule);
11221                 return -EINVAL;
11222         }
11223
11224         /* If the dst_pool is equal to vf_num, consider it as PF */
11225         if (mirror_conf->dst_pool == pf->vf_num)
11226                 dst_seid = pf->main_vsi_seid;
11227         else
11228                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11229
11230         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11231                                       mirr_rule->rule_type, mirr_rule->entries,
11232                                       j, &rule_id);
11233         if (ret < 0) {
11234                 PMD_DRV_LOG(ERR,
11235                         "failed to add mirror rule: ret = %d, aq_err = %d.",
11236                         ret, hw->aq.asq_last_status);
11237                 rte_free(mirr_rule);
11238                 return -ENOSYS;
11239         }
11240
11241         mirr_rule->index = sw_id;
11242         mirr_rule->num_entries = j;
11243         mirr_rule->id = rule_id;
11244         mirr_rule->dst_vsi_seid = dst_seid;
11245
11246         if (parent)
11247                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11248         else
11249                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11250
11251         pf->nb_mirror_rule++;
11252         return 0;
11253 }
11254
11255 /**
11256  * i40e_mirror_rule_reset
11257  * @dev: pointer to the device
11258  * @sw_id: mirror rule's sw_id
11259  *
11260  * reset a mirror rule.
11261  *
11262  **/
11263 static int
11264 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11265 {
11266         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11268         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11269         uint16_t seid;
11270         int ret;
11271
11272         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11273
11274         seid = pf->main_vsi->veb->seid;
11275
11276         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11277                 if (sw_id == it->index) {
11278                         mirr_rule = it;
11279                         break;
11280                 }
11281         }
11282         if (mirr_rule) {
11283                 ret = i40e_aq_del_mirror_rule(hw, seid,
11284                                 mirr_rule->rule_type,
11285                                 mirr_rule->entries,
11286                                 mirr_rule->num_entries, mirr_rule->id);
11287                 if (ret < 0) {
11288                         PMD_DRV_LOG(ERR,
11289                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
11290                                 ret, hw->aq.asq_last_status);
11291                         return -ENOSYS;
11292                 }
11293                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11294                 rte_free(mirr_rule);
11295                 pf->nb_mirror_rule--;
11296         } else {
11297                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11298                 return -ENOENT;
11299         }
11300         return 0;
11301 }
11302
11303 static uint64_t
11304 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11305 {
11306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11307         uint64_t systim_cycles;
11308
11309         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11310         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11311                         << 32;
11312
11313         return systim_cycles;
11314 }
11315
11316 static uint64_t
11317 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11318 {
11319         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11320         uint64_t rx_tstamp;
11321
11322         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11323         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11324                         << 32;
11325
11326         return rx_tstamp;
11327 }
11328
11329 static uint64_t
11330 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11331 {
11332         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11333         uint64_t tx_tstamp;
11334
11335         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11336         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11337                         << 32;
11338
11339         return tx_tstamp;
11340 }
11341
11342 static void
11343 i40e_start_timecounters(struct rte_eth_dev *dev)
11344 {
11345         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11346         struct i40e_adapter *adapter = dev->data->dev_private;
11347         struct rte_eth_link link;
11348         uint32_t tsync_inc_l;
11349         uint32_t tsync_inc_h;
11350
11351         /* Get current link speed. */
11352         i40e_dev_link_update(dev, 1);
11353         rte_eth_linkstatus_get(dev, &link);
11354
11355         switch (link.link_speed) {
11356         case ETH_SPEED_NUM_40G:
11357         case ETH_SPEED_NUM_25G:
11358                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11359                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11360                 break;
11361         case ETH_SPEED_NUM_10G:
11362                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11363                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11364                 break;
11365         case ETH_SPEED_NUM_1G:
11366                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11367                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11368                 break;
11369         default:
11370                 tsync_inc_l = 0x0;
11371                 tsync_inc_h = 0x0;
11372         }
11373
11374         /* Set the timesync increment value. */
11375         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11376         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11377
11378         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11379         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11380         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11381
11382         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11383         adapter->systime_tc.cc_shift = 0;
11384         adapter->systime_tc.nsec_mask = 0;
11385
11386         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11387         adapter->rx_tstamp_tc.cc_shift = 0;
11388         adapter->rx_tstamp_tc.nsec_mask = 0;
11389
11390         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11391         adapter->tx_tstamp_tc.cc_shift = 0;
11392         adapter->tx_tstamp_tc.nsec_mask = 0;
11393 }
11394
11395 static int
11396 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11397 {
11398         struct i40e_adapter *adapter = dev->data->dev_private;
11399
11400         adapter->systime_tc.nsec += delta;
11401         adapter->rx_tstamp_tc.nsec += delta;
11402         adapter->tx_tstamp_tc.nsec += delta;
11403
11404         return 0;
11405 }
11406
11407 static int
11408 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11409 {
11410         uint64_t ns;
11411         struct i40e_adapter *adapter = dev->data->dev_private;
11412
11413         ns = rte_timespec_to_ns(ts);
11414
11415         /* Set the timecounters to a new value. */
11416         adapter->systime_tc.nsec = ns;
11417         adapter->rx_tstamp_tc.nsec = ns;
11418         adapter->tx_tstamp_tc.nsec = ns;
11419
11420         return 0;
11421 }
11422
11423 static int
11424 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11425 {
11426         uint64_t ns, systime_cycles;
11427         struct i40e_adapter *adapter = dev->data->dev_private;
11428
11429         systime_cycles = i40e_read_systime_cyclecounter(dev);
11430         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11431         *ts = rte_ns_to_timespec(ns);
11432
11433         return 0;
11434 }
11435
11436 static int
11437 i40e_timesync_enable(struct rte_eth_dev *dev)
11438 {
11439         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11440         uint32_t tsync_ctl_l;
11441         uint32_t tsync_ctl_h;
11442
11443         /* Stop the timesync system time. */
11444         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11445         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11446         /* Reset the timesync system time value. */
11447         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11448         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11449
11450         i40e_start_timecounters(dev);
11451
11452         /* Clear timesync registers. */
11453         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11454         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11455         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11456         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11457         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11458         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11459
11460         /* Enable timestamping of PTP packets. */
11461         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11462         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11463
11464         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11465         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11466         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11467
11468         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11469         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11470
11471         return 0;
11472 }
11473
11474 static int
11475 i40e_timesync_disable(struct rte_eth_dev *dev)
11476 {
11477         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11478         uint32_t tsync_ctl_l;
11479         uint32_t tsync_ctl_h;
11480
11481         /* Disable timestamping of transmitted PTP packets. */
11482         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11483         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11484
11485         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11486         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11487
11488         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11489         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11490
11491         /* Reset the timesync increment value. */
11492         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11493         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11494
11495         return 0;
11496 }
11497
11498 static int
11499 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11500                                 struct timespec *timestamp, uint32_t flags)
11501 {
11502         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11503         struct i40e_adapter *adapter = dev->data->dev_private;
11504         uint32_t sync_status;
11505         uint32_t index = flags & 0x03;
11506         uint64_t rx_tstamp_cycles;
11507         uint64_t ns;
11508
11509         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11510         if ((sync_status & (1 << index)) == 0)
11511                 return -EINVAL;
11512
11513         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11514         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11515         *timestamp = rte_ns_to_timespec(ns);
11516
11517         return 0;
11518 }
11519
11520 static int
11521 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11522                                 struct timespec *timestamp)
11523 {
11524         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11525         struct i40e_adapter *adapter = dev->data->dev_private;
11526         uint32_t sync_status;
11527         uint64_t tx_tstamp_cycles;
11528         uint64_t ns;
11529
11530         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11531         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11532                 return -EINVAL;
11533
11534         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11535         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11536         *timestamp = rte_ns_to_timespec(ns);
11537
11538         return 0;
11539 }
11540
11541 /*
11542  * i40e_parse_dcb_configure - parse dcb configure from user
11543  * @dev: the device being configured
11544  * @dcb_cfg: pointer of the result of parse
11545  * @*tc_map: bit map of enabled traffic classes
11546  *
11547  * Returns 0 on success, negative value on failure
11548  */
11549 static int
11550 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11551                          struct i40e_dcbx_config *dcb_cfg,
11552                          uint8_t *tc_map)
11553 {
11554         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11555         uint8_t i, tc_bw, bw_lf;
11556
11557         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11558
11559         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11560         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11561                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11562                 return -EINVAL;
11563         }
11564
11565         /* assume each tc has the same bw */
11566         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11567         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11568                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11569         /* to ensure the sum of tcbw is equal to 100 */
11570         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11571         for (i = 0; i < bw_lf; i++)
11572                 dcb_cfg->etscfg.tcbwtable[i]++;
11573
11574         /* assume each tc has the same Transmission Selection Algorithm */
11575         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11576                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11577
11578         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11579                 dcb_cfg->etscfg.prioritytable[i] =
11580                                 dcb_rx_conf->dcb_tc[i];
11581
11582         /* FW needs one App to configure HW */
11583         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11584         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11585         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11586         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11587
11588         if (dcb_rx_conf->nb_tcs == 0)
11589                 *tc_map = 1; /* tc0 only */
11590         else
11591                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11592
11593         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11594                 dcb_cfg->pfc.willing = 0;
11595                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11596                 dcb_cfg->pfc.pfcenable = *tc_map;
11597         }
11598         return 0;
11599 }
11600
11601
11602 static enum i40e_status_code
11603 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11604                               struct i40e_aqc_vsi_properties_data *info,
11605                               uint8_t enabled_tcmap)
11606 {
11607         enum i40e_status_code ret;
11608         int i, total_tc = 0;
11609         uint16_t qpnum_per_tc, bsf, qp_idx;
11610         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11611         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11612         uint16_t used_queues;
11613
11614         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11615         if (ret != I40E_SUCCESS)
11616                 return ret;
11617
11618         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11619                 if (enabled_tcmap & (1 << i))
11620                         total_tc++;
11621         }
11622         if (total_tc == 0)
11623                 total_tc = 1;
11624         vsi->enabled_tc = enabled_tcmap;
11625
11626         /* different VSI has different queues assigned */
11627         if (vsi->type == I40E_VSI_MAIN)
11628                 used_queues = dev_data->nb_rx_queues -
11629                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11630         else if (vsi->type == I40E_VSI_VMDQ2)
11631                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11632         else {
11633                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11634                 return I40E_ERR_NO_AVAILABLE_VSI;
11635         }
11636
11637         qpnum_per_tc = used_queues / total_tc;
11638         /* Number of queues per enabled TC */
11639         if (qpnum_per_tc == 0) {
11640                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11641                 return I40E_ERR_INVALID_QP_ID;
11642         }
11643         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11644                                 I40E_MAX_Q_PER_TC);
11645         bsf = rte_bsf32(qpnum_per_tc);
11646
11647         /**
11648          * Configure TC and queue mapping parameters, for enabled TC,
11649          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11650          * default queue will serve it.
11651          */
11652         qp_idx = 0;
11653         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11654                 if (vsi->enabled_tc & (1 << i)) {
11655                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11656                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11657                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11658                         qp_idx += qpnum_per_tc;
11659                 } else
11660                         info->tc_mapping[i] = 0;
11661         }
11662
11663         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11664         if (vsi->type == I40E_VSI_SRIOV) {
11665                 info->mapping_flags |=
11666                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11667                 for (i = 0; i < vsi->nb_qps; i++)
11668                         info->queue_mapping[i] =
11669                                 rte_cpu_to_le_16(vsi->base_queue + i);
11670         } else {
11671                 info->mapping_flags |=
11672                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11673                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11674         }
11675         info->valid_sections |=
11676                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11677
11678         return I40E_SUCCESS;
11679 }
11680
11681 /*
11682  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11683  * @veb: VEB to be configured
11684  * @tc_map: enabled TC bitmap
11685  *
11686  * Returns 0 on success, negative value on failure
11687  */
11688 static enum i40e_status_code
11689 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11690 {
11691         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11692         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11693         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11694         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11695         enum i40e_status_code ret = I40E_SUCCESS;
11696         int i;
11697         uint32_t bw_max;
11698
11699         /* Check if enabled_tc is same as existing or new TCs */
11700         if (veb->enabled_tc == tc_map)
11701                 return ret;
11702
11703         /* configure tc bandwidth */
11704         memset(&veb_bw, 0, sizeof(veb_bw));
11705         veb_bw.tc_valid_bits = tc_map;
11706         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11707         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11708                 if (tc_map & BIT_ULL(i))
11709                         veb_bw.tc_bw_share_credits[i] = 1;
11710         }
11711         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11712                                                    &veb_bw, NULL);
11713         if (ret) {
11714                 PMD_INIT_LOG(ERR,
11715                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11716                         hw->aq.asq_last_status);
11717                 return ret;
11718         }
11719
11720         memset(&ets_query, 0, sizeof(ets_query));
11721         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11722                                                    &ets_query, NULL);
11723         if (ret != I40E_SUCCESS) {
11724                 PMD_DRV_LOG(ERR,
11725                         "Failed to get switch_comp ETS configuration %u",
11726                         hw->aq.asq_last_status);
11727                 return ret;
11728         }
11729         memset(&bw_query, 0, sizeof(bw_query));
11730         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11731                                                   &bw_query, NULL);
11732         if (ret != I40E_SUCCESS) {
11733                 PMD_DRV_LOG(ERR,
11734                         "Failed to get switch_comp bandwidth configuration %u",
11735                         hw->aq.asq_last_status);
11736                 return ret;
11737         }
11738
11739         /* store and print out BW info */
11740         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11741         veb->bw_info.bw_max = ets_query.tc_bw_max;
11742         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11743         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11744         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11745                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11746                      I40E_16_BIT_WIDTH);
11747         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11748                 veb->bw_info.bw_ets_share_credits[i] =
11749                                 bw_query.tc_bw_share_credits[i];
11750                 veb->bw_info.bw_ets_credits[i] =
11751                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11752                 /* 4 bits per TC, 4th bit is reserved */
11753                 veb->bw_info.bw_ets_max[i] =
11754                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11755                                   RTE_LEN2MASK(3, uint8_t));
11756                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11757                             veb->bw_info.bw_ets_share_credits[i]);
11758                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11759                             veb->bw_info.bw_ets_credits[i]);
11760                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11761                             veb->bw_info.bw_ets_max[i]);
11762         }
11763
11764         veb->enabled_tc = tc_map;
11765
11766         return ret;
11767 }
11768
11769
11770 /*
11771  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11772  * @vsi: VSI to be configured
11773  * @tc_map: enabled TC bitmap
11774  *
11775  * Returns 0 on success, negative value on failure
11776  */
11777 static enum i40e_status_code
11778 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11779 {
11780         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11781         struct i40e_vsi_context ctxt;
11782         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11783         enum i40e_status_code ret = I40E_SUCCESS;
11784         int i;
11785
11786         /* Check if enabled_tc is same as existing or new TCs */
11787         if (vsi->enabled_tc == tc_map)
11788                 return ret;
11789
11790         /* configure tc bandwidth */
11791         memset(&bw_data, 0, sizeof(bw_data));
11792         bw_data.tc_valid_bits = tc_map;
11793         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11794         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11795                 if (tc_map & BIT_ULL(i))
11796                         bw_data.tc_bw_credits[i] = 1;
11797         }
11798         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11799         if (ret) {
11800                 PMD_INIT_LOG(ERR,
11801                         "AQ command Config VSI BW allocation per TC failed = %d",
11802                         hw->aq.asq_last_status);
11803                 goto out;
11804         }
11805         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11806                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11807
11808         /* Update Queue Pairs Mapping for currently enabled UPs */
11809         ctxt.seid = vsi->seid;
11810         ctxt.pf_num = hw->pf_id;
11811         ctxt.vf_num = 0;
11812         ctxt.uplink_seid = vsi->uplink_seid;
11813         ctxt.info = vsi->info;
11814         i40e_get_cap(hw);
11815         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11816         if (ret)
11817                 goto out;
11818
11819         /* Update the VSI after updating the VSI queue-mapping information */
11820         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11821         if (ret) {
11822                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11823                         hw->aq.asq_last_status);
11824                 goto out;
11825         }
11826         /* update the local VSI info with updated queue map */
11827         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11828                                         sizeof(vsi->info.tc_mapping));
11829         rte_memcpy(&vsi->info.queue_mapping,
11830                         &ctxt.info.queue_mapping,
11831                 sizeof(vsi->info.queue_mapping));
11832         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11833         vsi->info.valid_sections = 0;
11834
11835         /* query and update current VSI BW information */
11836         ret = i40e_vsi_get_bw_config(vsi);
11837         if (ret) {
11838                 PMD_INIT_LOG(ERR,
11839                          "Failed updating vsi bw info, err %s aq_err %s",
11840                          i40e_stat_str(hw, ret),
11841                          i40e_aq_str(hw, hw->aq.asq_last_status));
11842                 goto out;
11843         }
11844
11845         vsi->enabled_tc = tc_map;
11846
11847 out:
11848         return ret;
11849 }
11850
11851 /*
11852  * i40e_dcb_hw_configure - program the dcb setting to hw
11853  * @pf: pf the configuration is taken on
11854  * @new_cfg: new configuration
11855  * @tc_map: enabled TC bitmap
11856  *
11857  * Returns 0 on success, negative value on failure
11858  */
11859 static enum i40e_status_code
11860 i40e_dcb_hw_configure(struct i40e_pf *pf,
11861                       struct i40e_dcbx_config *new_cfg,
11862                       uint8_t tc_map)
11863 {
11864         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11865         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11866         struct i40e_vsi *main_vsi = pf->main_vsi;
11867         struct i40e_vsi_list *vsi_list;
11868         enum i40e_status_code ret;
11869         int i;
11870         uint32_t val;
11871
11872         /* Use the FW API if FW > v4.4*/
11873         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11874               (hw->aq.fw_maj_ver >= 5))) {
11875                 PMD_INIT_LOG(ERR,
11876                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11877                 return I40E_ERR_FIRMWARE_API_VERSION;
11878         }
11879
11880         /* Check if need reconfiguration */
11881         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11882                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11883                 return I40E_SUCCESS;
11884         }
11885
11886         /* Copy the new config to the current config */
11887         *old_cfg = *new_cfg;
11888         old_cfg->etsrec = old_cfg->etscfg;
11889         ret = i40e_set_dcb_config(hw);
11890         if (ret) {
11891                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11892                          i40e_stat_str(hw, ret),
11893                          i40e_aq_str(hw, hw->aq.asq_last_status));
11894                 return ret;
11895         }
11896         /* set receive Arbiter to RR mode and ETS scheme by default */
11897         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11898                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11899                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11900                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11901                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11902                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11903                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11904                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11905                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11906                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11907                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11908                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11909                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11910         }
11911         /* get local mib to check whether it is configured correctly */
11912         /* IEEE mode */
11913         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11914         /* Get Local DCB Config */
11915         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11916                                      &hw->local_dcbx_config);
11917
11918         /* if Veb is created, need to update TC of it at first */
11919         if (main_vsi->veb) {
11920                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11921                 if (ret)
11922                         PMD_INIT_LOG(WARNING,
11923                                  "Failed configuring TC for VEB seid=%d",
11924                                  main_vsi->veb->seid);
11925         }
11926         /* Update each VSI */
11927         i40e_vsi_config_tc(main_vsi, tc_map);
11928         if (main_vsi->veb) {
11929                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11930                         /* Beside main VSI and VMDQ VSIs, only enable default
11931                          * TC for other VSIs
11932                          */
11933                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11934                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11935                                                          tc_map);
11936                         else
11937                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11938                                                          I40E_DEFAULT_TCMAP);
11939                         if (ret)
11940                                 PMD_INIT_LOG(WARNING,
11941                                         "Failed configuring TC for VSI seid=%d",
11942                                         vsi_list->vsi->seid);
11943                         /* continue */
11944                 }
11945         }
11946         return I40E_SUCCESS;
11947 }
11948
11949 /*
11950  * i40e_dcb_init_configure - initial dcb config
11951  * @dev: device being configured
11952  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11953  *
11954  * Returns 0 on success, negative value on failure
11955  */
11956 int
11957 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11958 {
11959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11961         int i, ret = 0;
11962
11963         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11964                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11965                 return -ENOTSUP;
11966         }
11967
11968         /* DCB initialization:
11969          * Update DCB configuration from the Firmware and configure
11970          * LLDP MIB change event.
11971          */
11972         if (sw_dcb == TRUE) {
11973                 /* Stopping lldp is necessary for DPDK, but it will cause
11974                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11975                  * for successful initialization of DCB is that LLDP is
11976                  * enabled. So it is needed to start lldp before DCB init
11977                  * and stop it after initialization.
11978                  */
11979                 ret = i40e_aq_start_lldp(hw, true, NULL);
11980                 if (ret != I40E_SUCCESS)
11981                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11982
11983                 ret = i40e_init_dcb(hw, true);
11984                 /* If lldp agent is stopped, the return value from
11985                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11986                  * adminq status. Otherwise, it should return success.
11987                  */
11988                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11989                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11990                         memset(&hw->local_dcbx_config, 0,
11991                                 sizeof(struct i40e_dcbx_config));
11992                         /* set dcb default configuration */
11993                         hw->local_dcbx_config.etscfg.willing = 0;
11994                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11995                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11996                         hw->local_dcbx_config.etscfg.tsatable[0] =
11997                                                 I40E_IEEE_TSA_ETS;
11998                         /* all UPs mapping to TC0 */
11999                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12000                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
12001                         hw->local_dcbx_config.etsrec =
12002                                 hw->local_dcbx_config.etscfg;
12003                         hw->local_dcbx_config.pfc.willing = 0;
12004                         hw->local_dcbx_config.pfc.pfccap =
12005                                                 I40E_MAX_TRAFFIC_CLASS;
12006                         /* FW needs one App to configure HW */
12007                         hw->local_dcbx_config.numapps = 1;
12008                         hw->local_dcbx_config.app[0].selector =
12009                                                 I40E_APP_SEL_ETHTYPE;
12010                         hw->local_dcbx_config.app[0].priority = 3;
12011                         hw->local_dcbx_config.app[0].protocolid =
12012                                                 I40E_APP_PROTOID_FCOE;
12013                         ret = i40e_set_dcb_config(hw);
12014                         if (ret) {
12015                                 PMD_INIT_LOG(ERR,
12016                                         "default dcb config fails. err = %d, aq_err = %d.",
12017                                         ret, hw->aq.asq_last_status);
12018                                 return -ENOSYS;
12019                         }
12020                 } else {
12021                         PMD_INIT_LOG(ERR,
12022                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
12023                                 ret, hw->aq.asq_last_status);
12024                         return -ENOTSUP;
12025                 }
12026
12027                 if (i40e_need_stop_lldp(dev)) {
12028                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
12029                         if (ret != I40E_SUCCESS)
12030                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
12031                 }
12032         } else {
12033                 ret = i40e_aq_start_lldp(hw, true, NULL);
12034                 if (ret != I40E_SUCCESS)
12035                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
12036
12037                 ret = i40e_init_dcb(hw, true);
12038                 if (!ret) {
12039                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
12040                                 PMD_INIT_LOG(ERR,
12041                                         "HW doesn't support DCBX offload.");
12042                                 return -ENOTSUP;
12043                         }
12044                 } else {
12045                         PMD_INIT_LOG(ERR,
12046                                 "DCBX configuration failed, err = %d, aq_err = %d.",
12047                                 ret, hw->aq.asq_last_status);
12048                         return -ENOTSUP;
12049                 }
12050         }
12051         return 0;
12052 }
12053
12054 /*
12055  * i40e_dcb_setup - setup dcb related config
12056  * @dev: device being configured
12057  *
12058  * Returns 0 on success, negative value on failure
12059  */
12060 static int
12061 i40e_dcb_setup(struct rte_eth_dev *dev)
12062 {
12063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12064         struct i40e_dcbx_config dcb_cfg;
12065         uint8_t tc_map = 0;
12066         int ret = 0;
12067
12068         if ((pf->flags & I40E_FLAG_DCB) == 0) {
12069                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
12070                 return -ENOTSUP;
12071         }
12072
12073         if (pf->vf_num != 0)
12074                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
12075
12076         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
12077         if (ret) {
12078                 PMD_INIT_LOG(ERR, "invalid dcb config");
12079                 return -EINVAL;
12080         }
12081         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
12082         if (ret) {
12083                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
12084                 return -ENOSYS;
12085         }
12086
12087         return 0;
12088 }
12089
12090 static int
12091 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
12092                       struct rte_eth_dcb_info *dcb_info)
12093 {
12094         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12095         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12096         struct i40e_vsi *vsi = pf->main_vsi;
12097         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
12098         uint16_t bsf, tc_mapping;
12099         int i, j = 0;
12100
12101         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
12102                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
12103         else
12104                 dcb_info->nb_tcs = 1;
12105         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12106                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
12107         for (i = 0; i < dcb_info->nb_tcs; i++)
12108                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
12109
12110         /* get queue mapping if vmdq is disabled */
12111         if (!pf->nb_cfg_vmdq_vsi) {
12112                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12113                         if (!(vsi->enabled_tc & (1 << i)))
12114                                 continue;
12115                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12116                         dcb_info->tc_queue.tc_rxq[j][i].base =
12117                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12118                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12119                         dcb_info->tc_queue.tc_txq[j][i].base =
12120                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12121                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12122                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12123                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12124                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12125                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12126                 }
12127                 return 0;
12128         }
12129
12130         /* get queue mapping if vmdq is enabled */
12131         do {
12132                 vsi = pf->vmdq[j].vsi;
12133                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12134                         if (!(vsi->enabled_tc & (1 << i)))
12135                                 continue;
12136                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12137                         dcb_info->tc_queue.tc_rxq[j][i].base =
12138                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12139                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12140                         dcb_info->tc_queue.tc_txq[j][i].base =
12141                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12142                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12143                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12144                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12145                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12146                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12147                 }
12148                 j++;
12149         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12150         return 0;
12151 }
12152
12153 static int
12154 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12155 {
12156         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12157         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12159         uint16_t msix_intr;
12160
12161         msix_intr = intr_handle->intr_vec[queue_id];
12162         if (msix_intr == I40E_MISC_VEC_ID)
12163                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12164                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
12165                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12166                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12167         else
12168                 I40E_WRITE_REG(hw,
12169                                I40E_PFINT_DYN_CTLN(msix_intr -
12170                                                    I40E_RX_VEC_START),
12171                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
12172                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12173                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12174
12175         I40E_WRITE_FLUSH(hw);
12176         rte_intr_ack(&pci_dev->intr_handle);
12177
12178         return 0;
12179 }
12180
12181 static int
12182 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12183 {
12184         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12185         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12186         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12187         uint16_t msix_intr;
12188
12189         msix_intr = intr_handle->intr_vec[queue_id];
12190         if (msix_intr == I40E_MISC_VEC_ID)
12191                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12192                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12193         else
12194                 I40E_WRITE_REG(hw,
12195                                I40E_PFINT_DYN_CTLN(msix_intr -
12196                                                    I40E_RX_VEC_START),
12197                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12198         I40E_WRITE_FLUSH(hw);
12199
12200         return 0;
12201 }
12202
12203 /**
12204  * This function is used to check if the register is valid.
12205  * Below is the valid registers list for X722 only:
12206  * 0x2b800--0x2bb00
12207  * 0x38700--0x38a00
12208  * 0x3d800--0x3db00
12209  * 0x208e00--0x209000
12210  * 0x20be00--0x20c000
12211  * 0x263c00--0x264000
12212  * 0x265c00--0x266000
12213  */
12214 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12215 {
12216         if ((type != I40E_MAC_X722) &&
12217             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12218              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12219              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12220              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12221              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12222              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12223              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12224                 return 0;
12225         else
12226                 return 1;
12227 }
12228
12229 static int i40e_get_regs(struct rte_eth_dev *dev,
12230                          struct rte_dev_reg_info *regs)
12231 {
12232         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12233         uint32_t *ptr_data = regs->data;
12234         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12235         const struct i40e_reg_info *reg_info;
12236
12237         if (ptr_data == NULL) {
12238                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12239                 regs->width = sizeof(uint32_t);
12240                 return 0;
12241         }
12242
12243         /* The first few registers have to be read using AQ operations */
12244         reg_idx = 0;
12245         while (i40e_regs_adminq[reg_idx].name) {
12246                 reg_info = &i40e_regs_adminq[reg_idx++];
12247                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12248                         for (arr_idx2 = 0;
12249                                         arr_idx2 <= reg_info->count2;
12250                                         arr_idx2++) {
12251                                 reg_offset = arr_idx * reg_info->stride1 +
12252                                         arr_idx2 * reg_info->stride2;
12253                                 reg_offset += reg_info->base_addr;
12254                                 ptr_data[reg_offset >> 2] =
12255                                         i40e_read_rx_ctl(hw, reg_offset);
12256                         }
12257         }
12258
12259         /* The remaining registers can be read using primitives */
12260         reg_idx = 0;
12261         while (i40e_regs_others[reg_idx].name) {
12262                 reg_info = &i40e_regs_others[reg_idx++];
12263                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12264                         for (arr_idx2 = 0;
12265                                         arr_idx2 <= reg_info->count2;
12266                                         arr_idx2++) {
12267                                 reg_offset = arr_idx * reg_info->stride1 +
12268                                         arr_idx2 * reg_info->stride2;
12269                                 reg_offset += reg_info->base_addr;
12270                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12271                                         ptr_data[reg_offset >> 2] = 0;
12272                                 else
12273                                         ptr_data[reg_offset >> 2] =
12274                                                 I40E_READ_REG(hw, reg_offset);
12275                         }
12276         }
12277
12278         return 0;
12279 }
12280
12281 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12282 {
12283         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12284
12285         /* Convert word count to byte count */
12286         return hw->nvm.sr_size << 1;
12287 }
12288
12289 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12290                            struct rte_dev_eeprom_info *eeprom)
12291 {
12292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12293         uint16_t *data = eeprom->data;
12294         uint16_t offset, length, cnt_words;
12295         int ret_code;
12296
12297         offset = eeprom->offset >> 1;
12298         length = eeprom->length >> 1;
12299         cnt_words = length;
12300
12301         if (offset > hw->nvm.sr_size ||
12302                 offset + length > hw->nvm.sr_size) {
12303                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12304                 return -EINVAL;
12305         }
12306
12307         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12308
12309         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12310         if (ret_code != I40E_SUCCESS || cnt_words != length) {
12311                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12312                 return -EIO;
12313         }
12314
12315         return 0;
12316 }
12317
12318 static int i40e_get_module_info(struct rte_eth_dev *dev,
12319                                 struct rte_eth_dev_module_info *modinfo)
12320 {
12321         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12322         uint32_t sff8472_comp = 0;
12323         uint32_t sff8472_swap = 0;
12324         uint32_t sff8636_rev = 0;
12325         i40e_status status;
12326         uint32_t type = 0;
12327
12328         /* Check if firmware supports reading module EEPROM. */
12329         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12330                 PMD_DRV_LOG(ERR,
12331                             "Module EEPROM memory read not supported. "
12332                             "Please update the NVM image.\n");
12333                 return -EINVAL;
12334         }
12335
12336         status = i40e_update_link_info(hw);
12337         if (status)
12338                 return -EIO;
12339
12340         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12341                 PMD_DRV_LOG(ERR,
12342                             "Cannot read module EEPROM memory. "
12343                             "No module connected.\n");
12344                 return -EINVAL;
12345         }
12346
12347         type = hw->phy.link_info.module_type[0];
12348
12349         switch (type) {
12350         case I40E_MODULE_TYPE_SFP:
12351                 status = i40e_aq_get_phy_register(hw,
12352                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12353                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12354                                 I40E_MODULE_SFF_8472_COMP,
12355                                 &sff8472_comp, NULL);
12356                 if (status)
12357                         return -EIO;
12358
12359                 status = i40e_aq_get_phy_register(hw,
12360                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12361                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12362                                 I40E_MODULE_SFF_8472_SWAP,
12363                                 &sff8472_swap, NULL);
12364                 if (status)
12365                         return -EIO;
12366
12367                 /* Check if the module requires address swap to access
12368                  * the other EEPROM memory page.
12369                  */
12370                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12371                         PMD_DRV_LOG(WARNING,
12372                                     "Module address swap to access "
12373                                     "page 0xA2 is not supported.\n");
12374                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12375                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12376                 } else if (sff8472_comp == 0x00) {
12377                         /* Module is not SFF-8472 compliant */
12378                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12379                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12380                 } else {
12381                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
12382                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12383                 }
12384                 break;
12385         case I40E_MODULE_TYPE_QSFP_PLUS:
12386                 /* Read from memory page 0. */
12387                 status = i40e_aq_get_phy_register(hw,
12388                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12389                                 0, 1,
12390                                 I40E_MODULE_REVISION_ADDR,
12391                                 &sff8636_rev, NULL);
12392                 if (status)
12393                         return -EIO;
12394                 /* Determine revision compliance byte */
12395                 if (sff8636_rev > 0x02) {
12396                         /* Module is SFF-8636 compliant */
12397                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
12398                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12399                 } else {
12400                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
12401                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12402                 }
12403                 break;
12404         case I40E_MODULE_TYPE_QSFP28:
12405                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12406                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12407                 break;
12408         default:
12409                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12410                 return -EINVAL;
12411         }
12412         return 0;
12413 }
12414
12415 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12416                                   struct rte_dev_eeprom_info *info)
12417 {
12418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12419         bool is_sfp = false;
12420         i40e_status status;
12421         uint8_t *data;
12422         uint32_t value = 0;
12423         uint32_t i;
12424
12425         if (!info || !info->length || !info->data)
12426                 return -EINVAL;
12427
12428         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12429                 is_sfp = true;
12430
12431         data = info->data;
12432         for (i = 0; i < info->length; i++) {
12433                 u32 offset = i + info->offset;
12434                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12435
12436                 /* Check if we need to access the other memory page */
12437                 if (is_sfp) {
12438                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12439                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12440                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12441                         }
12442                 } else {
12443                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12444                                 /* Compute memory page number and offset. */
12445                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12446                                 addr++;
12447                         }
12448                 }
12449                 status = i40e_aq_get_phy_register(hw,
12450                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12451                                 addr, 1, offset, &value, NULL);
12452                 if (status)
12453                         return -EIO;
12454                 data[i] = (uint8_t)value;
12455         }
12456         return 0;
12457 }
12458
12459 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12460                                      struct rte_ether_addr *mac_addr)
12461 {
12462         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12463         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12464         struct i40e_vsi *vsi = pf->main_vsi;
12465         struct i40e_mac_filter_info mac_filter;
12466         struct i40e_mac_filter *f;
12467         int ret;
12468
12469         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12470                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12471                 return -EINVAL;
12472         }
12473
12474         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12475                 if (rte_is_same_ether_addr(&pf->dev_addr,
12476                                                 &f->mac_info.mac_addr))
12477                         break;
12478         }
12479
12480         if (f == NULL) {
12481                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12482                 return -EIO;
12483         }
12484
12485         mac_filter = f->mac_info;
12486         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12487         if (ret != I40E_SUCCESS) {
12488                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12489                 return -EIO;
12490         }
12491         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12492         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12493         if (ret != I40E_SUCCESS) {
12494                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12495                 return -EIO;
12496         }
12497         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12498
12499         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12500                                         mac_addr->addr_bytes, NULL);
12501         if (ret != I40E_SUCCESS) {
12502                 PMD_DRV_LOG(ERR, "Failed to change mac");
12503                 return -EIO;
12504         }
12505
12506         return 0;
12507 }
12508
12509 static int
12510 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12511 {
12512         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12513         struct rte_eth_dev_data *dev_data = pf->dev_data;
12514         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12515         int ret = 0;
12516
12517         /* check if mtu is within the allowed range */
12518         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12519                 return -EINVAL;
12520
12521         /* mtu setting is forbidden if port is start */
12522         if (dev_data->dev_started) {
12523                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12524                             dev_data->port_id);
12525                 return -EBUSY;
12526         }
12527
12528         if (frame_size > RTE_ETHER_MAX_LEN)
12529                 dev_data->dev_conf.rxmode.offloads |=
12530                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12531         else
12532                 dev_data->dev_conf.rxmode.offloads &=
12533                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12534
12535         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12536
12537         return ret;
12538 }
12539
12540 /* Restore ethertype filter */
12541 static void
12542 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12543 {
12544         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12545         struct i40e_ethertype_filter_list
12546                 *ethertype_list = &pf->ethertype.ethertype_list;
12547         struct i40e_ethertype_filter *f;
12548         struct i40e_control_filter_stats stats;
12549         uint16_t flags;
12550
12551         TAILQ_FOREACH(f, ethertype_list, rules) {
12552                 flags = 0;
12553                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12554                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12555                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12556                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12557                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12558
12559                 memset(&stats, 0, sizeof(stats));
12560                 i40e_aq_add_rem_control_packet_filter(hw,
12561                                             f->input.mac_addr.addr_bytes,
12562                                             f->input.ether_type,
12563                                             flags, pf->main_vsi->seid,
12564                                             f->queue, 1, &stats, NULL);
12565         }
12566         PMD_DRV_LOG(INFO, "Ethertype filter:"
12567                     " mac_etype_used = %u, etype_used = %u,"
12568                     " mac_etype_free = %u, etype_free = %u",
12569                     stats.mac_etype_used, stats.etype_used,
12570                     stats.mac_etype_free, stats.etype_free);
12571 }
12572
12573 /* Restore tunnel filter */
12574 static void
12575 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12576 {
12577         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12578         struct i40e_vsi *vsi;
12579         struct i40e_pf_vf *vf;
12580         struct i40e_tunnel_filter_list
12581                 *tunnel_list = &pf->tunnel.tunnel_list;
12582         struct i40e_tunnel_filter *f;
12583         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12584         bool big_buffer = 0;
12585
12586         TAILQ_FOREACH(f, tunnel_list, rules) {
12587                 if (!f->is_to_vf)
12588                         vsi = pf->main_vsi;
12589                 else {
12590                         vf = &pf->vfs[f->vf_id];
12591                         vsi = vf->vsi;
12592                 }
12593                 memset(&cld_filter, 0, sizeof(cld_filter));
12594                 rte_ether_addr_copy((struct rte_ether_addr *)
12595                                 &f->input.outer_mac,
12596                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12597                 rte_ether_addr_copy((struct rte_ether_addr *)
12598                                 &f->input.inner_mac,
12599                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12600                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12601                 cld_filter.element.flags = f->input.flags;
12602                 cld_filter.element.tenant_id = f->input.tenant_id;
12603                 cld_filter.element.queue_number = f->queue;
12604                 rte_memcpy(cld_filter.general_fields,
12605                            f->input.general_fields,
12606                            sizeof(f->input.general_fields));
12607
12608                 if (((f->input.flags &
12609                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12610                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12611                     ((f->input.flags &
12612                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12613                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12614                     ((f->input.flags &
12615                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12616                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12617                         big_buffer = 1;
12618
12619                 if (big_buffer)
12620                         i40e_aq_add_cloud_filters_bb(hw,
12621                                         vsi->seid, &cld_filter, 1);
12622                 else
12623                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12624                                                   &cld_filter.element, 1);
12625         }
12626 }
12627
12628 /* Restore RSS filter */
12629 static inline void
12630 i40e_rss_filter_restore(struct i40e_pf *pf)
12631 {
12632         struct i40e_rss_conf_list *list = &pf->rss_config_list;
12633         struct i40e_rss_filter *filter;
12634
12635         TAILQ_FOREACH(filter, list, next) {
12636                 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12637         }
12638 }
12639
12640 static void
12641 i40e_filter_restore(struct i40e_pf *pf)
12642 {
12643         i40e_ethertype_filter_restore(pf);
12644         i40e_tunnel_filter_restore(pf);
12645         i40e_fdir_filter_restore(pf);
12646         i40e_rss_filter_restore(pf);
12647 }
12648
12649 bool
12650 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12651 {
12652         if (strcmp(dev->device->driver->name, drv->driver.name))
12653                 return false;
12654
12655         return true;
12656 }
12657
12658 bool
12659 is_i40e_supported(struct rte_eth_dev *dev)
12660 {
12661         return is_device_supported(dev, &rte_i40e_pmd);
12662 }
12663
12664 struct i40e_customized_pctype*
12665 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12666 {
12667         int i;
12668
12669         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12670                 if (pf->customized_pctype[i].index == index)
12671                         return &pf->customized_pctype[i];
12672         }
12673         return NULL;
12674 }
12675
12676 static int
12677 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12678                               uint32_t pkg_size, uint32_t proto_num,
12679                               struct rte_pmd_i40e_proto_info *proto,
12680                               enum rte_pmd_i40e_package_op op)
12681 {
12682         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12683         uint32_t pctype_num;
12684         struct rte_pmd_i40e_ptype_info *pctype;
12685         uint32_t buff_size;
12686         struct i40e_customized_pctype *new_pctype = NULL;
12687         uint8_t proto_id;
12688         uint8_t pctype_value;
12689         char name[64];
12690         uint32_t i, j, n;
12691         int ret;
12692
12693         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12694             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12695                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12696                 return -1;
12697         }
12698
12699         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12700                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12701                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12702         if (ret) {
12703                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12704                 return -1;
12705         }
12706         if (!pctype_num) {
12707                 PMD_DRV_LOG(INFO, "No new pctype added");
12708                 return -1;
12709         }
12710
12711         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12712         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12713         if (!pctype) {
12714                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12715                 return -1;
12716         }
12717         /* get information about new pctype list */
12718         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12719                                         (uint8_t *)pctype, buff_size,
12720                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12721         if (ret) {
12722                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12723                 rte_free(pctype);
12724                 return -1;
12725         }
12726
12727         /* Update customized pctype. */
12728         for (i = 0; i < pctype_num; i++) {
12729                 pctype_value = pctype[i].ptype_id;
12730                 memset(name, 0, sizeof(name));
12731                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12732                         proto_id = pctype[i].protocols[j];
12733                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12734                                 continue;
12735                         for (n = 0; n < proto_num; n++) {
12736                                 if (proto[n].proto_id != proto_id)
12737                                         continue;
12738                                 strlcat(name, proto[n].name, sizeof(name));
12739                                 strlcat(name, "_", sizeof(name));
12740                                 break;
12741                         }
12742                 }
12743                 name[strlen(name) - 1] = '\0';
12744                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12745                 if (!strcmp(name, "GTPC"))
12746                         new_pctype =
12747                                 i40e_find_customized_pctype(pf,
12748                                                       I40E_CUSTOMIZED_GTPC);
12749                 else if (!strcmp(name, "GTPU_IPV4"))
12750                         new_pctype =
12751                                 i40e_find_customized_pctype(pf,
12752                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12753                 else if (!strcmp(name, "GTPU_IPV6"))
12754                         new_pctype =
12755                                 i40e_find_customized_pctype(pf,
12756                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12757                 else if (!strcmp(name, "GTPU"))
12758                         new_pctype =
12759                                 i40e_find_customized_pctype(pf,
12760                                                       I40E_CUSTOMIZED_GTPU);
12761                 else if (!strcmp(name, "IPV4_L2TPV3"))
12762                         new_pctype =
12763                                 i40e_find_customized_pctype(pf,
12764                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12765                 else if (!strcmp(name, "IPV6_L2TPV3"))
12766                         new_pctype =
12767                                 i40e_find_customized_pctype(pf,
12768                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12769                 else if (!strcmp(name, "IPV4_ESP"))
12770                         new_pctype =
12771                                 i40e_find_customized_pctype(pf,
12772                                                 I40E_CUSTOMIZED_ESP_IPV4);
12773                 else if (!strcmp(name, "IPV6_ESP"))
12774                         new_pctype =
12775                                 i40e_find_customized_pctype(pf,
12776                                                 I40E_CUSTOMIZED_ESP_IPV6);
12777                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12778                         new_pctype =
12779                                 i40e_find_customized_pctype(pf,
12780                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12781                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12782                         new_pctype =
12783                                 i40e_find_customized_pctype(pf,
12784                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12785                 else if (!strcmp(name, "IPV4_AH"))
12786                         new_pctype =
12787                                 i40e_find_customized_pctype(pf,
12788                                                 I40E_CUSTOMIZED_AH_IPV4);
12789                 else if (!strcmp(name, "IPV6_AH"))
12790                         new_pctype =
12791                                 i40e_find_customized_pctype(pf,
12792                                                 I40E_CUSTOMIZED_AH_IPV6);
12793                 if (new_pctype) {
12794                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12795                                 new_pctype->pctype = pctype_value;
12796                                 new_pctype->valid = true;
12797                         } else {
12798                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12799                                 new_pctype->valid = false;
12800                         }
12801                 }
12802         }
12803
12804         rte_free(pctype);
12805         return 0;
12806 }
12807
12808 static int
12809 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12810                              uint32_t pkg_size, uint32_t proto_num,
12811                              struct rte_pmd_i40e_proto_info *proto,
12812                              enum rte_pmd_i40e_package_op op)
12813 {
12814         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12815         uint16_t port_id = dev->data->port_id;
12816         uint32_t ptype_num;
12817         struct rte_pmd_i40e_ptype_info *ptype;
12818         uint32_t buff_size;
12819         uint8_t proto_id;
12820         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12821         uint32_t i, j, n;
12822         bool in_tunnel;
12823         int ret;
12824
12825         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12826             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12827                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12828                 return -1;
12829         }
12830
12831         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12832                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12833                 return 0;
12834         }
12835
12836         /* get information about new ptype num */
12837         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12838                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12839                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12840         if (ret) {
12841                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12842                 return ret;
12843         }
12844         if (!ptype_num) {
12845                 PMD_DRV_LOG(INFO, "No new ptype added");
12846                 return -1;
12847         }
12848
12849         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12850         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12851         if (!ptype) {
12852                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12853                 return -1;
12854         }
12855
12856         /* get information about new ptype list */
12857         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12858                                         (uint8_t *)ptype, buff_size,
12859                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12860         if (ret) {
12861                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12862                 rte_free(ptype);
12863                 return ret;
12864         }
12865
12866         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12867         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12868         if (!ptype_mapping) {
12869                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12870                 rte_free(ptype);
12871                 return -1;
12872         }
12873
12874         /* Update ptype mapping table. */
12875         for (i = 0; i < ptype_num; i++) {
12876                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12877                 ptype_mapping[i].sw_ptype = 0;
12878                 in_tunnel = false;
12879                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12880                         proto_id = ptype[i].protocols[j];
12881                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12882                                 continue;
12883                         for (n = 0; n < proto_num; n++) {
12884                                 if (proto[n].proto_id != proto_id)
12885                                         continue;
12886                                 memset(name, 0, sizeof(name));
12887                                 strcpy(name, proto[n].name);
12888                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12889                                 if (!strncasecmp(name, "PPPOE", 5))
12890                                         ptype_mapping[i].sw_ptype |=
12891                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12892                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12893                                          !in_tunnel) {
12894                                         ptype_mapping[i].sw_ptype |=
12895                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12896                                         ptype_mapping[i].sw_ptype |=
12897                                                 RTE_PTYPE_L4_FRAG;
12898                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12899                                            in_tunnel) {
12900                                         ptype_mapping[i].sw_ptype |=
12901                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12902                                         ptype_mapping[i].sw_ptype |=
12903                                                 RTE_PTYPE_INNER_L4_FRAG;
12904                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12905                                         ptype_mapping[i].sw_ptype |=
12906                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12907                                         in_tunnel = true;
12908                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12909                                            !in_tunnel)
12910                                         ptype_mapping[i].sw_ptype |=
12911                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12912                                 else if (!strncasecmp(name, "IPV4", 4) &&
12913                                          in_tunnel)
12914                                         ptype_mapping[i].sw_ptype |=
12915                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12916                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12917                                          !in_tunnel) {
12918                                         ptype_mapping[i].sw_ptype |=
12919                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12920                                         ptype_mapping[i].sw_ptype |=
12921                                                 RTE_PTYPE_L4_FRAG;
12922                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12923                                            in_tunnel) {
12924                                         ptype_mapping[i].sw_ptype |=
12925                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12926                                         ptype_mapping[i].sw_ptype |=
12927                                                 RTE_PTYPE_INNER_L4_FRAG;
12928                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12929                                         ptype_mapping[i].sw_ptype |=
12930                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12931                                         in_tunnel = true;
12932                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12933                                            !in_tunnel)
12934                                         ptype_mapping[i].sw_ptype |=
12935                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12936                                 else if (!strncasecmp(name, "IPV6", 4) &&
12937                                          in_tunnel)
12938                                         ptype_mapping[i].sw_ptype |=
12939                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12940                                 else if (!strncasecmp(name, "UDP", 3) &&
12941                                          !in_tunnel)
12942                                         ptype_mapping[i].sw_ptype |=
12943                                                 RTE_PTYPE_L4_UDP;
12944                                 else if (!strncasecmp(name, "UDP", 3) &&
12945                                          in_tunnel)
12946                                         ptype_mapping[i].sw_ptype |=
12947                                                 RTE_PTYPE_INNER_L4_UDP;
12948                                 else if (!strncasecmp(name, "TCP", 3) &&
12949                                          !in_tunnel)
12950                                         ptype_mapping[i].sw_ptype |=
12951                                                 RTE_PTYPE_L4_TCP;
12952                                 else if (!strncasecmp(name, "TCP", 3) &&
12953                                          in_tunnel)
12954                                         ptype_mapping[i].sw_ptype |=
12955                                                 RTE_PTYPE_INNER_L4_TCP;
12956                                 else if (!strncasecmp(name, "SCTP", 4) &&
12957                                          !in_tunnel)
12958                                         ptype_mapping[i].sw_ptype |=
12959                                                 RTE_PTYPE_L4_SCTP;
12960                                 else if (!strncasecmp(name, "SCTP", 4) &&
12961                                          in_tunnel)
12962                                         ptype_mapping[i].sw_ptype |=
12963                                                 RTE_PTYPE_INNER_L4_SCTP;
12964                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12965                                           !strncasecmp(name, "ICMPV6", 6)) &&
12966                                          !in_tunnel)
12967                                         ptype_mapping[i].sw_ptype |=
12968                                                 RTE_PTYPE_L4_ICMP;
12969                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12970                                           !strncasecmp(name, "ICMPV6", 6)) &&
12971                                          in_tunnel)
12972                                         ptype_mapping[i].sw_ptype |=
12973                                                 RTE_PTYPE_INNER_L4_ICMP;
12974                                 else if (!strncasecmp(name, "GTPC", 4)) {
12975                                         ptype_mapping[i].sw_ptype |=
12976                                                 RTE_PTYPE_TUNNEL_GTPC;
12977                                         in_tunnel = true;
12978                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12979                                         ptype_mapping[i].sw_ptype |=
12980                                                 RTE_PTYPE_TUNNEL_GTPU;
12981                                         in_tunnel = true;
12982                                 } else if (!strncasecmp(name, "ESP", 3)) {
12983                                         ptype_mapping[i].sw_ptype |=
12984                                                 RTE_PTYPE_TUNNEL_ESP;
12985                                         in_tunnel = true;
12986                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12987                                         ptype_mapping[i].sw_ptype |=
12988                                                 RTE_PTYPE_TUNNEL_GRENAT;
12989                                         in_tunnel = true;
12990                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12991                                            !strncasecmp(name, "L2TPV2", 6) ||
12992                                            !strncasecmp(name, "L2TPV3", 6)) {
12993                                         ptype_mapping[i].sw_ptype |=
12994                                                 RTE_PTYPE_TUNNEL_L2TP;
12995                                         in_tunnel = true;
12996                                 }
12997
12998                                 break;
12999                         }
13000                 }
13001         }
13002
13003         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
13004                                                 ptype_num, 0);
13005         if (ret)
13006                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
13007
13008         rte_free(ptype_mapping);
13009         rte_free(ptype);
13010         return ret;
13011 }
13012
13013 void
13014 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
13015                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
13016 {
13017         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
13018         uint32_t proto_num;
13019         struct rte_pmd_i40e_proto_info *proto;
13020         uint32_t buff_size;
13021         uint32_t i;
13022         int ret;
13023
13024         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
13025             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
13026                 PMD_DRV_LOG(ERR, "Unsupported operation.");
13027                 return;
13028         }
13029
13030         /* get information about protocol number */
13031         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13032                                        (uint8_t *)&proto_num, sizeof(proto_num),
13033                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
13034         if (ret) {
13035                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
13036                 return;
13037         }
13038         if (!proto_num) {
13039                 PMD_DRV_LOG(INFO, "No new protocol added");
13040                 return;
13041         }
13042
13043         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
13044         proto = rte_zmalloc("new_proto", buff_size, 0);
13045         if (!proto) {
13046                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
13047                 return;
13048         }
13049
13050         /* get information about protocol list */
13051         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13052                                         (uint8_t *)proto, buff_size,
13053                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
13054         if (ret) {
13055                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
13056                 rte_free(proto);
13057                 return;
13058         }
13059
13060         /* Check if GTP is supported. */
13061         for (i = 0; i < proto_num; i++) {
13062                 if (!strncmp(proto[i].name, "GTP", 3)) {
13063                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13064                                 pf->gtp_support = true;
13065                         else
13066                                 pf->gtp_support = false;
13067                         break;
13068                 }
13069         }
13070
13071         /* Check if ESP is supported. */
13072         for (i = 0; i < proto_num; i++) {
13073                 if (!strncmp(proto[i].name, "ESP", 3)) {
13074                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13075                                 pf->esp_support = true;
13076                         else
13077                                 pf->esp_support = false;
13078                         break;
13079                 }
13080         }
13081
13082         /* Update customized pctype info */
13083         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
13084                                             proto_num, proto, op);
13085         if (ret)
13086                 PMD_DRV_LOG(INFO, "No pctype is updated.");
13087
13088         /* Update customized ptype info */
13089         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
13090                                            proto_num, proto, op);
13091         if (ret)
13092                 PMD_DRV_LOG(INFO, "No ptype is updated.");
13093
13094         rte_free(proto);
13095 }
13096
13097 /* Create a QinQ cloud filter
13098  *
13099  * The Fortville NIC has limited resources for tunnel filters,
13100  * so we can only reuse existing filters.
13101  *
13102  * In step 1 we define which Field Vector fields can be used for
13103  * filter types.
13104  * As we do not have the inner tag defined as a field,
13105  * we have to define it first, by reusing one of L1 entries.
13106  *
13107  * In step 2 we are replacing one of existing filter types with
13108  * a new one for QinQ.
13109  * As we reusing L1 and replacing L2, some of the default filter
13110  * types will disappear,which depends on L1 and L2 entries we reuse.
13111  *
13112  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
13113  *
13114  * 1.   Create L1 filter of outer vlan (12b) which will be in use
13115  *              later when we define the cloud filter.
13116  *      a.      Valid_flags.replace_cloud = 0
13117  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
13118  *      c.      New_filter = 0x10
13119  *      d.      TR bit = 0xff (optional, not used here)
13120  *      e.      Buffer – 2 entries:
13121  *              i.      Byte 0 = 8 (outer vlan FV index).
13122  *                      Byte 1 = 0 (rsv)
13123  *                      Byte 2-3 = 0x0fff
13124  *              ii.     Byte 0 = 37 (inner vlan FV index).
13125  *                      Byte 1 =0 (rsv)
13126  *                      Byte 2-3 = 0x0fff
13127  *
13128  * Step 2:
13129  * 2.   Create cloud filter using two L1 filters entries: stag and
13130  *              new filter(outer vlan+ inner vlan)
13131  *      a.      Valid_flags.replace_cloud = 1
13132  *      b.      Old_filter = 1 (instead of outer IP)
13133  *      c.      New_filter = 0x10
13134  *      d.      Buffer – 2 entries:
13135  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
13136  *                      Byte 1-3 = 0 (rsv)
13137  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13138  *                      Byte 9-11 = 0 (rsv)
13139  */
13140 static int
13141 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13142 {
13143         int ret = -ENOTSUP;
13144         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
13145         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
13146         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13147         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13148
13149         if (pf->support_multi_driver) {
13150                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13151                 return ret;
13152         }
13153
13154         /* Init */
13155         memset(&filter_replace, 0,
13156                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13157         memset(&filter_replace_buf, 0,
13158                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13159
13160         /* create L1 filter */
13161         filter_replace.old_filter_type =
13162                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13163         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13164         filter_replace.tr_bit = 0;
13165
13166         /* Prepare the buffer, 2 entries */
13167         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13168         filter_replace_buf.data[0] |=
13169                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13170         /* Field Vector 12b mask */
13171         filter_replace_buf.data[2] = 0xff;
13172         filter_replace_buf.data[3] = 0x0f;
13173         filter_replace_buf.data[4] =
13174                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13175         filter_replace_buf.data[4] |=
13176                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13177         /* Field Vector 12b mask */
13178         filter_replace_buf.data[6] = 0xff;
13179         filter_replace_buf.data[7] = 0x0f;
13180         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13181                         &filter_replace_buf);
13182         if (ret != I40E_SUCCESS)
13183                 return ret;
13184
13185         if (filter_replace.old_filter_type !=
13186             filter_replace.new_filter_type)
13187                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13188                             " original: 0x%x, new: 0x%x",
13189                             dev->device->name,
13190                             filter_replace.old_filter_type,
13191                             filter_replace.new_filter_type);
13192
13193         /* Apply the second L2 cloud filter */
13194         memset(&filter_replace, 0,
13195                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13196         memset(&filter_replace_buf, 0,
13197                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13198
13199         /* create L2 filter, input for L2 filter will be L1 filter  */
13200         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13201         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13202         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13203
13204         /* Prepare the buffer, 2 entries */
13205         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13206         filter_replace_buf.data[0] |=
13207                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13208         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13209         filter_replace_buf.data[4] |=
13210                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13211         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13212                         &filter_replace_buf);
13213         if (!ret && (filter_replace.old_filter_type !=
13214                      filter_replace.new_filter_type))
13215                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13216                             " original: 0x%x, new: 0x%x",
13217                             dev->device->name,
13218                             filter_replace.old_filter_type,
13219                             filter_replace.new_filter_type);
13220
13221         return ret;
13222 }
13223
13224 int
13225 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13226                    const struct rte_flow_action_rss *in)
13227 {
13228         if (in->key_len > RTE_DIM(out->key) ||
13229             in->queue_num > RTE_DIM(out->queue))
13230                 return -EINVAL;
13231         if (!in->key && in->key_len)
13232                 return -EINVAL;
13233         out->conf = (struct rte_flow_action_rss){
13234                 .func = in->func,
13235                 .level = in->level,
13236                 .types = in->types,
13237                 .key_len = in->key_len,
13238                 .queue_num = in->queue_num,
13239                 .queue = memcpy(out->queue, in->queue,
13240                                 sizeof(*in->queue) * in->queue_num),
13241         };
13242         if (in->key)
13243                 out->conf.key = memcpy(out->key, in->key, in->key_len);
13244         return 0;
13245 }
13246
13247 /* Write HENA register to enable hash */
13248 static int
13249 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13250 {
13251         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13252         uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13253         uint64_t hena;
13254         int ret;
13255
13256         ret = i40e_set_rss_key(pf->main_vsi, key,
13257                                rss_conf->conf.key_len);
13258         if (ret)
13259                 return ret;
13260
13261         hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13262         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13263         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13264         I40E_WRITE_FLUSH(hw);
13265
13266         return 0;
13267 }
13268
13269 /* Configure hash input set */
13270 static int
13271 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13272 {
13273         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13274         struct rte_eth_input_set_conf conf;
13275         uint64_t mask0;
13276         int ret = 0;
13277         uint32_t j;
13278         int i;
13279         static const struct {
13280                 uint64_t type;
13281                 enum rte_eth_input_set_field field;
13282         } inset_match_table[] = {
13283                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13284                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13285                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13286                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13287                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13288                         RTE_ETH_INPUT_SET_UNKNOWN},
13289                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13290                         RTE_ETH_INPUT_SET_UNKNOWN},
13291
13292                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13293                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13294                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13295                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13296                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13297                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13298                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13299                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13300
13301                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13302                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13303                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13304                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13305                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13306                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13307                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13308                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13309
13310                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13311                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13312                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13313                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13314                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13315                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13316                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13317                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13318
13319                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13320                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13321                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13322                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13323                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13324                         RTE_ETH_INPUT_SET_UNKNOWN},
13325                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13326                         RTE_ETH_INPUT_SET_UNKNOWN},
13327
13328                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13329                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13330                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13331                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13332                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13333                         RTE_ETH_INPUT_SET_UNKNOWN},
13334                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13335                         RTE_ETH_INPUT_SET_UNKNOWN},
13336
13337                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13338                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13339                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13340                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13341                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13342                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13343                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13344                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13345
13346                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13347                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13348                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13349                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13350                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13351                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13352                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13353                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13354
13355                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13356                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13357                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13358                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13359                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13360                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13361                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13362                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13363
13364                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13365                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13366                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13367                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13368                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13369                         RTE_ETH_INPUT_SET_UNKNOWN},
13370                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13371                         RTE_ETH_INPUT_SET_UNKNOWN},
13372         };
13373
13374         mask0 = types & pf->adapter->flow_types_mask;
13375         conf.op = RTE_ETH_INPUT_SET_SELECT;
13376         conf.inset_size = 0;
13377         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13378                 if (mask0 & (1ULL << i)) {
13379                         conf.flow_type = i;
13380                         break;
13381                 }
13382         }
13383
13384         for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13385                 if ((types & inset_match_table[j].type) ==
13386                     inset_match_table[j].type) {
13387                         if (inset_match_table[j].field ==
13388                             RTE_ETH_INPUT_SET_UNKNOWN)
13389                                 return -EINVAL;
13390
13391                         conf.field[conf.inset_size] =
13392                                 inset_match_table[j].field;
13393                         conf.inset_size++;
13394                 }
13395         }
13396
13397         if (conf.inset_size) {
13398                 ret = i40e_hash_filter_inset_select(hw, &conf);
13399                 if (ret)
13400                         return ret;
13401         }
13402
13403         return ret;
13404 }
13405
13406 /* Look up the conflicted rule then mark it as invalid */
13407 static void
13408 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13409                 struct i40e_rte_flow_rss_conf *conf)
13410 {
13411         struct i40e_rss_filter *rss_item;
13412         uint64_t rss_inset;
13413
13414         /* Clear input set bits before comparing the pctype */
13415         rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13416                 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13417
13418         /* Look up the conflicted rule then mark it as invalid */
13419         TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13420                 if (!rss_item->rss_filter_info.valid)
13421                         continue;
13422
13423                 if (conf->conf.queue_num &&
13424                     rss_item->rss_filter_info.conf.queue_num)
13425                         rss_item->rss_filter_info.valid = false;
13426
13427                 if (conf->conf.types &&
13428                     (rss_item->rss_filter_info.conf.types &
13429                     rss_inset) ==
13430                     (conf->conf.types & rss_inset))
13431                         rss_item->rss_filter_info.valid = false;
13432
13433                 if (conf->conf.func ==
13434                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13435                     rss_item->rss_filter_info.conf.func ==
13436                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13437                         rss_item->rss_filter_info.valid = false;
13438         }
13439 }
13440
13441 /* Configure RSS hash function */
13442 static int
13443 i40e_rss_config_hash_function(struct i40e_pf *pf,
13444                 struct i40e_rte_flow_rss_conf *conf)
13445 {
13446         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13447         uint32_t reg, i;
13448         uint64_t mask0;
13449         uint16_t j;
13450
13451         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13452                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13453                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13454                         PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13455                         I40E_WRITE_FLUSH(hw);
13456                         i40e_rss_mark_invalid_rule(pf, conf);
13457
13458                         return 0;
13459                 }
13460                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13461
13462                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13463                 I40E_WRITE_FLUSH(hw);
13464                 i40e_rss_mark_invalid_rule(pf, conf);
13465         } else if (conf->conf.func ==
13466                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13467                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13468
13469                 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13470                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13471                         if (mask0 & (1UL << i))
13472                                 break;
13473                 }
13474
13475                 if (i == UINT64_BIT)
13476                         return -EINVAL;
13477
13478                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13479                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13480                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13481                                 i40e_write_global_rx_ctl(hw,
13482                                         I40E_GLQF_HSYM(j),
13483                                         I40E_GLQF_HSYM_SYMH_ENA_MASK);
13484                 }
13485         }
13486
13487         return 0;
13488 }
13489
13490 /* Enable RSS according to the configuration */
13491 static int
13492 i40e_rss_enable_hash(struct i40e_pf *pf,
13493                 struct i40e_rte_flow_rss_conf *conf)
13494 {
13495         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13496         struct i40e_rte_flow_rss_conf rss_conf;
13497
13498         if (!(conf->conf.types & pf->adapter->flow_types_mask))
13499                 return -ENOTSUP;
13500
13501         memset(&rss_conf, 0, sizeof(rss_conf));
13502         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13503
13504         /* Configure hash input set */
13505         if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13506                 return -EINVAL;
13507
13508         if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13509             (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13510                 /* Random default keys */
13511                 static uint32_t rss_key_default[] = {0x6b793944,
13512                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13513                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13514                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13515
13516                 rss_conf.conf.key = (uint8_t *)rss_key_default;
13517                 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13518                                 sizeof(uint32_t);
13519                 PMD_DRV_LOG(INFO,
13520                         "No valid RSS key config for i40e, using default\n");
13521         }
13522
13523         rss_conf.conf.types |= rss_info->conf.types;
13524         i40e_rss_hash_set(pf, &rss_conf);
13525
13526         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13527                 i40e_rss_config_hash_function(pf, conf);
13528
13529         i40e_rss_mark_invalid_rule(pf, conf);
13530
13531         return 0;
13532 }
13533
13534 /* Configure RSS queue region */
13535 static int
13536 i40e_rss_config_queue_region(struct i40e_pf *pf,
13537                 struct i40e_rte_flow_rss_conf *conf)
13538 {
13539         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13540         uint32_t lut = 0;
13541         uint16_t j, num;
13542         uint32_t i;
13543
13544         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13545          * It's necessary to calculate the actual PF queues that are configured.
13546          */
13547         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13548                 num = i40e_pf_calc_configured_queues_num(pf);
13549         else
13550                 num = pf->dev_data->nb_rx_queues;
13551
13552         num = RTE_MIN(num, conf->conf.queue_num);
13553         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13554                         num);
13555
13556         if (num == 0) {
13557                 PMD_DRV_LOG(ERR,
13558                         "No PF queues are configured to enable RSS for port %u",
13559                         pf->dev_data->port_id);
13560                 return -ENOTSUP;
13561         }
13562
13563         /* Fill in redirection table */
13564         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13565                 if (j == num)
13566                         j = 0;
13567                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13568                         hw->func_caps.rss_table_entry_width) - 1));
13569                 if ((i & 3) == 3)
13570                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13571         }
13572
13573         i40e_rss_mark_invalid_rule(pf, conf);
13574
13575         return 0;
13576 }
13577
13578 /* Configure RSS hash function to default */
13579 static int
13580 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13581                 struct i40e_rte_flow_rss_conf *conf)
13582 {
13583         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13584         uint32_t i, reg;
13585         uint64_t mask0;
13586         uint16_t j;
13587
13588         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13589                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13590                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13591                         PMD_DRV_LOG(DEBUG,
13592                                 "Hash function already set to Toeplitz");
13593                         I40E_WRITE_FLUSH(hw);
13594
13595                         return 0;
13596                 }
13597                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13598
13599                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13600                 I40E_WRITE_FLUSH(hw);
13601         } else if (conf->conf.func ==
13602                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13603                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13604
13605                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13606                         if (mask0 & (1UL << i))
13607                                 break;
13608                 }
13609
13610                 if (i == UINT64_BIT)
13611                         return -EINVAL;
13612
13613                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13614                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13615                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13616                                 i40e_write_global_rx_ctl(hw,
13617                                         I40E_GLQF_HSYM(j),
13618                                         0);
13619                 }
13620         }
13621
13622         return 0;
13623 }
13624
13625 /* Disable RSS hash and configure default input set */
13626 static int
13627 i40e_rss_disable_hash(struct i40e_pf *pf,
13628                 struct i40e_rte_flow_rss_conf *conf)
13629 {
13630         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13631         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13632         struct i40e_rte_flow_rss_conf rss_conf;
13633         uint32_t i;
13634
13635         memset(&rss_conf, 0, sizeof(rss_conf));
13636         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13637
13638         /* Disable RSS hash */
13639         rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13640         i40e_rss_hash_set(pf, &rss_conf);
13641
13642         for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13643                 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13644                     !(conf->conf.types & (1ULL << i)))
13645                         continue;
13646
13647                 /* Configure default input set */
13648                 struct rte_eth_input_set_conf input_conf = {
13649                         .op = RTE_ETH_INPUT_SET_SELECT,
13650                         .flow_type = i,
13651                         .inset_size = 1,
13652                 };
13653                 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13654                 i40e_hash_filter_inset_select(hw, &input_conf);
13655         }
13656
13657         rss_info->conf.types = rss_conf.conf.types;
13658
13659         i40e_rss_clear_hash_function(pf, conf);
13660
13661         return 0;
13662 }
13663
13664 /* Configure RSS queue region to default */
13665 static int
13666 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13667 {
13668         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13669         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13670         uint16_t queue[I40E_MAX_Q_PER_TC];
13671         uint32_t num_rxq, i;
13672         uint32_t lut = 0;
13673         uint16_t j, num;
13674
13675         num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13676
13677         for (j = 0; j < num_rxq; j++)
13678                 queue[j] = j;
13679
13680         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13681          * It's necessary to calculate the actual PF queues that are configured.
13682          */
13683         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13684                 num = i40e_pf_calc_configured_queues_num(pf);
13685         else
13686                 num = pf->dev_data->nb_rx_queues;
13687
13688         num = RTE_MIN(num, num_rxq);
13689         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13690                         num);
13691
13692         if (num == 0) {
13693                 PMD_DRV_LOG(ERR,
13694                         "No PF queues are configured to enable RSS for port %u",
13695                         pf->dev_data->port_id);
13696                 return -ENOTSUP;
13697         }
13698
13699         /* Fill in redirection table */
13700         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13701                 if (j == num)
13702                         j = 0;
13703                 lut = (lut << 8) | (queue[j] & ((0x1 <<
13704                         hw->func_caps.rss_table_entry_width) - 1));
13705                 if ((i & 3) == 3)
13706                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13707         }
13708
13709         rss_info->conf.queue_num = 0;
13710         memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13711
13712         return 0;
13713 }
13714
13715 int
13716 i40e_config_rss_filter(struct i40e_pf *pf,
13717                 struct i40e_rte_flow_rss_conf *conf, bool add)
13718 {
13719         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13720         struct rte_flow_action_rss update_conf = rss_info->conf;
13721         int ret = 0;
13722
13723         if (add) {
13724                 if (conf->conf.queue_num) {
13725                         /* Configure RSS queue region */
13726                         ret = i40e_rss_config_queue_region(pf, conf);
13727                         if (ret)
13728                                 return ret;
13729
13730                         update_conf.queue_num = conf->conf.queue_num;
13731                         update_conf.queue = conf->conf.queue;
13732                 } else if (conf->conf.func ==
13733                            RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13734                         /* Configure hash function */
13735                         ret = i40e_rss_config_hash_function(pf, conf);
13736                         if (ret)
13737                                 return ret;
13738
13739                         update_conf.func = conf->conf.func;
13740                 } else {
13741                         /* Configure hash enable and input set */
13742                         ret = i40e_rss_enable_hash(pf, conf);
13743                         if (ret)
13744                                 return ret;
13745
13746                         update_conf.types |= conf->conf.types;
13747                         update_conf.key = conf->conf.key;
13748                         update_conf.key_len = conf->conf.key_len;
13749                 }
13750
13751                 /* Update RSS info in pf */
13752                 if (i40e_rss_conf_init(rss_info, &update_conf))
13753                         return -EINVAL;
13754         } else {
13755                 if (!conf->valid)
13756                         return 0;
13757
13758                 if (conf->conf.queue_num)
13759                         i40e_rss_clear_queue_region(pf);
13760                 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13761                         i40e_rss_clear_hash_function(pf, conf);
13762                 else
13763                         i40e_rss_disable_hash(pf, conf);
13764         }
13765
13766         return 0;
13767 }
13768
13769 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13770 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13771 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13772 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13773 #endif
13774 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13775 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13776 #endif
13777 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13778 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13779 #endif
13780
13781 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13782                               ETH_I40E_FLOATING_VEB_ARG "=1"
13783                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13784                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13785                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13786                               ETH_I40E_USE_LATEST_VEC "=0|1");