4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
54 #include <rte_hash_crc.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_adminq_cmd.h"
59 #include "base/i40e_type.h"
60 #include "base/i40e_register.h"
61 #include "base/i40e_dcb.h"
62 #include "i40e_ethdev.h"
63 #include "i40e_rxtx.h"
65 #include "i40e_regs.h"
67 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
68 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
70 #define I40E_CLEAR_PXE_WAIT_MS 200
72 /* Maximun number of capability elements */
73 #define I40E_MAX_CAP_ELE_NUM 128
75 /* Wait count and inteval */
76 #define I40E_CHK_Q_ENA_COUNT 1000
77 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
79 /* Maximun number of VSI */
80 #define I40E_MAX_NUM_VSIS (384UL)
82 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
84 /* Flow control default timer */
85 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
87 /* Flow control default high water */
88 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
90 /* Flow control default low water */
91 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
93 /* Flow control enable fwd bit */
94 #define I40E_PRTMAC_FWD_CTRL 0x00000001
96 /* Receive Packet Buffer size */
97 #define I40E_RXPBSIZE (968 * 1024)
100 #define I40E_KILOSHIFT 10
102 /* Receive Average Packet Size in Byte*/
103 #define I40E_PACKET_AVERAGE_SIZE 128
105 /* Mask of PF interrupt causes */
106 #define I40E_PFINT_ICR0_ENA_MASK ( \
107 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
108 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
109 I40E_PFINT_ICR0_ENA_GRST_MASK | \
110 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
111 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
112 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
113 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
114 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
115 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
117 #define I40E_FLOW_TYPES ( \
118 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
123 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
128 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
130 /* Additional timesync values. */
131 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
132 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
133 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
134 #define I40E_PRTTSYN_TSYNENA 0x80000000
135 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
136 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
138 #define I40E_MAX_PERCENT 100
139 #define I40E_DEFAULT_DCB_APP_NUM 1
140 #define I40E_DEFAULT_DCB_APP_PRIO 3
142 #define I40E_INSET_NONE 0x00000000000000000ULL
145 #define I40E_INSET_DMAC 0x0000000000000001ULL
146 #define I40E_INSET_SMAC 0x0000000000000002ULL
147 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
148 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
149 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
152 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
153 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
154 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
155 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
156 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
157 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
158 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
160 /* bit 16 ~ bit 31 */
161 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
162 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
163 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
164 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
165 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
166 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
167 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
168 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
170 /* bit 32 ~ bit 47, tunnel fields */
171 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
172 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
173 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
174 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
175 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
176 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
178 /* bit 48 ~ bit 55 */
179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
181 /* bit 56 ~ bit 63, Flex Payload */
182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
190 #define I40E_INSET_FLEX_PAYLOAD \
191 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
192 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
193 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
194 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
197 * Below are values for writing un-exposed registers suggested
200 /* Destination MAC address */
201 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
202 /* Source MAC address */
203 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
205 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
207 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
208 /* Single VLAN tag in the inner L2 header */
209 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
210 /* Source IPv4 address */
211 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
212 /* Destination IPv4 address */
213 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
214 /* Source IPv4 address for X722 */
215 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
216 /* Destination IPv4 address for X722 */
217 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
218 /* IPv4 Protocol for X722 */
219 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
220 /* IPv4 Time to Live for X722 */
221 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
222 /* IPv4 Type of Service (TOS) */
223 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
225 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
226 /* IPv4 Time to Live */
227 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
228 /* Source IPv6 address */
229 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
230 /* Destination IPv6 address */
231 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
232 /* IPv6 Traffic Class (TC) */
233 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
234 /* IPv6 Next Header */
235 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
237 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
239 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
240 /* Destination L4 port */
241 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
242 /* SCTP verification tag */
243 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
244 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
245 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
246 /* Source port of tunneling UDP */
247 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
248 /* Destination port of tunneling UDP */
249 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
250 /* UDP Tunneling ID, NVGRE/GRE key */
251 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
252 /* Last ether type */
253 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
254 /* Tunneling outer destination IPv4 address */
255 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
256 /* Tunneling outer destination IPv6 address */
257 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
258 /* 1st word of flex payload */
259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
260 /* 2nd word of flex payload */
261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
262 /* 3rd word of flex payload */
263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
264 /* 4th word of flex payload */
265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
266 /* 5th word of flex payload */
267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
268 /* 6th word of flex payload */
269 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
270 /* 7th word of flex payload */
271 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
272 /* 8th word of flex payload */
273 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
274 /* all 8 words flex payload */
275 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
276 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
278 #define I40E_TRANSLATE_INSET 0
279 #define I40E_TRANSLATE_REG 1
281 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
282 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
283 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
284 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
285 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
286 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
288 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
290 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
291 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
293 /* PCI offset for querying capability */
294 #define PCI_DEV_CAP_REG 0xA4
295 /* PCI offset for enabling/disabling Extended Tag */
296 #define PCI_DEV_CTRL_REG 0xA8
297 /* Bit mask of Extended Tag capability */
298 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
299 /* Bit shift of Extended Tag enable/disable */
300 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
301 /* Bit mask of Extended Tag enable/disable */
302 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
304 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
305 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
306 static int i40e_dev_configure(struct rte_eth_dev *dev);
307 static int i40e_dev_start(struct rte_eth_dev *dev);
308 static void i40e_dev_stop(struct rte_eth_dev *dev);
309 static void i40e_dev_close(struct rte_eth_dev *dev);
310 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
311 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
312 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
313 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
314 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
315 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
316 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
317 struct rte_eth_stats *stats);
318 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
319 struct rte_eth_xstat *xstats, unsigned n);
320 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
321 struct rte_eth_xstat_name *xstats_names,
323 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
324 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
328 static int i40e_fw_version_get(struct rte_eth_dev *dev,
329 char *fw_version, size_t fw_size);
330 static void i40e_dev_info_get(struct rte_eth_dev *dev,
331 struct rte_eth_dev_info *dev_info);
332 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
335 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
336 enum rte_vlan_type vlan_type,
338 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
339 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
342 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
343 static int i40e_dev_led_on(struct rte_eth_dev *dev);
344 static int i40e_dev_led_off(struct rte_eth_dev *dev);
345 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
346 struct rte_eth_fc_conf *fc_conf);
347 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
348 struct rte_eth_fc_conf *fc_conf);
349 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
350 struct rte_eth_pfc_conf *pfc_conf);
351 static void i40e_macaddr_add(struct rte_eth_dev *dev,
352 struct ether_addr *mac_addr,
355 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
356 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
357 struct rte_eth_rss_reta_entry64 *reta_conf,
359 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
360 struct rte_eth_rss_reta_entry64 *reta_conf,
363 static int i40e_get_cap(struct i40e_hw *hw);
364 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
365 static int i40e_pf_setup(struct i40e_pf *pf);
366 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
367 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
368 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
369 static int i40e_dcb_setup(struct rte_eth_dev *dev);
370 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
371 bool offset_loaded, uint64_t *offset, uint64_t *stat);
372 static void i40e_stat_update_48(struct i40e_hw *hw,
378 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
379 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
381 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
382 uint32_t base, uint32_t num);
383 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
384 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
386 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
388 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
389 static int i40e_veb_release(struct i40e_veb *veb);
390 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
391 struct i40e_vsi *vsi);
392 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
393 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
394 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
395 struct i40e_macvlan_filter *mv_f,
397 struct ether_addr *addr);
398 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
399 struct i40e_macvlan_filter *mv_f,
402 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
403 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
404 struct rte_eth_rss_conf *rss_conf);
405 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
406 struct rte_eth_rss_conf *rss_conf);
407 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
408 struct rte_eth_udp_tunnel *udp_tunnel);
409 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
410 struct rte_eth_udp_tunnel *udp_tunnel);
411 static void i40e_filter_input_set_init(struct i40e_pf *pf);
412 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
413 struct rte_eth_ethertype_filter *filter,
415 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
416 enum rte_filter_op filter_op,
418 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
419 enum rte_filter_type filter_type,
420 enum rte_filter_op filter_op,
422 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
423 struct rte_eth_dcb_info *dcb_info);
424 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
425 static void i40e_configure_registers(struct i40e_hw *hw);
426 static void i40e_hw_init(struct rte_eth_dev *dev);
427 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
428 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
429 struct rte_eth_mirror_conf *mirror_conf,
430 uint8_t sw_id, uint8_t on);
431 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
433 static int i40e_timesync_enable(struct rte_eth_dev *dev);
434 static int i40e_timesync_disable(struct rte_eth_dev *dev);
435 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
436 struct timespec *timestamp,
438 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
439 struct timespec *timestamp);
440 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
442 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
444 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
445 struct timespec *timestamp);
446 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
447 const struct timespec *timestamp);
449 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
451 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
454 static int i40e_get_regs(struct rte_eth_dev *dev,
455 struct rte_dev_reg_info *regs);
457 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
459 static int i40e_get_eeprom(struct rte_eth_dev *dev,
460 struct rte_dev_eeprom_info *eeprom);
462 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
463 struct ether_addr *mac_addr);
465 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
467 static int i40e_ethertype_filter_convert(
468 const struct rte_eth_ethertype_filter *input,
469 struct i40e_ethertype_filter *filter);
470 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
471 struct i40e_ethertype_filter *filter);
473 static int i40e_tunnel_filter_convert(
474 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
475 struct i40e_tunnel_filter *tunnel_filter);
476 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
477 struct i40e_tunnel_filter *tunnel_filter);
479 static const struct rte_pci_id pci_id_i40e_map[] = {
480 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
481 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
482 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
483 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
484 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
485 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
486 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
487 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
488 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
489 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
490 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
491 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
492 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
493 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
494 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
495 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
496 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
497 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
498 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
499 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
500 { .vendor_id = 0, /* sentinel */ },
503 static const struct eth_dev_ops i40e_eth_dev_ops = {
504 .dev_configure = i40e_dev_configure,
505 .dev_start = i40e_dev_start,
506 .dev_stop = i40e_dev_stop,
507 .dev_close = i40e_dev_close,
508 .promiscuous_enable = i40e_dev_promiscuous_enable,
509 .promiscuous_disable = i40e_dev_promiscuous_disable,
510 .allmulticast_enable = i40e_dev_allmulticast_enable,
511 .allmulticast_disable = i40e_dev_allmulticast_disable,
512 .dev_set_link_up = i40e_dev_set_link_up,
513 .dev_set_link_down = i40e_dev_set_link_down,
514 .link_update = i40e_dev_link_update,
515 .stats_get = i40e_dev_stats_get,
516 .xstats_get = i40e_dev_xstats_get,
517 .xstats_get_names = i40e_dev_xstats_get_names,
518 .stats_reset = i40e_dev_stats_reset,
519 .xstats_reset = i40e_dev_stats_reset,
520 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
521 .fw_version_get = i40e_fw_version_get,
522 .dev_infos_get = i40e_dev_info_get,
523 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
524 .vlan_filter_set = i40e_vlan_filter_set,
525 .vlan_tpid_set = i40e_vlan_tpid_set,
526 .vlan_offload_set = i40e_vlan_offload_set,
527 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
528 .vlan_pvid_set = i40e_vlan_pvid_set,
529 .rx_queue_start = i40e_dev_rx_queue_start,
530 .rx_queue_stop = i40e_dev_rx_queue_stop,
531 .tx_queue_start = i40e_dev_tx_queue_start,
532 .tx_queue_stop = i40e_dev_tx_queue_stop,
533 .rx_queue_setup = i40e_dev_rx_queue_setup,
534 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
535 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
536 .rx_queue_release = i40e_dev_rx_queue_release,
537 .rx_queue_count = i40e_dev_rx_queue_count,
538 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
539 .tx_queue_setup = i40e_dev_tx_queue_setup,
540 .tx_queue_release = i40e_dev_tx_queue_release,
541 .dev_led_on = i40e_dev_led_on,
542 .dev_led_off = i40e_dev_led_off,
543 .flow_ctrl_get = i40e_flow_ctrl_get,
544 .flow_ctrl_set = i40e_flow_ctrl_set,
545 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
546 .mac_addr_add = i40e_macaddr_add,
547 .mac_addr_remove = i40e_macaddr_remove,
548 .reta_update = i40e_dev_rss_reta_update,
549 .reta_query = i40e_dev_rss_reta_query,
550 .rss_hash_update = i40e_dev_rss_hash_update,
551 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
552 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
553 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
554 .filter_ctrl = i40e_dev_filter_ctrl,
555 .rxq_info_get = i40e_rxq_info_get,
556 .txq_info_get = i40e_txq_info_get,
557 .mirror_rule_set = i40e_mirror_rule_set,
558 .mirror_rule_reset = i40e_mirror_rule_reset,
559 .timesync_enable = i40e_timesync_enable,
560 .timesync_disable = i40e_timesync_disable,
561 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
562 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
563 .get_dcb_info = i40e_dev_get_dcb_info,
564 .timesync_adjust_time = i40e_timesync_adjust_time,
565 .timesync_read_time = i40e_timesync_read_time,
566 .timesync_write_time = i40e_timesync_write_time,
567 .get_reg = i40e_get_regs,
568 .get_eeprom_length = i40e_get_eeprom_length,
569 .get_eeprom = i40e_get_eeprom,
570 .mac_addr_set = i40e_set_default_mac_addr,
571 .mtu_set = i40e_dev_mtu_set,
574 /* store statistics names and its offset in stats structure */
575 struct rte_i40e_xstats_name_off {
576 char name[RTE_ETH_XSTATS_NAME_SIZE];
580 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
581 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
582 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
583 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
584 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
585 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
586 rx_unknown_protocol)},
587 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
588 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
589 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
590 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
593 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
594 sizeof(rte_i40e_stats_strings[0]))
596 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
597 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
598 tx_dropped_link_down)},
599 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
600 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
602 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
603 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
605 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
607 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
609 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
610 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
611 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
612 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
613 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
614 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
616 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
618 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
620 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
622 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
624 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
626 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
628 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
630 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
631 mac_short_packet_dropped)},
632 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
634 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
635 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
636 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
638 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
640 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
642 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
644 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
646 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
648 {"rx_flow_director_atr_match_packets",
649 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
650 {"rx_flow_director_sb_match_packets",
651 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
652 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
654 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
656 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
658 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
662 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
663 sizeof(rte_i40e_hw_port_strings[0]))
665 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
666 {"xon_packets", offsetof(struct i40e_hw_port_stats,
668 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
672 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
673 sizeof(rte_i40e_rxq_prio_strings[0]))
675 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
676 {"xon_packets", offsetof(struct i40e_hw_port_stats,
678 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
680 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
681 priority_xon_2_xoff)},
684 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
685 sizeof(rte_i40e_txq_prio_strings[0]))
687 static struct eth_driver rte_i40e_pmd = {
689 .id_table = pci_id_i40e_map,
690 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
691 .probe = rte_eth_dev_pci_probe,
692 .remove = rte_eth_dev_pci_remove,
694 .eth_dev_init = eth_i40e_dev_init,
695 .eth_dev_uninit = eth_i40e_dev_uninit,
696 .dev_private_size = sizeof(struct i40e_adapter),
700 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
701 struct rte_eth_link *link)
703 struct rte_eth_link *dst = link;
704 struct rte_eth_link *src = &(dev->data->dev_link);
706 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
707 *(uint64_t *)src) == 0)
714 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
715 struct rte_eth_link *link)
717 struct rte_eth_link *dst = &(dev->data->dev_link);
718 struct rte_eth_link *src = link;
720 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
721 *(uint64_t *)src) == 0)
727 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
728 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
729 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
731 #ifndef I40E_GLQF_ORT
732 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
734 #ifndef I40E_GLQF_PIT
735 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
738 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
741 * Initialize registers for flexible payload, which should be set by NVM.
742 * This should be removed from code once it is fixed in NVM.
744 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
745 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
746 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
747 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
748 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
749 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
750 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
751 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
752 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
753 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
754 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
755 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
757 /* Initialize registers for parsing packet type of QinQ */
758 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
759 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
762 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
765 * Add a ethertype filter to drop all flow control frames transmitted
769 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
771 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
772 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
773 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
774 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
777 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
778 I40E_FLOW_CONTROL_ETHERTYPE, flags,
779 pf->main_vsi_seid, 0,
782 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
783 " frames from VSIs.");
787 floating_veb_list_handler(__rte_unused const char *key,
788 const char *floating_veb_value,
792 unsigned int count = 0;
795 bool *vf_floating_veb = opaque;
797 while (isblank(*floating_veb_value))
798 floating_veb_value++;
800 /* Reset floating VEB configuration for VFs */
801 for (idx = 0; idx < I40E_MAX_VF; idx++)
802 vf_floating_veb[idx] = false;
806 while (isblank(*floating_veb_value))
807 floating_veb_value++;
808 if (*floating_veb_value == '\0')
811 idx = strtoul(floating_veb_value, &end, 10);
812 if (errno || end == NULL)
814 while (isblank(*end))
818 } else if ((*end == ';') || (*end == '\0')) {
820 if (min == I40E_MAX_VF)
822 if (max >= I40E_MAX_VF)
823 max = I40E_MAX_VF - 1;
824 for (idx = min; idx <= max; idx++) {
825 vf_floating_veb[idx] = true;
832 floating_veb_value = end + 1;
833 } while (*end != '\0');
842 config_vf_floating_veb(struct rte_devargs *devargs,
843 uint16_t floating_veb,
844 bool *vf_floating_veb)
846 struct rte_kvargs *kvlist;
848 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
852 /* All the VFs attach to the floating VEB by default
853 * when the floating VEB is enabled.
855 for (i = 0; i < I40E_MAX_VF; i++)
856 vf_floating_veb[i] = true;
861 kvlist = rte_kvargs_parse(devargs->args, NULL);
865 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
866 rte_kvargs_free(kvlist);
869 /* When the floating_veb_list parameter exists, all the VFs
870 * will attach to the legacy VEB firstly, then configure VFs
871 * to the floating VEB according to the floating_veb_list.
873 if (rte_kvargs_process(kvlist, floating_veb_list,
874 floating_veb_list_handler,
875 vf_floating_veb) < 0) {
876 rte_kvargs_free(kvlist);
879 rte_kvargs_free(kvlist);
883 i40e_check_floating_handler(__rte_unused const char *key,
885 __rte_unused void *opaque)
887 if (strcmp(value, "1"))
894 is_floating_veb_supported(struct rte_devargs *devargs)
896 struct rte_kvargs *kvlist;
897 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
902 kvlist = rte_kvargs_parse(devargs->args, NULL);
906 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
907 rte_kvargs_free(kvlist);
910 /* Floating VEB is enabled when there's key-value:
911 * enable_floating_veb=1
913 if (rte_kvargs_process(kvlist, floating_veb_key,
914 i40e_check_floating_handler, NULL) < 0) {
915 rte_kvargs_free(kvlist);
918 rte_kvargs_free(kvlist);
924 config_floating_veb(struct rte_eth_dev *dev)
926 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
927 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
928 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
930 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
932 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
934 is_floating_veb_supported(pci_dev->device.devargs);
935 config_vf_floating_veb(pci_dev->device.devargs,
937 pf->floating_veb_list);
939 pf->floating_veb = false;
943 #define I40E_L2_TAGS_S_TAG_SHIFT 1
944 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
947 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
949 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
950 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
951 char ethertype_hash_name[RTE_HASH_NAMESIZE];
954 struct rte_hash_parameters ethertype_hash_params = {
955 .name = ethertype_hash_name,
956 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
957 .key_len = sizeof(struct i40e_ethertype_filter_input),
958 .hash_func = rte_hash_crc,
961 /* Initialize ethertype filter rule list and hash */
962 TAILQ_INIT(ðertype_rule->ethertype_list);
963 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
964 "ethertype_%s", dev->data->name);
965 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
966 if (!ethertype_rule->hash_table) {
967 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
970 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
971 sizeof(struct i40e_ethertype_filter *) *
972 I40E_MAX_ETHERTYPE_FILTER_NUM,
974 if (!ethertype_rule->hash_map) {
976 "Failed to allocate memory for ethertype hash map!");
978 goto err_ethertype_hash_map_alloc;
983 err_ethertype_hash_map_alloc:
984 rte_hash_free(ethertype_rule->hash_table);
990 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
992 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
993 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
994 char tunnel_hash_name[RTE_HASH_NAMESIZE];
997 struct rte_hash_parameters tunnel_hash_params = {
998 .name = tunnel_hash_name,
999 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1000 .key_len = sizeof(struct i40e_tunnel_filter_input),
1001 .hash_func = rte_hash_crc,
1004 /* Initialize tunnel filter rule list and hash */
1005 TAILQ_INIT(&tunnel_rule->tunnel_list);
1006 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1007 "tunnel_%s", dev->data->name);
1008 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1009 if (!tunnel_rule->hash_table) {
1010 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1013 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1014 sizeof(struct i40e_tunnel_filter *) *
1015 I40E_MAX_TUNNEL_FILTER_NUM,
1017 if (!tunnel_rule->hash_map) {
1019 "Failed to allocate memory for tunnel hash map!");
1021 goto err_tunnel_hash_map_alloc;
1026 err_tunnel_hash_map_alloc:
1027 rte_hash_free(tunnel_rule->hash_table);
1033 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1035 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1036 struct i40e_fdir_info *fdir_info = &pf->fdir;
1037 char fdir_hash_name[RTE_HASH_NAMESIZE];
1040 struct rte_hash_parameters fdir_hash_params = {
1041 .name = fdir_hash_name,
1042 .entries = I40E_MAX_FDIR_FILTER_NUM,
1043 .key_len = sizeof(struct rte_eth_fdir_input),
1044 .hash_func = rte_hash_crc,
1047 /* Initialize flow director filter rule list and hash */
1048 TAILQ_INIT(&fdir_info->fdir_list);
1049 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1050 "fdir_%s", dev->data->name);
1051 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1052 if (!fdir_info->hash_table) {
1053 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1056 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1057 sizeof(struct i40e_fdir_filter *) *
1058 I40E_MAX_FDIR_FILTER_NUM,
1060 if (!fdir_info->hash_map) {
1062 "Failed to allocate memory for fdir hash map!");
1064 goto err_fdir_hash_map_alloc;
1068 err_fdir_hash_map_alloc:
1069 rte_hash_free(fdir_info->hash_table);
1075 eth_i40e_dev_init(struct rte_eth_dev *dev)
1077 struct rte_pci_device *pci_dev;
1078 struct rte_intr_handle *intr_handle;
1079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1080 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1081 struct i40e_vsi *vsi;
1084 uint8_t aq_fail = 0;
1086 PMD_INIT_FUNC_TRACE();
1088 dev->dev_ops = &i40e_eth_dev_ops;
1089 dev->rx_pkt_burst = i40e_recv_pkts;
1090 dev->tx_pkt_burst = i40e_xmit_pkts;
1091 dev->tx_pkt_prepare = i40e_prep_pkts;
1093 /* for secondary processes, we don't initialise any further as primary
1094 * has already done this work. Only check we don't need a different
1096 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1097 i40e_set_rx_function(dev);
1098 i40e_set_tx_function(dev);
1101 pci_dev = I40E_DEV_TO_PCI(dev);
1102 intr_handle = &pci_dev->intr_handle;
1104 rte_eth_copy_pci_info(dev, pci_dev);
1105 dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1107 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1108 pf->adapter->eth_dev = dev;
1109 pf->dev_data = dev->data;
1111 hw->back = I40E_PF_TO_ADAPTER(pf);
1112 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1114 PMD_INIT_LOG(ERR, "Hardware is not available, "
1115 "as address is NULL");
1119 hw->vendor_id = pci_dev->id.vendor_id;
1120 hw->device_id = pci_dev->id.device_id;
1121 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1122 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1123 hw->bus.device = pci_dev->addr.devid;
1124 hw->bus.func = pci_dev->addr.function;
1125 hw->adapter_stopped = 0;
1127 /* Make sure all is clean before doing PF reset */
1130 /* Initialize the hardware */
1133 /* Reset here to make sure all is clean for each PF */
1134 ret = i40e_pf_reset(hw);
1136 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1140 /* Initialize the shared code (base driver) */
1141 ret = i40e_init_shared_code(hw);
1143 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1148 * To work around the NVM issue, initialize registers
1149 * for flexible payload and packet type of QinQ by
1150 * software. It should be removed once issues are fixed
1153 i40e_GLQF_reg_init(hw);
1155 /* Initialize the input set for filters (hash and fd) to default value */
1156 i40e_filter_input_set_init(pf);
1158 /* Initialize the parameters for adminq */
1159 i40e_init_adminq_parameter(hw);
1160 ret = i40e_init_adminq(hw);
1161 if (ret != I40E_SUCCESS) {
1162 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1165 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1166 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1167 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1168 ((hw->nvm.version >> 12) & 0xf),
1169 ((hw->nvm.version >> 4) & 0xff),
1170 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1172 /* Need the special FW version to support floating VEB */
1173 config_floating_veb(dev);
1174 /* Clear PXE mode */
1175 i40e_clear_pxe_mode(hw);
1176 ret = i40e_dev_sync_phy_type(hw);
1178 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1179 goto err_sync_phy_type;
1182 * On X710, performance number is far from the expectation on recent
1183 * firmware versions. The fix for this issue may not be integrated in
1184 * the following firmware version. So the workaround in software driver
1185 * is needed. It needs to modify the initial values of 3 internal only
1186 * registers. Note that the workaround can be removed when it is fixed
1187 * in firmware in the future.
1189 i40e_configure_registers(hw);
1191 /* Get hw capabilities */
1192 ret = i40e_get_cap(hw);
1193 if (ret != I40E_SUCCESS) {
1194 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1195 goto err_get_capabilities;
1198 /* Initialize parameters for PF */
1199 ret = i40e_pf_parameter_init(dev);
1201 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1202 goto err_parameter_init;
1205 /* Initialize the queue management */
1206 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1208 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1209 goto err_qp_pool_init;
1211 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1212 hw->func_caps.num_msix_vectors - 1);
1214 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1215 goto err_msix_pool_init;
1218 /* Initialize lan hmc */
1219 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1220 hw->func_caps.num_rx_qp, 0, 0);
1221 if (ret != I40E_SUCCESS) {
1222 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1223 goto err_init_lan_hmc;
1226 /* Configure lan hmc */
1227 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1228 if (ret != I40E_SUCCESS) {
1229 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1230 goto err_configure_lan_hmc;
1233 /* Get and check the mac address */
1234 i40e_get_mac_addr(hw, hw->mac.addr);
1235 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1236 PMD_INIT_LOG(ERR, "mac address is not valid");
1238 goto err_get_mac_addr;
1240 /* Copy the permanent MAC address */
1241 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1242 (struct ether_addr *) hw->mac.perm_addr);
1244 /* Disable flow control */
1245 hw->fc.requested_mode = I40E_FC_NONE;
1246 i40e_set_fc(hw, &aq_fail, TRUE);
1248 /* Set the global registers with default ether type value */
1249 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1250 if (ret != I40E_SUCCESS) {
1251 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1253 goto err_setup_pf_switch;
1256 /* PF setup, which includes VSI setup */
1257 ret = i40e_pf_setup(pf);
1259 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1260 goto err_setup_pf_switch;
1263 /* reset all stats of the device, including pf and main vsi */
1264 i40e_dev_stats_reset(dev);
1268 /* Disable double vlan by default */
1269 i40e_vsi_config_double_vlan(vsi, FALSE);
1271 /* Disable S-TAG identification when floating_veb is disabled */
1272 if (!pf->floating_veb) {
1273 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1274 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1275 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1276 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1280 if (!vsi->max_macaddrs)
1281 len = ETHER_ADDR_LEN;
1283 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1285 /* Should be after VSI initialized */
1286 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1287 if (!dev->data->mac_addrs) {
1288 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1289 "for storing mac address");
1292 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1293 &dev->data->mac_addrs[0]);
1295 /* initialize pf host driver to setup SRIOV resource if applicable */
1296 i40e_pf_host_init(dev);
1298 /* register callback func to eal lib */
1299 rte_intr_callback_register(intr_handle,
1300 i40e_dev_interrupt_handler, dev);
1302 /* configure and enable device interrupt */
1303 i40e_pf_config_irq0(hw, TRUE);
1304 i40e_pf_enable_irq0(hw);
1306 /* enable uio intr after callback register */
1307 rte_intr_enable(intr_handle);
1309 * Add an ethertype filter to drop all flow control frames transmitted
1310 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1313 i40e_add_tx_flow_control_drop_filter(pf);
1315 /* Set the max frame size to 0x2600 by default,
1316 * in case other drivers changed the default value.
1318 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1320 /* initialize mirror rule list */
1321 TAILQ_INIT(&pf->mirror_list);
1323 /* Init dcb to sw mode by default */
1324 ret = i40e_dcb_init_configure(dev, TRUE);
1325 if (ret != I40E_SUCCESS) {
1326 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1327 pf->flags &= ~I40E_FLAG_DCB;
1330 ret = i40e_init_ethtype_filter_list(dev);
1332 goto err_init_ethtype_filter_list;
1333 ret = i40e_init_tunnel_filter_list(dev);
1335 goto err_init_tunnel_filter_list;
1336 ret = i40e_init_fdir_filter_list(dev);
1338 goto err_init_fdir_filter_list;
1342 err_init_fdir_filter_list:
1343 rte_free(pf->tunnel.hash_table);
1344 rte_free(pf->tunnel.hash_map);
1345 err_init_tunnel_filter_list:
1346 rte_free(pf->ethertype.hash_table);
1347 rte_free(pf->ethertype.hash_map);
1348 err_init_ethtype_filter_list:
1349 rte_free(dev->data->mac_addrs);
1351 i40e_vsi_release(pf->main_vsi);
1352 err_setup_pf_switch:
1354 err_configure_lan_hmc:
1355 (void)i40e_shutdown_lan_hmc(hw);
1357 i40e_res_pool_destroy(&pf->msix_pool);
1359 i40e_res_pool_destroy(&pf->qp_pool);
1362 err_get_capabilities:
1364 (void)i40e_shutdown_adminq(hw);
1370 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1372 struct i40e_ethertype_filter *p_ethertype;
1373 struct i40e_ethertype_rule *ethertype_rule;
1375 ethertype_rule = &pf->ethertype;
1376 /* Remove all ethertype filter rules and hash */
1377 if (ethertype_rule->hash_map)
1378 rte_free(ethertype_rule->hash_map);
1379 if (ethertype_rule->hash_table)
1380 rte_hash_free(ethertype_rule->hash_table);
1382 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1383 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1384 p_ethertype, rules);
1385 rte_free(p_ethertype);
1390 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1392 struct i40e_tunnel_filter *p_tunnel;
1393 struct i40e_tunnel_rule *tunnel_rule;
1395 tunnel_rule = &pf->tunnel;
1396 /* Remove all tunnel director rules and hash */
1397 if (tunnel_rule->hash_map)
1398 rte_free(tunnel_rule->hash_map);
1399 if (tunnel_rule->hash_table)
1400 rte_hash_free(tunnel_rule->hash_table);
1402 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1403 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1409 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1411 struct i40e_fdir_filter *p_fdir;
1412 struct i40e_fdir_info *fdir_info;
1414 fdir_info = &pf->fdir;
1415 /* Remove all flow director rules and hash */
1416 if (fdir_info->hash_map)
1417 rte_free(fdir_info->hash_map);
1418 if (fdir_info->hash_table)
1419 rte_hash_free(fdir_info->hash_table);
1421 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1422 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1428 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1431 struct rte_pci_device *pci_dev;
1432 struct rte_intr_handle *intr_handle;
1434 struct i40e_filter_control_settings settings;
1436 uint8_t aq_fail = 0;
1438 PMD_INIT_FUNC_TRACE();
1440 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1443 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445 pci_dev = I40E_DEV_TO_PCI(dev);
1446 intr_handle = &pci_dev->intr_handle;
1448 if (hw->adapter_stopped == 0)
1449 i40e_dev_close(dev);
1451 dev->dev_ops = NULL;
1452 dev->rx_pkt_burst = NULL;
1453 dev->tx_pkt_burst = NULL;
1455 /* Clear PXE mode */
1456 i40e_clear_pxe_mode(hw);
1458 /* Unconfigure filter control */
1459 memset(&settings, 0, sizeof(settings));
1460 ret = i40e_set_filter_control(hw, &settings);
1462 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1465 /* Disable flow control */
1466 hw->fc.requested_mode = I40E_FC_NONE;
1467 i40e_set_fc(hw, &aq_fail, TRUE);
1469 /* uninitialize pf host driver */
1470 i40e_pf_host_uninit(dev);
1472 rte_free(dev->data->mac_addrs);
1473 dev->data->mac_addrs = NULL;
1475 /* disable uio intr before callback unregister */
1476 rte_intr_disable(intr_handle);
1478 /* register callback func to eal lib */
1479 rte_intr_callback_unregister(intr_handle,
1480 i40e_dev_interrupt_handler, dev);
1482 i40e_rm_ethtype_filter_list(pf);
1483 i40e_rm_tunnel_filter_list(pf);
1484 i40e_rm_fdir_filter_list(pf);
1490 i40e_dev_configure(struct rte_eth_dev *dev)
1492 struct i40e_adapter *ad =
1493 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1494 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1495 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1498 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1499 * bulk allocation or vector Rx preconditions we will reset it.
1501 ad->rx_bulk_alloc_allowed = true;
1502 ad->rx_vec_allowed = true;
1503 ad->tx_simple_allowed = true;
1504 ad->tx_vec_allowed = true;
1506 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1507 ret = i40e_fdir_setup(pf);
1508 if (ret != I40E_SUCCESS) {
1509 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1512 ret = i40e_fdir_configure(dev);
1514 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1518 i40e_fdir_teardown(pf);
1520 ret = i40e_dev_init_vlan(dev);
1525 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1526 * RSS setting have different requirements.
1527 * General PMD driver call sequence are NIC init, configure,
1528 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1529 * will try to lookup the VSI that specific queue belongs to if VMDQ
1530 * applicable. So, VMDQ setting has to be done before
1531 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1532 * For RSS setting, it will try to calculate actual configured RX queue
1533 * number, which will be available after rx_queue_setup(). dev_start()
1534 * function is good to place RSS setup.
1536 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1537 ret = i40e_vmdq_setup(dev);
1542 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1543 ret = i40e_dcb_setup(dev);
1545 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1553 /* need to release vmdq resource if exists */
1554 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1555 i40e_vsi_release(pf->vmdq[i].vsi);
1556 pf->vmdq[i].vsi = NULL;
1561 /* need to release fdir resource if exists */
1562 i40e_fdir_teardown(pf);
1567 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1569 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1570 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1571 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1572 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1573 uint16_t msix_vect = vsi->msix_intr;
1576 for (i = 0; i < vsi->nb_qps; i++) {
1577 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1578 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1582 if (vsi->type != I40E_VSI_SRIOV) {
1583 if (!rte_intr_allow_others(intr_handle)) {
1584 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1585 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1587 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1590 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1591 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1593 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1598 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1599 vsi->user_param + (msix_vect - 1);
1601 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1602 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1604 I40E_WRITE_FLUSH(hw);
1608 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1609 int base_queue, int nb_queue)
1613 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1615 /* Bind all RX queues to allocated MSIX interrupt */
1616 for (i = 0; i < nb_queue; i++) {
1617 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1618 I40E_QINT_RQCTL_ITR_INDX_MASK |
1619 ((base_queue + i + 1) <<
1620 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1621 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1622 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1624 if (i == nb_queue - 1)
1625 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1626 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1629 /* Write first RX queue to Link list register as the head element */
1630 if (vsi->type != I40E_VSI_SRIOV) {
1632 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1634 if (msix_vect == I40E_MISC_VEC_ID) {
1635 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1637 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1639 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1641 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1644 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1646 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1648 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1650 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1657 if (msix_vect == I40E_MISC_VEC_ID) {
1659 I40E_VPINT_LNKLST0(vsi->user_param),
1661 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1663 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1665 /* num_msix_vectors_vf needs to minus irq0 */
1666 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1667 vsi->user_param + (msix_vect - 1);
1669 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1671 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1673 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1677 I40E_WRITE_FLUSH(hw);
1681 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1683 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1684 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1686 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1687 uint16_t msix_vect = vsi->msix_intr;
1688 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1689 uint16_t queue_idx = 0;
1694 for (i = 0; i < vsi->nb_qps; i++) {
1695 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1696 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1699 /* INTENA flag is not auto-cleared for interrupt */
1700 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1701 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1702 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1703 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1704 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1706 /* VF bind interrupt */
1707 if (vsi->type == I40E_VSI_SRIOV) {
1708 __vsi_queues_bind_intr(vsi, msix_vect,
1709 vsi->base_queue, vsi->nb_qps);
1713 /* PF & VMDq bind interrupt */
1714 if (rte_intr_dp_is_en(intr_handle)) {
1715 if (vsi->type == I40E_VSI_MAIN) {
1718 } else if (vsi->type == I40E_VSI_VMDQ2) {
1719 struct i40e_vsi *main_vsi =
1720 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1721 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1726 for (i = 0; i < vsi->nb_used_qps; i++) {
1728 if (!rte_intr_allow_others(intr_handle))
1729 /* allow to share MISC_VEC_ID */
1730 msix_vect = I40E_MISC_VEC_ID;
1732 /* no enough msix_vect, map all to one */
1733 __vsi_queues_bind_intr(vsi, msix_vect,
1734 vsi->base_queue + i,
1735 vsi->nb_used_qps - i);
1736 for (; !!record && i < vsi->nb_used_qps; i++)
1737 intr_handle->intr_vec[queue_idx + i] =
1741 /* 1:1 queue/msix_vect mapping */
1742 __vsi_queues_bind_intr(vsi, msix_vect,
1743 vsi->base_queue + i, 1);
1745 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1753 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1755 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1756 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1757 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1758 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1759 uint16_t interval = i40e_calc_itr_interval(\
1760 RTE_LIBRTE_I40E_ITR_INTERVAL);
1761 uint16_t msix_intr, i;
1763 if (rte_intr_allow_others(intr_handle))
1764 for (i = 0; i < vsi->nb_msix; i++) {
1765 msix_intr = vsi->msix_intr + i;
1766 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1767 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1768 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1769 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1771 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1774 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1775 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1776 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1777 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1779 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1781 I40E_WRITE_FLUSH(hw);
1785 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1787 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1788 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1789 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1790 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1791 uint16_t msix_intr, i;
1793 if (rte_intr_allow_others(intr_handle))
1794 for (i = 0; i < vsi->nb_msix; i++) {
1795 msix_intr = vsi->msix_intr + i;
1796 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1800 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1802 I40E_WRITE_FLUSH(hw);
1805 static inline uint8_t
1806 i40e_parse_link_speeds(uint16_t link_speeds)
1808 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1810 if (link_speeds & ETH_LINK_SPEED_40G)
1811 link_speed |= I40E_LINK_SPEED_40GB;
1812 if (link_speeds & ETH_LINK_SPEED_25G)
1813 link_speed |= I40E_LINK_SPEED_25GB;
1814 if (link_speeds & ETH_LINK_SPEED_20G)
1815 link_speed |= I40E_LINK_SPEED_20GB;
1816 if (link_speeds & ETH_LINK_SPEED_10G)
1817 link_speed |= I40E_LINK_SPEED_10GB;
1818 if (link_speeds & ETH_LINK_SPEED_1G)
1819 link_speed |= I40E_LINK_SPEED_1GB;
1820 if (link_speeds & ETH_LINK_SPEED_100M)
1821 link_speed |= I40E_LINK_SPEED_100MB;
1827 i40e_phy_conf_link(struct i40e_hw *hw,
1829 uint8_t force_speed)
1831 enum i40e_status_code status;
1832 struct i40e_aq_get_phy_abilities_resp phy_ab;
1833 struct i40e_aq_set_phy_config phy_conf;
1834 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1835 I40E_AQ_PHY_FLAG_PAUSE_RX |
1836 I40E_AQ_PHY_FLAG_PAUSE_RX |
1837 I40E_AQ_PHY_FLAG_LOW_POWER;
1838 const uint8_t advt = I40E_LINK_SPEED_40GB |
1839 I40E_LINK_SPEED_25GB |
1840 I40E_LINK_SPEED_10GB |
1841 I40E_LINK_SPEED_1GB |
1842 I40E_LINK_SPEED_100MB;
1846 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1851 memset(&phy_conf, 0, sizeof(phy_conf));
1853 /* bits 0-2 use the values from get_phy_abilities_resp */
1855 abilities |= phy_ab.abilities & mask;
1857 /* update ablities and speed */
1858 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1859 phy_conf.link_speed = advt;
1861 phy_conf.link_speed = force_speed;
1863 phy_conf.abilities = abilities;
1865 /* use get_phy_abilities_resp value for the rest */
1866 phy_conf.phy_type = phy_ab.phy_type;
1867 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1868 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1869 phy_conf.eee_capability = phy_ab.eee_capability;
1870 phy_conf.eeer = phy_ab.eeer_val;
1871 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1873 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1874 phy_ab.abilities, phy_ab.link_speed);
1875 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1876 phy_conf.abilities, phy_conf.link_speed);
1878 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1882 return I40E_SUCCESS;
1886 i40e_apply_link_speed(struct rte_eth_dev *dev)
1889 uint8_t abilities = 0;
1890 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1891 struct rte_eth_conf *conf = &dev->data->dev_conf;
1893 speed = i40e_parse_link_speeds(conf->link_speeds);
1894 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1895 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1896 abilities |= I40E_AQ_PHY_AN_ENABLED;
1897 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1899 /* Skip changing speed on 40G interfaces, FW does not support */
1900 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1901 speed = I40E_LINK_SPEED_UNKNOWN;
1902 abilities |= I40E_AQ_PHY_AN_ENABLED;
1905 return i40e_phy_conf_link(hw, abilities, speed);
1909 i40e_dev_start(struct rte_eth_dev *dev)
1911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 struct i40e_vsi *main_vsi = pf->main_vsi;
1915 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1916 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1917 uint32_t intr_vector = 0;
1919 hw->adapter_stopped = 0;
1921 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1922 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1923 dev->data->port_id);
1927 rte_intr_disable(intr_handle);
1929 if ((rte_intr_cap_multiple(intr_handle) ||
1930 !RTE_ETH_DEV_SRIOV(dev).active) &&
1931 dev->data->dev_conf.intr_conf.rxq != 0) {
1932 intr_vector = dev->data->nb_rx_queues;
1933 if (rte_intr_efd_enable(intr_handle, intr_vector))
1937 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1938 intr_handle->intr_vec =
1939 rte_zmalloc("intr_vec",
1940 dev->data->nb_rx_queues * sizeof(int),
1942 if (!intr_handle->intr_vec) {
1943 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1944 " intr_vec\n", dev->data->nb_rx_queues);
1949 /* Initialize VSI */
1950 ret = i40e_dev_rxtx_init(pf);
1951 if (ret != I40E_SUCCESS) {
1952 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1956 /* Map queues with MSIX interrupt */
1957 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1958 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1959 i40e_vsi_queues_bind_intr(main_vsi);
1960 i40e_vsi_enable_queues_intr(main_vsi);
1962 /* Map VMDQ VSI queues with MSIX interrupt */
1963 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1964 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1965 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1966 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1969 /* enable FDIR MSIX interrupt */
1970 if (pf->fdir.fdir_vsi) {
1971 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1972 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1975 /* Enable all queues which have been configured */
1976 ret = i40e_dev_switch_queues(pf, TRUE);
1977 if (ret != I40E_SUCCESS) {
1978 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1982 /* Enable receiving broadcast packets */
1983 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1984 if (ret != I40E_SUCCESS)
1985 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1987 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1988 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1990 if (ret != I40E_SUCCESS)
1991 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1994 /* Apply link configure */
1995 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1996 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1997 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1998 ETH_LINK_SPEED_40G)) {
1999 PMD_DRV_LOG(ERR, "Invalid link setting");
2002 ret = i40e_apply_link_speed(dev);
2003 if (I40E_SUCCESS != ret) {
2004 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2008 if (!rte_intr_allow_others(intr_handle)) {
2009 rte_intr_callback_unregister(intr_handle,
2010 i40e_dev_interrupt_handler,
2012 /* configure and enable device interrupt */
2013 i40e_pf_config_irq0(hw, FALSE);
2014 i40e_pf_enable_irq0(hw);
2016 if (dev->data->dev_conf.intr_conf.lsc != 0)
2017 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2018 " no intr multiplex\n");
2019 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2020 ret = i40e_aq_set_phy_int_mask(hw,
2021 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2022 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2023 I40E_AQ_EVENT_MEDIA_NA), NULL);
2024 if (ret != I40E_SUCCESS)
2025 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2027 /* Call get_link_info aq commond to enable LSE */
2028 i40e_dev_link_update(dev, 0);
2031 /* enable uio intr after callback register */
2032 rte_intr_enable(intr_handle);
2034 return I40E_SUCCESS;
2037 i40e_dev_switch_queues(pf, FALSE);
2038 i40e_dev_clear_queues(dev);
2044 i40e_dev_stop(struct rte_eth_dev *dev)
2046 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2047 struct i40e_vsi *main_vsi = pf->main_vsi;
2048 struct i40e_mirror_rule *p_mirror;
2049 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2050 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2053 /* Disable all queues */
2054 i40e_dev_switch_queues(pf, FALSE);
2056 /* un-map queues with interrupt registers */
2057 i40e_vsi_disable_queues_intr(main_vsi);
2058 i40e_vsi_queues_unbind_intr(main_vsi);
2060 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2061 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2062 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2065 if (pf->fdir.fdir_vsi) {
2066 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2067 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2069 /* Clear all queues and release memory */
2070 i40e_dev_clear_queues(dev);
2073 i40e_dev_set_link_down(dev);
2075 /* Remove all mirror rules */
2076 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2077 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2080 pf->nb_mirror_rule = 0;
2082 if (!rte_intr_allow_others(intr_handle))
2083 /* resume to the default handler */
2084 rte_intr_callback_register(intr_handle,
2085 i40e_dev_interrupt_handler,
2088 /* Clean datapath event and queue/vec mapping */
2089 rte_intr_efd_disable(intr_handle);
2090 if (intr_handle->intr_vec) {
2091 rte_free(intr_handle->intr_vec);
2092 intr_handle->intr_vec = NULL;
2097 i40e_dev_close(struct rte_eth_dev *dev)
2099 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2100 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2102 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2106 PMD_INIT_FUNC_TRACE();
2109 hw->adapter_stopped = 1;
2110 i40e_dev_free_queues(dev);
2112 /* Disable interrupt */
2113 i40e_pf_disable_irq0(hw);
2114 rte_intr_disable(intr_handle);
2116 /* shutdown and destroy the HMC */
2117 i40e_shutdown_lan_hmc(hw);
2119 /* release all the existing VSIs and VEBs */
2120 i40e_fdir_teardown(pf);
2121 i40e_vsi_release(pf->main_vsi);
2123 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2124 i40e_vsi_release(pf->vmdq[i].vsi);
2125 pf->vmdq[i].vsi = NULL;
2131 /* shutdown the adminq */
2132 i40e_aq_queue_shutdown(hw, true);
2133 i40e_shutdown_adminq(hw);
2135 i40e_res_pool_destroy(&pf->qp_pool);
2136 i40e_res_pool_destroy(&pf->msix_pool);
2138 /* force a PF reset to clean anything leftover */
2139 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2140 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2141 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2142 I40E_WRITE_FLUSH(hw);
2146 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2148 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2149 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150 struct i40e_vsi *vsi = pf->main_vsi;
2153 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2155 if (status != I40E_SUCCESS)
2156 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2158 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2160 if (status != I40E_SUCCESS)
2161 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2166 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2168 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2169 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2170 struct i40e_vsi *vsi = pf->main_vsi;
2173 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2175 if (status != I40E_SUCCESS)
2176 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2178 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2180 if (status != I40E_SUCCESS)
2181 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2185 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2187 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2188 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189 struct i40e_vsi *vsi = pf->main_vsi;
2192 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2193 if (ret != I40E_SUCCESS)
2194 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2198 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2200 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2201 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202 struct i40e_vsi *vsi = pf->main_vsi;
2205 if (dev->data->promiscuous == 1)
2206 return; /* must remain in all_multicast mode */
2208 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2209 vsi->seid, FALSE, NULL);
2210 if (ret != I40E_SUCCESS)
2211 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2215 * Set device link up.
2218 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2220 /* re-apply link speed setting */
2221 return i40e_apply_link_speed(dev);
2225 * Set device link down.
2228 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2230 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2231 uint8_t abilities = 0;
2232 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2234 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2235 return i40e_phy_conf_link(hw, abilities, speed);
2239 i40e_dev_link_update(struct rte_eth_dev *dev,
2240 int wait_to_complete)
2242 #define CHECK_INTERVAL 100 /* 100ms */
2243 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2244 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245 struct i40e_link_status link_status;
2246 struct rte_eth_link link, old;
2248 unsigned rep_cnt = MAX_REPEAT_TIME;
2249 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2251 memset(&link, 0, sizeof(link));
2252 memset(&old, 0, sizeof(old));
2253 memset(&link_status, 0, sizeof(link_status));
2254 rte_i40e_dev_atomic_read_link_status(dev, &old);
2257 /* Get link status information from hardware */
2258 status = i40e_aq_get_link_info(hw, enable_lse,
2259 &link_status, NULL);
2260 if (status != I40E_SUCCESS) {
2261 link.link_speed = ETH_SPEED_NUM_100M;
2262 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2263 PMD_DRV_LOG(ERR, "Failed to get link info");
2267 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2268 if (!wait_to_complete)
2271 rte_delay_ms(CHECK_INTERVAL);
2272 } while (!link.link_status && rep_cnt--);
2274 if (!link.link_status)
2277 /* i40e uses full duplex only */
2278 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2280 /* Parse the link status */
2281 switch (link_status.link_speed) {
2282 case I40E_LINK_SPEED_100MB:
2283 link.link_speed = ETH_SPEED_NUM_100M;
2285 case I40E_LINK_SPEED_1GB:
2286 link.link_speed = ETH_SPEED_NUM_1G;
2288 case I40E_LINK_SPEED_10GB:
2289 link.link_speed = ETH_SPEED_NUM_10G;
2291 case I40E_LINK_SPEED_20GB:
2292 link.link_speed = ETH_SPEED_NUM_20G;
2294 case I40E_LINK_SPEED_25GB:
2295 link.link_speed = ETH_SPEED_NUM_25G;
2297 case I40E_LINK_SPEED_40GB:
2298 link.link_speed = ETH_SPEED_NUM_40G;
2301 link.link_speed = ETH_SPEED_NUM_100M;
2305 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2306 ETH_LINK_SPEED_FIXED);
2309 rte_i40e_dev_atomic_write_link_status(dev, &link);
2310 if (link.link_status == old.link_status)
2316 /* Get all the statistics of a VSI */
2318 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2320 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2321 struct i40e_eth_stats *nes = &vsi->eth_stats;
2322 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2323 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2325 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2326 vsi->offset_loaded, &oes->rx_bytes,
2328 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2329 vsi->offset_loaded, &oes->rx_unicast,
2331 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2332 vsi->offset_loaded, &oes->rx_multicast,
2333 &nes->rx_multicast);
2334 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2335 vsi->offset_loaded, &oes->rx_broadcast,
2336 &nes->rx_broadcast);
2337 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2338 &oes->rx_discards, &nes->rx_discards);
2339 /* GLV_REPC not supported */
2340 /* GLV_RMPC not supported */
2341 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2342 &oes->rx_unknown_protocol,
2343 &nes->rx_unknown_protocol);
2344 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2345 vsi->offset_loaded, &oes->tx_bytes,
2347 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2348 vsi->offset_loaded, &oes->tx_unicast,
2350 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2351 vsi->offset_loaded, &oes->tx_multicast,
2352 &nes->tx_multicast);
2353 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2354 vsi->offset_loaded, &oes->tx_broadcast,
2355 &nes->tx_broadcast);
2356 /* GLV_TDPC not supported */
2357 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2358 &oes->tx_errors, &nes->tx_errors);
2359 vsi->offset_loaded = true;
2361 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2363 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2364 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2365 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2366 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2367 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2368 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2369 nes->rx_unknown_protocol);
2370 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2371 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2372 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2373 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2374 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2375 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2376 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2381 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2384 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2385 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2387 /* Get statistics of struct i40e_eth_stats */
2388 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2389 I40E_GLPRT_GORCL(hw->port),
2390 pf->offset_loaded, &os->eth.rx_bytes,
2392 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2393 I40E_GLPRT_UPRCL(hw->port),
2394 pf->offset_loaded, &os->eth.rx_unicast,
2395 &ns->eth.rx_unicast);
2396 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2397 I40E_GLPRT_MPRCL(hw->port),
2398 pf->offset_loaded, &os->eth.rx_multicast,
2399 &ns->eth.rx_multicast);
2400 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2401 I40E_GLPRT_BPRCL(hw->port),
2402 pf->offset_loaded, &os->eth.rx_broadcast,
2403 &ns->eth.rx_broadcast);
2404 /* Workaround: CRC size should not be included in byte statistics,
2405 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2407 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2408 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2410 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2411 pf->offset_loaded, &os->eth.rx_discards,
2412 &ns->eth.rx_discards);
2413 /* GLPRT_REPC not supported */
2414 /* GLPRT_RMPC not supported */
2415 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2417 &os->eth.rx_unknown_protocol,
2418 &ns->eth.rx_unknown_protocol);
2419 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2420 I40E_GLPRT_GOTCL(hw->port),
2421 pf->offset_loaded, &os->eth.tx_bytes,
2423 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2424 I40E_GLPRT_UPTCL(hw->port),
2425 pf->offset_loaded, &os->eth.tx_unicast,
2426 &ns->eth.tx_unicast);
2427 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2428 I40E_GLPRT_MPTCL(hw->port),
2429 pf->offset_loaded, &os->eth.tx_multicast,
2430 &ns->eth.tx_multicast);
2431 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2432 I40E_GLPRT_BPTCL(hw->port),
2433 pf->offset_loaded, &os->eth.tx_broadcast,
2434 &ns->eth.tx_broadcast);
2435 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2436 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2437 /* GLPRT_TEPC not supported */
2439 /* additional port specific stats */
2440 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2441 pf->offset_loaded, &os->tx_dropped_link_down,
2442 &ns->tx_dropped_link_down);
2443 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2444 pf->offset_loaded, &os->crc_errors,
2446 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2447 pf->offset_loaded, &os->illegal_bytes,
2448 &ns->illegal_bytes);
2449 /* GLPRT_ERRBC not supported */
2450 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2451 pf->offset_loaded, &os->mac_local_faults,
2452 &ns->mac_local_faults);
2453 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2454 pf->offset_loaded, &os->mac_remote_faults,
2455 &ns->mac_remote_faults);
2456 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2457 pf->offset_loaded, &os->rx_length_errors,
2458 &ns->rx_length_errors);
2459 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2460 pf->offset_loaded, &os->link_xon_rx,
2462 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2463 pf->offset_loaded, &os->link_xoff_rx,
2465 for (i = 0; i < 8; i++) {
2466 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2468 &os->priority_xon_rx[i],
2469 &ns->priority_xon_rx[i]);
2470 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2472 &os->priority_xoff_rx[i],
2473 &ns->priority_xoff_rx[i]);
2475 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2476 pf->offset_loaded, &os->link_xon_tx,
2478 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2479 pf->offset_loaded, &os->link_xoff_tx,
2481 for (i = 0; i < 8; i++) {
2482 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2484 &os->priority_xon_tx[i],
2485 &ns->priority_xon_tx[i]);
2486 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2488 &os->priority_xoff_tx[i],
2489 &ns->priority_xoff_tx[i]);
2490 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2492 &os->priority_xon_2_xoff[i],
2493 &ns->priority_xon_2_xoff[i]);
2495 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2496 I40E_GLPRT_PRC64L(hw->port),
2497 pf->offset_loaded, &os->rx_size_64,
2499 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2500 I40E_GLPRT_PRC127L(hw->port),
2501 pf->offset_loaded, &os->rx_size_127,
2503 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2504 I40E_GLPRT_PRC255L(hw->port),
2505 pf->offset_loaded, &os->rx_size_255,
2507 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2508 I40E_GLPRT_PRC511L(hw->port),
2509 pf->offset_loaded, &os->rx_size_511,
2511 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2512 I40E_GLPRT_PRC1023L(hw->port),
2513 pf->offset_loaded, &os->rx_size_1023,
2515 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2516 I40E_GLPRT_PRC1522L(hw->port),
2517 pf->offset_loaded, &os->rx_size_1522,
2519 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2520 I40E_GLPRT_PRC9522L(hw->port),
2521 pf->offset_loaded, &os->rx_size_big,
2523 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2524 pf->offset_loaded, &os->rx_undersize,
2526 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2527 pf->offset_loaded, &os->rx_fragments,
2529 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2530 pf->offset_loaded, &os->rx_oversize,
2532 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2533 pf->offset_loaded, &os->rx_jabber,
2535 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2536 I40E_GLPRT_PTC64L(hw->port),
2537 pf->offset_loaded, &os->tx_size_64,
2539 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2540 I40E_GLPRT_PTC127L(hw->port),
2541 pf->offset_loaded, &os->tx_size_127,
2543 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2544 I40E_GLPRT_PTC255L(hw->port),
2545 pf->offset_loaded, &os->tx_size_255,
2547 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2548 I40E_GLPRT_PTC511L(hw->port),
2549 pf->offset_loaded, &os->tx_size_511,
2551 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2552 I40E_GLPRT_PTC1023L(hw->port),
2553 pf->offset_loaded, &os->tx_size_1023,
2555 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2556 I40E_GLPRT_PTC1522L(hw->port),
2557 pf->offset_loaded, &os->tx_size_1522,
2559 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2560 I40E_GLPRT_PTC9522L(hw->port),
2561 pf->offset_loaded, &os->tx_size_big,
2563 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2565 &os->fd_sb_match, &ns->fd_sb_match);
2566 /* GLPRT_MSPDC not supported */
2567 /* GLPRT_XEC not supported */
2569 pf->offset_loaded = true;
2572 i40e_update_vsi_stats(pf->main_vsi);
2575 /* Get all statistics of a port */
2577 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2579 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2580 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2584 /* call read registers - updates values, now write them to struct */
2585 i40e_read_stats_registers(pf, hw);
2587 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2588 pf->main_vsi->eth_stats.rx_multicast +
2589 pf->main_vsi->eth_stats.rx_broadcast -
2590 pf->main_vsi->eth_stats.rx_discards;
2591 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2592 pf->main_vsi->eth_stats.tx_multicast +
2593 pf->main_vsi->eth_stats.tx_broadcast;
2594 stats->ibytes = ns->eth.rx_bytes;
2595 stats->obytes = ns->eth.tx_bytes;
2596 stats->oerrors = ns->eth.tx_errors +
2597 pf->main_vsi->eth_stats.tx_errors;
2600 stats->imissed = ns->eth.rx_discards +
2601 pf->main_vsi->eth_stats.rx_discards;
2602 stats->ierrors = ns->crc_errors +
2603 ns->rx_length_errors + ns->rx_undersize +
2604 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2606 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2607 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2608 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2609 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2610 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2611 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2612 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2613 ns->eth.rx_unknown_protocol);
2614 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2615 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2616 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2617 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2618 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2619 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2621 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2622 ns->tx_dropped_link_down);
2623 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2624 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2626 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2627 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2628 ns->mac_local_faults);
2629 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2630 ns->mac_remote_faults);
2631 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2632 ns->rx_length_errors);
2633 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2634 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2635 for (i = 0; i < 8; i++) {
2636 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2637 i, ns->priority_xon_rx[i]);
2638 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2639 i, ns->priority_xoff_rx[i]);
2641 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2642 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2643 for (i = 0; i < 8; i++) {
2644 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2645 i, ns->priority_xon_tx[i]);
2646 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2647 i, ns->priority_xoff_tx[i]);
2648 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2649 i, ns->priority_xon_2_xoff[i]);
2651 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2652 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2653 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2654 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2655 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2656 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2657 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2658 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2659 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2660 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2661 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2662 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2663 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2664 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2665 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2666 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2667 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2668 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2669 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2670 ns->mac_short_packet_dropped);
2671 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2672 ns->checksum_error);
2673 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2674 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2677 /* Reset the statistics */
2679 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2681 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2682 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2684 /* Mark PF and VSI stats to update the offset, aka "reset" */
2685 pf->offset_loaded = false;
2687 pf->main_vsi->offset_loaded = false;
2689 /* read the stats, reading current register values into offset */
2690 i40e_read_stats_registers(pf, hw);
2694 i40e_xstats_calc_num(void)
2696 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2697 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2698 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2701 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2702 struct rte_eth_xstat_name *xstats_names,
2703 __rte_unused unsigned limit)
2708 if (xstats_names == NULL)
2709 return i40e_xstats_calc_num();
2711 /* Note: limit checked in rte_eth_xstats_names() */
2713 /* Get stats from i40e_eth_stats struct */
2714 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2715 snprintf(xstats_names[count].name,
2716 sizeof(xstats_names[count].name),
2717 "%s", rte_i40e_stats_strings[i].name);
2721 /* Get individiual stats from i40e_hw_port struct */
2722 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2723 snprintf(xstats_names[count].name,
2724 sizeof(xstats_names[count].name),
2725 "%s", rte_i40e_hw_port_strings[i].name);
2729 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2730 for (prio = 0; prio < 8; prio++) {
2731 snprintf(xstats_names[count].name,
2732 sizeof(xstats_names[count].name),
2733 "rx_priority%u_%s", prio,
2734 rte_i40e_rxq_prio_strings[i].name);
2739 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2740 for (prio = 0; prio < 8; prio++) {
2741 snprintf(xstats_names[count].name,
2742 sizeof(xstats_names[count].name),
2743 "tx_priority%u_%s", prio,
2744 rte_i40e_txq_prio_strings[i].name);
2752 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2755 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2757 unsigned i, count, prio;
2758 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2760 count = i40e_xstats_calc_num();
2764 i40e_read_stats_registers(pf, hw);
2771 /* Get stats from i40e_eth_stats struct */
2772 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2773 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2774 rte_i40e_stats_strings[i].offset);
2775 xstats[count].id = count;
2779 /* Get individiual stats from i40e_hw_port struct */
2780 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2781 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2782 rte_i40e_hw_port_strings[i].offset);
2783 xstats[count].id = count;
2787 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2788 for (prio = 0; prio < 8; prio++) {
2789 xstats[count].value =
2790 *(uint64_t *)(((char *)hw_stats) +
2791 rte_i40e_rxq_prio_strings[i].offset +
2792 (sizeof(uint64_t) * prio));
2793 xstats[count].id = count;
2798 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2799 for (prio = 0; prio < 8; prio++) {
2800 xstats[count].value =
2801 *(uint64_t *)(((char *)hw_stats) +
2802 rte_i40e_txq_prio_strings[i].offset +
2803 (sizeof(uint64_t) * prio));
2804 xstats[count].id = count;
2813 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2814 __rte_unused uint16_t queue_id,
2815 __rte_unused uint8_t stat_idx,
2816 __rte_unused uint8_t is_rx)
2818 PMD_INIT_FUNC_TRACE();
2824 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2826 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832 full_ver = hw->nvm.oem_ver;
2833 ver = (u8)(full_ver >> 24);
2834 build = (u16)((full_ver >> 8) & 0xffff);
2835 patch = (u8)(full_ver & 0xff);
2837 ret = snprintf(fw_version, fw_size,
2838 "%d.%d%d 0x%08x %d.%d.%d",
2839 ((hw->nvm.version >> 12) & 0xf),
2840 ((hw->nvm.version >> 4) & 0xff),
2841 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2844 ret += 1; /* add the size of '\0' */
2845 if (fw_size < (u32)ret)
2852 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2854 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2855 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2856 struct i40e_vsi *vsi = pf->main_vsi;
2857 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2859 dev_info->pci_dev = pci_dev;
2860 dev_info->max_rx_queues = vsi->nb_qps;
2861 dev_info->max_tx_queues = vsi->nb_qps;
2862 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2863 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2864 dev_info->max_mac_addrs = vsi->max_macaddrs;
2865 dev_info->max_vfs = pci_dev->max_vfs;
2866 dev_info->rx_offload_capa =
2867 DEV_RX_OFFLOAD_VLAN_STRIP |
2868 DEV_RX_OFFLOAD_QINQ_STRIP |
2869 DEV_RX_OFFLOAD_IPV4_CKSUM |
2870 DEV_RX_OFFLOAD_UDP_CKSUM |
2871 DEV_RX_OFFLOAD_TCP_CKSUM;
2872 dev_info->tx_offload_capa =
2873 DEV_TX_OFFLOAD_VLAN_INSERT |
2874 DEV_TX_OFFLOAD_QINQ_INSERT |
2875 DEV_TX_OFFLOAD_IPV4_CKSUM |
2876 DEV_TX_OFFLOAD_UDP_CKSUM |
2877 DEV_TX_OFFLOAD_TCP_CKSUM |
2878 DEV_TX_OFFLOAD_SCTP_CKSUM |
2879 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2880 DEV_TX_OFFLOAD_TCP_TSO |
2881 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2882 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2883 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2884 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2885 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2887 dev_info->reta_size = pf->hash_lut_size;
2888 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2890 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2892 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2893 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2894 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2896 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2900 dev_info->default_txconf = (struct rte_eth_txconf) {
2902 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2903 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2904 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2906 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2907 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2908 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2909 ETH_TXQ_FLAGS_NOOFFLOADS,
2912 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2913 .nb_max = I40E_MAX_RING_DESC,
2914 .nb_min = I40E_MIN_RING_DESC,
2915 .nb_align = I40E_ALIGN_RING_DESC,
2918 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2919 .nb_max = I40E_MAX_RING_DESC,
2920 .nb_min = I40E_MIN_RING_DESC,
2921 .nb_align = I40E_ALIGN_RING_DESC,
2922 .nb_seg_max = I40E_TX_MAX_SEG,
2923 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2926 if (pf->flags & I40E_FLAG_VMDQ) {
2927 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2928 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2929 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2930 pf->max_nb_vmdq_vsi;
2931 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2932 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2933 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2936 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2938 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2939 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2941 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2944 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2948 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2950 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2951 struct i40e_vsi *vsi = pf->main_vsi;
2952 PMD_INIT_FUNC_TRACE();
2955 return i40e_vsi_add_vlan(vsi, vlan_id);
2957 return i40e_vsi_delete_vlan(vsi, vlan_id);
2961 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2962 enum rte_vlan_type vlan_type,
2965 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2966 uint64_t reg_r = 0, reg_w = 0;
2967 uint16_t reg_id = 0;
2969 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2971 switch (vlan_type) {
2972 case ETH_VLAN_TYPE_OUTER:
2978 case ETH_VLAN_TYPE_INNER:
2984 "Unsupported vlan type in single vlan.\n");
2990 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2993 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2995 if (ret != I40E_SUCCESS) {
2996 PMD_DRV_LOG(ERR, "Fail to debug read from "
2997 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
3001 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
3002 "0x%08"PRIx64"", reg_id, reg_r);
3004 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3005 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3006 if (reg_r == reg_w) {
3008 PMD_DRV_LOG(DEBUG, "No need to write");
3012 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3014 if (ret != I40E_SUCCESS) {
3016 PMD_DRV_LOG(ERR, "Fail to debug write to "
3017 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
3020 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3021 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3027 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3029 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3030 struct i40e_vsi *vsi = pf->main_vsi;
3032 if (mask & ETH_VLAN_FILTER_MASK) {
3033 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3034 i40e_vsi_config_vlan_filter(vsi, TRUE);
3036 i40e_vsi_config_vlan_filter(vsi, FALSE);
3039 if (mask & ETH_VLAN_STRIP_MASK) {
3040 /* Enable or disable VLAN stripping */
3041 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3042 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3044 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3047 if (mask & ETH_VLAN_EXTEND_MASK) {
3048 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3049 i40e_vsi_config_double_vlan(vsi, TRUE);
3050 /* Set global registers with default ether type value */
3051 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3053 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3057 i40e_vsi_config_double_vlan(vsi, FALSE);
3062 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3063 __rte_unused uint16_t queue,
3064 __rte_unused int on)
3066 PMD_INIT_FUNC_TRACE();
3070 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3072 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3073 struct i40e_vsi *vsi = pf->main_vsi;
3074 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3075 struct i40e_vsi_vlan_pvid_info info;
3077 memset(&info, 0, sizeof(info));
3080 info.config.pvid = pvid;
3082 info.config.reject.tagged =
3083 data->dev_conf.txmode.hw_vlan_reject_tagged;
3084 info.config.reject.untagged =
3085 data->dev_conf.txmode.hw_vlan_reject_untagged;
3088 return i40e_vsi_vlan_pvid_set(vsi, &info);
3092 i40e_dev_led_on(struct rte_eth_dev *dev)
3094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3095 uint32_t mode = i40e_led_get(hw);
3098 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3104 i40e_dev_led_off(struct rte_eth_dev *dev)
3106 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3107 uint32_t mode = i40e_led_get(hw);
3110 i40e_led_set(hw, 0, false);
3116 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3118 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3121 fc_conf->pause_time = pf->fc_conf.pause_time;
3122 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3123 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3125 /* Return current mode according to actual setting*/
3126 switch (hw->fc.current_mode) {
3128 fc_conf->mode = RTE_FC_FULL;
3130 case I40E_FC_TX_PAUSE:
3131 fc_conf->mode = RTE_FC_TX_PAUSE;
3133 case I40E_FC_RX_PAUSE:
3134 fc_conf->mode = RTE_FC_RX_PAUSE;
3138 fc_conf->mode = RTE_FC_NONE;
3145 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3147 uint32_t mflcn_reg, fctrl_reg, reg;
3148 uint32_t max_high_water;
3149 uint8_t i, aq_failure;
3153 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3154 [RTE_FC_NONE] = I40E_FC_NONE,
3155 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3156 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3157 [RTE_FC_FULL] = I40E_FC_FULL
3160 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3162 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3163 if ((fc_conf->high_water > max_high_water) ||
3164 (fc_conf->high_water < fc_conf->low_water)) {
3165 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
3166 "High_water must <= %d.", max_high_water);
3170 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3171 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3172 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3174 pf->fc_conf.pause_time = fc_conf->pause_time;
3175 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3176 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3178 PMD_INIT_FUNC_TRACE();
3180 /* All the link flow control related enable/disable register
3181 * configuration is handle by the F/W
3183 err = i40e_set_fc(hw, &aq_failure, true);
3187 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3188 /* Configure flow control refresh threshold,
3189 * the value for stat_tx_pause_refresh_timer[8]
3190 * is used for global pause operation.
3194 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3195 pf->fc_conf.pause_time);
3197 /* configure the timer value included in transmitted pause
3199 * the value for stat_tx_pause_quanta[8] is used for global
3202 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3203 pf->fc_conf.pause_time);
3205 fctrl_reg = I40E_READ_REG(hw,
3206 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3208 if (fc_conf->mac_ctrl_frame_fwd != 0)
3209 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3211 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3213 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3216 /* Configure pause time (2 TCs per register) */
3217 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3218 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3219 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3221 /* Configure flow control refresh threshold value */
3222 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3223 pf->fc_conf.pause_time / 2);
3225 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3227 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3228 *depending on configuration
3230 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3231 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3232 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3234 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3235 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3238 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3241 /* config the water marker both based on the packets and bytes */
3242 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3243 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3244 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3245 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3246 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3247 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3248 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3249 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3251 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3252 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3255 I40E_WRITE_FLUSH(hw);
3261 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3262 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3264 PMD_INIT_FUNC_TRACE();
3269 /* Add a MAC address, and update filters */
3271 i40e_macaddr_add(struct rte_eth_dev *dev,
3272 struct ether_addr *mac_addr,
3273 __rte_unused uint32_t index,
3276 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3277 struct i40e_mac_filter_info mac_filter;
3278 struct i40e_vsi *vsi;
3281 /* If VMDQ not enabled or configured, return */
3282 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3283 !pf->nb_cfg_vmdq_vsi)) {
3284 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3285 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3290 if (pool > pf->nb_cfg_vmdq_vsi) {
3291 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3292 pool, pf->nb_cfg_vmdq_vsi);
3296 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3297 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3298 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3300 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3305 vsi = pf->vmdq[pool - 1].vsi;
3307 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3308 if (ret != I40E_SUCCESS) {
3309 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3314 /* Remove a MAC address, and update filters */
3316 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3318 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3319 struct i40e_vsi *vsi;
3320 struct rte_eth_dev_data *data = dev->data;
3321 struct ether_addr *macaddr;
3326 macaddr = &(data->mac_addrs[index]);
3328 pool_sel = dev->data->mac_pool_sel[index];
3330 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3331 if (pool_sel & (1ULL << i)) {
3335 /* No VMDQ pool enabled or configured */
3336 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3337 (i > pf->nb_cfg_vmdq_vsi)) {
3338 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3342 vsi = pf->vmdq[i - 1].vsi;
3344 ret = i40e_vsi_delete_mac(vsi, macaddr);
3347 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3354 /* Set perfect match or hash match of MAC and VLAN for a VF */
3356 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3357 struct rte_eth_mac_filter *filter,
3361 struct i40e_mac_filter_info mac_filter;
3362 struct ether_addr old_mac;
3363 struct ether_addr *new_mac;
3364 struct i40e_pf_vf *vf = NULL;
3369 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3372 hw = I40E_PF_TO_HW(pf);
3374 if (filter == NULL) {
3375 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3379 new_mac = &filter->mac_addr;
3381 if (is_zero_ether_addr(new_mac)) {
3382 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3386 vf_id = filter->dst_id;
3388 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3389 PMD_DRV_LOG(ERR, "Invalid argument.");
3392 vf = &pf->vfs[vf_id];
3394 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3395 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3400 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3401 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3403 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3406 mac_filter.filter_type = filter->filter_type;
3407 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3408 if (ret != I40E_SUCCESS) {
3409 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3412 ether_addr_copy(new_mac, &pf->dev_addr);
3414 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3416 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3417 if (ret != I40E_SUCCESS) {
3418 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3422 /* Clear device address as it has been removed */
3423 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3424 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3430 /* MAC filter handle */
3432 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3435 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3436 struct rte_eth_mac_filter *filter;
3437 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3438 int ret = I40E_NOT_SUPPORTED;
3440 filter = (struct rte_eth_mac_filter *)(arg);
3442 switch (filter_op) {
3443 case RTE_ETH_FILTER_NOP:
3446 case RTE_ETH_FILTER_ADD:
3447 i40e_pf_disable_irq0(hw);
3449 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3450 i40e_pf_enable_irq0(hw);
3452 case RTE_ETH_FILTER_DELETE:
3453 i40e_pf_disable_irq0(hw);
3455 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3456 i40e_pf_enable_irq0(hw);
3459 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3460 ret = I40E_ERR_PARAM;
3468 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3470 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3471 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3477 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3478 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3481 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3485 uint32_t *lut_dw = (uint32_t *)lut;
3486 uint16_t i, lut_size_dw = lut_size / 4;
3488 for (i = 0; i < lut_size_dw; i++)
3489 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3496 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3505 pf = I40E_VSI_TO_PF(vsi);
3506 hw = I40E_VSI_TO_HW(vsi);
3508 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3509 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3512 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3516 uint32_t *lut_dw = (uint32_t *)lut;
3517 uint16_t i, lut_size_dw = lut_size / 4;
3519 for (i = 0; i < lut_size_dw; i++)
3520 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3521 I40E_WRITE_FLUSH(hw);
3528 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3529 struct rte_eth_rss_reta_entry64 *reta_conf,
3532 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3533 uint16_t i, lut_size = pf->hash_lut_size;
3534 uint16_t idx, shift;
3538 if (reta_size != lut_size ||
3539 reta_size > ETH_RSS_RETA_SIZE_512) {
3540 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3541 "(%d) doesn't match the number hardware can supported "
3542 "(%d)\n", reta_size, lut_size);
3546 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3548 PMD_DRV_LOG(ERR, "No memory can be allocated");
3551 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3554 for (i = 0; i < reta_size; i++) {
3555 idx = i / RTE_RETA_GROUP_SIZE;
3556 shift = i % RTE_RETA_GROUP_SIZE;
3557 if (reta_conf[idx].mask & (1ULL << shift))
3558 lut[i] = reta_conf[idx].reta[shift];
3560 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3569 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3570 struct rte_eth_rss_reta_entry64 *reta_conf,
3573 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3574 uint16_t i, lut_size = pf->hash_lut_size;
3575 uint16_t idx, shift;
3579 if (reta_size != lut_size ||
3580 reta_size > ETH_RSS_RETA_SIZE_512) {
3581 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3582 "(%d) doesn't match the number hardware can supported "
3583 "(%d)\n", reta_size, lut_size);
3587 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3589 PMD_DRV_LOG(ERR, "No memory can be allocated");
3593 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3596 for (i = 0; i < reta_size; i++) {
3597 idx = i / RTE_RETA_GROUP_SIZE;
3598 shift = i % RTE_RETA_GROUP_SIZE;
3599 if (reta_conf[idx].mask & (1ULL << shift))
3600 reta_conf[idx].reta[shift] = lut[i];
3610 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3611 * @hw: pointer to the HW structure
3612 * @mem: pointer to mem struct to fill out
3613 * @size: size of memory requested
3614 * @alignment: what to align the allocation to
3616 enum i40e_status_code
3617 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3618 struct i40e_dma_mem *mem,
3622 const struct rte_memzone *mz = NULL;
3623 char z_name[RTE_MEMZONE_NAMESIZE];
3626 return I40E_ERR_PARAM;
3628 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3629 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3630 alignment, RTE_PGSIZE_2M);
3632 return I40E_ERR_NO_MEMORY;
3636 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3637 mem->zone = (const void *)mz;
3638 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3639 "%"PRIu64, mz->name, mem->pa);
3641 return I40E_SUCCESS;
3645 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3646 * @hw: pointer to the HW structure
3647 * @mem: ptr to mem struct to free
3649 enum i40e_status_code
3650 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3651 struct i40e_dma_mem *mem)
3654 return I40E_ERR_PARAM;
3656 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3657 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3659 rte_memzone_free((const struct rte_memzone *)mem->zone);
3664 return I40E_SUCCESS;
3668 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3669 * @hw: pointer to the HW structure
3670 * @mem: pointer to mem struct to fill out
3671 * @size: size of memory requested
3673 enum i40e_status_code
3674 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3675 struct i40e_virt_mem *mem,
3679 return I40E_ERR_PARAM;
3682 mem->va = rte_zmalloc("i40e", size, 0);
3685 return I40E_SUCCESS;
3687 return I40E_ERR_NO_MEMORY;
3691 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3692 * @hw: pointer to the HW structure
3693 * @mem: pointer to mem struct to free
3695 enum i40e_status_code
3696 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3697 struct i40e_virt_mem *mem)
3700 return I40E_ERR_PARAM;
3705 return I40E_SUCCESS;
3709 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3711 rte_spinlock_init(&sp->spinlock);
3715 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3717 rte_spinlock_lock(&sp->spinlock);
3721 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3723 rte_spinlock_unlock(&sp->spinlock);
3727 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3733 * Get the hardware capabilities, which will be parsed
3734 * and saved into struct i40e_hw.
3737 i40e_get_cap(struct i40e_hw *hw)
3739 struct i40e_aqc_list_capabilities_element_resp *buf;
3740 uint16_t len, size = 0;
3743 /* Calculate a huge enough buff for saving response data temporarily */
3744 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3745 I40E_MAX_CAP_ELE_NUM;
3746 buf = rte_zmalloc("i40e", len, 0);
3748 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3749 return I40E_ERR_NO_MEMORY;
3752 /* Get, parse the capabilities and save it to hw */
3753 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3754 i40e_aqc_opc_list_func_capabilities, NULL);
3755 if (ret != I40E_SUCCESS)
3756 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3758 /* Free the temporary buffer after being used */
3765 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3767 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3768 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3769 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3770 uint16_t qp_count = 0, vsi_count = 0;
3772 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3773 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3776 /* Add the parameter init for LFC */
3777 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3778 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3779 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3781 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3782 pf->max_num_vsi = hw->func_caps.num_vsis;
3783 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3784 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3785 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3787 /* FDir queue/VSI allocation */
3788 pf->fdir_qp_offset = 0;
3789 if (hw->func_caps.fd) {
3790 pf->flags |= I40E_FLAG_FDIR;
3791 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3793 pf->fdir_nb_qps = 0;
3795 qp_count += pf->fdir_nb_qps;
3798 /* LAN queue/VSI allocation */
3799 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3800 if (!hw->func_caps.rss) {
3803 pf->flags |= I40E_FLAG_RSS;
3804 if (hw->mac.type == I40E_MAC_X722)
3805 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3806 pf->lan_nb_qps = pf->lan_nb_qp_max;
3808 qp_count += pf->lan_nb_qps;
3811 /* VF queue/VSI allocation */
3812 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3813 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3814 pf->flags |= I40E_FLAG_SRIOV;
3815 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3816 pf->vf_num = pci_dev->max_vfs;
3817 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3818 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3819 pf->vf_nb_qps * pf->vf_num);
3824 qp_count += pf->vf_nb_qps * pf->vf_num;
3825 vsi_count += pf->vf_num;
3827 /* VMDq queue/VSI allocation */
3828 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3829 pf->vmdq_nb_qps = 0;
3830 pf->max_nb_vmdq_vsi = 0;
3831 if (hw->func_caps.vmdq) {
3832 if (qp_count < hw->func_caps.num_tx_qp &&
3833 vsi_count < hw->func_caps.num_vsis) {
3834 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3835 qp_count) / pf->vmdq_nb_qp_max;
3837 /* Limit the maximum number of VMDq vsi to the maximum
3838 * ethdev can support
3840 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3841 hw->func_caps.num_vsis - vsi_count);
3842 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3844 if (pf->max_nb_vmdq_vsi) {
3845 pf->flags |= I40E_FLAG_VMDQ;
3846 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3847 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3848 "per VMDQ VSI, in total %u queues",
3849 pf->max_nb_vmdq_vsi,
3850 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3851 pf->max_nb_vmdq_vsi);
3853 PMD_DRV_LOG(INFO, "No enough queues left for "
3857 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3860 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3861 vsi_count += pf->max_nb_vmdq_vsi;
3863 if (hw->func_caps.dcb)
3864 pf->flags |= I40E_FLAG_DCB;
3866 if (qp_count > hw->func_caps.num_tx_qp) {
3867 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3868 "the hardware maximum %u", qp_count,
3869 hw->func_caps.num_tx_qp);
3872 if (vsi_count > hw->func_caps.num_vsis) {
3873 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3874 "the hardware maximum %u", vsi_count,
3875 hw->func_caps.num_vsis);
3883 i40e_pf_get_switch_config(struct i40e_pf *pf)
3885 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3886 struct i40e_aqc_get_switch_config_resp *switch_config;
3887 struct i40e_aqc_switch_config_element_resp *element;
3888 uint16_t start_seid = 0, num_reported;
3891 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3892 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3893 if (!switch_config) {
3894 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3898 /* Get the switch configurations */
3899 ret = i40e_aq_get_switch_config(hw, switch_config,
3900 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3901 if (ret != I40E_SUCCESS) {
3902 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3905 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3906 if (num_reported != 1) { /* The number should be 1 */
3907 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3911 /* Parse the switch configuration elements */
3912 element = &(switch_config->element[0]);
3913 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3914 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3915 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3917 PMD_DRV_LOG(INFO, "Unknown element type");
3920 rte_free(switch_config);
3926 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3929 struct pool_entry *entry;
3931 if (pool == NULL || num == 0)
3934 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3935 if (entry == NULL) {
3936 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3940 /* queue heap initialize */
3941 pool->num_free = num;
3942 pool->num_alloc = 0;
3944 LIST_INIT(&pool->alloc_list);
3945 LIST_INIT(&pool->free_list);
3947 /* Initialize element */
3951 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3956 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3958 struct pool_entry *entry, *next_entry;
3963 for (entry = LIST_FIRST(&pool->alloc_list);
3964 entry && (next_entry = LIST_NEXT(entry, next), 1);
3965 entry = next_entry) {
3966 LIST_REMOVE(entry, next);
3970 for (entry = LIST_FIRST(&pool->free_list);
3971 entry && (next_entry = LIST_NEXT(entry, next), 1);
3972 entry = next_entry) {
3973 LIST_REMOVE(entry, next);
3978 pool->num_alloc = 0;
3980 LIST_INIT(&pool->alloc_list);
3981 LIST_INIT(&pool->free_list);
3985 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3988 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3989 uint32_t pool_offset;
3993 PMD_DRV_LOG(ERR, "Invalid parameter");
3997 pool_offset = base - pool->base;
3998 /* Lookup in alloc list */
3999 LIST_FOREACH(entry, &pool->alloc_list, next) {
4000 if (entry->base == pool_offset) {
4001 valid_entry = entry;
4002 LIST_REMOVE(entry, next);
4007 /* Not find, return */
4008 if (valid_entry == NULL) {
4009 PMD_DRV_LOG(ERR, "Failed to find entry");
4014 * Found it, move it to free list and try to merge.
4015 * In order to make merge easier, always sort it by qbase.
4016 * Find adjacent prev and last entries.
4019 LIST_FOREACH(entry, &pool->free_list, next) {
4020 if (entry->base > valid_entry->base) {
4028 /* Try to merge with next one*/
4030 /* Merge with next one */
4031 if (valid_entry->base + valid_entry->len == next->base) {
4032 next->base = valid_entry->base;
4033 next->len += valid_entry->len;
4034 rte_free(valid_entry);
4041 /* Merge with previous one */
4042 if (prev->base + prev->len == valid_entry->base) {
4043 prev->len += valid_entry->len;
4044 /* If it merge with next one, remove next node */
4046 LIST_REMOVE(valid_entry, next);
4047 rte_free(valid_entry);
4049 rte_free(valid_entry);
4055 /* Not find any entry to merge, insert */
4058 LIST_INSERT_AFTER(prev, valid_entry, next);
4059 else if (next != NULL)
4060 LIST_INSERT_BEFORE(next, valid_entry, next);
4061 else /* It's empty list, insert to head */
4062 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4065 pool->num_free += valid_entry->len;
4066 pool->num_alloc -= valid_entry->len;
4072 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4075 struct pool_entry *entry, *valid_entry;
4077 if (pool == NULL || num == 0) {
4078 PMD_DRV_LOG(ERR, "Invalid parameter");
4082 if (pool->num_free < num) {
4083 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4084 num, pool->num_free);
4089 /* Lookup in free list and find most fit one */
4090 LIST_FOREACH(entry, &pool->free_list, next) {
4091 if (entry->len >= num) {
4093 if (entry->len == num) {
4094 valid_entry = entry;
4097 if (valid_entry == NULL || valid_entry->len > entry->len)
4098 valid_entry = entry;
4102 /* Not find one to satisfy the request, return */
4103 if (valid_entry == NULL) {
4104 PMD_DRV_LOG(ERR, "No valid entry found");
4108 * The entry have equal queue number as requested,
4109 * remove it from alloc_list.
4111 if (valid_entry->len == num) {
4112 LIST_REMOVE(valid_entry, next);
4115 * The entry have more numbers than requested,
4116 * create a new entry for alloc_list and minus its
4117 * queue base and number in free_list.
4119 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4120 if (entry == NULL) {
4121 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
4125 entry->base = valid_entry->base;
4127 valid_entry->base += num;
4128 valid_entry->len -= num;
4129 valid_entry = entry;
4132 /* Insert it into alloc list, not sorted */
4133 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4135 pool->num_free -= valid_entry->len;
4136 pool->num_alloc += valid_entry->len;
4138 return valid_entry->base + pool->base;
4142 * bitmap_is_subset - Check whether src2 is subset of src1
4145 bitmap_is_subset(uint8_t src1, uint8_t src2)
4147 return !((src1 ^ src2) & src2);
4150 static enum i40e_status_code
4151 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4153 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4155 /* If DCB is not supported, only default TC is supported */
4156 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4157 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4158 return I40E_NOT_SUPPORTED;
4161 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4162 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
4163 "HW support 0x%x", hw->func_caps.enabled_tcmap,
4165 return I40E_NOT_SUPPORTED;
4167 return I40E_SUCCESS;
4171 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4172 struct i40e_vsi_vlan_pvid_info *info)
4175 struct i40e_vsi_context ctxt;
4176 uint8_t vlan_flags = 0;
4179 if (vsi == NULL || info == NULL) {
4180 PMD_DRV_LOG(ERR, "invalid parameters");
4181 return I40E_ERR_PARAM;
4185 vsi->info.pvid = info->config.pvid;
4187 * If insert pvid is enabled, only tagged pkts are
4188 * allowed to be sent out.
4190 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4191 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4194 if (info->config.reject.tagged == 0)
4195 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4197 if (info->config.reject.untagged == 0)
4198 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4200 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4201 I40E_AQ_VSI_PVLAN_MODE_MASK);
4202 vsi->info.port_vlan_flags |= vlan_flags;
4203 vsi->info.valid_sections =
4204 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4205 memset(&ctxt, 0, sizeof(ctxt));
4206 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4207 ctxt.seid = vsi->seid;
4209 hw = I40E_VSI_TO_HW(vsi);
4210 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4211 if (ret != I40E_SUCCESS)
4212 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4218 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4220 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4222 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4224 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4225 if (ret != I40E_SUCCESS)
4229 PMD_DRV_LOG(ERR, "seid not valid");
4233 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4234 tc_bw_data.tc_valid_bits = enabled_tcmap;
4235 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4236 tc_bw_data.tc_bw_credits[i] =
4237 (enabled_tcmap & (1 << i)) ? 1 : 0;
4239 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4240 if (ret != I40E_SUCCESS) {
4241 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4245 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4246 sizeof(vsi->info.qs_handle));
4247 return I40E_SUCCESS;
4250 static enum i40e_status_code
4251 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4252 struct i40e_aqc_vsi_properties_data *info,
4253 uint8_t enabled_tcmap)
4255 enum i40e_status_code ret;
4256 int i, total_tc = 0;
4257 uint16_t qpnum_per_tc, bsf, qp_idx;
4259 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4260 if (ret != I40E_SUCCESS)
4263 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4264 if (enabled_tcmap & (1 << i))
4266 vsi->enabled_tc = enabled_tcmap;
4268 /* Number of queues per enabled TC */
4269 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4270 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4271 bsf = rte_bsf32(qpnum_per_tc);
4273 /* Adjust the queue number to actual queues that can be applied */
4274 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4275 vsi->nb_qps = qpnum_per_tc * total_tc;
4278 * Configure TC and queue mapping parameters, for enabled TC,
4279 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4280 * default queue will serve it.
4283 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4284 if (vsi->enabled_tc & (1 << i)) {
4285 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4286 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4287 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4288 qp_idx += qpnum_per_tc;
4290 info->tc_mapping[i] = 0;
4293 /* Associate queue number with VSI */
4294 if (vsi->type == I40E_VSI_SRIOV) {
4295 info->mapping_flags |=
4296 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4297 for (i = 0; i < vsi->nb_qps; i++)
4298 info->queue_mapping[i] =
4299 rte_cpu_to_le_16(vsi->base_queue + i);
4301 info->mapping_flags |=
4302 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4303 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4305 info->valid_sections |=
4306 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4308 return I40E_SUCCESS;
4312 i40e_veb_release(struct i40e_veb *veb)
4314 struct i40e_vsi *vsi;
4320 if (!TAILQ_EMPTY(&veb->head)) {
4321 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4324 /* associate_vsi field is NULL for floating VEB */
4325 if (veb->associate_vsi != NULL) {
4326 vsi = veb->associate_vsi;
4327 hw = I40E_VSI_TO_HW(vsi);
4329 vsi->uplink_seid = veb->uplink_seid;
4332 veb->associate_pf->main_vsi->floating_veb = NULL;
4333 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4336 i40e_aq_delete_element(hw, veb->seid, NULL);
4338 return I40E_SUCCESS;
4342 static struct i40e_veb *
4343 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4345 struct i40e_veb *veb;
4351 "veb setup failed, associated PF shouldn't null");
4354 hw = I40E_PF_TO_HW(pf);
4356 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4358 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4362 veb->associate_vsi = vsi;
4363 veb->associate_pf = pf;
4364 TAILQ_INIT(&veb->head);
4365 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4367 /* create floating veb if vsi is NULL */
4369 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4370 I40E_DEFAULT_TCMAP, false,
4371 &veb->seid, false, NULL);
4373 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4374 true, &veb->seid, false, NULL);
4377 if (ret != I40E_SUCCESS) {
4378 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4379 hw->aq.asq_last_status);
4383 /* get statistics index */
4384 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4385 &veb->stats_idx, NULL, NULL, NULL);
4386 if (ret != I40E_SUCCESS) {
4387 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4388 hw->aq.asq_last_status);
4391 /* Get VEB bandwidth, to be implemented */
4392 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4394 vsi->uplink_seid = veb->seid;
4403 i40e_vsi_release(struct i40e_vsi *vsi)
4407 struct i40e_vsi_list *vsi_list;
4410 struct i40e_mac_filter *f;
4411 uint16_t user_param;
4414 return I40E_SUCCESS;
4416 user_param = vsi->user_param;
4418 pf = I40E_VSI_TO_PF(vsi);
4419 hw = I40E_VSI_TO_HW(vsi);
4421 /* VSI has child to attach, release child first */
4423 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4424 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4427 i40e_veb_release(vsi->veb);
4430 if (vsi->floating_veb) {
4431 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4432 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4437 /* Remove all macvlan filters of the VSI */
4438 i40e_vsi_remove_all_macvlan_filter(vsi);
4439 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4442 if (vsi->type != I40E_VSI_MAIN &&
4443 ((vsi->type != I40E_VSI_SRIOV) ||
4444 !pf->floating_veb_list[user_param])) {
4445 /* Remove vsi from parent's sibling list */
4446 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4447 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4448 return I40E_ERR_PARAM;
4450 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4451 &vsi->sib_vsi_list, list);
4453 /* Remove all switch element of the VSI */
4454 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4455 if (ret != I40E_SUCCESS)
4456 PMD_DRV_LOG(ERR, "Failed to delete element");
4459 if ((vsi->type == I40E_VSI_SRIOV) &&
4460 pf->floating_veb_list[user_param]) {
4461 /* Remove vsi from parent's sibling list */
4462 if (vsi->parent_vsi == NULL ||
4463 vsi->parent_vsi->floating_veb == NULL) {
4464 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4465 return I40E_ERR_PARAM;
4467 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4468 &vsi->sib_vsi_list, list);
4470 /* Remove all switch element of the VSI */
4471 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4472 if (ret != I40E_SUCCESS)
4473 PMD_DRV_LOG(ERR, "Failed to delete element");
4476 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4478 if (vsi->type != I40E_VSI_SRIOV)
4479 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4482 return I40E_SUCCESS;
4486 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4488 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4489 struct i40e_aqc_remove_macvlan_element_data def_filter;
4490 struct i40e_mac_filter_info filter;
4493 if (vsi->type != I40E_VSI_MAIN)
4494 return I40E_ERR_CONFIG;
4495 memset(&def_filter, 0, sizeof(def_filter));
4496 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4498 def_filter.vlan_tag = 0;
4499 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4500 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4501 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4502 if (ret != I40E_SUCCESS) {
4503 struct i40e_mac_filter *f;
4504 struct ether_addr *mac;
4506 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4508 /* It needs to add the permanent mac into mac list */
4509 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4511 PMD_DRV_LOG(ERR, "failed to allocate memory");
4512 return I40E_ERR_NO_MEMORY;
4514 mac = &f->mac_info.mac_addr;
4515 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4517 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4518 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4523 (void)rte_memcpy(&filter.mac_addr,
4524 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4525 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4526 return i40e_vsi_add_mac(vsi, &filter);
4530 * i40e_vsi_get_bw_config - Query VSI BW Information
4531 * @vsi: the VSI to be queried
4533 * Returns 0 on success, negative value on failure
4535 static enum i40e_status_code
4536 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4538 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4539 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4540 struct i40e_hw *hw = &vsi->adapter->hw;
4545 memset(&bw_config, 0, sizeof(bw_config));
4546 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4547 if (ret != I40E_SUCCESS) {
4548 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4549 hw->aq.asq_last_status);
4553 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4554 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4555 &ets_sla_config, NULL);
4556 if (ret != I40E_SUCCESS) {
4557 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4558 "configuration %u", hw->aq.asq_last_status);
4562 /* store and print out BW info */
4563 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4564 vsi->bw_info.bw_max = bw_config.max_bw;
4565 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4566 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4567 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4568 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4570 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4571 vsi->bw_info.bw_ets_share_credits[i] =
4572 ets_sla_config.share_credits[i];
4573 vsi->bw_info.bw_ets_credits[i] =
4574 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4575 /* 4 bits per TC, 4th bit is reserved */
4576 vsi->bw_info.bw_ets_max[i] =
4577 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4578 RTE_LEN2MASK(3, uint8_t));
4579 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4580 vsi->bw_info.bw_ets_share_credits[i]);
4581 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4582 vsi->bw_info.bw_ets_credits[i]);
4583 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4584 vsi->bw_info.bw_ets_max[i]);
4587 return I40E_SUCCESS;
4590 /* i40e_enable_pf_lb
4591 * @pf: pointer to the pf structure
4593 * allow loopback on pf
4596 i40e_enable_pf_lb(struct i40e_pf *pf)
4598 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4599 struct i40e_vsi_context ctxt;
4602 /* Use the FW API if FW >= v5.0 */
4603 if (hw->aq.fw_maj_ver < 5) {
4604 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4608 memset(&ctxt, 0, sizeof(ctxt));
4609 ctxt.seid = pf->main_vsi_seid;
4610 ctxt.pf_num = hw->pf_id;
4611 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4613 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4614 ret, hw->aq.asq_last_status);
4617 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4618 ctxt.info.valid_sections =
4619 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4620 ctxt.info.switch_id |=
4621 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4623 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4625 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4626 hw->aq.asq_last_status);
4631 i40e_vsi_setup(struct i40e_pf *pf,
4632 enum i40e_vsi_type type,
4633 struct i40e_vsi *uplink_vsi,
4634 uint16_t user_param)
4636 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4637 struct i40e_vsi *vsi;
4638 struct i40e_mac_filter_info filter;
4640 struct i40e_vsi_context ctxt;
4641 struct ether_addr broadcast =
4642 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4644 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4645 uplink_vsi == NULL) {
4646 PMD_DRV_LOG(ERR, "VSI setup failed, "
4647 "VSI link shouldn't be NULL");
4651 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4652 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4653 "uplink VSI should be NULL");
4658 * 1.type is not MAIN and uplink vsi is not NULL
4659 * If uplink vsi didn't setup VEB, create one first under veb field
4660 * 2.type is SRIOV and the uplink is NULL
4661 * If floating VEB is NULL, create one veb under floating veb field
4664 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4665 uplink_vsi->veb == NULL) {
4666 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4668 if (uplink_vsi->veb == NULL) {
4669 PMD_DRV_LOG(ERR, "VEB setup failed");
4672 /* set ALLOWLOOPBACk on pf, when veb is created */
4673 i40e_enable_pf_lb(pf);
4676 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4677 pf->main_vsi->floating_veb == NULL) {
4678 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4680 if (pf->main_vsi->floating_veb == NULL) {
4681 PMD_DRV_LOG(ERR, "VEB setup failed");
4686 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4688 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4691 TAILQ_INIT(&vsi->mac_list);
4693 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4694 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4695 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4696 vsi->user_param = user_param;
4697 /* Allocate queues */
4698 switch (vsi->type) {
4699 case I40E_VSI_MAIN :
4700 vsi->nb_qps = pf->lan_nb_qps;
4702 case I40E_VSI_SRIOV :
4703 vsi->nb_qps = pf->vf_nb_qps;
4705 case I40E_VSI_VMDQ2:
4706 vsi->nb_qps = pf->vmdq_nb_qps;
4709 vsi->nb_qps = pf->fdir_nb_qps;
4715 * The filter status descriptor is reported in rx queue 0,
4716 * while the tx queue for fdir filter programming has no
4717 * such constraints, can be non-zero queues.
4718 * To simplify it, choose FDIR vsi use queue 0 pair.
4719 * To make sure it will use queue 0 pair, queue allocation
4720 * need be done before this function is called
4722 if (type != I40E_VSI_FDIR) {
4723 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4725 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4729 vsi->base_queue = ret;
4731 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4733 /* VF has MSIX interrupt in VF range, don't allocate here */
4734 if (type == I40E_VSI_MAIN) {
4735 ret = i40e_res_pool_alloc(&pf->msix_pool,
4736 RTE_MIN(vsi->nb_qps,
4737 RTE_MAX_RXTX_INTR_VEC_ID));
4739 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4741 goto fail_queue_alloc;
4743 vsi->msix_intr = ret;
4744 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4745 } else if (type != I40E_VSI_SRIOV) {
4746 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4748 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4749 goto fail_queue_alloc;
4751 vsi->msix_intr = ret;
4759 if (type == I40E_VSI_MAIN) {
4760 /* For main VSI, no need to add since it's default one */
4761 vsi->uplink_seid = pf->mac_seid;
4762 vsi->seid = pf->main_vsi_seid;
4763 /* Bind queues with specific MSIX interrupt */
4765 * Needs 2 interrupt at least, one for misc cause which will
4766 * enabled from OS side, Another for queues binding the
4767 * interrupt from device side only.
4770 /* Get default VSI parameters from hardware */
4771 memset(&ctxt, 0, sizeof(ctxt));
4772 ctxt.seid = vsi->seid;
4773 ctxt.pf_num = hw->pf_id;
4774 ctxt.uplink_seid = vsi->uplink_seid;
4776 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4777 if (ret != I40E_SUCCESS) {
4778 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4779 goto fail_msix_alloc;
4781 (void)rte_memcpy(&vsi->info, &ctxt.info,
4782 sizeof(struct i40e_aqc_vsi_properties_data));
4783 vsi->vsi_id = ctxt.vsi_number;
4784 vsi->info.valid_sections = 0;
4786 /* Configure tc, enabled TC0 only */
4787 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4789 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4790 goto fail_msix_alloc;
4793 /* TC, queue mapping */
4794 memset(&ctxt, 0, sizeof(ctxt));
4795 vsi->info.valid_sections |=
4796 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4797 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4798 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4799 (void)rte_memcpy(&ctxt.info, &vsi->info,
4800 sizeof(struct i40e_aqc_vsi_properties_data));
4801 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4802 I40E_DEFAULT_TCMAP);
4803 if (ret != I40E_SUCCESS) {
4804 PMD_DRV_LOG(ERR, "Failed to configure "
4805 "TC queue mapping");
4806 goto fail_msix_alloc;
4808 ctxt.seid = vsi->seid;
4809 ctxt.pf_num = hw->pf_id;
4810 ctxt.uplink_seid = vsi->uplink_seid;
4813 /* Update VSI parameters */
4814 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4815 if (ret != I40E_SUCCESS) {
4816 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4817 goto fail_msix_alloc;
4820 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4821 sizeof(vsi->info.tc_mapping));
4822 (void)rte_memcpy(&vsi->info.queue_mapping,
4823 &ctxt.info.queue_mapping,
4824 sizeof(vsi->info.queue_mapping));
4825 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4826 vsi->info.valid_sections = 0;
4828 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4832 * Updating default filter settings are necessary to prevent
4833 * reception of tagged packets.
4834 * Some old firmware configurations load a default macvlan
4835 * filter which accepts both tagged and untagged packets.
4836 * The updating is to use a normal filter instead if needed.
4837 * For NVM 4.2.2 or after, the updating is not needed anymore.
4838 * The firmware with correct configurations load the default
4839 * macvlan filter which is expected and cannot be removed.
4841 i40e_update_default_filter_setting(vsi);
4842 i40e_config_qinq(hw, vsi);
4843 } else if (type == I40E_VSI_SRIOV) {
4844 memset(&ctxt, 0, sizeof(ctxt));
4846 * For other VSI, the uplink_seid equals to uplink VSI's
4847 * uplink_seid since they share same VEB
4849 if (uplink_vsi == NULL)
4850 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4852 vsi->uplink_seid = uplink_vsi->uplink_seid;
4853 ctxt.pf_num = hw->pf_id;
4854 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4855 ctxt.uplink_seid = vsi->uplink_seid;
4856 ctxt.connection_type = 0x1;
4857 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4859 /* Use the VEB configuration if FW >= v5.0 */
4860 if (hw->aq.fw_maj_ver >= 5) {
4861 /* Configure switch ID */
4862 ctxt.info.valid_sections |=
4863 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4864 ctxt.info.switch_id =
4865 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4868 /* Configure port/vlan */
4869 ctxt.info.valid_sections |=
4870 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4871 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4872 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4873 I40E_DEFAULT_TCMAP);
4874 if (ret != I40E_SUCCESS) {
4875 PMD_DRV_LOG(ERR, "Failed to configure "
4876 "TC queue mapping");
4877 goto fail_msix_alloc;
4879 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4880 ctxt.info.valid_sections |=
4881 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4883 * Since VSI is not created yet, only configure parameter,
4884 * will add vsi below.
4887 i40e_config_qinq(hw, vsi);
4888 } else if (type == I40E_VSI_VMDQ2) {
4889 memset(&ctxt, 0, sizeof(ctxt));
4891 * For other VSI, the uplink_seid equals to uplink VSI's
4892 * uplink_seid since they share same VEB
4894 vsi->uplink_seid = uplink_vsi->uplink_seid;
4895 ctxt.pf_num = hw->pf_id;
4897 ctxt.uplink_seid = vsi->uplink_seid;
4898 ctxt.connection_type = 0x1;
4899 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4901 ctxt.info.valid_sections |=
4902 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4903 /* user_param carries flag to enable loop back */
4905 ctxt.info.switch_id =
4906 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4907 ctxt.info.switch_id |=
4908 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4911 /* Configure port/vlan */
4912 ctxt.info.valid_sections |=
4913 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4914 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4915 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4916 I40E_DEFAULT_TCMAP);
4917 if (ret != I40E_SUCCESS) {
4918 PMD_DRV_LOG(ERR, "Failed to configure "
4919 "TC queue mapping");
4920 goto fail_msix_alloc;
4922 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4923 ctxt.info.valid_sections |=
4924 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4925 } else if (type == I40E_VSI_FDIR) {
4926 memset(&ctxt, 0, sizeof(ctxt));
4927 vsi->uplink_seid = uplink_vsi->uplink_seid;
4928 ctxt.pf_num = hw->pf_id;
4930 ctxt.uplink_seid = vsi->uplink_seid;
4931 ctxt.connection_type = 0x1; /* regular data port */
4932 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4933 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4934 I40E_DEFAULT_TCMAP);
4935 if (ret != I40E_SUCCESS) {
4936 PMD_DRV_LOG(ERR, "Failed to configure "
4937 "TC queue mapping.");
4938 goto fail_msix_alloc;
4940 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4941 ctxt.info.valid_sections |=
4942 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4944 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4945 goto fail_msix_alloc;
4948 if (vsi->type != I40E_VSI_MAIN) {
4949 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4950 if (ret != I40E_SUCCESS) {
4951 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4952 hw->aq.asq_last_status);
4953 goto fail_msix_alloc;
4955 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4956 vsi->info.valid_sections = 0;
4957 vsi->seid = ctxt.seid;
4958 vsi->vsi_id = ctxt.vsi_number;
4959 vsi->sib_vsi_list.vsi = vsi;
4960 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4961 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4962 &vsi->sib_vsi_list, list);
4964 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4965 &vsi->sib_vsi_list, list);
4969 /* MAC/VLAN configuration */
4970 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4971 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4973 ret = i40e_vsi_add_mac(vsi, &filter);
4974 if (ret != I40E_SUCCESS) {
4975 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4976 goto fail_msix_alloc;
4979 /* Get VSI BW information */
4980 i40e_vsi_get_bw_config(vsi);
4983 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4985 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4991 /* Configure vlan filter on or off */
4993 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4996 struct i40e_mac_filter *f;
4998 struct i40e_mac_filter_info *mac_filter;
4999 enum rte_mac_filter_type desired_filter;
5000 int ret = I40E_SUCCESS;
5003 /* Filter to match MAC and VLAN */
5004 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5006 /* Filter to match only MAC */
5007 desired_filter = RTE_MAC_PERFECT_MATCH;
5012 mac_filter = rte_zmalloc("mac_filter_info_data",
5013 num * sizeof(*mac_filter), 0);
5014 if (mac_filter == NULL) {
5015 PMD_DRV_LOG(ERR, "failed to allocate memory");
5016 return I40E_ERR_NO_MEMORY;
5021 /* Remove all existing mac */
5022 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5023 mac_filter[i] = f->mac_info;
5024 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5026 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5027 on ? "enable" : "disable");
5033 /* Override with new filter */
5034 for (i = 0; i < num; i++) {
5035 mac_filter[i].filter_type = desired_filter;
5036 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5038 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5039 on ? "enable" : "disable");
5045 rte_free(mac_filter);
5049 /* Configure vlan stripping on or off */
5051 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5053 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5054 struct i40e_vsi_context ctxt;
5056 int ret = I40E_SUCCESS;
5058 /* Check if it has been already on or off */
5059 if (vsi->info.valid_sections &
5060 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5062 if ((vsi->info.port_vlan_flags &
5063 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5064 return 0; /* already on */
5066 if ((vsi->info.port_vlan_flags &
5067 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5068 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5069 return 0; /* already off */
5074 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5076 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5077 vsi->info.valid_sections =
5078 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5079 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5080 vsi->info.port_vlan_flags |= vlan_flags;
5081 ctxt.seid = vsi->seid;
5082 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5083 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5085 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5086 on ? "enable" : "disable");
5092 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5094 struct rte_eth_dev_data *data = dev->data;
5098 /* Apply vlan offload setting */
5099 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5100 i40e_vlan_offload_set(dev, mask);
5102 /* Apply double-vlan setting, not implemented yet */
5104 /* Apply pvid setting */
5105 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5106 data->dev_conf.txmode.hw_vlan_insert_pvid);
5108 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5114 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5116 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5118 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5122 i40e_update_flow_control(struct i40e_hw *hw)
5124 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5125 struct i40e_link_status link_status;
5126 uint32_t rxfc = 0, txfc = 0, reg;
5130 memset(&link_status, 0, sizeof(link_status));
5131 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5132 if (ret != I40E_SUCCESS) {
5133 PMD_DRV_LOG(ERR, "Failed to get link status information");
5134 goto write_reg; /* Disable flow control */
5137 an_info = hw->phy.link_info.an_info;
5138 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5139 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5140 ret = I40E_ERR_NOT_READY;
5141 goto write_reg; /* Disable flow control */
5144 * If link auto negotiation is enabled, flow control needs to
5145 * be configured according to it
5147 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5148 case I40E_LINK_PAUSE_RXTX:
5151 hw->fc.current_mode = I40E_FC_FULL;
5153 case I40E_AQ_LINK_PAUSE_RX:
5155 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5157 case I40E_AQ_LINK_PAUSE_TX:
5159 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5162 hw->fc.current_mode = I40E_FC_NONE;
5167 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5168 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5169 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5170 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5171 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5172 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5179 i40e_pf_setup(struct i40e_pf *pf)
5181 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5182 struct i40e_filter_control_settings settings;
5183 struct i40e_vsi *vsi;
5186 /* Clear all stats counters */
5187 pf->offset_loaded = FALSE;
5188 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5189 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5191 ret = i40e_pf_get_switch_config(pf);
5192 if (ret != I40E_SUCCESS) {
5193 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5196 if (pf->flags & I40E_FLAG_FDIR) {
5197 /* make queue allocated first, let FDIR use queue pair 0*/
5198 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5199 if (ret != I40E_FDIR_QUEUE_ID) {
5200 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
5202 pf->flags &= ~I40E_FLAG_FDIR;
5205 /* main VSI setup */
5206 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5208 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5209 return I40E_ERR_NOT_READY;
5213 /* Configure filter control */
5214 memset(&settings, 0, sizeof(settings));
5215 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5216 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5217 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5218 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5220 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5221 hw->func_caps.rss_table_size);
5222 return I40E_ERR_PARAM;
5224 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5225 "size: %u\n", hw->func_caps.rss_table_size);
5226 pf->hash_lut_size = hw->func_caps.rss_table_size;
5228 /* Enable ethtype and macvlan filters */
5229 settings.enable_ethtype = TRUE;
5230 settings.enable_macvlan = TRUE;
5231 ret = i40e_set_filter_control(hw, &settings);
5233 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5236 /* Update flow control according to the auto negotiation */
5237 i40e_update_flow_control(hw);
5239 return I40E_SUCCESS;
5243 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5249 * Set or clear TX Queue Disable flags,
5250 * which is required by hardware.
5252 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5253 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5255 /* Wait until the request is finished */
5256 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5257 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5258 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5259 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5260 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5266 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5267 return I40E_SUCCESS; /* already on, skip next steps */
5269 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5270 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5272 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5273 return I40E_SUCCESS; /* already off, skip next steps */
5274 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5276 /* Write the register */
5277 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5278 /* Check the result */
5279 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5280 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5281 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5283 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5284 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5287 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5288 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5292 /* Check if it is timeout */
5293 if (j >= I40E_CHK_Q_ENA_COUNT) {
5294 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5295 (on ? "enable" : "disable"), q_idx);
5296 return I40E_ERR_TIMEOUT;
5299 return I40E_SUCCESS;
5302 /* Swith on or off the tx queues */
5304 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5306 struct rte_eth_dev_data *dev_data = pf->dev_data;
5307 struct i40e_tx_queue *txq;
5308 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5312 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5313 txq = dev_data->tx_queues[i];
5314 /* Don't operate the queue if not configured or
5315 * if starting only per queue */
5316 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5319 ret = i40e_dev_tx_queue_start(dev, i);
5321 ret = i40e_dev_tx_queue_stop(dev, i);
5322 if ( ret != I40E_SUCCESS)
5326 return I40E_SUCCESS;
5330 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5335 /* Wait until the request is finished */
5336 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5337 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5338 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5339 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5340 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5345 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5346 return I40E_SUCCESS; /* Already on, skip next steps */
5347 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5349 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5350 return I40E_SUCCESS; /* Already off, skip next steps */
5351 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5354 /* Write the register */
5355 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5356 /* Check the result */
5357 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5358 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5359 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5361 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5362 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5365 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5366 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5371 /* Check if it is timeout */
5372 if (j >= I40E_CHK_Q_ENA_COUNT) {
5373 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5374 (on ? "enable" : "disable"), q_idx);
5375 return I40E_ERR_TIMEOUT;
5378 return I40E_SUCCESS;
5380 /* Switch on or off the rx queues */
5382 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5384 struct rte_eth_dev_data *dev_data = pf->dev_data;
5385 struct i40e_rx_queue *rxq;
5386 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5390 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5391 rxq = dev_data->rx_queues[i];
5392 /* Don't operate the queue if not configured or
5393 * if starting only per queue */
5394 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5397 ret = i40e_dev_rx_queue_start(dev, i);
5399 ret = i40e_dev_rx_queue_stop(dev, i);
5400 if (ret != I40E_SUCCESS)
5404 return I40E_SUCCESS;
5407 /* Switch on or off all the rx/tx queues */
5409 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5414 /* enable rx queues before enabling tx queues */
5415 ret = i40e_dev_switch_rx_queues(pf, on);
5417 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5420 ret = i40e_dev_switch_tx_queues(pf, on);
5422 /* Stop tx queues before stopping rx queues */
5423 ret = i40e_dev_switch_tx_queues(pf, on);
5425 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5428 ret = i40e_dev_switch_rx_queues(pf, on);
5434 /* Initialize VSI for TX */
5436 i40e_dev_tx_init(struct i40e_pf *pf)
5438 struct rte_eth_dev_data *data = pf->dev_data;
5440 uint32_t ret = I40E_SUCCESS;
5441 struct i40e_tx_queue *txq;
5443 for (i = 0; i < data->nb_tx_queues; i++) {
5444 txq = data->tx_queues[i];
5445 if (!txq || !txq->q_set)
5447 ret = i40e_tx_queue_init(txq);
5448 if (ret != I40E_SUCCESS)
5451 if (ret == I40E_SUCCESS)
5452 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5458 /* Initialize VSI for RX */
5460 i40e_dev_rx_init(struct i40e_pf *pf)
5462 struct rte_eth_dev_data *data = pf->dev_data;
5463 int ret = I40E_SUCCESS;
5465 struct i40e_rx_queue *rxq;
5467 i40e_pf_config_mq_rx(pf);
5468 for (i = 0; i < data->nb_rx_queues; i++) {
5469 rxq = data->rx_queues[i];
5470 if (!rxq || !rxq->q_set)
5473 ret = i40e_rx_queue_init(rxq);
5474 if (ret != I40E_SUCCESS) {
5475 PMD_DRV_LOG(ERR, "Failed to do RX queue "
5480 if (ret == I40E_SUCCESS)
5481 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5488 i40e_dev_rxtx_init(struct i40e_pf *pf)
5492 err = i40e_dev_tx_init(pf);
5494 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5497 err = i40e_dev_rx_init(pf);
5499 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5507 i40e_vmdq_setup(struct rte_eth_dev *dev)
5509 struct rte_eth_conf *conf = &dev->data->dev_conf;
5510 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5511 int i, err, conf_vsis, j, loop;
5512 struct i40e_vsi *vsi;
5513 struct i40e_vmdq_info *vmdq_info;
5514 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5515 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5518 * Disable interrupt to avoid message from VF. Furthermore, it will
5519 * avoid race condition in VSI creation/destroy.
5521 i40e_pf_disable_irq0(hw);
5523 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5524 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5528 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5529 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5530 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5531 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5532 pf->max_nb_vmdq_vsi);
5536 if (pf->vmdq != NULL) {
5537 PMD_INIT_LOG(INFO, "VMDQ already configured");
5541 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5542 sizeof(*vmdq_info) * conf_vsis, 0);
5544 if (pf->vmdq == NULL) {
5545 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5549 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5551 /* Create VMDQ VSI */
5552 for (i = 0; i < conf_vsis; i++) {
5553 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5554 vmdq_conf->enable_loop_back);
5556 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5560 vmdq_info = &pf->vmdq[i];
5562 vmdq_info->vsi = vsi;
5564 pf->nb_cfg_vmdq_vsi = conf_vsis;
5566 /* Configure Vlan */
5567 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5568 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5569 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5570 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5571 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5572 vmdq_conf->pool_map[i].vlan_id, j);
5574 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5575 vmdq_conf->pool_map[i].vlan_id);
5577 PMD_INIT_LOG(ERR, "Failed to add vlan");
5585 i40e_pf_enable_irq0(hw);
5590 for (i = 0; i < conf_vsis; i++)
5591 if (pf->vmdq[i].vsi == NULL)
5594 i40e_vsi_release(pf->vmdq[i].vsi);
5598 i40e_pf_enable_irq0(hw);
5603 i40e_stat_update_32(struct i40e_hw *hw,
5611 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5615 if (new_data >= *offset)
5616 *stat = (uint64_t)(new_data - *offset);
5618 *stat = (uint64_t)((new_data +
5619 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5623 i40e_stat_update_48(struct i40e_hw *hw,
5632 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5633 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5634 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5639 if (new_data >= *offset)
5640 *stat = new_data - *offset;
5642 *stat = (uint64_t)((new_data +
5643 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5645 *stat &= I40E_48_BIT_MASK;
5650 i40e_pf_disable_irq0(struct i40e_hw *hw)
5652 /* Disable all interrupt types */
5653 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5654 I40E_WRITE_FLUSH(hw);
5659 i40e_pf_enable_irq0(struct i40e_hw *hw)
5661 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5662 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5663 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5664 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5665 I40E_WRITE_FLUSH(hw);
5669 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5671 /* read pending request and disable first */
5672 i40e_pf_disable_irq0(hw);
5673 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5674 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5675 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5678 /* Link no queues with irq0 */
5679 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5680 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5684 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5686 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5687 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5690 uint32_t index, offset, val;
5695 * Try to find which VF trigger a reset, use absolute VF id to access
5696 * since the reg is global register.
5698 for (i = 0; i < pf->vf_num; i++) {
5699 abs_vf_id = hw->func_caps.vf_base_id + i;
5700 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5701 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5702 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5703 /* VFR event occured */
5704 if (val & (0x1 << offset)) {
5707 /* Clear the event first */
5708 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5710 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5712 * Only notify a VF reset event occured,
5713 * don't trigger another SW reset
5715 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5716 if (ret != I40E_SUCCESS)
5717 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5723 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5725 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5726 struct i40e_virtchnl_pf_event event;
5729 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5730 event.event_data.link_event.link_status =
5731 dev->data->dev_link.link_status;
5732 event.event_data.link_event.link_speed =
5733 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5735 for (i = 0; i < pf->vf_num; i++)
5736 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5737 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5741 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5743 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5744 struct i40e_arq_event_info info;
5745 uint16_t pending, opcode;
5748 info.buf_len = I40E_AQ_BUF_SZ;
5749 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5750 if (!info.msg_buf) {
5751 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5757 ret = i40e_clean_arq_element(hw, &info, &pending);
5759 if (ret != I40E_SUCCESS) {
5760 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5761 "aq_err: %u", hw->aq.asq_last_status);
5764 opcode = rte_le_to_cpu_16(info.desc.opcode);
5767 case i40e_aqc_opc_send_msg_to_pf:
5768 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5769 i40e_pf_host_handle_vf_msg(dev,
5770 rte_le_to_cpu_16(info.desc.retval),
5771 rte_le_to_cpu_32(info.desc.cookie_high),
5772 rte_le_to_cpu_32(info.desc.cookie_low),
5776 case i40e_aqc_opc_get_link_status:
5777 ret = i40e_dev_link_update(dev, 0);
5779 i40e_notify_all_vfs_link_status(dev);
5780 _rte_eth_dev_callback_process(dev,
5781 RTE_ETH_EVENT_INTR_LSC, NULL);
5785 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5790 rte_free(info.msg_buf);
5794 * Interrupt handler triggered by NIC for handling
5795 * specific interrupt.
5798 * Pointer to interrupt handle.
5800 * The address of parameter (struct rte_eth_dev *) regsitered before.
5806 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5809 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5810 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5813 /* Disable interrupt */
5814 i40e_pf_disable_irq0(hw);
5816 /* read out interrupt causes */
5817 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5819 /* No interrupt event indicated */
5820 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5821 PMD_DRV_LOG(INFO, "No interrupt event");
5824 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5825 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5826 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5827 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5828 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5829 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5830 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5831 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5832 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5833 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5834 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5835 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5836 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5837 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5838 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5839 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5841 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5842 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5843 i40e_dev_handle_vfr_event(dev);
5845 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5846 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5847 i40e_dev_handle_aq_msg(dev);
5851 /* Enable interrupt */
5852 i40e_pf_enable_irq0(hw);
5853 rte_intr_enable(intr_handle);
5857 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5858 struct i40e_macvlan_filter *filter,
5861 int ele_num, ele_buff_size;
5862 int num, actual_num, i;
5864 int ret = I40E_SUCCESS;
5865 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5866 struct i40e_aqc_add_macvlan_element_data *req_list;
5868 if (filter == NULL || total == 0)
5869 return I40E_ERR_PARAM;
5870 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5871 ele_buff_size = hw->aq.asq_buf_size;
5873 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5874 if (req_list == NULL) {
5875 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5876 return I40E_ERR_NO_MEMORY;
5881 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5882 memset(req_list, 0, ele_buff_size);
5884 for (i = 0; i < actual_num; i++) {
5885 (void)rte_memcpy(req_list[i].mac_addr,
5886 &filter[num + i].macaddr, ETH_ADDR_LEN);
5887 req_list[i].vlan_tag =
5888 rte_cpu_to_le_16(filter[num + i].vlan_id);
5890 switch (filter[num + i].filter_type) {
5891 case RTE_MAC_PERFECT_MATCH:
5892 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5893 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5895 case RTE_MACVLAN_PERFECT_MATCH:
5896 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5898 case RTE_MAC_HASH_MATCH:
5899 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5900 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5902 case RTE_MACVLAN_HASH_MATCH:
5903 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5906 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5907 ret = I40E_ERR_PARAM;
5911 req_list[i].queue_number = 0;
5913 req_list[i].flags = rte_cpu_to_le_16(flags);
5916 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5918 if (ret != I40E_SUCCESS) {
5919 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5923 } while (num < total);
5931 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5932 struct i40e_macvlan_filter *filter,
5935 int ele_num, ele_buff_size;
5936 int num, actual_num, i;
5938 int ret = I40E_SUCCESS;
5939 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5940 struct i40e_aqc_remove_macvlan_element_data *req_list;
5942 if (filter == NULL || total == 0)
5943 return I40E_ERR_PARAM;
5945 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5946 ele_buff_size = hw->aq.asq_buf_size;
5948 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5949 if (req_list == NULL) {
5950 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5951 return I40E_ERR_NO_MEMORY;
5956 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5957 memset(req_list, 0, ele_buff_size);
5959 for (i = 0; i < actual_num; i++) {
5960 (void)rte_memcpy(req_list[i].mac_addr,
5961 &filter[num + i].macaddr, ETH_ADDR_LEN);
5962 req_list[i].vlan_tag =
5963 rte_cpu_to_le_16(filter[num + i].vlan_id);
5965 switch (filter[num + i].filter_type) {
5966 case RTE_MAC_PERFECT_MATCH:
5967 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5968 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5970 case RTE_MACVLAN_PERFECT_MATCH:
5971 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5973 case RTE_MAC_HASH_MATCH:
5974 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5975 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5977 case RTE_MACVLAN_HASH_MATCH:
5978 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5981 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5982 ret = I40E_ERR_PARAM;
5985 req_list[i].flags = rte_cpu_to_le_16(flags);
5988 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5990 if (ret != I40E_SUCCESS) {
5991 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5995 } while (num < total);
6002 /* Find out specific MAC filter */
6003 static struct i40e_mac_filter *
6004 i40e_find_mac_filter(struct i40e_vsi *vsi,
6005 struct ether_addr *macaddr)
6007 struct i40e_mac_filter *f;
6009 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6010 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6018 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6021 uint32_t vid_idx, vid_bit;
6023 if (vlan_id > ETH_VLAN_ID_MAX)
6026 vid_idx = I40E_VFTA_IDX(vlan_id);
6027 vid_bit = I40E_VFTA_BIT(vlan_id);
6029 if (vsi->vfta[vid_idx] & vid_bit)
6036 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6037 uint16_t vlan_id, bool on)
6039 uint32_t vid_idx, vid_bit;
6041 if (vlan_id > ETH_VLAN_ID_MAX)
6044 vid_idx = I40E_VFTA_IDX(vlan_id);
6045 vid_bit = I40E_VFTA_BIT(vlan_id);
6048 vsi->vfta[vid_idx] |= vid_bit;
6050 vsi->vfta[vid_idx] &= ~vid_bit;
6054 * Find all vlan options for specific mac addr,
6055 * return with actual vlan found.
6058 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6059 struct i40e_macvlan_filter *mv_f,
6060 int num, struct ether_addr *addr)
6066 * Not to use i40e_find_vlan_filter to decrease the loop time,
6067 * although the code looks complex.
6069 if (num < vsi->vlan_num)
6070 return I40E_ERR_PARAM;
6073 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6075 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6076 if (vsi->vfta[j] & (1 << k)) {
6078 PMD_DRV_LOG(ERR, "vlan number "
6080 return I40E_ERR_PARAM;
6082 (void)rte_memcpy(&mv_f[i].macaddr,
6083 addr, ETH_ADDR_LEN);
6085 j * I40E_UINT32_BIT_SIZE + k;
6091 return I40E_SUCCESS;
6095 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6096 struct i40e_macvlan_filter *mv_f,
6101 struct i40e_mac_filter *f;
6103 if (num < vsi->mac_num)
6104 return I40E_ERR_PARAM;
6106 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6108 PMD_DRV_LOG(ERR, "buffer number not match");
6109 return I40E_ERR_PARAM;
6111 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6113 mv_f[i].vlan_id = vlan;
6114 mv_f[i].filter_type = f->mac_info.filter_type;
6118 return I40E_SUCCESS;
6122 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6125 struct i40e_mac_filter *f;
6126 struct i40e_macvlan_filter *mv_f;
6127 int ret = I40E_SUCCESS;
6129 if (vsi == NULL || vsi->mac_num == 0)
6130 return I40E_ERR_PARAM;
6132 /* Case that no vlan is set */
6133 if (vsi->vlan_num == 0)
6136 num = vsi->mac_num * vsi->vlan_num;
6138 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6140 PMD_DRV_LOG(ERR, "failed to allocate memory");
6141 return I40E_ERR_NO_MEMORY;
6145 if (vsi->vlan_num == 0) {
6146 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6147 (void)rte_memcpy(&mv_f[i].macaddr,
6148 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6149 mv_f[i].vlan_id = 0;
6153 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6154 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6155 vsi->vlan_num, &f->mac_info.mac_addr);
6156 if (ret != I40E_SUCCESS)
6162 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6170 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6172 struct i40e_macvlan_filter *mv_f;
6174 int ret = I40E_SUCCESS;
6176 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6177 return I40E_ERR_PARAM;
6179 /* If it's already set, just return */
6180 if (i40e_find_vlan_filter(vsi,vlan))
6181 return I40E_SUCCESS;
6183 mac_num = vsi->mac_num;
6186 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6187 return I40E_ERR_PARAM;
6190 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6193 PMD_DRV_LOG(ERR, "failed to allocate memory");
6194 return I40E_ERR_NO_MEMORY;
6197 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6199 if (ret != I40E_SUCCESS)
6202 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6204 if (ret != I40E_SUCCESS)
6207 i40e_set_vlan_filter(vsi, vlan, 1);
6217 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6219 struct i40e_macvlan_filter *mv_f;
6221 int ret = I40E_SUCCESS;
6224 * Vlan 0 is the generic filter for untagged packets
6225 * and can't be removed.
6227 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6228 return I40E_ERR_PARAM;
6230 /* If can't find it, just return */
6231 if (!i40e_find_vlan_filter(vsi, vlan))
6232 return I40E_ERR_PARAM;
6234 mac_num = vsi->mac_num;
6237 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6238 return I40E_ERR_PARAM;
6241 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6244 PMD_DRV_LOG(ERR, "failed to allocate memory");
6245 return I40E_ERR_NO_MEMORY;
6248 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6250 if (ret != I40E_SUCCESS)
6253 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6255 if (ret != I40E_SUCCESS)
6258 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6259 if (vsi->vlan_num == 1) {
6260 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6261 if (ret != I40E_SUCCESS)
6264 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6265 if (ret != I40E_SUCCESS)
6269 i40e_set_vlan_filter(vsi, vlan, 0);
6279 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6281 struct i40e_mac_filter *f;
6282 struct i40e_macvlan_filter *mv_f;
6283 int i, vlan_num = 0;
6284 int ret = I40E_SUCCESS;
6286 /* If it's add and we've config it, return */
6287 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6289 return I40E_SUCCESS;
6290 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6291 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6294 * If vlan_num is 0, that's the first time to add mac,
6295 * set mask for vlan_id 0.
6297 if (vsi->vlan_num == 0) {
6298 i40e_set_vlan_filter(vsi, 0, 1);
6301 vlan_num = vsi->vlan_num;
6302 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6303 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6306 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6308 PMD_DRV_LOG(ERR, "failed to allocate memory");
6309 return I40E_ERR_NO_MEMORY;
6312 for (i = 0; i < vlan_num; i++) {
6313 mv_f[i].filter_type = mac_filter->filter_type;
6314 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6318 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6319 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6320 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6321 &mac_filter->mac_addr);
6322 if (ret != I40E_SUCCESS)
6326 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6327 if (ret != I40E_SUCCESS)
6330 /* Add the mac addr into mac list */
6331 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6333 PMD_DRV_LOG(ERR, "failed to allocate memory");
6334 ret = I40E_ERR_NO_MEMORY;
6337 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6339 f->mac_info.filter_type = mac_filter->filter_type;
6340 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6351 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6353 struct i40e_mac_filter *f;
6354 struct i40e_macvlan_filter *mv_f;
6356 enum rte_mac_filter_type filter_type;
6357 int ret = I40E_SUCCESS;
6359 /* Can't find it, return an error */
6360 f = i40e_find_mac_filter(vsi, addr);
6362 return I40E_ERR_PARAM;
6364 vlan_num = vsi->vlan_num;
6365 filter_type = f->mac_info.filter_type;
6366 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6367 filter_type == RTE_MACVLAN_HASH_MATCH) {
6368 if (vlan_num == 0) {
6369 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6370 return I40E_ERR_PARAM;
6372 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6373 filter_type == RTE_MAC_HASH_MATCH)
6376 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6378 PMD_DRV_LOG(ERR, "failed to allocate memory");
6379 return I40E_ERR_NO_MEMORY;
6382 for (i = 0; i < vlan_num; i++) {
6383 mv_f[i].filter_type = filter_type;
6384 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6387 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6388 filter_type == RTE_MACVLAN_HASH_MATCH) {
6389 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6390 if (ret != I40E_SUCCESS)
6394 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6395 if (ret != I40E_SUCCESS)
6398 /* Remove the mac addr into mac list */
6399 TAILQ_REMOVE(&vsi->mac_list, f, next);
6409 /* Configure hash enable flags for RSS */
6411 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6418 if (flags & ETH_RSS_FRAG_IPV4)
6419 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6420 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6421 if (type == I40E_MAC_X722) {
6422 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6423 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6425 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6427 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6428 if (type == I40E_MAC_X722) {
6429 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6430 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6431 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6433 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6435 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6436 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6437 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6438 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6439 if (flags & ETH_RSS_FRAG_IPV6)
6440 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6441 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6442 if (type == I40E_MAC_X722) {
6443 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6444 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6446 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6448 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6449 if (type == I40E_MAC_X722) {
6450 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6451 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6452 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6454 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6456 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6457 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6458 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6459 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6460 if (flags & ETH_RSS_L2_PAYLOAD)
6461 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6466 /* Parse the hash enable flags */
6468 i40e_parse_hena(uint64_t flags)
6470 uint64_t rss_hf = 0;
6474 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6475 rss_hf |= ETH_RSS_FRAG_IPV4;
6476 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6477 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6478 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6479 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6480 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6481 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6482 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6483 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6484 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6485 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6486 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6487 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6488 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6489 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6490 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6491 rss_hf |= ETH_RSS_FRAG_IPV6;
6492 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6493 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6494 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6495 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6496 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6497 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6498 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6499 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6500 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6501 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6502 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6503 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6504 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6505 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6506 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6507 rss_hf |= ETH_RSS_L2_PAYLOAD;
6514 i40e_pf_disable_rss(struct i40e_pf *pf)
6516 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6519 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6520 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6521 if (hw->mac.type == I40E_MAC_X722)
6522 hena &= ~I40E_RSS_HENA_ALL_X722;
6524 hena &= ~I40E_RSS_HENA_ALL;
6525 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6526 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6527 I40E_WRITE_FLUSH(hw);
6531 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6533 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6534 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6537 if (!key || key_len == 0) {
6538 PMD_DRV_LOG(DEBUG, "No key to be configured");
6540 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6542 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6546 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6547 struct i40e_aqc_get_set_rss_key_data *key_dw =
6548 (struct i40e_aqc_get_set_rss_key_data *)key;
6550 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6552 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6555 uint32_t *hash_key = (uint32_t *)key;
6558 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6559 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6560 I40E_WRITE_FLUSH(hw);
6567 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6569 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6570 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6573 if (!key || !key_len)
6576 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6577 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6578 (struct i40e_aqc_get_set_rss_key_data *)key);
6580 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6584 uint32_t *key_dw = (uint32_t *)key;
6587 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6588 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6590 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6596 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6598 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6603 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6604 rss_conf->rss_key_len);
6608 rss_hf = rss_conf->rss_hf;
6609 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6610 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6611 if (hw->mac.type == I40E_MAC_X722)
6612 hena &= ~I40E_RSS_HENA_ALL_X722;
6614 hena &= ~I40E_RSS_HENA_ALL;
6615 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6616 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6617 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6618 I40E_WRITE_FLUSH(hw);
6624 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6625 struct rte_eth_rss_conf *rss_conf)
6627 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6628 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6629 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6632 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6633 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6634 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6635 ? I40E_RSS_HENA_ALL_X722
6636 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6637 if (rss_hf != 0) /* Enable RSS */
6639 return 0; /* Nothing to do */
6642 if (rss_hf == 0) /* Disable RSS */
6645 return i40e_hw_rss_hash_set(pf, rss_conf);
6649 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6650 struct rte_eth_rss_conf *rss_conf)
6652 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6653 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6656 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6657 &rss_conf->rss_key_len);
6659 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6660 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6661 rss_conf->rss_hf = i40e_parse_hena(hena);
6667 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6669 switch (filter_type) {
6670 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6671 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6673 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6674 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6676 case RTE_TUNNEL_FILTER_IMAC_TENID:
6677 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6679 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6680 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6682 case ETH_TUNNEL_FILTER_IMAC:
6683 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6685 case ETH_TUNNEL_FILTER_OIP:
6686 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6688 case ETH_TUNNEL_FILTER_IIP:
6689 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6692 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6699 /* Convert tunnel filter structure */
6701 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6703 struct i40e_tunnel_filter *tunnel_filter)
6705 ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6706 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6707 ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6708 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6709 tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6710 tunnel_filter->input.flags = cld_filter->flags;
6711 tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6712 tunnel_filter->queue = cld_filter->queue_number;
6717 /* Check if there exists the tunnel filter */
6718 struct i40e_tunnel_filter *
6719 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6720 const struct i40e_tunnel_filter_input *input)
6724 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6728 return tunnel_rule->hash_map[ret];
6731 /* Add a tunnel filter into the SW list */
6733 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6734 struct i40e_tunnel_filter *tunnel_filter)
6736 struct i40e_tunnel_rule *rule = &pf->tunnel;
6739 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6742 "Failed to insert tunnel filter to hash table %d!",
6746 rule->hash_map[ret] = tunnel_filter;
6748 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6753 /* Delete a tunnel filter from the SW list */
6755 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6756 struct i40e_tunnel_filter_input *input)
6758 struct i40e_tunnel_rule *rule = &pf->tunnel;
6759 struct i40e_tunnel_filter *tunnel_filter;
6762 ret = rte_hash_del_key(rule->hash_table, input);
6765 "Failed to delete tunnel filter to hash table %d!",
6769 tunnel_filter = rule->hash_map[ret];
6770 rule->hash_map[ret] = NULL;
6772 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6773 rte_free(tunnel_filter);
6779 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6780 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6785 uint8_t i, tun_type = 0;
6786 /* internal varialbe to convert ipv6 byte order */
6787 uint32_t convert_ipv6[4];
6789 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6790 struct i40e_vsi *vsi = pf->main_vsi;
6791 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6792 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6793 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6794 struct i40e_tunnel_filter *tunnel, *node;
6795 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6797 cld_filter = rte_zmalloc("tunnel_filter",
6798 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6801 if (NULL == cld_filter) {
6802 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6805 pfilter = cld_filter;
6807 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6808 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6810 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6811 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6812 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6813 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6814 rte_memcpy(&pfilter->ipaddr.v4.data,
6815 &rte_cpu_to_le_32(ipv4_addr),
6816 sizeof(pfilter->ipaddr.v4.data));
6818 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6819 for (i = 0; i < 4; i++) {
6821 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6823 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6824 sizeof(pfilter->ipaddr.v6.data));
6827 /* check tunneled type */
6828 switch (tunnel_filter->tunnel_type) {
6829 case RTE_TUNNEL_TYPE_VXLAN:
6830 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6832 case RTE_TUNNEL_TYPE_NVGRE:
6833 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6835 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6836 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6839 /* Other tunnel types is not supported. */
6840 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6841 rte_free(cld_filter);
6845 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6848 rte_free(cld_filter);
6852 pfilter->flags |= rte_cpu_to_le_16(
6853 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6854 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6855 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6856 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6858 /* Check if there is the filter in SW list */
6859 memset(&check_filter, 0, sizeof(check_filter));
6860 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6861 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6863 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6867 if (!add && !node) {
6868 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6873 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6875 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6878 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6879 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6880 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6882 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6885 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6888 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6891 rte_free(cld_filter);
6896 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6900 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6901 if (pf->vxlan_ports[i] == port)
6909 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6913 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6915 idx = i40e_get_vxlan_port_idx(pf, port);
6917 /* Check if port already exists */
6919 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6923 /* Now check if there is space to add the new port */
6924 idx = i40e_get_vxlan_port_idx(pf, 0);
6926 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6927 "not adding port %d", port);
6931 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6934 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6938 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6941 /* New port: add it and mark its index in the bitmap */
6942 pf->vxlan_ports[idx] = port;
6943 pf->vxlan_bitmap |= (1 << idx);
6945 if (!(pf->flags & I40E_FLAG_VXLAN))
6946 pf->flags |= I40E_FLAG_VXLAN;
6952 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6955 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6957 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6958 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6962 idx = i40e_get_vxlan_port_idx(pf, port);
6965 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6969 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6970 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6974 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6977 pf->vxlan_ports[idx] = 0;
6978 pf->vxlan_bitmap &= ~(1 << idx);
6980 if (!pf->vxlan_bitmap)
6981 pf->flags &= ~I40E_FLAG_VXLAN;
6986 /* Add UDP tunneling port */
6988 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6989 struct rte_eth_udp_tunnel *udp_tunnel)
6992 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6994 if (udp_tunnel == NULL)
6997 switch (udp_tunnel->prot_type) {
6998 case RTE_TUNNEL_TYPE_VXLAN:
6999 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7002 case RTE_TUNNEL_TYPE_GENEVE:
7003 case RTE_TUNNEL_TYPE_TEREDO:
7004 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7009 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7017 /* Remove UDP tunneling port */
7019 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7020 struct rte_eth_udp_tunnel *udp_tunnel)
7023 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7025 if (udp_tunnel == NULL)
7028 switch (udp_tunnel->prot_type) {
7029 case RTE_TUNNEL_TYPE_VXLAN:
7030 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7032 case RTE_TUNNEL_TYPE_GENEVE:
7033 case RTE_TUNNEL_TYPE_TEREDO:
7034 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7038 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7046 /* Calculate the maximum number of contiguous PF queues that are configured */
7048 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7050 struct rte_eth_dev_data *data = pf->dev_data;
7052 struct i40e_rx_queue *rxq;
7055 for (i = 0; i < pf->lan_nb_qps; i++) {
7056 rxq = data->rx_queues[i];
7057 if (rxq && rxq->q_set)
7068 i40e_pf_config_rss(struct i40e_pf *pf)
7070 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7071 struct rte_eth_rss_conf rss_conf;
7072 uint32_t i, lut = 0;
7076 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7077 * It's necessary to calulate the actual PF queues that are configured.
7079 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7080 num = i40e_pf_calc_configured_queues_num(pf);
7082 num = pf->dev_data->nb_rx_queues;
7084 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7085 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7089 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7093 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7096 lut = (lut << 8) | (j & ((0x1 <<
7097 hw->func_caps.rss_table_entry_width) - 1));
7099 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7102 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7103 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7104 i40e_pf_disable_rss(pf);
7107 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7108 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7109 /* Random default keys */
7110 static uint32_t rss_key_default[] = {0x6b793944,
7111 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7112 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7113 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7115 rss_conf.rss_key = (uint8_t *)rss_key_default;
7116 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7120 return i40e_hw_rss_hash_set(pf, &rss_conf);
7124 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7125 struct rte_eth_tunnel_filter_conf *filter)
7127 if (pf == NULL || filter == NULL) {
7128 PMD_DRV_LOG(ERR, "Invalid parameter");
7132 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7133 PMD_DRV_LOG(ERR, "Invalid queue ID");
7137 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7138 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7142 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7143 (is_zero_ether_addr(&filter->outer_mac))) {
7144 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7148 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7149 (is_zero_ether_addr(&filter->inner_mac))) {
7150 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7157 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7158 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7160 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7165 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7166 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7169 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7170 } else if (len == 4) {
7171 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7173 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7178 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7185 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7186 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7192 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7199 switch (cfg->cfg_type) {
7200 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7201 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7204 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7212 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7213 enum rte_filter_op filter_op,
7216 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7217 int ret = I40E_ERR_PARAM;
7219 switch (filter_op) {
7220 case RTE_ETH_FILTER_SET:
7221 ret = i40e_dev_global_config_set(hw,
7222 (struct rte_eth_global_cfg *)arg);
7225 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7233 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7234 enum rte_filter_op filter_op,
7237 struct rte_eth_tunnel_filter_conf *filter;
7238 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7239 int ret = I40E_SUCCESS;
7241 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7243 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7244 return I40E_ERR_PARAM;
7246 switch (filter_op) {
7247 case RTE_ETH_FILTER_NOP:
7248 if (!(pf->flags & I40E_FLAG_VXLAN))
7249 ret = I40E_NOT_SUPPORTED;
7251 case RTE_ETH_FILTER_ADD:
7252 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7254 case RTE_ETH_FILTER_DELETE:
7255 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7258 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7259 ret = I40E_ERR_PARAM;
7267 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7270 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7273 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7274 ret = i40e_pf_config_rss(pf);
7276 i40e_pf_disable_rss(pf);
7281 /* Get the symmetric hash enable configurations per port */
7283 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7285 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7287 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7290 /* Set the symmetric hash enable configurations per port */
7292 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7294 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7297 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7298 PMD_DRV_LOG(INFO, "Symmetric hash has already "
7302 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7304 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7305 PMD_DRV_LOG(INFO, "Symmetric hash has already "
7309 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7311 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7312 I40E_WRITE_FLUSH(hw);
7316 * Get global configurations of hash function type and symmetric hash enable
7317 * per flow type (pctype). Note that global configuration means it affects all
7318 * the ports on the same NIC.
7321 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7322 struct rte_eth_hash_global_conf *g_cfg)
7324 uint32_t reg, mask = I40E_FLOW_TYPES;
7326 enum i40e_filter_pctype pctype;
7328 memset(g_cfg, 0, sizeof(*g_cfg));
7329 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7330 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7331 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7333 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7334 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7335 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7337 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7338 if (!(mask & (1UL << i)))
7340 mask &= ~(1UL << i);
7341 /* Bit set indicats the coresponding flow type is supported */
7342 g_cfg->valid_bit_mask[0] |= (1UL << i);
7343 /* if flowtype is invalid, continue */
7344 if (!I40E_VALID_FLOW(i))
7346 pctype = i40e_flowtype_to_pctype(i);
7347 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7348 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7349 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7356 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7359 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7361 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7362 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7363 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7364 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7370 * As i40e supports less than 32 flow types, only first 32 bits need to
7373 mask0 = g_cfg->valid_bit_mask[0];
7374 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7376 /* Check if any unsupported flow type configured */
7377 if ((mask0 | i40e_mask) ^ i40e_mask)
7380 if (g_cfg->valid_bit_mask[i])
7388 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7394 * Set global configurations of hash function type and symmetric hash enable
7395 * per flow type (pctype). Note any modifying global configuration will affect
7396 * all the ports on the same NIC.
7399 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7400 struct rte_eth_hash_global_conf *g_cfg)
7405 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7406 enum i40e_filter_pctype pctype;
7408 /* Check the input parameters */
7409 ret = i40e_hash_global_config_check(g_cfg);
7413 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7414 if (!(mask0 & (1UL << i)))
7416 mask0 &= ~(1UL << i);
7417 /* if flowtype is invalid, continue */
7418 if (!I40E_VALID_FLOW(i))
7420 pctype = i40e_flowtype_to_pctype(i);
7421 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7422 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7423 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7426 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7427 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7429 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7430 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7434 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7435 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7437 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7438 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7442 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7444 /* Use the default, and keep it as it is */
7447 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7450 I40E_WRITE_FLUSH(hw);
7456 * Valid input sets for hash and flow director filters per PCTYPE
7459 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7460 enum rte_filter_type filter)
7464 static const uint64_t valid_hash_inset_table[] = {
7465 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7466 I40E_INSET_DMAC | I40E_INSET_SMAC |
7467 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7468 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7469 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7470 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7471 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7472 I40E_INSET_FLEX_PAYLOAD,
7473 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7474 I40E_INSET_DMAC | I40E_INSET_SMAC |
7475 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7476 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7477 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7478 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7479 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7480 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7481 I40E_INSET_FLEX_PAYLOAD,
7482 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7483 I40E_INSET_DMAC | I40E_INSET_SMAC |
7484 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7485 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7486 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7487 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7488 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7489 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7490 I40E_INSET_FLEX_PAYLOAD,
7491 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7492 I40E_INSET_DMAC | I40E_INSET_SMAC |
7493 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7494 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7495 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7496 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7497 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7498 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7499 I40E_INSET_FLEX_PAYLOAD,
7500 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7501 I40E_INSET_DMAC | I40E_INSET_SMAC |
7502 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7503 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7504 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7505 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7506 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7507 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7508 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7509 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7510 I40E_INSET_DMAC | I40E_INSET_SMAC |
7511 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7512 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7513 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7514 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7515 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7516 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7517 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7518 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7519 I40E_INSET_DMAC | I40E_INSET_SMAC |
7520 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7521 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7522 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7523 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7524 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7525 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7526 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7527 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7528 I40E_INSET_DMAC | I40E_INSET_SMAC |
7529 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7530 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7531 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7532 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7533 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7534 I40E_INSET_FLEX_PAYLOAD,
7535 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7536 I40E_INSET_DMAC | I40E_INSET_SMAC |
7537 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7538 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7539 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7540 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7541 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7542 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7543 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7544 I40E_INSET_DMAC | I40E_INSET_SMAC |
7545 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7546 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7547 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7548 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7549 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7550 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7551 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7552 I40E_INSET_DMAC | I40E_INSET_SMAC |
7553 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7554 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7555 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7556 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7557 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7558 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7559 I40E_INSET_FLEX_PAYLOAD,
7560 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7561 I40E_INSET_DMAC | I40E_INSET_SMAC |
7562 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7563 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7564 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7565 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7566 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7567 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7568 I40E_INSET_FLEX_PAYLOAD,
7569 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7570 I40E_INSET_DMAC | I40E_INSET_SMAC |
7571 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7572 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7573 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7574 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7575 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7576 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7577 I40E_INSET_FLEX_PAYLOAD,
7578 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7579 I40E_INSET_DMAC | I40E_INSET_SMAC |
7580 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7581 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7582 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7583 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7584 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7585 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7586 I40E_INSET_FLEX_PAYLOAD,
7587 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7588 I40E_INSET_DMAC | I40E_INSET_SMAC |
7589 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7590 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7591 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7592 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7593 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7594 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7595 I40E_INSET_FLEX_PAYLOAD,
7596 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7597 I40E_INSET_DMAC | I40E_INSET_SMAC |
7598 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7599 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7600 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7601 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7602 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7603 I40E_INSET_FLEX_PAYLOAD,
7604 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7605 I40E_INSET_DMAC | I40E_INSET_SMAC |
7606 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7607 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7608 I40E_INSET_FLEX_PAYLOAD,
7612 * Flow director supports only fields defined in
7613 * union rte_eth_fdir_flow.
7615 static const uint64_t valid_fdir_inset_table[] = {
7616 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7617 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7618 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7619 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7620 I40E_INSET_IPV4_TTL,
7621 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7622 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7623 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7624 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7625 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7626 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7627 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7628 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7629 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7630 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7631 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7632 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7633 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7634 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7635 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7636 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7637 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7638 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7639 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7640 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7641 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7642 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7643 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7644 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7645 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7646 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7647 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7648 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7649 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7650 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7652 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7653 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7654 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7655 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7656 I40E_INSET_IPV4_TTL,
7657 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7658 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7659 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7660 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7661 I40E_INSET_IPV6_HOP_LIMIT,
7662 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7663 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7664 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7665 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7666 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7667 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7668 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7669 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7670 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7671 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7672 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7673 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7674 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7675 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7676 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7677 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7678 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7679 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7680 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7681 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7682 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7683 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7684 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7685 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7686 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7687 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7688 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7689 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7690 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7691 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7693 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7694 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7695 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7696 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7697 I40E_INSET_IPV6_HOP_LIMIT,
7698 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7699 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7700 I40E_INSET_LAST_ETHER_TYPE,
7703 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7705 if (filter == RTE_ETH_FILTER_HASH)
7706 valid = valid_hash_inset_table[pctype];
7708 valid = valid_fdir_inset_table[pctype];
7714 * Validate if the input set is allowed for a specific PCTYPE
7717 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7718 enum rte_filter_type filter, uint64_t inset)
7722 valid = i40e_get_valid_input_set(pctype, filter);
7723 if (inset & (~valid))
7729 /* default input set fields combination per pctype */
7731 i40e_get_default_input_set(uint16_t pctype)
7733 static const uint64_t default_inset_table[] = {
7734 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7735 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7736 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7737 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7738 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7739 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7740 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7741 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7742 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7743 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7744 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7745 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7746 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7747 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7748 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7749 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7750 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7751 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7752 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7753 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7755 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7756 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7757 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7758 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7759 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7760 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7761 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7762 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7763 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7764 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7765 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7766 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7767 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7768 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7769 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7770 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7771 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7772 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7773 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7774 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7775 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7776 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7778 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7779 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7780 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7781 I40E_INSET_LAST_ETHER_TYPE,
7784 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7787 return default_inset_table[pctype];
7791 * Parse the input set from index to logical bit masks
7794 i40e_parse_input_set(uint64_t *inset,
7795 enum i40e_filter_pctype pctype,
7796 enum rte_eth_input_set_field *field,
7802 static const struct {
7803 enum rte_eth_input_set_field field;
7805 } inset_convert_table[] = {
7806 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7807 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7808 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7809 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7810 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7811 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7812 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7813 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7814 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7815 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7816 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7817 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7818 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7819 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7820 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7821 I40E_INSET_IPV6_NEXT_HDR},
7822 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7823 I40E_INSET_IPV6_HOP_LIMIT},
7824 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7825 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7826 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7827 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7828 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7829 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7830 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7831 I40E_INSET_SCTP_VT},
7832 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7833 I40E_INSET_TUNNEL_DMAC},
7834 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7835 I40E_INSET_VLAN_TUNNEL},
7836 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7837 I40E_INSET_TUNNEL_ID},
7838 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7839 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7840 I40E_INSET_FLEX_PAYLOAD_W1},
7841 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7842 I40E_INSET_FLEX_PAYLOAD_W2},
7843 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7844 I40E_INSET_FLEX_PAYLOAD_W3},
7845 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7846 I40E_INSET_FLEX_PAYLOAD_W4},
7847 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7848 I40E_INSET_FLEX_PAYLOAD_W5},
7849 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7850 I40E_INSET_FLEX_PAYLOAD_W6},
7851 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7852 I40E_INSET_FLEX_PAYLOAD_W7},
7853 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7854 I40E_INSET_FLEX_PAYLOAD_W8},
7857 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7860 /* Only one item allowed for default or all */
7862 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7863 *inset = i40e_get_default_input_set(pctype);
7865 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7866 *inset = I40E_INSET_NONE;
7871 for (i = 0, *inset = 0; i < size; i++) {
7872 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7873 if (field[i] == inset_convert_table[j].field) {
7874 *inset |= inset_convert_table[j].inset;
7879 /* It contains unsupported input set, return immediately */
7880 if (j == RTE_DIM(inset_convert_table))
7888 * Translate the input set from bit masks to register aware bit masks
7892 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7902 static const struct inset_map inset_map_common[] = {
7903 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7904 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7905 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7906 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7907 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7908 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7909 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7910 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7911 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7912 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7913 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7914 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7915 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7916 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7917 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7918 {I40E_INSET_TUNNEL_DMAC,
7919 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7920 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7921 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7922 {I40E_INSET_TUNNEL_SRC_PORT,
7923 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7924 {I40E_INSET_TUNNEL_DST_PORT,
7925 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7926 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7927 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7928 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7929 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7930 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7931 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7932 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7933 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7934 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7937 /* some different registers map in x722*/
7938 static const struct inset_map inset_map_diff_x722[] = {
7939 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7940 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7941 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7942 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7945 static const struct inset_map inset_map_diff_not_x722[] = {
7946 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7947 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7948 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7949 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7955 /* Translate input set to register aware inset */
7956 if (type == I40E_MAC_X722) {
7957 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7958 if (input & inset_map_diff_x722[i].inset)
7959 val |= inset_map_diff_x722[i].inset_reg;
7962 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7963 if (input & inset_map_diff_not_x722[i].inset)
7964 val |= inset_map_diff_not_x722[i].inset_reg;
7968 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7969 if (input & inset_map_common[i].inset)
7970 val |= inset_map_common[i].inset_reg;
7977 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7980 uint64_t inset_need_mask = inset;
7982 static const struct {
7985 } inset_mask_map[] = {
7986 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7987 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7988 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7989 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7990 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7991 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7992 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7993 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7996 if (!inset || !mask || !nb_elem)
7999 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8000 /* Clear the inset bit, if no MASK is required,
8001 * for example proto + ttl
8003 if ((inset & inset_mask_map[i].inset) ==
8004 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8005 inset_need_mask &= ~inset_mask_map[i].inset;
8006 if (!inset_need_mask)
8009 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8010 if ((inset_need_mask & inset_mask_map[i].inset) ==
8011 inset_mask_map[i].inset) {
8012 if (idx >= nb_elem) {
8013 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8016 mask[idx] = inset_mask_map[i].mask;
8025 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8027 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8029 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
8031 i40e_write_rx_ctl(hw, addr, val);
8032 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
8033 (uint32_t)i40e_read_rx_ctl(hw, addr));
8037 i40e_filter_input_set_init(struct i40e_pf *pf)
8039 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8040 enum i40e_filter_pctype pctype;
8041 uint64_t input_set, inset_reg;
8042 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8045 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8046 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8047 if (hw->mac.type == I40E_MAC_X722) {
8048 if (!I40E_VALID_PCTYPE_X722(pctype))
8051 if (!I40E_VALID_PCTYPE(pctype))
8055 input_set = i40e_get_default_input_set(pctype);
8057 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8058 I40E_INSET_MASK_NUM_REG);
8061 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8064 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8065 (uint32_t)(inset_reg & UINT32_MAX));
8066 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8067 (uint32_t)((inset_reg >>
8068 I40E_32_BIT_WIDTH) & UINT32_MAX));
8069 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8070 (uint32_t)(inset_reg & UINT32_MAX));
8071 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8072 (uint32_t)((inset_reg >>
8073 I40E_32_BIT_WIDTH) & UINT32_MAX));
8075 for (i = 0; i < num; i++) {
8076 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8078 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8081 /*clear unused mask registers of the pctype */
8082 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8083 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8085 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8088 I40E_WRITE_FLUSH(hw);
8090 /* store the default input set */
8091 pf->hash_input_set[pctype] = input_set;
8092 pf->fdir.input_set[pctype] = input_set;
8097 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8098 struct rte_eth_input_set_conf *conf)
8100 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8101 enum i40e_filter_pctype pctype;
8102 uint64_t input_set, inset_reg = 0;
8103 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8107 PMD_DRV_LOG(ERR, "Invalid pointer");
8110 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8111 conf->op != RTE_ETH_INPUT_SET_ADD) {
8112 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8116 if (!I40E_VALID_FLOW(conf->flow_type)) {
8117 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8121 if (hw->mac.type == I40E_MAC_X722) {
8122 /* get translated pctype value in fd pctype register */
8123 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8124 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8127 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8129 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8132 PMD_DRV_LOG(ERR, "Failed to parse input set");
8135 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8137 PMD_DRV_LOG(ERR, "Invalid input set");
8140 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8141 /* get inset value in register */
8142 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8143 inset_reg <<= I40E_32_BIT_WIDTH;
8144 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8145 input_set |= pf->hash_input_set[pctype];
8147 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8148 I40E_INSET_MASK_NUM_REG);
8152 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8154 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8155 (uint32_t)(inset_reg & UINT32_MAX));
8156 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8157 (uint32_t)((inset_reg >>
8158 I40E_32_BIT_WIDTH) & UINT32_MAX));
8160 for (i = 0; i < num; i++)
8161 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8163 /*clear unused mask registers of the pctype */
8164 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8165 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8167 I40E_WRITE_FLUSH(hw);
8169 pf->hash_input_set[pctype] = input_set;
8174 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8175 struct rte_eth_input_set_conf *conf)
8177 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8178 enum i40e_filter_pctype pctype;
8179 uint64_t input_set, inset_reg = 0;
8180 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8184 PMD_DRV_LOG(ERR, "Invalid pointer");
8187 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8188 conf->op != RTE_ETH_INPUT_SET_ADD) {
8189 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8193 if (!I40E_VALID_FLOW(conf->flow_type)) {
8194 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8198 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8200 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8203 PMD_DRV_LOG(ERR, "Failed to parse input set");
8206 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8208 PMD_DRV_LOG(ERR, "Invalid input set");
8212 /* get inset value in register */
8213 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8214 inset_reg <<= I40E_32_BIT_WIDTH;
8215 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8217 /* Can not change the inset reg for flex payload for fdir,
8218 * it is done by writing I40E_PRTQF_FD_FLXINSET
8219 * in i40e_set_flex_mask_on_pctype.
8221 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8222 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8224 input_set |= pf->fdir.input_set[pctype];
8225 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8226 I40E_INSET_MASK_NUM_REG);
8230 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8232 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8233 (uint32_t)(inset_reg & UINT32_MAX));
8234 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8235 (uint32_t)((inset_reg >>
8236 I40E_32_BIT_WIDTH) & UINT32_MAX));
8238 for (i = 0; i < num; i++)
8239 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8241 /*clear unused mask registers of the pctype */
8242 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8243 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8245 I40E_WRITE_FLUSH(hw);
8247 pf->fdir.input_set[pctype] = input_set;
8252 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8257 PMD_DRV_LOG(ERR, "Invalid pointer");
8261 switch (info->info_type) {
8262 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8263 i40e_get_symmetric_hash_enable_per_port(hw,
8264 &(info->info.enable));
8266 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8267 ret = i40e_get_hash_filter_global_config(hw,
8268 &(info->info.global_conf));
8271 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8281 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8286 PMD_DRV_LOG(ERR, "Invalid pointer");
8290 switch (info->info_type) {
8291 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8292 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8294 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8295 ret = i40e_set_hash_filter_global_config(hw,
8296 &(info->info.global_conf));
8298 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8299 ret = i40e_hash_filter_inset_select(hw,
8300 &(info->info.input_set_conf));
8304 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8313 /* Operations for hash function */
8315 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8316 enum rte_filter_op filter_op,
8319 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8322 switch (filter_op) {
8323 case RTE_ETH_FILTER_NOP:
8325 case RTE_ETH_FILTER_GET:
8326 ret = i40e_hash_filter_get(hw,
8327 (struct rte_eth_hash_filter_info *)arg);
8329 case RTE_ETH_FILTER_SET:
8330 ret = i40e_hash_filter_set(hw,
8331 (struct rte_eth_hash_filter_info *)arg);
8334 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8343 /* Convert ethertype filter structure */
8345 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8346 struct i40e_ethertype_filter *filter)
8348 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8349 filter->input.ether_type = input->ether_type;
8350 filter->flags = input->flags;
8351 filter->queue = input->queue;
8356 /* Check if there exists the ehtertype filter */
8357 struct i40e_ethertype_filter *
8358 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8359 const struct i40e_ethertype_filter_input *input)
8363 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8367 return ethertype_rule->hash_map[ret];
8370 /* Add ethertype filter in SW list */
8372 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8373 struct i40e_ethertype_filter *filter)
8375 struct i40e_ethertype_rule *rule = &pf->ethertype;
8378 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8381 "Failed to insert ethertype filter"
8382 " to hash table %d!",
8386 rule->hash_map[ret] = filter;
8388 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8393 /* Delete ethertype filter in SW list */
8395 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8396 struct i40e_ethertype_filter_input *input)
8398 struct i40e_ethertype_rule *rule = &pf->ethertype;
8399 struct i40e_ethertype_filter *filter;
8402 ret = rte_hash_del_key(rule->hash_table, input);
8405 "Failed to delete ethertype filter"
8406 " to hash table %d!",
8410 filter = rule->hash_map[ret];
8411 rule->hash_map[ret] = NULL;
8413 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8420 * Configure ethertype filter, which can director packet by filtering
8421 * with mac address and ether_type or only ether_type
8424 i40e_ethertype_filter_set(struct i40e_pf *pf,
8425 struct rte_eth_ethertype_filter *filter,
8428 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8429 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8430 struct i40e_ethertype_filter *ethertype_filter, *node;
8431 struct i40e_ethertype_filter check_filter;
8432 struct i40e_control_filter_stats stats;
8436 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8437 PMD_DRV_LOG(ERR, "Invalid queue ID");
8440 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8441 filter->ether_type == ETHER_TYPE_IPv6) {
8442 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8443 " control packet filter.", filter->ether_type);
8446 if (filter->ether_type == ETHER_TYPE_VLAN)
8447 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8450 /* Check if there is the filter in SW list */
8451 memset(&check_filter, 0, sizeof(check_filter));
8452 i40e_ethertype_filter_convert(filter, &check_filter);
8453 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8454 &check_filter.input);
8456 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8460 if (!add && !node) {
8461 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8465 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8466 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8467 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8468 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8469 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8471 memset(&stats, 0, sizeof(stats));
8472 ret = i40e_aq_add_rem_control_packet_filter(hw,
8473 filter->mac_addr.addr_bytes,
8474 filter->ether_type, flags,
8476 filter->queue, add, &stats, NULL);
8478 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8479 " mac_etype_used = %u, etype_used = %u,"
8480 " mac_etype_free = %u, etype_free = %u\n",
8481 ret, stats.mac_etype_used, stats.etype_used,
8482 stats.mac_etype_free, stats.etype_free);
8486 /* Add or delete a filter in SW list */
8488 ethertype_filter = rte_zmalloc("ethertype_filter",
8489 sizeof(*ethertype_filter), 0);
8490 rte_memcpy(ethertype_filter, &check_filter,
8491 sizeof(check_filter));
8492 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8494 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8501 * Handle operations for ethertype filter.
8504 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8505 enum rte_filter_op filter_op,
8508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8511 if (filter_op == RTE_ETH_FILTER_NOP)
8515 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8520 switch (filter_op) {
8521 case RTE_ETH_FILTER_ADD:
8522 ret = i40e_ethertype_filter_set(pf,
8523 (struct rte_eth_ethertype_filter *)arg,
8526 case RTE_ETH_FILTER_DELETE:
8527 ret = i40e_ethertype_filter_set(pf,
8528 (struct rte_eth_ethertype_filter *)arg,
8532 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8540 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8541 enum rte_filter_type filter_type,
8542 enum rte_filter_op filter_op,
8550 switch (filter_type) {
8551 case RTE_ETH_FILTER_NONE:
8552 /* For global configuration */
8553 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8555 case RTE_ETH_FILTER_HASH:
8556 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8558 case RTE_ETH_FILTER_MACVLAN:
8559 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8561 case RTE_ETH_FILTER_ETHERTYPE:
8562 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8564 case RTE_ETH_FILTER_TUNNEL:
8565 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8567 case RTE_ETH_FILTER_FDIR:
8568 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8571 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8581 * Check and enable Extended Tag.
8582 * Enabling Extended Tag is important for 40G performance.
8585 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8587 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8591 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8594 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8598 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8599 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8604 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8607 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8611 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8612 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8615 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8616 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8619 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8626 * As some registers wouldn't be reset unless a global hardware reset,
8627 * hardware initialization is needed to put those registers into an
8628 * expected initial state.
8631 i40e_hw_init(struct rte_eth_dev *dev)
8633 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8635 i40e_enable_extended_tag(dev);
8637 /* clear the PF Queue Filter control register */
8638 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8640 /* Disable symmetric hash per port */
8641 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8644 enum i40e_filter_pctype
8645 i40e_flowtype_to_pctype(uint16_t flow_type)
8647 static const enum i40e_filter_pctype pctype_table[] = {
8648 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8649 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8650 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8651 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8652 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8653 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8654 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8655 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8656 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8657 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8658 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8659 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8660 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8661 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8662 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8663 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8664 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8665 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8666 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8669 return pctype_table[flow_type];
8673 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8675 static const uint16_t flowtype_table[] = {
8676 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8677 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8678 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8679 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8680 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8681 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8682 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8683 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8684 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8685 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8686 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8687 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8688 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8689 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8690 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8691 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8692 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8693 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8694 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8695 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8696 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8697 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8698 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8699 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8700 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8701 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8702 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8703 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8704 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8705 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8706 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8709 return flowtype_table[pctype];
8713 * On X710, performance number is far from the expectation on recent firmware
8714 * versions; on XL710, performance number is also far from the expectation on
8715 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8716 * mode is enabled and port MAC address is equal to the packet destination MAC
8717 * address. The fix for this issue may not be integrated in the following
8718 * firmware version. So the workaround in software driver is needed. It needs
8719 * to modify the initial values of 3 internal only registers for both X710 and
8720 * XL710. Note that the values for X710 or XL710 could be different, and the
8721 * workaround can be removed when it is fixed in firmware in the future.
8724 /* For both X710 and XL710 */
8725 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8726 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8728 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8729 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8732 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8734 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8735 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8738 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8740 enum i40e_status_code status;
8741 struct i40e_aq_get_phy_abilities_resp phy_ab;
8744 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8755 i40e_configure_registers(struct i40e_hw *hw)
8761 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8762 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8763 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8769 for (i = 0; i < RTE_DIM(reg_table); i++) {
8770 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8771 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8772 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8774 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8777 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8780 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8783 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8787 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8788 reg_table[i].addr, reg);
8789 if (reg == reg_table[i].val)
8792 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8793 reg_table[i].val, NULL);
8795 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8796 "address of 0x%"PRIx32, reg_table[i].val,
8800 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8801 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8805 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8806 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8807 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8808 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8810 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8815 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8816 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8820 /* Configure for double VLAN RX stripping */
8821 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8822 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8823 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8824 ret = i40e_aq_debug_write_register(hw,
8825 I40E_VSI_TSR(vsi->vsi_id),
8828 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8830 return I40E_ERR_CONFIG;
8834 /* Configure for double VLAN TX insertion */
8835 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8836 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8837 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8838 ret = i40e_aq_debug_write_register(hw,
8839 I40E_VSI_L2TAGSTXVALID(
8840 vsi->vsi_id), reg, NULL);
8842 PMD_DRV_LOG(ERR, "Failed to update "
8843 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8844 return I40E_ERR_CONFIG;
8852 * i40e_aq_add_mirror_rule
8853 * @hw: pointer to the hardware structure
8854 * @seid: VEB seid to add mirror rule to
8855 * @dst_id: destination vsi seid
8856 * @entries: Buffer which contains the entities to be mirrored
8857 * @count: number of entities contained in the buffer
8858 * @rule_id:the rule_id of the rule to be added
8860 * Add a mirror rule for a given veb.
8863 static enum i40e_status_code
8864 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8865 uint16_t seid, uint16_t dst_id,
8866 uint16_t rule_type, uint16_t *entries,
8867 uint16_t count, uint16_t *rule_id)
8869 struct i40e_aq_desc desc;
8870 struct i40e_aqc_add_delete_mirror_rule cmd;
8871 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8872 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8875 enum i40e_status_code status;
8877 i40e_fill_default_direct_cmd_desc(&desc,
8878 i40e_aqc_opc_add_mirror_rule);
8879 memset(&cmd, 0, sizeof(cmd));
8881 buff_len = sizeof(uint16_t) * count;
8882 desc.datalen = rte_cpu_to_le_16(buff_len);
8884 desc.flags |= rte_cpu_to_le_16(
8885 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8886 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8887 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8888 cmd.num_entries = rte_cpu_to_le_16(count);
8889 cmd.seid = rte_cpu_to_le_16(seid);
8890 cmd.destination = rte_cpu_to_le_16(dst_id);
8892 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8893 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8894 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8896 " mirror_rules_used = %u, mirror_rules_free = %u,",
8897 hw->aq.asq_last_status, resp->rule_id,
8898 resp->mirror_rules_used, resp->mirror_rules_free);
8899 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8905 * i40e_aq_del_mirror_rule
8906 * @hw: pointer to the hardware structure
8907 * @seid: VEB seid to add mirror rule to
8908 * @entries: Buffer which contains the entities to be mirrored
8909 * @count: number of entities contained in the buffer
8910 * @rule_id:the rule_id of the rule to be delete
8912 * Delete a mirror rule for a given veb.
8915 static enum i40e_status_code
8916 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8917 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8918 uint16_t count, uint16_t rule_id)
8920 struct i40e_aq_desc desc;
8921 struct i40e_aqc_add_delete_mirror_rule cmd;
8922 uint16_t buff_len = 0;
8923 enum i40e_status_code status;
8926 i40e_fill_default_direct_cmd_desc(&desc,
8927 i40e_aqc_opc_delete_mirror_rule);
8928 memset(&cmd, 0, sizeof(cmd));
8929 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8930 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8932 cmd.num_entries = count;
8933 buff_len = sizeof(uint16_t) * count;
8934 desc.datalen = rte_cpu_to_le_16(buff_len);
8935 buff = (void *)entries;
8937 /* rule id is filled in destination field for deleting mirror rule */
8938 cmd.destination = rte_cpu_to_le_16(rule_id);
8940 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8941 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8942 cmd.seid = rte_cpu_to_le_16(seid);
8944 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8945 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8951 * i40e_mirror_rule_set
8952 * @dev: pointer to the hardware structure
8953 * @mirror_conf: mirror rule info
8954 * @sw_id: mirror rule's sw_id
8955 * @on: enable/disable
8957 * set a mirror rule.
8961 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8962 struct rte_eth_mirror_conf *mirror_conf,
8963 uint8_t sw_id, uint8_t on)
8965 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8966 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8967 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8968 struct i40e_mirror_rule *parent = NULL;
8969 uint16_t seid, dst_seid, rule_id;
8973 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8975 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8976 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8977 " without veb or vfs.");
8980 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8981 PMD_DRV_LOG(ERR, "mirror table is full.");
8984 if (mirror_conf->dst_pool > pf->vf_num) {
8985 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8986 mirror_conf->dst_pool);
8990 seid = pf->main_vsi->veb->seid;
8992 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8993 if (sw_id <= it->index) {
8999 if (mirr_rule && sw_id == mirr_rule->index) {
9001 PMD_DRV_LOG(ERR, "mirror rule exists.");
9004 ret = i40e_aq_del_mirror_rule(hw, seid,
9005 mirr_rule->rule_type,
9007 mirr_rule->num_entries, mirr_rule->id);
9009 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9010 " ret = %d, aq_err = %d.",
9011 ret, hw->aq.asq_last_status);
9014 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9015 rte_free(mirr_rule);
9016 pf->nb_mirror_rule--;
9020 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9024 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9025 sizeof(struct i40e_mirror_rule) , 0);
9027 PMD_DRV_LOG(ERR, "failed to allocate memory");
9028 return I40E_ERR_NO_MEMORY;
9030 switch (mirror_conf->rule_type) {
9031 case ETH_MIRROR_VLAN:
9032 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9033 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9034 mirr_rule->entries[j] =
9035 mirror_conf->vlan.vlan_id[i];
9040 PMD_DRV_LOG(ERR, "vlan is not specified.");
9041 rte_free(mirr_rule);
9044 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9046 case ETH_MIRROR_VIRTUAL_POOL_UP:
9047 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9048 /* check if the specified pool bit is out of range */
9049 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9050 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9051 rte_free(mirr_rule);
9054 for (i = 0, j = 0; i < pf->vf_num; i++) {
9055 if (mirror_conf->pool_mask & (1ULL << i)) {
9056 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9060 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9061 /* add pf vsi to entries */
9062 mirr_rule->entries[j] = pf->main_vsi_seid;
9066 PMD_DRV_LOG(ERR, "pool is not specified.");
9067 rte_free(mirr_rule);
9070 /* egress and ingress in aq commands means from switch but not port */
9071 mirr_rule->rule_type =
9072 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9073 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9074 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9076 case ETH_MIRROR_UPLINK_PORT:
9077 /* egress and ingress in aq commands means from switch but not port*/
9078 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9080 case ETH_MIRROR_DOWNLINK_PORT:
9081 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9084 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9085 mirror_conf->rule_type);
9086 rte_free(mirr_rule);
9090 /* If the dst_pool is equal to vf_num, consider it as PF */
9091 if (mirror_conf->dst_pool == pf->vf_num)
9092 dst_seid = pf->main_vsi_seid;
9094 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9096 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9097 mirr_rule->rule_type, mirr_rule->entries,
9100 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
9101 " ret = %d, aq_err = %d.",
9102 ret, hw->aq.asq_last_status);
9103 rte_free(mirr_rule);
9107 mirr_rule->index = sw_id;
9108 mirr_rule->num_entries = j;
9109 mirr_rule->id = rule_id;
9110 mirr_rule->dst_vsi_seid = dst_seid;
9113 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9115 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9117 pf->nb_mirror_rule++;
9122 * i40e_mirror_rule_reset
9123 * @dev: pointer to the device
9124 * @sw_id: mirror rule's sw_id
9126 * reset a mirror rule.
9130 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9132 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9133 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9134 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9138 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9140 seid = pf->main_vsi->veb->seid;
9142 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9143 if (sw_id == it->index) {
9149 ret = i40e_aq_del_mirror_rule(hw, seid,
9150 mirr_rule->rule_type,
9152 mirr_rule->num_entries, mirr_rule->id);
9154 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9155 " status = %d, aq_err = %d.",
9156 ret, hw->aq.asq_last_status);
9159 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9160 rte_free(mirr_rule);
9161 pf->nb_mirror_rule--;
9163 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9170 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9172 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9173 uint64_t systim_cycles;
9175 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9176 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9179 return systim_cycles;
9183 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9185 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9188 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9189 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9196 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9198 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9201 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9202 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9209 i40e_start_timecounters(struct rte_eth_dev *dev)
9211 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9212 struct i40e_adapter *adapter =
9213 (struct i40e_adapter *)dev->data->dev_private;
9214 struct rte_eth_link link;
9215 uint32_t tsync_inc_l;
9216 uint32_t tsync_inc_h;
9218 /* Get current link speed. */
9219 memset(&link, 0, sizeof(link));
9220 i40e_dev_link_update(dev, 1);
9221 rte_i40e_dev_atomic_read_link_status(dev, &link);
9223 switch (link.link_speed) {
9224 case ETH_SPEED_NUM_40G:
9225 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9226 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9228 case ETH_SPEED_NUM_10G:
9229 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9230 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9232 case ETH_SPEED_NUM_1G:
9233 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9234 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9241 /* Set the timesync increment value. */
9242 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9243 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9245 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9246 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9247 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9249 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9250 adapter->systime_tc.cc_shift = 0;
9251 adapter->systime_tc.nsec_mask = 0;
9253 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9254 adapter->rx_tstamp_tc.cc_shift = 0;
9255 adapter->rx_tstamp_tc.nsec_mask = 0;
9257 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9258 adapter->tx_tstamp_tc.cc_shift = 0;
9259 adapter->tx_tstamp_tc.nsec_mask = 0;
9263 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9265 struct i40e_adapter *adapter =
9266 (struct i40e_adapter *)dev->data->dev_private;
9268 adapter->systime_tc.nsec += delta;
9269 adapter->rx_tstamp_tc.nsec += delta;
9270 adapter->tx_tstamp_tc.nsec += delta;
9276 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9279 struct i40e_adapter *adapter =
9280 (struct i40e_adapter *)dev->data->dev_private;
9282 ns = rte_timespec_to_ns(ts);
9284 /* Set the timecounters to a new value. */
9285 adapter->systime_tc.nsec = ns;
9286 adapter->rx_tstamp_tc.nsec = ns;
9287 adapter->tx_tstamp_tc.nsec = ns;
9293 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9295 uint64_t ns, systime_cycles;
9296 struct i40e_adapter *adapter =
9297 (struct i40e_adapter *)dev->data->dev_private;
9299 systime_cycles = i40e_read_systime_cyclecounter(dev);
9300 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9301 *ts = rte_ns_to_timespec(ns);
9307 i40e_timesync_enable(struct rte_eth_dev *dev)
9309 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9310 uint32_t tsync_ctl_l;
9311 uint32_t tsync_ctl_h;
9313 /* Stop the timesync system time. */
9314 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9315 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9316 /* Reset the timesync system time value. */
9317 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9318 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9320 i40e_start_timecounters(dev);
9322 /* Clear timesync registers. */
9323 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9324 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9325 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9326 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9327 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9328 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9330 /* Enable timestamping of PTP packets. */
9331 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9332 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9334 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9335 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9336 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9338 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9339 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9345 i40e_timesync_disable(struct rte_eth_dev *dev)
9347 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9348 uint32_t tsync_ctl_l;
9349 uint32_t tsync_ctl_h;
9351 /* Disable timestamping of transmitted PTP packets. */
9352 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9353 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9355 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9356 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9358 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9359 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9361 /* Reset the timesync increment value. */
9362 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9363 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9369 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9370 struct timespec *timestamp, uint32_t flags)
9372 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9373 struct i40e_adapter *adapter =
9374 (struct i40e_adapter *)dev->data->dev_private;
9376 uint32_t sync_status;
9377 uint32_t index = flags & 0x03;
9378 uint64_t rx_tstamp_cycles;
9381 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9382 if ((sync_status & (1 << index)) == 0)
9385 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9386 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9387 *timestamp = rte_ns_to_timespec(ns);
9393 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9394 struct timespec *timestamp)
9396 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9397 struct i40e_adapter *adapter =
9398 (struct i40e_adapter *)dev->data->dev_private;
9400 uint32_t sync_status;
9401 uint64_t tx_tstamp_cycles;
9404 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9405 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9408 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9409 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9410 *timestamp = rte_ns_to_timespec(ns);
9416 * i40e_parse_dcb_configure - parse dcb configure from user
9417 * @dev: the device being configured
9418 * @dcb_cfg: pointer of the result of parse
9419 * @*tc_map: bit map of enabled traffic classes
9421 * Returns 0 on success, negative value on failure
9424 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9425 struct i40e_dcbx_config *dcb_cfg,
9428 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9429 uint8_t i, tc_bw, bw_lf;
9431 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9433 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9434 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9435 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9439 /* assume each tc has the same bw */
9440 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9441 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9442 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9443 /* to ensure the sum of tcbw is equal to 100 */
9444 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9445 for (i = 0; i < bw_lf; i++)
9446 dcb_cfg->etscfg.tcbwtable[i]++;
9448 /* assume each tc has the same Transmission Selection Algorithm */
9449 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9450 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9452 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9453 dcb_cfg->etscfg.prioritytable[i] =
9454 dcb_rx_conf->dcb_tc[i];
9456 /* FW needs one App to configure HW */
9457 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9458 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9459 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9460 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9462 if (dcb_rx_conf->nb_tcs == 0)
9463 *tc_map = 1; /* tc0 only */
9465 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9467 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9468 dcb_cfg->pfc.willing = 0;
9469 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9470 dcb_cfg->pfc.pfcenable = *tc_map;
9476 static enum i40e_status_code
9477 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9478 struct i40e_aqc_vsi_properties_data *info,
9479 uint8_t enabled_tcmap)
9481 enum i40e_status_code ret;
9482 int i, total_tc = 0;
9483 uint16_t qpnum_per_tc, bsf, qp_idx;
9484 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9485 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9486 uint16_t used_queues;
9488 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9489 if (ret != I40E_SUCCESS)
9492 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9493 if (enabled_tcmap & (1 << i))
9498 vsi->enabled_tc = enabled_tcmap;
9500 /* different VSI has different queues assigned */
9501 if (vsi->type == I40E_VSI_MAIN)
9502 used_queues = dev_data->nb_rx_queues -
9503 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9504 else if (vsi->type == I40E_VSI_VMDQ2)
9505 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9507 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9508 return I40E_ERR_NO_AVAILABLE_VSI;
9511 qpnum_per_tc = used_queues / total_tc;
9512 /* Number of queues per enabled TC */
9513 if (qpnum_per_tc == 0) {
9514 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9515 return I40E_ERR_INVALID_QP_ID;
9517 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9519 bsf = rte_bsf32(qpnum_per_tc);
9522 * Configure TC and queue mapping parameters, for enabled TC,
9523 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9524 * default queue will serve it.
9527 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9528 if (vsi->enabled_tc & (1 << i)) {
9529 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9530 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9531 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9532 qp_idx += qpnum_per_tc;
9534 info->tc_mapping[i] = 0;
9537 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9538 if (vsi->type == I40E_VSI_SRIOV) {
9539 info->mapping_flags |=
9540 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9541 for (i = 0; i < vsi->nb_qps; i++)
9542 info->queue_mapping[i] =
9543 rte_cpu_to_le_16(vsi->base_queue + i);
9545 info->mapping_flags |=
9546 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9547 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9549 info->valid_sections |=
9550 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9552 return I40E_SUCCESS;
9556 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9557 * @veb: VEB to be configured
9558 * @tc_map: enabled TC bitmap
9560 * Returns 0 on success, negative value on failure
9562 static enum i40e_status_code
9563 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9565 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9566 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9567 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9568 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9569 enum i40e_status_code ret = I40E_SUCCESS;
9573 /* Check if enabled_tc is same as existing or new TCs */
9574 if (veb->enabled_tc == tc_map)
9577 /* configure tc bandwidth */
9578 memset(&veb_bw, 0, sizeof(veb_bw));
9579 veb_bw.tc_valid_bits = tc_map;
9580 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9581 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9582 if (tc_map & BIT_ULL(i))
9583 veb_bw.tc_bw_share_credits[i] = 1;
9585 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9588 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9589 " per TC failed = %d",
9590 hw->aq.asq_last_status);
9594 memset(&ets_query, 0, sizeof(ets_query));
9595 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9597 if (ret != I40E_SUCCESS) {
9598 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9599 " configuration %u", hw->aq.asq_last_status);
9602 memset(&bw_query, 0, sizeof(bw_query));
9603 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9605 if (ret != I40E_SUCCESS) {
9606 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9607 " configuration %u", hw->aq.asq_last_status);
9611 /* store and print out BW info */
9612 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9613 veb->bw_info.bw_max = ets_query.tc_bw_max;
9614 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9615 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9616 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9617 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9619 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9620 veb->bw_info.bw_ets_share_credits[i] =
9621 bw_query.tc_bw_share_credits[i];
9622 veb->bw_info.bw_ets_credits[i] =
9623 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9624 /* 4 bits per TC, 4th bit is reserved */
9625 veb->bw_info.bw_ets_max[i] =
9626 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9627 RTE_LEN2MASK(3, uint8_t));
9628 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9629 veb->bw_info.bw_ets_share_credits[i]);
9630 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9631 veb->bw_info.bw_ets_credits[i]);
9632 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9633 veb->bw_info.bw_ets_max[i]);
9636 veb->enabled_tc = tc_map;
9643 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9644 * @vsi: VSI to be configured
9645 * @tc_map: enabled TC bitmap
9647 * Returns 0 on success, negative value on failure
9649 static enum i40e_status_code
9650 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9652 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9653 struct i40e_vsi_context ctxt;
9654 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9655 enum i40e_status_code ret = I40E_SUCCESS;
9658 /* Check if enabled_tc is same as existing or new TCs */
9659 if (vsi->enabled_tc == tc_map)
9662 /* configure tc bandwidth */
9663 memset(&bw_data, 0, sizeof(bw_data));
9664 bw_data.tc_valid_bits = tc_map;
9665 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9666 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9667 if (tc_map & BIT_ULL(i))
9668 bw_data.tc_bw_credits[i] = 1;
9670 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9672 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9673 " per TC failed = %d",
9674 hw->aq.asq_last_status);
9677 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9678 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9680 /* Update Queue Pairs Mapping for currently enabled UPs */
9681 ctxt.seid = vsi->seid;
9682 ctxt.pf_num = hw->pf_id;
9684 ctxt.uplink_seid = vsi->uplink_seid;
9685 ctxt.info = vsi->info;
9687 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9691 /* Update the VSI after updating the VSI queue-mapping information */
9692 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9694 PMD_INIT_LOG(ERR, "Failed to configure "
9695 "TC queue mapping = %d",
9696 hw->aq.asq_last_status);
9699 /* update the local VSI info with updated queue map */
9700 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9701 sizeof(vsi->info.tc_mapping));
9702 (void)rte_memcpy(&vsi->info.queue_mapping,
9703 &ctxt.info.queue_mapping,
9704 sizeof(vsi->info.queue_mapping));
9705 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9706 vsi->info.valid_sections = 0;
9708 /* query and update current VSI BW information */
9709 ret = i40e_vsi_get_bw_config(vsi);
9712 "Failed updating vsi bw info, err %s aq_err %s",
9713 i40e_stat_str(hw, ret),
9714 i40e_aq_str(hw, hw->aq.asq_last_status));
9718 vsi->enabled_tc = tc_map;
9725 * i40e_dcb_hw_configure - program the dcb setting to hw
9726 * @pf: pf the configuration is taken on
9727 * @new_cfg: new configuration
9728 * @tc_map: enabled TC bitmap
9730 * Returns 0 on success, negative value on failure
9732 static enum i40e_status_code
9733 i40e_dcb_hw_configure(struct i40e_pf *pf,
9734 struct i40e_dcbx_config *new_cfg,
9737 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9738 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9739 struct i40e_vsi *main_vsi = pf->main_vsi;
9740 struct i40e_vsi_list *vsi_list;
9741 enum i40e_status_code ret;
9745 /* Use the FW API if FW > v4.4*/
9746 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9747 (hw->aq.fw_maj_ver >= 5))) {
9748 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9749 " to configure DCB");
9750 return I40E_ERR_FIRMWARE_API_VERSION;
9753 /* Check if need reconfiguration */
9754 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9755 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9756 return I40E_SUCCESS;
9759 /* Copy the new config to the current config */
9760 *old_cfg = *new_cfg;
9761 old_cfg->etsrec = old_cfg->etscfg;
9762 ret = i40e_set_dcb_config(hw);
9765 "Set DCB Config failed, err %s aq_err %s\n",
9766 i40e_stat_str(hw, ret),
9767 i40e_aq_str(hw, hw->aq.asq_last_status));
9770 /* set receive Arbiter to RR mode and ETS scheme by default */
9771 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9772 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9773 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9774 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9775 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9776 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9777 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9778 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9779 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9780 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9781 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9782 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9783 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9785 /* get local mib to check whether it is configured correctly */
9787 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9788 /* Get Local DCB Config */
9789 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9790 &hw->local_dcbx_config);
9792 /* if Veb is created, need to update TC of it at first */
9793 if (main_vsi->veb) {
9794 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9796 PMD_INIT_LOG(WARNING,
9797 "Failed configuring TC for VEB seid=%d\n",
9798 main_vsi->veb->seid);
9800 /* Update each VSI */
9801 i40e_vsi_config_tc(main_vsi, tc_map);
9802 if (main_vsi->veb) {
9803 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9804 /* Beside main VSI and VMDQ VSIs, only enable default
9807 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9808 ret = i40e_vsi_config_tc(vsi_list->vsi,
9811 ret = i40e_vsi_config_tc(vsi_list->vsi,
9812 I40E_DEFAULT_TCMAP);
9814 PMD_INIT_LOG(WARNING,
9815 "Failed configuring TC for VSI seid=%d\n",
9816 vsi_list->vsi->seid);
9820 return I40E_SUCCESS;
9824 * i40e_dcb_init_configure - initial dcb config
9825 * @dev: device being configured
9826 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9828 * Returns 0 on success, negative value on failure
9831 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9833 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9834 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9837 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9838 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9842 /* DCB initialization:
9843 * Update DCB configuration from the Firmware and configure
9844 * LLDP MIB change event.
9846 if (sw_dcb == TRUE) {
9847 ret = i40e_init_dcb(hw);
9848 /* If lldp agent is stopped, the return value from
9849 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9850 * adminq status. Otherwise, it should return success.
9852 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9853 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9854 memset(&hw->local_dcbx_config, 0,
9855 sizeof(struct i40e_dcbx_config));
9856 /* set dcb default configuration */
9857 hw->local_dcbx_config.etscfg.willing = 0;
9858 hw->local_dcbx_config.etscfg.maxtcs = 0;
9859 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9860 hw->local_dcbx_config.etscfg.tsatable[0] =
9862 hw->local_dcbx_config.etsrec =
9863 hw->local_dcbx_config.etscfg;
9864 hw->local_dcbx_config.pfc.willing = 0;
9865 hw->local_dcbx_config.pfc.pfccap =
9866 I40E_MAX_TRAFFIC_CLASS;
9867 /* FW needs one App to configure HW */
9868 hw->local_dcbx_config.numapps = 1;
9869 hw->local_dcbx_config.app[0].selector =
9870 I40E_APP_SEL_ETHTYPE;
9871 hw->local_dcbx_config.app[0].priority = 3;
9872 hw->local_dcbx_config.app[0].protocolid =
9873 I40E_APP_PROTOID_FCOE;
9874 ret = i40e_set_dcb_config(hw);
9876 PMD_INIT_LOG(ERR, "default dcb config fails."
9877 " err = %d, aq_err = %d.", ret,
9878 hw->aq.asq_last_status);
9882 PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9883 " err = %d, aq_err = %d.", ret,
9884 hw->aq.asq_last_status);
9888 ret = i40e_aq_start_lldp(hw, NULL);
9889 if (ret != I40E_SUCCESS)
9890 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9892 ret = i40e_init_dcb(hw);
9894 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9895 PMD_INIT_LOG(ERR, "HW doesn't support"
9900 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9901 " aq_err = %d.", ret,
9902 hw->aq.asq_last_status);
9910 * i40e_dcb_setup - setup dcb related config
9911 * @dev: device being configured
9913 * Returns 0 on success, negative value on failure
9916 i40e_dcb_setup(struct rte_eth_dev *dev)
9918 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9919 struct i40e_dcbx_config dcb_cfg;
9923 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9924 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9928 if (pf->vf_num != 0)
9929 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9931 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9933 PMD_INIT_LOG(ERR, "invalid dcb config");
9936 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9938 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9946 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9947 struct rte_eth_dcb_info *dcb_info)
9949 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9950 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9951 struct i40e_vsi *vsi = pf->main_vsi;
9952 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9953 uint16_t bsf, tc_mapping;
9956 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9957 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9959 dcb_info->nb_tcs = 1;
9960 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9961 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9962 for (i = 0; i < dcb_info->nb_tcs; i++)
9963 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9965 /* get queue mapping if vmdq is disabled */
9966 if (!pf->nb_cfg_vmdq_vsi) {
9967 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9968 if (!(vsi->enabled_tc & (1 << i)))
9970 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9971 dcb_info->tc_queue.tc_rxq[j][i].base =
9972 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9973 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9974 dcb_info->tc_queue.tc_txq[j][i].base =
9975 dcb_info->tc_queue.tc_rxq[j][i].base;
9976 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9977 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9978 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9979 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9980 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9985 /* get queue mapping if vmdq is enabled */
9987 vsi = pf->vmdq[j].vsi;
9988 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9989 if (!(vsi->enabled_tc & (1 << i)))
9991 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9992 dcb_info->tc_queue.tc_rxq[j][i].base =
9993 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9994 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9995 dcb_info->tc_queue.tc_txq[j][i].base =
9996 dcb_info->tc_queue.tc_rxq[j][i].base;
9997 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9998 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9999 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10000 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10001 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10004 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10009 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10011 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10012 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10013 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10014 uint16_t interval =
10015 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10016 uint16_t msix_intr;
10018 msix_intr = intr_handle->intr_vec[queue_id];
10019 if (msix_intr == I40E_MISC_VEC_ID)
10020 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10021 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10022 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10023 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10025 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10028 I40E_PFINT_DYN_CTLN(msix_intr -
10029 I40E_RX_VEC_START),
10030 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10031 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10032 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10034 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10036 I40E_WRITE_FLUSH(hw);
10037 rte_intr_enable(&pci_dev->intr_handle);
10043 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10045 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10046 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10047 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10048 uint16_t msix_intr;
10050 msix_intr = intr_handle->intr_vec[queue_id];
10051 if (msix_intr == I40E_MISC_VEC_ID)
10052 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10055 I40E_PFINT_DYN_CTLN(msix_intr -
10056 I40E_RX_VEC_START),
10058 I40E_WRITE_FLUSH(hw);
10063 static int i40e_get_regs(struct rte_eth_dev *dev,
10064 struct rte_dev_reg_info *regs)
10066 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10067 uint32_t *ptr_data = regs->data;
10068 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10069 const struct i40e_reg_info *reg_info;
10071 if (ptr_data == NULL) {
10072 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10073 regs->width = sizeof(uint32_t);
10077 /* The first few registers have to be read using AQ operations */
10079 while (i40e_regs_adminq[reg_idx].name) {
10080 reg_info = &i40e_regs_adminq[reg_idx++];
10081 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10083 arr_idx2 <= reg_info->count2;
10085 reg_offset = arr_idx * reg_info->stride1 +
10086 arr_idx2 * reg_info->stride2;
10087 reg_offset += reg_info->base_addr;
10088 ptr_data[reg_offset >> 2] =
10089 i40e_read_rx_ctl(hw, reg_offset);
10093 /* The remaining registers can be read using primitives */
10095 while (i40e_regs_others[reg_idx].name) {
10096 reg_info = &i40e_regs_others[reg_idx++];
10097 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10099 arr_idx2 <= reg_info->count2;
10101 reg_offset = arr_idx * reg_info->stride1 +
10102 arr_idx2 * reg_info->stride2;
10103 reg_offset += reg_info->base_addr;
10104 ptr_data[reg_offset >> 2] =
10105 I40E_READ_REG(hw, reg_offset);
10112 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10114 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10116 /* Convert word count to byte count */
10117 return hw->nvm.sr_size << 1;
10120 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10121 struct rte_dev_eeprom_info *eeprom)
10123 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10124 uint16_t *data = eeprom->data;
10125 uint16_t offset, length, cnt_words;
10128 offset = eeprom->offset >> 1;
10129 length = eeprom->length >> 1;
10130 cnt_words = length;
10132 if (offset > hw->nvm.sr_size ||
10133 offset + length > hw->nvm.sr_size) {
10134 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10138 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10140 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10141 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10142 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10149 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10150 struct ether_addr *mac_addr)
10152 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10154 if (!is_valid_assigned_ether_addr(mac_addr)) {
10155 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10159 /* Flags: 0x3 updates port address */
10160 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10164 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10166 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10167 struct rte_eth_dev_data *dev_data = pf->dev_data;
10168 uint32_t frame_size = mtu + ETHER_HDR_LEN
10169 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10172 /* check if mtu is within the allowed range */
10173 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10176 /* mtu setting is forbidden if port is start */
10177 if (dev_data->dev_started) {
10179 "port %d must be stopped before configuration\n",
10180 dev_data->port_id);
10184 if (frame_size > ETHER_MAX_LEN)
10185 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10187 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10189 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;