drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 415 static void i40e_configure_registers(struct i40e_hw *hw);
 416 static void i40e_hw_init(struct rte_eth_dev *dev);
 417 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 418 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 419                         struct rte_eth_mirror_conf *mirror_conf,
 420                         uint8_t sw_id, uint8_t on);
 421 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 422
 423 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 425 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 426                                            struct timespec *timestamp,
 427                                            uint32_t flags);
 428 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 429                                            struct timespec *timestamp);
 430 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 431
 432 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 433
 434 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 435                                    struct timespec *timestamp);
 436 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 437                                     const struct timespec *timestamp);
 438
 439 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 440                                          uint16_t queue_id);
 441 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 442                                           uint16_t queue_id);
 443
 444 static int i40e_get_regs(struct rte_eth_dev *dev,
 445                          struct rte_dev_reg_info *regs);
 446
 447 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 448
 449 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 450                            struct rte_dev_eeprom_info *eeprom);
 451
 452 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 453                                       struct ether_addr *mac_addr);
 454
 455 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 456
 457 static const struct rte_pci_id pci_id_i40e_map[] = {
 458         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 459         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 460         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 461         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 462         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 463         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 464         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct eth_dev_ops i40e_eth_dev_ops = {
 482         .dev_configure                = i40e_dev_configure,
 483         .dev_start                    = i40e_dev_start,
 484         .dev_stop                     = i40e_dev_stop,
 485         .dev_close                    = i40e_dev_close,
 486         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 487         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 488         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 489         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 490         .dev_set_link_up              = i40e_dev_set_link_up,
 491         .dev_set_link_down            = i40e_dev_set_link_down,
 492         .link_update                  = i40e_dev_link_update,
 493         .stats_get                    = i40e_dev_stats_get,
 494         .xstats_get                   = i40e_dev_xstats_get,
 495         .xstats_get_names             = i40e_dev_xstats_get_names,
 496         .stats_reset                  = i40e_dev_stats_reset,
 497         .xstats_reset                 = i40e_dev_stats_reset,
 498         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 499         .dev_infos_get                = i40e_dev_info_get,
 500         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 501         .vlan_filter_set              = i40e_vlan_filter_set,
 502         .vlan_tpid_set                = i40e_vlan_tpid_set,
 503         .vlan_offload_set             = i40e_vlan_offload_set,
 504         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 505         .vlan_pvid_set                = i40e_vlan_pvid_set,
 506         .rx_queue_start               = i40e_dev_rx_queue_start,
 507         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 508         .tx_queue_start               = i40e_dev_tx_queue_start,
 509         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 510         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 511         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 512         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 513         .rx_queue_release             = i40e_dev_rx_queue_release,
 514         .rx_queue_count               = i40e_dev_rx_queue_count,
 515         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 516         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 517         .tx_queue_release             = i40e_dev_tx_queue_release,
 518         .dev_led_on                   = i40e_dev_led_on,
 519         .dev_led_off                  = i40e_dev_led_off,
 520         .flow_ctrl_get                = i40e_flow_ctrl_get,
 521         .flow_ctrl_set                = i40e_flow_ctrl_set,
 522         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 523         .mac_addr_add                 = i40e_macaddr_add,
 524         .mac_addr_remove              = i40e_macaddr_remove,
 525         .reta_update                  = i40e_dev_rss_reta_update,
 526         .reta_query                   = i40e_dev_rss_reta_query,
 527         .rss_hash_update              = i40e_dev_rss_hash_update,
 528         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 529         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 530         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 531         .filter_ctrl                  = i40e_dev_filter_ctrl,
 532         .rxq_info_get                 = i40e_rxq_info_get,
 533         .txq_info_get                 = i40e_txq_info_get,
 534         .mirror_rule_set              = i40e_mirror_rule_set,
 535         .mirror_rule_reset            = i40e_mirror_rule_reset,
 536         .timesync_enable              = i40e_timesync_enable,
 537         .timesync_disable             = i40e_timesync_disable,
 538         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 539         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 540         .get_dcb_info                 = i40e_dev_get_dcb_info,
 541         .timesync_adjust_time         = i40e_timesync_adjust_time,
 542         .timesync_read_time           = i40e_timesync_read_time,
 543         .timesync_write_time          = i40e_timesync_write_time,
 544         .get_reg                      = i40e_get_regs,
 545         .get_eeprom_length            = i40e_get_eeprom_length,
 546         .get_eeprom                   = i40e_get_eeprom,
 547         .mac_addr_set                 = i40e_set_default_mac_addr,
 548         .mtu_set                      = i40e_dev_mtu_set,
 549 };
 550
 551 /* store statistics names and its offset in stats structure */
 552 struct rte_i40e_xstats_name_off {
 553         char name[RTE_ETH_XSTATS_NAME_SIZE];
 554         unsigned offset;
 555 };
 556
 557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 558         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 559         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 560         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 561         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 562         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 563                 rx_unknown_protocol)},
 564         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 565         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 566         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 567         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 568 };
 569
 570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 571                 sizeof(rte_i40e_stats_strings[0]))
 572
 573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 574         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 575                 tx_dropped_link_down)},
 576         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 577         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 578                 illegal_bytes)},
 579         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 580         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 581                 mac_local_faults)},
 582         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 583                 mac_remote_faults)},
 584         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_length_errors)},
 586         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 587         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 588         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 589         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 590         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 591         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 592                 rx_size_127)},
 593         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 594                 rx_size_255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 596                 rx_size_511)},
 597         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 598                 rx_size_1023)},
 599         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 600                 rx_size_1522)},
 601         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 602                 rx_size_big)},
 603         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 604                 rx_undersize)},
 605         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 606                 rx_oversize)},
 607         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 608                 mac_short_packet_dropped)},
 609         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 610                 rx_fragments)},
 611         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 612         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 614                 tx_size_127)},
 615         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 616                 tx_size_255)},
 617         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 618                 tx_size_511)},
 619         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 620                 tx_size_1023)},
 621         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 622                 tx_size_1522)},
 623         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 624                 tx_size_big)},
 625         {"rx_flow_director_atr_match_packets",
 626                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 627         {"rx_flow_director_sb_match_packets",
 628                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 629         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 630                 tx_lpi_status)},
 631         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 632                 rx_lpi_status)},
 633         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 634                 tx_lpi_count)},
 635         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 636                 rx_lpi_count)},
 637 };
 638
 639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 640                 sizeof(rte_i40e_hw_port_strings[0]))
 641
 642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 643         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 644                 priority_xon_rx)},
 645         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 646                 priority_xoff_rx)},
 647 };
 648
 649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 650                 sizeof(rte_i40e_rxq_prio_strings[0]))
 651
 652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 653         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 654                 priority_xon_tx)},
 655         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 656                 priority_xoff_tx)},
 657         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_2_xoff)},
 659 };
 660
 661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 662                 sizeof(rte_i40e_txq_prio_strings[0]))
 663
 664 static struct eth_driver rte_i40e_pmd = {
 665         .pci_drv = {
 666                 .id_table = pci_id_i40e_map,
 667                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 668                         RTE_PCI_DRV_DETACHABLE,
 669                 .probe = rte_eth_dev_pci_probe,
 670                 .remove = rte_eth_dev_pci_remove,
 671         },
 672         .eth_dev_init = eth_i40e_dev_init,
 673         .eth_dev_uninit = eth_i40e_dev_uninit,
 674         .dev_private_size = sizeof(struct i40e_adapter),
 675 };
 676
 677 static inline int
 678 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 679                                      struct rte_eth_link *link)
 680 {
 681         struct rte_eth_link *dst = link;
 682         struct rte_eth_link *src = &(dev->data->dev_link);
 683
 684         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 685                                         *(uint64_t *)src) == 0)
 686                 return -1;
 687
 688         return 0;
 689 }
 690
 691 static inline int
 692 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 693                                       struct rte_eth_link *link)
 694 {
 695         struct rte_eth_link *dst = &(dev->data->dev_link);
 696         struct rte_eth_link *src = link;
 697
 698         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 699                                         *(uint64_t *)src) == 0)
 700                 return -1;
 701
 702         return 0;
 703 }
 704
 705 DRIVER_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 706 DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 707
 708 #ifndef I40E_GLQF_ORT
 709 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 710 #endif
 711 #ifndef I40E_GLQF_PIT
 712 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 713 #endif
 714
 715 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 716 {
 717         /*
 718          * Initialize registers for flexible payload, which should be set by NVM.
 719          * This should be removed from code once it is fixed in NVM.
 720          */
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 731         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 732         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 733
 734         /* Initialize registers for parsing packet type of QinQ */
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 736         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 737 }
 738
 739 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 740
 741 /*
 742  * Add a ethertype filter to drop all flow control frames transmitted
 743  * from VSIs.
 744 */
 745 static void
 746 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 747 {
 748         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 749         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 750                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 751                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 752         int ret;
 753
 754         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 755                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 756                                 pf->main_vsi_seid, 0,
 757                                 TRUE, NULL, NULL);
 758         if (ret)
 759                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 760                                   " frames from VSIs.");
 761 }
 762
 763 static int
 764 floating_veb_list_handler(__rte_unused const char *key,
 765                           const char *floating_veb_value,
 766                           void *opaque)
 767 {
 768         int idx = 0;
 769         unsigned int count = 0;
 770         char *end = NULL;
 771         int min, max;
 772         bool *vf_floating_veb = opaque;
 773
 774         while (isblank(*floating_veb_value))
 775                 floating_veb_value++;
 776
 777         /* Reset floating VEB configuration for VFs */
 778         for (idx = 0; idx < I40E_MAX_VF; idx++)
 779                 vf_floating_veb[idx] = false;
 780
 781         min = I40E_MAX_VF;
 782         do {
 783                 while (isblank(*floating_veb_value))
 784                         floating_veb_value++;
 785                 if (*floating_veb_value == '\0')
 786                         return -1;
 787                 errno = 0;
 788                 idx = strtoul(floating_veb_value, &end, 10);
 789                 if (errno || end == NULL)
 790                         return -1;
 791                 while (isblank(*end))
 792                         end++;
 793                 if (*end == '-') {
 794                         min = idx;
 795                 } else if ((*end == ';') || (*end == '\0')) {
 796                         max = idx;
 797                         if (min == I40E_MAX_VF)
 798                                 min = idx;
 799                         if (max >= I40E_MAX_VF)
 800                                 max = I40E_MAX_VF - 1;
 801                         for (idx = min; idx <= max; idx++) {
 802                                 vf_floating_veb[idx] = true;
 803                                 count++;
 804                         }
 805                         min = I40E_MAX_VF;
 806                 } else {
 807                         return -1;
 808                 }
 809                 floating_veb_value = end + 1;
 810         } while (*end != '\0');
 811
 812         if (count == 0)
 813                 return -1;
 814
 815         return 0;
 816 }
 817
 818 static void
 819 config_vf_floating_veb(struct rte_devargs *devargs,
 820                        uint16_t floating_veb,
 821                        bool *vf_floating_veb)
 822 {
 823         struct rte_kvargs *kvlist;
 824         int i;
 825         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 826
 827         if (!floating_veb)
 828                 return;
 829         /* All the VFs attach to the floating VEB by default
 830          * when the floating VEB is enabled.
 831          */
 832         for (i = 0; i < I40E_MAX_VF; i++)
 833                 vf_floating_veb[i] = true;
 834
 835         if (devargs == NULL)
 836                 return;
 837
 838         kvlist = rte_kvargs_parse(devargs->args, NULL);
 839         if (kvlist == NULL)
 840                 return;
 841
 842         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 843                 rte_kvargs_free(kvlist);
 844                 return;
 845         }
 846         /* When the floating_veb_list parameter exists, all the VFs
 847          * will attach to the legacy VEB firstly, then configure VFs
 848          * to the floating VEB according to the floating_veb_list.
 849          */
 850         if (rte_kvargs_process(kvlist, floating_veb_list,
 851                                floating_veb_list_handler,
 852                                vf_floating_veb) < 0) {
 853                 rte_kvargs_free(kvlist);
 854                 return;
 855         }
 856         rte_kvargs_free(kvlist);
 857 }
 858
 859 static int
 860 i40e_check_floating_handler(__rte_unused const char *key,
 861                             const char *value,
 862                             __rte_unused void *opaque)
 863 {
 864         if (strcmp(value, "1"))
 865                 return -1;
 866
 867         return 0;
 868 }
 869
 870 static int
 871 is_floating_veb_supported(struct rte_devargs *devargs)
 872 {
 873         struct rte_kvargs *kvlist;
 874         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 875
 876         if (devargs == NULL)
 877                 return 0;
 878
 879         kvlist = rte_kvargs_parse(devargs->args, NULL);
 880         if (kvlist == NULL)
 881                 return 0;
 882
 883         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 884                 rte_kvargs_free(kvlist);
 885                 return 0;
 886         }
 887         /* Floating VEB is enabled when there's key-value:
 888          * enable_floating_veb=1
 889          */
 890         if (rte_kvargs_process(kvlist, floating_veb_key,
 891                                i40e_check_floating_handler, NULL) < 0) {
 892                 rte_kvargs_free(kvlist);
 893                 return 0;
 894         }
 895         rte_kvargs_free(kvlist);
 896
 897         return 1;
 898 }
 899
 900 static void
 901 config_floating_veb(struct rte_eth_dev *dev)
 902 {
 903         struct rte_pci_device *pci_dev = dev->pci_dev;
 904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 906
 907         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 908
 909         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 910                 pf->floating_veb =
 911                         is_floating_veb_supported(pci_dev->device.devargs);
 912                 config_vf_floating_veb(pci_dev->device.devargs,
 913                                        pf->floating_veb,
 914                                        pf->floating_veb_list);
 915         } else {
 916                 pf->floating_veb = false;
 917         }
 918 }
 919
 920 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 921 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 922
 923 static int
 924 eth_i40e_dev_init(struct rte_eth_dev *dev)
 925 {
 926         struct rte_pci_device *pci_dev;
 927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 929         struct i40e_vsi *vsi;
 930         int ret;
 931         uint32_t len;
 932         uint8_t aq_fail = 0;
 933
 934         PMD_INIT_FUNC_TRACE();
 935
 936         dev->dev_ops = &i40e_eth_dev_ops;
 937         dev->rx_pkt_burst = i40e_recv_pkts;
 938         dev->tx_pkt_burst = i40e_xmit_pkts;
 939
 940         /* for secondary processes, we don't initialise any further as primary
 941          * has already done this work. Only check we don't need a different
 942          * RX function */
 943         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 944                 i40e_set_rx_function(dev);
 945                 i40e_set_tx_function(dev);
 946                 return 0;
 947         }
 948         pci_dev = dev->pci_dev;
 949
 950         rte_eth_copy_pci_info(dev, pci_dev);
 951
 952         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 953         pf->adapter->eth_dev = dev;
 954         pf->dev_data = dev->data;
 955
 956         hw->back = I40E_PF_TO_ADAPTER(pf);
 957         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 958         if (!hw->hw_addr) {
 959                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 960                              "as address is NULL");
 961                 return -ENODEV;
 962         }
 963
 964         hw->vendor_id = pci_dev->id.vendor_id;
 965         hw->device_id = pci_dev->id.device_id;
 966         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 967         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 968         hw->bus.device = pci_dev->addr.devid;
 969         hw->bus.func = pci_dev->addr.function;
 970         hw->adapter_stopped = 0;
 971
 972         /* Make sure all is clean before doing PF reset */
 973         i40e_clear_hw(hw);
 974
 975         /* Initialize the hardware */
 976         i40e_hw_init(dev);
 977
 978         /* Reset here to make sure all is clean for each PF */
 979         ret = i40e_pf_reset(hw);
 980         if (ret) {
 981                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 982                 return ret;
 983         }
 984
 985         /* Initialize the shared code (base driver) */
 986         ret = i40e_init_shared_code(hw);
 987         if (ret) {
 988                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 989                 return ret;
 990         }
 991
 992         /*
 993          * To work around the NVM issue, initialize registers
 994          * for flexible payload and packet type of QinQ by
 995          * software. It should be removed once issues are fixed
 996          * in NVM.
 997          */
 998         i40e_GLQF_reg_init(hw);
 999
1000         /* Initialize the input set for filters (hash and fd) to default value */
1001         i40e_filter_input_set_init(pf);
1002
1003         /* Initialize the parameters for adminq */
1004         i40e_init_adminq_parameter(hw);
1005         ret = i40e_init_adminq(hw);
1006         if (ret != I40E_SUCCESS) {
1007                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1008                 return -EIO;
1009         }
1010         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1011                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1012                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1013                      ((hw->nvm.version >> 12) & 0xf),
1014                      ((hw->nvm.version >> 4) & 0xff),
1015                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1016
1017         /* Need the special FW version to support floating VEB */
1018         config_floating_veb(dev);
1019         /* Clear PXE mode */
1020         i40e_clear_pxe_mode(hw);
1021         ret = i40e_dev_sync_phy_type(hw);
1022         if (ret) {
1023                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1024                 goto err_sync_phy_type;
1025         }
1026         /*
1027          * On X710, performance number is far from the expectation on recent
1028          * firmware versions. The fix for this issue may not be integrated in
1029          * the following firmware version. So the workaround in software driver
1030          * is needed. It needs to modify the initial values of 3 internal only
1031          * registers. Note that the workaround can be removed when it is fixed
1032          * in firmware in the future.
1033          */
1034         i40e_configure_registers(hw);
1035
1036         /* Get hw capabilities */
1037         ret = i40e_get_cap(hw);
1038         if (ret != I40E_SUCCESS) {
1039                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1040                 goto err_get_capabilities;
1041         }
1042
1043         /* Initialize parameters for PF */
1044         ret = i40e_pf_parameter_init(dev);
1045         if (ret != 0) {
1046                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1047                 goto err_parameter_init;
1048         }
1049
1050         /* Initialize the queue management */
1051         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1052         if (ret < 0) {
1053                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1054                 goto err_qp_pool_init;
1055         }
1056         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1057                                 hw->func_caps.num_msix_vectors - 1);
1058         if (ret < 0) {
1059                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1060                 goto err_msix_pool_init;
1061         }
1062
1063         /* Initialize lan hmc */
1064         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1065                                 hw->func_caps.num_rx_qp, 0, 0);
1066         if (ret != I40E_SUCCESS) {
1067                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1068                 goto err_init_lan_hmc;
1069         }
1070
1071         /* Configure lan hmc */
1072         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1073         if (ret != I40E_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1075                 goto err_configure_lan_hmc;
1076         }
1077
1078         /* Get and check the mac address */
1079         i40e_get_mac_addr(hw, hw->mac.addr);
1080         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1081                 PMD_INIT_LOG(ERR, "mac address is not valid");
1082                 ret = -EIO;
1083                 goto err_get_mac_addr;
1084         }
1085         /* Copy the permanent MAC address */
1086         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1087                         (struct ether_addr *) hw->mac.perm_addr);
1088
1089         /* Disable flow control */
1090         hw->fc.requested_mode = I40E_FC_NONE;
1091         i40e_set_fc(hw, &aq_fail, TRUE);
1092
1093         /* Set the global registers with default ether type value */
1094         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1095         if (ret != I40E_SUCCESS) {
1096                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1097                              "VLAN ether type");
1098                 goto err_setup_pf_switch;
1099         }
1100
1101         /* PF setup, which includes VSI setup */
1102         ret = i40e_pf_setup(pf);
1103         if (ret) {
1104                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1105                 goto err_setup_pf_switch;
1106         }
1107
1108         /* reset all stats of the device, including pf and main vsi */
1109         i40e_dev_stats_reset(dev);
1110
1111         vsi = pf->main_vsi;
1112
1113         /* Disable double vlan by default */
1114         i40e_vsi_config_double_vlan(vsi, FALSE);
1115
1116         /* Disable S-TAG identification by default */
1117         ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1118         if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1119                 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1120                 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1121         }
1122
1123         if (!vsi->max_macaddrs)
1124                 len = ETHER_ADDR_LEN;
1125         else
1126                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1127
1128         /* Should be after VSI initialized */
1129         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1130         if (!dev->data->mac_addrs) {
1131                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1132                                         "for storing mac address");
1133                 goto err_mac_alloc;
1134         }
1135         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1136                                         &dev->data->mac_addrs[0]);
1137
1138         /* initialize pf host driver to setup SRIOV resource if applicable */
1139         i40e_pf_host_init(dev);
1140
1141         /* register callback func to eal lib */
1142         rte_intr_callback_register(&(pci_dev->intr_handle),
1143                 i40e_dev_interrupt_handler, (void *)dev);
1144
1145         /* configure and enable device interrupt */
1146         i40e_pf_config_irq0(hw, TRUE);
1147         i40e_pf_enable_irq0(hw);
1148
1149         /* enable uio intr after callback register */
1150         rte_intr_enable(&(pci_dev->intr_handle));
1151         /*
1152          * Add an ethertype filter to drop all flow control frames transmitted
1153          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1154          * frames to wire.
1155          */
1156         i40e_add_tx_flow_control_drop_filter(pf);
1157
1158         /* Set the max frame size to 0x2600 by default,
1159          * in case other drivers changed the default value.
1160          */
1161         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1162
1163         /* initialize mirror rule list */
1164         TAILQ_INIT(&pf->mirror_list);
1165
1166         /* Init dcb to sw mode by default */
1167         ret = i40e_dcb_init_configure(dev, TRUE);
1168         if (ret != I40E_SUCCESS) {
1169                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1170                 pf->flags &= ~I40E_FLAG_DCB;
1171         }
1172
1173         return 0;
1174
1175 err_mac_alloc:
1176         i40e_vsi_release(pf->main_vsi);
1177 err_setup_pf_switch:
1178 err_get_mac_addr:
1179 err_configure_lan_hmc:
1180         (void)i40e_shutdown_lan_hmc(hw);
1181 err_init_lan_hmc:
1182         i40e_res_pool_destroy(&pf->msix_pool);
1183 err_msix_pool_init:
1184         i40e_res_pool_destroy(&pf->qp_pool);
1185 err_qp_pool_init:
1186 err_parameter_init:
1187 err_get_capabilities:
1188 err_sync_phy_type:
1189         (void)i40e_shutdown_adminq(hw);
1190
1191         return ret;
1192 }
1193
1194 static int
1195 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1196 {
1197         struct rte_pci_device *pci_dev;
1198         struct i40e_hw *hw;
1199         struct i40e_filter_control_settings settings;
1200         int ret;
1201         uint8_t aq_fail = 0;
1202
1203         PMD_INIT_FUNC_TRACE();
1204
1205         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1206                 return 0;
1207
1208         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1209         pci_dev = dev->pci_dev;
1210
1211         if (hw->adapter_stopped == 0)
1212                 i40e_dev_close(dev);
1213
1214         dev->dev_ops = NULL;
1215         dev->rx_pkt_burst = NULL;
1216         dev->tx_pkt_burst = NULL;
1217
1218         /* Disable LLDP */
1219         ret = i40e_aq_stop_lldp(hw, true, NULL);
1220         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1221                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1222
1223         /* Clear PXE mode */
1224         i40e_clear_pxe_mode(hw);
1225
1226         /* Unconfigure filter control */
1227         memset(&settings, 0, sizeof(settings));
1228         ret = i40e_set_filter_control(hw, &settings);
1229         if (ret)
1230                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1231                                         ret);
1232
1233         /* Disable flow control */
1234         hw->fc.requested_mode = I40E_FC_NONE;
1235         i40e_set_fc(hw, &aq_fail, TRUE);
1236
1237         /* uninitialize pf host driver */
1238         i40e_pf_host_uninit(dev);
1239
1240         rte_free(dev->data->mac_addrs);
1241         dev->data->mac_addrs = NULL;
1242
1243         /* disable uio intr before callback unregister */
1244         rte_intr_disable(&(pci_dev->intr_handle));
1245
1246         /* register callback func to eal lib */
1247         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1248                 i40e_dev_interrupt_handler, (void *)dev);
1249
1250         return 0;
1251 }
1252
1253 static int
1254 i40e_dev_configure(struct rte_eth_dev *dev)
1255 {
1256         struct i40e_adapter *ad =
1257                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1258         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1259         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1260         int i, ret;
1261
1262         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1263          * bulk allocation or vector Rx preconditions we will reset it.
1264          */
1265         ad->rx_bulk_alloc_allowed = true;
1266         ad->rx_vec_allowed = true;
1267         ad->tx_simple_allowed = true;
1268         ad->tx_vec_allowed = true;
1269
1270         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1271                 ret = i40e_fdir_setup(pf);
1272                 if (ret != I40E_SUCCESS) {
1273                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1274                         return -ENOTSUP;
1275                 }
1276                 ret = i40e_fdir_configure(dev);
1277                 if (ret < 0) {
1278                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1279                         goto err;
1280                 }
1281         } else
1282                 i40e_fdir_teardown(pf);
1283
1284         ret = i40e_dev_init_vlan(dev);
1285         if (ret < 0)
1286                 goto err;
1287
1288         /* VMDQ setup.
1289          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1290          *  RSS setting have different requirements.
1291          *  General PMD driver call sequence are NIC init, configure,
1292          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1293          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1294          *  applicable. So, VMDQ setting has to be done before
1295          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1296          *  For RSS setting, it will try to calculate actual configured RX queue
1297          *  number, which will be available after rx_queue_setup(). dev_start()
1298          *  function is good to place RSS setup.
1299          */
1300         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1301                 ret = i40e_vmdq_setup(dev);
1302                 if (ret)
1303                         goto err;
1304         }
1305
1306         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1307                 ret = i40e_dcb_setup(dev);
1308                 if (ret) {
1309                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1310                         goto err_dcb;
1311                 }
1312         }
1313
1314         return 0;
1315
1316 err_dcb:
1317         /* need to release vmdq resource if exists */
1318         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1319                 i40e_vsi_release(pf->vmdq[i].vsi);
1320                 pf->vmdq[i].vsi = NULL;
1321         }
1322         rte_free(pf->vmdq);
1323         pf->vmdq = NULL;
1324 err:
1325         /* need to release fdir resource if exists */
1326         i40e_fdir_teardown(pf);
1327         return ret;
1328 }
1329
1330 void
1331 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1332 {
1333         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1334         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1335         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1336         uint16_t msix_vect = vsi->msix_intr;
1337         uint16_t i;
1338
1339         for (i = 0; i < vsi->nb_qps; i++) {
1340                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1341                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1342                 rte_wmb();
1343         }
1344
1345         if (vsi->type != I40E_VSI_SRIOV) {
1346                 if (!rte_intr_allow_others(intr_handle)) {
1347                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1348                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1349                         I40E_WRITE_REG(hw,
1350                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1351                                        0);
1352                 } else {
1353                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1354                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1355                         I40E_WRITE_REG(hw,
1356                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1357                                                        msix_vect - 1), 0);
1358                 }
1359         } else {
1360                 uint32_t reg;
1361                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1362                         vsi->user_param + (msix_vect - 1);
1363
1364                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1365                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1366         }
1367         I40E_WRITE_FLUSH(hw);
1368 }
1369
1370 static void
1371 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1372                        int base_queue, int nb_queue)
1373 {
1374         int i;
1375         uint32_t val;
1376         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1377
1378         /* Bind all RX queues to allocated MSIX interrupt */
1379         for (i = 0; i < nb_queue; i++) {
1380                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1381                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1382                         ((base_queue + i + 1) <<
1383                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1384                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1385                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1386
1387                 if (i == nb_queue - 1)
1388                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1389                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1390         }
1391
1392         /* Write first RX queue to Link list register as the head element */
1393         if (vsi->type != I40E_VSI_SRIOV) {
1394                 uint16_t interval =
1395                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1396
1397                 if (msix_vect == I40E_MISC_VEC_ID) {
1398                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1399                                        (base_queue <<
1400                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1401                                        (0x0 <<
1402                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1403                         I40E_WRITE_REG(hw,
1404                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1405                                        interval);
1406                 } else {
1407                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1408                                        (base_queue <<
1409                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1410                                        (0x0 <<
1411                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1412                         I40E_WRITE_REG(hw,
1413                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1414                                                        msix_vect - 1),
1415                                        interval);
1416                 }
1417         } else {
1418                 uint32_t reg;
1419
1420                 if (msix_vect == I40E_MISC_VEC_ID) {
1421                         I40E_WRITE_REG(hw,
1422                                        I40E_VPINT_LNKLST0(vsi->user_param),
1423                                        (base_queue <<
1424                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1425                                        (0x0 <<
1426                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1427                 } else {
1428                         /* num_msix_vectors_vf needs to minus irq0 */
1429                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1430                                 vsi->user_param + (msix_vect - 1);
1431
1432                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1433                                        (base_queue <<
1434                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1435                                        (0x0 <<
1436                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1437                 }
1438         }
1439
1440         I40E_WRITE_FLUSH(hw);
1441 }
1442
1443 void
1444 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1445 {
1446         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1447         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1448         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1449         uint16_t msix_vect = vsi->msix_intr;
1450         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1451         uint16_t queue_idx = 0;
1452         int record = 0;
1453         uint32_t val;
1454         int i;
1455
1456         for (i = 0; i < vsi->nb_qps; i++) {
1457                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1458                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1459         }
1460
1461         /* INTENA flag is not auto-cleared for interrupt */
1462         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1463         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1464                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1465                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1466         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1467
1468         /* VF bind interrupt */
1469         if (vsi->type == I40E_VSI_SRIOV) {
1470                 __vsi_queues_bind_intr(vsi, msix_vect,
1471                                        vsi->base_queue, vsi->nb_qps);
1472                 return;
1473         }
1474
1475         /* PF & VMDq bind interrupt */
1476         if (rte_intr_dp_is_en(intr_handle)) {
1477                 if (vsi->type == I40E_VSI_MAIN) {
1478                         queue_idx = 0;
1479                         record = 1;
1480                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1481                         struct i40e_vsi *main_vsi =
1482                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1483                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1484                         record = 1;
1485                 }
1486         }
1487
1488         for (i = 0; i < vsi->nb_used_qps; i++) {
1489                 if (nb_msix <= 1) {
1490                         if (!rte_intr_allow_others(intr_handle))
1491                                 /* allow to share MISC_VEC_ID */
1492                                 msix_vect = I40E_MISC_VEC_ID;
1493
1494                         /* no enough msix_vect, map all to one */
1495                         __vsi_queues_bind_intr(vsi, msix_vect,
1496                                                vsi->base_queue + i,
1497                                                vsi->nb_used_qps - i);
1498                         for (; !!record && i < vsi->nb_used_qps; i++)
1499                                 intr_handle->intr_vec[queue_idx + i] =
1500                                         msix_vect;
1501                         break;
1502                 }
1503                 /* 1:1 queue/msix_vect mapping */
1504                 __vsi_queues_bind_intr(vsi, msix_vect,
1505                                        vsi->base_queue + i, 1);
1506                 if (!!record)
1507                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1508
1509                 msix_vect++;
1510                 nb_msix--;
1511         }
1512 }
1513
1514 static void
1515 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1516 {
1517         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1518         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1519         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1520         uint16_t interval = i40e_calc_itr_interval(\
1521                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1522         uint16_t msix_intr, i;
1523
1524         if (rte_intr_allow_others(intr_handle))
1525                 for (i = 0; i < vsi->nb_msix; i++) {
1526                         msix_intr = vsi->msix_intr + i;
1527                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1528                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1529                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1530                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1531                                 (interval <<
1532                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1533                 }
1534         else
1535                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1536                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1537                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1538                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1539                                (interval <<
1540                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1541
1542         I40E_WRITE_FLUSH(hw);
1543 }
1544
1545 static void
1546 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1547 {
1548         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1549         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1550         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1551         uint16_t msix_intr, i;
1552
1553         if (rte_intr_allow_others(intr_handle))
1554                 for (i = 0; i < vsi->nb_msix; i++) {
1555                         msix_intr = vsi->msix_intr + i;
1556                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1557                                        0);
1558                 }
1559         else
1560                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1561
1562         I40E_WRITE_FLUSH(hw);
1563 }
1564
1565 static inline uint8_t
1566 i40e_parse_link_speeds(uint16_t link_speeds)
1567 {
1568         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1569
1570         if (link_speeds & ETH_LINK_SPEED_40G)
1571                 link_speed |= I40E_LINK_SPEED_40GB;
1572         if (link_speeds & ETH_LINK_SPEED_20G)
1573                 link_speed |= I40E_LINK_SPEED_20GB;
1574         if (link_speeds & ETH_LINK_SPEED_10G)
1575                 link_speed |= I40E_LINK_SPEED_10GB;
1576         if (link_speeds & ETH_LINK_SPEED_1G)
1577                 link_speed |= I40E_LINK_SPEED_1GB;
1578         if (link_speeds & ETH_LINK_SPEED_100M)
1579                 link_speed |= I40E_LINK_SPEED_100MB;
1580
1581         return link_speed;
1582 }
1583
1584 static int
1585 i40e_phy_conf_link(struct i40e_hw *hw,
1586                    uint8_t abilities,
1587                    uint8_t force_speed)
1588 {
1589         enum i40e_status_code status;
1590         struct i40e_aq_get_phy_abilities_resp phy_ab;
1591         struct i40e_aq_set_phy_config phy_conf;
1592         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1593                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1594                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1595                         I40E_AQ_PHY_FLAG_LOW_POWER;
1596         const uint8_t advt = I40E_LINK_SPEED_40GB |
1597                         I40E_LINK_SPEED_10GB |
1598                         I40E_LINK_SPEED_1GB |
1599                         I40E_LINK_SPEED_100MB;
1600         int ret = -ENOTSUP;
1601
1602
1603         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1604                                               NULL);
1605         if (status)
1606                 return ret;
1607
1608         memset(&phy_conf, 0, sizeof(phy_conf));
1609
1610         /* bits 0-2 use the values from get_phy_abilities_resp */
1611         abilities &= ~mask;
1612         abilities |= phy_ab.abilities & mask;
1613
1614         /* update ablities and speed */
1615         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1616                 phy_conf.link_speed = advt;
1617         else
1618                 phy_conf.link_speed = force_speed;
1619
1620         phy_conf.abilities = abilities;
1621
1622         /* use get_phy_abilities_resp value for the rest */
1623         phy_conf.phy_type = phy_ab.phy_type;
1624         phy_conf.eee_capability = phy_ab.eee_capability;
1625         phy_conf.eeer = phy_ab.eeer_val;
1626         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1627
1628         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1629                     phy_ab.abilities, phy_ab.link_speed);
1630         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1631                     phy_conf.abilities, phy_conf.link_speed);
1632
1633         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1634         if (status)
1635                 return ret;
1636
1637         return I40E_SUCCESS;
1638 }
1639
1640 static int
1641 i40e_apply_link_speed(struct rte_eth_dev *dev)
1642 {
1643         uint8_t speed;
1644         uint8_t abilities = 0;
1645         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646         struct rte_eth_conf *conf = &dev->data->dev_conf;
1647
1648         speed = i40e_parse_link_speeds(conf->link_speeds);
1649         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1650         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1651                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1652         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1653
1654         /* Skip changing speed on 40G interfaces, FW does not support */
1655         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1656                 speed =  I40E_LINK_SPEED_UNKNOWN;
1657                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1658         }
1659
1660         return i40e_phy_conf_link(hw, abilities, speed);
1661 }
1662
1663 static int
1664 i40e_dev_start(struct rte_eth_dev *dev)
1665 {
1666         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1667         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1668         struct i40e_vsi *main_vsi = pf->main_vsi;
1669         int ret, i;
1670         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1671         uint32_t intr_vector = 0;
1672
1673         hw->adapter_stopped = 0;
1674
1675         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1676                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1677                              dev->data->port_id);
1678                 return -EINVAL;
1679         }
1680
1681         rte_intr_disable(intr_handle);
1682
1683         if ((rte_intr_cap_multiple(intr_handle) ||
1684              !RTE_ETH_DEV_SRIOV(dev).active) &&
1685             dev->data->dev_conf.intr_conf.rxq != 0) {
1686                 intr_vector = dev->data->nb_rx_queues;
1687                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1688                         return -1;
1689         }
1690
1691         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1692                 intr_handle->intr_vec =
1693                         rte_zmalloc("intr_vec",
1694                                     dev->data->nb_rx_queues * sizeof(int),
1695                                     0);
1696                 if (!intr_handle->intr_vec) {
1697                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1698                                      " intr_vec\n", dev->data->nb_rx_queues);
1699                         return -ENOMEM;
1700                 }
1701         }
1702
1703         /* Initialize VSI */
1704         ret = i40e_dev_rxtx_init(pf);
1705         if (ret != I40E_SUCCESS) {
1706                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1707                 goto err_up;
1708         }
1709
1710         /* Map queues with MSIX interrupt */
1711         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1712                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1713         i40e_vsi_queues_bind_intr(main_vsi);
1714         i40e_vsi_enable_queues_intr(main_vsi);
1715
1716         /* Map VMDQ VSI queues with MSIX interrupt */
1717         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1718                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1719                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1720                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1721         }
1722
1723         /* enable FDIR MSIX interrupt */
1724         if (pf->fdir.fdir_vsi) {
1725                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1726                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1727         }
1728
1729         /* Enable all queues which have been configured */
1730         ret = i40e_dev_switch_queues(pf, TRUE);
1731         if (ret != I40E_SUCCESS) {
1732                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1733                 goto err_up;
1734         }
1735
1736         /* Enable receiving broadcast packets */
1737         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1738         if (ret != I40E_SUCCESS)
1739                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1740
1741         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1742                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1743                                                 true, NULL);
1744                 if (ret != I40E_SUCCESS)
1745                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1746         }
1747
1748         /* Apply link configure */
1749         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1750                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1751                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1752                 PMD_DRV_LOG(ERR, "Invalid link setting");
1753                 goto err_up;
1754         }
1755         ret = i40e_apply_link_speed(dev);
1756         if (I40E_SUCCESS != ret) {
1757                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1758                 goto err_up;
1759         }
1760
1761         if (!rte_intr_allow_others(intr_handle)) {
1762                 rte_intr_callback_unregister(intr_handle,
1763                                              i40e_dev_interrupt_handler,
1764                                              (void *)dev);
1765                 /* configure and enable device interrupt */
1766                 i40e_pf_config_irq0(hw, FALSE);
1767                 i40e_pf_enable_irq0(hw);
1768
1769                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1770                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1771                                      " no intr multiplex\n");
1772         }
1773
1774         /* enable uio intr after callback register */
1775         rte_intr_enable(intr_handle);
1776
1777         return I40E_SUCCESS;
1778
1779 err_up:
1780         i40e_dev_switch_queues(pf, FALSE);
1781         i40e_dev_clear_queues(dev);
1782
1783         return ret;
1784 }
1785
1786 static void
1787 i40e_dev_stop(struct rte_eth_dev *dev)
1788 {
1789         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1790         struct i40e_vsi *main_vsi = pf->main_vsi;
1791         struct i40e_mirror_rule *p_mirror;
1792         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1793         int i;
1794
1795         /* Disable all queues */
1796         i40e_dev_switch_queues(pf, FALSE);
1797
1798         /* un-map queues with interrupt registers */
1799         i40e_vsi_disable_queues_intr(main_vsi);
1800         i40e_vsi_queues_unbind_intr(main_vsi);
1801
1802         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1803                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1804                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1805         }
1806
1807         if (pf->fdir.fdir_vsi) {
1808                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1809                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1810         }
1811         /* Clear all queues and release memory */
1812         i40e_dev_clear_queues(dev);
1813
1814         /* Set link down */
1815         i40e_dev_set_link_down(dev);
1816
1817         /* Remove all mirror rules */
1818         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1819                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1820                 rte_free(p_mirror);
1821         }
1822         pf->nb_mirror_rule = 0;
1823
1824         if (!rte_intr_allow_others(intr_handle))
1825                 /* resume to the default handler */
1826                 rte_intr_callback_register(intr_handle,
1827                                            i40e_dev_interrupt_handler,
1828                                            (void *)dev);
1829
1830         /* Clean datapath event and queue/vec mapping */
1831         rte_intr_efd_disable(intr_handle);
1832         if (intr_handle->intr_vec) {
1833                 rte_free(intr_handle->intr_vec);
1834                 intr_handle->intr_vec = NULL;
1835         }
1836 }
1837
1838 static void
1839 i40e_dev_close(struct rte_eth_dev *dev)
1840 {
1841         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843         uint32_t reg;
1844         int i;
1845
1846         PMD_INIT_FUNC_TRACE();
1847
1848         i40e_dev_stop(dev);
1849         hw->adapter_stopped = 1;
1850         i40e_dev_free_queues(dev);
1851
1852         /* Disable interrupt */
1853         i40e_pf_disable_irq0(hw);
1854         rte_intr_disable(&(dev->pci_dev->intr_handle));
1855
1856         /* shutdown and destroy the HMC */
1857         i40e_shutdown_lan_hmc(hw);
1858
1859         /* release all the existing VSIs and VEBs */
1860         i40e_fdir_teardown(pf);
1861         i40e_vsi_release(pf->main_vsi);
1862
1863         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1864                 i40e_vsi_release(pf->vmdq[i].vsi);
1865                 pf->vmdq[i].vsi = NULL;
1866         }
1867
1868         rte_free(pf->vmdq);
1869         pf->vmdq = NULL;
1870
1871         /* shutdown the adminq */
1872         i40e_aq_queue_shutdown(hw, true);
1873         i40e_shutdown_adminq(hw);
1874
1875         i40e_res_pool_destroy(&pf->qp_pool);
1876         i40e_res_pool_destroy(&pf->msix_pool);
1877
1878         /* force a PF reset to clean anything leftover */
1879         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1880         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1881                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1882         I40E_WRITE_FLUSH(hw);
1883 }
1884
1885 static void
1886 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1887 {
1888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890         struct i40e_vsi *vsi = pf->main_vsi;
1891         int status;
1892
1893         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1894                                                      true, NULL, true);
1895         if (status != I40E_SUCCESS)
1896                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1897
1898         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1899                                                         TRUE, NULL);
1900         if (status != I40E_SUCCESS)
1901                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1902
1903 }
1904
1905 static void
1906 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1907 {
1908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1909         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910         struct i40e_vsi *vsi = pf->main_vsi;
1911         int status;
1912
1913         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1914                                                      false, NULL, true);
1915         if (status != I40E_SUCCESS)
1916                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1917
1918         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1919                                                         false, NULL);
1920         if (status != I40E_SUCCESS)
1921                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1922 }
1923
1924 static void
1925 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1926 {
1927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         struct i40e_vsi *vsi = pf->main_vsi;
1930         int ret;
1931
1932         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1933         if (ret != I40E_SUCCESS)
1934                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1935 }
1936
1937 static void
1938 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1939 {
1940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         struct i40e_vsi *vsi = pf->main_vsi;
1943         int ret;
1944
1945         if (dev->data->promiscuous == 1)
1946                 return; /* must remain in all_multicast mode */
1947
1948         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1949                                 vsi->seid, FALSE, NULL);
1950         if (ret != I40E_SUCCESS)
1951                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1952 }
1953
1954 /*
1955  * Set device link up.
1956  */
1957 static int
1958 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1959 {
1960         /* re-apply link speed setting */
1961         return i40e_apply_link_speed(dev);
1962 }
1963
1964 /*
1965  * Set device link down.
1966  */
1967 static int
1968 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1969 {
1970         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1971         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1972         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973
1974         return i40e_phy_conf_link(hw, abilities, speed);
1975 }
1976
1977 int
1978 i40e_dev_link_update(struct rte_eth_dev *dev,
1979                      int wait_to_complete)
1980 {
1981 #define CHECK_INTERVAL 100  /* 100ms */
1982 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1984         struct i40e_link_status link_status;
1985         struct rte_eth_link link, old;
1986         int status;
1987         unsigned rep_cnt = MAX_REPEAT_TIME;
1988
1989         memset(&link, 0, sizeof(link));
1990         memset(&old, 0, sizeof(old));
1991         memset(&link_status, 0, sizeof(link_status));
1992         rte_i40e_dev_atomic_read_link_status(dev, &old);
1993
1994         do {
1995                 /* Get link status information from hardware */
1996                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1997                 if (status != I40E_SUCCESS) {
1998                         link.link_speed = ETH_SPEED_NUM_100M;
1999                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2000                         PMD_DRV_LOG(ERR, "Failed to get link info");
2001                         goto out;
2002                 }
2003
2004                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2005                 if (!wait_to_complete)
2006                         break;
2007
2008                 rte_delay_ms(CHECK_INTERVAL);
2009         } while (!link.link_status && rep_cnt--);
2010
2011         if (!link.link_status)
2012                 goto out;
2013
2014         /* i40e uses full duplex only */
2015         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2016
2017         /* Parse the link status */
2018         switch (link_status.link_speed) {
2019         case I40E_LINK_SPEED_100MB:
2020                 link.link_speed = ETH_SPEED_NUM_100M;
2021                 break;
2022         case I40E_LINK_SPEED_1GB:
2023                 link.link_speed = ETH_SPEED_NUM_1G;
2024                 break;
2025         case I40E_LINK_SPEED_10GB:
2026                 link.link_speed = ETH_SPEED_NUM_10G;
2027                 break;
2028         case I40E_LINK_SPEED_20GB:
2029                 link.link_speed = ETH_SPEED_NUM_20G;
2030                 break;
2031         case I40E_LINK_SPEED_40GB:
2032                 link.link_speed = ETH_SPEED_NUM_40G;
2033                 break;
2034         default:
2035                 link.link_speed = ETH_SPEED_NUM_100M;
2036                 break;
2037         }
2038
2039         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2040                         ETH_LINK_SPEED_FIXED);
2041
2042 out:
2043         rte_i40e_dev_atomic_write_link_status(dev, &link);
2044         if (link.link_status == old.link_status)
2045                 return -1;
2046
2047         return 0;
2048 }
2049
2050 /* Get all the statistics of a VSI */
2051 void
2052 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2053 {
2054         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2055         struct i40e_eth_stats *nes = &vsi->eth_stats;
2056         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2057         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2058
2059         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2060                             vsi->offset_loaded, &oes->rx_bytes,
2061                             &nes->rx_bytes);
2062         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2063                             vsi->offset_loaded, &oes->rx_unicast,
2064                             &nes->rx_unicast);
2065         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2066                             vsi->offset_loaded, &oes->rx_multicast,
2067                             &nes->rx_multicast);
2068         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2069                             vsi->offset_loaded, &oes->rx_broadcast,
2070                             &nes->rx_broadcast);
2071         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2072                             &oes->rx_discards, &nes->rx_discards);
2073         /* GLV_REPC not supported */
2074         /* GLV_RMPC not supported */
2075         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2076                             &oes->rx_unknown_protocol,
2077                             &nes->rx_unknown_protocol);
2078         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2079                             vsi->offset_loaded, &oes->tx_bytes,
2080                             &nes->tx_bytes);
2081         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2082                             vsi->offset_loaded, &oes->tx_unicast,
2083                             &nes->tx_unicast);
2084         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2085                             vsi->offset_loaded, &oes->tx_multicast,
2086                             &nes->tx_multicast);
2087         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2088                             vsi->offset_loaded,  &oes->tx_broadcast,
2089                             &nes->tx_broadcast);
2090         /* GLV_TDPC not supported */
2091         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2092                             &oes->tx_errors, &nes->tx_errors);
2093         vsi->offset_loaded = true;
2094
2095         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2096                     vsi->vsi_id);
2097         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2098         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2099         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2100         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2101         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2102         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2103                     nes->rx_unknown_protocol);
2104         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2105         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2106         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2107         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2108         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2109         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2110         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2111                     vsi->vsi_id);
2112 }
2113
2114 static void
2115 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2116 {
2117         unsigned int i;
2118         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2119         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2120
2121         /* Get statistics of struct i40e_eth_stats */
2122         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2123                             I40E_GLPRT_GORCL(hw->port),
2124                             pf->offset_loaded, &os->eth.rx_bytes,
2125                             &ns->eth.rx_bytes);
2126         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2127                             I40E_GLPRT_UPRCL(hw->port),
2128                             pf->offset_loaded, &os->eth.rx_unicast,
2129                             &ns->eth.rx_unicast);
2130         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2131                             I40E_GLPRT_MPRCL(hw->port),
2132                             pf->offset_loaded, &os->eth.rx_multicast,
2133                             &ns->eth.rx_multicast);
2134         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2135                             I40E_GLPRT_BPRCL(hw->port),
2136                             pf->offset_loaded, &os->eth.rx_broadcast,
2137                             &ns->eth.rx_broadcast);
2138         /* Workaround: CRC size should not be included in byte statistics,
2139          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2140          */
2141         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2142                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2143
2144         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2145                             pf->offset_loaded, &os->eth.rx_discards,
2146                             &ns->eth.rx_discards);
2147         /* GLPRT_REPC not supported */
2148         /* GLPRT_RMPC not supported */
2149         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2150                             pf->offset_loaded,
2151                             &os->eth.rx_unknown_protocol,
2152                             &ns->eth.rx_unknown_protocol);
2153         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2154                             I40E_GLPRT_GOTCL(hw->port),
2155                             pf->offset_loaded, &os->eth.tx_bytes,
2156                             &ns->eth.tx_bytes);
2157         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2158                             I40E_GLPRT_UPTCL(hw->port),
2159                             pf->offset_loaded, &os->eth.tx_unicast,
2160                             &ns->eth.tx_unicast);
2161         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2162                             I40E_GLPRT_MPTCL(hw->port),
2163                             pf->offset_loaded, &os->eth.tx_multicast,
2164                             &ns->eth.tx_multicast);
2165         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2166                             I40E_GLPRT_BPTCL(hw->port),
2167                             pf->offset_loaded, &os->eth.tx_broadcast,
2168                             &ns->eth.tx_broadcast);
2169         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2170                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2171         /* GLPRT_TEPC not supported */
2172
2173         /* additional port specific stats */
2174         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2175                             pf->offset_loaded, &os->tx_dropped_link_down,
2176                             &ns->tx_dropped_link_down);
2177         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2178                             pf->offset_loaded, &os->crc_errors,
2179                             &ns->crc_errors);
2180         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2181                             pf->offset_loaded, &os->illegal_bytes,
2182                             &ns->illegal_bytes);
2183         /* GLPRT_ERRBC not supported */
2184         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2185                             pf->offset_loaded, &os->mac_local_faults,
2186                             &ns->mac_local_faults);
2187         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2188                             pf->offset_loaded, &os->mac_remote_faults,
2189                             &ns->mac_remote_faults);
2190         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2191                             pf->offset_loaded, &os->rx_length_errors,
2192                             &ns->rx_length_errors);
2193         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2194                             pf->offset_loaded, &os->link_xon_rx,
2195                             &ns->link_xon_rx);
2196         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2197                             pf->offset_loaded, &os->link_xoff_rx,
2198                             &ns->link_xoff_rx);
2199         for (i = 0; i < 8; i++) {
2200                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2201                                     pf->offset_loaded,
2202                                     &os->priority_xon_rx[i],
2203                                     &ns->priority_xon_rx[i]);
2204                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2205                                     pf->offset_loaded,
2206                                     &os->priority_xoff_rx[i],
2207                                     &ns->priority_xoff_rx[i]);
2208         }
2209         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2210                             pf->offset_loaded, &os->link_xon_tx,
2211                             &ns->link_xon_tx);
2212         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2213                             pf->offset_loaded, &os->link_xoff_tx,
2214                             &ns->link_xoff_tx);
2215         for (i = 0; i < 8; i++) {
2216                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2217                                     pf->offset_loaded,
2218                                     &os->priority_xon_tx[i],
2219                                     &ns->priority_xon_tx[i]);
2220                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2221                                     pf->offset_loaded,
2222                                     &os->priority_xoff_tx[i],
2223                                     &ns->priority_xoff_tx[i]);
2224                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2225                                     pf->offset_loaded,
2226                                     &os->priority_xon_2_xoff[i],
2227                                     &ns->priority_xon_2_xoff[i]);
2228         }
2229         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2230                             I40E_GLPRT_PRC64L(hw->port),
2231                             pf->offset_loaded, &os->rx_size_64,
2232                             &ns->rx_size_64);
2233         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2234                             I40E_GLPRT_PRC127L(hw->port),
2235                             pf->offset_loaded, &os->rx_size_127,
2236                             &ns->rx_size_127);
2237         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2238                             I40E_GLPRT_PRC255L(hw->port),
2239                             pf->offset_loaded, &os->rx_size_255,
2240                             &ns->rx_size_255);
2241         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2242                             I40E_GLPRT_PRC511L(hw->port),
2243                             pf->offset_loaded, &os->rx_size_511,
2244                             &ns->rx_size_511);
2245         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2246                             I40E_GLPRT_PRC1023L(hw->port),
2247                             pf->offset_loaded, &os->rx_size_1023,
2248                             &ns->rx_size_1023);
2249         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2250                             I40E_GLPRT_PRC1522L(hw->port),
2251                             pf->offset_loaded, &os->rx_size_1522,
2252                             &ns->rx_size_1522);
2253         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2254                             I40E_GLPRT_PRC9522L(hw->port),
2255                             pf->offset_loaded, &os->rx_size_big,
2256                             &ns->rx_size_big);
2257         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2258                             pf->offset_loaded, &os->rx_undersize,
2259                             &ns->rx_undersize);
2260         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2261                             pf->offset_loaded, &os->rx_fragments,
2262                             &ns->rx_fragments);
2263         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2264                             pf->offset_loaded, &os->rx_oversize,
2265                             &ns->rx_oversize);
2266         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2267                             pf->offset_loaded, &os->rx_jabber,
2268                             &ns->rx_jabber);
2269         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2270                             I40E_GLPRT_PTC64L(hw->port),
2271                             pf->offset_loaded, &os->tx_size_64,
2272                             &ns->tx_size_64);
2273         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2274                             I40E_GLPRT_PTC127L(hw->port),
2275                             pf->offset_loaded, &os->tx_size_127,
2276                             &ns->tx_size_127);
2277         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2278                             I40E_GLPRT_PTC255L(hw->port),
2279                             pf->offset_loaded, &os->tx_size_255,
2280                             &ns->tx_size_255);
2281         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2282                             I40E_GLPRT_PTC511L(hw->port),
2283                             pf->offset_loaded, &os->tx_size_511,
2284                             &ns->tx_size_511);
2285         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2286                             I40E_GLPRT_PTC1023L(hw->port),
2287                             pf->offset_loaded, &os->tx_size_1023,
2288                             &ns->tx_size_1023);
2289         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2290                             I40E_GLPRT_PTC1522L(hw->port),
2291                             pf->offset_loaded, &os->tx_size_1522,
2292                             &ns->tx_size_1522);
2293         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2294                             I40E_GLPRT_PTC9522L(hw->port),
2295                             pf->offset_loaded, &os->tx_size_big,
2296                             &ns->tx_size_big);
2297         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2298                            pf->offset_loaded,
2299                            &os->fd_sb_match, &ns->fd_sb_match);
2300         /* GLPRT_MSPDC not supported */
2301         /* GLPRT_XEC not supported */
2302
2303         pf->offset_loaded = true;
2304
2305         if (pf->main_vsi)
2306                 i40e_update_vsi_stats(pf->main_vsi);
2307 }
2308
2309 /* Get all statistics of a port */
2310 static void
2311 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2312 {
2313         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2314         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2316         unsigned i;
2317
2318         /* call read registers - updates values, now write them to struct */
2319         i40e_read_stats_registers(pf, hw);
2320
2321         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2322                         pf->main_vsi->eth_stats.rx_multicast +
2323                         pf->main_vsi->eth_stats.rx_broadcast -
2324                         pf->main_vsi->eth_stats.rx_discards;
2325         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2326                         pf->main_vsi->eth_stats.tx_multicast +
2327                         pf->main_vsi->eth_stats.tx_broadcast;
2328         stats->ibytes   = ns->eth.rx_bytes;
2329         stats->obytes   = ns->eth.tx_bytes;
2330         stats->oerrors  = ns->eth.tx_errors +
2331                         pf->main_vsi->eth_stats.tx_errors;
2332
2333         /* Rx Errors */
2334         stats->imissed  = ns->eth.rx_discards +
2335                         pf->main_vsi->eth_stats.rx_discards;
2336         stats->ierrors  = ns->crc_errors +
2337                         ns->rx_length_errors + ns->rx_undersize +
2338                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2339
2340         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2341         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2342         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2343         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2344         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2345         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2346         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2347                     ns->eth.rx_unknown_protocol);
2348         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2349         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2350         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2351         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2352         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2353         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2354
2355         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2356                     ns->tx_dropped_link_down);
2357         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2358         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2359                     ns->illegal_bytes);
2360         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2361         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2362                     ns->mac_local_faults);
2363         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2364                     ns->mac_remote_faults);
2365         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2366                     ns->rx_length_errors);
2367         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2368         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2369         for (i = 0; i < 8; i++) {
2370                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2371                                 i, ns->priority_xon_rx[i]);
2372                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2373                                 i, ns->priority_xoff_rx[i]);
2374         }
2375         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2376         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2377         for (i = 0; i < 8; i++) {
2378                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2379                                 i, ns->priority_xon_tx[i]);
2380                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2381                                 i, ns->priority_xoff_tx[i]);
2382                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2383                                 i, ns->priority_xon_2_xoff[i]);
2384         }
2385         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2386         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2387         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2388         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2389         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2390         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2391         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2392         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2393         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2394         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2395         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2396         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2397         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2398         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2399         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2400         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2401         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2402         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2403         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2404                         ns->mac_short_packet_dropped);
2405         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2406                     ns->checksum_error);
2407         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2408         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2409 }
2410
2411 /* Reset the statistics */
2412 static void
2413 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2414 {
2415         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2416         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2417
2418         /* Mark PF and VSI stats to update the offset, aka "reset" */
2419         pf->offset_loaded = false;
2420         if (pf->main_vsi)
2421                 pf->main_vsi->offset_loaded = false;
2422
2423         /* read the stats, reading current register values into offset */
2424         i40e_read_stats_registers(pf, hw);
2425 }
2426
2427 static uint32_t
2428 i40e_xstats_calc_num(void)
2429 {
2430         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2431                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2432                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2433 }
2434
2435 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2436                                      struct rte_eth_xstat_name *xstats_names,
2437                                      __rte_unused unsigned limit)
2438 {
2439         unsigned count = 0;
2440         unsigned i, prio;
2441
2442         if (xstats_names == NULL)
2443                 return i40e_xstats_calc_num();
2444
2445         /* Note: limit checked in rte_eth_xstats_names() */
2446
2447         /* Get stats from i40e_eth_stats struct */
2448         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2449                 snprintf(xstats_names[count].name,
2450                          sizeof(xstats_names[count].name),
2451                          "%s", rte_i40e_stats_strings[i].name);
2452                 count++;
2453         }
2454
2455         /* Get individiual stats from i40e_hw_port struct */
2456         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2457                 snprintf(xstats_names[count].name,
2458                         sizeof(xstats_names[count].name),
2459                          "%s", rte_i40e_hw_port_strings[i].name);
2460                 count++;
2461         }
2462
2463         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2464                 for (prio = 0; prio < 8; prio++) {
2465                         snprintf(xstats_names[count].name,
2466                                  sizeof(xstats_names[count].name),
2467                                  "rx_priority%u_%s", prio,
2468                                  rte_i40e_rxq_prio_strings[i].name);
2469                         count++;
2470                 }
2471         }
2472
2473         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2474                 for (prio = 0; prio < 8; prio++) {
2475                         snprintf(xstats_names[count].name,
2476                                  sizeof(xstats_names[count].name),
2477                                  "tx_priority%u_%s", prio,
2478                                  rte_i40e_txq_prio_strings[i].name);
2479                         count++;
2480                 }
2481         }
2482         return count;
2483 }
2484
2485 static int
2486 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2487                     unsigned n)
2488 {
2489         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2490         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491         unsigned i, count, prio;
2492         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2493
2494         count = i40e_xstats_calc_num();
2495         if (n < count)
2496                 return count;
2497
2498         i40e_read_stats_registers(pf, hw);
2499
2500         if (xstats == NULL)
2501                 return 0;
2502
2503         count = 0;
2504
2505         /* Get stats from i40e_eth_stats struct */
2506         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2507                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2508                         rte_i40e_stats_strings[i].offset);
2509                 count++;
2510         }
2511
2512         /* Get individiual stats from i40e_hw_port struct */
2513         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2514                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2515                         rte_i40e_hw_port_strings[i].offset);
2516                 count++;
2517         }
2518
2519         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2520                 for (prio = 0; prio < 8; prio++) {
2521                         xstats[count].value =
2522                                 *(uint64_t *)(((char *)hw_stats) +
2523                                 rte_i40e_rxq_prio_strings[i].offset +
2524                                 (sizeof(uint64_t) * prio));
2525                         count++;
2526                 }
2527         }
2528
2529         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2530                 for (prio = 0; prio < 8; prio++) {
2531                         xstats[count].value =
2532                                 *(uint64_t *)(((char *)hw_stats) +
2533                                 rte_i40e_txq_prio_strings[i].offset +
2534                                 (sizeof(uint64_t) * prio));
2535                         count++;
2536                 }
2537         }
2538
2539         return count;
2540 }
2541
2542 static int
2543 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2544                                  __rte_unused uint16_t queue_id,
2545                                  __rte_unused uint8_t stat_idx,
2546                                  __rte_unused uint8_t is_rx)
2547 {
2548         PMD_INIT_FUNC_TRACE();
2549
2550         return -ENOSYS;
2551 }
2552
2553 static void
2554 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2555 {
2556         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2557         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2558         struct i40e_vsi *vsi = pf->main_vsi;
2559
2560         dev_info->max_rx_queues = vsi->nb_qps;
2561         dev_info->max_tx_queues = vsi->nb_qps;
2562         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2563         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2564         dev_info->max_mac_addrs = vsi->max_macaddrs;
2565         dev_info->max_vfs = dev->pci_dev->max_vfs;
2566         dev_info->rx_offload_capa =
2567                 DEV_RX_OFFLOAD_VLAN_STRIP |
2568                 DEV_RX_OFFLOAD_QINQ_STRIP |
2569                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2570                 DEV_RX_OFFLOAD_UDP_CKSUM |
2571                 DEV_RX_OFFLOAD_TCP_CKSUM;
2572         dev_info->tx_offload_capa =
2573                 DEV_TX_OFFLOAD_VLAN_INSERT |
2574                 DEV_TX_OFFLOAD_QINQ_INSERT |
2575                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2576                 DEV_TX_OFFLOAD_UDP_CKSUM |
2577                 DEV_TX_OFFLOAD_TCP_CKSUM |
2578                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2579                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2580                 DEV_TX_OFFLOAD_TCP_TSO;
2581         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2582                                                 sizeof(uint32_t);
2583         dev_info->reta_size = pf->hash_lut_size;
2584         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2585
2586         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2587                 .rx_thresh = {
2588                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2589                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2590                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2591                 },
2592                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2593                 .rx_drop_en = 0,
2594         };
2595
2596         dev_info->default_txconf = (struct rte_eth_txconf) {
2597                 .tx_thresh = {
2598                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2599                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2600                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2601                 },
2602                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2603                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2604                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2605                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2606         };
2607
2608         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2609                 .nb_max = I40E_MAX_RING_DESC,
2610                 .nb_min = I40E_MIN_RING_DESC,
2611                 .nb_align = I40E_ALIGN_RING_DESC,
2612         };
2613
2614         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2615                 .nb_max = I40E_MAX_RING_DESC,
2616                 .nb_min = I40E_MIN_RING_DESC,
2617                 .nb_align = I40E_ALIGN_RING_DESC,
2618         };
2619
2620         if (pf->flags & I40E_FLAG_VMDQ) {
2621                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2622                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2623                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2624                                                 pf->max_nb_vmdq_vsi;
2625                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2626                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2627                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2628         }
2629
2630         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2631                 /* For XL710 */
2632                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2633         else
2634                 /* For X710 */
2635                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2636 }
2637
2638 static int
2639 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2640 {
2641         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2642         struct i40e_vsi *vsi = pf->main_vsi;
2643         PMD_INIT_FUNC_TRACE();
2644
2645         if (on)
2646                 return i40e_vsi_add_vlan(vsi, vlan_id);
2647         else
2648                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2649 }
2650
2651 static int
2652 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2653                    enum rte_vlan_type vlan_type,
2654                    uint16_t tpid)
2655 {
2656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657         uint64_t reg_r = 0, reg_w = 0;
2658         uint16_t reg_id = 0;
2659         int ret = 0;
2660         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2661
2662         switch (vlan_type) {
2663         case ETH_VLAN_TYPE_OUTER:
2664                 if (qinq)
2665                         reg_id = 2;
2666                 else
2667                         reg_id = 3;
2668                 break;
2669         case ETH_VLAN_TYPE_INNER:
2670                 if (qinq)
2671                         reg_id = 3;
2672                 else {
2673                         ret = -EINVAL;
2674                         PMD_DRV_LOG(ERR,
2675                                 "Unsupported vlan type in single vlan.\n");
2676                         return ret;
2677                 }
2678                 break;
2679         default:
2680                 ret = -EINVAL;
2681                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2682                 return ret;
2683         }
2684         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2685                                           &reg_r, NULL);
2686         if (ret != I40E_SUCCESS) {
2687                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2688                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2689                 ret = -EIO;
2690                 return ret;
2691         }
2692         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2693                     "0x%08"PRIx64"", reg_id, reg_r);
2694
2695         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2696         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2697         if (reg_r == reg_w) {
2698                 ret = 0;
2699                 PMD_DRV_LOG(DEBUG, "No need to write");
2700                 return ret;
2701         }
2702
2703         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2704                                            reg_w, NULL);
2705         if (ret != I40E_SUCCESS) {
2706                 ret = -EIO;
2707                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2708                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2709                 return ret;
2710         }
2711         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2712                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2713
2714         return ret;
2715 }
2716
2717 static void
2718 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2719 {
2720         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2721         struct i40e_vsi *vsi = pf->main_vsi;
2722
2723         if (mask & ETH_VLAN_FILTER_MASK) {
2724                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2725                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2726                 else
2727                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2728         }
2729
2730         if (mask & ETH_VLAN_STRIP_MASK) {
2731                 /* Enable or disable VLAN stripping */
2732                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2733                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2734                 else
2735                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2736         }
2737
2738         if (mask & ETH_VLAN_EXTEND_MASK) {
2739                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2740                         i40e_vsi_config_double_vlan(vsi, TRUE);
2741                         /* Set global registers with default ether type value */
2742                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2743                                            ETHER_TYPE_VLAN);
2744                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2745                                            ETHER_TYPE_VLAN);
2746                 }
2747                 else
2748                         i40e_vsi_config_double_vlan(vsi, FALSE);
2749         }
2750 }
2751
2752 static void
2753 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2754                           __rte_unused uint16_t queue,
2755                           __rte_unused int on)
2756 {
2757         PMD_INIT_FUNC_TRACE();
2758 }
2759
2760 static int
2761 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2762 {
2763         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2764         struct i40e_vsi *vsi = pf->main_vsi;
2765         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2766         struct i40e_vsi_vlan_pvid_info info;
2767
2768         memset(&info, 0, sizeof(info));
2769         info.on = on;
2770         if (info.on)
2771                 info.config.pvid = pvid;
2772         else {
2773                 info.config.reject.tagged =
2774                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2775                 info.config.reject.untagged =
2776                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2777         }
2778
2779         return i40e_vsi_vlan_pvid_set(vsi, &info);
2780 }
2781
2782 static int
2783 i40e_dev_led_on(struct rte_eth_dev *dev)
2784 {
2785         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786         uint32_t mode = i40e_led_get(hw);
2787
2788         if (mode == 0)
2789                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2790
2791         return 0;
2792 }
2793
2794 static int
2795 i40e_dev_led_off(struct rte_eth_dev *dev)
2796 {
2797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2798         uint32_t mode = i40e_led_get(hw);
2799
2800         if (mode != 0)
2801                 i40e_led_set(hw, 0, false);
2802
2803         return 0;
2804 }
2805
2806 static int
2807 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2808 {
2809         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811
2812         fc_conf->pause_time = pf->fc_conf.pause_time;
2813         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2814         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2815
2816          /* Return current mode according to actual setting*/
2817         switch (hw->fc.current_mode) {
2818         case I40E_FC_FULL:
2819                 fc_conf->mode = RTE_FC_FULL;
2820                 break;
2821         case I40E_FC_TX_PAUSE:
2822                 fc_conf->mode = RTE_FC_TX_PAUSE;
2823                 break;
2824         case I40E_FC_RX_PAUSE:
2825                 fc_conf->mode = RTE_FC_RX_PAUSE;
2826                 break;
2827         case I40E_FC_NONE:
2828         default:
2829                 fc_conf->mode = RTE_FC_NONE;
2830         };
2831
2832         return 0;
2833 }
2834
2835 static int
2836 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2837 {
2838         uint32_t mflcn_reg, fctrl_reg, reg;
2839         uint32_t max_high_water;
2840         uint8_t i, aq_failure;
2841         int err;
2842         struct i40e_hw *hw;
2843         struct i40e_pf *pf;
2844         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2845                 [RTE_FC_NONE] = I40E_FC_NONE,
2846                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2847                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2848                 [RTE_FC_FULL] = I40E_FC_FULL
2849         };
2850
2851         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2852
2853         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2854         if ((fc_conf->high_water > max_high_water) ||
2855                         (fc_conf->high_water < fc_conf->low_water)) {
2856                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2857                         "High_water must <= %d.", max_high_water);
2858                 return -EINVAL;
2859         }
2860
2861         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2863         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2864
2865         pf->fc_conf.pause_time = fc_conf->pause_time;
2866         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2867         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2868
2869         PMD_INIT_FUNC_TRACE();
2870
2871         /* All the link flow control related enable/disable register
2872          * configuration is handle by the F/W
2873          */
2874         err = i40e_set_fc(hw, &aq_failure, true);
2875         if (err < 0)
2876                 return -ENOSYS;
2877
2878         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2879                 /* Configure flow control refresh threshold,
2880                  * the value for stat_tx_pause_refresh_timer[8]
2881                  * is used for global pause operation.
2882                  */
2883
2884                 I40E_WRITE_REG(hw,
2885                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2886                                pf->fc_conf.pause_time);
2887
2888                 /* configure the timer value included in transmitted pause
2889                  * frame,
2890                  * the value for stat_tx_pause_quanta[8] is used for global
2891                  * pause operation
2892                  */
2893                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2894                                pf->fc_conf.pause_time);
2895
2896                 fctrl_reg = I40E_READ_REG(hw,
2897                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2898
2899                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2900                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2901                 else
2902                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2903
2904                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2905                                fctrl_reg);
2906         } else {
2907                 /* Configure pause time (2 TCs per register) */
2908                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2909                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2910                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2911
2912                 /* Configure flow control refresh threshold value */
2913                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2914                                pf->fc_conf.pause_time / 2);
2915
2916                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2917
2918                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2919                  *depending on configuration
2920                  */
2921                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2922                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2923                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2924                 } else {
2925                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2926                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2927                 }
2928
2929                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2930         }
2931
2932         /* config the water marker both based on the packets and bytes */
2933         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2934                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2935                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2936         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2937                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2938                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2939         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2940                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2941                        << I40E_KILOSHIFT);
2942         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2943                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2944                        << I40E_KILOSHIFT);
2945
2946         I40E_WRITE_FLUSH(hw);
2947
2948         return 0;
2949 }
2950
2951 static int
2952 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2953                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2954 {
2955         PMD_INIT_FUNC_TRACE();
2956
2957         return -ENOSYS;
2958 }
2959
2960 /* Add a MAC address, and update filters */
2961 static void
2962 i40e_macaddr_add(struct rte_eth_dev *dev,
2963                  struct ether_addr *mac_addr,
2964                  __rte_unused uint32_t index,
2965                  uint32_t pool)
2966 {
2967         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2968         struct i40e_mac_filter_info mac_filter;
2969         struct i40e_vsi *vsi;
2970         int ret;
2971
2972         /* If VMDQ not enabled or configured, return */
2973         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2974                           !pf->nb_cfg_vmdq_vsi)) {
2975                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2976                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2977                         pool);
2978                 return;
2979         }
2980
2981         if (pool > pf->nb_cfg_vmdq_vsi) {
2982                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2983                                 pool, pf->nb_cfg_vmdq_vsi);
2984                 return;
2985         }
2986
2987         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2988         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2989                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2990         else
2991                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2992
2993         if (pool == 0)
2994                 vsi = pf->main_vsi;
2995         else
2996                 vsi = pf->vmdq[pool - 1].vsi;
2997
2998         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2999         if (ret != I40E_SUCCESS) {
3000                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3001                 return;
3002         }
3003 }
3004
3005 /* Remove a MAC address, and update filters */
3006 static void
3007 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3008 {
3009         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3010         struct i40e_vsi *vsi;
3011         struct rte_eth_dev_data *data = dev->data;
3012         struct ether_addr *macaddr;
3013         int ret;
3014         uint32_t i;
3015         uint64_t pool_sel;
3016
3017         macaddr = &(data->mac_addrs[index]);
3018
3019         pool_sel = dev->data->mac_pool_sel[index];
3020
3021         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3022                 if (pool_sel & (1ULL << i)) {
3023                         if (i == 0)
3024                                 vsi = pf->main_vsi;
3025                         else {
3026                                 /* No VMDQ pool enabled or configured */
3027                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3028                                         (i > pf->nb_cfg_vmdq_vsi)) {
3029                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3030                                                         "/configured");
3031                                         return;
3032                                 }
3033                                 vsi = pf->vmdq[i - 1].vsi;
3034                         }
3035                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3036
3037                         if (ret) {
3038                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3039                                 return;
3040                         }
3041                 }
3042         }
3043 }
3044
3045 /* Set perfect match or hash match of MAC and VLAN for a VF */
3046 static int
3047 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3048                  struct rte_eth_mac_filter *filter,
3049                  bool add)
3050 {
3051         struct i40e_hw *hw;
3052         struct i40e_mac_filter_info mac_filter;
3053         struct ether_addr old_mac;
3054         struct ether_addr *new_mac;
3055         struct i40e_pf_vf *vf = NULL;
3056         uint16_t vf_id;
3057         int ret;
3058
3059         if (pf == NULL) {
3060                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3061                 return -EINVAL;
3062         }
3063         hw = I40E_PF_TO_HW(pf);
3064
3065         if (filter == NULL) {
3066                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3067                 return -EINVAL;
3068         }
3069
3070         new_mac = &filter->mac_addr;
3071
3072         if (is_zero_ether_addr(new_mac)) {
3073                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3074                 return -EINVAL;
3075         }
3076
3077         vf_id = filter->dst_id;
3078
3079         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3080                 PMD_DRV_LOG(ERR, "Invalid argument.");
3081                 return -EINVAL;
3082         }
3083         vf = &pf->vfs[vf_id];
3084
3085         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3086                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3087                 return -EINVAL;
3088         }
3089
3090         if (add) {
3091                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3092                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3093                                 ETHER_ADDR_LEN);
3094                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3095                                  ETHER_ADDR_LEN);
3096
3097                 mac_filter.filter_type = filter->filter_type;
3098                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3099                 if (ret != I40E_SUCCESS) {
3100                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3101                         return -1;
3102                 }
3103                 ether_addr_copy(new_mac, &pf->dev_addr);
3104         } else {
3105                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3106                                 ETHER_ADDR_LEN);
3107                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3108                 if (ret != I40E_SUCCESS) {
3109                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3110                         return -1;
3111                 }
3112
3113                 /* Clear device address as it has been removed */
3114                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3115                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3116         }
3117
3118         return 0;
3119 }
3120
3121 /* MAC filter handle */
3122 static int
3123 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3124                 void *arg)
3125 {
3126         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3127         struct rte_eth_mac_filter *filter;
3128         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3129         int ret = I40E_NOT_SUPPORTED;
3130
3131         filter = (struct rte_eth_mac_filter *)(arg);
3132
3133         switch (filter_op) {
3134         case RTE_ETH_FILTER_NOP:
3135                 ret = I40E_SUCCESS;
3136                 break;
3137         case RTE_ETH_FILTER_ADD:
3138                 i40e_pf_disable_irq0(hw);
3139                 if (filter->is_vf)
3140                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3141                 i40e_pf_enable_irq0(hw);
3142                 break;
3143         case RTE_ETH_FILTER_DELETE:
3144                 i40e_pf_disable_irq0(hw);
3145                 if (filter->is_vf)
3146                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3147                 i40e_pf_enable_irq0(hw);
3148                 break;
3149         default:
3150                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3151                 ret = I40E_ERR_PARAM;
3152                 break;
3153         }
3154
3155         return ret;
3156 }
3157
3158 static int
3159 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3160 {
3161         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3162         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3163         int ret;
3164
3165         if (!lut)
3166                 return -EINVAL;
3167
3168         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3169                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3170                                           lut, lut_size);
3171                 if (ret) {
3172                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3173                         return ret;
3174                 }
3175         } else {
3176                 uint32_t *lut_dw = (uint32_t *)lut;
3177                 uint16_t i, lut_size_dw = lut_size / 4;
3178
3179                 for (i = 0; i < lut_size_dw; i++)
3180                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3181         }
3182
3183         return 0;
3184 }
3185
3186 static int
3187 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3188 {
3189         struct i40e_pf *pf;
3190         struct i40e_hw *hw;
3191         int ret;
3192
3193         if (!vsi || !lut)
3194                 return -EINVAL;
3195
3196         pf = I40E_VSI_TO_PF(vsi);
3197         hw = I40E_VSI_TO_HW(vsi);
3198
3199         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3200                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3201                                           lut, lut_size);
3202                 if (ret) {
3203                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3204                         return ret;
3205                 }
3206         } else {
3207                 uint32_t *lut_dw = (uint32_t *)lut;
3208                 uint16_t i, lut_size_dw = lut_size / 4;
3209
3210                 for (i = 0; i < lut_size_dw; i++)
3211                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3212                 I40E_WRITE_FLUSH(hw);
3213         }
3214
3215         return 0;
3216 }
3217
3218 static int
3219 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3220                          struct rte_eth_rss_reta_entry64 *reta_conf,
3221                          uint16_t reta_size)
3222 {
3223         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3224         uint16_t i, lut_size = pf->hash_lut_size;
3225         uint16_t idx, shift;
3226         uint8_t *lut;
3227         int ret;
3228
3229         if (reta_size != lut_size ||
3230                 reta_size > ETH_RSS_RETA_SIZE_512) {
3231                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3232                         "(%d) doesn't match the number hardware can supported "
3233                                         "(%d)\n", reta_size, lut_size);
3234                 return -EINVAL;
3235         }
3236
3237         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3238         if (!lut) {
3239                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3240                 return -ENOMEM;
3241         }
3242         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3243         if (ret)
3244                 goto out;
3245         for (i = 0; i < reta_size; i++) {
3246                 idx = i / RTE_RETA_GROUP_SIZE;
3247                 shift = i % RTE_RETA_GROUP_SIZE;
3248                 if (reta_conf[idx].mask & (1ULL << shift))
3249                         lut[i] = reta_conf[idx].reta[shift];
3250         }
3251         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3252
3253 out:
3254         rte_free(lut);
3255
3256         return ret;
3257 }
3258
3259 static int
3260 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3261                         struct rte_eth_rss_reta_entry64 *reta_conf,
3262                         uint16_t reta_size)
3263 {
3264         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3265         uint16_t i, lut_size = pf->hash_lut_size;
3266         uint16_t idx, shift;
3267         uint8_t *lut;
3268         int ret;
3269
3270         if (reta_size != lut_size ||
3271                 reta_size > ETH_RSS_RETA_SIZE_512) {
3272                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3273                         "(%d) doesn't match the number hardware can supported "
3274                                         "(%d)\n", reta_size, lut_size);
3275                 return -EINVAL;
3276         }
3277
3278         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3279         if (!lut) {
3280                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3281                 return -ENOMEM;
3282         }
3283
3284         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3285         if (ret)
3286                 goto out;
3287         for (i = 0; i < reta_size; i++) {
3288                 idx = i / RTE_RETA_GROUP_SIZE;
3289                 shift = i % RTE_RETA_GROUP_SIZE;
3290                 if (reta_conf[idx].mask & (1ULL << shift))
3291                         reta_conf[idx].reta[shift] = lut[i];
3292         }
3293
3294 out:
3295         rte_free(lut);
3296
3297         return ret;
3298 }
3299
3300 /**
3301  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3302  * @hw:   pointer to the HW structure
3303  * @mem:  pointer to mem struct to fill out
3304  * @size: size of memory requested
3305  * @alignment: what to align the allocation to
3306  **/
3307 enum i40e_status_code
3308 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3309                         struct i40e_dma_mem *mem,
3310                         u64 size,
3311                         u32 alignment)
3312 {
3313         const struct rte_memzone *mz = NULL;
3314         char z_name[RTE_MEMZONE_NAMESIZE];
3315
3316         if (!mem)
3317                 return I40E_ERR_PARAM;
3318
3319         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3320         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3321                                          alignment, RTE_PGSIZE_2M);
3322         if (!mz)
3323                 return I40E_ERR_NO_MEMORY;
3324
3325         mem->size = size;
3326         mem->va = mz->addr;
3327         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3328         mem->zone = (const void *)mz;
3329         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3330                     "%"PRIu64, mz->name, mem->pa);
3331
3332         return I40E_SUCCESS;
3333 }
3334
3335 /**
3336  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3337  * @hw:   pointer to the HW structure
3338  * @mem:  ptr to mem struct to free
3339  **/
3340 enum i40e_status_code
3341 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3342                     struct i40e_dma_mem *mem)
3343 {
3344         if (!mem)
3345                 return I40E_ERR_PARAM;
3346
3347         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3348                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3349                     mem->pa);
3350         rte_memzone_free((const struct rte_memzone *)mem->zone);
3351         mem->zone = NULL;
3352         mem->va = NULL;
3353         mem->pa = (u64)0;
3354
3355         return I40E_SUCCESS;
3356 }
3357
3358 /**
3359  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3360  * @hw:   pointer to the HW structure
3361  * @mem:  pointer to mem struct to fill out
3362  * @size: size of memory requested
3363  **/
3364 enum i40e_status_code
3365 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3366                          struct i40e_virt_mem *mem,
3367                          u32 size)
3368 {
3369         if (!mem)
3370                 return I40E_ERR_PARAM;
3371
3372         mem->size = size;
3373         mem->va = rte_zmalloc("i40e", size, 0);
3374
3375         if (mem->va)
3376                 return I40E_SUCCESS;
3377         else
3378                 return I40E_ERR_NO_MEMORY;
3379 }
3380
3381 /**
3382  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3383  * @hw:   pointer to the HW structure
3384  * @mem:  pointer to mem struct to free
3385  **/
3386 enum i40e_status_code
3387 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3388                      struct i40e_virt_mem *mem)
3389 {
3390         if (!mem)
3391                 return I40E_ERR_PARAM;
3392
3393         rte_free(mem->va);
3394         mem->va = NULL;
3395
3396         return I40E_SUCCESS;
3397 }
3398
3399 void
3400 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3401 {
3402         rte_spinlock_init(&sp->spinlock);
3403 }
3404
3405 void
3406 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3407 {
3408         rte_spinlock_lock(&sp->spinlock);
3409 }
3410
3411 void
3412 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3413 {
3414         rte_spinlock_unlock(&sp->spinlock);
3415 }
3416
3417 void
3418 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3419 {
3420         return;
3421 }
3422
3423 /**
3424  * Get the hardware capabilities, which will be parsed
3425  * and saved into struct i40e_hw.
3426  */
3427 static int
3428 i40e_get_cap(struct i40e_hw *hw)
3429 {
3430         struct i40e_aqc_list_capabilities_element_resp *buf;
3431         uint16_t len, size = 0;
3432         int ret;
3433
3434         /* Calculate a huge enough buff for saving response data temporarily */
3435         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3436                                                 I40E_MAX_CAP_ELE_NUM;
3437         buf = rte_zmalloc("i40e", len, 0);
3438         if (!buf) {
3439                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3440                 return I40E_ERR_NO_MEMORY;
3441         }
3442
3443         /* Get, parse the capabilities and save it to hw */
3444         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3445                         i40e_aqc_opc_list_func_capabilities, NULL);
3446         if (ret != I40E_SUCCESS)
3447                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3448
3449         /* Free the temporary buffer after being used */
3450         rte_free(buf);
3451
3452         return ret;
3453 }
3454
3455 static int
3456 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3457 {
3458         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3459         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3460         uint16_t qp_count = 0, vsi_count = 0;
3461
3462         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3463                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3464                 return -EINVAL;
3465         }
3466         /* Add the parameter init for LFC */
3467         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3468         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3469         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3470
3471         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3472         pf->max_num_vsi = hw->func_caps.num_vsis;
3473         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3474         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3475         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3476
3477         /* FDir queue/VSI allocation */
3478         pf->fdir_qp_offset = 0;
3479         if (hw->func_caps.fd) {
3480                 pf->flags |= I40E_FLAG_FDIR;
3481                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3482         } else {
3483                 pf->fdir_nb_qps = 0;
3484         }
3485         qp_count += pf->fdir_nb_qps;
3486         vsi_count += 1;
3487
3488         /* LAN queue/VSI allocation */
3489         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3490         if (!hw->func_caps.rss) {
3491                 pf->lan_nb_qps = 1;
3492         } else {
3493                 pf->flags |= I40E_FLAG_RSS;
3494                 if (hw->mac.type == I40E_MAC_X722)
3495                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3496                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3497         }
3498         qp_count += pf->lan_nb_qps;
3499         vsi_count += 1;
3500
3501         /* VF queue/VSI allocation */
3502         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3503         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3504                 pf->flags |= I40E_FLAG_SRIOV;
3505                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3506                 pf->vf_num = dev->pci_dev->max_vfs;
3507                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3508                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3509                             pf->vf_nb_qps * pf->vf_num);
3510         } else {
3511                 pf->vf_nb_qps = 0;
3512                 pf->vf_num = 0;
3513         }
3514         qp_count += pf->vf_nb_qps * pf->vf_num;
3515         vsi_count += pf->vf_num;
3516
3517         /* VMDq queue/VSI allocation */
3518         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3519         pf->vmdq_nb_qps = 0;
3520         pf->max_nb_vmdq_vsi = 0;
3521         if (hw->func_caps.vmdq) {
3522                 if (qp_count < hw->func_caps.num_tx_qp &&
3523                         vsi_count < hw->func_caps.num_vsis) {
3524                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3525                                 qp_count) / pf->vmdq_nb_qp_max;
3526
3527                         /* Limit the maximum number of VMDq vsi to the maximum
3528                          * ethdev can support
3529                          */
3530                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3531                                 hw->func_caps.num_vsis - vsi_count);
3532                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3533                                 ETH_64_POOLS);
3534                         if (pf->max_nb_vmdq_vsi) {
3535                                 pf->flags |= I40E_FLAG_VMDQ;
3536                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3537                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3538                                             "per VMDQ VSI, in total %u queues",
3539                                             pf->max_nb_vmdq_vsi,
3540                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3541                                             pf->max_nb_vmdq_vsi);
3542                         } else {
3543                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3544                                             "VMDq");
3545                         }
3546                 } else {
3547                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3548                 }
3549         }
3550         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3551         vsi_count += pf->max_nb_vmdq_vsi;
3552
3553         if (hw->func_caps.dcb)
3554                 pf->flags |= I40E_FLAG_DCB;
3555
3556         if (qp_count > hw->func_caps.num_tx_qp) {
3557                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3558                             "the hardware maximum %u", qp_count,
3559                             hw->func_caps.num_tx_qp);
3560                 return -EINVAL;
3561         }
3562         if (vsi_count > hw->func_caps.num_vsis) {
3563                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3564                             "the hardware maximum %u", vsi_count,
3565                             hw->func_caps.num_vsis);
3566                 return -EINVAL;
3567         }
3568
3569         return 0;
3570 }
3571
3572 static int
3573 i40e_pf_get_switch_config(struct i40e_pf *pf)
3574 {
3575         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3576         struct i40e_aqc_get_switch_config_resp *switch_config;
3577         struct i40e_aqc_switch_config_element_resp *element;
3578         uint16_t start_seid = 0, num_reported;
3579         int ret;
3580
3581         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3582                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3583         if (!switch_config) {
3584                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3585                 return -ENOMEM;
3586         }
3587
3588         /* Get the switch configurations */
3589         ret = i40e_aq_get_switch_config(hw, switch_config,
3590                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3591         if (ret != I40E_SUCCESS) {
3592                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3593                 goto fail;
3594         }
3595         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3596         if (num_reported != 1) { /* The number should be 1 */
3597                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3598                 goto fail;
3599         }
3600
3601         /* Parse the switch configuration elements */
3602         element = &(switch_config->element[0]);
3603         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3604                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3605                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3606         } else
3607                 PMD_DRV_LOG(INFO, "Unknown element type");
3608
3609 fail:
3610         rte_free(switch_config);
3611
3612         return ret;
3613 }
3614
3615 static int
3616 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3617                         uint32_t num)
3618 {
3619         struct pool_entry *entry;
3620
3621         if (pool == NULL || num == 0)
3622                 return -EINVAL;
3623
3624         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3625         if (entry == NULL) {
3626                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3627                 return -ENOMEM;
3628         }
3629
3630         /* queue heap initialize */
3631         pool->num_free = num;
3632         pool->num_alloc = 0;
3633         pool->base = base;
3634         LIST_INIT(&pool->alloc_list);
3635         LIST_INIT(&pool->free_list);
3636
3637         /* Initialize element  */
3638         entry->base = 0;
3639         entry->len = num;
3640
3641         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3642         return 0;
3643 }
3644
3645 static void
3646 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3647 {
3648         struct pool_entry *entry, *next_entry;
3649
3650         if (pool == NULL)
3651                 return;
3652
3653         for (entry = LIST_FIRST(&pool->alloc_list);
3654                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3655                         entry = next_entry) {
3656                 LIST_REMOVE(entry, next);
3657                 rte_free(entry);
3658         }
3659
3660         for (entry = LIST_FIRST(&pool->free_list);
3661                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3662                         entry = next_entry) {
3663                 LIST_REMOVE(entry, next);
3664                 rte_free(entry);
3665         }
3666
3667         pool->num_free = 0;
3668         pool->num_alloc = 0;
3669         pool->base = 0;
3670         LIST_INIT(&pool->alloc_list);
3671         LIST_INIT(&pool->free_list);
3672 }
3673
3674 static int
3675 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3676                        uint32_t base)
3677 {
3678         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3679         uint32_t pool_offset;
3680         int insert;
3681
3682         if (pool == NULL) {
3683                 PMD_DRV_LOG(ERR, "Invalid parameter");
3684                 return -EINVAL;
3685         }
3686
3687         pool_offset = base - pool->base;
3688         /* Lookup in alloc list */
3689         LIST_FOREACH(entry, &pool->alloc_list, next) {
3690                 if (entry->base == pool_offset) {
3691                         valid_entry = entry;
3692                         LIST_REMOVE(entry, next);
3693                         break;
3694                 }
3695         }
3696
3697         /* Not find, return */
3698         if (valid_entry == NULL) {
3699                 PMD_DRV_LOG(ERR, "Failed to find entry");
3700                 return -EINVAL;
3701         }
3702
3703         /**
3704          * Found it, move it to free list  and try to merge.
3705          * In order to make merge easier, always sort it by qbase.
3706          * Find adjacent prev and last entries.
3707          */
3708         prev = next = NULL;
3709         LIST_FOREACH(entry, &pool->free_list, next) {
3710                 if (entry->base > valid_entry->base) {
3711                         next = entry;
3712                         break;
3713                 }
3714                 prev = entry;
3715         }
3716
3717         insert = 0;
3718         /* Try to merge with next one*/
3719         if (next != NULL) {
3720                 /* Merge with next one */
3721                 if (valid_entry->base + valid_entry->len == next->base) {
3722                         next->base = valid_entry->base;
3723                         next->len += valid_entry->len;
3724                         rte_free(valid_entry);
3725                         valid_entry = next;
3726                         insert = 1;
3727                 }
3728         }
3729
3730         if (prev != NULL) {
3731                 /* Merge with previous one */
3732                 if (prev->base + prev->len == valid_entry->base) {
3733                         prev->len += valid_entry->len;
3734                         /* If it merge with next one, remove next node */
3735                         if (insert == 1) {
3736                                 LIST_REMOVE(valid_entry, next);
3737                                 rte_free(valid_entry);
3738                         } else {
3739                                 rte_free(valid_entry);
3740                                 insert = 1;
3741                         }
3742                 }
3743         }
3744
3745         /* Not find any entry to merge, insert */
3746         if (insert == 0) {
3747                 if (prev != NULL)
3748                         LIST_INSERT_AFTER(prev, valid_entry, next);
3749                 else if (next != NULL)
3750                         LIST_INSERT_BEFORE(next, valid_entry, next);
3751                 else /* It's empty list, insert to head */
3752                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3753         }
3754
3755         pool->num_free += valid_entry->len;
3756         pool->num_alloc -= valid_entry->len;
3757
3758         return 0;
3759 }
3760
3761 static int
3762 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3763                        uint16_t num)
3764 {
3765         struct pool_entry *entry, *valid_entry;
3766
3767         if (pool == NULL || num == 0) {
3768                 PMD_DRV_LOG(ERR, "Invalid parameter");
3769                 return -EINVAL;
3770         }
3771
3772         if (pool->num_free < num) {
3773                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3774                             num, pool->num_free);
3775                 return -ENOMEM;
3776         }
3777
3778         valid_entry = NULL;
3779         /* Lookup  in free list and find most fit one */
3780         LIST_FOREACH(entry, &pool->free_list, next) {
3781                 if (entry->len >= num) {
3782                         /* Find best one */
3783                         if (entry->len == num) {
3784                                 valid_entry = entry;
3785                                 break;
3786                         }
3787                         if (valid_entry == NULL || valid_entry->len > entry->len)
3788                                 valid_entry = entry;
3789                 }
3790         }
3791
3792         /* Not find one to satisfy the request, return */
3793         if (valid_entry == NULL) {
3794                 PMD_DRV_LOG(ERR, "No valid entry found");
3795                 return -ENOMEM;
3796         }
3797         /**
3798          * The entry have equal queue number as requested,
3799          * remove it from alloc_list.
3800          */
3801         if (valid_entry->len == num) {
3802                 LIST_REMOVE(valid_entry, next);
3803         } else {
3804                 /**
3805                  * The entry have more numbers than requested,
3806                  * create a new entry for alloc_list and minus its
3807                  * queue base and number in free_list.
3808                  */
3809                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3810                 if (entry == NULL) {
3811                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3812                                     "resource pool");
3813                         return -ENOMEM;
3814                 }
3815                 entry->base = valid_entry->base;
3816                 entry->len = num;
3817                 valid_entry->base += num;
3818                 valid_entry->len -= num;
3819                 valid_entry = entry;
3820         }
3821
3822         /* Insert it into alloc list, not sorted */
3823         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3824
3825         pool->num_free -= valid_entry->len;
3826         pool->num_alloc += valid_entry->len;
3827
3828         return valid_entry->base + pool->base;
3829 }
3830
3831 /**
3832  * bitmap_is_subset - Check whether src2 is subset of src1
3833  **/
3834 static inline int
3835 bitmap_is_subset(uint8_t src1, uint8_t src2)
3836 {
3837         return !((src1 ^ src2) & src2);
3838 }
3839
3840 static enum i40e_status_code
3841 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3842 {
3843         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3844
3845         /* If DCB is not supported, only default TC is supported */
3846         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3847                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3848                 return I40E_NOT_SUPPORTED;
3849         }
3850
3851         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3852                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3853                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3854                             enabled_tcmap);
3855                 return I40E_NOT_SUPPORTED;
3856         }
3857         return I40E_SUCCESS;
3858 }
3859
3860 int
3861 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3862                                 struct i40e_vsi_vlan_pvid_info *info)
3863 {
3864         struct i40e_hw *hw;
3865         struct i40e_vsi_context ctxt;
3866         uint8_t vlan_flags = 0;
3867         int ret;
3868
3869         if (vsi == NULL || info == NULL) {
3870                 PMD_DRV_LOG(ERR, "invalid parameters");
3871                 return I40E_ERR_PARAM;
3872         }
3873
3874         if (info->on) {
3875                 vsi->info.pvid = info->config.pvid;
3876                 /**
3877                  * If insert pvid is enabled, only tagged pkts are
3878                  * allowed to be sent out.
3879                  */
3880                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3881                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3882         } else {
3883                 vsi->info.pvid = 0;
3884                 if (info->config.reject.tagged == 0)
3885                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3886
3887                 if (info->config.reject.untagged == 0)
3888                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3889         }
3890         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3891                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3892         vsi->info.port_vlan_flags |= vlan_flags;
3893         vsi->info.valid_sections =
3894                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3895         memset(&ctxt, 0, sizeof(ctxt));
3896         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3897         ctxt.seid = vsi->seid;
3898
3899         hw = I40E_VSI_TO_HW(vsi);
3900         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3901         if (ret != I40E_SUCCESS)
3902                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3903
3904         return ret;
3905 }
3906
3907 static int
3908 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3909 {
3910         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3911         int i, ret;
3912         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3913
3914         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3915         if (ret != I40E_SUCCESS)
3916                 return ret;
3917
3918         if (!vsi->seid) {
3919                 PMD_DRV_LOG(ERR, "seid not valid");
3920                 return -EINVAL;
3921         }
3922
3923         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3924         tc_bw_data.tc_valid_bits = enabled_tcmap;
3925         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3926                 tc_bw_data.tc_bw_credits[i] =
3927                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3928
3929         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3930         if (ret != I40E_SUCCESS) {
3931                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3932                 return ret;
3933         }
3934
3935         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3936                                         sizeof(vsi->info.qs_handle));
3937         return I40E_SUCCESS;
3938 }
3939
3940 static enum i40e_status_code
3941 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3942                                  struct i40e_aqc_vsi_properties_data *info,
3943                                  uint8_t enabled_tcmap)
3944 {
3945         enum i40e_status_code ret;
3946         int i, total_tc = 0;
3947         uint16_t qpnum_per_tc, bsf, qp_idx;
3948
3949         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3950         if (ret != I40E_SUCCESS)
3951                 return ret;
3952
3953         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3954                 if (enabled_tcmap & (1 << i))
3955                         total_tc++;
3956         vsi->enabled_tc = enabled_tcmap;
3957
3958         /* Number of queues per enabled TC */
3959         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3960         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3961         bsf = rte_bsf32(qpnum_per_tc);
3962
3963         /* Adjust the queue number to actual queues that can be applied */
3964         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3965                 vsi->nb_qps = qpnum_per_tc * total_tc;
3966
3967         /**
3968          * Configure TC and queue mapping parameters, for enabled TC,
3969          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3970          * default queue will serve it.
3971          */
3972         qp_idx = 0;
3973         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3974                 if (vsi->enabled_tc & (1 << i)) {
3975                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3976                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3977                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3978                         qp_idx += qpnum_per_tc;
3979                 } else
3980                         info->tc_mapping[i] = 0;
3981         }
3982
3983         /* Associate queue number with VSI */
3984         if (vsi->type == I40E_VSI_SRIOV) {
3985                 info->mapping_flags |=
3986                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3987                 for (i = 0; i < vsi->nb_qps; i++)
3988                         info->queue_mapping[i] =
3989                                 rte_cpu_to_le_16(vsi->base_queue + i);
3990         } else {
3991                 info->mapping_flags |=
3992                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3993                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3994         }
3995         info->valid_sections |=
3996                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3997
3998         return I40E_SUCCESS;
3999 }
4000
4001 static int
4002 i40e_veb_release(struct i40e_veb *veb)
4003 {
4004         struct i40e_vsi *vsi;
4005         struct i40e_hw *hw;
4006
4007         if (veb == NULL)
4008                 return -EINVAL;
4009
4010         if (!TAILQ_EMPTY(&veb->head)) {
4011                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4012                 return -EACCES;
4013         }
4014         /* associate_vsi field is NULL for floating VEB */
4015         if (veb->associate_vsi != NULL) {
4016                 vsi = veb->associate_vsi;
4017                 hw = I40E_VSI_TO_HW(vsi);
4018
4019                 vsi->uplink_seid = veb->uplink_seid;
4020                 vsi->veb = NULL;
4021         } else {
4022                 veb->associate_pf->main_vsi->floating_veb = NULL;
4023                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4024         }
4025
4026         i40e_aq_delete_element(hw, veb->seid, NULL);
4027         rte_free(veb);
4028         return I40E_SUCCESS;
4029 }
4030
4031 /* Setup a veb */
4032 static struct i40e_veb *
4033 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4034 {
4035         struct i40e_veb *veb;
4036         int ret;
4037         struct i40e_hw *hw;
4038
4039         if (pf == NULL) {
4040                 PMD_DRV_LOG(ERR,
4041                             "veb setup failed, associated PF shouldn't null");
4042                 return NULL;
4043         }
4044         hw = I40E_PF_TO_HW(pf);
4045
4046         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4047         if (!veb) {
4048                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4049                 goto fail;
4050         }
4051
4052         veb->associate_vsi = vsi;
4053         veb->associate_pf = pf;
4054         TAILQ_INIT(&veb->head);
4055         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4056
4057         /* create floating veb if vsi is NULL */
4058         if (vsi != NULL) {
4059                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4060                                       I40E_DEFAULT_TCMAP, false,
4061                                       &veb->seid, false, NULL);
4062         } else {
4063                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4064                                       true, &veb->seid, false, NULL);
4065         }
4066
4067         if (ret != I40E_SUCCESS) {
4068                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4069                             hw->aq.asq_last_status);
4070                 goto fail;
4071         }
4072
4073         /* get statistics index */
4074         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4075                                 &veb->stats_idx, NULL, NULL, NULL);
4076         if (ret != I40E_SUCCESS) {
4077                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4078                             hw->aq.asq_last_status);
4079                 goto fail;
4080         }
4081         /* Get VEB bandwidth, to be implemented */
4082         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4083         if (vsi)
4084                 vsi->uplink_seid = veb->seid;
4085
4086         return veb;
4087 fail:
4088         rte_free(veb);
4089         return NULL;
4090 }
4091
4092 int
4093 i40e_vsi_release(struct i40e_vsi *vsi)
4094 {
4095         struct i40e_pf *pf;
4096         struct i40e_hw *hw;
4097         struct i40e_vsi_list *vsi_list;
4098         void *temp;
4099         int ret;
4100         struct i40e_mac_filter *f;
4101         uint16_t user_param = vsi->user_param;
4102
4103         if (!vsi)
4104                 return I40E_SUCCESS;
4105
4106         pf = I40E_VSI_TO_PF(vsi);
4107         hw = I40E_VSI_TO_HW(vsi);
4108
4109         /* VSI has child to attach, release child first */
4110         if (vsi->veb) {
4111                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4112                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4113                                 return -1;
4114                 }
4115                 i40e_veb_release(vsi->veb);
4116         }
4117
4118         if (vsi->floating_veb) {
4119                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4120                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4121                                 return -1;
4122                 }
4123         }
4124
4125         /* Remove all macvlan filters of the VSI */
4126         i40e_vsi_remove_all_macvlan_filter(vsi);
4127         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4128                 rte_free(f);
4129
4130         if (vsi->type != I40E_VSI_MAIN &&
4131             ((vsi->type != I40E_VSI_SRIOV) ||
4132             !pf->floating_veb_list[user_param])) {
4133                 /* Remove vsi from parent's sibling list */
4134                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4135                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4136                         return I40E_ERR_PARAM;
4137                 }
4138                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4139                                 &vsi->sib_vsi_list, list);
4140
4141                 /* Remove all switch element of the VSI */
4142                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4143                 if (ret != I40E_SUCCESS)
4144                         PMD_DRV_LOG(ERR, "Failed to delete element");
4145         }
4146
4147         if ((vsi->type == I40E_VSI_SRIOV) &&
4148             pf->floating_veb_list[user_param]) {
4149                 /* Remove vsi from parent's sibling list */
4150                 if (vsi->parent_vsi == NULL ||
4151                     vsi->parent_vsi->floating_veb == NULL) {
4152                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4153                         return I40E_ERR_PARAM;
4154                 }
4155                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4156                              &vsi->sib_vsi_list, list);
4157
4158                 /* Remove all switch element of the VSI */
4159                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4160                 if (ret != I40E_SUCCESS)
4161                         PMD_DRV_LOG(ERR, "Failed to delete element");
4162         }
4163
4164         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4165
4166         if (vsi->type != I40E_VSI_SRIOV)
4167                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4168         rte_free(vsi);
4169
4170         return I40E_SUCCESS;
4171 }
4172
4173 static int
4174 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4175 {
4176         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4177         struct i40e_aqc_remove_macvlan_element_data def_filter;
4178         struct i40e_mac_filter_info filter;
4179         int ret;
4180
4181         if (vsi->type != I40E_VSI_MAIN)
4182                 return I40E_ERR_CONFIG;
4183         memset(&def_filter, 0, sizeof(def_filter));
4184         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4185                                         ETH_ADDR_LEN);
4186         def_filter.vlan_tag = 0;
4187         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4188                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4189         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4190         if (ret != I40E_SUCCESS) {
4191                 struct i40e_mac_filter *f;
4192                 struct ether_addr *mac;
4193
4194                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4195                             "macvlan filter");
4196                 /* It needs to add the permanent mac into mac list */
4197                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4198                 if (f == NULL) {
4199                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4200                         return I40E_ERR_NO_MEMORY;
4201                 }
4202                 mac = &f->mac_info.mac_addr;
4203                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4204                                 ETH_ADDR_LEN);
4205                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4206                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4207                 vsi->mac_num++;
4208
4209                 return ret;
4210         }
4211         (void)rte_memcpy(&filter.mac_addr,
4212                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4213         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4214         return i40e_vsi_add_mac(vsi, &filter);
4215 }
4216
4217 /*
4218  * i40e_vsi_get_bw_config - Query VSI BW Information
4219  * @vsi: the VSI to be queried
4220  *
4221  * Returns 0 on success, negative value on failure
4222  */
4223 static enum i40e_status_code
4224 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4225 {
4226         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4227         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4228         struct i40e_hw *hw = &vsi->adapter->hw;
4229         i40e_status ret;
4230         int i;
4231         uint32_t bw_max;
4232
4233         memset(&bw_config, 0, sizeof(bw_config));
4234         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4235         if (ret != I40E_SUCCESS) {
4236                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4237                             hw->aq.asq_last_status);
4238                 return ret;
4239         }
4240
4241         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4242         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4243                                         &ets_sla_config, NULL);
4244         if (ret != I40E_SUCCESS) {
4245                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4246                             "configuration %u", hw->aq.asq_last_status);
4247                 return ret;
4248         }
4249
4250         /* store and print out BW info */
4251         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4252         vsi->bw_info.bw_max = bw_config.max_bw;
4253         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4254         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4255         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4256                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4257                      I40E_16_BIT_WIDTH);
4258         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4259                 vsi->bw_info.bw_ets_share_credits[i] =
4260                                 ets_sla_config.share_credits[i];
4261                 vsi->bw_info.bw_ets_credits[i] =
4262                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4263                 /* 4 bits per TC, 4th bit is reserved */
4264                 vsi->bw_info.bw_ets_max[i] =
4265                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4266                                   RTE_LEN2MASK(3, uint8_t));
4267                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4268                             vsi->bw_info.bw_ets_share_credits[i]);
4269                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4270                             vsi->bw_info.bw_ets_credits[i]);
4271                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4272                             vsi->bw_info.bw_ets_max[i]);
4273         }
4274
4275         return I40E_SUCCESS;
4276 }
4277
4278 /* i40e_enable_pf_lb
4279  * @pf: pointer to the pf structure
4280  *
4281  * allow loopback on pf
4282  */
4283 static inline void
4284 i40e_enable_pf_lb(struct i40e_pf *pf)
4285 {
4286         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4287         struct i40e_vsi_context ctxt;
4288         int ret;
4289
4290         /* Use the FW API if FW >= v5.0 */
4291         if (hw->aq.fw_maj_ver < 5) {
4292                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4293                 return;
4294         }
4295
4296         memset(&ctxt, 0, sizeof(ctxt));
4297         ctxt.seid = pf->main_vsi_seid;
4298         ctxt.pf_num = hw->pf_id;
4299         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4300         if (ret) {
4301                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4302                             ret, hw->aq.asq_last_status);
4303                 return;
4304         }
4305         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4306         ctxt.info.valid_sections =
4307                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4308         ctxt.info.switch_id |=
4309                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4310
4311         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4312         if (ret)
4313                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4314                             hw->aq.asq_last_status);
4315 }
4316
4317 /* Setup a VSI */
4318 struct i40e_vsi *
4319 i40e_vsi_setup(struct i40e_pf *pf,
4320                enum i40e_vsi_type type,
4321                struct i40e_vsi *uplink_vsi,
4322                uint16_t user_param)
4323 {
4324         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4325         struct i40e_vsi *vsi;
4326         struct i40e_mac_filter_info filter;
4327         int ret;
4328         struct i40e_vsi_context ctxt;
4329         struct ether_addr broadcast =
4330                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4331
4332         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4333             uplink_vsi == NULL) {
4334                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4335                             "VSI link shouldn't be NULL");
4336                 return NULL;
4337         }
4338
4339         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4340                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4341                             "uplink VSI should be NULL");
4342                 return NULL;
4343         }
4344
4345         /* two situations
4346          * 1.type is not MAIN and uplink vsi is not NULL
4347          * If uplink vsi didn't setup VEB, create one first under veb field
4348          * 2.type is SRIOV and the uplink is NULL
4349          * If floating VEB is NULL, create one veb under floating veb field
4350          */
4351
4352         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4353             uplink_vsi->veb == NULL) {
4354                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4355
4356                 if (uplink_vsi->veb == NULL) {
4357                         PMD_DRV_LOG(ERR, "VEB setup failed");
4358                         return NULL;
4359                 }
4360                 /* set ALLOWLOOPBACk on pf, when veb is created */
4361                 i40e_enable_pf_lb(pf);
4362         }
4363
4364         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4365             pf->main_vsi->floating_veb == NULL) {
4366                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4367
4368                 if (pf->main_vsi->floating_veb == NULL) {
4369                         PMD_DRV_LOG(ERR, "VEB setup failed");
4370                         return NULL;
4371                 }
4372         }
4373
4374         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4375         if (!vsi) {
4376                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4377                 return NULL;
4378         }
4379         TAILQ_INIT(&vsi->mac_list);
4380         vsi->type = type;
4381         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4382         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4383         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4384         vsi->user_param = user_param;
4385         /* Allocate queues */
4386         switch (vsi->type) {
4387         case I40E_VSI_MAIN  :
4388                 vsi->nb_qps = pf->lan_nb_qps;
4389                 break;
4390         case I40E_VSI_SRIOV :
4391                 vsi->nb_qps = pf->vf_nb_qps;
4392                 break;
4393         case I40E_VSI_VMDQ2:
4394                 vsi->nb_qps = pf->vmdq_nb_qps;
4395                 break;
4396         case I40E_VSI_FDIR:
4397                 vsi->nb_qps = pf->fdir_nb_qps;
4398                 break;
4399         default:
4400                 goto fail_mem;
4401         }
4402         /*
4403          * The filter status descriptor is reported in rx queue 0,
4404          * while the tx queue for fdir filter programming has no
4405          * such constraints, can be non-zero queues.
4406          * To simplify it, choose FDIR vsi use queue 0 pair.
4407          * To make sure it will use queue 0 pair, queue allocation
4408          * need be done before this function is called
4409          */
4410         if (type != I40E_VSI_FDIR) {
4411                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4412                         if (ret < 0) {
4413                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4414                                                 vsi->seid, ret);
4415                                 goto fail_mem;
4416                         }
4417                         vsi->base_queue = ret;
4418         } else
4419                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4420
4421         /* VF has MSIX interrupt in VF range, don't allocate here */
4422         if (type == I40E_VSI_MAIN) {
4423                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4424                                           RTE_MIN(vsi->nb_qps,
4425                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4426                 if (ret < 0) {
4427                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4428                                     vsi->seid, ret);
4429                         goto fail_queue_alloc;
4430                 }
4431                 vsi->msix_intr = ret;
4432                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4433         } else if (type != I40E_VSI_SRIOV) {
4434                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4435                 if (ret < 0) {
4436                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4437                         goto fail_queue_alloc;
4438                 }
4439                 vsi->msix_intr = ret;
4440                 vsi->nb_msix = 1;
4441         } else {
4442                 vsi->msix_intr = 0;
4443                 vsi->nb_msix = 0;
4444         }
4445
4446         /* Add VSI */
4447         if (type == I40E_VSI_MAIN) {
4448                 /* For main VSI, no need to add since it's default one */
4449                 vsi->uplink_seid = pf->mac_seid;
4450                 vsi->seid = pf->main_vsi_seid;
4451                 /* Bind queues with specific MSIX interrupt */
4452                 /**
4453                  * Needs 2 interrupt at least, one for misc cause which will
4454                  * enabled from OS side, Another for queues binding the
4455                  * interrupt from device side only.
4456                  */
4457
4458                 /* Get default VSI parameters from hardware */
4459                 memset(&ctxt, 0, sizeof(ctxt));
4460                 ctxt.seid = vsi->seid;
4461                 ctxt.pf_num = hw->pf_id;
4462                 ctxt.uplink_seid = vsi->uplink_seid;
4463                 ctxt.vf_num = 0;
4464                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4465                 if (ret != I40E_SUCCESS) {
4466                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4467                         goto fail_msix_alloc;
4468                 }
4469                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4470                         sizeof(struct i40e_aqc_vsi_properties_data));
4471                 vsi->vsi_id = ctxt.vsi_number;
4472                 vsi->info.valid_sections = 0;
4473
4474                 /* Configure tc, enabled TC0 only */
4475                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4476                         I40E_SUCCESS) {
4477                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4478                         goto fail_msix_alloc;
4479                 }
4480
4481                 /* TC, queue mapping */
4482                 memset(&ctxt, 0, sizeof(ctxt));
4483                 vsi->info.valid_sections |=
4484                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4485                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4486                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4487                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4488                         sizeof(struct i40e_aqc_vsi_properties_data));
4489                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4490                                                 I40E_DEFAULT_TCMAP);
4491                 if (ret != I40E_SUCCESS) {
4492                         PMD_DRV_LOG(ERR, "Failed to configure "
4493                                     "TC queue mapping");
4494                         goto fail_msix_alloc;
4495                 }
4496                 ctxt.seid = vsi->seid;
4497                 ctxt.pf_num = hw->pf_id;
4498                 ctxt.uplink_seid = vsi->uplink_seid;
4499                 ctxt.vf_num = 0;
4500
4501                 /* Update VSI parameters */
4502                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4503                 if (ret != I40E_SUCCESS) {
4504                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4505                         goto fail_msix_alloc;
4506                 }
4507
4508                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4509                                                 sizeof(vsi->info.tc_mapping));
4510                 (void)rte_memcpy(&vsi->info.queue_mapping,
4511                                 &ctxt.info.queue_mapping,
4512                         sizeof(vsi->info.queue_mapping));
4513                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4514                 vsi->info.valid_sections = 0;
4515
4516                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4517                                 ETH_ADDR_LEN);
4518
4519                 /**
4520                  * Updating default filter settings are necessary to prevent
4521                  * reception of tagged packets.
4522                  * Some old firmware configurations load a default macvlan
4523                  * filter which accepts both tagged and untagged packets.
4524                  * The updating is to use a normal filter instead if needed.
4525                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4526                  * The firmware with correct configurations load the default
4527                  * macvlan filter which is expected and cannot be removed.
4528                  */
4529                 i40e_update_default_filter_setting(vsi);
4530                 i40e_config_qinq(hw, vsi);
4531         } else if (type == I40E_VSI_SRIOV) {
4532                 memset(&ctxt, 0, sizeof(ctxt));
4533                 /**
4534                  * For other VSI, the uplink_seid equals to uplink VSI's
4535                  * uplink_seid since they share same VEB
4536                  */
4537                 if (uplink_vsi == NULL)
4538                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4539                 else
4540                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4541                 ctxt.pf_num = hw->pf_id;
4542                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4543                 ctxt.uplink_seid = vsi->uplink_seid;
4544                 ctxt.connection_type = 0x1;
4545                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4546
4547                 /* Use the VEB configuration if FW >= v5.0 */
4548                 if (hw->aq.fw_maj_ver >= 5) {
4549                         /* Configure switch ID */
4550                         ctxt.info.valid_sections |=
4551                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4552                         ctxt.info.switch_id =
4553                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4554                 }
4555
4556                 /* Configure port/vlan */
4557                 ctxt.info.valid_sections |=
4558                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4559                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4560                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4561                                                 I40E_DEFAULT_TCMAP);
4562                 if (ret != I40E_SUCCESS) {
4563                         PMD_DRV_LOG(ERR, "Failed to configure "
4564                                     "TC queue mapping");
4565                         goto fail_msix_alloc;
4566                 }
4567                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4568                 ctxt.info.valid_sections |=
4569                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4570                 /**
4571                  * Since VSI is not created yet, only configure parameter,
4572                  * will add vsi below.
4573                  */
4574
4575                 i40e_config_qinq(hw, vsi);
4576         } else if (type == I40E_VSI_VMDQ2) {
4577                 memset(&ctxt, 0, sizeof(ctxt));
4578                 /*
4579                  * For other VSI, the uplink_seid equals to uplink VSI's
4580                  * uplink_seid since they share same VEB
4581                  */
4582                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4583                 ctxt.pf_num = hw->pf_id;
4584                 ctxt.vf_num = 0;
4585                 ctxt.uplink_seid = vsi->uplink_seid;
4586                 ctxt.connection_type = 0x1;
4587                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4588
4589                 ctxt.info.valid_sections |=
4590                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4591                 /* user_param carries flag to enable loop back */
4592                 if (user_param) {
4593                         ctxt.info.switch_id =
4594                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4595                         ctxt.info.switch_id |=
4596                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4597                 }
4598
4599                 /* Configure port/vlan */
4600                 ctxt.info.valid_sections |=
4601                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4602                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4603                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4604                                                 I40E_DEFAULT_TCMAP);
4605                 if (ret != I40E_SUCCESS) {
4606                         PMD_DRV_LOG(ERR, "Failed to configure "
4607                                         "TC queue mapping");
4608                         goto fail_msix_alloc;
4609                 }
4610                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4611                 ctxt.info.valid_sections |=
4612                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4613         } else if (type == I40E_VSI_FDIR) {
4614                 memset(&ctxt, 0, sizeof(ctxt));
4615                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4616                 ctxt.pf_num = hw->pf_id;
4617                 ctxt.vf_num = 0;
4618                 ctxt.uplink_seid = vsi->uplink_seid;
4619                 ctxt.connection_type = 0x1;     /* regular data port */
4620                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4621                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4622                                                 I40E_DEFAULT_TCMAP);
4623                 if (ret != I40E_SUCCESS) {
4624                         PMD_DRV_LOG(ERR, "Failed to configure "
4625                                         "TC queue mapping.");
4626                         goto fail_msix_alloc;
4627                 }
4628                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4629                 ctxt.info.valid_sections |=
4630                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4631         } else {
4632                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4633                 goto fail_msix_alloc;
4634         }
4635
4636         if (vsi->type != I40E_VSI_MAIN) {
4637                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4638                 if (ret != I40E_SUCCESS) {
4639                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4640                                     hw->aq.asq_last_status);
4641                         goto fail_msix_alloc;
4642                 }
4643                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4644                 vsi->info.valid_sections = 0;
4645                 vsi->seid = ctxt.seid;
4646                 vsi->vsi_id = ctxt.vsi_number;
4647                 vsi->sib_vsi_list.vsi = vsi;
4648                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4649                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4650                                           &vsi->sib_vsi_list, list);
4651                 } else {
4652                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4653                                           &vsi->sib_vsi_list, list);
4654                 }
4655         }
4656
4657         /* MAC/VLAN configuration */
4658         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4659         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4660
4661         ret = i40e_vsi_add_mac(vsi, &filter);
4662         if (ret != I40E_SUCCESS) {
4663                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4664                 goto fail_msix_alloc;
4665         }
4666
4667         /* Get VSI BW information */
4668         i40e_vsi_get_bw_config(vsi);
4669         return vsi;
4670 fail_msix_alloc:
4671         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4672 fail_queue_alloc:
4673         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4674 fail_mem:
4675         rte_free(vsi);
4676         return NULL;
4677 }
4678
4679 /* Configure vlan filter on or off */
4680 int
4681 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4682 {
4683         int i, num;
4684         struct i40e_mac_filter *f;
4685         void *temp;
4686         struct i40e_mac_filter_info *mac_filter;
4687         enum rte_mac_filter_type desired_filter;
4688         int ret = I40E_SUCCESS;
4689
4690         if (on) {
4691                 /* Filter to match MAC and VLAN */
4692                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4693         } else {
4694                 /* Filter to match only MAC */
4695                 desired_filter = RTE_MAC_PERFECT_MATCH;
4696         }
4697
4698         num = vsi->mac_num;
4699
4700         mac_filter = rte_zmalloc("mac_filter_info_data",
4701                                  num * sizeof(*mac_filter), 0);
4702         if (mac_filter == NULL) {
4703                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4704                 return I40E_ERR_NO_MEMORY;
4705         }
4706
4707         i = 0;
4708
4709         /* Remove all existing mac */
4710         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4711                 mac_filter[i] = f->mac_info;
4712                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4713                 if (ret) {
4714                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4715                                     on ? "enable" : "disable");
4716                         goto DONE;
4717                 }
4718                 i++;
4719         }
4720
4721         /* Override with new filter */
4722         for (i = 0; i < num; i++) {
4723                 mac_filter[i].filter_type = desired_filter;
4724                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4725                 if (ret) {
4726                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4727                                     on ? "enable" : "disable");
4728                         goto DONE;
4729                 }
4730         }
4731
4732 DONE:
4733         rte_free(mac_filter);
4734         return ret;
4735 }
4736
4737 /* Configure vlan stripping on or off */
4738 int
4739 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4740 {
4741         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4742         struct i40e_vsi_context ctxt;
4743         uint8_t vlan_flags;
4744         int ret = I40E_SUCCESS;
4745
4746         /* Check if it has been already on or off */
4747         if (vsi->info.valid_sections &
4748                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4749                 if (on) {
4750                         if ((vsi->info.port_vlan_flags &
4751                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4752                                 return 0; /* already on */
4753                 } else {
4754                         if ((vsi->info.port_vlan_flags &
4755                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4756                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4757                                 return 0; /* already off */
4758                 }
4759         }
4760
4761         if (on)
4762                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4763         else
4764                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4765         vsi->info.valid_sections =
4766                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4767         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4768         vsi->info.port_vlan_flags |= vlan_flags;
4769         ctxt.seid = vsi->seid;
4770         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4771         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4772         if (ret)
4773                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4774                             on ? "enable" : "disable");
4775
4776         return ret;
4777 }
4778
4779 static int
4780 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4781 {
4782         struct rte_eth_dev_data *data = dev->data;
4783         int ret;
4784         int mask = 0;
4785
4786         /* Apply vlan offload setting */
4787         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4788         i40e_vlan_offload_set(dev, mask);
4789
4790         /* Apply double-vlan setting, not implemented yet */
4791
4792         /* Apply pvid setting */
4793         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4794                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4795         if (ret)
4796                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4797
4798         return ret;
4799 }
4800
4801 static int
4802 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4803 {
4804         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4805
4806         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4807 }
4808
4809 static int
4810 i40e_update_flow_control(struct i40e_hw *hw)
4811 {
4812 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4813         struct i40e_link_status link_status;
4814         uint32_t rxfc = 0, txfc = 0, reg;
4815         uint8_t an_info;
4816         int ret;
4817
4818         memset(&link_status, 0, sizeof(link_status));
4819         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4820         if (ret != I40E_SUCCESS) {
4821                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4822                 goto write_reg; /* Disable flow control */
4823         }
4824
4825         an_info = hw->phy.link_info.an_info;
4826         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4827                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4828                 ret = I40E_ERR_NOT_READY;
4829                 goto write_reg; /* Disable flow control */
4830         }
4831         /**
4832          * If link auto negotiation is enabled, flow control needs to
4833          * be configured according to it
4834          */
4835         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4836         case I40E_LINK_PAUSE_RXTX:
4837                 rxfc = 1;
4838                 txfc = 1;
4839                 hw->fc.current_mode = I40E_FC_FULL;
4840                 break;
4841         case I40E_AQ_LINK_PAUSE_RX:
4842                 rxfc = 1;
4843                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4844                 break;
4845         case I40E_AQ_LINK_PAUSE_TX:
4846                 txfc = 1;
4847                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4848                 break;
4849         default:
4850                 hw->fc.current_mode = I40E_FC_NONE;
4851                 break;
4852         }
4853
4854 write_reg:
4855         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4856                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4857         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4858         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4859         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4860         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4861
4862         return ret;
4863 }
4864
4865 /* PF setup */
4866 static int
4867 i40e_pf_setup(struct i40e_pf *pf)
4868 {
4869         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4870         struct i40e_filter_control_settings settings;
4871         struct i40e_vsi *vsi;
4872         int ret;
4873
4874         /* Clear all stats counters */
4875         pf->offset_loaded = FALSE;
4876         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4877         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4878
4879         ret = i40e_pf_get_switch_config(pf);
4880         if (ret != I40E_SUCCESS) {
4881                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4882                 return ret;
4883         }
4884         if (pf->flags & I40E_FLAG_FDIR) {
4885                 /* make queue allocated first, let FDIR use queue pair 0*/
4886                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4887                 if (ret != I40E_FDIR_QUEUE_ID) {
4888                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4889                                     " ret =%d", ret);
4890                         pf->flags &= ~I40E_FLAG_FDIR;
4891                 }
4892         }
4893         /*  main VSI setup */
4894         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4895         if (!vsi) {
4896                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4897                 return I40E_ERR_NOT_READY;
4898         }
4899         pf->main_vsi = vsi;
4900
4901         /* Configure filter control */
4902         memset(&settings, 0, sizeof(settings));
4903         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4904                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4905         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4906                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4907         else {
4908                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4909                                                 hw->func_caps.rss_table_size);
4910                 return I40E_ERR_PARAM;
4911         }
4912         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4913                         "size: %u\n", hw->func_caps.rss_table_size);
4914         pf->hash_lut_size = hw->func_caps.rss_table_size;
4915
4916         /* Enable ethtype and macvlan filters */
4917         settings.enable_ethtype = TRUE;
4918         settings.enable_macvlan = TRUE;
4919         ret = i40e_set_filter_control(hw, &settings);
4920         if (ret)
4921                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4922                                                                 ret);
4923
4924         /* Update flow control according to the auto negotiation */
4925         i40e_update_flow_control(hw);
4926
4927         return I40E_SUCCESS;
4928 }
4929
4930 int
4931 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4932 {
4933         uint32_t reg;
4934         uint16_t j;
4935
4936         /**
4937          * Set or clear TX Queue Disable flags,
4938          * which is required by hardware.
4939          */
4940         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4941         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4942
4943         /* Wait until the request is finished */
4944         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4945                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4946                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4947                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4948                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4949                                                         & 0x1))) {
4950                         break;
4951                 }
4952         }
4953         if (on) {
4954                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4955                         return I40E_SUCCESS; /* already on, skip next steps */
4956
4957                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4958                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4959         } else {
4960                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4961                         return I40E_SUCCESS; /* already off, skip next steps */
4962                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4963         }
4964         /* Write the register */
4965         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4966         /* Check the result */
4967         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4968                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4969                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4970                 if (on) {
4971                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4972                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4973                                 break;
4974                 } else {
4975                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4976                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4977                                 break;
4978                 }
4979         }
4980         /* Check if it is timeout */
4981         if (j >= I40E_CHK_Q_ENA_COUNT) {
4982                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4983                             (on ? "enable" : "disable"), q_idx);
4984                 return I40E_ERR_TIMEOUT;
4985         }
4986
4987         return I40E_SUCCESS;
4988 }
4989
4990 /* Swith on or off the tx queues */
4991 static int
4992 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4993 {
4994         struct rte_eth_dev_data *dev_data = pf->dev_data;
4995         struct i40e_tx_queue *txq;
4996         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4997         uint16_t i;
4998         int ret;
4999
5000         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5001                 txq = dev_data->tx_queues[i];
5002                 /* Don't operate the queue if not configured or
5003                  * if starting only per queue */
5004                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5005                         continue;
5006                 if (on)
5007                         ret = i40e_dev_tx_queue_start(dev, i);
5008                 else
5009                         ret = i40e_dev_tx_queue_stop(dev, i);
5010                 if ( ret != I40E_SUCCESS)
5011                         return ret;
5012         }
5013
5014         return I40E_SUCCESS;
5015 }
5016
5017 int
5018 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5019 {
5020         uint32_t reg;
5021         uint16_t j;
5022
5023         /* Wait until the request is finished */
5024         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5025                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5026                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5027                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5028                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5029                         break;
5030         }
5031
5032         if (on) {
5033                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5034                         return I40E_SUCCESS; /* Already on, skip next steps */
5035                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5036         } else {
5037                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5038                         return I40E_SUCCESS; /* Already off, skip next steps */
5039                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5040         }
5041
5042         /* Write the register */
5043         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5044         /* Check the result */
5045         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5046                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5047                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5048                 if (on) {
5049                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5050                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5051                                 break;
5052                 } else {
5053                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5054                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5055                                 break;
5056                 }
5057         }
5058
5059         /* Check if it is timeout */
5060         if (j >= I40E_CHK_Q_ENA_COUNT) {
5061                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5062                             (on ? "enable" : "disable"), q_idx);
5063                 return I40E_ERR_TIMEOUT;
5064         }
5065
5066         return I40E_SUCCESS;
5067 }
5068 /* Switch on or off the rx queues */
5069 static int
5070 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5071 {
5072         struct rte_eth_dev_data *dev_data = pf->dev_data;
5073         struct i40e_rx_queue *rxq;
5074         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5075         uint16_t i;
5076         int ret;
5077
5078         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5079                 rxq = dev_data->rx_queues[i];
5080                 /* Don't operate the queue if not configured or
5081                  * if starting only per queue */
5082                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5083                         continue;
5084                 if (on)
5085                         ret = i40e_dev_rx_queue_start(dev, i);
5086                 else
5087                         ret = i40e_dev_rx_queue_stop(dev, i);
5088                 if (ret != I40E_SUCCESS)
5089                         return ret;
5090         }
5091
5092         return I40E_SUCCESS;
5093 }
5094
5095 /* Switch on or off all the rx/tx queues */
5096 int
5097 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5098 {
5099         int ret;
5100
5101         if (on) {
5102                 /* enable rx queues before enabling tx queues */
5103                 ret = i40e_dev_switch_rx_queues(pf, on);
5104                 if (ret) {
5105                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5106                         return ret;
5107                 }
5108                 ret = i40e_dev_switch_tx_queues(pf, on);
5109         } else {
5110                 /* Stop tx queues before stopping rx queues */
5111                 ret = i40e_dev_switch_tx_queues(pf, on);
5112                 if (ret) {
5113                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5114                         return ret;
5115                 }
5116                 ret = i40e_dev_switch_rx_queues(pf, on);
5117         }
5118
5119         return ret;
5120 }
5121
5122 /* Initialize VSI for TX */
5123 static int
5124 i40e_dev_tx_init(struct i40e_pf *pf)
5125 {
5126         struct rte_eth_dev_data *data = pf->dev_data;
5127         uint16_t i;
5128         uint32_t ret = I40E_SUCCESS;
5129         struct i40e_tx_queue *txq;
5130
5131         for (i = 0; i < data->nb_tx_queues; i++) {
5132                 txq = data->tx_queues[i];
5133                 if (!txq || !txq->q_set)
5134                         continue;
5135                 ret = i40e_tx_queue_init(txq);
5136                 if (ret != I40E_SUCCESS)
5137                         break;
5138         }
5139         if (ret == I40E_SUCCESS)
5140                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5141                                      ->eth_dev);
5142
5143         return ret;
5144 }
5145
5146 /* Initialize VSI for RX */
5147 static int
5148 i40e_dev_rx_init(struct i40e_pf *pf)
5149 {
5150         struct rte_eth_dev_data *data = pf->dev_data;
5151         int ret = I40E_SUCCESS;
5152         uint16_t i;
5153         struct i40e_rx_queue *rxq;
5154
5155         i40e_pf_config_mq_rx(pf);
5156         for (i = 0; i < data->nb_rx_queues; i++) {
5157                 rxq = data->rx_queues[i];
5158                 if (!rxq || !rxq->q_set)
5159                         continue;
5160
5161                 ret = i40e_rx_queue_init(rxq);
5162                 if (ret != I40E_SUCCESS) {
5163                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5164                                     "initialization");
5165                         break;
5166                 }
5167         }
5168         if (ret == I40E_SUCCESS)
5169                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5170                                      ->eth_dev);
5171
5172         return ret;
5173 }
5174
5175 static int
5176 i40e_dev_rxtx_init(struct i40e_pf *pf)
5177 {
5178         int err;
5179
5180         err = i40e_dev_tx_init(pf);
5181         if (err) {
5182                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5183                 return err;
5184         }
5185         err = i40e_dev_rx_init(pf);
5186         if (err) {
5187                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5188                 return err;
5189         }
5190
5191         return err;
5192 }
5193
5194 static int
5195 i40e_vmdq_setup(struct rte_eth_dev *dev)
5196 {
5197         struct rte_eth_conf *conf = &dev->data->dev_conf;
5198         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5199         int i, err, conf_vsis, j, loop;
5200         struct i40e_vsi *vsi;
5201         struct i40e_vmdq_info *vmdq_info;
5202         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5203         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5204
5205         /*
5206          * Disable interrupt to avoid message from VF. Furthermore, it will
5207          * avoid race condition in VSI creation/destroy.
5208          */
5209         i40e_pf_disable_irq0(hw);
5210
5211         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5212                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5213                 return -ENOTSUP;
5214         }
5215
5216         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5217         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5218                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5219                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5220                         pf->max_nb_vmdq_vsi);
5221                 return -ENOTSUP;
5222         }
5223
5224         if (pf->vmdq != NULL) {
5225                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5226                 return 0;
5227         }
5228
5229         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5230                                 sizeof(*vmdq_info) * conf_vsis, 0);
5231
5232         if (pf->vmdq == NULL) {
5233                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5234                 return -ENOMEM;
5235         }
5236
5237         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5238
5239         /* Create VMDQ VSI */
5240         for (i = 0; i < conf_vsis; i++) {
5241                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5242                                 vmdq_conf->enable_loop_back);
5243                 if (vsi == NULL) {
5244                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5245                         err = -1;
5246                         goto err_vsi_setup;
5247                 }
5248                 vmdq_info = &pf->vmdq[i];
5249                 vmdq_info->pf = pf;
5250                 vmdq_info->vsi = vsi;
5251         }
5252         pf->nb_cfg_vmdq_vsi = conf_vsis;
5253
5254         /* Configure Vlan */
5255         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5256         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5257                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5258                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5259                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5260                                         vmdq_conf->pool_map[i].vlan_id, j);
5261
5262                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5263                                                 vmdq_conf->pool_map[i].vlan_id);
5264                                 if (err) {
5265                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5266                                         err = -1;
5267                                         goto err_vsi_setup;
5268                                 }
5269                         }
5270                 }
5271         }
5272
5273         i40e_pf_enable_irq0(hw);
5274
5275         return 0;
5276
5277 err_vsi_setup:
5278         for (i = 0; i < conf_vsis; i++)
5279                 if (pf->vmdq[i].vsi == NULL)
5280                         break;
5281                 else
5282                         i40e_vsi_release(pf->vmdq[i].vsi);
5283
5284         rte_free(pf->vmdq);
5285         pf->vmdq = NULL;
5286         i40e_pf_enable_irq0(hw);
5287         return err;
5288 }
5289
5290 static void
5291 i40e_stat_update_32(struct i40e_hw *hw,
5292                    uint32_t reg,
5293                    bool offset_loaded,
5294                    uint64_t *offset,
5295                    uint64_t *stat)
5296 {
5297         uint64_t new_data;
5298
5299         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5300         if (!offset_loaded)
5301                 *offset = new_data;
5302
5303         if (new_data >= *offset)
5304                 *stat = (uint64_t)(new_data - *offset);
5305         else
5306                 *stat = (uint64_t)((new_data +
5307                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5308 }
5309
5310 static void
5311 i40e_stat_update_48(struct i40e_hw *hw,
5312                    uint32_t hireg,
5313                    uint32_t loreg,
5314                    bool offset_loaded,
5315                    uint64_t *offset,
5316                    uint64_t *stat)
5317 {
5318         uint64_t new_data;
5319
5320         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5321         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5322                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5323
5324         if (!offset_loaded)
5325                 *offset = new_data;
5326
5327         if (new_data >= *offset)
5328                 *stat = new_data - *offset;
5329         else
5330                 *stat = (uint64_t)((new_data +
5331                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5332
5333         *stat &= I40E_48_BIT_MASK;
5334 }
5335
5336 /* Disable IRQ0 */
5337 void
5338 i40e_pf_disable_irq0(struct i40e_hw *hw)
5339 {
5340         /* Disable all interrupt types */
5341         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5342         I40E_WRITE_FLUSH(hw);
5343 }
5344
5345 /* Enable IRQ0 */
5346 void
5347 i40e_pf_enable_irq0(struct i40e_hw *hw)
5348 {
5349         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5350                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5351                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5352                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5353         I40E_WRITE_FLUSH(hw);
5354 }
5355
5356 static void
5357 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5358 {
5359         /* read pending request and disable first */
5360         i40e_pf_disable_irq0(hw);
5361         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5362         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5363                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5364
5365         if (no_queue)
5366                 /* Link no queues with irq0 */
5367                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5368                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5369 }
5370
5371 static void
5372 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5373 {
5374         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5375         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5376         int i;
5377         uint16_t abs_vf_id;
5378         uint32_t index, offset, val;
5379
5380         if (!pf->vfs)
5381                 return;
5382         /**
5383          * Try to find which VF trigger a reset, use absolute VF id to access
5384          * since the reg is global register.
5385          */
5386         for (i = 0; i < pf->vf_num; i++) {
5387                 abs_vf_id = hw->func_caps.vf_base_id + i;
5388                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5389                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5390                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5391                 /* VFR event occured */
5392                 if (val & (0x1 << offset)) {
5393                         int ret;
5394
5395                         /* Clear the event first */
5396                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5397                                                         (0x1 << offset));
5398                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5399                         /**
5400                          * Only notify a VF reset event occured,
5401                          * don't trigger another SW reset
5402                          */
5403                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5404                         if (ret != I40E_SUCCESS)
5405                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5406                 }
5407         }
5408 }
5409
5410 static void
5411 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5412 {
5413         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5414         struct i40e_arq_event_info info;
5415         uint16_t pending, opcode;
5416         int ret;
5417
5418         info.buf_len = I40E_AQ_BUF_SZ;
5419         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5420         if (!info.msg_buf) {
5421                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5422                 return;
5423         }
5424
5425         pending = 1;
5426         while (pending) {
5427                 ret = i40e_clean_arq_element(hw, &info, &pending);
5428
5429                 if (ret != I40E_SUCCESS) {
5430                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5431                                     "aq_err: %u", hw->aq.asq_last_status);
5432                         break;
5433                 }
5434                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5435
5436                 switch (opcode) {
5437                 case i40e_aqc_opc_send_msg_to_pf:
5438                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5439                         i40e_pf_host_handle_vf_msg(dev,
5440                                         rte_le_to_cpu_16(info.desc.retval),
5441                                         rte_le_to_cpu_32(info.desc.cookie_high),
5442                                         rte_le_to_cpu_32(info.desc.cookie_low),
5443                                         info.msg_buf,
5444                                         info.msg_len);
5445                         break;
5446                 default:
5447                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5448                                     opcode);
5449                         break;
5450                 }
5451         }
5452         rte_free(info.msg_buf);
5453 }
5454
5455 /*
5456  * Interrupt handler is registered as the alarm callback for handling LSC
5457  * interrupt in a definite of time, in order to wait the NIC into a stable
5458  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5459  * no need for link down interrupt.
5460  */
5461 static void
5462 i40e_dev_interrupt_delayed_handler(void *param)
5463 {
5464         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5466         uint32_t icr0;
5467
5468         /* read interrupt causes again */
5469         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5470
5471 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5472         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5473                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5474         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5475                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5476         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5477                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5478         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5479                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5480         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5481                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5482                                                                 "state\n");
5483         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5484                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5485         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5486                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5487 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5488
5489         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5490                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5491                 i40e_dev_handle_vfr_event(dev);
5492         }
5493         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5494                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5495                 i40e_dev_handle_aq_msg(dev);
5496         }
5497
5498         /* handle the link up interrupt in an alarm callback */
5499         i40e_dev_link_update(dev, 0);
5500         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5501
5502         i40e_pf_enable_irq0(hw);
5503         rte_intr_enable(&(dev->pci_dev->intr_handle));
5504 }
5505
5506 /**
5507  * Interrupt handler triggered by NIC  for handling
5508  * specific interrupt.
5509  *
5510  * @param handle
5511  *  Pointer to interrupt handle.
5512  * @param param
5513  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5514  *
5515  * @return
5516  *  void
5517  */
5518 static void
5519 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5520                            void *param)
5521 {
5522         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5523         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5524         uint32_t icr0;
5525
5526         /* Disable interrupt */
5527         i40e_pf_disable_irq0(hw);
5528
5529         /* read out interrupt causes */
5530         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5531
5532         /* No interrupt event indicated */
5533         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5534                 PMD_DRV_LOG(INFO, "No interrupt event");
5535                 goto done;
5536         }
5537 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5538         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5539                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5540         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5541                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5542         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5543                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5544         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5545                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5546         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5547                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5548         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5549                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5550         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5551                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5552 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5553
5554         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5555                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5556                 i40e_dev_handle_vfr_event(dev);
5557         }
5558         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5559                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5560                 i40e_dev_handle_aq_msg(dev);
5561         }
5562
5563         /* Link Status Change interrupt */
5564         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5565 #define I40E_US_PER_SECOND 1000000
5566                 struct rte_eth_link link;
5567
5568                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5569                 memset(&link, 0, sizeof(link));
5570                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5571                 i40e_dev_link_update(dev, 0);
5572
5573                 /*
5574                  * For link up interrupt, it needs to wait 1 second to let the
5575                  * hardware be a stable state. Otherwise several consecutive
5576                  * interrupts can be observed.
5577                  * For link down interrupt, no need to wait.
5578                  */
5579                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5580                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5581                         return;
5582                 else
5583                         _rte_eth_dev_callback_process(dev,
5584                                 RTE_ETH_EVENT_INTR_LSC);
5585         }
5586
5587 done:
5588         /* Enable interrupt */
5589         i40e_pf_enable_irq0(hw);
5590         rte_intr_enable(&(dev->pci_dev->intr_handle));
5591 }
5592
5593 static int
5594 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5595                          struct i40e_macvlan_filter *filter,
5596                          int total)
5597 {
5598         int ele_num, ele_buff_size;
5599         int num, actual_num, i;
5600         uint16_t flags;
5601         int ret = I40E_SUCCESS;
5602         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5603         struct i40e_aqc_add_macvlan_element_data *req_list;
5604
5605         if (filter == NULL  || total == 0)
5606                 return I40E_ERR_PARAM;
5607         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5608         ele_buff_size = hw->aq.asq_buf_size;
5609
5610         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5611         if (req_list == NULL) {
5612                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5613                 return I40E_ERR_NO_MEMORY;
5614         }
5615
5616         num = 0;
5617         do {
5618                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5619                 memset(req_list, 0, ele_buff_size);
5620
5621                 for (i = 0; i < actual_num; i++) {
5622                         (void)rte_memcpy(req_list[i].mac_addr,
5623                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5624                         req_list[i].vlan_tag =
5625                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5626
5627                         switch (filter[num + i].filter_type) {
5628                         case RTE_MAC_PERFECT_MATCH:
5629                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5630                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5631                                 break;
5632                         case RTE_MACVLAN_PERFECT_MATCH:
5633                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5634                                 break;
5635                         case RTE_MAC_HASH_MATCH:
5636                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5637                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5638                                 break;
5639                         case RTE_MACVLAN_HASH_MATCH:
5640                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5641                                 break;
5642                         default:
5643                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5644                                 ret = I40E_ERR_PARAM;
5645                                 goto DONE;
5646                         }
5647
5648                         req_list[i].queue_number = 0;
5649
5650                         req_list[i].flags = rte_cpu_to_le_16(flags);
5651                 }
5652
5653                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5654                                                 actual_num, NULL);
5655                 if (ret != I40E_SUCCESS) {
5656                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5657                         goto DONE;
5658                 }
5659                 num += actual_num;
5660         } while (num < total);
5661
5662 DONE:
5663         rte_free(req_list);
5664         return ret;
5665 }
5666
5667 static int
5668 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5669                             struct i40e_macvlan_filter *filter,
5670                             int total)
5671 {
5672         int ele_num, ele_buff_size;
5673         int num, actual_num, i;
5674         uint16_t flags;
5675         int ret = I40E_SUCCESS;
5676         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5677         struct i40e_aqc_remove_macvlan_element_data *req_list;
5678
5679         if (filter == NULL  || total == 0)
5680                 return I40E_ERR_PARAM;
5681
5682         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5683         ele_buff_size = hw->aq.asq_buf_size;
5684
5685         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5686         if (req_list == NULL) {
5687                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5688                 return I40E_ERR_NO_MEMORY;
5689         }
5690
5691         num = 0;
5692         do {
5693                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5694                 memset(req_list, 0, ele_buff_size);
5695
5696                 for (i = 0; i < actual_num; i++) {
5697                         (void)rte_memcpy(req_list[i].mac_addr,
5698                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5699                         req_list[i].vlan_tag =
5700                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5701
5702                         switch (filter[num + i].filter_type) {
5703                         case RTE_MAC_PERFECT_MATCH:
5704                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5705                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5706                                 break;
5707                         case RTE_MACVLAN_PERFECT_MATCH:
5708                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5709                                 break;
5710                         case RTE_MAC_HASH_MATCH:
5711                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5712                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5713                                 break;
5714                         case RTE_MACVLAN_HASH_MATCH:
5715                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5716                                 break;
5717                         default:
5718                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5719                                 ret = I40E_ERR_PARAM;
5720                                 goto DONE;
5721                         }
5722                         req_list[i].flags = rte_cpu_to_le_16(flags);
5723                 }
5724
5725                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5726                                                 actual_num, NULL);
5727                 if (ret != I40E_SUCCESS) {
5728                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5729                         goto DONE;
5730                 }
5731                 num += actual_num;
5732         } while (num < total);
5733
5734 DONE:
5735         rte_free(req_list);
5736         return ret;
5737 }
5738
5739 /* Find out specific MAC filter */
5740 static struct i40e_mac_filter *
5741 i40e_find_mac_filter(struct i40e_vsi *vsi,
5742                          struct ether_addr *macaddr)
5743 {
5744         struct i40e_mac_filter *f;
5745
5746         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5747                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5748                         return f;
5749         }
5750
5751         return NULL;
5752 }
5753
5754 static bool
5755 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5756                          uint16_t vlan_id)
5757 {
5758         uint32_t vid_idx, vid_bit;
5759
5760         if (vlan_id > ETH_VLAN_ID_MAX)
5761                 return 0;
5762
5763         vid_idx = I40E_VFTA_IDX(vlan_id);
5764         vid_bit = I40E_VFTA_BIT(vlan_id);
5765
5766         if (vsi->vfta[vid_idx] & vid_bit)
5767                 return 1;
5768         else
5769                 return 0;
5770 }
5771
5772 static void
5773 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5774                          uint16_t vlan_id, bool on)
5775 {
5776         uint32_t vid_idx, vid_bit;
5777
5778         if (vlan_id > ETH_VLAN_ID_MAX)
5779                 return;
5780
5781         vid_idx = I40E_VFTA_IDX(vlan_id);
5782         vid_bit = I40E_VFTA_BIT(vlan_id);
5783
5784         if (on)
5785                 vsi->vfta[vid_idx] |= vid_bit;
5786         else
5787                 vsi->vfta[vid_idx] &= ~vid_bit;
5788 }
5789
5790 /**
5791  * Find all vlan options for specific mac addr,
5792  * return with actual vlan found.
5793  */
5794 static inline int
5795 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5796                            struct i40e_macvlan_filter *mv_f,
5797                            int num, struct ether_addr *addr)
5798 {
5799         int i;
5800         uint32_t j, k;
5801
5802         /**
5803          * Not to use i40e_find_vlan_filter to decrease the loop time,
5804          * although the code looks complex.
5805           */
5806         if (num < vsi->vlan_num)
5807                 return I40E_ERR_PARAM;
5808
5809         i = 0;
5810         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5811                 if (vsi->vfta[j]) {
5812                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5813                                 if (vsi->vfta[j] & (1 << k)) {
5814                                         if (i > num - 1) {
5815                                                 PMD_DRV_LOG(ERR, "vlan number "
5816                                                             "not match");
5817                                                 return I40E_ERR_PARAM;
5818                                         }
5819                                         (void)rte_memcpy(&mv_f[i].macaddr,
5820                                                         addr, ETH_ADDR_LEN);
5821                                         mv_f[i].vlan_id =
5822                                                 j * I40E_UINT32_BIT_SIZE + k;
5823                                         i++;
5824                                 }
5825                         }
5826                 }
5827         }
5828         return I40E_SUCCESS;
5829 }
5830
5831 static inline int
5832 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5833                            struct i40e_macvlan_filter *mv_f,
5834                            int num,
5835                            uint16_t vlan)
5836 {
5837         int i = 0;
5838         struct i40e_mac_filter *f;
5839
5840         if (num < vsi->mac_num)
5841                 return I40E_ERR_PARAM;
5842
5843         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5844                 if (i > num - 1) {
5845                         PMD_DRV_LOG(ERR, "buffer number not match");
5846                         return I40E_ERR_PARAM;
5847                 }
5848                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5849                                 ETH_ADDR_LEN);
5850                 mv_f[i].vlan_id = vlan;
5851                 mv_f[i].filter_type = f->mac_info.filter_type;
5852                 i++;
5853         }
5854
5855         return I40E_SUCCESS;
5856 }
5857
5858 static int
5859 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5860 {
5861         int i, num;
5862         struct i40e_mac_filter *f;
5863         struct i40e_macvlan_filter *mv_f;
5864         int ret = I40E_SUCCESS;
5865
5866         if (vsi == NULL || vsi->mac_num == 0)
5867                 return I40E_ERR_PARAM;
5868
5869         /* Case that no vlan is set */
5870         if (vsi->vlan_num == 0)
5871                 num = vsi->mac_num;
5872         else
5873                 num = vsi->mac_num * vsi->vlan_num;
5874
5875         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5876         if (mv_f == NULL) {
5877                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5878                 return I40E_ERR_NO_MEMORY;
5879         }
5880
5881         i = 0;
5882         if (vsi->vlan_num == 0) {
5883                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5884                         (void)rte_memcpy(&mv_f[i].macaddr,
5885                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5886                         mv_f[i].vlan_id = 0;
5887                         i++;
5888                 }
5889         } else {
5890                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5891                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5892                                         vsi->vlan_num, &f->mac_info.mac_addr);
5893                         if (ret != I40E_SUCCESS)
5894                                 goto DONE;
5895                         i += vsi->vlan_num;
5896                 }
5897         }
5898
5899         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5900 DONE:
5901         rte_free(mv_f);
5902
5903         return ret;
5904 }
5905
5906 int
5907 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5908 {
5909         struct i40e_macvlan_filter *mv_f;
5910         int mac_num;
5911         int ret = I40E_SUCCESS;
5912
5913         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5914                 return I40E_ERR_PARAM;
5915
5916         /* If it's already set, just return */
5917         if (i40e_find_vlan_filter(vsi,vlan))
5918                 return I40E_SUCCESS;
5919
5920         mac_num = vsi->mac_num;
5921
5922         if (mac_num == 0) {
5923                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5924                 return I40E_ERR_PARAM;
5925         }
5926
5927         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5928
5929         if (mv_f == NULL) {
5930                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5931                 return I40E_ERR_NO_MEMORY;
5932         }
5933
5934         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5935
5936         if (ret != I40E_SUCCESS)
5937                 goto DONE;
5938
5939         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5940
5941         if (ret != I40E_SUCCESS)
5942                 goto DONE;
5943
5944         i40e_set_vlan_filter(vsi, vlan, 1);
5945
5946         vsi->vlan_num++;
5947         ret = I40E_SUCCESS;
5948 DONE:
5949         rte_free(mv_f);
5950         return ret;
5951 }
5952
5953 int
5954 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5955 {
5956         struct i40e_macvlan_filter *mv_f;
5957         int mac_num;
5958         int ret = I40E_SUCCESS;
5959
5960         /**
5961          * Vlan 0 is the generic filter for untagged packets
5962          * and can't be removed.
5963          */
5964         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5965                 return I40E_ERR_PARAM;
5966
5967         /* If can't find it, just return */
5968         if (!i40e_find_vlan_filter(vsi, vlan))
5969                 return I40E_ERR_PARAM;
5970
5971         mac_num = vsi->mac_num;
5972
5973         if (mac_num == 0) {
5974                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5975                 return I40E_ERR_PARAM;
5976         }
5977
5978         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5979
5980         if (mv_f == NULL) {
5981                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5982                 return I40E_ERR_NO_MEMORY;
5983         }
5984
5985         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5986
5987         if (ret != I40E_SUCCESS)
5988                 goto DONE;
5989
5990         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5991
5992         if (ret != I40E_SUCCESS)
5993                 goto DONE;
5994
5995         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5996         if (vsi->vlan_num == 1) {
5997                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5998                 if (ret != I40E_SUCCESS)
5999                         goto DONE;
6000
6001                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6002                 if (ret != I40E_SUCCESS)
6003                         goto DONE;
6004         }
6005
6006         i40e_set_vlan_filter(vsi, vlan, 0);
6007
6008         vsi->vlan_num--;
6009         ret = I40E_SUCCESS;
6010 DONE:
6011         rte_free(mv_f);
6012         return ret;
6013 }
6014
6015 int
6016 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6017 {
6018         struct i40e_mac_filter *f;
6019         struct i40e_macvlan_filter *mv_f;
6020         int i, vlan_num = 0;
6021         int ret = I40E_SUCCESS;
6022
6023         /* If it's add and we've config it, return */
6024         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6025         if (f != NULL)
6026                 return I40E_SUCCESS;
6027         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6028                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6029
6030                 /**
6031                  * If vlan_num is 0, that's the first time to add mac,
6032                  * set mask for vlan_id 0.
6033                  */
6034                 if (vsi->vlan_num == 0) {
6035                         i40e_set_vlan_filter(vsi, 0, 1);
6036                         vsi->vlan_num = 1;
6037                 }
6038                 vlan_num = vsi->vlan_num;
6039         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6040                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6041                 vlan_num = 1;
6042
6043         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6044         if (mv_f == NULL) {
6045                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6046                 return I40E_ERR_NO_MEMORY;
6047         }
6048
6049         for (i = 0; i < vlan_num; i++) {
6050                 mv_f[i].filter_type = mac_filter->filter_type;
6051                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6052                                 ETH_ADDR_LEN);
6053         }
6054
6055         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6056                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6057                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6058                                         &mac_filter->mac_addr);
6059                 if (ret != I40E_SUCCESS)
6060                         goto DONE;
6061         }
6062
6063         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6064         if (ret != I40E_SUCCESS)
6065                 goto DONE;
6066
6067         /* Add the mac addr into mac list */
6068         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6069         if (f == NULL) {
6070                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6071                 ret = I40E_ERR_NO_MEMORY;
6072                 goto DONE;
6073         }
6074         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6075                         ETH_ADDR_LEN);
6076         f->mac_info.filter_type = mac_filter->filter_type;
6077         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6078         vsi->mac_num++;
6079
6080         ret = I40E_SUCCESS;
6081 DONE:
6082         rte_free(mv_f);
6083
6084         return ret;
6085 }
6086
6087 int
6088 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6089 {
6090         struct i40e_mac_filter *f;
6091         struct i40e_macvlan_filter *mv_f;
6092         int i, vlan_num;
6093         enum rte_mac_filter_type filter_type;
6094         int ret = I40E_SUCCESS;
6095
6096         /* Can't find it, return an error */
6097         f = i40e_find_mac_filter(vsi, addr);
6098         if (f == NULL)
6099                 return I40E_ERR_PARAM;
6100
6101         vlan_num = vsi->vlan_num;
6102         filter_type = f->mac_info.filter_type;
6103         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6104                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6105                 if (vlan_num == 0) {
6106                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6107                         return I40E_ERR_PARAM;
6108                 }
6109         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6110                         filter_type == RTE_MAC_HASH_MATCH)
6111                 vlan_num = 1;
6112
6113         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6114         if (mv_f == NULL) {
6115                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6116                 return I40E_ERR_NO_MEMORY;
6117         }
6118
6119         for (i = 0; i < vlan_num; i++) {
6120                 mv_f[i].filter_type = filter_type;
6121                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6122                                 ETH_ADDR_LEN);
6123         }
6124         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6125                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6126                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6127                 if (ret != I40E_SUCCESS)
6128                         goto DONE;
6129         }
6130
6131         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6132         if (ret != I40E_SUCCESS)
6133                 goto DONE;
6134
6135         /* Remove the mac addr into mac list */
6136         TAILQ_REMOVE(&vsi->mac_list, f, next);
6137         rte_free(f);
6138         vsi->mac_num--;
6139
6140         ret = I40E_SUCCESS;
6141 DONE:
6142         rte_free(mv_f);
6143         return ret;
6144 }
6145
6146 /* Configure hash enable flags for RSS */
6147 uint64_t
6148 i40e_config_hena(uint64_t flags)
6149 {
6150         uint64_t hena = 0;
6151
6152         if (!flags)
6153                 return hena;
6154
6155         if (flags & ETH_RSS_FRAG_IPV4)
6156                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6157         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6158 #ifdef X722_SUPPORT
6159                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6160                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6161 #else
6162                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6163 #endif
6164         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6165 #ifdef X722_SUPPORT
6166                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6167                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6168                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6169 #else
6170                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6171 #endif
6172         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6173                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6174         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6175                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6176         if (flags & ETH_RSS_FRAG_IPV6)
6177                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6178         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6179 #ifdef X722_SUPPORT
6180                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6181                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6182 #else
6183                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6184 #endif
6185         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6186 #ifdef X722_SUPPORT
6187                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6188                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6189                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6190 #else
6191                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6192 #endif
6193         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6194                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6195         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6196                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6197         if (flags & ETH_RSS_L2_PAYLOAD)
6198                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6199
6200         return hena;
6201 }
6202
6203 /* Parse the hash enable flags */
6204 uint64_t
6205 i40e_parse_hena(uint64_t flags)
6206 {
6207         uint64_t rss_hf = 0;
6208
6209         if (!flags)
6210                 return rss_hf;
6211         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6212                 rss_hf |= ETH_RSS_FRAG_IPV4;
6213         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6214                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6215 #ifdef X722_SUPPORT
6216         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6217                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6218 #endif
6219         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6220                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6221 #ifdef X722_SUPPORT
6222         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6223                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6224         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6225                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6226 #endif
6227         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6228                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6229         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6230                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6231         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6232                 rss_hf |= ETH_RSS_FRAG_IPV6;
6233         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6234                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6235 #ifdef X722_SUPPORT
6236         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6237                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6238 #endif
6239         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6240                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6241 #ifdef X722_SUPPORT
6242         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6243                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6244         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6245                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6246 #endif
6247         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6248                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6249         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6250                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6251         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6252                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6253
6254         return rss_hf;
6255 }
6256
6257 /* Disable RSS */
6258 static void
6259 i40e_pf_disable_rss(struct i40e_pf *pf)
6260 {
6261         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6262         uint64_t hena;
6263
6264         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6265         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6266         hena &= ~I40E_RSS_HENA_ALL;
6267         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6268         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6269         I40E_WRITE_FLUSH(hw);
6270 }
6271
6272 static int
6273 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6274 {
6275         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6276         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6277         int ret = 0;
6278
6279         if (!key || key_len == 0) {
6280                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6281                 return 0;
6282         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6283                 sizeof(uint32_t)) {
6284                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6285                 return -EINVAL;
6286         }
6287
6288         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6289                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6290                         (struct i40e_aqc_get_set_rss_key_data *)key;
6291
6292                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6293                 if (ret)
6294                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6295                                      "via AQ");
6296         } else {
6297                 uint32_t *hash_key = (uint32_t *)key;
6298                 uint16_t i;
6299
6300                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6301                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6302                 I40E_WRITE_FLUSH(hw);
6303         }
6304
6305         return ret;
6306 }
6307
6308 static int
6309 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6310 {
6311         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6312         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6313         int ret;
6314
6315         if (!key || !key_len)
6316                 return -EINVAL;
6317
6318         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6319                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6320                         (struct i40e_aqc_get_set_rss_key_data *)key);
6321                 if (ret) {
6322                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6323                         return ret;
6324                 }
6325         } else {
6326                 uint32_t *key_dw = (uint32_t *)key;
6327                 uint16_t i;
6328
6329                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6330                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6331         }
6332         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6333
6334         return 0;
6335 }
6336
6337 static int
6338 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6339 {
6340         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6341         uint64_t rss_hf;
6342         uint64_t hena;
6343         int ret;
6344
6345         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6346                                rss_conf->rss_key_len);
6347         if (ret)
6348                 return ret;
6349
6350         rss_hf = rss_conf->rss_hf;
6351         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6352         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6353         hena &= ~I40E_RSS_HENA_ALL;
6354         hena |= i40e_config_hena(rss_hf);
6355         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6356         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6357         I40E_WRITE_FLUSH(hw);
6358
6359         return 0;
6360 }
6361
6362 static int
6363 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6364                          struct rte_eth_rss_conf *rss_conf)
6365 {
6366         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6367         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6368         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6369         uint64_t hena;
6370
6371         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6372         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6373         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6374                 if (rss_hf != 0) /* Enable RSS */
6375                         return -EINVAL;
6376                 return 0; /* Nothing to do */
6377         }
6378         /* RSS enabled */
6379         if (rss_hf == 0) /* Disable RSS */
6380                 return -EINVAL;
6381
6382         return i40e_hw_rss_hash_set(pf, rss_conf);
6383 }
6384
6385 static int
6386 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6387                            struct rte_eth_rss_conf *rss_conf)
6388 {
6389         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6390         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6391         uint64_t hena;
6392
6393         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6394                          &rss_conf->rss_key_len);
6395
6396         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6397         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6398         rss_conf->rss_hf = i40e_parse_hena(hena);
6399
6400         return 0;
6401 }
6402
6403 static int
6404 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6405 {
6406         switch (filter_type) {
6407         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6408                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6409                 break;
6410         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6411                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6412                 break;
6413         case RTE_TUNNEL_FILTER_IMAC_TENID:
6414                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6415                 break;
6416         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6417                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6418                 break;
6419         case ETH_TUNNEL_FILTER_IMAC:
6420                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6421                 break;
6422         case ETH_TUNNEL_FILTER_OIP:
6423                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6424                 break;
6425         case ETH_TUNNEL_FILTER_IIP:
6426                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6427                 break;
6428         default:
6429                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6430                 return -EINVAL;
6431         }
6432
6433         return 0;
6434 }
6435
6436 static int
6437 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6438                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6439                         uint8_t add)
6440 {
6441         uint16_t ip_type;
6442         uint32_t ipv4_addr;
6443         uint8_t i, tun_type = 0;
6444         /* internal varialbe to convert ipv6 byte order */
6445         uint32_t convert_ipv6[4];
6446         int val, ret = 0;
6447         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6448         struct i40e_vsi *vsi = pf->main_vsi;
6449         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6450         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6451
6452         cld_filter = rte_zmalloc("tunnel_filter",
6453                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6454                 0);
6455
6456         if (NULL == cld_filter) {
6457                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6458                 return -EINVAL;
6459         }
6460         pfilter = cld_filter;
6461
6462         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6463         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6464
6465         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6466         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6467                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6468                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6469                 rte_memcpy(&pfilter->ipaddr.v4.data,
6470                                 &rte_cpu_to_le_32(ipv4_addr),
6471                                 sizeof(pfilter->ipaddr.v4.data));
6472         } else {
6473                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6474                 for (i = 0; i < 4; i++) {
6475                         convert_ipv6[i] =
6476                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6477                 }
6478                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6479                                 sizeof(pfilter->ipaddr.v6.data));
6480         }
6481
6482         /* check tunneled type */
6483         switch (tunnel_filter->tunnel_type) {
6484         case RTE_TUNNEL_TYPE_VXLAN:
6485                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6486                 break;
6487         case RTE_TUNNEL_TYPE_NVGRE:
6488                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6489                 break;
6490         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6491                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6492                 break;
6493         default:
6494                 /* Other tunnel types is not supported. */
6495                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6496                 rte_free(cld_filter);
6497                 return -EINVAL;
6498         }
6499
6500         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6501                                                 &pfilter->flags);
6502         if (val < 0) {
6503                 rte_free(cld_filter);
6504                 return -EINVAL;
6505         }
6506
6507         pfilter->flags |= rte_cpu_to_le_16(
6508                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6509                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6510         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6511         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6512
6513         if (add)
6514                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6515         else
6516                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6517                                                 cld_filter, 1);
6518
6519         rte_free(cld_filter);
6520         return ret;
6521 }
6522
6523 static int
6524 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6525 {
6526         uint8_t i;
6527
6528         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6529                 if (pf->vxlan_ports[i] == port)
6530                         return i;
6531         }
6532
6533         return -1;
6534 }
6535
6536 static int
6537 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6538 {
6539         int  idx, ret;
6540         uint8_t filter_idx;
6541         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6542
6543         idx = i40e_get_vxlan_port_idx(pf, port);
6544
6545         /* Check if port already exists */
6546         if (idx >= 0) {
6547                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6548                 return -EINVAL;
6549         }
6550
6551         /* Now check if there is space to add the new port */
6552         idx = i40e_get_vxlan_port_idx(pf, 0);
6553         if (idx < 0) {
6554                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6555                         "not adding port %d", port);
6556                 return -ENOSPC;
6557         }
6558
6559         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6560                                         &filter_idx, NULL);
6561         if (ret < 0) {
6562                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6563                 return -1;
6564         }
6565
6566         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6567                          port,  filter_idx);
6568
6569         /* New port: add it and mark its index in the bitmap */
6570         pf->vxlan_ports[idx] = port;
6571         pf->vxlan_bitmap |= (1 << idx);
6572
6573         if (!(pf->flags & I40E_FLAG_VXLAN))
6574                 pf->flags |= I40E_FLAG_VXLAN;
6575
6576         return 0;
6577 }
6578
6579 static int
6580 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6581 {
6582         int idx;
6583         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6584
6585         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6586                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6587                 return -EINVAL;
6588         }
6589
6590         idx = i40e_get_vxlan_port_idx(pf, port);
6591
6592         if (idx < 0) {
6593                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6594                 return -EINVAL;
6595         }
6596
6597         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6598                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6599                 return -1;
6600         }
6601
6602         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6603                         port, idx);
6604
6605         pf->vxlan_ports[idx] = 0;
6606         pf->vxlan_bitmap &= ~(1 << idx);
6607
6608         if (!pf->vxlan_bitmap)
6609                 pf->flags &= ~I40E_FLAG_VXLAN;
6610
6611         return 0;
6612 }
6613
6614 /* Add UDP tunneling port */
6615 static int
6616 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6617                              struct rte_eth_udp_tunnel *udp_tunnel)
6618 {
6619         int ret = 0;
6620         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6621
6622         if (udp_tunnel == NULL)
6623                 return -EINVAL;
6624
6625         switch (udp_tunnel->prot_type) {
6626         case RTE_TUNNEL_TYPE_VXLAN:
6627                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6628                 break;
6629
6630         case RTE_TUNNEL_TYPE_GENEVE:
6631         case RTE_TUNNEL_TYPE_TEREDO:
6632                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6633                 ret = -1;
6634                 break;
6635
6636         default:
6637                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6638                 ret = -1;
6639                 break;
6640         }
6641
6642         return ret;
6643 }
6644
6645 /* Remove UDP tunneling port */
6646 static int
6647 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6648                              struct rte_eth_udp_tunnel *udp_tunnel)
6649 {
6650         int ret = 0;
6651         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6652
6653         if (udp_tunnel == NULL)
6654                 return -EINVAL;
6655
6656         switch (udp_tunnel->prot_type) {
6657         case RTE_TUNNEL_TYPE_VXLAN:
6658                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6659                 break;
6660         case RTE_TUNNEL_TYPE_GENEVE:
6661         case RTE_TUNNEL_TYPE_TEREDO:
6662                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6663                 ret = -1;
6664                 break;
6665         default:
6666                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6667                 ret = -1;
6668                 break;
6669         }
6670
6671         return ret;
6672 }
6673
6674 /* Calculate the maximum number of contiguous PF queues that are configured */
6675 static int
6676 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6677 {
6678         struct rte_eth_dev_data *data = pf->dev_data;
6679         int i, num;
6680         struct i40e_rx_queue *rxq;
6681
6682         num = 0;
6683         for (i = 0; i < pf->lan_nb_qps; i++) {
6684                 rxq = data->rx_queues[i];
6685                 if (rxq && rxq->q_set)
6686                         num++;
6687                 else
6688                         break;
6689         }
6690
6691         return num;
6692 }
6693
6694 /* Configure RSS */
6695 static int
6696 i40e_pf_config_rss(struct i40e_pf *pf)
6697 {
6698         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6699         struct rte_eth_rss_conf rss_conf;
6700         uint32_t i, lut = 0;
6701         uint16_t j, num;
6702
6703         /*
6704          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6705          * It's necessary to calulate the actual PF queues that are configured.
6706          */
6707         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6708                 num = i40e_pf_calc_configured_queues_num(pf);
6709         else
6710                 num = pf->dev_data->nb_rx_queues;
6711
6712         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6713         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6714                         num);
6715
6716         if (num == 0) {
6717                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6718                 return -ENOTSUP;
6719         }
6720
6721         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6722                 if (j == num)
6723                         j = 0;
6724                 lut = (lut << 8) | (j & ((0x1 <<
6725                         hw->func_caps.rss_table_entry_width) - 1));
6726                 if ((i & 3) == 3)
6727                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6728         }
6729
6730         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6731         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6732                 i40e_pf_disable_rss(pf);
6733                 return 0;
6734         }
6735         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6736                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6737                 /* Random default keys */
6738                 static uint32_t rss_key_default[] = {0x6b793944,
6739                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6740                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6741                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6742
6743                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6744                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6745                                                         sizeof(uint32_t);
6746         }
6747
6748         return i40e_hw_rss_hash_set(pf, &rss_conf);
6749 }
6750
6751 static int
6752 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6753                                struct rte_eth_tunnel_filter_conf *filter)
6754 {
6755         if (pf == NULL || filter == NULL) {
6756                 PMD_DRV_LOG(ERR, "Invalid parameter");
6757                 return -EINVAL;
6758         }
6759
6760         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6761                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6762                 return -EINVAL;
6763         }
6764
6765         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6766                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6767                 return -EINVAL;
6768         }
6769
6770         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6771                 (is_zero_ether_addr(&filter->outer_mac))) {
6772                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6773                 return -EINVAL;
6774         }
6775
6776         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6777                 (is_zero_ether_addr(&filter->inner_mac))) {
6778                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6779                 return -EINVAL;
6780         }
6781
6782         return 0;
6783 }
6784
6785 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6786 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6787 static int
6788 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6789 {
6790         uint32_t val, reg;
6791         int ret = -EINVAL;
6792
6793         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6794         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6795
6796         if (len == 3) {
6797                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6798         } else if (len == 4) {
6799                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6800         } else {
6801                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6802                 return ret;
6803         }
6804
6805         if (reg != val) {
6806                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6807                                                    reg, NULL);
6808                 if (ret != 0)
6809                         return ret;
6810         } else {
6811                 ret = 0;
6812         }
6813         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6814                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6815
6816         return ret;
6817 }
6818
6819 static int
6820 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6821 {
6822         int ret = -EINVAL;
6823
6824         if (!hw || !cfg)
6825                 return -EINVAL;
6826
6827         switch (cfg->cfg_type) {
6828         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6829                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6830                 break;
6831         default:
6832                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6833                 break;
6834         }
6835
6836         return ret;
6837 }
6838
6839 static int
6840 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6841                                enum rte_filter_op filter_op,
6842                                void *arg)
6843 {
6844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6845         int ret = I40E_ERR_PARAM;
6846
6847         switch (filter_op) {
6848         case RTE_ETH_FILTER_SET:
6849                 ret = i40e_dev_global_config_set(hw,
6850                         (struct rte_eth_global_cfg *)arg);
6851                 break;
6852         default:
6853                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6854                 break;
6855         }
6856
6857         return ret;
6858 }
6859
6860 static int
6861 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6862                           enum rte_filter_op filter_op,
6863                           void *arg)
6864 {
6865         struct rte_eth_tunnel_filter_conf *filter;
6866         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6867         int ret = I40E_SUCCESS;
6868
6869         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6870
6871         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6872                 return I40E_ERR_PARAM;
6873
6874         switch (filter_op) {
6875         case RTE_ETH_FILTER_NOP:
6876                 if (!(pf->flags & I40E_FLAG_VXLAN))
6877                         ret = I40E_NOT_SUPPORTED;
6878                 break;
6879         case RTE_ETH_FILTER_ADD:
6880                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6881                 break;
6882         case RTE_ETH_FILTER_DELETE:
6883                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6884                 break;
6885         default:
6886                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6887                 ret = I40E_ERR_PARAM;
6888                 break;
6889         }
6890
6891         return ret;
6892 }
6893
6894 static int
6895 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6896 {
6897         int ret = 0;
6898         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6899
6900         /* RSS setup */
6901         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6902                 ret = i40e_pf_config_rss(pf);
6903         else
6904                 i40e_pf_disable_rss(pf);
6905
6906         return ret;
6907 }
6908
6909 /* Get the symmetric hash enable configurations per port */
6910 static void
6911 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6912 {
6913         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6914
6915         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6916 }
6917
6918 /* Set the symmetric hash enable configurations per port */
6919 static void
6920 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6921 {
6922         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6923
6924         if (enable > 0) {
6925                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6926                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6927                                                         "been enabled");
6928                         return;
6929                 }
6930                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6931         } else {
6932                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6933                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6934                                                         "been disabled");
6935                         return;
6936                 }
6937                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6938         }
6939         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6940         I40E_WRITE_FLUSH(hw);
6941 }
6942
6943 /*
6944  * Get global configurations of hash function type and symmetric hash enable
6945  * per flow type (pctype). Note that global configuration means it affects all
6946  * the ports on the same NIC.
6947  */
6948 static int
6949 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6950                                    struct rte_eth_hash_global_conf *g_cfg)
6951 {
6952         uint32_t reg, mask = I40E_FLOW_TYPES;
6953         uint16_t i;
6954         enum i40e_filter_pctype pctype;
6955
6956         memset(g_cfg, 0, sizeof(*g_cfg));
6957         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6958         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6959                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6960         else
6961                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6962         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6963                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6964
6965         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6966                 if (!(mask & (1UL << i)))
6967                         continue;
6968                 mask &= ~(1UL << i);
6969                 /* Bit set indicats the coresponding flow type is supported */
6970                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6971                 /* if flowtype is invalid, continue */
6972                 if (!I40E_VALID_FLOW(i))
6973                         continue;
6974                 pctype = i40e_flowtype_to_pctype(i);
6975                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6976                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6977                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6978         }
6979
6980         return 0;
6981 }
6982
6983 static int
6984 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6985 {
6986         uint32_t i;
6987         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6988
6989         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6990                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6991                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6992                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6993                                                 g_cfg->hash_func);
6994                 return -EINVAL;
6995         }
6996
6997         /*
6998          * As i40e supports less than 32 flow types, only first 32 bits need to
6999          * be checked.
7000          */
7001         mask0 = g_cfg->valid_bit_mask[0];
7002         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7003                 if (i == 0) {
7004                         /* Check if any unsupported flow type configured */
7005                         if ((mask0 | i40e_mask) ^ i40e_mask)
7006                                 goto mask_err;
7007                 } else {
7008                         if (g_cfg->valid_bit_mask[i])
7009                                 goto mask_err;
7010                 }
7011         }
7012
7013         return 0;
7014
7015 mask_err:
7016         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7017
7018         return -EINVAL;
7019 }
7020
7021 /*
7022  * Set global configurations of hash function type and symmetric hash enable
7023  * per flow type (pctype). Note any modifying global configuration will affect
7024  * all the ports on the same NIC.
7025  */
7026 static int
7027 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7028                                    struct rte_eth_hash_global_conf *g_cfg)
7029 {
7030         int ret;
7031         uint16_t i;
7032         uint32_t reg;
7033         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7034         enum i40e_filter_pctype pctype;
7035
7036         /* Check the input parameters */
7037         ret = i40e_hash_global_config_check(g_cfg);
7038         if (ret < 0)
7039                 return ret;
7040
7041         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7042                 if (!(mask0 & (1UL << i)))
7043                         continue;
7044                 mask0 &= ~(1UL << i);
7045                 /* if flowtype is invalid, continue */
7046                 if (!I40E_VALID_FLOW(i))
7047                         continue;
7048                 pctype = i40e_flowtype_to_pctype(i);
7049                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7050                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7051                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7052         }
7053
7054         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7055         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7056                 /* Toeplitz */
7057                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7058                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7059                                                                 "Toeplitz");
7060                         goto out;
7061                 }
7062                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7063         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7064                 /* Simple XOR */
7065                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7066                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7067                                                         "Simple XOR");
7068                         goto out;
7069                 }
7070                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7071         } else
7072                 /* Use the default, and keep it as it is */
7073                 goto out;
7074
7075         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7076
7077 out:
7078         I40E_WRITE_FLUSH(hw);
7079
7080         return 0;
7081 }
7082
7083 /**
7084  * Valid input sets for hash and flow director filters per PCTYPE
7085  */
7086 static uint64_t
7087 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7088                 enum rte_filter_type filter)
7089 {
7090         uint64_t valid;
7091
7092         static const uint64_t valid_hash_inset_table[] = {
7093                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7094                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7095                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7096                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7097                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7098                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7099                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7100                         I40E_INSET_FLEX_PAYLOAD,
7101                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7102                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7103                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7104                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7105                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7106                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7107                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7108                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7109                         I40E_INSET_FLEX_PAYLOAD,
7110 #ifdef X722_SUPPORT
7111                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7112                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7113                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7114                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7115                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7116                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7117                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7118                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7119                         I40E_INSET_FLEX_PAYLOAD,
7120                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7121                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7122                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7123                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7124                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7125                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7126                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7127                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7128                         I40E_INSET_FLEX_PAYLOAD,
7129 #endif
7130                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7131                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7132                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7133                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7134                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7135                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7136                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7137                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7138                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7139 #ifdef X722_SUPPORT
7140                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7141                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7142                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7143                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7144                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7145                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7146                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7147                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7148                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7149 #endif
7150                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7151                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7152                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7153                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7154                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7155                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7156                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7157                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7158                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7159                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7160                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7161                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7162                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7163                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7164                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7165                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7166                         I40E_INSET_FLEX_PAYLOAD,
7167                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7168                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7169                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7170                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7171                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7172                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7173                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7174                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7175                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7176                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7177                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7178                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7179                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7180                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7181                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7182                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7183 #ifdef X722_SUPPORT
7184                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7185                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7186                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7187                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7188                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7189                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7190                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7191                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7192                         I40E_INSET_FLEX_PAYLOAD,
7193                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7194                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7195                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7196                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7197                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7198                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7199                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7200                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7201                         I40E_INSET_FLEX_PAYLOAD,
7202 #endif
7203                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7204                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7205                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7206                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7207                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7208                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7209                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7210                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7211                         I40E_INSET_FLEX_PAYLOAD,
7212 #ifdef X722_SUPPORT
7213                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7214                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7215                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7216                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7217                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7218                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7219                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7220                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7221                         I40E_INSET_FLEX_PAYLOAD,
7222 #endif
7223                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7224                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7225                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7226                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7227                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7228                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7229                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7230                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7231                         I40E_INSET_FLEX_PAYLOAD,
7232                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7233                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7234                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7235                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7236                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7237                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7238                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7239                         I40E_INSET_FLEX_PAYLOAD,
7240                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7241                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7242                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7243                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7244                         I40E_INSET_FLEX_PAYLOAD,
7245         };
7246
7247         /**
7248          * Flow director supports only fields defined in
7249          * union rte_eth_fdir_flow.
7250          */
7251         static const uint64_t valid_fdir_inset_table[] = {
7252                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7253                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7254                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7255                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7256                 I40E_INSET_IPV4_TTL,
7257                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7258                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7259                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7260                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7261                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7262 #ifdef X722_SUPPORT
7263                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7264                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7265                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7266                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7267                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7268                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7269                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7270                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7271                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7272                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7273 #endif
7274                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7275                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7276                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7277                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7278                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7279 #ifdef X722_SUPPORT
7280                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7281                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7282                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7283                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7284                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7285 #endif
7286                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7287                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7288                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7289                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7290                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7291                 I40E_INSET_SCTP_VT,
7292                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7293                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7294                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7295                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7296                 I40E_INSET_IPV4_TTL,
7297                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7298                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7299                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7300                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7301                 I40E_INSET_IPV6_HOP_LIMIT,
7302                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7303                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7304                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7305                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7306                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7307 #ifdef X722_SUPPORT
7308                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7309                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7310                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7311                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7312                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7313                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7314                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7315                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7316                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7317                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7318 #endif
7319                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7320                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7321                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7322                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7323                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7324 #ifdef X722_SUPPORT
7325                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7326                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7327                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7328                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7329                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7330 #endif
7331                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7332                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7333                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7334                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7335                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7336                 I40E_INSET_SCTP_VT,
7337                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7338                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7339                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7340                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7341                 I40E_INSET_IPV6_HOP_LIMIT,
7342                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7343                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7344                 I40E_INSET_LAST_ETHER_TYPE,
7345         };
7346
7347         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7348                 return 0;
7349         if (filter == RTE_ETH_FILTER_HASH)
7350                 valid = valid_hash_inset_table[pctype];
7351         else
7352                 valid = valid_fdir_inset_table[pctype];
7353
7354         return valid;
7355 }
7356
7357 /**
7358  * Validate if the input set is allowed for a specific PCTYPE
7359  */
7360 static int
7361 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7362                 enum rte_filter_type filter, uint64_t inset)
7363 {
7364         uint64_t valid;
7365
7366         valid = i40e_get_valid_input_set(pctype, filter);
7367         if (inset & (~valid))
7368                 return -EINVAL;
7369
7370         return 0;
7371 }
7372
7373 /* default input set fields combination per pctype */
7374 static uint64_t
7375 i40e_get_default_input_set(uint16_t pctype)
7376 {
7377         static const uint64_t default_inset_table[] = {
7378                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7379                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7380                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7381                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7382                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7383 #ifdef X722_SUPPORT
7384                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7385                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7386                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7387                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7388                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7389                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7390 #endif
7391                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7392                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7393                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7394 #ifdef X722_SUPPORT
7395                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7396                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7397                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7398 #endif
7399                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7400                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7401                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7402                         I40E_INSET_SCTP_VT,
7403                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7404                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7405                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7406                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7407                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7408                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7409                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7410 #ifdef X722_SUPPORT
7411                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7412                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7413                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7414                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7415                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7416                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7417 #endif
7418                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7419                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7420                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7421 #ifdef X722_SUPPORT
7422                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7423                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7424                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7425 #endif
7426                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7427                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7428                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7429                         I40E_INSET_SCTP_VT,
7430                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7431                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7432                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7433                         I40E_INSET_LAST_ETHER_TYPE,
7434         };
7435
7436         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7437                 return 0;
7438
7439         return default_inset_table[pctype];
7440 }
7441
7442 /**
7443  * Parse the input set from index to logical bit masks
7444  */
7445 static int
7446 i40e_parse_input_set(uint64_t *inset,
7447                      enum i40e_filter_pctype pctype,
7448                      enum rte_eth_input_set_field *field,
7449                      uint16_t size)
7450 {
7451         uint16_t i, j;
7452         int ret = -EINVAL;
7453
7454         static const struct {
7455                 enum rte_eth_input_set_field field;
7456                 uint64_t inset;
7457         } inset_convert_table[] = {
7458                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7459                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7460                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7461                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7462                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7463                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7464                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7465                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7466                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7467                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7468                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7469                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7470                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7471                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7472                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7473                         I40E_INSET_IPV6_NEXT_HDR},
7474                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7475                         I40E_INSET_IPV6_HOP_LIMIT},
7476                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7477                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7478                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7479                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7480                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7481                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7482                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7483                         I40E_INSET_SCTP_VT},
7484                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7485                         I40E_INSET_TUNNEL_DMAC},
7486                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7487                         I40E_INSET_VLAN_TUNNEL},
7488                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7489                         I40E_INSET_TUNNEL_ID},
7490                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7491                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7492                         I40E_INSET_FLEX_PAYLOAD_W1},
7493                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7494                         I40E_INSET_FLEX_PAYLOAD_W2},
7495                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7496                         I40E_INSET_FLEX_PAYLOAD_W3},
7497                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7498                         I40E_INSET_FLEX_PAYLOAD_W4},
7499                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7500                         I40E_INSET_FLEX_PAYLOAD_W5},
7501                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7502                         I40E_INSET_FLEX_PAYLOAD_W6},
7503                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7504                         I40E_INSET_FLEX_PAYLOAD_W7},
7505                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7506                         I40E_INSET_FLEX_PAYLOAD_W8},
7507         };
7508
7509         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7510                 return ret;
7511
7512         /* Only one item allowed for default or all */
7513         if (size == 1) {
7514                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7515                         *inset = i40e_get_default_input_set(pctype);
7516                         return 0;
7517                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7518                         *inset = I40E_INSET_NONE;
7519                         return 0;
7520                 }
7521         }
7522
7523         for (i = 0, *inset = 0; i < size; i++) {
7524                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7525                         if (field[i] == inset_convert_table[j].field) {
7526                                 *inset |= inset_convert_table[j].inset;
7527                                 break;
7528                         }
7529                 }
7530
7531                 /* It contains unsupported input set, return immediately */
7532                 if (j == RTE_DIM(inset_convert_table))
7533                         return ret;
7534         }
7535
7536         return 0;
7537 }
7538
7539 /**
7540  * Translate the input set from bit masks to register aware bit masks
7541  * and vice versa
7542  */
7543 static uint64_t
7544 i40e_translate_input_set_reg(uint64_t input)
7545 {
7546         uint64_t val = 0;
7547         uint16_t i;
7548
7549         static const struct {
7550                 uint64_t inset;
7551                 uint64_t inset_reg;
7552         } inset_map[] = {
7553                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7554                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7555                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7556                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7557                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7558                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7559                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7560                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7561                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7562                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7563                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7564                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7565                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7566                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7567                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7568                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7569                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7570                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7571                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7572                 {I40E_INSET_TUNNEL_DMAC,
7573                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7574                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7575                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7576                 {I40E_INSET_TUNNEL_SRC_PORT,
7577                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7578                 {I40E_INSET_TUNNEL_DST_PORT,
7579                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7580                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7581                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7582                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7583                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7584                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7585                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7586                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7587                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7588                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7589         };
7590
7591         if (input == 0)
7592                 return val;
7593
7594         /* Translate input set to register aware inset */
7595         for (i = 0; i < RTE_DIM(inset_map); i++) {
7596                 if (input & inset_map[i].inset)
7597                         val |= inset_map[i].inset_reg;
7598         }
7599
7600         return val;
7601 }
7602
7603 static int
7604 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7605 {
7606         uint8_t i, idx = 0;
7607         uint64_t inset_need_mask = inset;
7608
7609         static const struct {
7610                 uint64_t inset;
7611                 uint32_t mask;
7612         } inset_mask_map[] = {
7613                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7614                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7615                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7616                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7617                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7618                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7619                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7620                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7621         };
7622
7623         if (!inset || !mask || !nb_elem)
7624                 return 0;
7625
7626         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7627                 /* Clear the inset bit, if no MASK is required,
7628                  * for example proto + ttl
7629                  */
7630                 if ((inset & inset_mask_map[i].inset) ==
7631                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7632                         inset_need_mask &= ~inset_mask_map[i].inset;
7633                 if (!inset_need_mask)
7634                         return 0;
7635         }
7636         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7637                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7638                     inset_mask_map[i].inset) {
7639                         if (idx >= nb_elem) {
7640                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7641                                 return -EINVAL;
7642                         }
7643                         mask[idx] = inset_mask_map[i].mask;
7644                         idx++;
7645                 }
7646         }
7647
7648         return idx;
7649 }
7650
7651 static void
7652 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7653 {
7654         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7655
7656         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7657         if (reg != val)
7658                 i40e_write_rx_ctl(hw, addr, val);
7659         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7660                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7661 }
7662
7663 static void
7664 i40e_filter_input_set_init(struct i40e_pf *pf)
7665 {
7666         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7667         enum i40e_filter_pctype pctype;
7668         uint64_t input_set, inset_reg;
7669         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7670         int num, i;
7671
7672         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7673              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7674                 if (!I40E_VALID_PCTYPE(pctype))
7675                         continue;
7676                 input_set = i40e_get_default_input_set(pctype);
7677
7678                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7679                                                    I40E_INSET_MASK_NUM_REG);
7680                 if (num < 0)
7681                         return;
7682                 inset_reg = i40e_translate_input_set_reg(input_set);
7683
7684                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7685                                       (uint32_t)(inset_reg & UINT32_MAX));
7686                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7687                                      (uint32_t)((inset_reg >>
7688                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7689                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7690                                       (uint32_t)(inset_reg & UINT32_MAX));
7691                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7692                                      (uint32_t)((inset_reg >>
7693                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7694
7695                 for (i = 0; i < num; i++) {
7696                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7697                                              mask_reg[i]);
7698                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7699                                              mask_reg[i]);
7700                 }
7701                 /*clear unused mask registers of the pctype */
7702                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7703                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7704                                              0);
7705                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7706                                              0);
7707                 }
7708                 I40E_WRITE_FLUSH(hw);
7709
7710                 /* store the default input set */
7711                 pf->hash_input_set[pctype] = input_set;
7712                 pf->fdir.input_set[pctype] = input_set;
7713         }
7714 }
7715
7716 int
7717 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7718                          struct rte_eth_input_set_conf *conf)
7719 {
7720         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7721         enum i40e_filter_pctype pctype;
7722         uint64_t input_set, inset_reg = 0;
7723         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7724         int ret, i, num;
7725
7726         if (!conf) {
7727                 PMD_DRV_LOG(ERR, "Invalid pointer");
7728                 return -EFAULT;
7729         }
7730         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7731             conf->op != RTE_ETH_INPUT_SET_ADD) {
7732                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7733                 return -EINVAL;
7734         }
7735
7736         if (!I40E_VALID_FLOW(conf->flow_type)) {
7737                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7738                 return -EINVAL;
7739         }
7740
7741 #ifdef X722_SUPPORT
7742         /* get translated pctype value in fd pctype register */
7743         pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7744                 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7745                 conf->flow_type)));
7746 #else
7747         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7748 #endif
7749
7750         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7751                                    conf->inset_size);
7752         if (ret) {
7753                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7754                 return -EINVAL;
7755         }
7756         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7757                                     input_set) != 0) {
7758                 PMD_DRV_LOG(ERR, "Invalid input set");
7759                 return -EINVAL;
7760         }
7761         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7762                 /* get inset value in register */
7763                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7764                 inset_reg <<= I40E_32_BIT_WIDTH;
7765                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7766                 input_set |= pf->hash_input_set[pctype];
7767         }
7768         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7769                                            I40E_INSET_MASK_NUM_REG);
7770         if (num < 0)
7771                 return -EINVAL;
7772
7773         inset_reg |= i40e_translate_input_set_reg(input_set);
7774
7775         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7776                               (uint32_t)(inset_reg & UINT32_MAX));
7777         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7778                              (uint32_t)((inset_reg >>
7779                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7780
7781         for (i = 0; i < num; i++)
7782                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7783                                      mask_reg[i]);
7784         /*clear unused mask registers of the pctype */
7785         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7786                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7787                                      0);
7788         I40E_WRITE_FLUSH(hw);
7789
7790         pf->hash_input_set[pctype] = input_set;
7791         return 0;
7792 }
7793
7794 int
7795 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7796                          struct rte_eth_input_set_conf *conf)
7797 {
7798         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7799         enum i40e_filter_pctype pctype;
7800         uint64_t input_set, inset_reg = 0;
7801         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7802         int ret, i, num;
7803
7804         if (!hw || !conf) {
7805                 PMD_DRV_LOG(ERR, "Invalid pointer");
7806                 return -EFAULT;
7807         }
7808         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7809             conf->op != RTE_ETH_INPUT_SET_ADD) {
7810                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7811                 return -EINVAL;
7812         }
7813
7814         if (!I40E_VALID_FLOW(conf->flow_type)) {
7815                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7816                 return -EINVAL;
7817         }
7818
7819         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7820
7821         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7822                                    conf->inset_size);
7823         if (ret) {
7824                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7825                 return -EINVAL;
7826         }
7827         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7828                                     input_set) != 0) {
7829                 PMD_DRV_LOG(ERR, "Invalid input set");
7830                 return -EINVAL;
7831         }
7832
7833         /* get inset value in register */
7834         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7835         inset_reg <<= I40E_32_BIT_WIDTH;
7836         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7837
7838         /* Can not change the inset reg for flex payload for fdir,
7839          * it is done by writing I40E_PRTQF_FD_FLXINSET
7840          * in i40e_set_flex_mask_on_pctype.
7841          */
7842         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7843                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7844         else
7845                 input_set |= pf->fdir.input_set[pctype];
7846         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7847                                            I40E_INSET_MASK_NUM_REG);
7848         if (num < 0)
7849                 return -EINVAL;
7850
7851         inset_reg |= i40e_translate_input_set_reg(input_set);
7852
7853         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7854                               (uint32_t)(inset_reg & UINT32_MAX));
7855         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7856                              (uint32_t)((inset_reg >>
7857                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7858
7859         for (i = 0; i < num; i++)
7860                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7861                                      mask_reg[i]);
7862         /*clear unused mask registers of the pctype */
7863         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7864                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7865                                      0);
7866         I40E_WRITE_FLUSH(hw);
7867
7868         pf->fdir.input_set[pctype] = input_set;
7869         return 0;
7870 }
7871
7872 static int
7873 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7874 {
7875         int ret = 0;
7876
7877         if (!hw || !info) {
7878                 PMD_DRV_LOG(ERR, "Invalid pointer");
7879                 return -EFAULT;
7880         }
7881
7882         switch (info->info_type) {
7883         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7884                 i40e_get_symmetric_hash_enable_per_port(hw,
7885                                         &(info->info.enable));
7886                 break;
7887         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7888                 ret = i40e_get_hash_filter_global_config(hw,
7889                                 &(info->info.global_conf));
7890                 break;
7891         default:
7892                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7893                                                         info->info_type);
7894                 ret = -EINVAL;
7895                 break;
7896         }
7897
7898         return ret;
7899 }
7900
7901 static int
7902 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7903 {
7904         int ret = 0;
7905
7906         if (!hw || !info) {
7907                 PMD_DRV_LOG(ERR, "Invalid pointer");
7908                 return -EFAULT;
7909         }
7910
7911         switch (info->info_type) {
7912         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7913                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7914                 break;
7915         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7916                 ret = i40e_set_hash_filter_global_config(hw,
7917                                 &(info->info.global_conf));
7918                 break;
7919         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7920                 ret = i40e_hash_filter_inset_select(hw,
7921                                                &(info->info.input_set_conf));
7922                 break;
7923
7924         default:
7925                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7926                                                         info->info_type);
7927                 ret = -EINVAL;
7928                 break;
7929         }
7930
7931         return ret;
7932 }
7933
7934 /* Operations for hash function */
7935 static int
7936 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7937                       enum rte_filter_op filter_op,
7938                       void *arg)
7939 {
7940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7941         int ret = 0;
7942
7943         switch (filter_op) {
7944         case RTE_ETH_FILTER_NOP:
7945                 break;
7946         case RTE_ETH_FILTER_GET:
7947                 ret = i40e_hash_filter_get(hw,
7948                         (struct rte_eth_hash_filter_info *)arg);
7949                 break;
7950         case RTE_ETH_FILTER_SET:
7951                 ret = i40e_hash_filter_set(hw,
7952                         (struct rte_eth_hash_filter_info *)arg);
7953                 break;
7954         default:
7955                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7956                                                                 filter_op);
7957                 ret = -ENOTSUP;
7958                 break;
7959         }
7960
7961         return ret;
7962 }
7963
7964 /*
7965  * Configure ethertype filter, which can director packet by filtering
7966  * with mac address and ether_type or only ether_type
7967  */
7968 static int
7969 i40e_ethertype_filter_set(struct i40e_pf *pf,
7970                         struct rte_eth_ethertype_filter *filter,
7971                         bool add)
7972 {
7973         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7974         struct i40e_control_filter_stats stats;
7975         uint16_t flags = 0;
7976         int ret;
7977
7978         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7979                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7980                 return -EINVAL;
7981         }
7982         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7983                 filter->ether_type == ETHER_TYPE_IPv6) {
7984                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7985                         " control packet filter.", filter->ether_type);
7986                 return -EINVAL;
7987         }
7988         if (filter->ether_type == ETHER_TYPE_VLAN)
7989                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7990                         " not supported.");
7991
7992         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7993                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7994         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7995                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7996         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7997
7998         memset(&stats, 0, sizeof(stats));
7999         ret = i40e_aq_add_rem_control_packet_filter(hw,
8000                         filter->mac_addr.addr_bytes,
8001                         filter->ether_type, flags,
8002                         pf->main_vsi->seid,
8003                         filter->queue, add, &stats, NULL);
8004
8005         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8006                          " mac_etype_used = %u, etype_used = %u,"
8007                          " mac_etype_free = %u, etype_free = %u\n",
8008                          ret, stats.mac_etype_used, stats.etype_used,
8009                          stats.mac_etype_free, stats.etype_free);
8010         if (ret < 0)
8011                 return -ENOSYS;
8012         return 0;
8013 }
8014
8015 /*
8016  * Handle operations for ethertype filter.
8017  */
8018 static int
8019 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8020                                 enum rte_filter_op filter_op,
8021                                 void *arg)
8022 {
8023         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8024         int ret = 0;
8025
8026         if (filter_op == RTE_ETH_FILTER_NOP)
8027                 return ret;
8028
8029         if (arg == NULL) {
8030                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8031                             filter_op);
8032                 return -EINVAL;
8033         }
8034
8035         switch (filter_op) {
8036         case RTE_ETH_FILTER_ADD:
8037                 ret = i40e_ethertype_filter_set(pf,
8038                         (struct rte_eth_ethertype_filter *)arg,
8039                         TRUE);
8040                 break;
8041         case RTE_ETH_FILTER_DELETE:
8042                 ret = i40e_ethertype_filter_set(pf,
8043                         (struct rte_eth_ethertype_filter *)arg,
8044                         FALSE);
8045                 break;
8046         default:
8047                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8048                 ret = -ENOSYS;
8049                 break;
8050         }
8051         return ret;
8052 }
8053
8054 static int
8055 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8056                      enum rte_filter_type filter_type,
8057                      enum rte_filter_op filter_op,
8058                      void *arg)
8059 {
8060         int ret = 0;
8061
8062         if (dev == NULL)
8063                 return -EINVAL;
8064
8065         switch (filter_type) {
8066         case RTE_ETH_FILTER_NONE:
8067                 /* For global configuration */
8068                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8069                 break;
8070         case RTE_ETH_FILTER_HASH:
8071                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8072                 break;
8073         case RTE_ETH_FILTER_MACVLAN:
8074                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8075                 break;
8076         case RTE_ETH_FILTER_ETHERTYPE:
8077                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8078                 break;
8079         case RTE_ETH_FILTER_TUNNEL:
8080                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8081                 break;
8082         case RTE_ETH_FILTER_FDIR:
8083                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8084                 break;
8085         default:
8086                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8087                                                         filter_type);
8088                 ret = -EINVAL;
8089                 break;
8090         }
8091
8092         return ret;
8093 }
8094
8095 /*
8096  * Check and enable Extended Tag.
8097  * Enabling Extended Tag is important for 40G performance.
8098  */
8099 static void
8100 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8101 {
8102         uint32_t buf = 0;
8103         int ret;
8104
8105         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8106                                       PCI_DEV_CAP_REG);
8107         if (ret < 0) {
8108                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8109                             PCI_DEV_CAP_REG);
8110                 return;
8111         }
8112         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8113                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8114                 return;
8115         }
8116
8117         buf = 0;
8118         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8119                                       PCI_DEV_CTRL_REG);
8120         if (ret < 0) {
8121                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8122                             PCI_DEV_CTRL_REG);
8123                 return;
8124         }
8125         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8126                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8127                 return;
8128         }
8129         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8130         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8131                                        PCI_DEV_CTRL_REG);
8132         if (ret < 0) {
8133                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8134                             PCI_DEV_CTRL_REG);
8135                 return;
8136         }
8137 }
8138
8139 /*
8140  * As some registers wouldn't be reset unless a global hardware reset,
8141  * hardware initialization is needed to put those registers into an
8142  * expected initial state.
8143  */
8144 static void
8145 i40e_hw_init(struct rte_eth_dev *dev)
8146 {
8147         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8148
8149         i40e_enable_extended_tag(dev);
8150
8151         /* clear the PF Queue Filter control register */
8152         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8153
8154         /* Disable symmetric hash per port */
8155         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8156 }
8157
8158 enum i40e_filter_pctype
8159 i40e_flowtype_to_pctype(uint16_t flow_type)
8160 {
8161         static const enum i40e_filter_pctype pctype_table[] = {
8162                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8163                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8164                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8165                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8166                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8167                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8168                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8169                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8170                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8171                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8172                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8173                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8174                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8175                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8176                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8177                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8178                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8179                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8180                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8181         };
8182
8183         return pctype_table[flow_type];
8184 }
8185
8186 uint16_t
8187 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8188 {
8189         static const uint16_t flowtype_table[] = {
8190                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8191                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8192                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8193 #ifdef X722_SUPPORT
8194                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8195                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8196                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8197                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8198 #endif
8199                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8200                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8201 #ifdef X722_SUPPORT
8202                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8203                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8204 #endif
8205                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8206                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8207                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8208                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8209                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8210                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8211                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8212 #ifdef X722_SUPPORT
8213                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8214                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8215                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8216                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8217 #endif
8218                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8219                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8220 #ifdef X722_SUPPORT
8221                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8222                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8223 #endif
8224                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8225                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8226                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8227                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8228                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8229         };
8230
8231         return flowtype_table[pctype];
8232 }
8233
8234 /*
8235  * On X710, performance number is far from the expectation on recent firmware
8236  * versions; on XL710, performance number is also far from the expectation on
8237  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8238  * mode is enabled and port MAC address is equal to the packet destination MAC
8239  * address. The fix for this issue may not be integrated in the following
8240  * firmware version. So the workaround in software driver is needed. It needs
8241  * to modify the initial values of 3 internal only registers for both X710 and
8242  * XL710. Note that the values for X710 or XL710 could be different, and the
8243  * workaround can be removed when it is fixed in firmware in the future.
8244  */
8245
8246 /* For both X710 and XL710 */
8247 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8248 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8249
8250 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8251 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8252
8253 /* For X710 */
8254 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8255 /* For XL710 */
8256 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8257 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8258
8259 static int
8260 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8261 {
8262         enum i40e_status_code status;
8263         struct i40e_aq_get_phy_abilities_resp phy_ab;
8264         int ret = -ENOTSUP;
8265
8266         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8267                                               NULL);
8268
8269         if (status)
8270                 return ret;
8271
8272         return 0;
8273 }
8274
8275
8276 static void
8277 i40e_configure_registers(struct i40e_hw *hw)
8278 {
8279         static struct {
8280                 uint32_t addr;
8281                 uint64_t val;
8282         } reg_table[] = {
8283                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8284                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8285                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8286         };
8287         uint64_t reg;
8288         uint32_t i;
8289         int ret;
8290
8291         for (i = 0; i < RTE_DIM(reg_table); i++) {
8292                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8293                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) /* For XL710 */
8294                                 reg_table[i].val =
8295                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8296                         else /* For X710 */
8297                                 reg_table[i].val =
8298                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8299                 }
8300
8301                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8302                                                         &reg, NULL);
8303                 if (ret < 0) {
8304                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8305                                                         reg_table[i].addr);
8306                         break;
8307                 }
8308                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8309                                                 reg_table[i].addr, reg);
8310                 if (reg == reg_table[i].val)
8311                         continue;
8312
8313                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8314                                                 reg_table[i].val, NULL);
8315                 if (ret < 0) {
8316                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8317                                 "address of 0x%"PRIx32, reg_table[i].val,
8318                                                         reg_table[i].addr);
8319                         break;
8320                 }
8321                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8322                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8323         }
8324 }
8325
8326 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8327 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8328 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8329 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8330 static int
8331 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8332 {
8333         uint32_t reg;
8334         int ret;
8335
8336         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8337                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8338                 return -EINVAL;
8339         }
8340
8341         /* Configure for double VLAN RX stripping */
8342         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8343         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8344                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8345                 ret = i40e_aq_debug_write_register(hw,
8346                                                    I40E_VSI_TSR(vsi->vsi_id),
8347                                                    reg, NULL);
8348                 if (ret < 0) {
8349                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8350                                     vsi->vsi_id);
8351                         return I40E_ERR_CONFIG;
8352                 }
8353         }
8354
8355         /* Configure for double VLAN TX insertion */
8356         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8357         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8358                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8359                 ret = i40e_aq_debug_write_register(hw,
8360                                                    I40E_VSI_L2TAGSTXVALID(
8361                                                    vsi->vsi_id), reg, NULL);
8362                 if (ret < 0) {
8363                         PMD_DRV_LOG(ERR, "Failed to update "
8364                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8365                         return I40E_ERR_CONFIG;
8366                 }
8367         }
8368
8369         return 0;
8370 }
8371
8372 /**
8373  * i40e_aq_add_mirror_rule
8374  * @hw: pointer to the hardware structure
8375  * @seid: VEB seid to add mirror rule to
8376  * @dst_id: destination vsi seid
8377  * @entries: Buffer which contains the entities to be mirrored
8378  * @count: number of entities contained in the buffer
8379  * @rule_id:the rule_id of the rule to be added
8380  *
8381  * Add a mirror rule for a given veb.
8382  *
8383  **/
8384 static enum i40e_status_code
8385 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8386                         uint16_t seid, uint16_t dst_id,
8387                         uint16_t rule_type, uint16_t *entries,
8388                         uint16_t count, uint16_t *rule_id)
8389 {
8390         struct i40e_aq_desc desc;
8391         struct i40e_aqc_add_delete_mirror_rule cmd;
8392         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8393                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8394                 &desc.params.raw;
8395         uint16_t buff_len;
8396         enum i40e_status_code status;
8397
8398         i40e_fill_default_direct_cmd_desc(&desc,
8399                                           i40e_aqc_opc_add_mirror_rule);
8400         memset(&cmd, 0, sizeof(cmd));
8401
8402         buff_len = sizeof(uint16_t) * count;
8403         desc.datalen = rte_cpu_to_le_16(buff_len);
8404         if (buff_len > 0)
8405                 desc.flags |= rte_cpu_to_le_16(
8406                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8407         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8408                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8409         cmd.num_entries = rte_cpu_to_le_16(count);
8410         cmd.seid = rte_cpu_to_le_16(seid);
8411         cmd.destination = rte_cpu_to_le_16(dst_id);
8412
8413         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8414         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8415         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8416                          "rule_id = %u"
8417                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8418                          hw->aq.asq_last_status, resp->rule_id,
8419                          resp->mirror_rules_used, resp->mirror_rules_free);
8420         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8421
8422         return status;
8423 }
8424
8425 /**
8426  * i40e_aq_del_mirror_rule
8427  * @hw: pointer to the hardware structure
8428  * @seid: VEB seid to add mirror rule to
8429  * @entries: Buffer which contains the entities to be mirrored
8430  * @count: number of entities contained in the buffer
8431  * @rule_id:the rule_id of the rule to be delete
8432  *
8433  * Delete a mirror rule for a given veb.
8434  *
8435  **/
8436 static enum i40e_status_code
8437 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8438                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8439                 uint16_t count, uint16_t rule_id)
8440 {
8441         struct i40e_aq_desc desc;
8442         struct i40e_aqc_add_delete_mirror_rule cmd;
8443         uint16_t buff_len = 0;
8444         enum i40e_status_code status;
8445         void *buff = NULL;
8446
8447         i40e_fill_default_direct_cmd_desc(&desc,
8448                                           i40e_aqc_opc_delete_mirror_rule);
8449         memset(&cmd, 0, sizeof(cmd));
8450         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8451                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8452                                                           I40E_AQ_FLAG_RD));
8453                 cmd.num_entries = count;
8454                 buff_len = sizeof(uint16_t) * count;
8455                 desc.datalen = rte_cpu_to_le_16(buff_len);
8456                 buff = (void *)entries;
8457         } else
8458                 /* rule id is filled in destination field for deleting mirror rule */
8459                 cmd.destination = rte_cpu_to_le_16(rule_id);
8460
8461         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8462                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8463         cmd.seid = rte_cpu_to_le_16(seid);
8464
8465         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8466         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8467
8468         return status;
8469 }
8470
8471 /**
8472  * i40e_mirror_rule_set
8473  * @dev: pointer to the hardware structure
8474  * @mirror_conf: mirror rule info
8475  * @sw_id: mirror rule's sw_id
8476  * @on: enable/disable
8477  *
8478  * set a mirror rule.
8479  *
8480  **/
8481 static int
8482 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8483                         struct rte_eth_mirror_conf *mirror_conf,
8484                         uint8_t sw_id, uint8_t on)
8485 {
8486         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8487         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8488         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8489         struct i40e_mirror_rule *parent = NULL;
8490         uint16_t seid, dst_seid, rule_id;
8491         uint16_t i, j = 0;
8492         int ret;
8493
8494         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8495
8496         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8497                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8498                         " without veb or vfs.");
8499                 return -ENOSYS;
8500         }
8501         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8502                 PMD_DRV_LOG(ERR, "mirror table is full.");
8503                 return -ENOSPC;
8504         }
8505         if (mirror_conf->dst_pool > pf->vf_num) {
8506                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8507                                  mirror_conf->dst_pool);
8508                 return -EINVAL;
8509         }
8510
8511         seid = pf->main_vsi->veb->seid;
8512
8513         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8514                 if (sw_id <= it->index) {
8515                         mirr_rule = it;
8516                         break;
8517                 }
8518                 parent = it;
8519         }
8520         if (mirr_rule && sw_id == mirr_rule->index) {
8521                 if (on) {
8522                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8523                         return -EEXIST;
8524                 } else {
8525                         ret = i40e_aq_del_mirror_rule(hw, seid,
8526                                         mirr_rule->rule_type,
8527                                         mirr_rule->entries,
8528                                         mirr_rule->num_entries, mirr_rule->id);
8529                         if (ret < 0) {
8530                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8531                                                    " ret = %d, aq_err = %d.",
8532                                                    ret, hw->aq.asq_last_status);
8533                                 return -ENOSYS;
8534                         }
8535                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8536                         rte_free(mirr_rule);
8537                         pf->nb_mirror_rule--;
8538                         return 0;
8539                 }
8540         } else if (!on) {
8541                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8542                 return -ENOENT;
8543         }
8544
8545         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8546                                 sizeof(struct i40e_mirror_rule) , 0);
8547         if (!mirr_rule) {
8548                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8549                 return I40E_ERR_NO_MEMORY;
8550         }
8551         switch (mirror_conf->rule_type) {
8552         case ETH_MIRROR_VLAN:
8553                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8554                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8555                                 mirr_rule->entries[j] =
8556                                         mirror_conf->vlan.vlan_id[i];
8557                                 j++;
8558                         }
8559                 }
8560                 if (j == 0) {
8561                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8562                         rte_free(mirr_rule);
8563                         return -EINVAL;
8564                 }
8565                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8566                 break;
8567         case ETH_MIRROR_VIRTUAL_POOL_UP:
8568         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8569                 /* check if the specified pool bit is out of range */
8570                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8571                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8572                         rte_free(mirr_rule);
8573                         return -EINVAL;
8574                 }
8575                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8576                         if (mirror_conf->pool_mask & (1ULL << i)) {
8577                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8578                                 j++;
8579                         }
8580                 }
8581                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8582                         /* add pf vsi to entries */
8583                         mirr_rule->entries[j] = pf->main_vsi_seid;
8584                         j++;
8585                 }
8586                 if (j == 0) {
8587                         PMD_DRV_LOG(ERR, "pool is not specified.");
8588                         rte_free(mirr_rule);
8589                         return -EINVAL;
8590                 }
8591                 /* egress and ingress in aq commands means from switch but not port */
8592                 mirr_rule->rule_type =
8593                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8594                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8595                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8596                 break;
8597         case ETH_MIRROR_UPLINK_PORT:
8598                 /* egress and ingress in aq commands means from switch but not port*/
8599                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8600                 break;
8601         case ETH_MIRROR_DOWNLINK_PORT:
8602                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8603                 break;
8604         default:
8605                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8606                         mirror_conf->rule_type);
8607                 rte_free(mirr_rule);
8608                 return -EINVAL;
8609         }
8610
8611         /* If the dst_pool is equal to vf_num, consider it as PF */
8612         if (mirror_conf->dst_pool == pf->vf_num)
8613                 dst_seid = pf->main_vsi_seid;
8614         else
8615                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8616
8617         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8618                                       mirr_rule->rule_type, mirr_rule->entries,
8619                                       j, &rule_id);
8620         if (ret < 0) {
8621                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8622                                    " ret = %d, aq_err = %d.",
8623                                    ret, hw->aq.asq_last_status);
8624                 rte_free(mirr_rule);
8625                 return -ENOSYS;
8626         }
8627
8628         mirr_rule->index = sw_id;
8629         mirr_rule->num_entries = j;
8630         mirr_rule->id = rule_id;
8631         mirr_rule->dst_vsi_seid = dst_seid;
8632
8633         if (parent)
8634                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8635         else
8636                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8637
8638         pf->nb_mirror_rule++;
8639         return 0;
8640 }
8641
8642 /**
8643  * i40e_mirror_rule_reset
8644  * @dev: pointer to the device
8645  * @sw_id: mirror rule's sw_id
8646  *
8647  * reset a mirror rule.
8648  *
8649  **/
8650 static int
8651 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8652 {
8653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8655         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8656         uint16_t seid;
8657         int ret;
8658
8659         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8660
8661         seid = pf->main_vsi->veb->seid;
8662
8663         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8664                 if (sw_id == it->index) {
8665                         mirr_rule = it;
8666                         break;
8667                 }
8668         }
8669         if (mirr_rule) {
8670                 ret = i40e_aq_del_mirror_rule(hw, seid,
8671                                 mirr_rule->rule_type,
8672                                 mirr_rule->entries,
8673                                 mirr_rule->num_entries, mirr_rule->id);
8674                 if (ret < 0) {
8675                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8676                                            " status = %d, aq_err = %d.",
8677                                            ret, hw->aq.asq_last_status);
8678                         return -ENOSYS;
8679                 }
8680                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8681                 rte_free(mirr_rule);
8682                 pf->nb_mirror_rule--;
8683         } else {
8684                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8685                 return -ENOENT;
8686         }
8687         return 0;
8688 }
8689
8690 static uint64_t
8691 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8692 {
8693         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8694         uint64_t systim_cycles;
8695
8696         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8697         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8698                         << 32;
8699
8700         return systim_cycles;
8701 }
8702
8703 static uint64_t
8704 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8705 {
8706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8707         uint64_t rx_tstamp;
8708
8709         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8710         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8711                         << 32;
8712
8713         return rx_tstamp;
8714 }
8715
8716 static uint64_t
8717 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8718 {
8719         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8720         uint64_t tx_tstamp;
8721
8722         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8723         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8724                         << 32;
8725
8726         return tx_tstamp;
8727 }
8728
8729 static void
8730 i40e_start_timecounters(struct rte_eth_dev *dev)
8731 {
8732         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8733         struct i40e_adapter *adapter =
8734                         (struct i40e_adapter *)dev->data->dev_private;
8735         struct rte_eth_link link;
8736         uint32_t tsync_inc_l;
8737         uint32_t tsync_inc_h;
8738
8739         /* Get current link speed. */
8740         memset(&link, 0, sizeof(link));
8741         i40e_dev_link_update(dev, 1);
8742         rte_i40e_dev_atomic_read_link_status(dev, &link);
8743
8744         switch (link.link_speed) {
8745         case ETH_SPEED_NUM_40G:
8746                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8747                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8748                 break;
8749         case ETH_SPEED_NUM_10G:
8750                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8751                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8752                 break;
8753         case ETH_SPEED_NUM_1G:
8754                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8755                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8756                 break;
8757         default:
8758                 tsync_inc_l = 0x0;
8759                 tsync_inc_h = 0x0;
8760         }
8761
8762         /* Set the timesync increment value. */
8763         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8764         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8765
8766         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8767         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8768         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8769
8770         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8771         adapter->systime_tc.cc_shift = 0;
8772         adapter->systime_tc.nsec_mask = 0;
8773
8774         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8775         adapter->rx_tstamp_tc.cc_shift = 0;
8776         adapter->rx_tstamp_tc.nsec_mask = 0;
8777
8778         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8779         adapter->tx_tstamp_tc.cc_shift = 0;
8780         adapter->tx_tstamp_tc.nsec_mask = 0;
8781 }
8782
8783 static int
8784 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8785 {
8786         struct i40e_adapter *adapter =
8787                         (struct i40e_adapter *)dev->data->dev_private;
8788
8789         adapter->systime_tc.nsec += delta;
8790         adapter->rx_tstamp_tc.nsec += delta;
8791         adapter->tx_tstamp_tc.nsec += delta;
8792
8793         return 0;
8794 }
8795
8796 static int
8797 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8798 {
8799         uint64_t ns;
8800         struct i40e_adapter *adapter =
8801                         (struct i40e_adapter *)dev->data->dev_private;
8802
8803         ns = rte_timespec_to_ns(ts);
8804
8805         /* Set the timecounters to a new value. */
8806         adapter->systime_tc.nsec = ns;
8807         adapter->rx_tstamp_tc.nsec = ns;
8808         adapter->tx_tstamp_tc.nsec = ns;
8809
8810         return 0;
8811 }
8812
8813 static int
8814 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8815 {
8816         uint64_t ns, systime_cycles;
8817         struct i40e_adapter *adapter =
8818                         (struct i40e_adapter *)dev->data->dev_private;
8819
8820         systime_cycles = i40e_read_systime_cyclecounter(dev);
8821         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8822         *ts = rte_ns_to_timespec(ns);
8823
8824         return 0;
8825 }
8826
8827 static int
8828 i40e_timesync_enable(struct rte_eth_dev *dev)
8829 {
8830         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8831         uint32_t tsync_ctl_l;
8832         uint32_t tsync_ctl_h;
8833
8834         /* Stop the timesync system time. */
8835         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8836         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8837         /* Reset the timesync system time value. */
8838         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8839         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8840
8841         i40e_start_timecounters(dev);
8842
8843         /* Clear timesync registers. */
8844         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8845         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8846         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8847         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8848         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8849         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8850
8851         /* Enable timestamping of PTP packets. */
8852         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8853         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8854
8855         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8856         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8857         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8858
8859         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8860         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8861
8862         return 0;
8863 }
8864
8865 static int
8866 i40e_timesync_disable(struct rte_eth_dev *dev)
8867 {
8868         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8869         uint32_t tsync_ctl_l;
8870         uint32_t tsync_ctl_h;
8871
8872         /* Disable timestamping of transmitted PTP packets. */
8873         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8874         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8875
8876         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8877         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8878
8879         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8880         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8881
8882         /* Reset the timesync increment value. */
8883         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8884         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8885
8886         return 0;
8887 }
8888
8889 static int
8890 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8891                                 struct timespec *timestamp, uint32_t flags)
8892 {
8893         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8894         struct i40e_adapter *adapter =
8895                 (struct i40e_adapter *)dev->data->dev_private;
8896
8897         uint32_t sync_status;
8898         uint32_t index = flags & 0x03;
8899         uint64_t rx_tstamp_cycles;
8900         uint64_t ns;
8901
8902         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8903         if ((sync_status & (1 << index)) == 0)
8904                 return -EINVAL;
8905
8906         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8907         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8908         *timestamp = rte_ns_to_timespec(ns);
8909
8910         return 0;
8911 }
8912
8913 static int
8914 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8915                                 struct timespec *timestamp)
8916 {
8917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8918         struct i40e_adapter *adapter =
8919                 (struct i40e_adapter *)dev->data->dev_private;
8920
8921         uint32_t sync_status;
8922         uint64_t tx_tstamp_cycles;
8923         uint64_t ns;
8924
8925         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8926         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8927                 return -EINVAL;
8928
8929         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8930         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8931         *timestamp = rte_ns_to_timespec(ns);
8932
8933         return 0;
8934 }
8935
8936 /*
8937  * i40e_parse_dcb_configure - parse dcb configure from user
8938  * @dev: the device being configured
8939  * @dcb_cfg: pointer of the result of parse
8940  * @*tc_map: bit map of enabled traffic classes
8941  *
8942  * Returns 0 on success, negative value on failure
8943  */
8944 static int
8945 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8946                          struct i40e_dcbx_config *dcb_cfg,
8947                          uint8_t *tc_map)
8948 {
8949         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8950         uint8_t i, tc_bw, bw_lf;
8951
8952         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8953
8954         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8955         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8956                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8957                 return -EINVAL;
8958         }
8959
8960         /* assume each tc has the same bw */
8961         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8962         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8963                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8964         /* to ensure the sum of tcbw is equal to 100 */
8965         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8966         for (i = 0; i < bw_lf; i++)
8967                 dcb_cfg->etscfg.tcbwtable[i]++;
8968
8969         /* assume each tc has the same Transmission Selection Algorithm */
8970         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8971                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8972
8973         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8974                 dcb_cfg->etscfg.prioritytable[i] =
8975                                 dcb_rx_conf->dcb_tc[i];
8976
8977         /* FW needs one App to configure HW */
8978         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8979         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8980         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8981         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8982
8983         if (dcb_rx_conf->nb_tcs == 0)
8984                 *tc_map = 1; /* tc0 only */
8985         else
8986                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8987
8988         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8989                 dcb_cfg->pfc.willing = 0;
8990                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8991                 dcb_cfg->pfc.pfcenable = *tc_map;
8992         }
8993         return 0;
8994 }
8995
8996
8997 static enum i40e_status_code
8998 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8999                               struct i40e_aqc_vsi_properties_data *info,
9000                               uint8_t enabled_tcmap)
9001 {
9002         enum i40e_status_code ret;
9003         int i, total_tc = 0;
9004         uint16_t qpnum_per_tc, bsf, qp_idx;
9005         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9006         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9007         uint16_t used_queues;
9008
9009         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9010         if (ret != I40E_SUCCESS)
9011                 return ret;
9012
9013         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9014                 if (enabled_tcmap & (1 << i))
9015                         total_tc++;
9016         }
9017         if (total_tc == 0)
9018                 total_tc = 1;
9019         vsi->enabled_tc = enabled_tcmap;
9020
9021         /* different VSI has different queues assigned */
9022         if (vsi->type == I40E_VSI_MAIN)
9023                 used_queues = dev_data->nb_rx_queues -
9024                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9025         else if (vsi->type == I40E_VSI_VMDQ2)
9026                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9027         else {
9028                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9029                 return I40E_ERR_NO_AVAILABLE_VSI;
9030         }
9031
9032         qpnum_per_tc = used_queues / total_tc;
9033         /* Number of queues per enabled TC */
9034         if (qpnum_per_tc == 0) {
9035                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9036                 return I40E_ERR_INVALID_QP_ID;
9037         }
9038         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9039                                 I40E_MAX_Q_PER_TC);
9040         bsf = rte_bsf32(qpnum_per_tc);
9041
9042         /**
9043          * Configure TC and queue mapping parameters, for enabled TC,
9044          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9045          * default queue will serve it.
9046          */
9047         qp_idx = 0;
9048         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9049                 if (vsi->enabled_tc & (1 << i)) {
9050                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9051                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9052                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9053                         qp_idx += qpnum_per_tc;
9054                 } else
9055                         info->tc_mapping[i] = 0;
9056         }
9057
9058         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9059         if (vsi->type == I40E_VSI_SRIOV) {
9060                 info->mapping_flags |=
9061                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9062                 for (i = 0; i < vsi->nb_qps; i++)
9063                         info->queue_mapping[i] =
9064                                 rte_cpu_to_le_16(vsi->base_queue + i);
9065         } else {
9066                 info->mapping_flags |=
9067                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9068                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9069         }
9070         info->valid_sections |=
9071                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9072
9073         return I40E_SUCCESS;
9074 }
9075
9076 /*
9077  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9078  * @veb: VEB to be configured
9079  * @tc_map: enabled TC bitmap
9080  *
9081  * Returns 0 on success, negative value on failure
9082  */
9083 static enum i40e_status_code
9084 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9085 {
9086         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9087         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9088         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9089         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9090         enum i40e_status_code ret = I40E_SUCCESS;
9091         int i;
9092         uint32_t bw_max;
9093
9094         /* Check if enabled_tc is same as existing or new TCs */
9095         if (veb->enabled_tc == tc_map)
9096                 return ret;
9097
9098         /* configure tc bandwidth */
9099         memset(&veb_bw, 0, sizeof(veb_bw));
9100         veb_bw.tc_valid_bits = tc_map;
9101         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9102         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9103                 if (tc_map & BIT_ULL(i))
9104                         veb_bw.tc_bw_share_credits[i] = 1;
9105         }
9106         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9107                                                    &veb_bw, NULL);
9108         if (ret) {
9109                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9110                                   " per TC failed = %d",
9111                                   hw->aq.asq_last_status);
9112                 return ret;
9113         }
9114
9115         memset(&ets_query, 0, sizeof(ets_query));
9116         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9117                                                    &ets_query, NULL);
9118         if (ret != I40E_SUCCESS) {
9119                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9120                                  " configuration %u", hw->aq.asq_last_status);
9121                 return ret;
9122         }
9123         memset(&bw_query, 0, sizeof(bw_query));
9124         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9125                                                   &bw_query, NULL);
9126         if (ret != I40E_SUCCESS) {
9127                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9128                                  " configuration %u", hw->aq.asq_last_status);
9129                 return ret;
9130         }
9131
9132         /* store and print out BW info */
9133         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9134         veb->bw_info.bw_max = ets_query.tc_bw_max;
9135         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9136         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9137         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9138                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9139                      I40E_16_BIT_WIDTH);
9140         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9141                 veb->bw_info.bw_ets_share_credits[i] =
9142                                 bw_query.tc_bw_share_credits[i];
9143                 veb->bw_info.bw_ets_credits[i] =
9144                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9145                 /* 4 bits per TC, 4th bit is reserved */
9146                 veb->bw_info.bw_ets_max[i] =
9147                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9148                                   RTE_LEN2MASK(3, uint8_t));
9149                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9150                             veb->bw_info.bw_ets_share_credits[i]);
9151                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9152                             veb->bw_info.bw_ets_credits[i]);
9153                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9154                             veb->bw_info.bw_ets_max[i]);
9155         }
9156
9157         veb->enabled_tc = tc_map;
9158
9159         return ret;
9160 }
9161
9162
9163 /*
9164  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9165  * @vsi: VSI to be configured
9166  * @tc_map: enabled TC bitmap
9167  *
9168  * Returns 0 on success, negative value on failure
9169  */
9170 static enum i40e_status_code
9171 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9172 {
9173         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9174         struct i40e_vsi_context ctxt;
9175         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9176         enum i40e_status_code ret = I40E_SUCCESS;
9177         int i;
9178
9179         /* Check if enabled_tc is same as existing or new TCs */
9180         if (vsi->enabled_tc == tc_map)
9181                 return ret;
9182
9183         /* configure tc bandwidth */
9184         memset(&bw_data, 0, sizeof(bw_data));
9185         bw_data.tc_valid_bits = tc_map;
9186         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9187         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9188                 if (tc_map & BIT_ULL(i))
9189                         bw_data.tc_bw_credits[i] = 1;
9190         }
9191         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9192         if (ret) {
9193                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9194                         " per TC failed = %d",
9195                         hw->aq.asq_last_status);
9196                 goto out;
9197         }
9198         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9199                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9200
9201         /* Update Queue Pairs Mapping for currently enabled UPs */
9202         ctxt.seid = vsi->seid;
9203         ctxt.pf_num = hw->pf_id;
9204         ctxt.vf_num = 0;
9205         ctxt.uplink_seid = vsi->uplink_seid;
9206         ctxt.info = vsi->info;
9207         i40e_get_cap(hw);
9208         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9209         if (ret)
9210                 goto out;
9211
9212         /* Update the VSI after updating the VSI queue-mapping information */
9213         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9214         if (ret) {
9215                 PMD_INIT_LOG(ERR, "Failed to configure "
9216                             "TC queue mapping = %d",
9217                             hw->aq.asq_last_status);
9218                 goto out;
9219         }
9220         /* update the local VSI info with updated queue map */
9221         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9222                                         sizeof(vsi->info.tc_mapping));
9223         (void)rte_memcpy(&vsi->info.queue_mapping,
9224                         &ctxt.info.queue_mapping,
9225                 sizeof(vsi->info.queue_mapping));
9226         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9227         vsi->info.valid_sections = 0;
9228
9229         /* query and update current VSI BW information */
9230         ret = i40e_vsi_get_bw_config(vsi);
9231         if (ret) {
9232                 PMD_INIT_LOG(ERR,
9233                          "Failed updating vsi bw info, err %s aq_err %s",
9234                          i40e_stat_str(hw, ret),
9235                          i40e_aq_str(hw, hw->aq.asq_last_status));
9236                 goto out;
9237         }
9238
9239         vsi->enabled_tc = tc_map;
9240
9241 out:
9242         return ret;
9243 }
9244
9245 /*
9246  * i40e_dcb_hw_configure - program the dcb setting to hw
9247  * @pf: pf the configuration is taken on
9248  * @new_cfg: new configuration
9249  * @tc_map: enabled TC bitmap
9250  *
9251  * Returns 0 on success, negative value on failure
9252  */
9253 static enum i40e_status_code
9254 i40e_dcb_hw_configure(struct i40e_pf *pf,
9255                       struct i40e_dcbx_config *new_cfg,
9256                       uint8_t tc_map)
9257 {
9258         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9259         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9260         struct i40e_vsi *main_vsi = pf->main_vsi;
9261         struct i40e_vsi_list *vsi_list;
9262         enum i40e_status_code ret;
9263         int i;
9264         uint32_t val;
9265
9266         /* Use the FW API if FW > v4.4*/
9267         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9268               (hw->aq.fw_maj_ver >= 5))) {
9269                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9270                                   " to configure DCB");
9271                 return I40E_ERR_FIRMWARE_API_VERSION;
9272         }
9273
9274         /* Check if need reconfiguration */
9275         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9276                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9277                 return I40E_SUCCESS;
9278         }
9279
9280         /* Copy the new config to the current config */
9281         *old_cfg = *new_cfg;
9282         old_cfg->etsrec = old_cfg->etscfg;
9283         ret = i40e_set_dcb_config(hw);
9284         if (ret) {
9285                 PMD_INIT_LOG(ERR,
9286                          "Set DCB Config failed, err %s aq_err %s\n",
9287                          i40e_stat_str(hw, ret),
9288                          i40e_aq_str(hw, hw->aq.asq_last_status));
9289                 return ret;
9290         }
9291         /* set receive Arbiter to RR mode and ETS scheme by default */
9292         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9293                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9294                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9295                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9296                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9297                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9298                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9299                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9300                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9301                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9302                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9303                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9304                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9305         }
9306         /* get local mib to check whether it is configured correctly */
9307         /* IEEE mode */
9308         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9309         /* Get Local DCB Config */
9310         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9311                                      &hw->local_dcbx_config);
9312
9313         /* if Veb is created, need to update TC of it at first */
9314         if (main_vsi->veb) {
9315                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9316                 if (ret)
9317                         PMD_INIT_LOG(WARNING,
9318                                  "Failed configuring TC for VEB seid=%d\n",
9319                                  main_vsi->veb->seid);
9320         }
9321         /* Update each VSI */
9322         i40e_vsi_config_tc(main_vsi, tc_map);
9323         if (main_vsi->veb) {
9324                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9325                         /* Beside main VSI and VMDQ VSIs, only enable default
9326                          * TC for other VSIs
9327                          */
9328                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9329                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9330                                                          tc_map);
9331                         else
9332                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9333                                                          I40E_DEFAULT_TCMAP);
9334                         if (ret)
9335                                 PMD_INIT_LOG(WARNING,
9336                                          "Failed configuring TC for VSI seid=%d\n",
9337                                          vsi_list->vsi->seid);
9338                         /* continue */
9339                 }
9340         }
9341         return I40E_SUCCESS;
9342 }
9343
9344 /*
9345  * i40e_dcb_init_configure - initial dcb config
9346  * @dev: device being configured
9347  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9348  *
9349  * Returns 0 on success, negative value on failure
9350  */
9351 static int
9352 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9353 {
9354         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9355         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9356         int ret = 0;
9357
9358         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9359                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9360                 return -ENOTSUP;
9361         }
9362
9363         /* DCB initialization:
9364          * Update DCB configuration from the Firmware and configure
9365          * LLDP MIB change event.
9366          */
9367         if (sw_dcb == TRUE) {
9368                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9369                 if (ret != I40E_SUCCESS)
9370                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9371
9372                 ret = i40e_init_dcb(hw);
9373                 /* if sw_dcb, lldp agent is stopped, the return from
9374                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9375                  * adminq status.
9376                  */
9377                 if (ret != I40E_SUCCESS &&
9378                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9379                         memset(&hw->local_dcbx_config, 0,
9380                                 sizeof(struct i40e_dcbx_config));
9381                         /* set dcb default configuration */
9382                         hw->local_dcbx_config.etscfg.willing = 0;
9383                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9384                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9385                         hw->local_dcbx_config.etscfg.tsatable[0] =
9386                                                 I40E_IEEE_TSA_ETS;
9387                         hw->local_dcbx_config.etsrec =
9388                                 hw->local_dcbx_config.etscfg;
9389                         hw->local_dcbx_config.pfc.willing = 0;
9390                         hw->local_dcbx_config.pfc.pfccap =
9391                                                 I40E_MAX_TRAFFIC_CLASS;
9392                         /* FW needs one App to configure HW */
9393                         hw->local_dcbx_config.numapps = 1;
9394                         hw->local_dcbx_config.app[0].selector =
9395                                                 I40E_APP_SEL_ETHTYPE;
9396                         hw->local_dcbx_config.app[0].priority = 3;
9397                         hw->local_dcbx_config.app[0].protocolid =
9398                                                 I40E_APP_PROTOID_FCOE;
9399                         ret = i40e_set_dcb_config(hw);
9400                         if (ret) {
9401                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9402                                         " err = %d, aq_err = %d.", ret,
9403                                           hw->aq.asq_last_status);
9404                                 return -ENOSYS;
9405                         }
9406                 } else {
9407                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9408                                           " aq_err = %d.", ret,
9409                                           hw->aq.asq_last_status);
9410                         return -ENOTSUP;
9411                 }
9412         } else {
9413                 ret = i40e_aq_start_lldp(hw, NULL);
9414                 if (ret != I40E_SUCCESS)
9415                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9416
9417                 ret = i40e_init_dcb(hw);
9418                 if (!ret) {
9419                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9420                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9421                                                   " DCBX offload.");
9422                                 return -ENOTSUP;
9423                         }
9424                 } else {
9425                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9426                                           " aq_err = %d.", ret,
9427                                           hw->aq.asq_last_status);
9428                         return -ENOTSUP;
9429                 }
9430         }
9431         return 0;
9432 }
9433
9434 /*
9435  * i40e_dcb_setup - setup dcb related config
9436  * @dev: device being configured
9437  *
9438  * Returns 0 on success, negative value on failure
9439  */
9440 static int
9441 i40e_dcb_setup(struct rte_eth_dev *dev)
9442 {
9443         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9444         struct i40e_dcbx_config dcb_cfg;
9445         uint8_t tc_map = 0;
9446         int ret = 0;
9447
9448         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9449                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9450                 return -ENOTSUP;
9451         }
9452
9453         if (pf->vf_num != 0)
9454                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9455
9456         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9457         if (ret) {
9458                 PMD_INIT_LOG(ERR, "invalid dcb config");
9459                 return -EINVAL;
9460         }
9461         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9462         if (ret) {
9463                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9464                 return -ENOSYS;
9465         }
9466
9467         return 0;
9468 }
9469
9470 static int
9471 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9472                       struct rte_eth_dcb_info *dcb_info)
9473 {
9474         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9475         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9476         struct i40e_vsi *vsi = pf->main_vsi;
9477         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9478         uint16_t bsf, tc_mapping;
9479         int i, j = 0;
9480
9481         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9482                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9483         else
9484                 dcb_info->nb_tcs = 1;
9485         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9486                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9487         for (i = 0; i < dcb_info->nb_tcs; i++)
9488                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9489
9490         /* get queue mapping if vmdq is disabled */
9491         if (!pf->nb_cfg_vmdq_vsi) {
9492                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9493                         if (!(vsi->enabled_tc & (1 << i)))
9494                                 continue;
9495                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9496                         dcb_info->tc_queue.tc_rxq[j][i].base =
9497                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9498                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9499                         dcb_info->tc_queue.tc_txq[j][i].base =
9500                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9501                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9502                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9503                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9504                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9505                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9506                 }
9507                 return 0;
9508         }
9509
9510         /* get queue mapping if vmdq is enabled */
9511         do {
9512                 vsi = pf->vmdq[j].vsi;
9513                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9514                         if (!(vsi->enabled_tc & (1 << i)))
9515                                 continue;
9516                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9517                         dcb_info->tc_queue.tc_rxq[j][i].base =
9518                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9519                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9520                         dcb_info->tc_queue.tc_txq[j][i].base =
9521                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9522                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9523                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9524                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9525                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9526                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9527                 }
9528                 j++;
9529         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9530         return 0;
9531 }
9532
9533 static int
9534 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9535 {
9536         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9538         uint16_t interval =
9539                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9540         uint16_t msix_intr;
9541
9542         msix_intr = intr_handle->intr_vec[queue_id];
9543         if (msix_intr == I40E_MISC_VEC_ID)
9544                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9545                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9546                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9547                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9548                                (interval <<
9549                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9550         else
9551                 I40E_WRITE_REG(hw,
9552                                I40E_PFINT_DYN_CTLN(msix_intr -
9553                                                    I40E_RX_VEC_START),
9554                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9555                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9556                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9557                                (interval <<
9558                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9559
9560         I40E_WRITE_FLUSH(hw);
9561         rte_intr_enable(&dev->pci_dev->intr_handle);
9562
9563         return 0;
9564 }
9565
9566 static int
9567 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9568 {
9569         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9570         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9571         uint16_t msix_intr;
9572
9573         msix_intr = intr_handle->intr_vec[queue_id];
9574         if (msix_intr == I40E_MISC_VEC_ID)
9575                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9576         else
9577                 I40E_WRITE_REG(hw,
9578                                I40E_PFINT_DYN_CTLN(msix_intr -
9579                                                    I40E_RX_VEC_START),
9580                                0);
9581         I40E_WRITE_FLUSH(hw);
9582
9583         return 0;
9584 }
9585
9586 static int i40e_get_regs(struct rte_eth_dev *dev,
9587                          struct rte_dev_reg_info *regs)
9588 {
9589         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9590         uint32_t *ptr_data = regs->data;
9591         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9592         const struct i40e_reg_info *reg_info;
9593
9594         if (ptr_data == NULL) {
9595                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9596                 regs->width = sizeof(uint32_t);
9597                 return 0;
9598         }
9599
9600         /* The first few registers have to be read using AQ operations */
9601         reg_idx = 0;
9602         while (i40e_regs_adminq[reg_idx].name) {
9603                 reg_info = &i40e_regs_adminq[reg_idx++];
9604                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9605                         for (arr_idx2 = 0;
9606                                         arr_idx2 <= reg_info->count2;
9607                                         arr_idx2++) {
9608                                 reg_offset = arr_idx * reg_info->stride1 +
9609                                         arr_idx2 * reg_info->stride2;
9610                                 reg_offset += reg_info->base_addr;
9611                                 ptr_data[reg_offset >> 2] =
9612                                         i40e_read_rx_ctl(hw, reg_offset);
9613                         }
9614         }
9615
9616         /* The remaining registers can be read using primitives */
9617         reg_idx = 0;
9618         while (i40e_regs_others[reg_idx].name) {
9619                 reg_info = &i40e_regs_others[reg_idx++];
9620                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9621                         for (arr_idx2 = 0;
9622                                         arr_idx2 <= reg_info->count2;
9623                                         arr_idx2++) {
9624                                 reg_offset = arr_idx * reg_info->stride1 +
9625                                         arr_idx2 * reg_info->stride2;
9626                                 reg_offset += reg_info->base_addr;
9627                                 ptr_data[reg_offset >> 2] =
9628                                         I40E_READ_REG(hw, reg_offset);
9629                         }
9630         }
9631
9632         return 0;
9633 }
9634
9635 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9636 {
9637         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9638
9639         /* Convert word count to byte count */
9640         return hw->nvm.sr_size << 1;
9641 }
9642
9643 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9644                            struct rte_dev_eeprom_info *eeprom)
9645 {
9646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9647         uint16_t *data = eeprom->data;
9648         uint16_t offset, length, cnt_words;
9649         int ret_code;
9650
9651         offset = eeprom->offset >> 1;
9652         length = eeprom->length >> 1;
9653         cnt_words = length;
9654
9655         if (offset > hw->nvm.sr_size ||
9656                 offset + length > hw->nvm.sr_size) {
9657                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9658                 return -EINVAL;
9659         }
9660
9661         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9662
9663         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9664         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9665                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9666                 return -EIO;
9667         }
9668
9669         return 0;
9670 }
9671
9672 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9673                                       struct ether_addr *mac_addr)
9674 {
9675         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9676
9677         if (!is_valid_assigned_ether_addr(mac_addr)) {
9678                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9679                 return;
9680         }
9681
9682         /* Flags: 0x3 updates port address */
9683         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9684 }
9685
9686 static int
9687 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9688 {
9689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9690         struct rte_eth_dev_data *dev_data = pf->dev_data;
9691         uint32_t frame_size = mtu + ETHER_HDR_LEN
9692                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9693         int ret = 0;
9694
9695         /* check if mtu is within the allowed range */
9696         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9697                 return -EINVAL;
9698
9699         /* mtu setting is forbidden if port is start */
9700         if (dev_data->dev_started) {
9701                 PMD_DRV_LOG(ERR,
9702                             "port %d must be stopped before configuration\n",
9703                             dev_data->port_id);
9704                 return -EBUSY;
9705         }
9706
9707         if (frame_size > ETHER_MAX_LEN)
9708                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9709         else
9710                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9711
9712         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9713
9714         return ret;
9715 }