1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
30 #include <rte_os_shim.h>
32 #include "i40e_logs.h"
33 #include "base/i40e_prototype.h"
34 #include "base/i40e_adminq_cmd.h"
35 #include "base/i40e_type.h"
36 #include "base/i40e_register.h"
37 #include "base/i40e_dcb.h"
38 #include "i40e_ethdev.h"
39 #include "i40e_rxtx.h"
41 #include "i40e_regs.h"
42 #include "rte_pmd_i40e.h"
43 #include "i40e_hash.h"
45 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
46 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
47 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
48 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
49 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
51 #define I40E_CLEAR_PXE_WAIT_MS 200
52 #define I40E_VSI_TSR_QINQ_STRIP 0x4010
53 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
55 /* Maximun number of capability elements */
56 #define I40E_MAX_CAP_ELE_NUM 128
58 /* Wait count and interval */
59 #define I40E_CHK_Q_ENA_COUNT 1000
60 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
62 /* Maximun number of VSI */
63 #define I40E_MAX_NUM_VSIS (384UL)
65 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
67 /* Flow control default timer */
68 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
70 /* Flow control enable fwd bit */
71 #define I40E_PRTMAC_FWD_CTRL 0x00000001
73 /* Receive Packet Buffer size */
74 #define I40E_RXPBSIZE (968 * 1024)
77 #define I40E_KILOSHIFT 10
79 /* Flow control default high water */
80 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
82 /* Flow control default low water */
83 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
85 /* Receive Average Packet Size in Byte*/
86 #define I40E_PACKET_AVERAGE_SIZE 128
88 /* Mask of PF interrupt causes */
89 #define I40E_PFINT_ICR0_ENA_MASK ( \
90 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
91 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
92 I40E_PFINT_ICR0_ENA_GRST_MASK | \
93 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
94 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
95 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
96 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
97 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
98 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
100 #define I40E_FLOW_TYPES ( \
101 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
106 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
108 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
109 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
110 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
111 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
113 /* Additional timesync values. */
114 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
115 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
116 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
117 #define I40E_PRTTSYN_TSYNENA 0x80000000
118 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
119 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
122 * Below are values for writing un-exposed registers suggested
125 /* Destination MAC address */
126 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
127 /* Source MAC address */
128 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
129 /* Outer (S-Tag) VLAN tag in the outer L2 header */
130 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
131 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
132 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
133 /* Single VLAN tag in the inner L2 header */
134 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
135 /* Source IPv4 address */
136 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
137 /* Destination IPv4 address */
138 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
139 /* Source IPv4 address for X722 */
140 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
141 /* Destination IPv4 address for X722 */
142 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
143 /* IPv4 Protocol for X722 */
144 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
145 /* IPv4 Time to Live for X722 */
146 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
147 /* IPv4 Type of Service (TOS) */
148 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
150 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
151 /* IPv4 Time to Live */
152 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
153 /* Source IPv6 address */
154 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
155 /* Destination IPv6 address */
156 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
157 /* IPv6 Traffic Class (TC) */
158 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
159 /* IPv6 Next Header */
160 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
162 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
164 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
165 /* Destination L4 port */
166 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
167 /* SCTP verification tag */
168 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
169 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
170 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
171 /* Source port of tunneling UDP */
172 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
173 /* Destination port of tunneling UDP */
174 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
175 /* UDP Tunneling ID, NVGRE/GRE key */
176 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
177 /* Last ether type */
178 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
179 /* Tunneling outer destination IPv4 address */
180 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
181 /* Tunneling outer destination IPv6 address */
182 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
183 /* 1st word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
185 /* 2nd word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
187 /* 3rd word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
189 /* 4th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
191 /* 5th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
193 /* 6th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
195 /* 7th word of flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
197 /* 8th word of flex payload */
198 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
199 /* all 8 words flex payload */
200 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
201 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
203 #define I40E_TRANSLATE_INSET 0
204 #define I40E_TRANSLATE_REG 1
206 #define I40E_INSET_IPV4_TOS_MASK 0x0000FF00UL
207 #define I40E_INSET_IPV4_TTL_MASK 0x000000FFUL
208 #define I40E_INSET_IPV4_PROTO_MASK 0x0000FF00UL
209 #define I40E_INSET_IPV6_TC_MASK 0x0000F00FUL
210 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x0000FF00UL
211 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000000FFUL
213 /* PCI offset for querying capability */
214 #define PCI_DEV_CAP_REG 0xA4
215 /* PCI offset for enabling/disabling Extended Tag */
216 #define PCI_DEV_CTRL_REG 0xA8
217 /* Bit mask of Extended Tag capability */
218 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
219 /* Bit shift of Extended Tag enable/disable */
220 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
221 /* Bit mask of Extended Tag enable/disable */
222 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
224 #define I40E_GLQF_PIT_IPV4_START 2
225 #define I40E_GLQF_PIT_IPV4_COUNT 2
226 #define I40E_GLQF_PIT_IPV6_START 4
227 #define I40E_GLQF_PIT_IPV6_COUNT 2
229 #define I40E_GLQF_PIT_SOURCE_OFF_GET(a) \
230 (((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
231 I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
233 #define I40E_GLQF_PIT_DEST_OFF_GET(a) \
234 (((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
235 I40E_GLQF_PIT_DEST_OFF_SHIFT)
237 #define I40E_GLQF_PIT_FSIZE_GET(a) (((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
238 I40E_GLQF_PIT_FSIZE_SHIFT)
240 #define I40E_GLQF_PIT_BUILD(off, mask) (((off) << 16) | (mask))
241 #define I40E_FDIR_FIELD_OFFSET(a) ((a) >> 1)
243 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
244 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
245 static int i40e_dev_configure(struct rte_eth_dev *dev);
246 static int i40e_dev_start(struct rte_eth_dev *dev);
247 static int i40e_dev_stop(struct rte_eth_dev *dev);
248 static int i40e_dev_close(struct rte_eth_dev *dev);
249 static int i40e_dev_reset(struct rte_eth_dev *dev);
250 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
251 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
252 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
253 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
254 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
255 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
256 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
259 struct rte_eth_xstat *xstats, unsigned n);
260 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
261 struct rte_eth_xstat_name *xstats_names,
263 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
264 static int i40e_fw_version_get(struct rte_eth_dev *dev,
265 char *fw_version, size_t fw_size);
266 static int i40e_dev_info_get(struct rte_eth_dev *dev,
267 struct rte_eth_dev_info *dev_info);
268 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
271 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
272 enum rte_vlan_type vlan_type,
274 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
275 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
279 static int i40e_dev_led_on(struct rte_eth_dev *dev);
280 static int i40e_dev_led_off(struct rte_eth_dev *dev);
281 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
282 struct rte_eth_fc_conf *fc_conf);
283 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
284 struct rte_eth_fc_conf *fc_conf);
285 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
286 struct rte_eth_pfc_conf *pfc_conf);
287 static int i40e_macaddr_add(struct rte_eth_dev *dev,
288 struct rte_ether_addr *mac_addr,
291 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
292 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
293 struct rte_eth_rss_reta_entry64 *reta_conf,
295 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
296 struct rte_eth_rss_reta_entry64 *reta_conf,
299 static int i40e_get_cap(struct i40e_hw *hw);
300 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
301 static int i40e_pf_setup(struct i40e_pf *pf);
302 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
303 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
304 static int i40e_dcb_setup(struct rte_eth_dev *dev);
305 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
306 bool offset_loaded, uint64_t *offset, uint64_t *stat);
307 static void i40e_stat_update_48(struct i40e_hw *hw,
313 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
314 static void i40e_dev_interrupt_handler(void *param);
315 static void i40e_dev_alarm_handler(void *param);
316 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
317 uint32_t base, uint32_t num);
318 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
319 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
321 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
323 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
324 static int i40e_veb_release(struct i40e_veb *veb);
325 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
326 struct i40e_vsi *vsi);
327 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
328 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
329 struct i40e_macvlan_filter *mv_f,
332 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
333 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
334 struct rte_eth_rss_conf *rss_conf);
335 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
336 struct rte_eth_rss_conf *rss_conf);
337 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
338 struct rte_eth_udp_tunnel *udp_tunnel);
339 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
340 struct rte_eth_udp_tunnel *udp_tunnel);
341 static void i40e_filter_input_set_init(struct i40e_pf *pf);
342 static int i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
343 const struct rte_flow_ops **ops);
344 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
345 struct rte_eth_dcb_info *dcb_info);
346 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
347 static void i40e_configure_registers(struct i40e_hw *hw);
348 static void i40e_hw_init(struct rte_eth_dev *dev);
349 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
350 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
356 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
357 struct rte_eth_mirror_conf *mirror_conf,
358 uint8_t sw_id, uint8_t on);
359 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
361 static int i40e_timesync_enable(struct rte_eth_dev *dev);
362 static int i40e_timesync_disable(struct rte_eth_dev *dev);
363 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
364 struct timespec *timestamp,
366 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
367 struct timespec *timestamp);
368 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
370 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
372 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
373 struct timespec *timestamp);
374 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
375 const struct timespec *timestamp);
377 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
379 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
382 static int i40e_get_regs(struct rte_eth_dev *dev,
383 struct rte_dev_reg_info *regs);
385 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
387 static int i40e_get_eeprom(struct rte_eth_dev *dev,
388 struct rte_dev_eeprom_info *eeprom);
390 static int i40e_get_module_info(struct rte_eth_dev *dev,
391 struct rte_eth_dev_module_info *modinfo);
392 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
393 struct rte_dev_eeprom_info *info);
395 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
396 struct rte_ether_addr *mac_addr);
398 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
400 static int i40e_ethertype_filter_convert(
401 const struct rte_eth_ethertype_filter *input,
402 struct i40e_ethertype_filter *filter);
403 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
404 struct i40e_ethertype_filter *filter);
406 static int i40e_tunnel_filter_convert(
407 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
408 struct i40e_tunnel_filter *tunnel_filter);
409 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
410 struct i40e_tunnel_filter *tunnel_filter);
411 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
413 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
414 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
415 static void i40e_filter_restore(struct i40e_pf *pf);
416 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
418 static const char *const valid_keys[] = {
419 ETH_I40E_FLOATING_VEB_ARG,
420 ETH_I40E_FLOATING_VEB_LIST_ARG,
421 ETH_I40E_SUPPORT_MULTI_DRIVER,
422 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
426 static const struct rte_pci_id pci_id_i40e_map[] = {
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
452 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
453 { .vendor_id = 0, /* sentinel */ },
456 static const struct eth_dev_ops i40e_eth_dev_ops = {
457 .dev_configure = i40e_dev_configure,
458 .dev_start = i40e_dev_start,
459 .dev_stop = i40e_dev_stop,
460 .dev_close = i40e_dev_close,
461 .dev_reset = i40e_dev_reset,
462 .promiscuous_enable = i40e_dev_promiscuous_enable,
463 .promiscuous_disable = i40e_dev_promiscuous_disable,
464 .allmulticast_enable = i40e_dev_allmulticast_enable,
465 .allmulticast_disable = i40e_dev_allmulticast_disable,
466 .dev_set_link_up = i40e_dev_set_link_up,
467 .dev_set_link_down = i40e_dev_set_link_down,
468 .link_update = i40e_dev_link_update,
469 .stats_get = i40e_dev_stats_get,
470 .xstats_get = i40e_dev_xstats_get,
471 .xstats_get_names = i40e_dev_xstats_get_names,
472 .stats_reset = i40e_dev_stats_reset,
473 .xstats_reset = i40e_dev_stats_reset,
474 .fw_version_get = i40e_fw_version_get,
475 .dev_infos_get = i40e_dev_info_get,
476 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
477 .vlan_filter_set = i40e_vlan_filter_set,
478 .vlan_tpid_set = i40e_vlan_tpid_set,
479 .vlan_offload_set = i40e_vlan_offload_set,
480 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
481 .vlan_pvid_set = i40e_vlan_pvid_set,
482 .rx_queue_start = i40e_dev_rx_queue_start,
483 .rx_queue_stop = i40e_dev_rx_queue_stop,
484 .tx_queue_start = i40e_dev_tx_queue_start,
485 .tx_queue_stop = i40e_dev_tx_queue_stop,
486 .rx_queue_setup = i40e_dev_rx_queue_setup,
487 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
488 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
489 .rx_queue_release = i40e_dev_rx_queue_release,
490 .tx_queue_setup = i40e_dev_tx_queue_setup,
491 .tx_queue_release = i40e_dev_tx_queue_release,
492 .dev_led_on = i40e_dev_led_on,
493 .dev_led_off = i40e_dev_led_off,
494 .flow_ctrl_get = i40e_flow_ctrl_get,
495 .flow_ctrl_set = i40e_flow_ctrl_set,
496 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
497 .mac_addr_add = i40e_macaddr_add,
498 .mac_addr_remove = i40e_macaddr_remove,
499 .reta_update = i40e_dev_rss_reta_update,
500 .reta_query = i40e_dev_rss_reta_query,
501 .rss_hash_update = i40e_dev_rss_hash_update,
502 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
503 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
504 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
505 .flow_ops_get = i40e_dev_flow_ops_get,
506 .rxq_info_get = i40e_rxq_info_get,
507 .txq_info_get = i40e_txq_info_get,
508 .rx_burst_mode_get = i40e_rx_burst_mode_get,
509 .tx_burst_mode_get = i40e_tx_burst_mode_get,
510 .mirror_rule_set = i40e_mirror_rule_set,
511 .mirror_rule_reset = i40e_mirror_rule_reset,
512 .timesync_enable = i40e_timesync_enable,
513 .timesync_disable = i40e_timesync_disable,
514 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
515 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
516 .get_dcb_info = i40e_dev_get_dcb_info,
517 .timesync_adjust_time = i40e_timesync_adjust_time,
518 .timesync_read_time = i40e_timesync_read_time,
519 .timesync_write_time = i40e_timesync_write_time,
520 .get_reg = i40e_get_regs,
521 .get_eeprom_length = i40e_get_eeprom_length,
522 .get_eeprom = i40e_get_eeprom,
523 .get_module_info = i40e_get_module_info,
524 .get_module_eeprom = i40e_get_module_eeprom,
525 .mac_addr_set = i40e_set_default_mac_addr,
526 .mtu_set = i40e_dev_mtu_set,
527 .tm_ops_get = i40e_tm_ops_get,
528 .tx_done_cleanup = i40e_tx_done_cleanup,
529 .get_monitor_addr = i40e_get_monitor_addr,
532 /* store statistics names and its offset in stats structure */
533 struct rte_i40e_xstats_name_off {
534 char name[RTE_ETH_XSTATS_NAME_SIZE];
538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
539 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
540 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
541 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
542 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
543 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
544 rx_unknown_protocol)},
545 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
546 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
547 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
548 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
552 sizeof(rte_i40e_stats_strings[0]))
554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
555 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
556 tx_dropped_link_down)},
557 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
558 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
560 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
561 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
563 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
567 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
568 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
569 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
570 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
571 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
572 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
580 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
582 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
584 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
588 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
589 mac_short_packet_dropped)},
590 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
592 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
593 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
594 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
600 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
602 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
604 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
606 {"rx_flow_director_atr_match_packets",
607 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
608 {"rx_flow_director_sb_match_packets",
609 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
610 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
612 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
614 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
616 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
621 sizeof(rte_i40e_hw_port_strings[0]))
623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
624 {"xon_packets", offsetof(struct i40e_hw_port_stats,
626 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
631 sizeof(rte_i40e_rxq_prio_strings[0]))
633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
634 {"xon_packets", offsetof(struct i40e_hw_port_stats,
636 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
638 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
639 priority_xon_2_xoff)},
642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
643 sizeof(rte_i40e_txq_prio_strings[0]))
646 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
647 struct rte_pci_device *pci_dev)
649 char name[RTE_ETH_NAME_MAX_LEN];
650 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
653 if (pci_dev->device.devargs) {
654 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
660 if (eth_da.nb_representor_ports > 0 &&
661 eth_da.type != RTE_ETH_REPRESENTOR_VF) {
662 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
663 pci_dev->device.devargs->args);
667 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
668 sizeof(struct i40e_adapter),
669 eth_dev_pci_specific_init, pci_dev,
670 eth_i40e_dev_init, NULL);
672 if (retval || eth_da.nb_representor_ports < 1)
675 /* probe VF representor ports */
676 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
677 pci_dev->device.name);
679 if (pf_ethdev == NULL)
682 for (i = 0; i < eth_da.nb_representor_ports; i++) {
683 struct i40e_vf_representor representor = {
684 .vf_id = eth_da.representor_ports[i],
685 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
686 pf_ethdev->data->dev_private)->switch_domain_id,
687 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
688 pf_ethdev->data->dev_private)
691 /* representor port net_bdf_port */
692 snprintf(name, sizeof(name), "net_%s_representor_%d",
693 pci_dev->device.name, eth_da.representor_ports[i]);
695 retval = rte_eth_dev_create(&pci_dev->device, name,
696 sizeof(struct i40e_vf_representor), NULL, NULL,
697 i40e_vf_representor_init, &representor);
700 PMD_DRV_LOG(ERR, "failed to create i40e vf "
701 "representor %s.", name);
707 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
709 struct rte_eth_dev *ethdev;
711 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
715 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
716 return rte_eth_dev_pci_generic_remove(pci_dev,
717 i40e_vf_representor_uninit);
719 return rte_eth_dev_pci_generic_remove(pci_dev,
720 eth_i40e_dev_uninit);
723 static struct rte_pci_driver rte_i40e_pmd = {
724 .id_table = pci_id_i40e_map,
725 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
726 .probe = eth_i40e_pci_probe,
727 .remove = eth_i40e_pci_remove,
731 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
734 uint32_t ori_reg_val;
735 struct rte_eth_dev *dev;
737 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
738 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
739 i40e_write_rx_ctl(hw, reg_addr, reg_val);
740 if (ori_reg_val != reg_val)
742 "i40e device %s changed global register [0x%08x]."
743 " original: 0x%08x, new: 0x%08x",
744 dev->device->name, reg_addr, ori_reg_val, reg_val);
747 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
748 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
749 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
751 #ifndef I40E_GLQF_ORT
752 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
754 #ifndef I40E_GLQF_PIT
755 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
757 #ifndef I40E_GLQF_L3_MAP
758 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
761 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
764 * Initialize registers for parsing packet type of QinQ
765 * This should be removed from code once proper
766 * configuration API is added to avoid configuration conflicts
767 * between ports of the same device.
769 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
770 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
773 static inline void i40e_config_automask(struct i40e_pf *pf)
775 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
778 /* INTENA flag is not auto-cleared for interrupt */
779 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
780 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
781 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
783 /* If support multi-driver, PF will use INT0. */
784 if (!pf->support_multi_driver)
785 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
787 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
790 static inline void i40e_clear_automask(struct i40e_pf *pf)
792 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
795 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
796 val &= ~(I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
797 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK);
799 if (!pf->support_multi_driver)
800 val &= ~I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
802 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
805 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
808 * Add a ethertype filter to drop all flow control frames transmitted
812 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
814 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
815 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
816 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
817 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
820 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
821 I40E_FLOW_CONTROL_ETHERTYPE, flags,
822 pf->main_vsi_seid, 0,
826 "Failed to add filter to drop flow control frames from VSIs.");
830 floating_veb_list_handler(__rte_unused const char *key,
831 const char *floating_veb_value,
835 unsigned int count = 0;
838 bool *vf_floating_veb = opaque;
840 while (isblank(*floating_veb_value))
841 floating_veb_value++;
843 /* Reset floating VEB configuration for VFs */
844 for (idx = 0; idx < I40E_MAX_VF; idx++)
845 vf_floating_veb[idx] = false;
849 while (isblank(*floating_veb_value))
850 floating_veb_value++;
851 if (*floating_veb_value == '\0')
854 idx = strtoul(floating_veb_value, &end, 10);
855 if (errno || end == NULL)
857 while (isblank(*end))
861 } else if ((*end == ';') || (*end == '\0')) {
863 if (min == I40E_MAX_VF)
865 if (max >= I40E_MAX_VF)
866 max = I40E_MAX_VF - 1;
867 for (idx = min; idx <= max; idx++) {
868 vf_floating_veb[idx] = true;
875 floating_veb_value = end + 1;
876 } while (*end != '\0');
885 config_vf_floating_veb(struct rte_devargs *devargs,
886 uint16_t floating_veb,
887 bool *vf_floating_veb)
889 struct rte_kvargs *kvlist;
891 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
895 /* All the VFs attach to the floating VEB by default
896 * when the floating VEB is enabled.
898 for (i = 0; i < I40E_MAX_VF; i++)
899 vf_floating_veb[i] = true;
904 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
908 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
909 rte_kvargs_free(kvlist);
912 /* When the floating_veb_list parameter exists, all the VFs
913 * will attach to the legacy VEB firstly, then configure VFs
914 * to the floating VEB according to the floating_veb_list.
916 if (rte_kvargs_process(kvlist, floating_veb_list,
917 floating_veb_list_handler,
918 vf_floating_veb) < 0) {
919 rte_kvargs_free(kvlist);
922 rte_kvargs_free(kvlist);
926 i40e_check_floating_handler(__rte_unused const char *key,
928 __rte_unused void *opaque)
930 if (strcmp(value, "1"))
937 is_floating_veb_supported(struct rte_devargs *devargs)
939 struct rte_kvargs *kvlist;
940 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
945 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
949 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
950 rte_kvargs_free(kvlist);
953 /* Floating VEB is enabled when there's key-value:
954 * enable_floating_veb=1
956 if (rte_kvargs_process(kvlist, floating_veb_key,
957 i40e_check_floating_handler, NULL) < 0) {
958 rte_kvargs_free(kvlist);
961 rte_kvargs_free(kvlist);
967 config_floating_veb(struct rte_eth_dev *dev)
969 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
970 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
971 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
973 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
975 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
977 is_floating_veb_supported(pci_dev->device.devargs);
978 config_vf_floating_veb(pci_dev->device.devargs,
980 pf->floating_veb_list);
982 pf->floating_veb = false;
986 #define I40E_L2_TAGS_S_TAG_SHIFT 1
987 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
990 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
992 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
993 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
994 char ethertype_hash_name[RTE_HASH_NAMESIZE];
997 struct rte_hash_parameters ethertype_hash_params = {
998 .name = ethertype_hash_name,
999 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
1000 .key_len = sizeof(struct i40e_ethertype_filter_input),
1001 .hash_func = rte_hash_crc,
1002 .hash_func_init_val = 0,
1003 .socket_id = rte_socket_id(),
1006 /* Initialize ethertype filter rule list and hash */
1007 TAILQ_INIT(ðertype_rule->ethertype_list);
1008 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
1009 "ethertype_%s", dev->device->name);
1010 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
1011 if (!ethertype_rule->hash_table) {
1012 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
1015 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
1016 sizeof(struct i40e_ethertype_filter *) *
1017 I40E_MAX_ETHERTYPE_FILTER_NUM,
1019 if (!ethertype_rule->hash_map) {
1021 "Failed to allocate memory for ethertype hash map!");
1023 goto err_ethertype_hash_map_alloc;
1028 err_ethertype_hash_map_alloc:
1029 rte_hash_free(ethertype_rule->hash_table);
1035 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1037 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1038 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1039 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1042 struct rte_hash_parameters tunnel_hash_params = {
1043 .name = tunnel_hash_name,
1044 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1045 .key_len = sizeof(struct i40e_tunnel_filter_input),
1046 .hash_func = rte_hash_crc,
1047 .hash_func_init_val = 0,
1048 .socket_id = rte_socket_id(),
1051 /* Initialize tunnel filter rule list and hash */
1052 TAILQ_INIT(&tunnel_rule->tunnel_list);
1053 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1054 "tunnel_%s", dev->device->name);
1055 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1056 if (!tunnel_rule->hash_table) {
1057 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1060 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1061 sizeof(struct i40e_tunnel_filter *) *
1062 I40E_MAX_TUNNEL_FILTER_NUM,
1064 if (!tunnel_rule->hash_map) {
1066 "Failed to allocate memory for tunnel hash map!");
1068 goto err_tunnel_hash_map_alloc;
1073 err_tunnel_hash_map_alloc:
1074 rte_hash_free(tunnel_rule->hash_table);
1080 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1082 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1083 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1084 struct i40e_fdir_info *fdir_info = &pf->fdir;
1085 char fdir_hash_name[RTE_HASH_NAMESIZE];
1086 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1087 uint32_t best = hw->func_caps.fd_filters_best_effort;
1088 struct rte_bitmap *bmp = NULL;
1094 struct rte_hash_parameters fdir_hash_params = {
1095 .name = fdir_hash_name,
1096 .entries = I40E_MAX_FDIR_FILTER_NUM,
1097 .key_len = sizeof(struct i40e_fdir_input),
1098 .hash_func = rte_hash_crc,
1099 .hash_func_init_val = 0,
1100 .socket_id = rte_socket_id(),
1103 /* Initialize flow director filter rule list and hash */
1104 TAILQ_INIT(&fdir_info->fdir_list);
1105 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1106 "fdir_%s", dev->device->name);
1107 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1108 if (!fdir_info->hash_table) {
1109 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1113 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1114 sizeof(struct i40e_fdir_filter *) *
1115 I40E_MAX_FDIR_FILTER_NUM,
1117 if (!fdir_info->hash_map) {
1119 "Failed to allocate memory for fdir hash map!");
1121 goto err_fdir_hash_map_alloc;
1124 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1125 sizeof(struct i40e_fdir_filter) *
1126 I40E_MAX_FDIR_FILTER_NUM,
1129 if (!fdir_info->fdir_filter_array) {
1131 "Failed to allocate memory for fdir filter array!");
1133 goto err_fdir_filter_array_alloc;
1136 fdir_info->fdir_space_size = alloc + best;
1137 fdir_info->fdir_actual_cnt = 0;
1138 fdir_info->fdir_guarantee_total_space = alloc;
1139 fdir_info->fdir_guarantee_free_space =
1140 fdir_info->fdir_guarantee_total_space;
1142 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1144 fdir_info->fdir_flow_pool.pool =
1145 rte_zmalloc("i40e_fdir_entry",
1146 sizeof(struct i40e_fdir_entry) *
1147 fdir_info->fdir_space_size,
1150 if (!fdir_info->fdir_flow_pool.pool) {
1152 "Failed to allocate memory for bitmap flow!");
1154 goto err_fdir_bitmap_flow_alloc;
1157 for (i = 0; i < fdir_info->fdir_space_size; i++)
1158 fdir_info->fdir_flow_pool.pool[i].idx = i;
1161 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1162 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1165 "Failed to allocate memory for fdir bitmap!");
1167 goto err_fdir_mem_alloc;
1169 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1172 "Failed to initialization fdir bitmap!");
1174 goto err_fdir_bmp_alloc;
1176 for (i = 0; i < fdir_info->fdir_space_size; i++)
1177 rte_bitmap_set(bmp, i);
1179 fdir_info->fdir_flow_pool.bitmap = bmp;
1186 rte_free(fdir_info->fdir_flow_pool.pool);
1187 err_fdir_bitmap_flow_alloc:
1188 rte_free(fdir_info->fdir_filter_array);
1189 err_fdir_filter_array_alloc:
1190 rte_free(fdir_info->hash_map);
1191 err_fdir_hash_map_alloc:
1192 rte_hash_free(fdir_info->hash_table);
1198 i40e_init_customized_info(struct i40e_pf *pf)
1202 /* Initialize customized pctype */
1203 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1204 pf->customized_pctype[i].index = i;
1205 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1206 pf->customized_pctype[i].valid = false;
1209 pf->gtp_support = false;
1210 pf->esp_support = false;
1214 i40e_init_filter_invalidation(struct i40e_pf *pf)
1216 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1217 struct i40e_fdir_info *fdir_info = &pf->fdir;
1218 uint32_t glqf_ctl_reg = 0;
1220 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1221 if (!pf->support_multi_driver) {
1222 fdir_info->fdir_invalprio = 1;
1223 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1224 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1225 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1227 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1228 fdir_info->fdir_invalprio = 1;
1229 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1231 fdir_info->fdir_invalprio = 0;
1232 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1238 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1240 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1241 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1242 struct i40e_queue_regions *info = &pf->queue_region;
1245 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1246 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1248 memset(info, 0, sizeof(struct i40e_queue_regions));
1252 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1257 unsigned long support_multi_driver;
1260 pf = (struct i40e_pf *)opaque;
1263 support_multi_driver = strtoul(value, &end, 10);
1264 if (errno != 0 || end == value || *end != 0) {
1265 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1269 if (support_multi_driver == 1 || support_multi_driver == 0)
1270 pf->support_multi_driver = (bool)support_multi_driver;
1272 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1273 "enable global configuration by default."
1274 ETH_I40E_SUPPORT_MULTI_DRIVER);
1279 i40e_support_multi_driver(struct rte_eth_dev *dev)
1281 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1282 struct rte_kvargs *kvlist;
1285 /* Enable global configuration by default */
1286 pf->support_multi_driver = false;
1288 if (!dev->device->devargs)
1291 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1295 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1296 if (!kvargs_count) {
1297 rte_kvargs_free(kvlist);
1301 if (kvargs_count > 1)
1302 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1303 "the first invalid or last valid one is used !",
1304 ETH_I40E_SUPPORT_MULTI_DRIVER);
1306 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1307 i40e_parse_multi_drv_handler, pf) < 0) {
1308 rte_kvargs_free(kvlist);
1312 rte_kvargs_free(kvlist);
1317 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1318 uint32_t reg_addr, uint64_t reg_val,
1319 struct i40e_asq_cmd_details *cmd_details)
1321 uint64_t ori_reg_val;
1322 struct rte_eth_dev *dev;
1325 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1326 if (ret != I40E_SUCCESS) {
1328 "Fail to debug read from 0x%08x",
1332 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1334 if (ori_reg_val != reg_val)
1335 PMD_DRV_LOG(WARNING,
1336 "i40e device %s changed global register [0x%08x]."
1337 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1338 dev->device->name, reg_addr, ori_reg_val, reg_val);
1340 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1344 read_vf_msg_config(__rte_unused const char *key,
1348 struct i40e_vf_msg_cfg *cfg = opaque;
1350 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1351 &cfg->ignore_second) != 3) {
1352 memset(cfg, 0, sizeof(*cfg));
1353 PMD_DRV_LOG(ERR, "format error! example: "
1354 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1359 * If the message validation function been enabled, the 'period'
1360 * and 'ignore_second' must greater than 0.
1362 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1363 memset(cfg, 0, sizeof(*cfg));
1364 PMD_DRV_LOG(ERR, "%s error! the second and third"
1365 " number must be greater than 0!",
1366 ETH_I40E_VF_MSG_CFG);
1374 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1375 struct i40e_vf_msg_cfg *msg_cfg)
1377 struct rte_kvargs *kvlist;
1381 memset(msg_cfg, 0, sizeof(*msg_cfg));
1383 if (!dev->device->devargs)
1386 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1390 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1394 if (kvargs_count > 1) {
1395 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1396 ETH_I40E_VF_MSG_CFG);
1401 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1402 read_vf_msg_config, msg_cfg) < 0)
1406 rte_kvargs_free(kvlist);
1410 #define I40E_ALARM_INTERVAL 50000 /* us */
1413 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1415 struct rte_pci_device *pci_dev;
1416 struct rte_intr_handle *intr_handle;
1417 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1418 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419 struct i40e_vsi *vsi;
1422 uint8_t aq_fail = 0;
1424 PMD_INIT_FUNC_TRACE();
1426 dev->dev_ops = &i40e_eth_dev_ops;
1427 dev->rx_queue_count = i40e_dev_rx_queue_count;
1428 dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1429 dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1430 dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1431 dev->rx_pkt_burst = i40e_recv_pkts;
1432 dev->tx_pkt_burst = i40e_xmit_pkts;
1433 dev->tx_pkt_prepare = i40e_prep_pkts;
1435 /* for secondary processes, we don't initialise any further as primary
1436 * has already done this work. Only check we don't need a different
1438 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1439 i40e_set_rx_function(dev);
1440 i40e_set_tx_function(dev);
1443 i40e_set_default_ptype_table(dev);
1444 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1445 intr_handle = &pci_dev->intr_handle;
1447 rte_eth_copy_pci_info(dev, pci_dev);
1448 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1450 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1451 pf->adapter->eth_dev = dev;
1452 pf->dev_data = dev->data;
1454 hw->back = I40E_PF_TO_ADAPTER(pf);
1455 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1458 "Hardware is not available, as address is NULL");
1462 hw->vendor_id = pci_dev->id.vendor_id;
1463 hw->device_id = pci_dev->id.device_id;
1464 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1465 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1466 hw->bus.device = pci_dev->addr.devid;
1467 hw->bus.func = pci_dev->addr.function;
1468 hw->adapter_stopped = 0;
1469 hw->adapter_closed = 0;
1471 /* Init switch device pointer */
1472 hw->switch_dev = NULL;
1475 * Switch Tag value should not be identical to either the First Tag
1476 * or Second Tag values. So set something other than common Ethertype
1477 * for internal switching.
1479 hw->switch_tag = 0xffff;
1481 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1482 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1483 PMD_INIT_LOG(ERR, "\nERROR: "
1484 "Firmware recovery mode detected. Limiting functionality.\n"
1485 "Refer to the Intel(R) Ethernet Adapters and Devices "
1486 "User Guide for details on firmware recovery mode.");
1490 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1491 /* Check if need to support multi-driver */
1492 i40e_support_multi_driver(dev);
1494 /* Make sure all is clean before doing PF reset */
1497 /* Reset here to make sure all is clean for each PF */
1498 ret = i40e_pf_reset(hw);
1500 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1504 /* Initialize the shared code (base driver) */
1505 ret = i40e_init_shared_code(hw);
1507 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1511 /* Initialize the parameters for adminq */
1512 i40e_init_adminq_parameter(hw);
1513 ret = i40e_init_adminq(hw);
1514 if (ret != I40E_SUCCESS) {
1515 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1518 /* Firmware of SFP x722 does not support 802.1ad frames ability */
1519 if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
1520 hw->device_id == I40E_DEV_ID_SFP_I_X722)
1521 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1523 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1524 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1525 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1526 ((hw->nvm.version >> 12) & 0xf),
1527 ((hw->nvm.version >> 4) & 0xff),
1528 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1530 /* Initialize the hardware */
1533 i40e_config_automask(pf);
1535 i40e_set_default_pctype_table(dev);
1538 * To work around the NVM issue, initialize registers
1539 * for packet type of QinQ by software.
1540 * It should be removed once issues are fixed in NVM.
1542 if (!pf->support_multi_driver)
1543 i40e_GLQF_reg_init(hw);
1545 /* Initialize the input set for filters (hash and fd) to default value */
1546 i40e_filter_input_set_init(pf);
1548 /* initialise the L3_MAP register */
1549 if (!pf->support_multi_driver) {
1550 ret = i40e_aq_debug_write_global_register(hw,
1551 I40E_GLQF_L3_MAP(40),
1554 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1557 "Global register 0x%08x is changed with 0x28",
1558 I40E_GLQF_L3_MAP(40));
1561 /* Need the special FW version to support floating VEB */
1562 config_floating_veb(dev);
1563 /* Clear PXE mode */
1564 i40e_clear_pxe_mode(hw);
1565 i40e_dev_sync_phy_type(hw);
1568 * On X710, performance number is far from the expectation on recent
1569 * firmware versions. The fix for this issue may not be integrated in
1570 * the following firmware version. So the workaround in software driver
1571 * is needed. It needs to modify the initial values of 3 internal only
1572 * registers. Note that the workaround can be removed when it is fixed
1573 * in firmware in the future.
1575 i40e_configure_registers(hw);
1577 /* Get hw capabilities */
1578 ret = i40e_get_cap(hw);
1579 if (ret != I40E_SUCCESS) {
1580 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1581 goto err_get_capabilities;
1584 /* Initialize parameters for PF */
1585 ret = i40e_pf_parameter_init(dev);
1587 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1588 goto err_parameter_init;
1591 /* Initialize the queue management */
1592 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1594 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1595 goto err_qp_pool_init;
1597 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1598 hw->func_caps.num_msix_vectors - 1);
1600 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1601 goto err_msix_pool_init;
1604 /* Initialize lan hmc */
1605 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1606 hw->func_caps.num_rx_qp, 0, 0);
1607 if (ret != I40E_SUCCESS) {
1608 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1609 goto err_init_lan_hmc;
1612 /* Configure lan hmc */
1613 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1614 if (ret != I40E_SUCCESS) {
1615 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1616 goto err_configure_lan_hmc;
1619 /* Get and check the mac address */
1620 i40e_get_mac_addr(hw, hw->mac.addr);
1621 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1622 PMD_INIT_LOG(ERR, "mac address is not valid");
1624 goto err_get_mac_addr;
1626 /* Copy the permanent MAC address */
1627 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1628 (struct rte_ether_addr *)hw->mac.perm_addr);
1630 /* Disable flow control */
1631 hw->fc.requested_mode = I40E_FC_NONE;
1632 i40e_set_fc(hw, &aq_fail, TRUE);
1634 /* Set the global registers with default ether type value */
1635 if (!pf->support_multi_driver) {
1636 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1637 RTE_ETHER_TYPE_VLAN);
1638 if (ret != I40E_SUCCESS) {
1640 "Failed to set the default outer "
1642 goto err_setup_pf_switch;
1646 /* PF setup, which includes VSI setup */
1647 ret = i40e_pf_setup(pf);
1649 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1650 goto err_setup_pf_switch;
1655 /* Disable double vlan by default */
1656 i40e_vsi_config_double_vlan(vsi, FALSE);
1658 /* Disable S-TAG identification when floating_veb is disabled */
1659 if (!pf->floating_veb) {
1660 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1661 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1662 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1663 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1667 if (!vsi->max_macaddrs)
1668 len = RTE_ETHER_ADDR_LEN;
1670 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1672 /* Should be after VSI initialized */
1673 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1674 if (!dev->data->mac_addrs) {
1676 "Failed to allocated memory for storing mac address");
1679 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1680 &dev->data->mac_addrs[0]);
1682 /* Init dcb to sw mode by default */
1683 ret = i40e_dcb_init_configure(dev, TRUE);
1684 if (ret != I40E_SUCCESS) {
1685 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1686 pf->flags &= ~I40E_FLAG_DCB;
1688 /* Update HW struct after DCB configuration */
1691 /* initialize pf host driver to setup SRIOV resource if applicable */
1692 i40e_pf_host_init(dev);
1694 /* register callback func to eal lib */
1695 rte_intr_callback_register(intr_handle,
1696 i40e_dev_interrupt_handler, dev);
1698 /* configure and enable device interrupt */
1699 i40e_pf_config_irq0(hw, TRUE);
1700 i40e_pf_enable_irq0(hw);
1702 /* enable uio intr after callback register */
1703 rte_intr_enable(intr_handle);
1705 /* By default disable flexible payload in global configuration */
1706 if (!pf->support_multi_driver)
1707 i40e_flex_payload_reg_set_default(hw);
1710 * Add an ethertype filter to drop all flow control frames transmitted
1711 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1714 i40e_add_tx_flow_control_drop_filter(pf);
1716 /* Set the max frame size to 0x2600 by default,
1717 * in case other drivers changed the default value.
1719 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1721 /* initialize mirror rule list */
1722 TAILQ_INIT(&pf->mirror_list);
1724 /* initialize RSS rule list */
1725 TAILQ_INIT(&pf->rss_config_list);
1727 /* initialize Traffic Manager configuration */
1728 i40e_tm_conf_init(dev);
1730 /* Initialize customized information */
1731 i40e_init_customized_info(pf);
1733 /* Initialize the filter invalidation configuration */
1734 i40e_init_filter_invalidation(pf);
1736 ret = i40e_init_ethtype_filter_list(dev);
1738 goto err_init_ethtype_filter_list;
1739 ret = i40e_init_tunnel_filter_list(dev);
1741 goto err_init_tunnel_filter_list;
1742 ret = i40e_init_fdir_filter_list(dev);
1744 goto err_init_fdir_filter_list;
1746 /* initialize queue region configuration */
1747 i40e_init_queue_region_conf(dev);
1749 /* reset all stats of the device, including pf and main vsi */
1750 i40e_dev_stats_reset(dev);
1754 err_init_fdir_filter_list:
1755 rte_free(pf->tunnel.hash_table);
1756 rte_free(pf->tunnel.hash_map);
1757 err_init_tunnel_filter_list:
1758 rte_free(pf->ethertype.hash_table);
1759 rte_free(pf->ethertype.hash_map);
1760 err_init_ethtype_filter_list:
1761 rte_free(dev->data->mac_addrs);
1762 dev->data->mac_addrs = NULL;
1764 i40e_vsi_release(pf->main_vsi);
1765 err_setup_pf_switch:
1767 err_configure_lan_hmc:
1768 (void)i40e_shutdown_lan_hmc(hw);
1770 i40e_res_pool_destroy(&pf->msix_pool);
1772 i40e_res_pool_destroy(&pf->qp_pool);
1775 err_get_capabilities:
1776 (void)i40e_shutdown_adminq(hw);
1782 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1784 struct i40e_ethertype_filter *p_ethertype;
1785 struct i40e_ethertype_rule *ethertype_rule;
1787 ethertype_rule = &pf->ethertype;
1788 /* Remove all ethertype filter rules and hash */
1789 if (ethertype_rule->hash_map)
1790 rte_free(ethertype_rule->hash_map);
1791 if (ethertype_rule->hash_table)
1792 rte_hash_free(ethertype_rule->hash_table);
1794 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1795 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1796 p_ethertype, rules);
1797 rte_free(p_ethertype);
1802 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1804 struct i40e_tunnel_filter *p_tunnel;
1805 struct i40e_tunnel_rule *tunnel_rule;
1807 tunnel_rule = &pf->tunnel;
1808 /* Remove all tunnel director rules and hash */
1809 if (tunnel_rule->hash_map)
1810 rte_free(tunnel_rule->hash_map);
1811 if (tunnel_rule->hash_table)
1812 rte_hash_free(tunnel_rule->hash_table);
1814 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1815 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1821 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1823 struct i40e_fdir_filter *p_fdir;
1824 struct i40e_fdir_info *fdir_info;
1826 fdir_info = &pf->fdir;
1828 /* Remove all flow director rules */
1829 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1830 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1834 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1836 struct i40e_fdir_info *fdir_info;
1838 fdir_info = &pf->fdir;
1840 /* flow director memory cleanup */
1841 if (fdir_info->hash_map)
1842 rte_free(fdir_info->hash_map);
1843 if (fdir_info->hash_table)
1844 rte_hash_free(fdir_info->hash_table);
1845 if (fdir_info->fdir_flow_pool.bitmap)
1846 rte_free(fdir_info->fdir_flow_pool.bitmap);
1847 if (fdir_info->fdir_flow_pool.pool)
1848 rte_free(fdir_info->fdir_flow_pool.pool);
1849 if (fdir_info->fdir_filter_array)
1850 rte_free(fdir_info->fdir_filter_array);
1853 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1856 * Disable by default flexible payload
1857 * for corresponding L2/L3/L4 layers.
1859 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1860 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1861 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1865 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1869 PMD_INIT_FUNC_TRACE();
1871 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1874 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876 if (hw->adapter_closed == 0)
1877 i40e_dev_close(dev);
1883 i40e_dev_configure(struct rte_eth_dev *dev)
1885 struct i40e_adapter *ad =
1886 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1887 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1888 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1889 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1892 ret = i40e_dev_sync_phy_type(hw);
1896 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1897 * bulk allocation or vector Rx preconditions we will reset it.
1899 ad->rx_bulk_alloc_allowed = true;
1900 ad->rx_vec_allowed = true;
1901 ad->tx_simple_allowed = true;
1902 ad->tx_vec_allowed = true;
1904 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1905 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1907 /* Only legacy filter API needs the following fdir config. So when the
1908 * legacy filter API is deprecated, the following codes should also be
1911 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1912 ret = i40e_fdir_setup(pf);
1913 if (ret != I40E_SUCCESS) {
1914 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1917 ret = i40e_fdir_configure(dev);
1919 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1923 i40e_fdir_teardown(pf);
1925 ret = i40e_dev_init_vlan(dev);
1930 * General PMD driver call sequence are NIC init, configure,
1931 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1932 * will try to lookup the VSI that specific queue belongs to if VMDQ
1933 * applicable. So, VMDQ setting has to be done before
1934 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1935 * For RSS setting, it will try to calculate actual configured RX queue
1936 * number, which will be available after rx_queue_setup(). dev_start()
1937 * function is good to place RSS setup.
1939 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1940 ret = i40e_vmdq_setup(dev);
1945 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1946 ret = i40e_dcb_setup(dev);
1948 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1953 TAILQ_INIT(&pf->flow_list);
1958 /* need to release vmdq resource if exists */
1959 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1960 i40e_vsi_release(pf->vmdq[i].vsi);
1961 pf->vmdq[i].vsi = NULL;
1966 /* Need to release fdir resource if exists.
1967 * Only legacy filter API needs the following fdir config. So when the
1968 * legacy filter API is deprecated, the following code should also be
1971 i40e_fdir_teardown(pf);
1976 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1978 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1979 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1980 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1981 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1982 uint16_t msix_vect = vsi->msix_intr;
1985 for (i = 0; i < vsi->nb_qps; i++) {
1986 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1987 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1991 if (vsi->type != I40E_VSI_SRIOV) {
1992 if (!rte_intr_allow_others(intr_handle)) {
1993 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1994 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1996 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1999 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2000 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2002 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2007 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2008 vsi->user_param + (msix_vect - 1);
2010 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2011 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2013 I40E_WRITE_FLUSH(hw);
2017 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2018 int base_queue, int nb_queue,
2023 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2024 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2026 /* Bind all RX queues to allocated MSIX interrupt */
2027 for (i = 0; i < nb_queue; i++) {
2028 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2029 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2030 ((base_queue + i + 1) <<
2031 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2032 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2033 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2035 if (i == nb_queue - 1)
2036 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2037 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2040 /* Write first RX queue to Link list register as the head element */
2041 if (vsi->type != I40E_VSI_SRIOV) {
2043 i40e_calc_itr_interval(1, pf->support_multi_driver);
2045 if (msix_vect == I40E_MISC_VEC_ID) {
2046 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2048 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2050 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2052 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2055 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2057 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2059 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2061 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2068 if (msix_vect == I40E_MISC_VEC_ID) {
2070 I40E_VPINT_LNKLST0(vsi->user_param),
2072 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2074 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2076 /* num_msix_vectors_vf needs to minus irq0 */
2077 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2078 vsi->user_param + (msix_vect - 1);
2080 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2082 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2084 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2088 I40E_WRITE_FLUSH(hw);
2092 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2094 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2095 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2096 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2097 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2098 uint16_t msix_vect = vsi->msix_intr;
2099 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2100 uint16_t queue_idx = 0;
2104 for (i = 0; i < vsi->nb_qps; i++) {
2105 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2106 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2109 /* VF bind interrupt */
2110 if (vsi->type == I40E_VSI_SRIOV) {
2111 if (vsi->nb_msix == 0) {
2112 PMD_DRV_LOG(ERR, "No msix resource");
2115 __vsi_queues_bind_intr(vsi, msix_vect,
2116 vsi->base_queue, vsi->nb_qps,
2121 /* PF & VMDq bind interrupt */
2122 if (rte_intr_dp_is_en(intr_handle)) {
2123 if (vsi->type == I40E_VSI_MAIN) {
2126 } else if (vsi->type == I40E_VSI_VMDQ2) {
2127 struct i40e_vsi *main_vsi =
2128 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2129 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2134 for (i = 0; i < vsi->nb_used_qps; i++) {
2135 if (vsi->nb_msix == 0) {
2136 PMD_DRV_LOG(ERR, "No msix resource");
2138 } else if (nb_msix <= 1) {
2139 if (!rte_intr_allow_others(intr_handle))
2140 /* allow to share MISC_VEC_ID */
2141 msix_vect = I40E_MISC_VEC_ID;
2143 /* no enough msix_vect, map all to one */
2144 __vsi_queues_bind_intr(vsi, msix_vect,
2145 vsi->base_queue + i,
2146 vsi->nb_used_qps - i,
2148 for (; !!record && i < vsi->nb_used_qps; i++)
2149 intr_handle->intr_vec[queue_idx + i] =
2153 /* 1:1 queue/msix_vect mapping */
2154 __vsi_queues_bind_intr(vsi, msix_vect,
2155 vsi->base_queue + i, 1,
2158 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2168 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2170 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2171 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2172 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2173 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2174 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2175 uint16_t msix_intr, i;
2177 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2178 for (i = 0; i < vsi->nb_msix; i++) {
2179 msix_intr = vsi->msix_intr + i;
2180 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2181 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2182 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2183 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2186 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2187 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2188 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2189 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2191 I40E_WRITE_FLUSH(hw);
2195 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2197 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2198 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2199 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2200 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2201 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2202 uint16_t msix_intr, i;
2204 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2205 for (i = 0; i < vsi->nb_msix; i++) {
2206 msix_intr = vsi->msix_intr + i;
2207 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2208 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2211 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2212 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2214 I40E_WRITE_FLUSH(hw);
2217 static inline uint8_t
2218 i40e_parse_link_speeds(uint16_t link_speeds)
2220 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2222 if (link_speeds & ETH_LINK_SPEED_40G)
2223 link_speed |= I40E_LINK_SPEED_40GB;
2224 if (link_speeds & ETH_LINK_SPEED_25G)
2225 link_speed |= I40E_LINK_SPEED_25GB;
2226 if (link_speeds & ETH_LINK_SPEED_20G)
2227 link_speed |= I40E_LINK_SPEED_20GB;
2228 if (link_speeds & ETH_LINK_SPEED_10G)
2229 link_speed |= I40E_LINK_SPEED_10GB;
2230 if (link_speeds & ETH_LINK_SPEED_1G)
2231 link_speed |= I40E_LINK_SPEED_1GB;
2232 if (link_speeds & ETH_LINK_SPEED_100M)
2233 link_speed |= I40E_LINK_SPEED_100MB;
2239 i40e_phy_conf_link(struct i40e_hw *hw,
2241 uint8_t force_speed,
2244 enum i40e_status_code status;
2245 struct i40e_aq_get_phy_abilities_resp phy_ab;
2246 struct i40e_aq_set_phy_config phy_conf;
2247 enum i40e_aq_phy_type cnt;
2248 uint8_t avail_speed;
2249 uint32_t phy_type_mask = 0;
2251 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2252 I40E_AQ_PHY_FLAG_PAUSE_RX |
2253 I40E_AQ_PHY_FLAG_PAUSE_RX |
2254 I40E_AQ_PHY_FLAG_LOW_POWER;
2257 /* To get phy capabilities of available speeds. */
2258 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2261 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2265 avail_speed = phy_ab.link_speed;
2267 /* To get the current phy config. */
2268 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2271 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2276 /* If link needs to go up and it is in autoneg mode the speed is OK,
2277 * no need to set up again.
2279 if (is_up && phy_ab.phy_type != 0 &&
2280 abilities & I40E_AQ_PHY_AN_ENABLED &&
2281 phy_ab.link_speed != 0)
2282 return I40E_SUCCESS;
2284 memset(&phy_conf, 0, sizeof(phy_conf));
2286 /* bits 0-2 use the values from get_phy_abilities_resp */
2288 abilities |= phy_ab.abilities & mask;
2290 phy_conf.abilities = abilities;
2292 /* If link needs to go up, but the force speed is not supported,
2293 * Warn users and config the default available speeds.
2295 if (is_up && !(force_speed & avail_speed)) {
2296 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2297 phy_conf.link_speed = avail_speed;
2299 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2302 /* PHY type mask needs to include each type except PHY type extension */
2303 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2304 phy_type_mask |= 1 << cnt;
2306 /* use get_phy_abilities_resp value for the rest */
2307 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2308 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2309 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2310 I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
2311 I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
2312 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2313 phy_conf.eee_capability = phy_ab.eee_capability;
2314 phy_conf.eeer = phy_ab.eeer_val;
2315 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2317 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2318 phy_ab.abilities, phy_ab.link_speed);
2319 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2320 phy_conf.abilities, phy_conf.link_speed);
2322 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2326 return I40E_SUCCESS;
2330 i40e_apply_link_speed(struct rte_eth_dev *dev)
2333 uint8_t abilities = 0;
2334 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2335 struct rte_eth_conf *conf = &dev->data->dev_conf;
2337 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2338 I40E_AQ_PHY_LINK_ENABLED;
2340 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2341 conf->link_speeds = ETH_LINK_SPEED_40G |
2342 ETH_LINK_SPEED_25G |
2343 ETH_LINK_SPEED_20G |
2344 ETH_LINK_SPEED_10G |
2346 ETH_LINK_SPEED_100M;
2348 abilities |= I40E_AQ_PHY_AN_ENABLED;
2350 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2352 speed = i40e_parse_link_speeds(conf->link_speeds);
2354 return i40e_phy_conf_link(hw, abilities, speed, true);
2358 i40e_dev_start(struct rte_eth_dev *dev)
2360 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2361 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2362 struct i40e_vsi *main_vsi = pf->main_vsi;
2364 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2365 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2366 uint32_t intr_vector = 0;
2367 struct i40e_vsi *vsi;
2368 uint16_t nb_rxq, nb_txq;
2370 hw->adapter_stopped = 0;
2372 rte_intr_disable(intr_handle);
2374 if ((rte_intr_cap_multiple(intr_handle) ||
2375 !RTE_ETH_DEV_SRIOV(dev).active) &&
2376 dev->data->dev_conf.intr_conf.rxq != 0) {
2377 intr_vector = dev->data->nb_rx_queues;
2378 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2383 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2384 intr_handle->intr_vec =
2385 rte_zmalloc("intr_vec",
2386 dev->data->nb_rx_queues * sizeof(int),
2388 if (!intr_handle->intr_vec) {
2390 "Failed to allocate %d rx_queues intr_vec",
2391 dev->data->nb_rx_queues);
2396 /* Initialize VSI */
2397 ret = i40e_dev_rxtx_init(pf);
2398 if (ret != I40E_SUCCESS) {
2399 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2403 /* Map queues with MSIX interrupt */
2404 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2405 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2406 ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2409 i40e_vsi_enable_queues_intr(main_vsi);
2411 /* Map VMDQ VSI queues with MSIX interrupt */
2412 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2413 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2414 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2415 I40E_ITR_INDEX_DEFAULT);
2418 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2421 /* Enable all queues which have been configured */
2422 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2423 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2428 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2429 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2434 /* Enable receiving broadcast packets */
2435 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2436 if (ret != I40E_SUCCESS)
2437 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2439 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2440 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2442 if (ret != I40E_SUCCESS)
2443 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2446 /* Enable the VLAN promiscuous mode. */
2448 for (i = 0; i < pf->vf_num; i++) {
2449 vsi = pf->vfs[i].vsi;
2450 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2455 /* Enable mac loopback mode */
2456 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2457 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2458 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2459 if (ret != I40E_SUCCESS) {
2460 PMD_DRV_LOG(ERR, "fail to set loopback link");
2465 /* Apply link configure */
2466 ret = i40e_apply_link_speed(dev);
2467 if (I40E_SUCCESS != ret) {
2468 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2472 if (!rte_intr_allow_others(intr_handle)) {
2473 rte_intr_callback_unregister(intr_handle,
2474 i40e_dev_interrupt_handler,
2476 /* configure and enable device interrupt */
2477 i40e_pf_config_irq0(hw, FALSE);
2478 i40e_pf_enable_irq0(hw);
2480 if (dev->data->dev_conf.intr_conf.lsc != 0)
2482 "lsc won't enable because of no intr multiplex");
2484 ret = i40e_aq_set_phy_int_mask(hw,
2485 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2486 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2487 I40E_AQ_EVENT_MEDIA_NA), NULL);
2488 if (ret != I40E_SUCCESS)
2489 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2491 /* Call get_link_info aq commond to enable/disable LSE */
2492 i40e_dev_link_update(dev, 0);
2495 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2496 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2497 i40e_dev_alarm_handler, dev);
2499 /* enable uio intr after callback register */
2500 rte_intr_enable(intr_handle);
2503 i40e_filter_restore(pf);
2505 if (pf->tm_conf.root && !pf->tm_conf.committed)
2506 PMD_DRV_LOG(WARNING,
2507 "please call hierarchy_commit() "
2508 "before starting the port");
2510 return I40E_SUCCESS;
2513 for (i = 0; i < nb_txq; i++)
2514 i40e_dev_tx_queue_stop(dev, i);
2516 for (i = 0; i < nb_rxq; i++)
2517 i40e_dev_rx_queue_stop(dev, i);
2523 i40e_dev_stop(struct rte_eth_dev *dev)
2525 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2526 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527 struct i40e_vsi *main_vsi = pf->main_vsi;
2528 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2529 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2532 if (hw->adapter_stopped == 1)
2535 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2536 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2537 rte_intr_enable(intr_handle);
2540 /* Disable all queues */
2541 for (i = 0; i < dev->data->nb_tx_queues; i++)
2542 i40e_dev_tx_queue_stop(dev, i);
2544 for (i = 0; i < dev->data->nb_rx_queues; i++)
2545 i40e_dev_rx_queue_stop(dev, i);
2547 /* un-map queues with interrupt registers */
2548 i40e_vsi_disable_queues_intr(main_vsi);
2549 i40e_vsi_queues_unbind_intr(main_vsi);
2551 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2552 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2553 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2556 /* Clear all queues and release memory */
2557 i40e_dev_clear_queues(dev);
2560 i40e_dev_set_link_down(dev);
2562 if (!rte_intr_allow_others(intr_handle))
2563 /* resume to the default handler */
2564 rte_intr_callback_register(intr_handle,
2565 i40e_dev_interrupt_handler,
2568 /* Clean datapath event and queue/vec mapping */
2569 rte_intr_efd_disable(intr_handle);
2570 if (intr_handle->intr_vec) {
2571 rte_free(intr_handle->intr_vec);
2572 intr_handle->intr_vec = NULL;
2575 /* reset hierarchy commit */
2576 pf->tm_conf.committed = false;
2578 hw->adapter_stopped = 1;
2579 dev->data->dev_started = 0;
2581 pf->adapter->rss_reta_updated = 0;
2587 i40e_dev_close(struct rte_eth_dev *dev)
2589 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2590 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2592 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2593 struct i40e_mirror_rule *p_mirror;
2594 struct i40e_filter_control_settings settings;
2595 struct rte_flow *p_flow;
2599 uint8_t aq_fail = 0;
2602 PMD_INIT_FUNC_TRACE();
2603 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2606 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2608 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2611 ret = i40e_dev_stop(dev);
2613 /* Remove all mirror rules */
2614 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2615 ret = i40e_aq_del_mirror_rule(hw,
2616 pf->main_vsi->veb->seid,
2617 p_mirror->rule_type,
2619 p_mirror->num_entries,
2622 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2623 "status = %d, aq_err = %d.", ret,
2624 hw->aq.asq_last_status);
2626 /* remove mirror software resource anyway */
2627 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2629 pf->nb_mirror_rule--;
2632 i40e_dev_free_queues(dev);
2634 /* Disable interrupt */
2635 i40e_pf_disable_irq0(hw);
2636 rte_intr_disable(intr_handle);
2639 * Only legacy filter API needs the following fdir config. So when the
2640 * legacy filter API is deprecated, the following code should also be
2643 i40e_fdir_teardown(pf);
2645 /* shutdown and destroy the HMC */
2646 i40e_shutdown_lan_hmc(hw);
2648 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2649 i40e_vsi_release(pf->vmdq[i].vsi);
2650 pf->vmdq[i].vsi = NULL;
2655 /* release all the existing VSIs and VEBs */
2656 i40e_vsi_release(pf->main_vsi);
2658 /* shutdown the adminq */
2659 i40e_aq_queue_shutdown(hw, true);
2660 i40e_shutdown_adminq(hw);
2662 i40e_res_pool_destroy(&pf->qp_pool);
2663 i40e_res_pool_destroy(&pf->msix_pool);
2665 /* Disable flexible payload in global configuration */
2666 if (!pf->support_multi_driver)
2667 i40e_flex_payload_reg_set_default(hw);
2669 /* force a PF reset to clean anything leftover */
2670 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2671 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2672 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2673 I40E_WRITE_FLUSH(hw);
2675 /* Clear PXE mode */
2676 i40e_clear_pxe_mode(hw);
2678 /* Unconfigure filter control */
2679 memset(&settings, 0, sizeof(settings));
2680 ret = i40e_set_filter_control(hw, &settings);
2682 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2685 /* Disable flow control */
2686 hw->fc.requested_mode = I40E_FC_NONE;
2687 i40e_set_fc(hw, &aq_fail, TRUE);
2689 /* uninitialize pf host driver */
2690 i40e_pf_host_uninit(dev);
2693 ret = rte_intr_callback_unregister(intr_handle,
2694 i40e_dev_interrupt_handler, dev);
2695 if (ret >= 0 || ret == -ENOENT) {
2697 } else if (ret != -EAGAIN) {
2699 "intr callback unregister failed: %d",
2702 i40e_msec_delay(500);
2703 } while (retries++ < 5);
2705 i40e_rm_ethtype_filter_list(pf);
2706 i40e_rm_tunnel_filter_list(pf);
2707 i40e_rm_fdir_filter_list(pf);
2709 /* Remove all flows */
2710 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2711 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2712 /* Do not free FDIR flows since they are static allocated */
2713 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2717 /* release the fdir static allocated memory */
2718 i40e_fdir_memory_cleanup(pf);
2720 /* Remove all Traffic Manager configuration */
2721 i40e_tm_conf_uninit(dev);
2723 i40e_clear_automask(pf);
2725 hw->adapter_closed = 1;
2730 * Reset PF device only to re-initialize resources in PMD layer
2733 i40e_dev_reset(struct rte_eth_dev *dev)
2737 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2738 * its VF to make them align with it. The detailed notification
2739 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2740 * To avoid unexpected behavior in VF, currently reset of PF with
2741 * SR-IOV activation is not supported. It might be supported later.
2743 if (dev->data->sriov.active)
2746 ret = eth_i40e_dev_uninit(dev);
2750 ret = eth_i40e_dev_init(dev, NULL);
2756 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2758 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2759 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2760 struct i40e_vsi *vsi = pf->main_vsi;
2763 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2765 if (status != I40E_SUCCESS) {
2766 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2770 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2772 if (status != I40E_SUCCESS) {
2773 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2774 /* Rollback unicast promiscuous mode */
2775 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2784 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2786 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2787 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788 struct i40e_vsi *vsi = pf->main_vsi;
2791 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2793 if (status != I40E_SUCCESS) {
2794 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2798 /* must remain in all_multicast mode */
2799 if (dev->data->all_multicast == 1)
2802 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2804 if (status != I40E_SUCCESS) {
2805 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2806 /* Rollback unicast promiscuous mode */
2807 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2816 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2818 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2819 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820 struct i40e_vsi *vsi = pf->main_vsi;
2823 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2824 if (ret != I40E_SUCCESS) {
2825 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2833 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2835 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2836 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837 struct i40e_vsi *vsi = pf->main_vsi;
2840 if (dev->data->promiscuous == 1)
2841 return 0; /* must remain in all_multicast mode */
2843 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2844 vsi->seid, FALSE, NULL);
2845 if (ret != I40E_SUCCESS) {
2846 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2854 * Set device link up.
2857 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2859 /* re-apply link speed setting */
2860 return i40e_apply_link_speed(dev);
2864 * Set device link down.
2867 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2869 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2870 uint8_t abilities = 0;
2871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2874 return i40e_phy_conf_link(hw, abilities, speed, false);
2877 static __rte_always_inline void
2878 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2880 /* Link status registers and values*/
2881 #define I40E_PRTMAC_LINKSTA 0x001E2420
2882 #define I40E_REG_LINK_UP 0x40000080
2883 #define I40E_PRTMAC_MACC 0x001E24E0
2884 #define I40E_REG_MACC_25GB 0x00020000
2885 #define I40E_REG_SPEED_MASK 0x38000000
2886 #define I40E_REG_SPEED_0 0x00000000
2887 #define I40E_REG_SPEED_1 0x08000000
2888 #define I40E_REG_SPEED_2 0x10000000
2889 #define I40E_REG_SPEED_3 0x18000000
2890 #define I40E_REG_SPEED_4 0x20000000
2891 uint32_t link_speed;
2894 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2895 link_speed = reg_val & I40E_REG_SPEED_MASK;
2896 reg_val &= I40E_REG_LINK_UP;
2897 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2899 if (unlikely(link->link_status == 0))
2902 /* Parse the link status */
2903 switch (link_speed) {
2904 case I40E_REG_SPEED_0:
2905 link->link_speed = ETH_SPEED_NUM_100M;
2907 case I40E_REG_SPEED_1:
2908 link->link_speed = ETH_SPEED_NUM_1G;
2910 case I40E_REG_SPEED_2:
2911 if (hw->mac.type == I40E_MAC_X722)
2912 link->link_speed = ETH_SPEED_NUM_2_5G;
2914 link->link_speed = ETH_SPEED_NUM_10G;
2916 case I40E_REG_SPEED_3:
2917 if (hw->mac.type == I40E_MAC_X722) {
2918 link->link_speed = ETH_SPEED_NUM_5G;
2920 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2922 if (reg_val & I40E_REG_MACC_25GB)
2923 link->link_speed = ETH_SPEED_NUM_25G;
2925 link->link_speed = ETH_SPEED_NUM_40G;
2928 case I40E_REG_SPEED_4:
2929 if (hw->mac.type == I40E_MAC_X722)
2930 link->link_speed = ETH_SPEED_NUM_10G;
2932 link->link_speed = ETH_SPEED_NUM_20G;
2935 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2940 static __rte_always_inline void
2941 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2942 bool enable_lse, int wait_to_complete)
2944 #define CHECK_INTERVAL 100 /* 100ms */
2945 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2946 uint32_t rep_cnt = MAX_REPEAT_TIME;
2947 struct i40e_link_status link_status;
2950 memset(&link_status, 0, sizeof(link_status));
2953 memset(&link_status, 0, sizeof(link_status));
2955 /* Get link status information from hardware */
2956 status = i40e_aq_get_link_info(hw, enable_lse,
2957 &link_status, NULL);
2958 if (unlikely(status != I40E_SUCCESS)) {
2959 link->link_speed = ETH_SPEED_NUM_NONE;
2960 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2961 PMD_DRV_LOG(ERR, "Failed to get link info");
2965 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2966 if (!wait_to_complete || link->link_status)
2969 rte_delay_ms(CHECK_INTERVAL);
2970 } while (--rep_cnt);
2972 /* Parse the link status */
2973 switch (link_status.link_speed) {
2974 case I40E_LINK_SPEED_100MB:
2975 link->link_speed = ETH_SPEED_NUM_100M;
2977 case I40E_LINK_SPEED_1GB:
2978 link->link_speed = ETH_SPEED_NUM_1G;
2980 case I40E_LINK_SPEED_10GB:
2981 link->link_speed = ETH_SPEED_NUM_10G;
2983 case I40E_LINK_SPEED_20GB:
2984 link->link_speed = ETH_SPEED_NUM_20G;
2986 case I40E_LINK_SPEED_25GB:
2987 link->link_speed = ETH_SPEED_NUM_25G;
2989 case I40E_LINK_SPEED_40GB:
2990 link->link_speed = ETH_SPEED_NUM_40G;
2993 if (link->link_status)
2994 link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2996 link->link_speed = ETH_SPEED_NUM_NONE;
3002 i40e_dev_link_update(struct rte_eth_dev *dev,
3003 int wait_to_complete)
3005 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3006 struct rte_eth_link link;
3007 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3010 memset(&link, 0, sizeof(link));
3012 /* i40e uses full duplex only */
3013 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3014 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3015 ETH_LINK_SPEED_FIXED);
3017 if (!wait_to_complete && !enable_lse)
3018 update_link_reg(hw, &link);
3020 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3023 rte_eth_linkstatus_get(hw->switch_dev, &link);
3025 ret = rte_eth_linkstatus_set(dev, &link);
3026 i40e_notify_all_vfs_link_status(dev);
3032 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3033 uint32_t loreg, bool offset_loaded, uint64_t *offset,
3034 uint64_t *stat, uint64_t *prev_stat)
3036 i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3037 /* enlarge the limitation when statistics counters overflowed */
3038 if (offset_loaded) {
3039 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3040 *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3041 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3046 /* Get all the statistics of a VSI */
3048 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3050 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3051 struct i40e_eth_stats *nes = &vsi->eth_stats;
3052 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3053 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3055 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3056 vsi->offset_loaded, &oes->rx_bytes,
3057 &nes->rx_bytes, &vsi->prev_rx_bytes);
3058 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3059 vsi->offset_loaded, &oes->rx_unicast,
3061 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3062 vsi->offset_loaded, &oes->rx_multicast,
3063 &nes->rx_multicast);
3064 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3065 vsi->offset_loaded, &oes->rx_broadcast,
3066 &nes->rx_broadcast);
3067 /* exclude CRC bytes */
3068 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3069 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3071 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3072 &oes->rx_discards, &nes->rx_discards);
3073 /* GLV_REPC not supported */
3074 /* GLV_RMPC not supported */
3075 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3076 &oes->rx_unknown_protocol,
3077 &nes->rx_unknown_protocol);
3078 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3079 vsi->offset_loaded, &oes->tx_bytes,
3080 &nes->tx_bytes, &vsi->prev_tx_bytes);
3081 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3082 vsi->offset_loaded, &oes->tx_unicast,
3084 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3085 vsi->offset_loaded, &oes->tx_multicast,
3086 &nes->tx_multicast);
3087 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3088 vsi->offset_loaded, &oes->tx_broadcast,
3089 &nes->tx_broadcast);
3090 /* GLV_TDPC not supported */
3091 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3092 &oes->tx_errors, &nes->tx_errors);
3093 vsi->offset_loaded = true;
3095 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3097 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3098 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3099 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3100 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3101 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3102 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3103 nes->rx_unknown_protocol);
3104 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3105 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3106 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3107 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3108 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3109 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3110 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3115 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3118 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3119 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3121 /* Get rx/tx bytes of internal transfer packets */
3122 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3123 I40E_GLV_GORCL(hw->port),
3125 &pf->internal_stats_offset.rx_bytes,
3126 &pf->internal_stats.rx_bytes,
3127 &pf->internal_prev_rx_bytes);
3128 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3129 I40E_GLV_GOTCL(hw->port),
3131 &pf->internal_stats_offset.tx_bytes,
3132 &pf->internal_stats.tx_bytes,
3133 &pf->internal_prev_tx_bytes);
3134 /* Get total internal rx packet count */
3135 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3136 I40E_GLV_UPRCL(hw->port),
3138 &pf->internal_stats_offset.rx_unicast,
3139 &pf->internal_stats.rx_unicast);
3140 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3141 I40E_GLV_MPRCL(hw->port),
3143 &pf->internal_stats_offset.rx_multicast,
3144 &pf->internal_stats.rx_multicast);
3145 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3146 I40E_GLV_BPRCL(hw->port),
3148 &pf->internal_stats_offset.rx_broadcast,
3149 &pf->internal_stats.rx_broadcast);
3150 /* Get total internal tx packet count */
3151 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3152 I40E_GLV_UPTCL(hw->port),
3154 &pf->internal_stats_offset.tx_unicast,
3155 &pf->internal_stats.tx_unicast);
3156 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3157 I40E_GLV_MPTCL(hw->port),
3159 &pf->internal_stats_offset.tx_multicast,
3160 &pf->internal_stats.tx_multicast);
3161 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3162 I40E_GLV_BPTCL(hw->port),
3164 &pf->internal_stats_offset.tx_broadcast,
3165 &pf->internal_stats.tx_broadcast);
3167 /* exclude CRC size */
3168 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3169 pf->internal_stats.rx_multicast +
3170 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3172 /* Get statistics of struct i40e_eth_stats */
3173 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3174 I40E_GLPRT_GORCL(hw->port),
3175 pf->offset_loaded, &os->eth.rx_bytes,
3176 &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3177 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3178 I40E_GLPRT_UPRCL(hw->port),
3179 pf->offset_loaded, &os->eth.rx_unicast,
3180 &ns->eth.rx_unicast);
3181 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3182 I40E_GLPRT_MPRCL(hw->port),
3183 pf->offset_loaded, &os->eth.rx_multicast,
3184 &ns->eth.rx_multicast);
3185 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3186 I40E_GLPRT_BPRCL(hw->port),
3187 pf->offset_loaded, &os->eth.rx_broadcast,
3188 &ns->eth.rx_broadcast);
3189 /* Workaround: CRC size should not be included in byte statistics,
3190 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3193 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3194 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3196 /* exclude internal rx bytes
3197 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3198 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3200 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3202 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3203 ns->eth.rx_bytes = 0;
3205 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3207 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3208 ns->eth.rx_unicast = 0;
3210 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3212 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3213 ns->eth.rx_multicast = 0;
3215 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3217 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3218 ns->eth.rx_broadcast = 0;
3220 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3222 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3223 pf->offset_loaded, &os->eth.rx_discards,
3224 &ns->eth.rx_discards);
3225 /* GLPRT_REPC not supported */
3226 /* GLPRT_RMPC not supported */
3227 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3229 &os->eth.rx_unknown_protocol,
3230 &ns->eth.rx_unknown_protocol);
3231 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3232 I40E_GLPRT_GOTCL(hw->port),
3233 pf->offset_loaded, &os->eth.tx_bytes,
3234 &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3235 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3236 I40E_GLPRT_UPTCL(hw->port),
3237 pf->offset_loaded, &os->eth.tx_unicast,
3238 &ns->eth.tx_unicast);
3239 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3240 I40E_GLPRT_MPTCL(hw->port),
3241 pf->offset_loaded, &os->eth.tx_multicast,
3242 &ns->eth.tx_multicast);
3243 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3244 I40E_GLPRT_BPTCL(hw->port),
3245 pf->offset_loaded, &os->eth.tx_broadcast,
3246 &ns->eth.tx_broadcast);
3247 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3248 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3250 /* exclude internal tx bytes
3251 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3252 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3254 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3256 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3257 ns->eth.tx_bytes = 0;
3259 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3261 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3262 ns->eth.tx_unicast = 0;
3264 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3266 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3267 ns->eth.tx_multicast = 0;
3269 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3271 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3272 ns->eth.tx_broadcast = 0;
3274 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3276 /* GLPRT_TEPC not supported */
3278 /* additional port specific stats */
3279 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3280 pf->offset_loaded, &os->tx_dropped_link_down,
3281 &ns->tx_dropped_link_down);
3282 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3283 pf->offset_loaded, &os->crc_errors,
3285 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3286 pf->offset_loaded, &os->illegal_bytes,
3287 &ns->illegal_bytes);
3288 /* GLPRT_ERRBC not supported */
3289 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3290 pf->offset_loaded, &os->mac_local_faults,
3291 &ns->mac_local_faults);
3292 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3293 pf->offset_loaded, &os->mac_remote_faults,
3294 &ns->mac_remote_faults);
3295 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3296 pf->offset_loaded, &os->rx_length_errors,
3297 &ns->rx_length_errors);
3298 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3299 pf->offset_loaded, &os->link_xon_rx,
3301 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3302 pf->offset_loaded, &os->link_xoff_rx,
3304 for (i = 0; i < 8; i++) {
3305 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3307 &os->priority_xon_rx[i],
3308 &ns->priority_xon_rx[i]);
3309 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3311 &os->priority_xoff_rx[i],
3312 &ns->priority_xoff_rx[i]);
3314 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3315 pf->offset_loaded, &os->link_xon_tx,
3317 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3318 pf->offset_loaded, &os->link_xoff_tx,
3320 for (i = 0; i < 8; i++) {
3321 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3323 &os->priority_xon_tx[i],
3324 &ns->priority_xon_tx[i]);
3325 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3327 &os->priority_xoff_tx[i],
3328 &ns->priority_xoff_tx[i]);
3329 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3331 &os->priority_xon_2_xoff[i],
3332 &ns->priority_xon_2_xoff[i]);
3334 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3335 I40E_GLPRT_PRC64L(hw->port),
3336 pf->offset_loaded, &os->rx_size_64,
3338 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3339 I40E_GLPRT_PRC127L(hw->port),
3340 pf->offset_loaded, &os->rx_size_127,
3342 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3343 I40E_GLPRT_PRC255L(hw->port),
3344 pf->offset_loaded, &os->rx_size_255,
3346 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3347 I40E_GLPRT_PRC511L(hw->port),
3348 pf->offset_loaded, &os->rx_size_511,
3350 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3351 I40E_GLPRT_PRC1023L(hw->port),
3352 pf->offset_loaded, &os->rx_size_1023,
3354 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3355 I40E_GLPRT_PRC1522L(hw->port),
3356 pf->offset_loaded, &os->rx_size_1522,
3358 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3359 I40E_GLPRT_PRC9522L(hw->port),
3360 pf->offset_loaded, &os->rx_size_big,
3362 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3363 pf->offset_loaded, &os->rx_undersize,
3365 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3366 pf->offset_loaded, &os->rx_fragments,
3368 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3369 pf->offset_loaded, &os->rx_oversize,
3371 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3372 pf->offset_loaded, &os->rx_jabber,
3374 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3375 I40E_GLPRT_PTC64L(hw->port),
3376 pf->offset_loaded, &os->tx_size_64,
3378 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3379 I40E_GLPRT_PTC127L(hw->port),
3380 pf->offset_loaded, &os->tx_size_127,
3382 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3383 I40E_GLPRT_PTC255L(hw->port),
3384 pf->offset_loaded, &os->tx_size_255,
3386 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3387 I40E_GLPRT_PTC511L(hw->port),
3388 pf->offset_loaded, &os->tx_size_511,
3390 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3391 I40E_GLPRT_PTC1023L(hw->port),
3392 pf->offset_loaded, &os->tx_size_1023,
3394 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3395 I40E_GLPRT_PTC1522L(hw->port),
3396 pf->offset_loaded, &os->tx_size_1522,
3398 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3399 I40E_GLPRT_PTC9522L(hw->port),
3400 pf->offset_loaded, &os->tx_size_big,
3402 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3404 &os->fd_sb_match, &ns->fd_sb_match);
3405 /* GLPRT_MSPDC not supported */
3406 /* GLPRT_XEC not supported */
3408 pf->offset_loaded = true;
3411 i40e_update_vsi_stats(pf->main_vsi);
3414 /* Get all statistics of a port */
3416 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3418 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3419 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3420 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3421 struct i40e_vsi *vsi;
3424 /* call read registers - updates values, now write them to struct */
3425 i40e_read_stats_registers(pf, hw);
3427 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3428 pf->main_vsi->eth_stats.rx_multicast +
3429 pf->main_vsi->eth_stats.rx_broadcast -
3430 pf->main_vsi->eth_stats.rx_discards;
3431 stats->opackets = ns->eth.tx_unicast +
3432 ns->eth.tx_multicast +
3433 ns->eth.tx_broadcast;
3434 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3435 stats->obytes = ns->eth.tx_bytes;
3436 stats->oerrors = ns->eth.tx_errors +
3437 pf->main_vsi->eth_stats.tx_errors;
3440 stats->imissed = ns->eth.rx_discards +
3441 pf->main_vsi->eth_stats.rx_discards;
3442 stats->ierrors = ns->crc_errors +
3443 ns->rx_length_errors + ns->rx_undersize +
3444 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3447 for (i = 0; i < pf->vf_num; i++) {
3448 vsi = pf->vfs[i].vsi;
3449 i40e_update_vsi_stats(vsi);
3451 stats->ipackets += (vsi->eth_stats.rx_unicast +
3452 vsi->eth_stats.rx_multicast +
3453 vsi->eth_stats.rx_broadcast -
3454 vsi->eth_stats.rx_discards);
3455 stats->ibytes += vsi->eth_stats.rx_bytes;
3456 stats->oerrors += vsi->eth_stats.tx_errors;
3457 stats->imissed += vsi->eth_stats.rx_discards;
3461 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3462 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3463 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3464 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3465 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3466 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3467 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3468 ns->eth.rx_unknown_protocol);
3469 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3470 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3471 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3472 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3473 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3474 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3476 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3477 ns->tx_dropped_link_down);
3478 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3479 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3481 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3482 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3483 ns->mac_local_faults);
3484 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3485 ns->mac_remote_faults);
3486 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3487 ns->rx_length_errors);
3488 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3489 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3490 for (i = 0; i < 8; i++) {
3491 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3492 i, ns->priority_xon_rx[i]);
3493 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3494 i, ns->priority_xoff_rx[i]);
3496 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3497 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3498 for (i = 0; i < 8; i++) {
3499 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3500 i, ns->priority_xon_tx[i]);
3501 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3502 i, ns->priority_xoff_tx[i]);
3503 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3504 i, ns->priority_xon_2_xoff[i]);
3506 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3507 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3508 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3509 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3510 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3511 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3512 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3513 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3514 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3515 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3516 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3517 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3518 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3519 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3520 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3521 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3522 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3523 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3524 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3525 ns->mac_short_packet_dropped);
3526 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3527 ns->checksum_error);
3528 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3529 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3533 /* Reset the statistics */
3535 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3537 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3538 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3540 /* Mark PF and VSI stats to update the offset, aka "reset" */
3541 pf->offset_loaded = false;
3543 pf->main_vsi->offset_loaded = false;
3545 /* read the stats, reading current register values into offset */
3546 i40e_read_stats_registers(pf, hw);
3552 i40e_xstats_calc_num(void)
3554 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3555 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3556 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3559 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3560 struct rte_eth_xstat_name *xstats_names,
3561 __rte_unused unsigned limit)
3566 if (xstats_names == NULL)
3567 return i40e_xstats_calc_num();
3569 /* Note: limit checked in rte_eth_xstats_names() */
3571 /* Get stats from i40e_eth_stats struct */
3572 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3573 strlcpy(xstats_names[count].name,
3574 rte_i40e_stats_strings[i].name,
3575 sizeof(xstats_names[count].name));
3579 /* Get individiual stats from i40e_hw_port struct */
3580 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3581 strlcpy(xstats_names[count].name,
3582 rte_i40e_hw_port_strings[i].name,
3583 sizeof(xstats_names[count].name));
3587 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3588 for (prio = 0; prio < 8; prio++) {
3589 snprintf(xstats_names[count].name,
3590 sizeof(xstats_names[count].name),
3591 "rx_priority%u_%s", prio,
3592 rte_i40e_rxq_prio_strings[i].name);
3597 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3598 for (prio = 0; prio < 8; prio++) {
3599 snprintf(xstats_names[count].name,
3600 sizeof(xstats_names[count].name),
3601 "tx_priority%u_%s", prio,
3602 rte_i40e_txq_prio_strings[i].name);
3610 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615 unsigned i, count, prio;
3616 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3618 count = i40e_xstats_calc_num();
3622 i40e_read_stats_registers(pf, hw);
3629 /* Get stats from i40e_eth_stats struct */
3630 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3631 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3632 rte_i40e_stats_strings[i].offset);
3633 xstats[count].id = count;
3637 /* Get individiual stats from i40e_hw_port struct */
3638 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3639 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3640 rte_i40e_hw_port_strings[i].offset);
3641 xstats[count].id = count;
3645 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3646 for (prio = 0; prio < 8; prio++) {
3647 xstats[count].value =
3648 *(uint64_t *)(((char *)hw_stats) +
3649 rte_i40e_rxq_prio_strings[i].offset +
3650 (sizeof(uint64_t) * prio));
3651 xstats[count].id = count;
3656 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3657 for (prio = 0; prio < 8; prio++) {
3658 xstats[count].value =
3659 *(uint64_t *)(((char *)hw_stats) +
3660 rte_i40e_txq_prio_strings[i].offset +
3661 (sizeof(uint64_t) * prio));
3662 xstats[count].id = count;
3671 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3673 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679 full_ver = hw->nvm.oem_ver;
3680 ver = (u8)(full_ver >> 24);
3681 build = (u16)((full_ver >> 8) & 0xffff);
3682 patch = (u8)(full_ver & 0xff);
3684 ret = snprintf(fw_version, fw_size,
3685 "%d.%d%d 0x%08x %d.%d.%d",
3686 ((hw->nvm.version >> 12) & 0xf),
3687 ((hw->nvm.version >> 4) & 0xff),
3688 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3693 ret += 1; /* add the size of '\0' */
3694 if (fw_size < (size_t)ret)
3701 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3702 * the Rx data path does not hang if the FW LLDP is stopped.
3703 * return true if lldp need to stop
3704 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3707 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3710 char ver_str[64] = {0};
3711 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3713 i40e_fw_version_get(dev, ver_str, 64);
3714 nvm_ver = atof(ver_str);
3715 if ((hw->mac.type == I40E_MAC_X722 ||
3716 hw->mac.type == I40E_MAC_X722_VF) &&
3717 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3719 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3726 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3728 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3729 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3730 struct i40e_vsi *vsi = pf->main_vsi;
3731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3733 dev_info->max_rx_queues = vsi->nb_qps;
3734 dev_info->max_tx_queues = vsi->nb_qps;
3735 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3736 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3737 dev_info->max_mac_addrs = vsi->max_macaddrs;
3738 dev_info->max_vfs = pci_dev->max_vfs;
3739 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3740 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3741 dev_info->rx_queue_offload_capa = 0;
3742 dev_info->rx_offload_capa =
3743 DEV_RX_OFFLOAD_VLAN_STRIP |
3744 DEV_RX_OFFLOAD_QINQ_STRIP |
3745 DEV_RX_OFFLOAD_IPV4_CKSUM |
3746 DEV_RX_OFFLOAD_UDP_CKSUM |
3747 DEV_RX_OFFLOAD_TCP_CKSUM |
3748 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3749 DEV_RX_OFFLOAD_KEEP_CRC |
3750 DEV_RX_OFFLOAD_SCATTER |
3751 DEV_RX_OFFLOAD_VLAN_EXTEND |
3752 DEV_RX_OFFLOAD_VLAN_FILTER |
3753 DEV_RX_OFFLOAD_JUMBO_FRAME |
3754 DEV_RX_OFFLOAD_RSS_HASH;
3756 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3757 dev_info->tx_offload_capa =
3758 DEV_TX_OFFLOAD_VLAN_INSERT |
3759 DEV_TX_OFFLOAD_QINQ_INSERT |
3760 DEV_TX_OFFLOAD_IPV4_CKSUM |
3761 DEV_TX_OFFLOAD_UDP_CKSUM |
3762 DEV_TX_OFFLOAD_TCP_CKSUM |
3763 DEV_TX_OFFLOAD_SCTP_CKSUM |
3764 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3765 DEV_TX_OFFLOAD_TCP_TSO |
3766 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3767 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3768 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3769 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3770 DEV_TX_OFFLOAD_MULTI_SEGS |
3771 dev_info->tx_queue_offload_capa;
3772 dev_info->dev_capa =
3773 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3774 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3776 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3778 dev_info->reta_size = pf->hash_lut_size;
3779 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3781 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3783 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3784 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3785 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3787 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3792 dev_info->default_txconf = (struct rte_eth_txconf) {
3794 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3795 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3796 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3798 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3799 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3803 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3804 .nb_max = I40E_MAX_RING_DESC,
3805 .nb_min = I40E_MIN_RING_DESC,
3806 .nb_align = I40E_ALIGN_RING_DESC,
3809 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3810 .nb_max = I40E_MAX_RING_DESC,
3811 .nb_min = I40E_MIN_RING_DESC,
3812 .nb_align = I40E_ALIGN_RING_DESC,
3813 .nb_seg_max = I40E_TX_MAX_SEG,
3814 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3817 if (pf->flags & I40E_FLAG_VMDQ) {
3818 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3819 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3820 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3821 pf->max_nb_vmdq_vsi;
3822 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3823 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3824 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3827 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3829 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3830 dev_info->default_rxportconf.nb_queues = 2;
3831 dev_info->default_txportconf.nb_queues = 2;
3832 if (dev->data->nb_rx_queues == 1)
3833 dev_info->default_rxportconf.ring_size = 2048;
3835 dev_info->default_rxportconf.ring_size = 1024;
3836 if (dev->data->nb_tx_queues == 1)
3837 dev_info->default_txportconf.ring_size = 1024;
3839 dev_info->default_txportconf.ring_size = 512;
3841 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3843 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3844 dev_info->default_rxportconf.nb_queues = 1;
3845 dev_info->default_txportconf.nb_queues = 1;
3846 dev_info->default_rxportconf.ring_size = 256;
3847 dev_info->default_txportconf.ring_size = 256;
3850 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3851 dev_info->default_rxportconf.nb_queues = 1;
3852 dev_info->default_txportconf.nb_queues = 1;
3853 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3854 dev_info->default_rxportconf.ring_size = 512;
3855 dev_info->default_txportconf.ring_size = 256;
3857 dev_info->default_rxportconf.ring_size = 256;
3858 dev_info->default_txportconf.ring_size = 256;
3861 dev_info->default_rxportconf.burst_size = 32;
3862 dev_info->default_txportconf.burst_size = 32;
3868 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3870 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3871 struct i40e_vsi *vsi = pf->main_vsi;
3872 PMD_INIT_FUNC_TRACE();
3875 return i40e_vsi_add_vlan(vsi, vlan_id);
3877 return i40e_vsi_delete_vlan(vsi, vlan_id);
3881 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3882 enum rte_vlan_type vlan_type,
3883 uint16_t tpid, int qinq)
3885 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888 uint16_t reg_id = 3;
3892 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3896 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3898 if (ret != I40E_SUCCESS) {
3900 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3905 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3908 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3909 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3910 if (reg_r == reg_w) {
3911 PMD_DRV_LOG(DEBUG, "No need to write");
3915 ret = i40e_aq_debug_write_global_register(hw,
3916 I40E_GL_SWT_L2TAGCTRL(reg_id),
3918 if (ret != I40E_SUCCESS) {
3920 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3925 "Global register 0x%08x is changed with value 0x%08x",
3926 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3932 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3933 enum rte_vlan_type vlan_type,
3936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3938 int qinq = dev->data->dev_conf.rxmode.offloads &
3939 DEV_RX_OFFLOAD_VLAN_EXTEND;
3942 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3943 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3944 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3946 "Unsupported vlan type.");
3950 if (pf->support_multi_driver) {
3951 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3955 /* 802.1ad frames ability is added in NVM API 1.7*/
3956 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3958 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3959 hw->first_tag = rte_cpu_to_le_16(tpid);
3960 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3961 hw->second_tag = rte_cpu_to_le_16(tpid);
3963 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3964 hw->second_tag = rte_cpu_to_le_16(tpid);
3966 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3967 if (ret != I40E_SUCCESS) {
3969 "Set switch config failed aq_err: %d",
3970 hw->aq.asq_last_status);
3974 /* If NVM API < 1.7, keep the register setting */
3975 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3981 /* Configure outer vlan stripping on or off in QinQ mode */
3983 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3985 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3986 int ret = I40E_SUCCESS;
3989 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3990 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
3994 /* Configure for outer VLAN RX stripping */
3995 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
3998 reg |= I40E_VSI_TSR_QINQ_STRIP;
4000 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4002 ret = i40e_aq_debug_write_register(hw,
4003 I40E_VSI_TSR(vsi->vsi_id),
4006 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4008 return I40E_ERR_CONFIG;
4015 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4017 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4018 struct i40e_vsi *vsi = pf->main_vsi;
4019 struct rte_eth_rxmode *rxmode;
4021 rxmode = &dev->data->dev_conf.rxmode;
4022 if (mask & ETH_VLAN_FILTER_MASK) {
4023 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4024 i40e_vsi_config_vlan_filter(vsi, TRUE);
4026 i40e_vsi_config_vlan_filter(vsi, FALSE);
4029 if (mask & ETH_VLAN_STRIP_MASK) {
4030 /* Enable or disable VLAN stripping */
4031 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4032 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4034 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4037 if (mask & ETH_VLAN_EXTEND_MASK) {
4038 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4039 i40e_vsi_config_double_vlan(vsi, TRUE);
4040 /* Set global registers with default ethertype. */
4041 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4042 RTE_ETHER_TYPE_VLAN);
4043 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4044 RTE_ETHER_TYPE_VLAN);
4047 i40e_vsi_config_double_vlan(vsi, FALSE);
4050 if (mask & ETH_QINQ_STRIP_MASK) {
4051 /* Enable or disable outer VLAN stripping */
4052 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4053 i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4055 i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4062 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4063 __rte_unused uint16_t queue,
4064 __rte_unused int on)
4066 PMD_INIT_FUNC_TRACE();
4070 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4072 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4073 struct i40e_vsi *vsi = pf->main_vsi;
4074 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4075 struct i40e_vsi_vlan_pvid_info info;
4077 memset(&info, 0, sizeof(info));
4080 info.config.pvid = pvid;
4082 info.config.reject.tagged =
4083 data->dev_conf.txmode.hw_vlan_reject_tagged;
4084 info.config.reject.untagged =
4085 data->dev_conf.txmode.hw_vlan_reject_untagged;
4088 return i40e_vsi_vlan_pvid_set(vsi, &info);
4092 i40e_dev_led_on(struct rte_eth_dev *dev)
4094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4095 uint32_t mode = i40e_led_get(hw);
4098 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4104 i40e_dev_led_off(struct rte_eth_dev *dev)
4106 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4107 uint32_t mode = i40e_led_get(hw);
4110 i40e_led_set(hw, 0, false);
4116 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4118 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4119 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4121 fc_conf->pause_time = pf->fc_conf.pause_time;
4123 /* read out from register, in case they are modified by other port */
4124 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4125 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4126 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4127 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4129 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4130 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4132 /* Return current mode according to actual setting*/
4133 switch (hw->fc.current_mode) {
4135 fc_conf->mode = RTE_FC_FULL;
4137 case I40E_FC_TX_PAUSE:
4138 fc_conf->mode = RTE_FC_TX_PAUSE;
4140 case I40E_FC_RX_PAUSE:
4141 fc_conf->mode = RTE_FC_RX_PAUSE;
4145 fc_conf->mode = RTE_FC_NONE;
4152 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4154 uint32_t mflcn_reg, fctrl_reg, reg;
4155 uint32_t max_high_water;
4156 uint8_t i, aq_failure;
4160 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4161 [RTE_FC_NONE] = I40E_FC_NONE,
4162 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4163 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4164 [RTE_FC_FULL] = I40E_FC_FULL
4167 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4169 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4170 if ((fc_conf->high_water > max_high_water) ||
4171 (fc_conf->high_water < fc_conf->low_water)) {
4173 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4178 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4179 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4180 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4182 pf->fc_conf.pause_time = fc_conf->pause_time;
4183 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4184 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4186 PMD_INIT_FUNC_TRACE();
4188 /* All the link flow control related enable/disable register
4189 * configuration is handle by the F/W
4191 err = i40e_set_fc(hw, &aq_failure, true);
4195 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4196 /* Configure flow control refresh threshold,
4197 * the value for stat_tx_pause_refresh_timer[8]
4198 * is used for global pause operation.
4202 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4203 pf->fc_conf.pause_time);
4205 /* configure the timer value included in transmitted pause
4207 * the value for stat_tx_pause_quanta[8] is used for global
4210 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4211 pf->fc_conf.pause_time);
4213 fctrl_reg = I40E_READ_REG(hw,
4214 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4216 if (fc_conf->mac_ctrl_frame_fwd != 0)
4217 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4219 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4221 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4224 /* Configure pause time (2 TCs per register) */
4225 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4226 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4227 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4229 /* Configure flow control refresh threshold value */
4230 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4231 pf->fc_conf.pause_time / 2);
4233 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4235 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4236 *depending on configuration
4238 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4239 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4240 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4242 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4243 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4246 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4249 if (!pf->support_multi_driver) {
4250 /* config water marker both based on the packets and bytes */
4251 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4252 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4253 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4254 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4255 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4256 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4257 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4258 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4260 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4261 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4265 "Water marker configuration is not supported.");
4268 I40E_WRITE_FLUSH(hw);
4274 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4275 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4277 PMD_INIT_FUNC_TRACE();
4282 /* Add a MAC address, and update filters */
4284 i40e_macaddr_add(struct rte_eth_dev *dev,
4285 struct rte_ether_addr *mac_addr,
4286 __rte_unused uint32_t index,
4289 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4290 struct i40e_mac_filter_info mac_filter;
4291 struct i40e_vsi *vsi;
4292 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4295 /* If VMDQ not enabled or configured, return */
4296 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4297 !pf->nb_cfg_vmdq_vsi)) {
4298 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4299 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4304 if (pool > pf->nb_cfg_vmdq_vsi) {
4305 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4306 pool, pf->nb_cfg_vmdq_vsi);
4310 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4311 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4312 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4314 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4319 vsi = pf->vmdq[pool - 1].vsi;
4321 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4322 if (ret != I40E_SUCCESS) {
4323 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4329 /* Remove a MAC address, and update filters */
4331 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4333 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4334 struct i40e_vsi *vsi;
4335 struct rte_eth_dev_data *data = dev->data;
4336 struct rte_ether_addr *macaddr;
4341 macaddr = &(data->mac_addrs[index]);
4343 pool_sel = dev->data->mac_pool_sel[index];
4345 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4346 if (pool_sel & (1ULL << i)) {
4350 /* No VMDQ pool enabled or configured */
4351 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4352 (i > pf->nb_cfg_vmdq_vsi)) {
4354 "No VMDQ pool enabled/configured");
4357 vsi = pf->vmdq[i - 1].vsi;
4359 ret = i40e_vsi_delete_mac(vsi, macaddr);
4362 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4370 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4372 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4373 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4380 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4381 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4382 vsi->type != I40E_VSI_SRIOV,
4385 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4389 uint32_t *lut_dw = (uint32_t *)lut;
4390 uint16_t i, lut_size_dw = lut_size / 4;
4392 if (vsi->type == I40E_VSI_SRIOV) {
4393 for (i = 0; i <= lut_size_dw; i++) {
4394 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4395 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4398 for (i = 0; i < lut_size_dw; i++)
4399 lut_dw[i] = I40E_READ_REG(hw,
4408 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4416 pf = I40E_VSI_TO_PF(vsi);
4417 hw = I40E_VSI_TO_HW(vsi);
4419 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4420 enum i40e_status_code status;
4422 status = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4423 vsi->type != I40E_VSI_SRIOV,
4427 "Failed to update RSS lookup table, error status: %d",
4432 uint32_t *lut_dw = (uint32_t *)lut;
4433 uint16_t i, lut_size_dw = lut_size / 4;
4435 if (vsi->type == I40E_VSI_SRIOV) {
4436 for (i = 0; i < lut_size_dw; i++)
4439 I40E_VFQF_HLUT1(i, vsi->user_param),
4442 for (i = 0; i < lut_size_dw; i++)
4443 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4446 I40E_WRITE_FLUSH(hw);
4453 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4454 struct rte_eth_rss_reta_entry64 *reta_conf,
4457 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4458 uint16_t i, lut_size = pf->hash_lut_size;
4459 uint16_t idx, shift;
4463 if (reta_size != lut_size ||
4464 reta_size > ETH_RSS_RETA_SIZE_512) {
4466 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4467 reta_size, lut_size);
4471 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4473 PMD_DRV_LOG(ERR, "No memory can be allocated");
4476 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4479 for (i = 0; i < reta_size; i++) {
4480 idx = i / RTE_RETA_GROUP_SIZE;
4481 shift = i % RTE_RETA_GROUP_SIZE;
4482 if (reta_conf[idx].mask & (1ULL << shift))
4483 lut[i] = reta_conf[idx].reta[shift];
4485 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4487 pf->adapter->rss_reta_updated = 1;
4496 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4497 struct rte_eth_rss_reta_entry64 *reta_conf,
4500 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4501 uint16_t i, lut_size = pf->hash_lut_size;
4502 uint16_t idx, shift;
4506 if (reta_size != lut_size ||
4507 reta_size > ETH_RSS_RETA_SIZE_512) {
4509 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4510 reta_size, lut_size);
4514 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4516 PMD_DRV_LOG(ERR, "No memory can be allocated");
4520 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4523 for (i = 0; i < reta_size; i++) {
4524 idx = i / RTE_RETA_GROUP_SIZE;
4525 shift = i % RTE_RETA_GROUP_SIZE;
4526 if (reta_conf[idx].mask & (1ULL << shift))
4527 reta_conf[idx].reta[shift] = lut[i];
4537 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4538 * @hw: pointer to the HW structure
4539 * @mem: pointer to mem struct to fill out
4540 * @size: size of memory requested
4541 * @alignment: what to align the allocation to
4543 enum i40e_status_code
4544 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4545 struct i40e_dma_mem *mem,
4549 const struct rte_memzone *mz = NULL;
4550 char z_name[RTE_MEMZONE_NAMESIZE];
4553 return I40E_ERR_PARAM;
4555 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4556 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4557 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4559 return I40E_ERR_NO_MEMORY;
4564 mem->zone = (const void *)mz;
4566 "memzone %s allocated with physical address: %"PRIu64,
4569 return I40E_SUCCESS;
4573 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4574 * @hw: pointer to the HW structure
4575 * @mem: ptr to mem struct to free
4577 enum i40e_status_code
4578 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4579 struct i40e_dma_mem *mem)
4582 return I40E_ERR_PARAM;
4585 "memzone %s to be freed with physical address: %"PRIu64,
4586 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4587 rte_memzone_free((const struct rte_memzone *)mem->zone);
4592 return I40E_SUCCESS;
4596 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4597 * @hw: pointer to the HW structure
4598 * @mem: pointer to mem struct to fill out
4599 * @size: size of memory requested
4601 enum i40e_status_code
4602 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4603 struct i40e_virt_mem *mem,
4607 return I40E_ERR_PARAM;
4610 mem->va = rte_zmalloc("i40e", size, 0);
4613 return I40E_SUCCESS;
4615 return I40E_ERR_NO_MEMORY;
4619 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4620 * @hw: pointer to the HW structure
4621 * @mem: pointer to mem struct to free
4623 enum i40e_status_code
4624 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4625 struct i40e_virt_mem *mem)
4628 return I40E_ERR_PARAM;
4633 return I40E_SUCCESS;
4637 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4639 rte_spinlock_init(&sp->spinlock);
4643 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4645 rte_spinlock_lock(&sp->spinlock);
4649 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4651 rte_spinlock_unlock(&sp->spinlock);
4655 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4661 * Get the hardware capabilities, which will be parsed
4662 * and saved into struct i40e_hw.
4665 i40e_get_cap(struct i40e_hw *hw)
4667 struct i40e_aqc_list_capabilities_element_resp *buf;
4668 uint16_t len, size = 0;
4671 /* Calculate a huge enough buff for saving response data temporarily */
4672 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4673 I40E_MAX_CAP_ELE_NUM;
4674 buf = rte_zmalloc("i40e", len, 0);
4676 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4677 return I40E_ERR_NO_MEMORY;
4680 /* Get, parse the capabilities and save it to hw */
4681 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4682 i40e_aqc_opc_list_func_capabilities, NULL);
4683 if (ret != I40E_SUCCESS)
4684 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4686 /* Free the temporary buffer after being used */
4692 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4694 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4702 pf = (struct i40e_pf *)opaque;
4706 num = strtoul(value, &end, 0);
4707 if (errno != 0 || end == value || *end != 0) {
4708 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4709 "kept the value = %hu", value, pf->vf_nb_qp_max);
4713 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4714 pf->vf_nb_qp_max = (uint16_t)num;
4716 /* here return 0 to make next valid same argument work */
4717 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4718 "power of 2 and equal or less than 16 !, Now it is "
4719 "kept the value = %hu", num, pf->vf_nb_qp_max);
4724 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4726 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4727 struct rte_kvargs *kvlist;
4730 /* set default queue number per VF as 4 */
4731 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4733 if (dev->device->devargs == NULL)
4736 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4740 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4741 if (!kvargs_count) {
4742 rte_kvargs_free(kvlist);
4746 if (kvargs_count > 1)
4747 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4748 "the first invalid or last valid one is used !",
4749 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4751 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4752 i40e_pf_parse_vf_queue_number_handler, pf);
4754 rte_kvargs_free(kvlist);
4760 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4762 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4763 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4764 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4765 uint16_t qp_count = 0, vsi_count = 0;
4767 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4768 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4772 i40e_pf_config_vf_rxq_number(dev);
4774 /* Add the parameter init for LFC */
4775 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4776 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4777 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4779 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4780 pf->max_num_vsi = hw->func_caps.num_vsis;
4781 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4782 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4784 /* FDir queue/VSI allocation */
4785 pf->fdir_qp_offset = 0;
4786 if (hw->func_caps.fd) {
4787 pf->flags |= I40E_FLAG_FDIR;
4788 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4790 pf->fdir_nb_qps = 0;
4792 qp_count += pf->fdir_nb_qps;
4795 /* LAN queue/VSI allocation */
4796 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4797 if (!hw->func_caps.rss) {
4800 pf->flags |= I40E_FLAG_RSS;
4801 if (hw->mac.type == I40E_MAC_X722)
4802 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4803 pf->lan_nb_qps = pf->lan_nb_qp_max;
4805 qp_count += pf->lan_nb_qps;
4808 /* VF queue/VSI allocation */
4809 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4810 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4811 pf->flags |= I40E_FLAG_SRIOV;
4812 pf->vf_nb_qps = pf->vf_nb_qp_max;
4813 pf->vf_num = pci_dev->max_vfs;
4815 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4816 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4821 qp_count += pf->vf_nb_qps * pf->vf_num;
4822 vsi_count += pf->vf_num;
4824 /* VMDq queue/VSI allocation */
4825 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4826 pf->vmdq_nb_qps = 0;
4827 pf->max_nb_vmdq_vsi = 0;
4828 if (hw->func_caps.vmdq) {
4829 if (qp_count < hw->func_caps.num_tx_qp &&
4830 vsi_count < hw->func_caps.num_vsis) {
4831 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4832 qp_count) / pf->vmdq_nb_qp_max;
4834 /* Limit the maximum number of VMDq vsi to the maximum
4835 * ethdev can support
4837 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4838 hw->func_caps.num_vsis - vsi_count);
4839 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4841 if (pf->max_nb_vmdq_vsi) {
4842 pf->flags |= I40E_FLAG_VMDQ;
4843 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4845 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4846 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4847 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4850 "No enough queues left for VMDq");
4853 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4856 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4857 vsi_count += pf->max_nb_vmdq_vsi;
4859 if (hw->func_caps.dcb)
4860 pf->flags |= I40E_FLAG_DCB;
4862 if (qp_count > hw->func_caps.num_tx_qp) {
4864 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4865 qp_count, hw->func_caps.num_tx_qp);
4868 if (vsi_count > hw->func_caps.num_vsis) {
4870 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4871 vsi_count, hw->func_caps.num_vsis);
4879 i40e_pf_get_switch_config(struct i40e_pf *pf)
4881 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4882 struct i40e_aqc_get_switch_config_resp *switch_config;
4883 struct i40e_aqc_switch_config_element_resp *element;
4884 uint16_t start_seid = 0, num_reported;
4887 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4888 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4889 if (!switch_config) {
4890 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4894 /* Get the switch configurations */
4895 ret = i40e_aq_get_switch_config(hw, switch_config,
4896 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4897 if (ret != I40E_SUCCESS) {
4898 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4901 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4902 if (num_reported != 1) { /* The number should be 1 */
4903 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4907 /* Parse the switch configuration elements */
4908 element = &(switch_config->element[0]);
4909 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4910 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4911 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4913 PMD_DRV_LOG(INFO, "Unknown element type");
4916 rte_free(switch_config);
4922 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4925 struct pool_entry *entry;
4927 if (pool == NULL || num == 0)
4930 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4931 if (entry == NULL) {
4932 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4936 /* queue heap initialize */
4937 pool->num_free = num;
4938 pool->num_alloc = 0;
4940 LIST_INIT(&pool->alloc_list);
4941 LIST_INIT(&pool->free_list);
4943 /* Initialize element */
4947 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4952 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4954 struct pool_entry *entry, *next_entry;
4959 for (entry = LIST_FIRST(&pool->alloc_list);
4960 entry && (next_entry = LIST_NEXT(entry, next), 1);
4961 entry = next_entry) {
4962 LIST_REMOVE(entry, next);
4966 for (entry = LIST_FIRST(&pool->free_list);
4967 entry && (next_entry = LIST_NEXT(entry, next), 1);
4968 entry = next_entry) {
4969 LIST_REMOVE(entry, next);
4974 pool->num_alloc = 0;
4976 LIST_INIT(&pool->alloc_list);
4977 LIST_INIT(&pool->free_list);
4981 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4984 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4985 uint32_t pool_offset;
4990 PMD_DRV_LOG(ERR, "Invalid parameter");
4994 pool_offset = base - pool->base;
4995 /* Lookup in alloc list */
4996 LIST_FOREACH(entry, &pool->alloc_list, next) {
4997 if (entry->base == pool_offset) {
4998 valid_entry = entry;
4999 LIST_REMOVE(entry, next);
5004 /* Not find, return */
5005 if (valid_entry == NULL) {
5006 PMD_DRV_LOG(ERR, "Failed to find entry");
5011 * Found it, move it to free list and try to merge.
5012 * In order to make merge easier, always sort it by qbase.
5013 * Find adjacent prev and last entries.
5016 LIST_FOREACH(entry, &pool->free_list, next) {
5017 if (entry->base > valid_entry->base) {
5025 len = valid_entry->len;
5026 /* Try to merge with next one*/
5028 /* Merge with next one */
5029 if (valid_entry->base + len == next->base) {
5030 next->base = valid_entry->base;
5032 rte_free(valid_entry);
5039 /* Merge with previous one */
5040 if (prev->base + prev->len == valid_entry->base) {
5042 /* If it merge with next one, remove next node */
5044 LIST_REMOVE(valid_entry, next);
5045 rte_free(valid_entry);
5048 rte_free(valid_entry);
5055 /* Not find any entry to merge, insert */
5058 LIST_INSERT_AFTER(prev, valid_entry, next);
5059 else if (next != NULL)
5060 LIST_INSERT_BEFORE(next, valid_entry, next);
5061 else /* It's empty list, insert to head */
5062 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5065 pool->num_free += len;
5066 pool->num_alloc -= len;
5072 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5075 struct pool_entry *entry, *valid_entry;
5077 if (pool == NULL || num == 0) {
5078 PMD_DRV_LOG(ERR, "Invalid parameter");
5082 if (pool->num_free < num) {
5083 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5084 num, pool->num_free);
5089 /* Lookup in free list and find most fit one */
5090 LIST_FOREACH(entry, &pool->free_list, next) {
5091 if (entry->len >= num) {
5093 if (entry->len == num) {
5094 valid_entry = entry;
5097 if (valid_entry == NULL || valid_entry->len > entry->len)
5098 valid_entry = entry;
5102 /* Not find one to satisfy the request, return */
5103 if (valid_entry == NULL) {
5104 PMD_DRV_LOG(ERR, "No valid entry found");
5108 * The entry have equal queue number as requested,
5109 * remove it from alloc_list.
5111 if (valid_entry->len == num) {
5112 LIST_REMOVE(valid_entry, next);
5115 * The entry have more numbers than requested,
5116 * create a new entry for alloc_list and minus its
5117 * queue base and number in free_list.
5119 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5120 if (entry == NULL) {
5122 "Failed to allocate memory for resource pool");
5125 entry->base = valid_entry->base;
5127 valid_entry->base += num;
5128 valid_entry->len -= num;
5129 valid_entry = entry;
5132 /* Insert it into alloc list, not sorted */
5133 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5135 pool->num_free -= valid_entry->len;
5136 pool->num_alloc += valid_entry->len;
5138 return valid_entry->base + pool->base;
5142 * bitmap_is_subset - Check whether src2 is subset of src1
5145 bitmap_is_subset(uint8_t src1, uint8_t src2)
5147 return !((src1 ^ src2) & src2);
5150 static enum i40e_status_code
5151 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5153 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5155 /* If DCB is not supported, only default TC is supported */
5156 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5157 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5158 return I40E_NOT_SUPPORTED;
5161 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5163 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5164 hw->func_caps.enabled_tcmap, enabled_tcmap);
5165 return I40E_NOT_SUPPORTED;
5167 return I40E_SUCCESS;
5171 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5172 struct i40e_vsi_vlan_pvid_info *info)
5175 struct i40e_vsi_context ctxt;
5176 uint8_t vlan_flags = 0;
5179 if (vsi == NULL || info == NULL) {
5180 PMD_DRV_LOG(ERR, "invalid parameters");
5181 return I40E_ERR_PARAM;
5185 vsi->info.pvid = info->config.pvid;
5187 * If insert pvid is enabled, only tagged pkts are
5188 * allowed to be sent out.
5190 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5191 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5194 if (info->config.reject.tagged == 0)
5195 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5197 if (info->config.reject.untagged == 0)
5198 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5200 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5201 I40E_AQ_VSI_PVLAN_MODE_MASK);
5202 vsi->info.port_vlan_flags |= vlan_flags;
5203 vsi->info.valid_sections =
5204 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5205 memset(&ctxt, 0, sizeof(ctxt));
5206 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5207 ctxt.seid = vsi->seid;
5209 hw = I40E_VSI_TO_HW(vsi);
5210 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5211 if (ret != I40E_SUCCESS)
5212 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5218 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5220 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5222 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5224 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5225 if (ret != I40E_SUCCESS)
5229 PMD_DRV_LOG(ERR, "seid not valid");
5233 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5234 tc_bw_data.tc_valid_bits = enabled_tcmap;
5235 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5236 tc_bw_data.tc_bw_credits[i] =
5237 (enabled_tcmap & (1 << i)) ? 1 : 0;
5239 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5240 if (ret != I40E_SUCCESS) {
5241 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5245 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5246 sizeof(vsi->info.qs_handle));
5247 return I40E_SUCCESS;
5250 static enum i40e_status_code
5251 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5252 struct i40e_aqc_vsi_properties_data *info,
5253 uint8_t enabled_tcmap)
5255 enum i40e_status_code ret;
5256 int i, total_tc = 0;
5257 uint16_t qpnum_per_tc, bsf, qp_idx;
5259 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5260 if (ret != I40E_SUCCESS)
5263 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5264 if (enabled_tcmap & (1 << i))
5268 vsi->enabled_tc = enabled_tcmap;
5270 /* Number of queues per enabled TC */
5271 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5272 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5273 bsf = rte_bsf32(qpnum_per_tc);
5275 /* Adjust the queue number to actual queues that can be applied */
5276 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5277 vsi->nb_qps = qpnum_per_tc * total_tc;
5280 * Configure TC and queue mapping parameters, for enabled TC,
5281 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5282 * default queue will serve it.
5285 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5286 if (vsi->enabled_tc & (1 << i)) {
5287 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5288 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5289 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5290 qp_idx += qpnum_per_tc;
5292 info->tc_mapping[i] = 0;
5295 /* Associate queue number with VSI */
5296 if (vsi->type == I40E_VSI_SRIOV) {
5297 info->mapping_flags |=
5298 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5299 for (i = 0; i < vsi->nb_qps; i++)
5300 info->queue_mapping[i] =
5301 rte_cpu_to_le_16(vsi->base_queue + i);
5303 info->mapping_flags |=
5304 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5305 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5307 info->valid_sections |=
5308 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5310 return I40E_SUCCESS;
5314 i40e_veb_release(struct i40e_veb *veb)
5316 struct i40e_vsi *vsi;
5322 if (!TAILQ_EMPTY(&veb->head)) {
5323 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5326 /* associate_vsi field is NULL for floating VEB */
5327 if (veb->associate_vsi != NULL) {
5328 vsi = veb->associate_vsi;
5329 hw = I40E_VSI_TO_HW(vsi);
5331 vsi->uplink_seid = veb->uplink_seid;
5334 veb->associate_pf->main_vsi->floating_veb = NULL;
5335 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5338 i40e_aq_delete_element(hw, veb->seid, NULL);
5340 return I40E_SUCCESS;
5344 static struct i40e_veb *
5345 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5347 struct i40e_veb *veb;
5353 "veb setup failed, associated PF shouldn't null");
5356 hw = I40E_PF_TO_HW(pf);
5358 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5360 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5364 veb->associate_vsi = vsi;
5365 veb->associate_pf = pf;
5366 TAILQ_INIT(&veb->head);
5367 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5369 /* create floating veb if vsi is NULL */
5371 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5372 I40E_DEFAULT_TCMAP, false,
5373 &veb->seid, false, NULL);
5375 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5376 true, &veb->seid, false, NULL);
5379 if (ret != I40E_SUCCESS) {
5380 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5381 hw->aq.asq_last_status);
5384 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5386 /* get statistics index */
5387 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5388 &veb->stats_idx, NULL, NULL, NULL);
5389 if (ret != I40E_SUCCESS) {
5390 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5391 hw->aq.asq_last_status);
5394 /* Get VEB bandwidth, to be implemented */
5395 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5397 vsi->uplink_seid = veb->seid;
5406 i40e_vsi_release(struct i40e_vsi *vsi)
5410 struct i40e_vsi_list *vsi_list;
5413 struct i40e_mac_filter *f;
5414 uint16_t user_param;
5417 return I40E_SUCCESS;
5422 user_param = vsi->user_param;
5424 pf = I40E_VSI_TO_PF(vsi);
5425 hw = I40E_VSI_TO_HW(vsi);
5427 /* VSI has child to attach, release child first */
5429 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5430 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5433 i40e_veb_release(vsi->veb);
5436 if (vsi->floating_veb) {
5437 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5438 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5443 /* Remove all macvlan filters of the VSI */
5444 i40e_vsi_remove_all_macvlan_filter(vsi);
5445 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5448 if (vsi->type != I40E_VSI_MAIN &&
5449 ((vsi->type != I40E_VSI_SRIOV) ||
5450 !pf->floating_veb_list[user_param])) {
5451 /* Remove vsi from parent's sibling list */
5452 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5453 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5454 return I40E_ERR_PARAM;
5456 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5457 &vsi->sib_vsi_list, list);
5459 /* Remove all switch element of the VSI */
5460 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5461 if (ret != I40E_SUCCESS)
5462 PMD_DRV_LOG(ERR, "Failed to delete element");
5465 if ((vsi->type == I40E_VSI_SRIOV) &&
5466 pf->floating_veb_list[user_param]) {
5467 /* Remove vsi from parent's sibling list */
5468 if (vsi->parent_vsi == NULL ||
5469 vsi->parent_vsi->floating_veb == NULL) {
5470 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5471 return I40E_ERR_PARAM;
5473 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5474 &vsi->sib_vsi_list, list);
5476 /* Remove all switch element of the VSI */
5477 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5478 if (ret != I40E_SUCCESS)
5479 PMD_DRV_LOG(ERR, "Failed to delete element");
5482 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5484 if (vsi->type != I40E_VSI_SRIOV)
5485 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5488 return I40E_SUCCESS;
5492 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5494 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5495 struct i40e_aqc_remove_macvlan_element_data def_filter;
5496 struct i40e_mac_filter_info filter;
5499 if (vsi->type != I40E_VSI_MAIN)
5500 return I40E_ERR_CONFIG;
5501 memset(&def_filter, 0, sizeof(def_filter));
5502 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5504 def_filter.vlan_tag = 0;
5505 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5506 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5507 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5508 if (ret != I40E_SUCCESS) {
5509 struct i40e_mac_filter *f;
5510 struct rte_ether_addr *mac;
5513 "Cannot remove the default macvlan filter");
5514 /* It needs to add the permanent mac into mac list */
5515 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5517 PMD_DRV_LOG(ERR, "failed to allocate memory");
5518 return I40E_ERR_NO_MEMORY;
5520 mac = &f->mac_info.mac_addr;
5521 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5523 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5524 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5529 rte_memcpy(&filter.mac_addr,
5530 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5531 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5532 return i40e_vsi_add_mac(vsi, &filter);
5536 * i40e_vsi_get_bw_config - Query VSI BW Information
5537 * @vsi: the VSI to be queried
5539 * Returns 0 on success, negative value on failure
5541 static enum i40e_status_code
5542 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5544 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5545 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5546 struct i40e_hw *hw = &vsi->adapter->hw;
5551 memset(&bw_config, 0, sizeof(bw_config));
5552 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5553 if (ret != I40E_SUCCESS) {
5554 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5555 hw->aq.asq_last_status);
5559 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5560 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5561 &ets_sla_config, NULL);
5562 if (ret != I40E_SUCCESS) {
5564 "VSI failed to get TC bandwdith configuration %u",
5565 hw->aq.asq_last_status);
5569 /* store and print out BW info */
5570 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5571 vsi->bw_info.bw_max = bw_config.max_bw;
5572 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5573 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5574 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5575 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5577 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5578 vsi->bw_info.bw_ets_share_credits[i] =
5579 ets_sla_config.share_credits[i];
5580 vsi->bw_info.bw_ets_credits[i] =
5581 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5582 /* 4 bits per TC, 4th bit is reserved */
5583 vsi->bw_info.bw_ets_max[i] =
5584 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5585 RTE_LEN2MASK(3, uint8_t));
5586 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5587 vsi->bw_info.bw_ets_share_credits[i]);
5588 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5589 vsi->bw_info.bw_ets_credits[i]);
5590 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5591 vsi->bw_info.bw_ets_max[i]);
5594 return I40E_SUCCESS;
5597 /* i40e_enable_pf_lb
5598 * @pf: pointer to the pf structure
5600 * allow loopback on pf
5603 i40e_enable_pf_lb(struct i40e_pf *pf)
5605 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5606 struct i40e_vsi_context ctxt;
5609 /* Use the FW API if FW >= v5.0 */
5610 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5611 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5615 memset(&ctxt, 0, sizeof(ctxt));
5616 ctxt.seid = pf->main_vsi_seid;
5617 ctxt.pf_num = hw->pf_id;
5618 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5620 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5621 ret, hw->aq.asq_last_status);
5624 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5625 ctxt.info.valid_sections =
5626 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5627 ctxt.info.switch_id |=
5628 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5630 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5632 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5633 hw->aq.asq_last_status);
5638 i40e_vsi_setup(struct i40e_pf *pf,
5639 enum i40e_vsi_type type,
5640 struct i40e_vsi *uplink_vsi,
5641 uint16_t user_param)
5643 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5644 struct i40e_vsi *vsi;
5645 struct i40e_mac_filter_info filter;
5647 struct i40e_vsi_context ctxt;
5648 struct rte_ether_addr broadcast =
5649 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5651 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5652 uplink_vsi == NULL) {
5654 "VSI setup failed, VSI link shouldn't be NULL");
5658 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5660 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5665 * 1.type is not MAIN and uplink vsi is not NULL
5666 * If uplink vsi didn't setup VEB, create one first under veb field
5667 * 2.type is SRIOV and the uplink is NULL
5668 * If floating VEB is NULL, create one veb under floating veb field
5671 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5672 uplink_vsi->veb == NULL) {
5673 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5675 if (uplink_vsi->veb == NULL) {
5676 PMD_DRV_LOG(ERR, "VEB setup failed");
5679 /* set ALLOWLOOPBACk on pf, when veb is created */
5680 i40e_enable_pf_lb(pf);
5683 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5684 pf->main_vsi->floating_veb == NULL) {
5685 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5687 if (pf->main_vsi->floating_veb == NULL) {
5688 PMD_DRV_LOG(ERR, "VEB setup failed");
5693 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5695 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5698 TAILQ_INIT(&vsi->mac_list);
5700 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5701 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5702 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5703 vsi->user_param = user_param;
5704 vsi->vlan_anti_spoof_on = 0;
5705 vsi->vlan_filter_on = 0;
5706 /* Allocate queues */
5707 switch (vsi->type) {
5708 case I40E_VSI_MAIN :
5709 vsi->nb_qps = pf->lan_nb_qps;
5711 case I40E_VSI_SRIOV :
5712 vsi->nb_qps = pf->vf_nb_qps;
5714 case I40E_VSI_VMDQ2:
5715 vsi->nb_qps = pf->vmdq_nb_qps;
5718 vsi->nb_qps = pf->fdir_nb_qps;
5724 * The filter status descriptor is reported in rx queue 0,
5725 * while the tx queue for fdir filter programming has no
5726 * such constraints, can be non-zero queues.
5727 * To simplify it, choose FDIR vsi use queue 0 pair.
5728 * To make sure it will use queue 0 pair, queue allocation
5729 * need be done before this function is called
5731 if (type != I40E_VSI_FDIR) {
5732 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5734 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5738 vsi->base_queue = ret;
5740 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5742 /* VF has MSIX interrupt in VF range, don't allocate here */
5743 if (type == I40E_VSI_MAIN) {
5744 if (pf->support_multi_driver) {
5745 /* If support multi-driver, need to use INT0 instead of
5746 * allocating from msix pool. The Msix pool is init from
5747 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5748 * to 1 without calling i40e_res_pool_alloc.
5753 ret = i40e_res_pool_alloc(&pf->msix_pool,
5754 RTE_MIN(vsi->nb_qps,
5755 RTE_MAX_RXTX_INTR_VEC_ID));
5758 "VSI MAIN %d get heap failed %d",
5760 goto fail_queue_alloc;
5762 vsi->msix_intr = ret;
5763 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5764 RTE_MAX_RXTX_INTR_VEC_ID);
5766 } else if (type != I40E_VSI_SRIOV) {
5767 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5769 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5770 if (type != I40E_VSI_FDIR)
5771 goto fail_queue_alloc;
5775 vsi->msix_intr = ret;
5784 if (type == I40E_VSI_MAIN) {
5785 /* For main VSI, no need to add since it's default one */
5786 vsi->uplink_seid = pf->mac_seid;
5787 vsi->seid = pf->main_vsi_seid;
5788 /* Bind queues with specific MSIX interrupt */
5790 * Needs 2 interrupt at least, one for misc cause which will
5791 * enabled from OS side, Another for queues binding the
5792 * interrupt from device side only.
5795 /* Get default VSI parameters from hardware */
5796 memset(&ctxt, 0, sizeof(ctxt));
5797 ctxt.seid = vsi->seid;
5798 ctxt.pf_num = hw->pf_id;
5799 ctxt.uplink_seid = vsi->uplink_seid;
5801 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5802 if (ret != I40E_SUCCESS) {
5803 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5804 goto fail_msix_alloc;
5806 rte_memcpy(&vsi->info, &ctxt.info,
5807 sizeof(struct i40e_aqc_vsi_properties_data));
5808 vsi->vsi_id = ctxt.vsi_number;
5809 vsi->info.valid_sections = 0;
5811 /* Configure tc, enabled TC0 only */
5812 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5814 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5815 goto fail_msix_alloc;
5818 /* TC, queue mapping */
5819 memset(&ctxt, 0, sizeof(ctxt));
5820 vsi->info.valid_sections |=
5821 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5822 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5823 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5824 rte_memcpy(&ctxt.info, &vsi->info,
5825 sizeof(struct i40e_aqc_vsi_properties_data));
5826 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5827 I40E_DEFAULT_TCMAP);
5828 if (ret != I40E_SUCCESS) {
5830 "Failed to configure TC queue mapping");
5831 goto fail_msix_alloc;
5833 ctxt.seid = vsi->seid;
5834 ctxt.pf_num = hw->pf_id;
5835 ctxt.uplink_seid = vsi->uplink_seid;
5838 /* Update VSI parameters */
5839 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5840 if (ret != I40E_SUCCESS) {
5841 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5842 goto fail_msix_alloc;
5845 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5846 sizeof(vsi->info.tc_mapping));
5847 rte_memcpy(&vsi->info.queue_mapping,
5848 &ctxt.info.queue_mapping,
5849 sizeof(vsi->info.queue_mapping));
5850 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5851 vsi->info.valid_sections = 0;
5853 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5857 * Updating default filter settings are necessary to prevent
5858 * reception of tagged packets.
5859 * Some old firmware configurations load a default macvlan
5860 * filter which accepts both tagged and untagged packets.
5861 * The updating is to use a normal filter instead if needed.
5862 * For NVM 4.2.2 or after, the updating is not needed anymore.
5863 * The firmware with correct configurations load the default
5864 * macvlan filter which is expected and cannot be removed.
5866 i40e_update_default_filter_setting(vsi);
5867 i40e_config_qinq(hw, vsi);
5868 } else if (type == I40E_VSI_SRIOV) {
5869 memset(&ctxt, 0, sizeof(ctxt));
5871 * For other VSI, the uplink_seid equals to uplink VSI's
5872 * uplink_seid since they share same VEB
5874 if (uplink_vsi == NULL)
5875 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5877 vsi->uplink_seid = uplink_vsi->uplink_seid;
5878 ctxt.pf_num = hw->pf_id;
5879 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5880 ctxt.uplink_seid = vsi->uplink_seid;
5881 ctxt.connection_type = 0x1;
5882 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5884 /* Use the VEB configuration if FW >= v5.0 */
5885 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5886 /* Configure switch ID */
5887 ctxt.info.valid_sections |=
5888 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5889 ctxt.info.switch_id =
5890 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5893 /* Configure port/vlan */
5894 ctxt.info.valid_sections |=
5895 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5896 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5897 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5898 hw->func_caps.enabled_tcmap);
5899 if (ret != I40E_SUCCESS) {
5901 "Failed to configure TC queue mapping");
5902 goto fail_msix_alloc;
5905 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5906 ctxt.info.valid_sections |=
5907 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5909 * Since VSI is not created yet, only configure parameter,
5910 * will add vsi below.
5913 i40e_config_qinq(hw, vsi);
5914 } else if (type == I40E_VSI_VMDQ2) {
5915 memset(&ctxt, 0, sizeof(ctxt));
5917 * For other VSI, the uplink_seid equals to uplink VSI's
5918 * uplink_seid since they share same VEB
5920 vsi->uplink_seid = uplink_vsi->uplink_seid;
5921 ctxt.pf_num = hw->pf_id;
5923 ctxt.uplink_seid = vsi->uplink_seid;
5924 ctxt.connection_type = 0x1;
5925 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5927 ctxt.info.valid_sections |=
5928 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5929 /* user_param carries flag to enable loop back */
5931 ctxt.info.switch_id =
5932 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5933 ctxt.info.switch_id |=
5934 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5937 /* Configure port/vlan */
5938 ctxt.info.valid_sections |=
5939 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5940 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5941 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5942 I40E_DEFAULT_TCMAP);
5943 if (ret != I40E_SUCCESS) {
5945 "Failed to configure TC queue mapping");
5946 goto fail_msix_alloc;
5948 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5949 ctxt.info.valid_sections |=
5950 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5951 } else if (type == I40E_VSI_FDIR) {
5952 memset(&ctxt, 0, sizeof(ctxt));
5953 vsi->uplink_seid = uplink_vsi->uplink_seid;
5954 ctxt.pf_num = hw->pf_id;
5956 ctxt.uplink_seid = vsi->uplink_seid;
5957 ctxt.connection_type = 0x1; /* regular data port */
5958 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5959 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5960 I40E_DEFAULT_TCMAP);
5961 if (ret != I40E_SUCCESS) {
5963 "Failed to configure TC queue mapping.");
5964 goto fail_msix_alloc;
5966 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5967 ctxt.info.valid_sections |=
5968 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5970 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5971 goto fail_msix_alloc;
5974 if (vsi->type != I40E_VSI_MAIN) {
5975 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5976 if (ret != I40E_SUCCESS) {
5977 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5978 hw->aq.asq_last_status);
5979 goto fail_msix_alloc;
5981 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5982 vsi->info.valid_sections = 0;
5983 vsi->seid = ctxt.seid;
5984 vsi->vsi_id = ctxt.vsi_number;
5985 vsi->sib_vsi_list.vsi = vsi;
5986 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5987 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5988 &vsi->sib_vsi_list, list);
5990 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5991 &vsi->sib_vsi_list, list);
5995 /* MAC/VLAN configuration */
5996 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5997 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5999 ret = i40e_vsi_add_mac(vsi, &filter);
6000 if (ret != I40E_SUCCESS) {
6001 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6002 goto fail_msix_alloc;
6005 /* Get VSI BW information */
6006 i40e_vsi_get_bw_config(vsi);
6009 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6011 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6017 /* Configure vlan filter on or off */
6019 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6022 struct i40e_mac_filter *f;
6024 struct i40e_mac_filter_info *mac_filter;
6025 enum i40e_mac_filter_type desired_filter;
6026 int ret = I40E_SUCCESS;
6029 /* Filter to match MAC and VLAN */
6030 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6032 /* Filter to match only MAC */
6033 desired_filter = I40E_MAC_PERFECT_MATCH;
6038 mac_filter = rte_zmalloc("mac_filter_info_data",
6039 num * sizeof(*mac_filter), 0);
6040 if (mac_filter == NULL) {
6041 PMD_DRV_LOG(ERR, "failed to allocate memory");
6042 return I40E_ERR_NO_MEMORY;
6047 /* Remove all existing mac */
6048 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6049 mac_filter[i] = f->mac_info;
6050 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6052 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6053 on ? "enable" : "disable");
6059 /* Override with new filter */
6060 for (i = 0; i < num; i++) {
6061 mac_filter[i].filter_type = desired_filter;
6062 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6064 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6065 on ? "enable" : "disable");
6071 rte_free(mac_filter);
6075 /* Configure vlan stripping on or off */
6077 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6079 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6080 struct i40e_vsi_context ctxt;
6082 int ret = I40E_SUCCESS;
6084 /* Check if it has been already on or off */
6085 if (vsi->info.valid_sections &
6086 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6088 if ((vsi->info.port_vlan_flags &
6089 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6090 return 0; /* already on */
6092 if ((vsi->info.port_vlan_flags &
6093 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6094 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6095 return 0; /* already off */
6100 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6102 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6103 vsi->info.valid_sections =
6104 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6105 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6106 vsi->info.port_vlan_flags |= vlan_flags;
6107 ctxt.seid = vsi->seid;
6108 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6109 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6111 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6112 on ? "enable" : "disable");
6118 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6120 struct rte_eth_dev_data *data = dev->data;
6124 /* Apply vlan offload setting */
6125 mask = ETH_VLAN_STRIP_MASK |
6126 ETH_QINQ_STRIP_MASK |
6127 ETH_VLAN_FILTER_MASK |
6128 ETH_VLAN_EXTEND_MASK;
6129 ret = i40e_vlan_offload_set(dev, mask);
6131 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6135 /* Apply pvid setting */
6136 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6137 data->dev_conf.txmode.hw_vlan_insert_pvid);
6139 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6145 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6147 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6149 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6153 i40e_update_flow_control(struct i40e_hw *hw)
6155 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6156 struct i40e_link_status link_status;
6157 uint32_t rxfc = 0, txfc = 0, reg;
6161 memset(&link_status, 0, sizeof(link_status));
6162 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6163 if (ret != I40E_SUCCESS) {
6164 PMD_DRV_LOG(ERR, "Failed to get link status information");
6165 goto write_reg; /* Disable flow control */
6168 an_info = hw->phy.link_info.an_info;
6169 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6170 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6171 ret = I40E_ERR_NOT_READY;
6172 goto write_reg; /* Disable flow control */
6175 * If link auto negotiation is enabled, flow control needs to
6176 * be configured according to it
6178 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6179 case I40E_LINK_PAUSE_RXTX:
6182 hw->fc.current_mode = I40E_FC_FULL;
6184 case I40E_AQ_LINK_PAUSE_RX:
6186 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6188 case I40E_AQ_LINK_PAUSE_TX:
6190 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6193 hw->fc.current_mode = I40E_FC_NONE;
6198 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6199 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6200 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6201 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6202 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6203 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6210 i40e_pf_setup(struct i40e_pf *pf)
6212 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6213 struct i40e_filter_control_settings settings;
6214 struct i40e_vsi *vsi;
6217 /* Clear all stats counters */
6218 pf->offset_loaded = FALSE;
6219 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6220 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6221 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6222 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6224 ret = i40e_pf_get_switch_config(pf);
6225 if (ret != I40E_SUCCESS) {
6226 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6230 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6232 PMD_INIT_LOG(WARNING,
6233 "failed to allocate switch domain for device %d", ret);
6235 if (pf->flags & I40E_FLAG_FDIR) {
6236 /* make queue allocated first, let FDIR use queue pair 0*/
6237 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6238 if (ret != I40E_FDIR_QUEUE_ID) {
6240 "queue allocation fails for FDIR: ret =%d",
6242 pf->flags &= ~I40E_FLAG_FDIR;
6245 /* main VSI setup */
6246 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6248 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6249 return I40E_ERR_NOT_READY;
6253 /* Configure filter control */
6254 memset(&settings, 0, sizeof(settings));
6255 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6256 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6257 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6258 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6260 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6261 hw->func_caps.rss_table_size);
6262 return I40E_ERR_PARAM;
6264 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6265 hw->func_caps.rss_table_size);
6266 pf->hash_lut_size = hw->func_caps.rss_table_size;
6268 /* Enable ethtype and macvlan filters */
6269 settings.enable_ethtype = TRUE;
6270 settings.enable_macvlan = TRUE;
6271 ret = i40e_set_filter_control(hw, &settings);
6273 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6276 /* Update flow control according to the auto negotiation */
6277 i40e_update_flow_control(hw);
6279 return I40E_SUCCESS;
6283 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6289 * Set or clear TX Queue Disable flags,
6290 * which is required by hardware.
6292 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6293 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6295 /* Wait until the request is finished */
6296 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6297 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6298 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6299 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6300 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6306 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6307 return I40E_SUCCESS; /* already on, skip next steps */
6309 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6310 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6312 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6313 return I40E_SUCCESS; /* already off, skip next steps */
6314 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6316 /* Write the register */
6317 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6318 /* Check the result */
6319 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6320 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6321 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6323 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6324 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6327 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6328 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6332 /* Check if it is timeout */
6333 if (j >= I40E_CHK_Q_ENA_COUNT) {
6334 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6335 (on ? "enable" : "disable"), q_idx);
6336 return I40E_ERR_TIMEOUT;
6339 return I40E_SUCCESS;
6343 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6348 /* Wait until the request is finished */
6349 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6350 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6351 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6352 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6353 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6358 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6359 return I40E_SUCCESS; /* Already on, skip next steps */
6360 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6362 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6363 return I40E_SUCCESS; /* Already off, skip next steps */
6364 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6367 /* Write the register */
6368 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6369 /* Check the result */
6370 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6371 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6372 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6374 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6375 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6378 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6379 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6384 /* Check if it is timeout */
6385 if (j >= I40E_CHK_Q_ENA_COUNT) {
6386 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6387 (on ? "enable" : "disable"), q_idx);
6388 return I40E_ERR_TIMEOUT;
6391 return I40E_SUCCESS;
6394 /* Initialize VSI for TX */
6396 i40e_dev_tx_init(struct i40e_pf *pf)
6398 struct rte_eth_dev_data *data = pf->dev_data;
6400 uint32_t ret = I40E_SUCCESS;
6401 struct i40e_tx_queue *txq;
6403 for (i = 0; i < data->nb_tx_queues; i++) {
6404 txq = data->tx_queues[i];
6405 if (!txq || !txq->q_set)
6407 ret = i40e_tx_queue_init(txq);
6408 if (ret != I40E_SUCCESS)
6411 if (ret == I40E_SUCCESS)
6412 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6418 /* Initialize VSI for RX */
6420 i40e_dev_rx_init(struct i40e_pf *pf)
6422 struct rte_eth_dev_data *data = pf->dev_data;
6423 int ret = I40E_SUCCESS;
6425 struct i40e_rx_queue *rxq;
6427 i40e_pf_config_rss(pf);
6428 for (i = 0; i < data->nb_rx_queues; i++) {
6429 rxq = data->rx_queues[i];
6430 if (!rxq || !rxq->q_set)
6433 ret = i40e_rx_queue_init(rxq);
6434 if (ret != I40E_SUCCESS) {
6436 "Failed to do RX queue initialization");
6440 if (ret == I40E_SUCCESS)
6441 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6448 i40e_dev_rxtx_init(struct i40e_pf *pf)
6452 err = i40e_dev_tx_init(pf);
6454 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6457 err = i40e_dev_rx_init(pf);
6459 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6467 i40e_vmdq_setup(struct rte_eth_dev *dev)
6469 struct rte_eth_conf *conf = &dev->data->dev_conf;
6470 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6471 int i, err, conf_vsis, j, loop;
6472 struct i40e_vsi *vsi;
6473 struct i40e_vmdq_info *vmdq_info;
6474 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6475 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6478 * Disable interrupt to avoid message from VF. Furthermore, it will
6479 * avoid race condition in VSI creation/destroy.
6481 i40e_pf_disable_irq0(hw);
6483 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6484 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6488 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6489 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6490 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6491 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6492 pf->max_nb_vmdq_vsi);
6496 if (pf->vmdq != NULL) {
6497 PMD_INIT_LOG(INFO, "VMDQ already configured");
6501 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6502 sizeof(*vmdq_info) * conf_vsis, 0);
6504 if (pf->vmdq == NULL) {
6505 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6509 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6511 /* Create VMDQ VSI */
6512 for (i = 0; i < conf_vsis; i++) {
6513 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6514 vmdq_conf->enable_loop_back);
6516 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6520 vmdq_info = &pf->vmdq[i];
6522 vmdq_info->vsi = vsi;
6524 pf->nb_cfg_vmdq_vsi = conf_vsis;
6526 /* Configure Vlan */
6527 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6528 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6529 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6530 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6531 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6532 vmdq_conf->pool_map[i].vlan_id, j);
6534 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6535 vmdq_conf->pool_map[i].vlan_id);
6537 PMD_INIT_LOG(ERR, "Failed to add vlan");
6545 i40e_pf_enable_irq0(hw);
6550 for (i = 0; i < conf_vsis; i++)
6551 if (pf->vmdq[i].vsi == NULL)
6554 i40e_vsi_release(pf->vmdq[i].vsi);
6558 i40e_pf_enable_irq0(hw);
6563 i40e_stat_update_32(struct i40e_hw *hw,
6571 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6575 if (new_data >= *offset)
6576 *stat = (uint64_t)(new_data - *offset);
6578 *stat = (uint64_t)((new_data +
6579 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6583 i40e_stat_update_48(struct i40e_hw *hw,
6592 if (hw->device_id == I40E_DEV_ID_QEMU) {
6593 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6594 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6595 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6597 new_data = I40E_READ_REG64(hw, loreg);
6603 if (new_data >= *offset)
6604 *stat = new_data - *offset;
6606 *stat = (uint64_t)((new_data +
6607 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6609 *stat &= I40E_48_BIT_MASK;
6614 i40e_pf_disable_irq0(struct i40e_hw *hw)
6616 /* Disable all interrupt types */
6617 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6618 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6619 I40E_WRITE_FLUSH(hw);
6624 i40e_pf_enable_irq0(struct i40e_hw *hw)
6626 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6627 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6628 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6629 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6630 I40E_WRITE_FLUSH(hw);
6634 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6636 /* read pending request and disable first */
6637 i40e_pf_disable_irq0(hw);
6638 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6639 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6640 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6643 /* Link no queues with irq0 */
6644 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6645 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6649 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6651 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6652 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6655 uint32_t index, offset, val;
6660 * Try to find which VF trigger a reset, use absolute VF id to access
6661 * since the reg is global register.
6663 for (i = 0; i < pf->vf_num; i++) {
6664 abs_vf_id = hw->func_caps.vf_base_id + i;
6665 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6666 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6667 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6668 /* VFR event occurred */
6669 if (val & (0x1 << offset)) {
6672 /* Clear the event first */
6673 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6675 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6677 * Only notify a VF reset event occurred,
6678 * don't trigger another SW reset
6680 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6681 if (ret != I40E_SUCCESS)
6682 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6688 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6690 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6693 for (i = 0; i < pf->vf_num; i++)
6694 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6698 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6700 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6701 struct i40e_arq_event_info info;
6702 uint16_t pending, opcode;
6705 info.buf_len = I40E_AQ_BUF_SZ;
6706 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6707 if (!info.msg_buf) {
6708 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6714 ret = i40e_clean_arq_element(hw, &info, &pending);
6716 if (ret != I40E_SUCCESS) {
6718 "Failed to read msg from AdminQ, aq_err: %u",
6719 hw->aq.asq_last_status);
6722 opcode = rte_le_to_cpu_16(info.desc.opcode);
6725 case i40e_aqc_opc_send_msg_to_pf:
6726 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6727 i40e_pf_host_handle_vf_msg(dev,
6728 rte_le_to_cpu_16(info.desc.retval),
6729 rte_le_to_cpu_32(info.desc.cookie_high),
6730 rte_le_to_cpu_32(info.desc.cookie_low),
6734 case i40e_aqc_opc_get_link_status:
6735 ret = i40e_dev_link_update(dev, 0);
6737 rte_eth_dev_callback_process(dev,
6738 RTE_ETH_EVENT_INTR_LSC, NULL);
6741 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6746 rte_free(info.msg_buf);
6750 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6752 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6753 #define I40E_MDD_CLEAR16 0xFFFF
6754 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6755 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6756 bool mdd_detected = false;
6757 struct i40e_pf_vf *vf;
6761 /* find what triggered the MDD event */
6762 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6763 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6764 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6765 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6766 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6767 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6768 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6769 I40E_GL_MDET_TX_EVENT_SHIFT;
6770 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6771 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6772 hw->func_caps.base_queue;
6773 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6774 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6775 event, queue, pf_num, vf_num, dev->data->name);
6776 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6777 mdd_detected = true;
6779 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6780 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6781 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6782 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6783 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6784 I40E_GL_MDET_RX_EVENT_SHIFT;
6785 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6786 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6787 hw->func_caps.base_queue;
6789 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6790 "queue %d of function 0x%02x device %s\n",
6791 event, queue, func, dev->data->name);
6792 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6793 mdd_detected = true;
6797 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6798 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6799 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6800 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6802 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6803 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6804 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6806 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6810 /* see if one of the VFs needs its hand slapped */
6811 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6813 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6814 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6815 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6817 vf->num_mdd_events++;
6818 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6820 i, vf->num_mdd_events);
6823 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6824 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6825 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6827 vf->num_mdd_events++;
6828 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6830 i, vf->num_mdd_events);
6836 * Interrupt handler triggered by NIC for handling
6837 * specific interrupt.
6840 * Pointer to interrupt handle.
6842 * The address of parameter (struct rte_eth_dev *) regsitered before.
6848 i40e_dev_interrupt_handler(void *param)
6850 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6851 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6854 /* Disable interrupt */
6855 i40e_pf_disable_irq0(hw);
6857 /* read out interrupt causes */
6858 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6860 /* No interrupt event indicated */
6861 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6862 PMD_DRV_LOG(INFO, "No interrupt event");
6865 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6866 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6867 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6868 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6869 i40e_handle_mdd_event(dev);
6871 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6872 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6873 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6874 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6875 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6876 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6877 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6878 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6879 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6880 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6882 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6883 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6884 i40e_dev_handle_vfr_event(dev);
6886 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6887 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6888 i40e_dev_handle_aq_msg(dev);
6892 /* Enable interrupt */
6893 i40e_pf_enable_irq0(hw);
6897 i40e_dev_alarm_handler(void *param)
6899 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6900 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6903 /* Disable interrupt */
6904 i40e_pf_disable_irq0(hw);
6906 /* read out interrupt causes */
6907 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6909 /* No interrupt event indicated */
6910 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6912 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6913 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6914 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6915 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6916 i40e_handle_mdd_event(dev);
6918 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6919 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6920 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6921 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6922 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6923 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6924 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6925 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6926 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6927 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6929 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6930 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6931 i40e_dev_handle_vfr_event(dev);
6933 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6934 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6935 i40e_dev_handle_aq_msg(dev);
6939 /* Enable interrupt */
6940 i40e_pf_enable_irq0(hw);
6941 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6942 i40e_dev_alarm_handler, dev);
6946 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6947 struct i40e_macvlan_filter *filter,
6950 int ele_num, ele_buff_size;
6951 int num, actual_num, i;
6953 int ret = I40E_SUCCESS;
6954 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6955 struct i40e_aqc_add_macvlan_element_data *req_list;
6957 if (filter == NULL || total == 0)
6958 return I40E_ERR_PARAM;
6959 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6960 ele_buff_size = hw->aq.asq_buf_size;
6962 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6963 if (req_list == NULL) {
6964 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6965 return I40E_ERR_NO_MEMORY;
6970 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6971 memset(req_list, 0, ele_buff_size);
6973 for (i = 0; i < actual_num; i++) {
6974 rte_memcpy(req_list[i].mac_addr,
6975 &filter[num + i].macaddr, ETH_ADDR_LEN);
6976 req_list[i].vlan_tag =
6977 rte_cpu_to_le_16(filter[num + i].vlan_id);
6979 switch (filter[num + i].filter_type) {
6980 case I40E_MAC_PERFECT_MATCH:
6981 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6982 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6984 case I40E_MACVLAN_PERFECT_MATCH:
6985 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6987 case I40E_MAC_HASH_MATCH:
6988 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6989 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6991 case I40E_MACVLAN_HASH_MATCH:
6992 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6995 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6996 ret = I40E_ERR_PARAM;
7000 req_list[i].queue_number = 0;
7002 req_list[i].flags = rte_cpu_to_le_16(flags);
7005 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7007 if (ret != I40E_SUCCESS) {
7008 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7012 } while (num < total);
7020 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7021 struct i40e_macvlan_filter *filter,
7024 int ele_num, ele_buff_size;
7025 int num, actual_num, i;
7027 int ret = I40E_SUCCESS;
7028 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7029 struct i40e_aqc_remove_macvlan_element_data *req_list;
7031 if (filter == NULL || total == 0)
7032 return I40E_ERR_PARAM;
7034 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7035 ele_buff_size = hw->aq.asq_buf_size;
7037 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7038 if (req_list == NULL) {
7039 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7040 return I40E_ERR_NO_MEMORY;
7045 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7046 memset(req_list, 0, ele_buff_size);
7048 for (i = 0; i < actual_num; i++) {
7049 rte_memcpy(req_list[i].mac_addr,
7050 &filter[num + i].macaddr, ETH_ADDR_LEN);
7051 req_list[i].vlan_tag =
7052 rte_cpu_to_le_16(filter[num + i].vlan_id);
7054 switch (filter[num + i].filter_type) {
7055 case I40E_MAC_PERFECT_MATCH:
7056 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7057 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7059 case I40E_MACVLAN_PERFECT_MATCH:
7060 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7062 case I40E_MAC_HASH_MATCH:
7063 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7064 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7066 case I40E_MACVLAN_HASH_MATCH:
7067 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7070 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7071 ret = I40E_ERR_PARAM;
7074 req_list[i].flags = rte_cpu_to_le_16(flags);
7077 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7079 if (ret != I40E_SUCCESS) {
7080 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7084 } while (num < total);
7091 /* Find out specific MAC filter */
7092 static struct i40e_mac_filter *
7093 i40e_find_mac_filter(struct i40e_vsi *vsi,
7094 struct rte_ether_addr *macaddr)
7096 struct i40e_mac_filter *f;
7098 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7099 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7107 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7110 uint32_t vid_idx, vid_bit;
7112 if (vlan_id > ETH_VLAN_ID_MAX)
7115 vid_idx = I40E_VFTA_IDX(vlan_id);
7116 vid_bit = I40E_VFTA_BIT(vlan_id);
7118 if (vsi->vfta[vid_idx] & vid_bit)
7125 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7126 uint16_t vlan_id, bool on)
7128 uint32_t vid_idx, vid_bit;
7130 vid_idx = I40E_VFTA_IDX(vlan_id);
7131 vid_bit = I40E_VFTA_BIT(vlan_id);
7134 vsi->vfta[vid_idx] |= vid_bit;
7136 vsi->vfta[vid_idx] &= ~vid_bit;
7140 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7141 uint16_t vlan_id, bool on)
7143 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7144 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7147 if (vlan_id > ETH_VLAN_ID_MAX)
7150 i40e_store_vlan_filter(vsi, vlan_id, on);
7152 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7155 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7158 ret = i40e_aq_add_vlan(hw, vsi->seid,
7159 &vlan_data, 1, NULL);
7160 if (ret != I40E_SUCCESS)
7161 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7163 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7164 &vlan_data, 1, NULL);
7165 if (ret != I40E_SUCCESS)
7167 "Failed to remove vlan filter");
7172 * Find all vlan options for specific mac addr,
7173 * return with actual vlan found.
7176 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7177 struct i40e_macvlan_filter *mv_f,
7178 int num, struct rte_ether_addr *addr)
7184 * Not to use i40e_find_vlan_filter to decrease the loop time,
7185 * although the code looks complex.
7187 if (num < vsi->vlan_num)
7188 return I40E_ERR_PARAM;
7191 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7193 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7194 if (vsi->vfta[j] & (1 << k)) {
7197 "vlan number doesn't match");
7198 return I40E_ERR_PARAM;
7200 rte_memcpy(&mv_f[i].macaddr,
7201 addr, ETH_ADDR_LEN);
7203 j * I40E_UINT32_BIT_SIZE + k;
7209 return I40E_SUCCESS;
7213 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7214 struct i40e_macvlan_filter *mv_f,
7219 struct i40e_mac_filter *f;
7221 if (num < vsi->mac_num)
7222 return I40E_ERR_PARAM;
7224 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7226 PMD_DRV_LOG(ERR, "buffer number not match");
7227 return I40E_ERR_PARAM;
7229 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7231 mv_f[i].vlan_id = vlan;
7232 mv_f[i].filter_type = f->mac_info.filter_type;
7236 return I40E_SUCCESS;
7240 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7243 struct i40e_mac_filter *f;
7244 struct i40e_macvlan_filter *mv_f;
7245 int ret = I40E_SUCCESS;
7247 if (vsi == NULL || vsi->mac_num == 0)
7248 return I40E_ERR_PARAM;
7250 /* Case that no vlan is set */
7251 if (vsi->vlan_num == 0)
7254 num = vsi->mac_num * vsi->vlan_num;
7256 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7258 PMD_DRV_LOG(ERR, "failed to allocate memory");
7259 return I40E_ERR_NO_MEMORY;
7263 if (vsi->vlan_num == 0) {
7264 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7265 rte_memcpy(&mv_f[i].macaddr,
7266 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7267 mv_f[i].filter_type = f->mac_info.filter_type;
7268 mv_f[i].vlan_id = 0;
7272 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7273 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7274 vsi->vlan_num, &f->mac_info.mac_addr);
7275 if (ret != I40E_SUCCESS)
7277 for (j = i; j < i + vsi->vlan_num; j++)
7278 mv_f[j].filter_type = f->mac_info.filter_type;
7283 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7291 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7293 struct i40e_macvlan_filter *mv_f;
7295 int ret = I40E_SUCCESS;
7297 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7298 return I40E_ERR_PARAM;
7300 /* If it's already set, just return */
7301 if (i40e_find_vlan_filter(vsi,vlan))
7302 return I40E_SUCCESS;
7304 mac_num = vsi->mac_num;
7307 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7308 return I40E_ERR_PARAM;
7311 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7314 PMD_DRV_LOG(ERR, "failed to allocate memory");
7315 return I40E_ERR_NO_MEMORY;
7318 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7320 if (ret != I40E_SUCCESS)
7323 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7325 if (ret != I40E_SUCCESS)
7328 i40e_set_vlan_filter(vsi, vlan, 1);
7338 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7340 struct i40e_macvlan_filter *mv_f;
7342 int ret = I40E_SUCCESS;
7345 * Vlan 0 is the generic filter for untagged packets
7346 * and can't be removed.
7348 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7349 return I40E_ERR_PARAM;
7351 /* If can't find it, just return */
7352 if (!i40e_find_vlan_filter(vsi, vlan))
7353 return I40E_ERR_PARAM;
7355 mac_num = vsi->mac_num;
7358 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7359 return I40E_ERR_PARAM;
7362 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7365 PMD_DRV_LOG(ERR, "failed to allocate memory");
7366 return I40E_ERR_NO_MEMORY;
7369 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7371 if (ret != I40E_SUCCESS)
7374 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7376 if (ret != I40E_SUCCESS)
7379 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7380 if (vsi->vlan_num == 1) {
7381 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7382 if (ret != I40E_SUCCESS)
7385 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7386 if (ret != I40E_SUCCESS)
7390 i40e_set_vlan_filter(vsi, vlan, 0);
7400 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7402 struct i40e_mac_filter *f;
7403 struct i40e_macvlan_filter *mv_f;
7404 int i, vlan_num = 0;
7405 int ret = I40E_SUCCESS;
7407 /* If it's add and we've config it, return */
7408 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7410 return I40E_SUCCESS;
7411 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7412 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7415 * If vlan_num is 0, that's the first time to add mac,
7416 * set mask for vlan_id 0.
7418 if (vsi->vlan_num == 0) {
7419 i40e_set_vlan_filter(vsi, 0, 1);
7422 vlan_num = vsi->vlan_num;
7423 } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7424 mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7427 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7429 PMD_DRV_LOG(ERR, "failed to allocate memory");
7430 return I40E_ERR_NO_MEMORY;
7433 for (i = 0; i < vlan_num; i++) {
7434 mv_f[i].filter_type = mac_filter->filter_type;
7435 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7439 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7440 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7441 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7442 &mac_filter->mac_addr);
7443 if (ret != I40E_SUCCESS)
7447 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7448 if (ret != I40E_SUCCESS)
7451 /* Add the mac addr into mac list */
7452 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7454 PMD_DRV_LOG(ERR, "failed to allocate memory");
7455 ret = I40E_ERR_NO_MEMORY;
7458 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7460 f->mac_info.filter_type = mac_filter->filter_type;
7461 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7472 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7474 struct i40e_mac_filter *f;
7475 struct i40e_macvlan_filter *mv_f;
7477 enum i40e_mac_filter_type filter_type;
7478 int ret = I40E_SUCCESS;
7480 /* Can't find it, return an error */
7481 f = i40e_find_mac_filter(vsi, addr);
7483 return I40E_ERR_PARAM;
7485 vlan_num = vsi->vlan_num;
7486 filter_type = f->mac_info.filter_type;
7487 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7488 filter_type == I40E_MACVLAN_HASH_MATCH) {
7489 if (vlan_num == 0) {
7490 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7491 return I40E_ERR_PARAM;
7493 } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7494 filter_type == I40E_MAC_HASH_MATCH)
7497 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7499 PMD_DRV_LOG(ERR, "failed to allocate memory");
7500 return I40E_ERR_NO_MEMORY;
7503 for (i = 0; i < vlan_num; i++) {
7504 mv_f[i].filter_type = filter_type;
7505 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7508 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7509 filter_type == I40E_MACVLAN_HASH_MATCH) {
7510 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7511 if (ret != I40E_SUCCESS)
7515 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7516 if (ret != I40E_SUCCESS)
7519 /* Remove the mac addr into mac list */
7520 TAILQ_REMOVE(&vsi->mac_list, f, next);
7530 /* Configure hash enable flags for RSS */
7532 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7540 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7541 if (flags & (1ULL << i))
7542 hena |= adapter->pctypes_tbl[i];
7548 /* Parse the hash enable flags */
7550 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7552 uint64_t rss_hf = 0;
7558 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7559 if (flags & adapter->pctypes_tbl[i])
7560 rss_hf |= (1ULL << i);
7567 i40e_pf_disable_rss(struct i40e_pf *pf)
7569 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7571 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7572 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7573 I40E_WRITE_FLUSH(hw);
7577 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7579 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7580 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7581 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7582 I40E_VFQF_HKEY_MAX_INDEX :
7583 I40E_PFQF_HKEY_MAX_INDEX;
7585 if (!key || key_len == 0) {
7586 PMD_DRV_LOG(DEBUG, "No key to be configured");
7588 } else if (key_len != (key_idx + 1) *
7590 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7594 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7595 struct i40e_aqc_get_set_rss_key_data *key_dw =
7596 (struct i40e_aqc_get_set_rss_key_data *)key;
7597 enum i40e_status_code status =
7598 i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7602 "Failed to configure RSS key via AQ, error status: %d",
7607 uint32_t *hash_key = (uint32_t *)key;
7610 if (vsi->type == I40E_VSI_SRIOV) {
7611 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7614 I40E_VFQF_HKEY1(i, vsi->user_param),
7618 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7619 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7622 I40E_WRITE_FLUSH(hw);
7629 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7631 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7632 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7636 if (!key || !key_len)
7639 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7640 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7641 (struct i40e_aqc_get_set_rss_key_data *)key);
7643 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7647 uint32_t *key_dw = (uint32_t *)key;
7650 if (vsi->type == I40E_VSI_SRIOV) {
7651 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7652 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7653 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7655 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7658 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7659 reg = I40E_PFQF_HKEY(i);
7660 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7662 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7670 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7672 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7676 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7677 rss_conf->rss_key_len);
7681 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7682 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7683 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7684 I40E_WRITE_FLUSH(hw);
7690 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7691 struct rte_eth_rss_conf *rss_conf)
7693 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7694 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7695 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7698 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7699 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7701 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7702 if (rss_hf != 0) /* Enable RSS */
7704 return 0; /* Nothing to do */
7707 if (rss_hf == 0) /* Disable RSS */
7710 return i40e_hw_rss_hash_set(pf, rss_conf);
7714 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7715 struct rte_eth_rss_conf *rss_conf)
7717 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7718 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7725 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7726 &rss_conf->rss_key_len);
7730 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7731 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7732 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7738 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7740 switch (filter_type) {
7741 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7742 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7744 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7745 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7747 case RTE_TUNNEL_FILTER_IMAC_TENID:
7748 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7750 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7751 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7753 case ETH_TUNNEL_FILTER_IMAC:
7754 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7756 case ETH_TUNNEL_FILTER_OIP:
7757 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7759 case ETH_TUNNEL_FILTER_IIP:
7760 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7763 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7770 /* Convert tunnel filter structure */
7772 i40e_tunnel_filter_convert(
7773 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7774 struct i40e_tunnel_filter *tunnel_filter)
7776 rte_ether_addr_copy((struct rte_ether_addr *)
7777 &cld_filter->element.outer_mac,
7778 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7779 rte_ether_addr_copy((struct rte_ether_addr *)
7780 &cld_filter->element.inner_mac,
7781 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7782 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7783 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7784 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7785 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7786 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7788 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7789 tunnel_filter->input.flags = cld_filter->element.flags;
7790 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7791 tunnel_filter->queue = cld_filter->element.queue_number;
7792 rte_memcpy(tunnel_filter->input.general_fields,
7793 cld_filter->general_fields,
7794 sizeof(cld_filter->general_fields));
7799 /* Check if there exists the tunnel filter */
7800 struct i40e_tunnel_filter *
7801 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7802 const struct i40e_tunnel_filter_input *input)
7806 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7810 return tunnel_rule->hash_map[ret];
7813 /* Add a tunnel filter into the SW list */
7815 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7816 struct i40e_tunnel_filter *tunnel_filter)
7818 struct i40e_tunnel_rule *rule = &pf->tunnel;
7821 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7824 "Failed to insert tunnel filter to hash table %d!",
7828 rule->hash_map[ret] = tunnel_filter;
7830 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7835 /* Delete a tunnel filter from the SW list */
7837 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7838 struct i40e_tunnel_filter_input *input)
7840 struct i40e_tunnel_rule *rule = &pf->tunnel;
7841 struct i40e_tunnel_filter *tunnel_filter;
7844 ret = rte_hash_del_key(rule->hash_table, input);
7847 "Failed to delete tunnel filter to hash table %d!",
7851 tunnel_filter = rule->hash_map[ret];
7852 rule->hash_map[ret] = NULL;
7854 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7855 rte_free(tunnel_filter);
7860 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7861 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7862 #define I40E_TR_GENEVE_KEY_MASK 0x8
7863 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7864 #define I40E_TR_GRE_KEY_MASK 0x400
7865 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7866 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7867 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7868 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7869 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7870 #define I40E_DIRECTION_INGRESS_KEY 0x8000
7871 #define I40E_TR_L4_TYPE_TCP 0x2
7872 #define I40E_TR_L4_TYPE_UDP 0x4
7873 #define I40E_TR_L4_TYPE_SCTP 0x8
7876 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7878 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7879 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7880 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7881 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7882 enum i40e_status_code status = I40E_SUCCESS;
7884 if (pf->support_multi_driver) {
7885 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7886 return I40E_NOT_SUPPORTED;
7889 memset(&filter_replace, 0,
7890 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7891 memset(&filter_replace_buf, 0,
7892 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7894 /* create L1 filter */
7895 filter_replace.old_filter_type =
7896 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7897 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7898 filter_replace.tr_bit = 0;
7900 /* Prepare the buffer, 3 entries */
7901 filter_replace_buf.data[0] =
7902 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7903 filter_replace_buf.data[0] |=
7904 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7905 filter_replace_buf.data[2] = 0xFF;
7906 filter_replace_buf.data[3] = 0xFF;
7907 filter_replace_buf.data[4] =
7908 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7909 filter_replace_buf.data[4] |=
7910 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7911 filter_replace_buf.data[7] = 0xF0;
7912 filter_replace_buf.data[8]
7913 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7914 filter_replace_buf.data[8] |=
7915 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7916 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7917 I40E_TR_GENEVE_KEY_MASK |
7918 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7919 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7920 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7921 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7923 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7924 &filter_replace_buf);
7925 if (!status && (filter_replace.old_filter_type !=
7926 filter_replace.new_filter_type))
7927 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7928 " original: 0x%x, new: 0x%x",
7930 filter_replace.old_filter_type,
7931 filter_replace.new_filter_type);
7937 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7939 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7940 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7941 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7942 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7943 enum i40e_status_code status = I40E_SUCCESS;
7945 if (pf->support_multi_driver) {
7946 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7947 return I40E_NOT_SUPPORTED;
7951 memset(&filter_replace, 0,
7952 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7953 memset(&filter_replace_buf, 0,
7954 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7955 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7956 I40E_AQC_MIRROR_CLOUD_FILTER;
7957 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7958 filter_replace.new_filter_type =
7959 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7960 /* Prepare the buffer, 2 entries */
7961 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7962 filter_replace_buf.data[0] |=
7963 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7964 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7965 filter_replace_buf.data[4] |=
7966 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7967 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7968 &filter_replace_buf);
7971 if (filter_replace.old_filter_type !=
7972 filter_replace.new_filter_type)
7973 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7974 " original: 0x%x, new: 0x%x",
7976 filter_replace.old_filter_type,
7977 filter_replace.new_filter_type);
7980 memset(&filter_replace, 0,
7981 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7982 memset(&filter_replace_buf, 0,
7983 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7985 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7986 I40E_AQC_MIRROR_CLOUD_FILTER;
7987 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7988 filter_replace.new_filter_type =
7989 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7990 /* Prepare the buffer, 2 entries */
7991 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7992 filter_replace_buf.data[0] |=
7993 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7994 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7995 filter_replace_buf.data[4] |=
7996 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7998 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7999 &filter_replace_buf);
8000 if (!status && (filter_replace.old_filter_type !=
8001 filter_replace.new_filter_type))
8002 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8003 " original: 0x%x, new: 0x%x",
8005 filter_replace.old_filter_type,
8006 filter_replace.new_filter_type);
8011 static enum i40e_status_code
8012 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8014 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8015 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8016 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8017 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8018 enum i40e_status_code status = I40E_SUCCESS;
8020 if (pf->support_multi_driver) {
8021 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8022 return I40E_NOT_SUPPORTED;
8026 memset(&filter_replace, 0,
8027 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8028 memset(&filter_replace_buf, 0,
8029 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8030 /* create L1 filter */
8031 filter_replace.old_filter_type =
8032 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8033 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8034 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8035 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8036 /* Prepare the buffer, 2 entries */
8037 filter_replace_buf.data[0] =
8038 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8039 filter_replace_buf.data[0] |=
8040 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8041 filter_replace_buf.data[2] = 0xFF;
8042 filter_replace_buf.data[3] = 0xFF;
8043 filter_replace_buf.data[4] =
8044 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8045 filter_replace_buf.data[4] |=
8046 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8047 filter_replace_buf.data[6] = 0xFF;
8048 filter_replace_buf.data[7] = 0xFF;
8049 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8050 &filter_replace_buf);
8053 if (filter_replace.old_filter_type !=
8054 filter_replace.new_filter_type)
8055 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8056 " original: 0x%x, new: 0x%x",
8058 filter_replace.old_filter_type,
8059 filter_replace.new_filter_type);
8062 memset(&filter_replace, 0,
8063 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8064 memset(&filter_replace_buf, 0,
8065 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8066 /* create L1 filter */
8067 filter_replace.old_filter_type =
8068 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8069 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8070 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8071 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8072 /* Prepare the buffer, 2 entries */
8073 filter_replace_buf.data[0] =
8074 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8075 filter_replace_buf.data[0] |=
8076 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8077 filter_replace_buf.data[2] = 0xFF;
8078 filter_replace_buf.data[3] = 0xFF;
8079 filter_replace_buf.data[4] =
8080 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8081 filter_replace_buf.data[4] |=
8082 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8083 filter_replace_buf.data[6] = 0xFF;
8084 filter_replace_buf.data[7] = 0xFF;
8086 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8087 &filter_replace_buf);
8088 if (!status && (filter_replace.old_filter_type !=
8089 filter_replace.new_filter_type))
8090 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8091 " original: 0x%x, new: 0x%x",
8093 filter_replace.old_filter_type,
8094 filter_replace.new_filter_type);
8100 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8102 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8103 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8104 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8105 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8106 enum i40e_status_code status = I40E_SUCCESS;
8108 if (pf->support_multi_driver) {
8109 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8110 return I40E_NOT_SUPPORTED;
8114 memset(&filter_replace, 0,
8115 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8116 memset(&filter_replace_buf, 0,
8117 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8118 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8119 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8120 filter_replace.new_filter_type =
8121 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8122 /* Prepare the buffer, 2 entries */
8123 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8124 filter_replace_buf.data[0] |=
8125 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8126 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8127 filter_replace_buf.data[4] |=
8128 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8129 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8130 &filter_replace_buf);
8133 if (filter_replace.old_filter_type !=
8134 filter_replace.new_filter_type)
8135 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8136 " original: 0x%x, new: 0x%x",
8138 filter_replace.old_filter_type,
8139 filter_replace.new_filter_type);
8142 memset(&filter_replace, 0,
8143 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8144 memset(&filter_replace_buf, 0,
8145 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8146 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8147 filter_replace.old_filter_type =
8148 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8149 filter_replace.new_filter_type =
8150 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8151 /* Prepare the buffer, 2 entries */
8152 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8153 filter_replace_buf.data[0] |=
8154 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8155 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8156 filter_replace_buf.data[4] |=
8157 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8159 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8160 &filter_replace_buf);
8161 if (!status && (filter_replace.old_filter_type !=
8162 filter_replace.new_filter_type))
8163 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8164 " original: 0x%x, new: 0x%x",
8166 filter_replace.old_filter_type,
8167 filter_replace.new_filter_type);
8172 static enum i40e_status_code
8173 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8174 enum i40e_l4_port_type l4_port_type)
8176 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8177 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8178 enum i40e_status_code status = I40E_SUCCESS;
8179 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8180 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8182 if (pf->support_multi_driver) {
8183 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8184 return I40E_NOT_SUPPORTED;
8187 memset(&filter_replace, 0,
8188 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8189 memset(&filter_replace_buf, 0,
8190 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8192 /* create L1 filter */
8193 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8194 filter_replace.old_filter_type =
8195 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8196 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8197 filter_replace_buf.data[8] =
8198 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8200 filter_replace.old_filter_type =
8201 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8202 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8203 filter_replace_buf.data[8] =
8204 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8207 filter_replace.tr_bit = 0;
8208 /* Prepare the buffer, 3 entries */
8209 filter_replace_buf.data[0] =
8210 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8211 filter_replace_buf.data[0] |=
8212 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8213 filter_replace_buf.data[2] = 0x00;
8214 filter_replace_buf.data[3] =
8215 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8216 filter_replace_buf.data[4] =
8217 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8218 filter_replace_buf.data[4] |=
8219 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8220 filter_replace_buf.data[5] = 0x00;
8221 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8222 I40E_TR_L4_TYPE_TCP |
8223 I40E_TR_L4_TYPE_SCTP;
8224 filter_replace_buf.data[7] = 0x00;
8225 filter_replace_buf.data[8] |=
8226 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8227 filter_replace_buf.data[9] = 0x00;
8228 filter_replace_buf.data[10] = 0xFF;
8229 filter_replace_buf.data[11] = 0xFF;
8231 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8232 &filter_replace_buf);
8233 if (!status && filter_replace.old_filter_type !=
8234 filter_replace.new_filter_type)
8235 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8236 " original: 0x%x, new: 0x%x",
8238 filter_replace.old_filter_type,
8239 filter_replace.new_filter_type);
8244 static enum i40e_status_code
8245 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8246 enum i40e_l4_port_type l4_port_type)
8248 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8249 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8250 enum i40e_status_code status = I40E_SUCCESS;
8251 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8252 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8254 if (pf->support_multi_driver) {
8255 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8256 return I40E_NOT_SUPPORTED;
8259 memset(&filter_replace, 0,
8260 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8261 memset(&filter_replace_buf, 0,
8262 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8264 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8265 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8266 filter_replace.new_filter_type =
8267 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8268 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8270 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8271 filter_replace.new_filter_type =
8272 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8273 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8276 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8277 filter_replace.tr_bit = 0;
8278 /* Prepare the buffer, 2 entries */
8279 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8280 filter_replace_buf.data[0] |=
8281 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8282 filter_replace_buf.data[4] |=
8283 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8284 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8285 &filter_replace_buf);
8287 if (!status && filter_replace.old_filter_type !=
8288 filter_replace.new_filter_type)
8289 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8290 " original: 0x%x, new: 0x%x",
8292 filter_replace.old_filter_type,
8293 filter_replace.new_filter_type);
8299 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8300 struct i40e_tunnel_filter_conf *tunnel_filter,
8304 uint32_t ipv4_addr, ipv4_addr_le;
8305 uint8_t i, tun_type = 0;
8306 /* internal variable to convert ipv6 byte order */
8307 uint32_t convert_ipv6[4];
8309 struct i40e_pf_vf *vf = NULL;
8310 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8311 struct i40e_vsi *vsi;
8312 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8313 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8314 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8315 struct i40e_tunnel_filter *tunnel, *node;
8316 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8318 bool big_buffer = 0;
8320 cld_filter = rte_zmalloc("tunnel_filter",
8321 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8324 if (cld_filter == NULL) {
8325 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8328 pfilter = cld_filter;
8330 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8331 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8332 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8333 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8335 pfilter->element.inner_vlan =
8336 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8337 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8338 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8339 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8340 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8341 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8343 sizeof(pfilter->element.ipaddr.v4.data));
8345 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8346 for (i = 0; i < 4; i++) {
8348 rte_cpu_to_le_32(rte_be_to_cpu_32(
8349 tunnel_filter->ip_addr.ipv6_addr[i]));
8351 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8353 sizeof(pfilter->element.ipaddr.v6.data));
8356 /* check tunneled type */
8357 switch (tunnel_filter->tunnel_type) {
8358 case I40E_TUNNEL_TYPE_VXLAN:
8359 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8361 case I40E_TUNNEL_TYPE_NVGRE:
8362 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8364 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8365 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8367 case I40E_TUNNEL_TYPE_MPLSoUDP:
8368 if (!pf->mpls_replace_flag) {
8369 i40e_replace_mpls_l1_filter(pf);
8370 i40e_replace_mpls_cloud_filter(pf);
8371 pf->mpls_replace_flag = 1;
8373 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8374 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8376 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8377 (teid_le & 0xF) << 12;
8378 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8381 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8383 case I40E_TUNNEL_TYPE_MPLSoGRE:
8384 if (!pf->mpls_replace_flag) {
8385 i40e_replace_mpls_l1_filter(pf);
8386 i40e_replace_mpls_cloud_filter(pf);
8387 pf->mpls_replace_flag = 1;
8389 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8390 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8392 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8393 (teid_le & 0xF) << 12;
8394 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8397 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8399 case I40E_TUNNEL_TYPE_GTPC:
8400 if (!pf->gtp_replace_flag) {
8401 i40e_replace_gtp_l1_filter(pf);
8402 i40e_replace_gtp_cloud_filter(pf);
8403 pf->gtp_replace_flag = 1;
8405 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8406 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8407 (teid_le >> 16) & 0xFFFF;
8408 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8410 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8414 case I40E_TUNNEL_TYPE_GTPU:
8415 if (!pf->gtp_replace_flag) {
8416 i40e_replace_gtp_l1_filter(pf);
8417 i40e_replace_gtp_cloud_filter(pf);
8418 pf->gtp_replace_flag = 1;
8420 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8421 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8422 (teid_le >> 16) & 0xFFFF;
8423 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8425 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8429 case I40E_TUNNEL_TYPE_QINQ:
8430 if (!pf->qinq_replace_flag) {
8431 ret = i40e_cloud_filter_qinq_create(pf);
8434 "QinQ tunnel filter already created.");
8435 pf->qinq_replace_flag = 1;
8437 /* Add in the General fields the values of
8438 * the Outer and Inner VLAN
8439 * Big Buffer should be set, see changes in
8440 * i40e_aq_add_cloud_filters
8442 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8443 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8446 case I40E_CLOUD_TYPE_UDP:
8447 case I40E_CLOUD_TYPE_TCP:
8448 case I40E_CLOUD_TYPE_SCTP:
8449 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8450 if (!pf->sport_replace_flag) {
8451 i40e_replace_port_l1_filter(pf,
8452 tunnel_filter->l4_port_type);
8453 i40e_replace_port_cloud_filter(pf,
8454 tunnel_filter->l4_port_type);
8455 pf->sport_replace_flag = 1;
8457 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8458 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8459 I40E_DIRECTION_INGRESS_KEY;
8461 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8462 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8463 I40E_TR_L4_TYPE_UDP;
8464 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8465 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8466 I40E_TR_L4_TYPE_TCP;
8468 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8469 I40E_TR_L4_TYPE_SCTP;
8471 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8472 (teid_le >> 16) & 0xFFFF;
8475 if (!pf->dport_replace_flag) {
8476 i40e_replace_port_l1_filter(pf,
8477 tunnel_filter->l4_port_type);
8478 i40e_replace_port_cloud_filter(pf,
8479 tunnel_filter->l4_port_type);
8480 pf->dport_replace_flag = 1;
8482 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8483 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8484 I40E_DIRECTION_INGRESS_KEY;
8486 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8487 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8488 I40E_TR_L4_TYPE_UDP;
8489 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8490 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8491 I40E_TR_L4_TYPE_TCP;
8493 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8494 I40E_TR_L4_TYPE_SCTP;
8496 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8497 (teid_le >> 16) & 0xFFFF;
8503 /* Other tunnel types is not supported. */
8504 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8505 rte_free(cld_filter);
8509 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8510 pfilter->element.flags =
8511 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8512 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8513 pfilter->element.flags =
8514 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8515 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8516 pfilter->element.flags =
8517 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8518 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8519 pfilter->element.flags =
8520 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8521 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8522 pfilter->element.flags |=
8523 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8524 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8525 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8526 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8527 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8528 pfilter->element.flags |=
8529 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8531 pfilter->element.flags |=
8532 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8534 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8535 &pfilter->element.flags);
8537 rte_free(cld_filter);
8542 pfilter->element.flags |= rte_cpu_to_le_16(
8543 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8544 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8545 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8546 pfilter->element.queue_number =
8547 rte_cpu_to_le_16(tunnel_filter->queue_id);
8549 if (!tunnel_filter->is_to_vf)
8552 if (tunnel_filter->vf_id >= pf->vf_num) {
8553 PMD_DRV_LOG(ERR, "Invalid argument.");
8554 rte_free(cld_filter);
8557 vf = &pf->vfs[tunnel_filter->vf_id];
8561 /* Check if there is the filter in SW list */
8562 memset(&check_filter, 0, sizeof(check_filter));
8563 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8564 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8565 check_filter.vf_id = tunnel_filter->vf_id;
8566 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8568 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8569 rte_free(cld_filter);
8573 if (!add && !node) {
8574 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8575 rte_free(cld_filter);
8581 ret = i40e_aq_add_cloud_filters_bb(hw,
8582 vsi->seid, cld_filter, 1);
8584 ret = i40e_aq_add_cloud_filters(hw,
8585 vsi->seid, &cld_filter->element, 1);
8587 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8588 rte_free(cld_filter);
8591 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8592 if (tunnel == NULL) {
8593 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8594 rte_free(cld_filter);
8598 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8599 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8604 ret = i40e_aq_rem_cloud_filters_bb(
8605 hw, vsi->seid, cld_filter, 1);
8607 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8608 &cld_filter->element, 1);
8610 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8611 rte_free(cld_filter);
8614 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8617 rte_free(cld_filter);
8622 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8626 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8627 if (pf->vxlan_ports[i] == port)
8635 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8638 uint8_t filter_idx = 0;
8639 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8641 idx = i40e_get_vxlan_port_idx(pf, port);
8643 /* Check if port already exists */
8645 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8649 /* Now check if there is space to add the new port */
8650 idx = i40e_get_vxlan_port_idx(pf, 0);
8653 "Maximum number of UDP ports reached, not adding port %d",
8658 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8661 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8665 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8668 /* New port: add it and mark its index in the bitmap */
8669 pf->vxlan_ports[idx] = port;
8670 pf->vxlan_bitmap |= (1 << idx);
8672 if (!(pf->flags & I40E_FLAG_VXLAN))
8673 pf->flags |= I40E_FLAG_VXLAN;
8679 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8682 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8684 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8685 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8689 idx = i40e_get_vxlan_port_idx(pf, port);
8692 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8696 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8697 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8701 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8704 pf->vxlan_ports[idx] = 0;
8705 pf->vxlan_bitmap &= ~(1 << idx);
8707 if (!pf->vxlan_bitmap)
8708 pf->flags &= ~I40E_FLAG_VXLAN;
8713 /* Add UDP tunneling port */
8715 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8716 struct rte_eth_udp_tunnel *udp_tunnel)
8719 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8721 if (udp_tunnel == NULL)
8724 switch (udp_tunnel->prot_type) {
8725 case RTE_TUNNEL_TYPE_VXLAN:
8726 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8727 I40E_AQC_TUNNEL_TYPE_VXLAN);
8729 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8730 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8731 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8733 case RTE_TUNNEL_TYPE_GENEVE:
8734 case RTE_TUNNEL_TYPE_TEREDO:
8735 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8740 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8748 /* Remove UDP tunneling port */
8750 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8751 struct rte_eth_udp_tunnel *udp_tunnel)
8754 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8756 if (udp_tunnel == NULL)
8759 switch (udp_tunnel->prot_type) {
8760 case RTE_TUNNEL_TYPE_VXLAN:
8761 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8762 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8764 case RTE_TUNNEL_TYPE_GENEVE:
8765 case RTE_TUNNEL_TYPE_TEREDO:
8766 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8770 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8778 /* Calculate the maximum number of contiguous PF queues that are configured */
8780 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8782 struct rte_eth_dev_data *data = pf->dev_data;
8784 struct i40e_rx_queue *rxq;
8787 for (i = 0; i < pf->lan_nb_qps; i++) {
8788 rxq = data->rx_queues[i];
8789 if (rxq && rxq->q_set)
8798 /* Reset the global configure of hash function and input sets */
8800 i40e_pf_global_rss_reset(struct i40e_pf *pf)
8802 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8803 uint32_t reg, reg_val;
8806 /* Reset global RSS function sets */
8807 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8808 if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
8809 reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
8810 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
8813 for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
8817 if (hw->mac.type == I40E_MAC_X722)
8818 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
8822 /* Reset pctype insets */
8823 inset = i40e_get_default_input_set(i);
8825 pf->hash_input_set[pctype] = inset;
8826 inset = i40e_translate_input_set_reg(hw->mac.type,
8829 reg = I40E_GLQF_HASH_INSET(0, pctype);
8830 i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
8831 reg = I40E_GLQF_HASH_INSET(1, pctype);
8832 i40e_check_write_global_reg(hw, reg,
8833 (uint32_t)(inset >> 32));
8835 /* Clear unused mask registers of the pctype */
8836 for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
8837 reg = I40E_GLQF_HASH_MSK(j, pctype);
8838 i40e_check_write_global_reg(hw, reg, 0);
8842 /* Reset pctype symmetric sets */
8843 reg = I40E_GLQF_HSYM(pctype);
8844 reg_val = i40e_read_rx_ctl(hw, reg);
8845 if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8846 reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
8847 i40e_write_global_rx_ctl(hw, reg, reg_val);
8850 I40E_WRITE_FLUSH(hw);
8854 i40e_pf_reset_rss_reta(struct i40e_pf *pf)
8856 struct i40e_hw *hw = &pf->adapter->hw;
8857 uint8_t lut[ETH_RSS_RETA_SIZE_512];
8861 /* If both VMDQ and RSS enabled, not all of PF queues are
8862 * configured. It's necessary to calculate the actual PF
8863 * queues that are configured.
8865 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8866 num = i40e_pf_calc_configured_queues_num(pf);
8868 num = pf->dev_data->nb_rx_queues;
8870 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8874 for (i = 0; i < hw->func_caps.rss_table_size; i++)
8875 lut[i] = (uint8_t)(i % (uint32_t)num);
8877 return i40e_set_rss_lut(pf->main_vsi, lut, (uint16_t)i);
8881 i40e_pf_reset_rss_key(struct i40e_pf *pf)
8883 const uint8_t key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8888 rss_key = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key;
8890 pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key_len < key_len) {
8891 static uint32_t rss_key_default[] = {0x6b793944,
8892 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8893 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8894 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8896 rss_key = (uint8_t *)rss_key_default;
8899 return i40e_set_rss_key(pf->main_vsi, rss_key, key_len);
8903 i40e_pf_rss_reset(struct i40e_pf *pf)
8905 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8909 pf->hash_filter_enabled = 0;
8910 i40e_pf_disable_rss(pf);
8911 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8913 if (!pf->support_multi_driver)
8914 i40e_pf_global_rss_reset(pf);
8916 /* Reset RETA table */
8917 if (pf->adapter->rss_reta_updated == 0) {
8918 ret = i40e_pf_reset_rss_reta(pf);
8923 return i40e_pf_reset_rss_key(pf);
8928 i40e_pf_config_rss(struct i40e_pf *pf)
8931 enum rte_eth_rx_mq_mode mq_mode;
8932 uint64_t rss_hf, hena;
8935 ret = i40e_pf_rss_reset(pf);
8937 PMD_DRV_LOG(ERR, "Reset RSS failed, RSS has been disabled");
8941 rss_hf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
8942 mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8943 if (!(rss_hf & pf->adapter->flow_types_mask) ||
8944 !(mq_mode & ETH_MQ_RX_RSS_FLAG))
8947 hw = I40E_PF_TO_HW(pf);
8948 hena = i40e_config_hena(pf->adapter, rss_hf);
8949 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
8950 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
8951 I40E_WRITE_FLUSH(hw);
8956 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8957 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8959 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8961 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8965 if (pf->support_multi_driver) {
8966 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8970 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8971 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8974 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8975 } else if (len == 4) {
8976 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8978 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8983 ret = i40e_aq_debug_write_global_register(hw,
8984 I40E_GL_PRS_FVBM(2),
8988 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8989 "with value 0x%08x",
8990 I40E_GL_PRS_FVBM(2), reg);
8994 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8995 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9000 /* Set the symmetric hash enable configurations per port */
9002 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9004 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9007 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)
9010 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9012 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK))
9015 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9017 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9018 I40E_WRITE_FLUSH(hw);
9022 * Valid input sets for hash and flow director filters per PCTYPE
9025 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9026 enum rte_filter_type filter)
9030 static const uint64_t valid_hash_inset_table[] = {
9031 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9032 I40E_INSET_DMAC | I40E_INSET_SMAC |
9033 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9034 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9035 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9036 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9037 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9038 I40E_INSET_FLEX_PAYLOAD,
9039 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9040 I40E_INSET_DMAC | I40E_INSET_SMAC |
9041 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9042 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9043 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9044 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9045 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9046 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9047 I40E_INSET_FLEX_PAYLOAD,
9048 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9049 I40E_INSET_DMAC | I40E_INSET_SMAC |
9050 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9051 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9052 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9053 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9054 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9055 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9056 I40E_INSET_FLEX_PAYLOAD,
9057 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9058 I40E_INSET_DMAC | I40E_INSET_SMAC |
9059 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9060 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9061 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9062 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9063 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9064 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9065 I40E_INSET_FLEX_PAYLOAD,
9066 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9067 I40E_INSET_DMAC | I40E_INSET_SMAC |
9068 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9069 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9070 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9071 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9072 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9073 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9074 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9075 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9076 I40E_INSET_DMAC | I40E_INSET_SMAC |
9077 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9078 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9079 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9080 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9081 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9082 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9083 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9084 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9085 I40E_INSET_DMAC | I40E_INSET_SMAC |
9086 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9087 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9088 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9089 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9090 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9091 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9092 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9093 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9094 I40E_INSET_DMAC | I40E_INSET_SMAC |
9095 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9096 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9097 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9098 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9099 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9100 I40E_INSET_FLEX_PAYLOAD,
9101 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9102 I40E_INSET_DMAC | I40E_INSET_SMAC |
9103 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9104 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9105 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9106 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9107 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9108 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9109 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9110 I40E_INSET_DMAC | I40E_INSET_SMAC |
9111 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9112 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9113 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9114 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9115 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9116 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9117 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9118 I40E_INSET_DMAC | I40E_INSET_SMAC |
9119 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9120 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9121 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9122 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9123 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9124 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9125 I40E_INSET_FLEX_PAYLOAD,
9126 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9127 I40E_INSET_DMAC | I40E_INSET_SMAC |
9128 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9129 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9130 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9131 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9132 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9133 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9134 I40E_INSET_FLEX_PAYLOAD,
9135 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9136 I40E_INSET_DMAC | I40E_INSET_SMAC |
9137 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9138 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9139 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9140 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9141 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9142 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9143 I40E_INSET_FLEX_PAYLOAD,
9144 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9145 I40E_INSET_DMAC | I40E_INSET_SMAC |
9146 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9147 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9148 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9149 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9150 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9151 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9152 I40E_INSET_FLEX_PAYLOAD,
9153 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9154 I40E_INSET_DMAC | I40E_INSET_SMAC |
9155 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9156 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9157 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9158 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9159 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9160 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9161 I40E_INSET_FLEX_PAYLOAD,
9162 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9163 I40E_INSET_DMAC | I40E_INSET_SMAC |
9164 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9165 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9166 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9167 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9168 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9169 I40E_INSET_FLEX_PAYLOAD,
9170 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9171 I40E_INSET_DMAC | I40E_INSET_SMAC |
9172 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9173 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9174 I40E_INSET_FLEX_PAYLOAD,
9178 * Flow director supports only fields defined in
9179 * union rte_eth_fdir_flow.
9181 static const uint64_t valid_fdir_inset_table[] = {
9182 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9183 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9184 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9185 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9186 I40E_INSET_IPV4_TTL,
9187 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9188 I40E_INSET_DMAC | I40E_INSET_SMAC |
9189 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9190 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9191 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9192 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9193 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9194 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9195 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9196 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9197 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9198 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9199 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9200 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9201 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9202 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9203 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9204 I40E_INSET_DMAC | I40E_INSET_SMAC |
9205 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9206 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9207 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9208 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9209 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9210 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9211 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9212 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9213 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9214 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9215 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9216 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9217 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9218 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9220 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9221 I40E_INSET_DMAC | I40E_INSET_SMAC |
9222 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9223 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9224 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9225 I40E_INSET_IPV4_TTL,
9226 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9227 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9228 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9229 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9230 I40E_INSET_IPV6_HOP_LIMIT,
9231 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9232 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9233 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9234 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9235 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9236 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9237 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9238 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9239 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9240 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9241 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9242 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9243 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9244 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9245 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9246 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9247 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9248 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9249 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9250 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9251 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9252 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9253 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9254 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9255 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9256 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9257 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9258 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9259 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9260 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9262 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9263 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9264 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9265 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9266 I40E_INSET_IPV6_HOP_LIMIT,
9267 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9268 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9269 I40E_INSET_LAST_ETHER_TYPE,
9272 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9274 if (filter == RTE_ETH_FILTER_HASH)
9275 valid = valid_hash_inset_table[pctype];
9277 valid = valid_fdir_inset_table[pctype];
9283 * Validate if the input set is allowed for a specific PCTYPE
9286 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9287 enum rte_filter_type filter, uint64_t inset)
9291 valid = i40e_get_valid_input_set(pctype, filter);
9292 if (inset & (~valid))
9298 /* default input set fields combination per pctype */
9300 i40e_get_default_input_set(uint16_t pctype)
9302 static const uint64_t default_inset_table[] = {
9303 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9304 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9305 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9306 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9307 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9308 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9309 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9310 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9311 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9312 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9313 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9314 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9315 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9316 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9317 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9318 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9319 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9320 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9321 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9322 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9324 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9325 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9326 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9327 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9328 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9329 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9330 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9331 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9332 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9333 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9334 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9335 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9336 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9337 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9338 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9339 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9340 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9341 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9342 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9343 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9344 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9345 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9347 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9348 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9349 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9350 I40E_INSET_LAST_ETHER_TYPE,
9353 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9356 return default_inset_table[pctype];
9360 * Translate the input set from bit masks to register aware bit masks
9364 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9374 static const struct inset_map inset_map_common[] = {
9375 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9376 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9377 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9378 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9379 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9380 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9381 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9382 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9383 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9384 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9385 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9386 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9387 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9388 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9389 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9390 {I40E_INSET_TUNNEL_DMAC,
9391 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9392 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9393 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9394 {I40E_INSET_TUNNEL_SRC_PORT,
9395 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9396 {I40E_INSET_TUNNEL_DST_PORT,
9397 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9398 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9399 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9400 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9401 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9402 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9403 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9404 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9405 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9406 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9409 /* some different registers map in x722*/
9410 static const struct inset_map inset_map_diff_x722[] = {
9411 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9412 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9413 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9414 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9417 static const struct inset_map inset_map_diff_not_x722[] = {
9418 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9419 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9420 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9421 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9427 /* Translate input set to register aware inset */
9428 if (type == I40E_MAC_X722) {
9429 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9430 if (input & inset_map_diff_x722[i].inset)
9431 val |= inset_map_diff_x722[i].inset_reg;
9434 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9435 if (input & inset_map_diff_not_x722[i].inset)
9436 val |= inset_map_diff_not_x722[i].inset_reg;
9440 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9441 if (input & inset_map_common[i].inset)
9442 val |= inset_map_common[i].inset_reg;
9449 i40e_get_inset_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
9450 uint32_t pit_reg_count, uint32_t hdr_off)
9452 const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
9453 uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
9454 uint32_t i, reg_val, src_off, count;
9456 for (i = pit_reg_start; i < pit_reg_end; i++) {
9457 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
9459 src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
9460 count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
9462 if (src_off <= field_off && (src_off + count) > field_off)
9466 if (i >= pit_reg_end) {
9468 "Hardware GLQF_PIT configuration does not support this field mask");
9472 return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
9476 i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
9477 uint32_t *mask, uint8_t nb_elem)
9479 static const uint64_t mask_inset[] = {
9480 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
9481 I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
9483 static const struct {
9487 } inset_mask_offset_map[] = {
9488 { I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
9489 offsetof(struct rte_ipv4_hdr, type_of_service) },
9491 { I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
9492 offsetof(struct rte_ipv4_hdr, next_proto_id) },
9494 { I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
9495 offsetof(struct rte_ipv4_hdr, time_to_live) },
9497 { I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
9498 offsetof(struct rte_ipv6_hdr, vtc_flow) },
9500 { I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
9501 offsetof(struct rte_ipv6_hdr, proto) },
9503 { I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
9504 offsetof(struct rte_ipv6_hdr, hop_limits) },
9514 for (i = 0; i < RTE_DIM(mask_inset); i++) {
9515 /* Clear the inset bit, if no MASK is required,
9516 * for example proto + ttl
9518 if ((mask_inset[i] & inset) == mask_inset[i]) {
9519 inset &= ~mask_inset[i];
9525 for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
9526 uint32_t pit_start, pit_count;
9529 if (!(inset_mask_offset_map[i].inset & inset))
9532 if (inset_mask_offset_map[i].inset &
9533 (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9534 I40E_INSET_IPV4_TTL)) {
9535 pit_start = I40E_GLQF_PIT_IPV4_START;
9536 pit_count = I40E_GLQF_PIT_IPV4_COUNT;
9538 pit_start = I40E_GLQF_PIT_IPV6_START;
9539 pit_count = I40E_GLQF_PIT_IPV6_COUNT;
9542 offset = i40e_get_inset_field_offset(hw, pit_start, pit_count,
9543 inset_mask_offset_map[i].offset);
9548 if (idx >= nb_elem) {
9550 "Configuration of inset mask out of range %u",
9555 mask[idx] = I40E_GLQF_PIT_BUILD((uint32_t)offset,
9556 inset_mask_offset_map[i].mask);
9564 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9566 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9568 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9570 i40e_write_rx_ctl(hw, addr, val);
9571 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9572 (uint32_t)i40e_read_rx_ctl(hw, addr));
9576 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9578 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9579 struct rte_eth_dev *dev;
9581 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9583 i40e_write_rx_ctl(hw, addr, val);
9584 PMD_DRV_LOG(WARNING,
9585 "i40e device %s changed global register [0x%08x]."
9586 " original: 0x%08x, new: 0x%08x",
9587 dev->device->name, addr, reg,
9588 (uint32_t)i40e_read_rx_ctl(hw, addr));
9593 i40e_filter_input_set_init(struct i40e_pf *pf)
9595 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9596 enum i40e_filter_pctype pctype;
9597 uint64_t input_set, inset_reg;
9598 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9602 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9603 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9604 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9606 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9609 input_set = i40e_get_default_input_set(pctype);
9611 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9612 I40E_INSET_MASK_NUM_REG);
9615 if (pf->support_multi_driver && num > 0) {
9616 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9619 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9622 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9623 (uint32_t)(inset_reg & UINT32_MAX));
9624 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9625 (uint32_t)((inset_reg >>
9626 I40E_32_BIT_WIDTH) & UINT32_MAX));
9627 if (!pf->support_multi_driver) {
9628 i40e_check_write_global_reg(hw,
9629 I40E_GLQF_HASH_INSET(0, pctype),
9630 (uint32_t)(inset_reg & UINT32_MAX));
9631 i40e_check_write_global_reg(hw,
9632 I40E_GLQF_HASH_INSET(1, pctype),
9633 (uint32_t)((inset_reg >>
9634 I40E_32_BIT_WIDTH) & UINT32_MAX));
9636 for (i = 0; i < num; i++) {
9637 i40e_check_write_global_reg(hw,
9638 I40E_GLQF_FD_MSK(i, pctype),
9640 i40e_check_write_global_reg(hw,
9641 I40E_GLQF_HASH_MSK(i, pctype),
9644 /*clear unused mask registers of the pctype */
9645 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9646 i40e_check_write_global_reg(hw,
9647 I40E_GLQF_FD_MSK(i, pctype),
9649 i40e_check_write_global_reg(hw,
9650 I40E_GLQF_HASH_MSK(i, pctype),
9654 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9656 I40E_WRITE_FLUSH(hw);
9658 /* store the default input set */
9659 if (!pf->support_multi_driver)
9660 pf->hash_input_set[pctype] = input_set;
9661 pf->fdir.input_set[pctype] = input_set;
9666 i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set,
9667 uint32_t pctype, bool add)
9669 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9670 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9671 uint64_t inset_reg = 0;
9674 if (pf->support_multi_driver) {
9676 "Modify input set is not permitted when multi-driver enabled.");
9680 /* For X722, get translated pctype in fd pctype register */
9681 if (hw->mac.type == I40E_MAC_X722)
9682 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(pctype));
9685 /* get inset value in register */
9686 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9687 inset_reg <<= I40E_32_BIT_WIDTH;
9688 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9689 input_set |= pf->hash_input_set[pctype];
9691 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9692 I40E_INSET_MASK_NUM_REG);
9696 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9698 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9699 (uint32_t)(inset_reg & UINT32_MAX));
9700 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9701 (uint32_t)((inset_reg >>
9702 I40E_32_BIT_WIDTH) & UINT32_MAX));
9704 for (i = 0; i < num; i++)
9705 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9707 /*clear unused mask registers of the pctype */
9708 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9709 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9711 I40E_WRITE_FLUSH(hw);
9713 pf->hash_input_set[pctype] = input_set;
9717 /* Convert ethertype filter structure */
9719 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9720 struct i40e_ethertype_filter *filter)
9722 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9723 RTE_ETHER_ADDR_LEN);
9724 filter->input.ether_type = input->ether_type;
9725 filter->flags = input->flags;
9726 filter->queue = input->queue;
9731 /* Check if there exists the ehtertype filter */
9732 struct i40e_ethertype_filter *
9733 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9734 const struct i40e_ethertype_filter_input *input)
9738 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9742 return ethertype_rule->hash_map[ret];
9745 /* Add ethertype filter in SW list */
9747 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9748 struct i40e_ethertype_filter *filter)
9750 struct i40e_ethertype_rule *rule = &pf->ethertype;
9753 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9756 "Failed to insert ethertype filter"
9757 " to hash table %d!",
9761 rule->hash_map[ret] = filter;
9763 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9768 /* Delete ethertype filter in SW list */
9770 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9771 struct i40e_ethertype_filter_input *input)
9773 struct i40e_ethertype_rule *rule = &pf->ethertype;
9774 struct i40e_ethertype_filter *filter;
9777 ret = rte_hash_del_key(rule->hash_table, input);
9780 "Failed to delete ethertype filter"
9781 " to hash table %d!",
9785 filter = rule->hash_map[ret];
9786 rule->hash_map[ret] = NULL;
9788 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9795 * Configure ethertype filter, which can director packet by filtering
9796 * with mac address and ether_type or only ether_type
9799 i40e_ethertype_filter_set(struct i40e_pf *pf,
9800 struct rte_eth_ethertype_filter *filter,
9803 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9804 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9805 struct i40e_ethertype_filter *ethertype_filter, *node;
9806 struct i40e_ethertype_filter check_filter;
9807 struct i40e_control_filter_stats stats;
9811 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9812 PMD_DRV_LOG(ERR, "Invalid queue ID");
9815 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9816 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9818 "unsupported ether_type(0x%04x) in control packet filter.",
9819 filter->ether_type);
9822 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9823 PMD_DRV_LOG(WARNING,
9824 "filter vlan ether_type in first tag is not supported.");
9826 /* Check if there is the filter in SW list */
9827 memset(&check_filter, 0, sizeof(check_filter));
9828 i40e_ethertype_filter_convert(filter, &check_filter);
9829 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9830 &check_filter.input);
9832 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9836 if (!add && !node) {
9837 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9841 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9842 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9843 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9844 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9845 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9847 memset(&stats, 0, sizeof(stats));
9848 ret = i40e_aq_add_rem_control_packet_filter(hw,
9849 filter->mac_addr.addr_bytes,
9850 filter->ether_type, flags,
9852 filter->queue, add, &stats, NULL);
9855 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9856 ret, stats.mac_etype_used, stats.etype_used,
9857 stats.mac_etype_free, stats.etype_free);
9861 /* Add or delete a filter in SW list */
9863 ethertype_filter = rte_zmalloc("ethertype_filter",
9864 sizeof(*ethertype_filter), 0);
9865 if (ethertype_filter == NULL) {
9866 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9870 rte_memcpy(ethertype_filter, &check_filter,
9871 sizeof(check_filter));
9872 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9874 rte_free(ethertype_filter);
9876 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9883 i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
9884 const struct rte_flow_ops **ops)
9889 *ops = &i40e_flow_ops;
9894 * Check and enable Extended Tag.
9895 * Enabling Extended Tag is important for 40G performance.
9898 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9900 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9904 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9907 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9911 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9912 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9917 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9920 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9924 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9925 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9928 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9929 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9932 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9939 * As some registers wouldn't be reset unless a global hardware reset,
9940 * hardware initialization is needed to put those registers into an
9941 * expected initial state.
9944 i40e_hw_init(struct rte_eth_dev *dev)
9946 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9948 i40e_enable_extended_tag(dev);
9950 /* clear the PF Queue Filter control register */
9951 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9953 /* Disable symmetric hash per port */
9954 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9958 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9959 * however this function will return only one highest pctype index,
9960 * which is not quite correct. This is known problem of i40e driver
9961 * and needs to be fixed later.
9963 enum i40e_filter_pctype
9964 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9967 uint64_t pctype_mask;
9969 if (flow_type < I40E_FLOW_TYPE_MAX) {
9970 pctype_mask = adapter->pctypes_tbl[flow_type];
9971 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9972 if (pctype_mask & (1ULL << i))
9973 return (enum i40e_filter_pctype)i;
9976 return I40E_FILTER_PCTYPE_INVALID;
9980 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9981 enum i40e_filter_pctype pctype)
9984 uint64_t pctype_mask = 1ULL << pctype;
9986 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9988 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9992 return RTE_ETH_FLOW_UNKNOWN;
9996 * On X710, performance number is far from the expectation on recent firmware
9997 * versions; on XL710, performance number is also far from the expectation on
9998 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9999 * mode is enabled and port MAC address is equal to the packet destination MAC
10000 * address. The fix for this issue may not be integrated in the following
10001 * firmware version. So the workaround in software driver is needed. It needs
10002 * to modify the initial values of 3 internal only registers for both X710 and
10003 * XL710. Note that the values for X710 or XL710 could be different, and the
10004 * workaround can be removed when it is fixed in firmware in the future.
10007 /* For both X710 and XL710 */
10008 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10009 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10010 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10012 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10013 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10016 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10017 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10020 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10022 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10023 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10026 * GL_SWR_PM_UP_THR:
10027 * The value is not impacted from the link speed, its value is set according
10028 * to the total number of ports for a better pipe-monitor configuration.
10031 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10033 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10034 .device_id = (dev), \
10035 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10037 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10038 .device_id = (dev), \
10039 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10041 static const struct {
10042 uint16_t device_id;
10044 } swr_pm_table[] = {
10045 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10046 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10047 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10048 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10049 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10051 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10052 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10053 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10054 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10055 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10056 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10057 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10061 if (value == NULL) {
10062 PMD_DRV_LOG(ERR, "value is NULL");
10066 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10067 if (hw->device_id == swr_pm_table[i].device_id) {
10068 *value = swr_pm_table[i].val;
10070 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10072 hw->device_id, *value);
10081 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10083 enum i40e_status_code status;
10084 struct i40e_aq_get_phy_abilities_resp phy_ab;
10085 int ret = -ENOTSUP;
10088 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10092 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10095 rte_delay_us(100000);
10097 status = i40e_aq_get_phy_capabilities(hw, false,
10098 true, &phy_ab, NULL);
10106 i40e_configure_registers(struct i40e_hw *hw)
10112 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10113 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10114 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10120 for (i = 0; i < RTE_DIM(reg_table); i++) {
10121 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10122 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10124 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10125 else /* For X710/XL710/XXV710 */
10126 if (hw->aq.fw_maj_ver < 6)
10128 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10131 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10134 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10135 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10137 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10138 else /* For X710/XL710/XXV710 */
10140 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10143 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10146 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10147 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10148 "GL_SWR_PM_UP_THR value fixup",
10153 reg_table[i].val = cfg_val;
10156 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10159 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10160 reg_table[i].addr);
10163 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10164 reg_table[i].addr, reg);
10165 if (reg == reg_table[i].val)
10168 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10169 reg_table[i].val, NULL);
10172 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10173 reg_table[i].val, reg_table[i].addr);
10176 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10177 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10181 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10182 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10183 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10185 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10190 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10191 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10195 /* Configure for double VLAN RX stripping */
10196 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10197 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10198 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10199 ret = i40e_aq_debug_write_register(hw,
10200 I40E_VSI_TSR(vsi->vsi_id),
10203 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10205 return I40E_ERR_CONFIG;
10209 /* Configure for double VLAN TX insertion */
10210 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10211 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10212 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10213 ret = i40e_aq_debug_write_register(hw,
10214 I40E_VSI_L2TAGSTXVALID(
10215 vsi->vsi_id), reg, NULL);
10218 "Failed to update VSI_L2TAGSTXVALID[%d]",
10220 return I40E_ERR_CONFIG;
10228 * i40e_aq_add_mirror_rule
10229 * @hw: pointer to the hardware structure
10230 * @seid: VEB seid to add mirror rule to
10231 * @dst_id: destination vsi seid
10232 * @entries: Buffer which contains the entities to be mirrored
10233 * @count: number of entities contained in the buffer
10234 * @rule_id:the rule_id of the rule to be added
10236 * Add a mirror rule for a given veb.
10239 static enum i40e_status_code
10240 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10241 uint16_t seid, uint16_t dst_id,
10242 uint16_t rule_type, uint16_t *entries,
10243 uint16_t count, uint16_t *rule_id)
10245 struct i40e_aq_desc desc;
10246 struct i40e_aqc_add_delete_mirror_rule cmd;
10247 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10248 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10251 enum i40e_status_code status;
10253 i40e_fill_default_direct_cmd_desc(&desc,
10254 i40e_aqc_opc_add_mirror_rule);
10255 memset(&cmd, 0, sizeof(cmd));
10257 buff_len = sizeof(uint16_t) * count;
10258 desc.datalen = rte_cpu_to_le_16(buff_len);
10260 desc.flags |= rte_cpu_to_le_16(
10261 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10262 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10263 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10264 cmd.num_entries = rte_cpu_to_le_16(count);
10265 cmd.seid = rte_cpu_to_le_16(seid);
10266 cmd.destination = rte_cpu_to_le_16(dst_id);
10268 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10269 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10271 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10272 hw->aq.asq_last_status, resp->rule_id,
10273 resp->mirror_rules_used, resp->mirror_rules_free);
10274 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10280 * i40e_aq_del_mirror_rule
10281 * @hw: pointer to the hardware structure
10282 * @seid: VEB seid to add mirror rule to
10283 * @entries: Buffer which contains the entities to be mirrored
10284 * @count: number of entities contained in the buffer
10285 * @rule_id:the rule_id of the rule to be delete
10287 * Delete a mirror rule for a given veb.
10290 static enum i40e_status_code
10291 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10292 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10293 uint16_t count, uint16_t rule_id)
10295 struct i40e_aq_desc desc;
10296 struct i40e_aqc_add_delete_mirror_rule cmd;
10297 uint16_t buff_len = 0;
10298 enum i40e_status_code status;
10301 i40e_fill_default_direct_cmd_desc(&desc,
10302 i40e_aqc_opc_delete_mirror_rule);
10303 memset(&cmd, 0, sizeof(cmd));
10304 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10305 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10307 cmd.num_entries = count;
10308 buff_len = sizeof(uint16_t) * count;
10309 desc.datalen = rte_cpu_to_le_16(buff_len);
10310 buff = (void *)entries;
10312 /* rule id is filled in destination field for deleting mirror rule */
10313 cmd.destination = rte_cpu_to_le_16(rule_id);
10315 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10316 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10317 cmd.seid = rte_cpu_to_le_16(seid);
10319 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10320 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10326 * i40e_mirror_rule_set
10327 * @dev: pointer to the hardware structure
10328 * @mirror_conf: mirror rule info
10329 * @sw_id: mirror rule's sw_id
10330 * @on: enable/disable
10332 * set a mirror rule.
10336 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10337 struct rte_eth_mirror_conf *mirror_conf,
10338 uint8_t sw_id, uint8_t on)
10340 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10341 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10342 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10343 struct i40e_mirror_rule *parent = NULL;
10344 uint16_t seid, dst_seid, rule_id;
10348 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10350 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10352 "mirror rule can not be configured without veb or vfs.");
10355 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10356 PMD_DRV_LOG(ERR, "mirror table is full.");
10359 if (mirror_conf->dst_pool > pf->vf_num) {
10360 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10361 mirror_conf->dst_pool);
10365 seid = pf->main_vsi->veb->seid;
10367 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10368 if (sw_id <= it->index) {
10374 if (mirr_rule && sw_id == mirr_rule->index) {
10376 PMD_DRV_LOG(ERR, "mirror rule exists.");
10379 ret = i40e_aq_del_mirror_rule(hw, seid,
10380 mirr_rule->rule_type,
10381 mirr_rule->entries,
10382 mirr_rule->num_entries, mirr_rule->id);
10385 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10386 ret, hw->aq.asq_last_status);
10389 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10390 rte_free(mirr_rule);
10391 pf->nb_mirror_rule--;
10395 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10399 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10400 sizeof(struct i40e_mirror_rule) , 0);
10402 PMD_DRV_LOG(ERR, "failed to allocate memory");
10403 return I40E_ERR_NO_MEMORY;
10405 switch (mirror_conf->rule_type) {
10406 case ETH_MIRROR_VLAN:
10407 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10408 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10409 mirr_rule->entries[j] =
10410 mirror_conf->vlan.vlan_id[i];
10415 PMD_DRV_LOG(ERR, "vlan is not specified.");
10416 rte_free(mirr_rule);
10419 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10421 case ETH_MIRROR_VIRTUAL_POOL_UP:
10422 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10423 /* check if the specified pool bit is out of range */
10424 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10425 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10426 rte_free(mirr_rule);
10429 for (i = 0, j = 0; i < pf->vf_num; i++) {
10430 if (mirror_conf->pool_mask & (1ULL << i)) {
10431 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10435 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10436 /* add pf vsi to entries */
10437 mirr_rule->entries[j] = pf->main_vsi_seid;
10441 PMD_DRV_LOG(ERR, "pool is not specified.");
10442 rte_free(mirr_rule);
10445 /* egress and ingress in aq commands means from switch but not port */
10446 mirr_rule->rule_type =
10447 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10448 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10449 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10451 case ETH_MIRROR_UPLINK_PORT:
10452 /* egress and ingress in aq commands means from switch but not port*/
10453 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10455 case ETH_MIRROR_DOWNLINK_PORT:
10456 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10459 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10460 mirror_conf->rule_type);
10461 rte_free(mirr_rule);
10465 /* If the dst_pool is equal to vf_num, consider it as PF */
10466 if (mirror_conf->dst_pool == pf->vf_num)
10467 dst_seid = pf->main_vsi_seid;
10469 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10471 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10472 mirr_rule->rule_type, mirr_rule->entries,
10476 "failed to add mirror rule: ret = %d, aq_err = %d.",
10477 ret, hw->aq.asq_last_status);
10478 rte_free(mirr_rule);
10482 mirr_rule->index = sw_id;
10483 mirr_rule->num_entries = j;
10484 mirr_rule->id = rule_id;
10485 mirr_rule->dst_vsi_seid = dst_seid;
10488 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10490 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10492 pf->nb_mirror_rule++;
10497 * i40e_mirror_rule_reset
10498 * @dev: pointer to the device
10499 * @sw_id: mirror rule's sw_id
10501 * reset a mirror rule.
10505 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10507 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10508 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10509 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10513 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10515 seid = pf->main_vsi->veb->seid;
10517 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10518 if (sw_id == it->index) {
10524 ret = i40e_aq_del_mirror_rule(hw, seid,
10525 mirr_rule->rule_type,
10526 mirr_rule->entries,
10527 mirr_rule->num_entries, mirr_rule->id);
10530 "failed to remove mirror rule: status = %d, aq_err = %d.",
10531 ret, hw->aq.asq_last_status);
10534 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10535 rte_free(mirr_rule);
10536 pf->nb_mirror_rule--;
10538 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10545 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10547 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10548 uint64_t systim_cycles;
10550 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10551 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10554 return systim_cycles;
10558 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10560 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10561 uint64_t rx_tstamp;
10563 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10564 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10571 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10573 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10574 uint64_t tx_tstamp;
10576 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10577 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10584 i40e_start_timecounters(struct rte_eth_dev *dev)
10586 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10587 struct i40e_adapter *adapter = dev->data->dev_private;
10588 struct rte_eth_link link;
10589 uint32_t tsync_inc_l;
10590 uint32_t tsync_inc_h;
10592 /* Get current link speed. */
10593 i40e_dev_link_update(dev, 1);
10594 rte_eth_linkstatus_get(dev, &link);
10596 switch (link.link_speed) {
10597 case ETH_SPEED_NUM_40G:
10598 case ETH_SPEED_NUM_25G:
10599 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10600 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10602 case ETH_SPEED_NUM_10G:
10603 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10604 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10606 case ETH_SPEED_NUM_1G:
10607 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10608 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10615 /* Set the timesync increment value. */
10616 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10617 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10619 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10620 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10621 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10623 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10624 adapter->systime_tc.cc_shift = 0;
10625 adapter->systime_tc.nsec_mask = 0;
10627 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10628 adapter->rx_tstamp_tc.cc_shift = 0;
10629 adapter->rx_tstamp_tc.nsec_mask = 0;
10631 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10632 adapter->tx_tstamp_tc.cc_shift = 0;
10633 adapter->tx_tstamp_tc.nsec_mask = 0;
10637 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10639 struct i40e_adapter *adapter = dev->data->dev_private;
10641 adapter->systime_tc.nsec += delta;
10642 adapter->rx_tstamp_tc.nsec += delta;
10643 adapter->tx_tstamp_tc.nsec += delta;
10649 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10652 struct i40e_adapter *adapter = dev->data->dev_private;
10654 ns = rte_timespec_to_ns(ts);
10656 /* Set the timecounters to a new value. */
10657 adapter->systime_tc.nsec = ns;
10658 adapter->rx_tstamp_tc.nsec = ns;
10659 adapter->tx_tstamp_tc.nsec = ns;
10665 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10667 uint64_t ns, systime_cycles;
10668 struct i40e_adapter *adapter = dev->data->dev_private;
10670 systime_cycles = i40e_read_systime_cyclecounter(dev);
10671 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10672 *ts = rte_ns_to_timespec(ns);
10678 i40e_timesync_enable(struct rte_eth_dev *dev)
10680 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10681 uint32_t tsync_ctl_l;
10682 uint32_t tsync_ctl_h;
10684 /* Stop the timesync system time. */
10685 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10686 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10687 /* Reset the timesync system time value. */
10688 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10689 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10691 i40e_start_timecounters(dev);
10693 /* Clear timesync registers. */
10694 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10695 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10696 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10697 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10698 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10699 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10701 /* Enable timestamping of PTP packets. */
10702 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10703 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10705 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10706 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10707 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10709 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10710 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10716 i40e_timesync_disable(struct rte_eth_dev *dev)
10718 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10719 uint32_t tsync_ctl_l;
10720 uint32_t tsync_ctl_h;
10722 /* Disable timestamping of transmitted PTP packets. */
10723 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10724 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10726 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10727 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10729 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10730 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10732 /* Reset the timesync increment value. */
10733 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10734 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10740 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10741 struct timespec *timestamp, uint32_t flags)
10743 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10744 struct i40e_adapter *adapter = dev->data->dev_private;
10745 uint32_t sync_status;
10746 uint32_t index = flags & 0x03;
10747 uint64_t rx_tstamp_cycles;
10750 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10751 if ((sync_status & (1 << index)) == 0)
10754 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10755 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10756 *timestamp = rte_ns_to_timespec(ns);
10762 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10763 struct timespec *timestamp)
10765 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10766 struct i40e_adapter *adapter = dev->data->dev_private;
10767 uint32_t sync_status;
10768 uint64_t tx_tstamp_cycles;
10771 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10772 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10775 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10776 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10777 *timestamp = rte_ns_to_timespec(ns);
10783 * i40e_parse_dcb_configure - parse dcb configure from user
10784 * @dev: the device being configured
10785 * @dcb_cfg: pointer of the result of parse
10786 * @*tc_map: bit map of enabled traffic classes
10788 * Returns 0 on success, negative value on failure
10791 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10792 struct i40e_dcbx_config *dcb_cfg,
10795 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10796 uint8_t i, tc_bw, bw_lf;
10798 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10800 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10801 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10802 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10806 /* assume each tc has the same bw */
10807 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10808 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10809 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10810 /* to ensure the sum of tcbw is equal to 100 */
10811 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10812 for (i = 0; i < bw_lf; i++)
10813 dcb_cfg->etscfg.tcbwtable[i]++;
10815 /* assume each tc has the same Transmission Selection Algorithm */
10816 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10817 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10819 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10820 dcb_cfg->etscfg.prioritytable[i] =
10821 dcb_rx_conf->dcb_tc[i];
10823 /* FW needs one App to configure HW */
10824 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10825 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10826 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10827 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10829 if (dcb_rx_conf->nb_tcs == 0)
10830 *tc_map = 1; /* tc0 only */
10832 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10834 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10835 dcb_cfg->pfc.willing = 0;
10836 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10837 dcb_cfg->pfc.pfcenable = *tc_map;
10843 static enum i40e_status_code
10844 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10845 struct i40e_aqc_vsi_properties_data *info,
10846 uint8_t enabled_tcmap)
10848 enum i40e_status_code ret;
10849 int i, total_tc = 0;
10850 uint16_t qpnum_per_tc, bsf, qp_idx;
10851 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10852 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10853 uint16_t used_queues;
10855 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10856 if (ret != I40E_SUCCESS)
10859 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10860 if (enabled_tcmap & (1 << i))
10865 vsi->enabled_tc = enabled_tcmap;
10867 /* different VSI has different queues assigned */
10868 if (vsi->type == I40E_VSI_MAIN)
10869 used_queues = dev_data->nb_rx_queues -
10870 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10871 else if (vsi->type == I40E_VSI_VMDQ2)
10872 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10874 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10875 return I40E_ERR_NO_AVAILABLE_VSI;
10878 qpnum_per_tc = used_queues / total_tc;
10879 /* Number of queues per enabled TC */
10880 if (qpnum_per_tc == 0) {
10881 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10882 return I40E_ERR_INVALID_QP_ID;
10884 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10885 I40E_MAX_Q_PER_TC);
10886 bsf = rte_bsf32(qpnum_per_tc);
10889 * Configure TC and queue mapping parameters, for enabled TC,
10890 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10891 * default queue will serve it.
10894 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10895 if (vsi->enabled_tc & (1 << i)) {
10896 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10897 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10898 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10899 qp_idx += qpnum_per_tc;
10901 info->tc_mapping[i] = 0;
10904 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10905 if (vsi->type == I40E_VSI_SRIOV) {
10906 info->mapping_flags |=
10907 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10908 for (i = 0; i < vsi->nb_qps; i++)
10909 info->queue_mapping[i] =
10910 rte_cpu_to_le_16(vsi->base_queue + i);
10912 info->mapping_flags |=
10913 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10914 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10916 info->valid_sections |=
10917 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10919 return I40E_SUCCESS;
10923 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10924 * @veb: VEB to be configured
10925 * @tc_map: enabled TC bitmap
10927 * Returns 0 on success, negative value on failure
10929 static enum i40e_status_code
10930 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10932 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10933 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10934 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10935 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10936 enum i40e_status_code ret = I40E_SUCCESS;
10940 /* Check if enabled_tc is same as existing or new TCs */
10941 if (veb->enabled_tc == tc_map)
10944 /* configure tc bandwidth */
10945 memset(&veb_bw, 0, sizeof(veb_bw));
10946 veb_bw.tc_valid_bits = tc_map;
10947 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10948 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10949 if (tc_map & BIT_ULL(i))
10950 veb_bw.tc_bw_share_credits[i] = 1;
10952 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10956 "AQ command Config switch_comp BW allocation per TC failed = %d",
10957 hw->aq.asq_last_status);
10961 memset(&ets_query, 0, sizeof(ets_query));
10962 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10964 if (ret != I40E_SUCCESS) {
10966 "Failed to get switch_comp ETS configuration %u",
10967 hw->aq.asq_last_status);
10970 memset(&bw_query, 0, sizeof(bw_query));
10971 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10973 if (ret != I40E_SUCCESS) {
10975 "Failed to get switch_comp bandwidth configuration %u",
10976 hw->aq.asq_last_status);
10980 /* store and print out BW info */
10981 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10982 veb->bw_info.bw_max = ets_query.tc_bw_max;
10983 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10984 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10985 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10986 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10987 I40E_16_BIT_WIDTH);
10988 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10989 veb->bw_info.bw_ets_share_credits[i] =
10990 bw_query.tc_bw_share_credits[i];
10991 veb->bw_info.bw_ets_credits[i] =
10992 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10993 /* 4 bits per TC, 4th bit is reserved */
10994 veb->bw_info.bw_ets_max[i] =
10995 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10996 RTE_LEN2MASK(3, uint8_t));
10997 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10998 veb->bw_info.bw_ets_share_credits[i]);
10999 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11000 veb->bw_info.bw_ets_credits[i]);
11001 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11002 veb->bw_info.bw_ets_max[i]);
11005 veb->enabled_tc = tc_map;
11012 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11013 * @vsi: VSI to be configured
11014 * @tc_map: enabled TC bitmap
11016 * Returns 0 on success, negative value on failure
11018 static enum i40e_status_code
11019 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11021 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11022 struct i40e_vsi_context ctxt;
11023 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11024 enum i40e_status_code ret = I40E_SUCCESS;
11027 /* Check if enabled_tc is same as existing or new TCs */
11028 if (vsi->enabled_tc == tc_map)
11031 /* configure tc bandwidth */
11032 memset(&bw_data, 0, sizeof(bw_data));
11033 bw_data.tc_valid_bits = tc_map;
11034 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11035 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11036 if (tc_map & BIT_ULL(i))
11037 bw_data.tc_bw_credits[i] = 1;
11039 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11042 "AQ command Config VSI BW allocation per TC failed = %d",
11043 hw->aq.asq_last_status);
11046 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11047 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11049 /* Update Queue Pairs Mapping for currently enabled UPs */
11050 ctxt.seid = vsi->seid;
11051 ctxt.pf_num = hw->pf_id;
11053 ctxt.uplink_seid = vsi->uplink_seid;
11054 ctxt.info = vsi->info;
11056 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11060 /* Update the VSI after updating the VSI queue-mapping information */
11061 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11063 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11064 hw->aq.asq_last_status);
11067 /* update the local VSI info with updated queue map */
11068 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11069 sizeof(vsi->info.tc_mapping));
11070 rte_memcpy(&vsi->info.queue_mapping,
11071 &ctxt.info.queue_mapping,
11072 sizeof(vsi->info.queue_mapping));
11073 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11074 vsi->info.valid_sections = 0;
11076 /* query and update current VSI BW information */
11077 ret = i40e_vsi_get_bw_config(vsi);
11080 "Failed updating vsi bw info, err %s aq_err %s",
11081 i40e_stat_str(hw, ret),
11082 i40e_aq_str(hw, hw->aq.asq_last_status));
11086 vsi->enabled_tc = tc_map;
11093 * i40e_dcb_hw_configure - program the dcb setting to hw
11094 * @pf: pf the configuration is taken on
11095 * @new_cfg: new configuration
11096 * @tc_map: enabled TC bitmap
11098 * Returns 0 on success, negative value on failure
11100 static enum i40e_status_code
11101 i40e_dcb_hw_configure(struct i40e_pf *pf,
11102 struct i40e_dcbx_config *new_cfg,
11105 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11106 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11107 struct i40e_vsi *main_vsi = pf->main_vsi;
11108 struct i40e_vsi_list *vsi_list;
11109 enum i40e_status_code ret;
11113 /* Use the FW API if FW > v4.4*/
11114 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11115 (hw->aq.fw_maj_ver >= 5))) {
11117 "FW < v4.4, can not use FW LLDP API to configure DCB");
11118 return I40E_ERR_FIRMWARE_API_VERSION;
11121 /* Check if need reconfiguration */
11122 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11123 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11124 return I40E_SUCCESS;
11127 /* Copy the new config to the current config */
11128 *old_cfg = *new_cfg;
11129 old_cfg->etsrec = old_cfg->etscfg;
11130 ret = i40e_set_dcb_config(hw);
11132 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11133 i40e_stat_str(hw, ret),
11134 i40e_aq_str(hw, hw->aq.asq_last_status));
11137 /* set receive Arbiter to RR mode and ETS scheme by default */
11138 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11139 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11140 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11141 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11142 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11143 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11144 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11145 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11146 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11147 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11148 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11149 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11150 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11152 /* get local mib to check whether it is configured correctly */
11154 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11155 /* Get Local DCB Config */
11156 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11157 &hw->local_dcbx_config);
11159 /* if Veb is created, need to update TC of it at first */
11160 if (main_vsi->veb) {
11161 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11163 PMD_INIT_LOG(WARNING,
11164 "Failed configuring TC for VEB seid=%d",
11165 main_vsi->veb->seid);
11167 /* Update each VSI */
11168 i40e_vsi_config_tc(main_vsi, tc_map);
11169 if (main_vsi->veb) {
11170 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11171 /* Beside main VSI and VMDQ VSIs, only enable default
11172 * TC for other VSIs
11174 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11175 ret = i40e_vsi_config_tc(vsi_list->vsi,
11178 ret = i40e_vsi_config_tc(vsi_list->vsi,
11179 I40E_DEFAULT_TCMAP);
11181 PMD_INIT_LOG(WARNING,
11182 "Failed configuring TC for VSI seid=%d",
11183 vsi_list->vsi->seid);
11187 return I40E_SUCCESS;
11191 * i40e_dcb_init_configure - initial dcb config
11192 * @dev: device being configured
11193 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11195 * Returns 0 on success, negative value on failure
11198 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11200 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11201 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11204 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11205 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11209 /* DCB initialization:
11210 * Update DCB configuration from the Firmware and configure
11211 * LLDP MIB change event.
11213 if (sw_dcb == TRUE) {
11214 /* Stopping lldp is necessary for DPDK, but it will cause
11215 * DCB init failed. For i40e_init_dcb(), the prerequisite
11216 * for successful initialization of DCB is that LLDP is
11217 * enabled. So it is needed to start lldp before DCB init
11218 * and stop it after initialization.
11220 ret = i40e_aq_start_lldp(hw, true, NULL);
11221 if (ret != I40E_SUCCESS)
11222 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11224 ret = i40e_init_dcb(hw, true);
11225 /* If lldp agent is stopped, the return value from
11226 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11227 * adminq status. Otherwise, it should return success.
11229 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11230 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11231 memset(&hw->local_dcbx_config, 0,
11232 sizeof(struct i40e_dcbx_config));
11233 /* set dcb default configuration */
11234 hw->local_dcbx_config.etscfg.willing = 0;
11235 hw->local_dcbx_config.etscfg.maxtcs = 0;
11236 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11237 hw->local_dcbx_config.etscfg.tsatable[0] =
11239 /* all UPs mapping to TC0 */
11240 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11241 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11242 hw->local_dcbx_config.etsrec =
11243 hw->local_dcbx_config.etscfg;
11244 hw->local_dcbx_config.pfc.willing = 0;
11245 hw->local_dcbx_config.pfc.pfccap =
11246 I40E_MAX_TRAFFIC_CLASS;
11247 /* FW needs one App to configure HW */
11248 hw->local_dcbx_config.numapps = 1;
11249 hw->local_dcbx_config.app[0].selector =
11250 I40E_APP_SEL_ETHTYPE;
11251 hw->local_dcbx_config.app[0].priority = 3;
11252 hw->local_dcbx_config.app[0].protocolid =
11253 I40E_APP_PROTOID_FCOE;
11254 ret = i40e_set_dcb_config(hw);
11257 "default dcb config fails. err = %d, aq_err = %d.",
11258 ret, hw->aq.asq_last_status);
11263 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11264 ret, hw->aq.asq_last_status);
11268 if (i40e_need_stop_lldp(dev)) {
11269 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11270 if (ret != I40E_SUCCESS)
11271 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11274 ret = i40e_aq_start_lldp(hw, true, NULL);
11275 if (ret != I40E_SUCCESS)
11276 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11278 ret = i40e_init_dcb(hw, true);
11280 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11282 "HW doesn't support DCBX offload.");
11287 "DCBX configuration failed, err = %d, aq_err = %d.",
11288 ret, hw->aq.asq_last_status);
11296 * i40e_dcb_setup - setup dcb related config
11297 * @dev: device being configured
11299 * Returns 0 on success, negative value on failure
11302 i40e_dcb_setup(struct rte_eth_dev *dev)
11304 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11305 struct i40e_dcbx_config dcb_cfg;
11306 uint8_t tc_map = 0;
11309 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11310 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11314 if (pf->vf_num != 0)
11315 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11317 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11319 PMD_INIT_LOG(ERR, "invalid dcb config");
11322 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11324 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11332 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11333 struct rte_eth_dcb_info *dcb_info)
11335 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11336 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11337 struct i40e_vsi *vsi = pf->main_vsi;
11338 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11339 uint16_t bsf, tc_mapping;
11342 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11343 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11345 dcb_info->nb_tcs = 1;
11346 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11347 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11348 for (i = 0; i < dcb_info->nb_tcs; i++)
11349 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11351 /* get queue mapping if vmdq is disabled */
11352 if (!pf->nb_cfg_vmdq_vsi) {
11353 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11354 if (!(vsi->enabled_tc & (1 << i)))
11356 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11357 dcb_info->tc_queue.tc_rxq[j][i].base =
11358 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11359 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11360 dcb_info->tc_queue.tc_txq[j][i].base =
11361 dcb_info->tc_queue.tc_rxq[j][i].base;
11362 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11363 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11364 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11365 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11366 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11371 /* get queue mapping if vmdq is enabled */
11373 vsi = pf->vmdq[j].vsi;
11374 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11375 if (!(vsi->enabled_tc & (1 << i)))
11377 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11378 dcb_info->tc_queue.tc_rxq[j][i].base =
11379 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11380 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11381 dcb_info->tc_queue.tc_txq[j][i].base =
11382 dcb_info->tc_queue.tc_rxq[j][i].base;
11383 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11384 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11385 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11386 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11387 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11390 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11395 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11397 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11398 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11399 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11400 uint16_t msix_intr;
11402 msix_intr = intr_handle->intr_vec[queue_id];
11403 if (msix_intr == I40E_MISC_VEC_ID)
11404 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11405 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11406 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11407 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11410 I40E_PFINT_DYN_CTLN(msix_intr -
11411 I40E_RX_VEC_START),
11412 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11413 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11414 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11416 I40E_WRITE_FLUSH(hw);
11417 rte_intr_ack(&pci_dev->intr_handle);
11423 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11425 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11426 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11427 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11428 uint16_t msix_intr;
11430 msix_intr = intr_handle->intr_vec[queue_id];
11431 if (msix_intr == I40E_MISC_VEC_ID)
11432 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11433 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11436 I40E_PFINT_DYN_CTLN(msix_intr -
11437 I40E_RX_VEC_START),
11438 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11439 I40E_WRITE_FLUSH(hw);
11445 * This function is used to check if the register is valid.
11446 * Below is the valid registers list for X722 only:
11450 * 0x208e00--0x209000
11451 * 0x20be00--0x20c000
11452 * 0x263c00--0x264000
11453 * 0x265c00--0x266000
11455 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11457 if ((type != I40E_MAC_X722) &&
11458 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11459 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11460 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11461 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11462 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11463 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11464 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11470 static int i40e_get_regs(struct rte_eth_dev *dev,
11471 struct rte_dev_reg_info *regs)
11473 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11474 uint32_t *ptr_data = regs->data;
11475 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11476 const struct i40e_reg_info *reg_info;
11478 if (ptr_data == NULL) {
11479 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11480 regs->width = sizeof(uint32_t);
11484 /* The first few registers have to be read using AQ operations */
11486 while (i40e_regs_adminq[reg_idx].name) {
11487 reg_info = &i40e_regs_adminq[reg_idx++];
11488 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11490 arr_idx2 <= reg_info->count2;
11492 reg_offset = arr_idx * reg_info->stride1 +
11493 arr_idx2 * reg_info->stride2;
11494 reg_offset += reg_info->base_addr;
11495 ptr_data[reg_offset >> 2] =
11496 i40e_read_rx_ctl(hw, reg_offset);
11500 /* The remaining registers can be read using primitives */
11502 while (i40e_regs_others[reg_idx].name) {
11503 reg_info = &i40e_regs_others[reg_idx++];
11504 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11506 arr_idx2 <= reg_info->count2;
11508 reg_offset = arr_idx * reg_info->stride1 +
11509 arr_idx2 * reg_info->stride2;
11510 reg_offset += reg_info->base_addr;
11511 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11512 ptr_data[reg_offset >> 2] = 0;
11514 ptr_data[reg_offset >> 2] =
11515 I40E_READ_REG(hw, reg_offset);
11522 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11524 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11526 /* Convert word count to byte count */
11527 return hw->nvm.sr_size << 1;
11530 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11531 struct rte_dev_eeprom_info *eeprom)
11533 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11534 uint16_t *data = eeprom->data;
11535 uint16_t offset, length, cnt_words;
11538 offset = eeprom->offset >> 1;
11539 length = eeprom->length >> 1;
11540 cnt_words = length;
11542 if (offset > hw->nvm.sr_size ||
11543 offset + length > hw->nvm.sr_size) {
11544 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11548 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11550 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11551 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11552 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11559 static int i40e_get_module_info(struct rte_eth_dev *dev,
11560 struct rte_eth_dev_module_info *modinfo)
11562 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11563 uint32_t sff8472_comp = 0;
11564 uint32_t sff8472_swap = 0;
11565 uint32_t sff8636_rev = 0;
11566 i40e_status status;
11569 /* Check if firmware supports reading module EEPROM. */
11570 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11572 "Module EEPROM memory read not supported. "
11573 "Please update the NVM image.\n");
11577 status = i40e_update_link_info(hw);
11581 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11583 "Cannot read module EEPROM memory. "
11584 "No module connected.\n");
11588 type = hw->phy.link_info.module_type[0];
11591 case I40E_MODULE_TYPE_SFP:
11592 status = i40e_aq_get_phy_register(hw,
11593 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11594 I40E_I2C_EEPROM_DEV_ADDR, 1,
11595 I40E_MODULE_SFF_8472_COMP,
11596 &sff8472_comp, NULL);
11600 status = i40e_aq_get_phy_register(hw,
11601 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11602 I40E_I2C_EEPROM_DEV_ADDR, 1,
11603 I40E_MODULE_SFF_8472_SWAP,
11604 &sff8472_swap, NULL);
11608 /* Check if the module requires address swap to access
11609 * the other EEPROM memory page.
11611 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11612 PMD_DRV_LOG(WARNING,
11613 "Module address swap to access "
11614 "page 0xA2 is not supported.\n");
11615 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11616 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11617 } else if (sff8472_comp == 0x00) {
11618 /* Module is not SFF-8472 compliant */
11619 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11620 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11622 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11623 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11626 case I40E_MODULE_TYPE_QSFP_PLUS:
11627 /* Read from memory page 0. */
11628 status = i40e_aq_get_phy_register(hw,
11629 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11631 I40E_MODULE_REVISION_ADDR,
11632 &sff8636_rev, NULL);
11635 /* Determine revision compliance byte */
11636 if (sff8636_rev > 0x02) {
11637 /* Module is SFF-8636 compliant */
11638 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11639 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11641 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11642 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11645 case I40E_MODULE_TYPE_QSFP28:
11646 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11647 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11650 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11656 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11657 struct rte_dev_eeprom_info *info)
11659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11660 bool is_sfp = false;
11661 i40e_status status;
11663 uint32_t value = 0;
11666 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11670 for (i = 0; i < info->length; i++) {
11671 u32 offset = i + info->offset;
11672 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11674 /* Check if we need to access the other memory page */
11676 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11677 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11678 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11681 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11682 /* Compute memory page number and offset. */
11683 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11687 status = i40e_aq_get_phy_register(hw,
11688 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11689 addr, 1, offset, &value, NULL);
11692 data[i] = (uint8_t)value;
11697 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11698 struct rte_ether_addr *mac_addr)
11700 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11701 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11702 struct i40e_vsi *vsi = pf->main_vsi;
11703 struct i40e_mac_filter_info mac_filter;
11704 struct i40e_mac_filter *f;
11707 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11708 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11712 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11713 if (rte_is_same_ether_addr(&pf->dev_addr,
11714 &f->mac_info.mac_addr))
11719 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11723 mac_filter = f->mac_info;
11724 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11725 if (ret != I40E_SUCCESS) {
11726 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11729 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11730 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11731 if (ret != I40E_SUCCESS) {
11732 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11735 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11737 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11738 mac_addr->addr_bytes, NULL);
11739 if (ret != I40E_SUCCESS) {
11740 PMD_DRV_LOG(ERR, "Failed to change mac");
11748 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11750 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11751 struct rte_eth_dev_data *dev_data = pf->dev_data;
11752 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11755 /* check if mtu is within the allowed range */
11756 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
11759 /* mtu setting is forbidden if port is start */
11760 if (dev_data->dev_started) {
11761 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11762 dev_data->port_id);
11766 if (frame_size > I40E_ETH_MAX_LEN)
11767 dev_data->dev_conf.rxmode.offloads |=
11768 DEV_RX_OFFLOAD_JUMBO_FRAME;
11770 dev_data->dev_conf.rxmode.offloads &=
11771 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11773 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11778 /* Restore ethertype filter */
11780 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11782 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11783 struct i40e_ethertype_filter_list
11784 *ethertype_list = &pf->ethertype.ethertype_list;
11785 struct i40e_ethertype_filter *f;
11786 struct i40e_control_filter_stats stats;
11789 TAILQ_FOREACH(f, ethertype_list, rules) {
11791 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11792 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11793 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11794 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11795 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11797 memset(&stats, 0, sizeof(stats));
11798 i40e_aq_add_rem_control_packet_filter(hw,
11799 f->input.mac_addr.addr_bytes,
11800 f->input.ether_type,
11801 flags, pf->main_vsi->seid,
11802 f->queue, 1, &stats, NULL);
11804 PMD_DRV_LOG(INFO, "Ethertype filter:"
11805 " mac_etype_used = %u, etype_used = %u,"
11806 " mac_etype_free = %u, etype_free = %u",
11807 stats.mac_etype_used, stats.etype_used,
11808 stats.mac_etype_free, stats.etype_free);
11811 /* Restore tunnel filter */
11813 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11815 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11816 struct i40e_vsi *vsi;
11817 struct i40e_pf_vf *vf;
11818 struct i40e_tunnel_filter_list
11819 *tunnel_list = &pf->tunnel.tunnel_list;
11820 struct i40e_tunnel_filter *f;
11821 struct i40e_aqc_cloud_filters_element_bb cld_filter;
11822 bool big_buffer = 0;
11824 TAILQ_FOREACH(f, tunnel_list, rules) {
11826 vsi = pf->main_vsi;
11828 vf = &pf->vfs[f->vf_id];
11831 memset(&cld_filter, 0, sizeof(cld_filter));
11832 rte_ether_addr_copy((struct rte_ether_addr *)
11833 &f->input.outer_mac,
11834 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
11835 rte_ether_addr_copy((struct rte_ether_addr *)
11836 &f->input.inner_mac,
11837 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
11838 cld_filter.element.inner_vlan = f->input.inner_vlan;
11839 cld_filter.element.flags = f->input.flags;
11840 cld_filter.element.tenant_id = f->input.tenant_id;
11841 cld_filter.element.queue_number = f->queue;
11842 rte_memcpy(cld_filter.general_fields,
11843 f->input.general_fields,
11844 sizeof(f->input.general_fields));
11846 if (((f->input.flags &
11847 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11848 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11850 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11851 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11853 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11854 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11858 i40e_aq_add_cloud_filters_bb(hw,
11859 vsi->seid, &cld_filter, 1);
11861 i40e_aq_add_cloud_filters(hw, vsi->seid,
11862 &cld_filter.element, 1);
11867 i40e_filter_restore(struct i40e_pf *pf)
11869 i40e_ethertype_filter_restore(pf);
11870 i40e_tunnel_filter_restore(pf);
11871 i40e_fdir_filter_restore(pf);
11872 (void)i40e_hash_filter_restore(pf);
11876 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11878 if (strcmp(dev->device->driver->name, drv->driver.name))
11885 is_i40e_supported(struct rte_eth_dev *dev)
11887 return is_device_supported(dev, &rte_i40e_pmd);
11890 struct i40e_customized_pctype*
11891 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11895 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11896 if (pf->customized_pctype[i].index == index)
11897 return &pf->customized_pctype[i];
11903 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11904 uint32_t pkg_size, uint32_t proto_num,
11905 struct rte_pmd_i40e_proto_info *proto,
11906 enum rte_pmd_i40e_package_op op)
11908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11909 uint32_t pctype_num;
11910 struct rte_pmd_i40e_ptype_info *pctype;
11911 uint32_t buff_size;
11912 struct i40e_customized_pctype *new_pctype = NULL;
11914 uint8_t pctype_value;
11919 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11920 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11921 PMD_DRV_LOG(ERR, "Unsupported operation.");
11925 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11926 (uint8_t *)&pctype_num, sizeof(pctype_num),
11927 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11929 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11933 PMD_DRV_LOG(INFO, "No new pctype added");
11937 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11938 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11940 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11943 /* get information about new pctype list */
11944 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11945 (uint8_t *)pctype, buff_size,
11946 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11948 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11953 /* Update customized pctype. */
11954 for (i = 0; i < pctype_num; i++) {
11955 pctype_value = pctype[i].ptype_id;
11956 memset(name, 0, sizeof(name));
11957 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11958 proto_id = pctype[i].protocols[j];
11959 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11961 for (n = 0; n < proto_num; n++) {
11962 if (proto[n].proto_id != proto_id)
11964 strlcat(name, proto[n].name, sizeof(name));
11965 strlcat(name, "_", sizeof(name));
11969 name[strlen(name) - 1] = '\0';
11970 PMD_DRV_LOG(INFO, "name = %s\n", name);
11971 if (!strcmp(name, "GTPC"))
11973 i40e_find_customized_pctype(pf,
11974 I40E_CUSTOMIZED_GTPC);
11975 else if (!strcmp(name, "GTPU_IPV4"))
11977 i40e_find_customized_pctype(pf,
11978 I40E_CUSTOMIZED_GTPU_IPV4);
11979 else if (!strcmp(name, "GTPU_IPV6"))
11981 i40e_find_customized_pctype(pf,
11982 I40E_CUSTOMIZED_GTPU_IPV6);
11983 else if (!strcmp(name, "GTPU"))
11985 i40e_find_customized_pctype(pf,
11986 I40E_CUSTOMIZED_GTPU);
11987 else if (!strcmp(name, "IPV4_L2TPV3"))
11989 i40e_find_customized_pctype(pf,
11990 I40E_CUSTOMIZED_IPV4_L2TPV3);
11991 else if (!strcmp(name, "IPV6_L2TPV3"))
11993 i40e_find_customized_pctype(pf,
11994 I40E_CUSTOMIZED_IPV6_L2TPV3);
11995 else if (!strcmp(name, "IPV4_ESP"))
11997 i40e_find_customized_pctype(pf,
11998 I40E_CUSTOMIZED_ESP_IPV4);
11999 else if (!strcmp(name, "IPV6_ESP"))
12001 i40e_find_customized_pctype(pf,
12002 I40E_CUSTOMIZED_ESP_IPV6);
12003 else if (!strcmp(name, "IPV4_UDP_ESP"))
12005 i40e_find_customized_pctype(pf,
12006 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12007 else if (!strcmp(name, "IPV6_UDP_ESP"))
12009 i40e_find_customized_pctype(pf,
12010 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12011 else if (!strcmp(name, "IPV4_AH"))
12013 i40e_find_customized_pctype(pf,
12014 I40E_CUSTOMIZED_AH_IPV4);
12015 else if (!strcmp(name, "IPV6_AH"))
12017 i40e_find_customized_pctype(pf,
12018 I40E_CUSTOMIZED_AH_IPV6);
12020 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12021 new_pctype->pctype = pctype_value;
12022 new_pctype->valid = true;
12024 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12025 new_pctype->valid = false;
12035 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12036 uint32_t pkg_size, uint32_t proto_num,
12037 struct rte_pmd_i40e_proto_info *proto,
12038 enum rte_pmd_i40e_package_op op)
12040 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12041 uint16_t port_id = dev->data->port_id;
12042 uint32_t ptype_num;
12043 struct rte_pmd_i40e_ptype_info *ptype;
12044 uint32_t buff_size;
12046 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12051 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12052 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12053 PMD_DRV_LOG(ERR, "Unsupported operation.");
12057 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12058 rte_pmd_i40e_ptype_mapping_reset(port_id);
12062 /* get information about new ptype num */
12063 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12064 (uint8_t *)&ptype_num, sizeof(ptype_num),
12065 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12067 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12071 PMD_DRV_LOG(INFO, "No new ptype added");
12075 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12076 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12078 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12082 /* get information about new ptype list */
12083 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12084 (uint8_t *)ptype, buff_size,
12085 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12087 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12092 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12093 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12094 if (!ptype_mapping) {
12095 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12100 /* Update ptype mapping table. */
12101 for (i = 0; i < ptype_num; i++) {
12102 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12103 ptype_mapping[i].sw_ptype = 0;
12105 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12106 proto_id = ptype[i].protocols[j];
12107 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12109 for (n = 0; n < proto_num; n++) {
12110 if (proto[n].proto_id != proto_id)
12112 memset(name, 0, sizeof(name));
12113 strcpy(name, proto[n].name);
12114 PMD_DRV_LOG(INFO, "name = %s\n", name);
12115 if (!strncasecmp(name, "PPPOE", 5))
12116 ptype_mapping[i].sw_ptype |=
12117 RTE_PTYPE_L2_ETHER_PPPOE;
12118 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12120 ptype_mapping[i].sw_ptype |=
12121 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12122 ptype_mapping[i].sw_ptype |=
12124 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12126 ptype_mapping[i].sw_ptype |=
12127 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12128 ptype_mapping[i].sw_ptype |=
12129 RTE_PTYPE_INNER_L4_FRAG;
12130 } else if (!strncasecmp(name, "OIPV4", 5)) {
12131 ptype_mapping[i].sw_ptype |=
12132 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12134 } else if (!strncasecmp(name, "IPV4", 4) &&
12136 ptype_mapping[i].sw_ptype |=
12137 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12138 else if (!strncasecmp(name, "IPV4", 4) &&
12140 ptype_mapping[i].sw_ptype |=
12141 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12142 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12144 ptype_mapping[i].sw_ptype |=
12145 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12146 ptype_mapping[i].sw_ptype |=
12148 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12150 ptype_mapping[i].sw_ptype |=
12151 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12152 ptype_mapping[i].sw_ptype |=
12153 RTE_PTYPE_INNER_L4_FRAG;
12154 } else if (!strncasecmp(name, "OIPV6", 5)) {
12155 ptype_mapping[i].sw_ptype |=
12156 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12158 } else if (!strncasecmp(name, "IPV6", 4) &&
12160 ptype_mapping[i].sw_ptype |=
12161 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12162 else if (!strncasecmp(name, "IPV6", 4) &&
12164 ptype_mapping[i].sw_ptype |=
12165 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12166 else if (!strncasecmp(name, "UDP", 3) &&
12168 ptype_mapping[i].sw_ptype |=
12170 else if (!strncasecmp(name, "UDP", 3) &&
12172 ptype_mapping[i].sw_ptype |=
12173 RTE_PTYPE_INNER_L4_UDP;
12174 else if (!strncasecmp(name, "TCP", 3) &&
12176 ptype_mapping[i].sw_ptype |=
12178 else if (!strncasecmp(name, "TCP", 3) &&
12180 ptype_mapping[i].sw_ptype |=
12181 RTE_PTYPE_INNER_L4_TCP;
12182 else if (!strncasecmp(name, "SCTP", 4) &&
12184 ptype_mapping[i].sw_ptype |=
12186 else if (!strncasecmp(name, "SCTP", 4) &&
12188 ptype_mapping[i].sw_ptype |=
12189 RTE_PTYPE_INNER_L4_SCTP;
12190 else if ((!strncasecmp(name, "ICMP", 4) ||
12191 !strncasecmp(name, "ICMPV6", 6)) &&
12193 ptype_mapping[i].sw_ptype |=
12195 else if ((!strncasecmp(name, "ICMP", 4) ||
12196 !strncasecmp(name, "ICMPV6", 6)) &&
12198 ptype_mapping[i].sw_ptype |=
12199 RTE_PTYPE_INNER_L4_ICMP;
12200 else if (!strncasecmp(name, "GTPC", 4)) {
12201 ptype_mapping[i].sw_ptype |=
12202 RTE_PTYPE_TUNNEL_GTPC;
12204 } else if (!strncasecmp(name, "GTPU", 4)) {
12205 ptype_mapping[i].sw_ptype |=
12206 RTE_PTYPE_TUNNEL_GTPU;
12208 } else if (!strncasecmp(name, "ESP", 3)) {
12209 ptype_mapping[i].sw_ptype |=
12210 RTE_PTYPE_TUNNEL_ESP;
12212 } else if (!strncasecmp(name, "GRENAT", 6)) {
12213 ptype_mapping[i].sw_ptype |=
12214 RTE_PTYPE_TUNNEL_GRENAT;
12216 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12217 !strncasecmp(name, "L2TPV2", 6) ||
12218 !strncasecmp(name, "L2TPV3", 6)) {
12219 ptype_mapping[i].sw_ptype |=
12220 RTE_PTYPE_TUNNEL_L2TP;
12229 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12232 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12234 rte_free(ptype_mapping);
12240 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12241 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12243 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12244 uint32_t proto_num;
12245 struct rte_pmd_i40e_proto_info *proto;
12246 uint32_t buff_size;
12250 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12251 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12252 PMD_DRV_LOG(ERR, "Unsupported operation.");
12256 /* get information about protocol number */
12257 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12258 (uint8_t *)&proto_num, sizeof(proto_num),
12259 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12261 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12265 PMD_DRV_LOG(INFO, "No new protocol added");
12269 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12270 proto = rte_zmalloc("new_proto", buff_size, 0);
12272 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12276 /* get information about protocol list */
12277 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12278 (uint8_t *)proto, buff_size,
12279 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12281 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12286 /* Check if GTP is supported. */
12287 for (i = 0; i < proto_num; i++) {
12288 if (!strncmp(proto[i].name, "GTP", 3)) {
12289 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12290 pf->gtp_support = true;
12292 pf->gtp_support = false;
12297 /* Check if ESP is supported. */
12298 for (i = 0; i < proto_num; i++) {
12299 if (!strncmp(proto[i].name, "ESP", 3)) {
12300 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12301 pf->esp_support = true;
12303 pf->esp_support = false;
12308 /* Update customized pctype info */
12309 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12310 proto_num, proto, op);
12312 PMD_DRV_LOG(INFO, "No pctype is updated.");
12314 /* Update customized ptype info */
12315 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12316 proto_num, proto, op);
12318 PMD_DRV_LOG(INFO, "No ptype is updated.");
12323 /* Create a QinQ cloud filter
12325 * The Fortville NIC has limited resources for tunnel filters,
12326 * so we can only reuse existing filters.
12328 * In step 1 we define which Field Vector fields can be used for
12330 * As we do not have the inner tag defined as a field,
12331 * we have to define it first, by reusing one of L1 entries.
12333 * In step 2 we are replacing one of existing filter types with
12334 * a new one for QinQ.
12335 * As we reusing L1 and replacing L2, some of the default filter
12336 * types will disappear,which depends on L1 and L2 entries we reuse.
12338 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12340 * 1. Create L1 filter of outer vlan (12b) which will be in use
12341 * later when we define the cloud filter.
12342 * a. Valid_flags.replace_cloud = 0
12343 * b. Old_filter = 10 (Stag_Inner_Vlan)
12344 * c. New_filter = 0x10
12345 * d. TR bit = 0xff (optional, not used here)
12346 * e. Buffer – 2 entries:
12347 * i. Byte 0 = 8 (outer vlan FV index).
12349 * Byte 2-3 = 0x0fff
12350 * ii. Byte 0 = 37 (inner vlan FV index).
12352 * Byte 2-3 = 0x0fff
12355 * 2. Create cloud filter using two L1 filters entries: stag and
12356 * new filter(outer vlan+ inner vlan)
12357 * a. Valid_flags.replace_cloud = 1
12358 * b. Old_filter = 1 (instead of outer IP)
12359 * c. New_filter = 0x10
12360 * d. Buffer – 2 entries:
12361 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12362 * Byte 1-3 = 0 (rsv)
12363 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12364 * Byte 9-11 = 0 (rsv)
12367 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12369 int ret = -ENOTSUP;
12370 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12371 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12372 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12373 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12375 if (pf->support_multi_driver) {
12376 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12381 memset(&filter_replace, 0,
12382 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12383 memset(&filter_replace_buf, 0,
12384 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12386 /* create L1 filter */
12387 filter_replace.old_filter_type =
12388 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12389 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12390 filter_replace.tr_bit = 0;
12392 /* Prepare the buffer, 2 entries */
12393 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12394 filter_replace_buf.data[0] |=
12395 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12396 /* Field Vector 12b mask */
12397 filter_replace_buf.data[2] = 0xff;
12398 filter_replace_buf.data[3] = 0x0f;
12399 filter_replace_buf.data[4] =
12400 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12401 filter_replace_buf.data[4] |=
12402 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12403 /* Field Vector 12b mask */
12404 filter_replace_buf.data[6] = 0xff;
12405 filter_replace_buf.data[7] = 0x0f;
12406 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12407 &filter_replace_buf);
12408 if (ret != I40E_SUCCESS)
12411 if (filter_replace.old_filter_type !=
12412 filter_replace.new_filter_type)
12413 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12414 " original: 0x%x, new: 0x%x",
12416 filter_replace.old_filter_type,
12417 filter_replace.new_filter_type);
12419 /* Apply the second L2 cloud filter */
12420 memset(&filter_replace, 0,
12421 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12422 memset(&filter_replace_buf, 0,
12423 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12425 /* create L2 filter, input for L2 filter will be L1 filter */
12426 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12427 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12428 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12430 /* Prepare the buffer, 2 entries */
12431 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12432 filter_replace_buf.data[0] |=
12433 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12434 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12435 filter_replace_buf.data[4] |=
12436 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12437 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12438 &filter_replace_buf);
12439 if (!ret && (filter_replace.old_filter_type !=
12440 filter_replace.new_filter_type))
12441 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12442 " original: 0x%x, new: 0x%x",
12444 filter_replace.old_filter_type,
12445 filter_replace.new_filter_type);
12450 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
12451 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
12452 #ifdef RTE_ETHDEV_DEBUG_RX
12453 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
12455 #ifdef RTE_ETHDEV_DEBUG_TX
12456 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
12459 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12460 ETH_I40E_FLOATING_VEB_ARG "=1"
12461 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12462 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12463 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");