4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
54 #include <rte_tailq.h>
55 #include <rte_hash_crc.h>
57 #include "i40e_logs.h"
58 #include "base/i40e_prototype.h"
59 #include "base/i40e_adminq_cmd.h"
60 #include "base/i40e_type.h"
61 #include "base/i40e_register.h"
62 #include "base/i40e_dcb.h"
63 #include "i40e_ethdev.h"
64 #include "i40e_rxtx.h"
66 #include "i40e_regs.h"
67 #include "rte_pmd_i40e.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and inteval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control default high water */
90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
92 /* Flow control default low water */
93 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
95 /* Flow control enable fwd bit */
96 #define I40E_PRTMAC_FWD_CTRL 0x00000001
98 /* Receive Packet Buffer size */
99 #define I40E_RXPBSIZE (968 * 1024)
101 /* Kilobytes shift */
102 #define I40E_KILOSHIFT 10
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 /* The max bandwidth of i40e is 40Gbps. */
248 #define I40E_QOS_BW_MAX 40000
249 /* The bandwidth should be the multiple of 50Mbps. */
250 #define I40E_QOS_BW_GRANULARITY 50
251 /* The min bandwidth weight is 1. */
252 #define I40E_QOS_BW_WEIGHT_MIN 1
253 /* The max bandwidth weight is 127. */
254 #define I40E_QOS_BW_WEIGHT_MAX 127
256 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
257 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
258 static int i40e_dev_configure(struct rte_eth_dev *dev);
259 static int i40e_dev_start(struct rte_eth_dev *dev);
260 static void i40e_dev_stop(struct rte_eth_dev *dev);
261 static void i40e_dev_close(struct rte_eth_dev *dev);
262 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
263 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
264 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
265 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
266 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
267 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
268 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
269 struct rte_eth_stats *stats);
270 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
271 struct rte_eth_xstat *xstats, unsigned n);
272 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
273 struct rte_eth_xstat_name *xstats_names,
275 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
276 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
280 static int i40e_fw_version_get(struct rte_eth_dev *dev,
281 char *fw_version, size_t fw_size);
282 static void i40e_dev_info_get(struct rte_eth_dev *dev,
283 struct rte_eth_dev_info *dev_info);
284 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
287 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
288 enum rte_vlan_type vlan_type,
290 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
291 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
294 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
295 static int i40e_dev_led_on(struct rte_eth_dev *dev);
296 static int i40e_dev_led_off(struct rte_eth_dev *dev);
297 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
298 struct rte_eth_fc_conf *fc_conf);
299 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
300 struct rte_eth_fc_conf *fc_conf);
301 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
302 struct rte_eth_pfc_conf *pfc_conf);
303 static void i40e_macaddr_add(struct rte_eth_dev *dev,
304 struct ether_addr *mac_addr,
307 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
308 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
309 struct rte_eth_rss_reta_entry64 *reta_conf,
311 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
312 struct rte_eth_rss_reta_entry64 *reta_conf,
315 static int i40e_get_cap(struct i40e_hw *hw);
316 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
317 static int i40e_pf_setup(struct i40e_pf *pf);
318 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
319 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
320 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
321 static int i40e_dcb_setup(struct rte_eth_dev *dev);
322 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
323 bool offset_loaded, uint64_t *offset, uint64_t *stat);
324 static void i40e_stat_update_48(struct i40e_hw *hw,
330 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
331 static void i40e_dev_interrupt_handler(void *param);
332 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
333 uint32_t base, uint32_t num);
334 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
335 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
337 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
339 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
340 static int i40e_veb_release(struct i40e_veb *veb);
341 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
342 struct i40e_vsi *vsi);
343 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
344 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
345 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
346 struct i40e_macvlan_filter *mv_f,
348 struct ether_addr *addr);
349 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
350 struct i40e_macvlan_filter *mv_f,
353 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
354 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
355 struct rte_eth_rss_conf *rss_conf);
356 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
357 struct rte_eth_rss_conf *rss_conf);
358 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
359 struct rte_eth_udp_tunnel *udp_tunnel);
360 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
361 struct rte_eth_udp_tunnel *udp_tunnel);
362 static void i40e_filter_input_set_init(struct i40e_pf *pf);
363 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
364 enum rte_filter_op filter_op,
366 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
367 enum rte_filter_type filter_type,
368 enum rte_filter_op filter_op,
370 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
371 struct rte_eth_dcb_info *dcb_info);
372 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
373 static void i40e_configure_registers(struct i40e_hw *hw);
374 static void i40e_hw_init(struct rte_eth_dev *dev);
375 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
376 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
377 struct rte_eth_mirror_conf *mirror_conf,
378 uint8_t sw_id, uint8_t on);
379 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
381 static int i40e_timesync_enable(struct rte_eth_dev *dev);
382 static int i40e_timesync_disable(struct rte_eth_dev *dev);
383 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
384 struct timespec *timestamp,
386 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
387 struct timespec *timestamp);
388 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
390 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
392 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
393 struct timespec *timestamp);
394 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
395 const struct timespec *timestamp);
397 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
399 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
402 static int i40e_get_regs(struct rte_eth_dev *dev,
403 struct rte_dev_reg_info *regs);
405 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
407 static int i40e_get_eeprom(struct rte_eth_dev *dev,
408 struct rte_dev_eeprom_info *eeprom);
410 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
411 struct ether_addr *mac_addr);
413 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
415 static int i40e_ethertype_filter_convert(
416 const struct rte_eth_ethertype_filter *input,
417 struct i40e_ethertype_filter *filter);
418 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
419 struct i40e_ethertype_filter *filter);
421 static int i40e_tunnel_filter_convert(
422 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
423 struct i40e_tunnel_filter *tunnel_filter);
424 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
425 struct i40e_tunnel_filter *tunnel_filter);
426 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
428 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
429 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
430 static void i40e_filter_restore(struct i40e_pf *pf);
432 int i40e_logtype_init;
433 int i40e_logtype_driver;
435 static const struct rte_pci_id pci_id_i40e_map[] = {
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
452 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
453 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
454 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
455 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
456 { .vendor_id = 0, /* sentinel */ },
459 static const struct eth_dev_ops i40e_eth_dev_ops = {
460 .dev_configure = i40e_dev_configure,
461 .dev_start = i40e_dev_start,
462 .dev_stop = i40e_dev_stop,
463 .dev_close = i40e_dev_close,
464 .promiscuous_enable = i40e_dev_promiscuous_enable,
465 .promiscuous_disable = i40e_dev_promiscuous_disable,
466 .allmulticast_enable = i40e_dev_allmulticast_enable,
467 .allmulticast_disable = i40e_dev_allmulticast_disable,
468 .dev_set_link_up = i40e_dev_set_link_up,
469 .dev_set_link_down = i40e_dev_set_link_down,
470 .link_update = i40e_dev_link_update,
471 .stats_get = i40e_dev_stats_get,
472 .xstats_get = i40e_dev_xstats_get,
473 .xstats_get_names = i40e_dev_xstats_get_names,
474 .stats_reset = i40e_dev_stats_reset,
475 .xstats_reset = i40e_dev_stats_reset,
476 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
477 .fw_version_get = i40e_fw_version_get,
478 .dev_infos_get = i40e_dev_info_get,
479 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
480 .vlan_filter_set = i40e_vlan_filter_set,
481 .vlan_tpid_set = i40e_vlan_tpid_set,
482 .vlan_offload_set = i40e_vlan_offload_set,
483 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
484 .vlan_pvid_set = i40e_vlan_pvid_set,
485 .rx_queue_start = i40e_dev_rx_queue_start,
486 .rx_queue_stop = i40e_dev_rx_queue_stop,
487 .tx_queue_start = i40e_dev_tx_queue_start,
488 .tx_queue_stop = i40e_dev_tx_queue_stop,
489 .rx_queue_setup = i40e_dev_rx_queue_setup,
490 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
491 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
492 .rx_queue_release = i40e_dev_rx_queue_release,
493 .rx_queue_count = i40e_dev_rx_queue_count,
494 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
495 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
496 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
497 .tx_queue_setup = i40e_dev_tx_queue_setup,
498 .tx_queue_release = i40e_dev_tx_queue_release,
499 .dev_led_on = i40e_dev_led_on,
500 .dev_led_off = i40e_dev_led_off,
501 .flow_ctrl_get = i40e_flow_ctrl_get,
502 .flow_ctrl_set = i40e_flow_ctrl_set,
503 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
504 .mac_addr_add = i40e_macaddr_add,
505 .mac_addr_remove = i40e_macaddr_remove,
506 .reta_update = i40e_dev_rss_reta_update,
507 .reta_query = i40e_dev_rss_reta_query,
508 .rss_hash_update = i40e_dev_rss_hash_update,
509 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
510 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
511 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
512 .filter_ctrl = i40e_dev_filter_ctrl,
513 .rxq_info_get = i40e_rxq_info_get,
514 .txq_info_get = i40e_txq_info_get,
515 .mirror_rule_set = i40e_mirror_rule_set,
516 .mirror_rule_reset = i40e_mirror_rule_reset,
517 .timesync_enable = i40e_timesync_enable,
518 .timesync_disable = i40e_timesync_disable,
519 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
520 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
521 .get_dcb_info = i40e_dev_get_dcb_info,
522 .timesync_adjust_time = i40e_timesync_adjust_time,
523 .timesync_read_time = i40e_timesync_read_time,
524 .timesync_write_time = i40e_timesync_write_time,
525 .get_reg = i40e_get_regs,
526 .get_eeprom_length = i40e_get_eeprom_length,
527 .get_eeprom = i40e_get_eeprom,
528 .mac_addr_set = i40e_set_default_mac_addr,
529 .mtu_set = i40e_dev_mtu_set,
532 /* store statistics names and its offset in stats structure */
533 struct rte_i40e_xstats_name_off {
534 char name[RTE_ETH_XSTATS_NAME_SIZE];
538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
539 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
540 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
541 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
542 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
543 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
544 rx_unknown_protocol)},
545 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
546 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
547 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
548 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
552 sizeof(rte_i40e_stats_strings[0]))
554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
555 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
556 tx_dropped_link_down)},
557 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
558 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
560 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
561 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
563 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
567 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
568 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
569 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
570 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
571 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
572 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
580 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
582 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
584 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
588 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
589 mac_short_packet_dropped)},
590 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
592 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
593 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
594 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
600 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
602 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
604 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
606 {"rx_flow_director_atr_match_packets",
607 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
608 {"rx_flow_director_sb_match_packets",
609 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
610 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
612 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
614 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
616 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
621 sizeof(rte_i40e_hw_port_strings[0]))
623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
624 {"xon_packets", offsetof(struct i40e_hw_port_stats,
626 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
631 sizeof(rte_i40e_rxq_prio_strings[0]))
633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
634 {"xon_packets", offsetof(struct i40e_hw_port_stats,
636 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
638 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
639 priority_xon_2_xoff)},
642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
643 sizeof(rte_i40e_txq_prio_strings[0]))
645 static struct eth_driver rte_i40e_pmd = {
647 .id_table = pci_id_i40e_map,
648 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
649 .probe = rte_eth_dev_pci_probe,
650 .remove = rte_eth_dev_pci_remove,
652 .eth_dev_init = eth_i40e_dev_init,
653 .eth_dev_uninit = eth_i40e_dev_uninit,
654 .dev_private_size = sizeof(struct i40e_adapter),
658 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
659 struct rte_eth_link *link)
661 struct rte_eth_link *dst = link;
662 struct rte_eth_link *src = &(dev->data->dev_link);
664 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
665 *(uint64_t *)src) == 0)
672 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
673 struct rte_eth_link *link)
675 struct rte_eth_link *dst = &(dev->data->dev_link);
676 struct rte_eth_link *src = link;
678 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
679 *(uint64_t *)src) == 0)
685 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
686 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
687 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
689 #ifndef I40E_GLQF_ORT
690 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
692 #ifndef I40E_GLQF_PIT
693 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
695 #ifndef I40E_GLQF_L3_MAP
696 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
699 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
702 * Initialize registers for flexible payload, which should be set by NVM.
703 * This should be removed from code once it is fixed in NVM.
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
712 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
713 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
715 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
716 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
718 /* Initialize registers for parsing packet type of QinQ */
719 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
720 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
723 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
726 * Add a ethertype filter to drop all flow control frames transmitted
730 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
732 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
733 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
734 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
735 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
738 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
739 I40E_FLOW_CONTROL_ETHERTYPE, flags,
740 pf->main_vsi_seid, 0,
744 "Failed to add filter to drop flow control frames from VSIs.");
748 floating_veb_list_handler(__rte_unused const char *key,
749 const char *floating_veb_value,
753 unsigned int count = 0;
756 bool *vf_floating_veb = opaque;
758 while (isblank(*floating_veb_value))
759 floating_veb_value++;
761 /* Reset floating VEB configuration for VFs */
762 for (idx = 0; idx < I40E_MAX_VF; idx++)
763 vf_floating_veb[idx] = false;
767 while (isblank(*floating_veb_value))
768 floating_veb_value++;
769 if (*floating_veb_value == '\0')
772 idx = strtoul(floating_veb_value, &end, 10);
773 if (errno || end == NULL)
775 while (isblank(*end))
779 } else if ((*end == ';') || (*end == '\0')) {
781 if (min == I40E_MAX_VF)
783 if (max >= I40E_MAX_VF)
784 max = I40E_MAX_VF - 1;
785 for (idx = min; idx <= max; idx++) {
786 vf_floating_veb[idx] = true;
793 floating_veb_value = end + 1;
794 } while (*end != '\0');
803 config_vf_floating_veb(struct rte_devargs *devargs,
804 uint16_t floating_veb,
805 bool *vf_floating_veb)
807 struct rte_kvargs *kvlist;
809 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
813 /* All the VFs attach to the floating VEB by default
814 * when the floating VEB is enabled.
816 for (i = 0; i < I40E_MAX_VF; i++)
817 vf_floating_veb[i] = true;
822 kvlist = rte_kvargs_parse(devargs->args, NULL);
826 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
827 rte_kvargs_free(kvlist);
830 /* When the floating_veb_list parameter exists, all the VFs
831 * will attach to the legacy VEB firstly, then configure VFs
832 * to the floating VEB according to the floating_veb_list.
834 if (rte_kvargs_process(kvlist, floating_veb_list,
835 floating_veb_list_handler,
836 vf_floating_veb) < 0) {
837 rte_kvargs_free(kvlist);
840 rte_kvargs_free(kvlist);
844 i40e_check_floating_handler(__rte_unused const char *key,
846 __rte_unused void *opaque)
848 if (strcmp(value, "1"))
855 is_floating_veb_supported(struct rte_devargs *devargs)
857 struct rte_kvargs *kvlist;
858 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
863 kvlist = rte_kvargs_parse(devargs->args, NULL);
867 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
868 rte_kvargs_free(kvlist);
871 /* Floating VEB is enabled when there's key-value:
872 * enable_floating_veb=1
874 if (rte_kvargs_process(kvlist, floating_veb_key,
875 i40e_check_floating_handler, NULL) < 0) {
876 rte_kvargs_free(kvlist);
879 rte_kvargs_free(kvlist);
885 config_floating_veb(struct rte_eth_dev *dev)
887 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
888 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
889 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
891 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
893 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
895 is_floating_veb_supported(pci_dev->device.devargs);
896 config_vf_floating_veb(pci_dev->device.devargs,
898 pf->floating_veb_list);
900 pf->floating_veb = false;
904 #define I40E_L2_TAGS_S_TAG_SHIFT 1
905 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
908 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
910 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
911 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
912 char ethertype_hash_name[RTE_HASH_NAMESIZE];
915 struct rte_hash_parameters ethertype_hash_params = {
916 .name = ethertype_hash_name,
917 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
918 .key_len = sizeof(struct i40e_ethertype_filter_input),
919 .hash_func = rte_hash_crc,
920 .hash_func_init_val = 0,
921 .socket_id = rte_socket_id(),
924 /* Initialize ethertype filter rule list and hash */
925 TAILQ_INIT(ðertype_rule->ethertype_list);
926 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
927 "ethertype_%s", dev->data->name);
928 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
929 if (!ethertype_rule->hash_table) {
930 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
933 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
934 sizeof(struct i40e_ethertype_filter *) *
935 I40E_MAX_ETHERTYPE_FILTER_NUM,
937 if (!ethertype_rule->hash_map) {
939 "Failed to allocate memory for ethertype hash map!");
941 goto err_ethertype_hash_map_alloc;
946 err_ethertype_hash_map_alloc:
947 rte_hash_free(ethertype_rule->hash_table);
953 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
956 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
957 char tunnel_hash_name[RTE_HASH_NAMESIZE];
960 struct rte_hash_parameters tunnel_hash_params = {
961 .name = tunnel_hash_name,
962 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
963 .key_len = sizeof(struct i40e_tunnel_filter_input),
964 .hash_func = rte_hash_crc,
965 .hash_func_init_val = 0,
966 .socket_id = rte_socket_id(),
969 /* Initialize tunnel filter rule list and hash */
970 TAILQ_INIT(&tunnel_rule->tunnel_list);
971 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
972 "tunnel_%s", dev->data->name);
973 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
974 if (!tunnel_rule->hash_table) {
975 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
978 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
979 sizeof(struct i40e_tunnel_filter *) *
980 I40E_MAX_TUNNEL_FILTER_NUM,
982 if (!tunnel_rule->hash_map) {
984 "Failed to allocate memory for tunnel hash map!");
986 goto err_tunnel_hash_map_alloc;
991 err_tunnel_hash_map_alloc:
992 rte_hash_free(tunnel_rule->hash_table);
998 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001 struct i40e_fdir_info *fdir_info = &pf->fdir;
1002 char fdir_hash_name[RTE_HASH_NAMESIZE];
1005 struct rte_hash_parameters fdir_hash_params = {
1006 .name = fdir_hash_name,
1007 .entries = I40E_MAX_FDIR_FILTER_NUM,
1008 .key_len = sizeof(struct rte_eth_fdir_input),
1009 .hash_func = rte_hash_crc,
1010 .hash_func_init_val = 0,
1011 .socket_id = rte_socket_id(),
1014 /* Initialize flow director filter rule list and hash */
1015 TAILQ_INIT(&fdir_info->fdir_list);
1016 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1017 "fdir_%s", dev->data->name);
1018 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1019 if (!fdir_info->hash_table) {
1020 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1023 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1024 sizeof(struct i40e_fdir_filter *) *
1025 I40E_MAX_FDIR_FILTER_NUM,
1027 if (!fdir_info->hash_map) {
1029 "Failed to allocate memory for fdir hash map!");
1031 goto err_fdir_hash_map_alloc;
1035 err_fdir_hash_map_alloc:
1036 rte_hash_free(fdir_info->hash_table);
1042 eth_i40e_dev_init(struct rte_eth_dev *dev)
1044 struct rte_pci_device *pci_dev;
1045 struct rte_intr_handle *intr_handle;
1046 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1047 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1048 struct i40e_vsi *vsi;
1051 uint8_t aq_fail = 0;
1053 PMD_INIT_FUNC_TRACE();
1055 dev->dev_ops = &i40e_eth_dev_ops;
1056 dev->rx_pkt_burst = i40e_recv_pkts;
1057 dev->tx_pkt_burst = i40e_xmit_pkts;
1058 dev->tx_pkt_prepare = i40e_prep_pkts;
1060 /* for secondary processes, we don't initialise any further as primary
1061 * has already done this work. Only check we don't need a different
1063 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1064 i40e_set_rx_function(dev);
1065 i40e_set_tx_function(dev);
1068 pci_dev = I40E_DEV_TO_PCI(dev);
1069 intr_handle = &pci_dev->intr_handle;
1071 rte_eth_copy_pci_info(dev, pci_dev);
1072 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1074 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1075 pf->adapter->eth_dev = dev;
1076 pf->dev_data = dev->data;
1078 hw->back = I40E_PF_TO_ADAPTER(pf);
1079 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1082 "Hardware is not available, as address is NULL");
1086 hw->vendor_id = pci_dev->id.vendor_id;
1087 hw->device_id = pci_dev->id.device_id;
1088 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1089 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1090 hw->bus.device = pci_dev->addr.devid;
1091 hw->bus.func = pci_dev->addr.function;
1092 hw->adapter_stopped = 0;
1094 /* Make sure all is clean before doing PF reset */
1097 /* Initialize the hardware */
1100 /* Reset here to make sure all is clean for each PF */
1101 ret = i40e_pf_reset(hw);
1103 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1107 /* Initialize the shared code (base driver) */
1108 ret = i40e_init_shared_code(hw);
1110 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1115 * To work around the NVM issue, initialize registers
1116 * for flexible payload and packet type of QinQ by
1117 * software. It should be removed once issues are fixed
1120 i40e_GLQF_reg_init(hw);
1122 /* Initialize the input set for filters (hash and fd) to default value */
1123 i40e_filter_input_set_init(pf);
1125 /* Initialize the parameters for adminq */
1126 i40e_init_adminq_parameter(hw);
1127 ret = i40e_init_adminq(hw);
1128 if (ret != I40E_SUCCESS) {
1129 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1132 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1133 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1134 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1135 ((hw->nvm.version >> 12) & 0xf),
1136 ((hw->nvm.version >> 4) & 0xff),
1137 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1139 /* initialise the L3_MAP register */
1140 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1143 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1145 /* Need the special FW version to support floating VEB */
1146 config_floating_veb(dev);
1147 /* Clear PXE mode */
1148 i40e_clear_pxe_mode(hw);
1149 ret = i40e_dev_sync_phy_type(hw);
1151 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1152 goto err_sync_phy_type;
1155 * On X710, performance number is far from the expectation on recent
1156 * firmware versions. The fix for this issue may not be integrated in
1157 * the following firmware version. So the workaround in software driver
1158 * is needed. It needs to modify the initial values of 3 internal only
1159 * registers. Note that the workaround can be removed when it is fixed
1160 * in firmware in the future.
1162 i40e_configure_registers(hw);
1164 /* Get hw capabilities */
1165 ret = i40e_get_cap(hw);
1166 if (ret != I40E_SUCCESS) {
1167 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1168 goto err_get_capabilities;
1171 /* Initialize parameters for PF */
1172 ret = i40e_pf_parameter_init(dev);
1174 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1175 goto err_parameter_init;
1178 /* Initialize the queue management */
1179 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1181 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1182 goto err_qp_pool_init;
1184 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1185 hw->func_caps.num_msix_vectors - 1);
1187 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1188 goto err_msix_pool_init;
1191 /* Initialize lan hmc */
1192 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1193 hw->func_caps.num_rx_qp, 0, 0);
1194 if (ret != I40E_SUCCESS) {
1195 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1196 goto err_init_lan_hmc;
1199 /* Configure lan hmc */
1200 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1201 if (ret != I40E_SUCCESS) {
1202 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1203 goto err_configure_lan_hmc;
1206 /* Get and check the mac address */
1207 i40e_get_mac_addr(hw, hw->mac.addr);
1208 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1209 PMD_INIT_LOG(ERR, "mac address is not valid");
1211 goto err_get_mac_addr;
1213 /* Copy the permanent MAC address */
1214 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1215 (struct ether_addr *) hw->mac.perm_addr);
1217 /* Disable flow control */
1218 hw->fc.requested_mode = I40E_FC_NONE;
1219 i40e_set_fc(hw, &aq_fail, TRUE);
1221 /* Set the global registers with default ether type value */
1222 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1223 if (ret != I40E_SUCCESS) {
1225 "Failed to set the default outer VLAN ether type");
1226 goto err_setup_pf_switch;
1229 /* PF setup, which includes VSI setup */
1230 ret = i40e_pf_setup(pf);
1232 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1233 goto err_setup_pf_switch;
1236 /* reset all stats of the device, including pf and main vsi */
1237 i40e_dev_stats_reset(dev);
1241 /* Disable double vlan by default */
1242 i40e_vsi_config_double_vlan(vsi, FALSE);
1244 /* Disable S-TAG identification when floating_veb is disabled */
1245 if (!pf->floating_veb) {
1246 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1247 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1248 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1249 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1253 if (!vsi->max_macaddrs)
1254 len = ETHER_ADDR_LEN;
1256 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1258 /* Should be after VSI initialized */
1259 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1260 if (!dev->data->mac_addrs) {
1262 "Failed to allocated memory for storing mac address");
1265 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1266 &dev->data->mac_addrs[0]);
1268 /* Init dcb to sw mode by default */
1269 ret = i40e_dcb_init_configure(dev, TRUE);
1270 if (ret != I40E_SUCCESS) {
1271 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1272 pf->flags &= ~I40E_FLAG_DCB;
1274 /* Update HW struct after DCB configuration */
1277 /* initialize pf host driver to setup SRIOV resource if applicable */
1278 i40e_pf_host_init(dev);
1280 /* register callback func to eal lib */
1281 rte_intr_callback_register(intr_handle,
1282 i40e_dev_interrupt_handler, dev);
1284 /* configure and enable device interrupt */
1285 i40e_pf_config_irq0(hw, TRUE);
1286 i40e_pf_enable_irq0(hw);
1288 /* enable uio intr after callback register */
1289 rte_intr_enable(intr_handle);
1291 * Add an ethertype filter to drop all flow control frames transmitted
1292 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1295 i40e_add_tx_flow_control_drop_filter(pf);
1297 /* Set the max frame size to 0x2600 by default,
1298 * in case other drivers changed the default value.
1300 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1302 /* initialize mirror rule list */
1303 TAILQ_INIT(&pf->mirror_list);
1305 ret = i40e_init_ethtype_filter_list(dev);
1307 goto err_init_ethtype_filter_list;
1308 ret = i40e_init_tunnel_filter_list(dev);
1310 goto err_init_tunnel_filter_list;
1311 ret = i40e_init_fdir_filter_list(dev);
1313 goto err_init_fdir_filter_list;
1317 err_init_fdir_filter_list:
1318 rte_free(pf->tunnel.hash_table);
1319 rte_free(pf->tunnel.hash_map);
1320 err_init_tunnel_filter_list:
1321 rte_free(pf->ethertype.hash_table);
1322 rte_free(pf->ethertype.hash_map);
1323 err_init_ethtype_filter_list:
1324 rte_free(dev->data->mac_addrs);
1326 i40e_vsi_release(pf->main_vsi);
1327 err_setup_pf_switch:
1329 err_configure_lan_hmc:
1330 (void)i40e_shutdown_lan_hmc(hw);
1332 i40e_res_pool_destroy(&pf->msix_pool);
1334 i40e_res_pool_destroy(&pf->qp_pool);
1337 err_get_capabilities:
1339 (void)i40e_shutdown_adminq(hw);
1345 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1347 struct i40e_ethertype_filter *p_ethertype;
1348 struct i40e_ethertype_rule *ethertype_rule;
1350 ethertype_rule = &pf->ethertype;
1351 /* Remove all ethertype filter rules and hash */
1352 if (ethertype_rule->hash_map)
1353 rte_free(ethertype_rule->hash_map);
1354 if (ethertype_rule->hash_table)
1355 rte_hash_free(ethertype_rule->hash_table);
1357 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1358 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1359 p_ethertype, rules);
1360 rte_free(p_ethertype);
1365 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1367 struct i40e_tunnel_filter *p_tunnel;
1368 struct i40e_tunnel_rule *tunnel_rule;
1370 tunnel_rule = &pf->tunnel;
1371 /* Remove all tunnel director rules and hash */
1372 if (tunnel_rule->hash_map)
1373 rte_free(tunnel_rule->hash_map);
1374 if (tunnel_rule->hash_table)
1375 rte_hash_free(tunnel_rule->hash_table);
1377 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1378 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1384 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1386 struct i40e_fdir_filter *p_fdir;
1387 struct i40e_fdir_info *fdir_info;
1389 fdir_info = &pf->fdir;
1390 /* Remove all flow director rules and hash */
1391 if (fdir_info->hash_map)
1392 rte_free(fdir_info->hash_map);
1393 if (fdir_info->hash_table)
1394 rte_hash_free(fdir_info->hash_table);
1396 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1397 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1403 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1406 struct rte_pci_device *pci_dev;
1407 struct rte_intr_handle *intr_handle;
1409 struct i40e_filter_control_settings settings;
1410 struct rte_flow *p_flow;
1412 uint8_t aq_fail = 0;
1414 PMD_INIT_FUNC_TRACE();
1416 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1419 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1420 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421 pci_dev = I40E_DEV_TO_PCI(dev);
1422 intr_handle = &pci_dev->intr_handle;
1424 if (hw->adapter_stopped == 0)
1425 i40e_dev_close(dev);
1427 dev->dev_ops = NULL;
1428 dev->rx_pkt_burst = NULL;
1429 dev->tx_pkt_burst = NULL;
1431 /* Clear PXE mode */
1432 i40e_clear_pxe_mode(hw);
1434 /* Unconfigure filter control */
1435 memset(&settings, 0, sizeof(settings));
1436 ret = i40e_set_filter_control(hw, &settings);
1438 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1441 /* Disable flow control */
1442 hw->fc.requested_mode = I40E_FC_NONE;
1443 i40e_set_fc(hw, &aq_fail, TRUE);
1445 /* uninitialize pf host driver */
1446 i40e_pf_host_uninit(dev);
1448 rte_free(dev->data->mac_addrs);
1449 dev->data->mac_addrs = NULL;
1451 /* disable uio intr before callback unregister */
1452 rte_intr_disable(intr_handle);
1454 /* register callback func to eal lib */
1455 rte_intr_callback_unregister(intr_handle,
1456 i40e_dev_interrupt_handler, dev);
1458 i40e_rm_ethtype_filter_list(pf);
1459 i40e_rm_tunnel_filter_list(pf);
1460 i40e_rm_fdir_filter_list(pf);
1462 /* Remove all flows */
1463 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1464 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1472 i40e_dev_configure(struct rte_eth_dev *dev)
1474 struct i40e_adapter *ad =
1475 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1476 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1477 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1480 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1481 * bulk allocation or vector Rx preconditions we will reset it.
1483 ad->rx_bulk_alloc_allowed = true;
1484 ad->rx_vec_allowed = true;
1485 ad->tx_simple_allowed = true;
1486 ad->tx_vec_allowed = true;
1488 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1489 ret = i40e_fdir_setup(pf);
1490 if (ret != I40E_SUCCESS) {
1491 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1494 ret = i40e_fdir_configure(dev);
1496 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1500 i40e_fdir_teardown(pf);
1502 ret = i40e_dev_init_vlan(dev);
1507 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1508 * RSS setting have different requirements.
1509 * General PMD driver call sequence are NIC init, configure,
1510 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1511 * will try to lookup the VSI that specific queue belongs to if VMDQ
1512 * applicable. So, VMDQ setting has to be done before
1513 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1514 * For RSS setting, it will try to calculate actual configured RX queue
1515 * number, which will be available after rx_queue_setup(). dev_start()
1516 * function is good to place RSS setup.
1518 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1519 ret = i40e_vmdq_setup(dev);
1524 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1525 ret = i40e_dcb_setup(dev);
1527 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1532 TAILQ_INIT(&pf->flow_list);
1537 /* need to release vmdq resource if exists */
1538 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1539 i40e_vsi_release(pf->vmdq[i].vsi);
1540 pf->vmdq[i].vsi = NULL;
1545 /* need to release fdir resource if exists */
1546 i40e_fdir_teardown(pf);
1551 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1553 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1554 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1555 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1556 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1557 uint16_t msix_vect = vsi->msix_intr;
1560 for (i = 0; i < vsi->nb_qps; i++) {
1561 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1562 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1566 if (vsi->type != I40E_VSI_SRIOV) {
1567 if (!rte_intr_allow_others(intr_handle)) {
1568 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1569 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1571 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1574 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1575 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1577 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1582 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1583 vsi->user_param + (msix_vect - 1);
1585 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1586 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1588 I40E_WRITE_FLUSH(hw);
1592 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1593 int base_queue, int nb_queue)
1597 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1599 /* Bind all RX queues to allocated MSIX interrupt */
1600 for (i = 0; i < nb_queue; i++) {
1601 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1602 I40E_QINT_RQCTL_ITR_INDX_MASK |
1603 ((base_queue + i + 1) <<
1604 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1605 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1606 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1608 if (i == nb_queue - 1)
1609 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1610 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1613 /* Write first RX queue to Link list register as the head element */
1614 if (vsi->type != I40E_VSI_SRIOV) {
1616 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1618 if (msix_vect == I40E_MISC_VEC_ID) {
1619 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1621 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1623 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1625 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1628 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1630 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1632 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1634 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1641 if (msix_vect == I40E_MISC_VEC_ID) {
1643 I40E_VPINT_LNKLST0(vsi->user_param),
1645 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1647 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1649 /* num_msix_vectors_vf needs to minus irq0 */
1650 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1651 vsi->user_param + (msix_vect - 1);
1653 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1655 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1657 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1661 I40E_WRITE_FLUSH(hw);
1665 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1667 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1668 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1669 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1670 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1671 uint16_t msix_vect = vsi->msix_intr;
1672 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1673 uint16_t queue_idx = 0;
1678 for (i = 0; i < vsi->nb_qps; i++) {
1679 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1680 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1683 /* INTENA flag is not auto-cleared for interrupt */
1684 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1685 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1686 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1687 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1688 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1690 /* VF bind interrupt */
1691 if (vsi->type == I40E_VSI_SRIOV) {
1692 __vsi_queues_bind_intr(vsi, msix_vect,
1693 vsi->base_queue, vsi->nb_qps);
1697 /* PF & VMDq bind interrupt */
1698 if (rte_intr_dp_is_en(intr_handle)) {
1699 if (vsi->type == I40E_VSI_MAIN) {
1702 } else if (vsi->type == I40E_VSI_VMDQ2) {
1703 struct i40e_vsi *main_vsi =
1704 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1705 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1710 for (i = 0; i < vsi->nb_used_qps; i++) {
1712 if (!rte_intr_allow_others(intr_handle))
1713 /* allow to share MISC_VEC_ID */
1714 msix_vect = I40E_MISC_VEC_ID;
1716 /* no enough msix_vect, map all to one */
1717 __vsi_queues_bind_intr(vsi, msix_vect,
1718 vsi->base_queue + i,
1719 vsi->nb_used_qps - i);
1720 for (; !!record && i < vsi->nb_used_qps; i++)
1721 intr_handle->intr_vec[queue_idx + i] =
1725 /* 1:1 queue/msix_vect mapping */
1726 __vsi_queues_bind_intr(vsi, msix_vect,
1727 vsi->base_queue + i, 1);
1729 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1737 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1739 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1740 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1741 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1742 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1743 uint16_t interval = i40e_calc_itr_interval(\
1744 RTE_LIBRTE_I40E_ITR_INTERVAL);
1745 uint16_t msix_intr, i;
1747 if (rte_intr_allow_others(intr_handle))
1748 for (i = 0; i < vsi->nb_msix; i++) {
1749 msix_intr = vsi->msix_intr + i;
1750 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1751 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1752 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1753 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1755 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1758 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1759 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1760 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1761 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1763 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1765 I40E_WRITE_FLUSH(hw);
1769 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1771 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1772 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1773 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1774 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1775 uint16_t msix_intr, i;
1777 if (rte_intr_allow_others(intr_handle))
1778 for (i = 0; i < vsi->nb_msix; i++) {
1779 msix_intr = vsi->msix_intr + i;
1780 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1784 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1786 I40E_WRITE_FLUSH(hw);
1789 static inline uint8_t
1790 i40e_parse_link_speeds(uint16_t link_speeds)
1792 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1794 if (link_speeds & ETH_LINK_SPEED_40G)
1795 link_speed |= I40E_LINK_SPEED_40GB;
1796 if (link_speeds & ETH_LINK_SPEED_25G)
1797 link_speed |= I40E_LINK_SPEED_25GB;
1798 if (link_speeds & ETH_LINK_SPEED_20G)
1799 link_speed |= I40E_LINK_SPEED_20GB;
1800 if (link_speeds & ETH_LINK_SPEED_10G)
1801 link_speed |= I40E_LINK_SPEED_10GB;
1802 if (link_speeds & ETH_LINK_SPEED_1G)
1803 link_speed |= I40E_LINK_SPEED_1GB;
1804 if (link_speeds & ETH_LINK_SPEED_100M)
1805 link_speed |= I40E_LINK_SPEED_100MB;
1811 i40e_phy_conf_link(struct i40e_hw *hw,
1813 uint8_t force_speed)
1815 enum i40e_status_code status;
1816 struct i40e_aq_get_phy_abilities_resp phy_ab;
1817 struct i40e_aq_set_phy_config phy_conf;
1818 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1819 I40E_AQ_PHY_FLAG_PAUSE_RX |
1820 I40E_AQ_PHY_FLAG_PAUSE_RX |
1821 I40E_AQ_PHY_FLAG_LOW_POWER;
1822 const uint8_t advt = I40E_LINK_SPEED_40GB |
1823 I40E_LINK_SPEED_25GB |
1824 I40E_LINK_SPEED_10GB |
1825 I40E_LINK_SPEED_1GB |
1826 I40E_LINK_SPEED_100MB;
1830 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1835 memset(&phy_conf, 0, sizeof(phy_conf));
1837 /* bits 0-2 use the values from get_phy_abilities_resp */
1839 abilities |= phy_ab.abilities & mask;
1841 /* update ablities and speed */
1842 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1843 phy_conf.link_speed = advt;
1845 phy_conf.link_speed = force_speed;
1847 phy_conf.abilities = abilities;
1849 /* use get_phy_abilities_resp value for the rest */
1850 phy_conf.phy_type = phy_ab.phy_type;
1851 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1852 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1853 phy_conf.eee_capability = phy_ab.eee_capability;
1854 phy_conf.eeer = phy_ab.eeer_val;
1855 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1857 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1858 phy_ab.abilities, phy_ab.link_speed);
1859 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1860 phy_conf.abilities, phy_conf.link_speed);
1862 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1866 return I40E_SUCCESS;
1870 i40e_apply_link_speed(struct rte_eth_dev *dev)
1873 uint8_t abilities = 0;
1874 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1875 struct rte_eth_conf *conf = &dev->data->dev_conf;
1877 speed = i40e_parse_link_speeds(conf->link_speeds);
1878 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1879 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1880 abilities |= I40E_AQ_PHY_AN_ENABLED;
1881 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1883 /* Skip changing speed on 40G interfaces, FW does not support */
1884 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1885 speed = I40E_LINK_SPEED_UNKNOWN;
1886 abilities |= I40E_AQ_PHY_AN_ENABLED;
1889 return i40e_phy_conf_link(hw, abilities, speed);
1893 i40e_dev_start(struct rte_eth_dev *dev)
1895 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1896 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897 struct i40e_vsi *main_vsi = pf->main_vsi;
1899 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1900 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1901 uint32_t intr_vector = 0;
1902 struct i40e_vsi *vsi;
1904 hw->adapter_stopped = 0;
1906 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1907 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1908 dev->data->port_id);
1912 rte_intr_disable(intr_handle);
1914 if ((rte_intr_cap_multiple(intr_handle) ||
1915 !RTE_ETH_DEV_SRIOV(dev).active) &&
1916 dev->data->dev_conf.intr_conf.rxq != 0) {
1917 intr_vector = dev->data->nb_rx_queues;
1918 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1923 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1924 intr_handle->intr_vec =
1925 rte_zmalloc("intr_vec",
1926 dev->data->nb_rx_queues * sizeof(int),
1928 if (!intr_handle->intr_vec) {
1930 "Failed to allocate %d rx_queues intr_vec",
1931 dev->data->nb_rx_queues);
1936 /* Initialize VSI */
1937 ret = i40e_dev_rxtx_init(pf);
1938 if (ret != I40E_SUCCESS) {
1939 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1943 /* Map queues with MSIX interrupt */
1944 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1945 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1946 i40e_vsi_queues_bind_intr(main_vsi);
1947 i40e_vsi_enable_queues_intr(main_vsi);
1949 /* Map VMDQ VSI queues with MSIX interrupt */
1950 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1951 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1952 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1953 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1956 /* enable FDIR MSIX interrupt */
1957 if (pf->fdir.fdir_vsi) {
1958 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1959 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1962 /* Enable all queues which have been configured */
1963 ret = i40e_dev_switch_queues(pf, TRUE);
1964 if (ret != I40E_SUCCESS) {
1965 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1969 /* Enable receiving broadcast packets */
1970 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1971 if (ret != I40E_SUCCESS)
1972 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1974 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1975 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1977 if (ret != I40E_SUCCESS)
1978 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1981 /* Enable the VLAN promiscuous mode. */
1983 for (i = 0; i < pf->vf_num; i++) {
1984 vsi = pf->vfs[i].vsi;
1985 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1990 /* Apply link configure */
1991 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1992 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1993 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1994 ETH_LINK_SPEED_40G)) {
1995 PMD_DRV_LOG(ERR, "Invalid link setting");
1998 ret = i40e_apply_link_speed(dev);
1999 if (I40E_SUCCESS != ret) {
2000 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2004 if (!rte_intr_allow_others(intr_handle)) {
2005 rte_intr_callback_unregister(intr_handle,
2006 i40e_dev_interrupt_handler,
2008 /* configure and enable device interrupt */
2009 i40e_pf_config_irq0(hw, FALSE);
2010 i40e_pf_enable_irq0(hw);
2012 if (dev->data->dev_conf.intr_conf.lsc != 0)
2014 "lsc won't enable because of no intr multiplex");
2015 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2016 ret = i40e_aq_set_phy_int_mask(hw,
2017 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2018 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2019 I40E_AQ_EVENT_MEDIA_NA), NULL);
2020 if (ret != I40E_SUCCESS)
2021 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2023 /* Call get_link_info aq commond to enable LSE */
2024 i40e_dev_link_update(dev, 0);
2027 /* enable uio intr after callback register */
2028 rte_intr_enable(intr_handle);
2030 i40e_filter_restore(pf);
2032 return I40E_SUCCESS;
2035 i40e_dev_switch_queues(pf, FALSE);
2036 i40e_dev_clear_queues(dev);
2042 i40e_dev_stop(struct rte_eth_dev *dev)
2044 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2045 struct i40e_vsi *main_vsi = pf->main_vsi;
2046 struct i40e_mirror_rule *p_mirror;
2047 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2048 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2051 /* Disable all queues */
2052 i40e_dev_switch_queues(pf, FALSE);
2054 /* un-map queues with interrupt registers */
2055 i40e_vsi_disable_queues_intr(main_vsi);
2056 i40e_vsi_queues_unbind_intr(main_vsi);
2058 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2059 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2060 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2063 if (pf->fdir.fdir_vsi) {
2064 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2065 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2067 /* Clear all queues and release memory */
2068 i40e_dev_clear_queues(dev);
2071 i40e_dev_set_link_down(dev);
2073 /* Remove all mirror rules */
2074 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2075 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2078 pf->nb_mirror_rule = 0;
2080 if (!rte_intr_allow_others(intr_handle))
2081 /* resume to the default handler */
2082 rte_intr_callback_register(intr_handle,
2083 i40e_dev_interrupt_handler,
2086 /* Clean datapath event and queue/vec mapping */
2087 rte_intr_efd_disable(intr_handle);
2088 if (intr_handle->intr_vec) {
2089 rte_free(intr_handle->intr_vec);
2090 intr_handle->intr_vec = NULL;
2095 i40e_dev_close(struct rte_eth_dev *dev)
2097 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2098 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2100 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2104 PMD_INIT_FUNC_TRACE();
2107 hw->adapter_stopped = 1;
2108 i40e_dev_free_queues(dev);
2110 /* Disable interrupt */
2111 i40e_pf_disable_irq0(hw);
2112 rte_intr_disable(intr_handle);
2114 /* shutdown and destroy the HMC */
2115 i40e_shutdown_lan_hmc(hw);
2117 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2118 i40e_vsi_release(pf->vmdq[i].vsi);
2119 pf->vmdq[i].vsi = NULL;
2124 /* release all the existing VSIs and VEBs */
2125 i40e_fdir_teardown(pf);
2126 i40e_vsi_release(pf->main_vsi);
2128 /* shutdown the adminq */
2129 i40e_aq_queue_shutdown(hw, true);
2130 i40e_shutdown_adminq(hw);
2132 i40e_res_pool_destroy(&pf->qp_pool);
2133 i40e_res_pool_destroy(&pf->msix_pool);
2135 /* force a PF reset to clean anything leftover */
2136 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2137 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2138 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2139 I40E_WRITE_FLUSH(hw);
2143 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2145 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2146 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2147 struct i40e_vsi *vsi = pf->main_vsi;
2150 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2152 if (status != I40E_SUCCESS)
2153 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2155 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2157 if (status != I40E_SUCCESS)
2158 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2163 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2165 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2166 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167 struct i40e_vsi *vsi = pf->main_vsi;
2170 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2172 if (status != I40E_SUCCESS)
2173 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2175 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2177 if (status != I40E_SUCCESS)
2178 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2182 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2184 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2185 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186 struct i40e_vsi *vsi = pf->main_vsi;
2189 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2190 if (ret != I40E_SUCCESS)
2191 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2195 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2197 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2198 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2199 struct i40e_vsi *vsi = pf->main_vsi;
2202 if (dev->data->promiscuous == 1)
2203 return; /* must remain in all_multicast mode */
2205 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2206 vsi->seid, FALSE, NULL);
2207 if (ret != I40E_SUCCESS)
2208 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2212 * Set device link up.
2215 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2217 /* re-apply link speed setting */
2218 return i40e_apply_link_speed(dev);
2222 * Set device link down.
2225 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2227 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2228 uint8_t abilities = 0;
2229 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2231 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2232 return i40e_phy_conf_link(hw, abilities, speed);
2236 i40e_dev_link_update(struct rte_eth_dev *dev,
2237 int wait_to_complete)
2239 #define CHECK_INTERVAL 100 /* 100ms */
2240 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2241 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242 struct i40e_link_status link_status;
2243 struct rte_eth_link link, old;
2245 unsigned rep_cnt = MAX_REPEAT_TIME;
2246 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2248 memset(&link, 0, sizeof(link));
2249 memset(&old, 0, sizeof(old));
2250 memset(&link_status, 0, sizeof(link_status));
2251 rte_i40e_dev_atomic_read_link_status(dev, &old);
2254 /* Get link status information from hardware */
2255 status = i40e_aq_get_link_info(hw, enable_lse,
2256 &link_status, NULL);
2257 if (status != I40E_SUCCESS) {
2258 link.link_speed = ETH_SPEED_NUM_100M;
2259 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2260 PMD_DRV_LOG(ERR, "Failed to get link info");
2264 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2265 if (!wait_to_complete || link.link_status)
2268 rte_delay_ms(CHECK_INTERVAL);
2269 } while (--rep_cnt);
2271 if (!link.link_status)
2274 /* i40e uses full duplex only */
2275 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2277 /* Parse the link status */
2278 switch (link_status.link_speed) {
2279 case I40E_LINK_SPEED_100MB:
2280 link.link_speed = ETH_SPEED_NUM_100M;
2282 case I40E_LINK_SPEED_1GB:
2283 link.link_speed = ETH_SPEED_NUM_1G;
2285 case I40E_LINK_SPEED_10GB:
2286 link.link_speed = ETH_SPEED_NUM_10G;
2288 case I40E_LINK_SPEED_20GB:
2289 link.link_speed = ETH_SPEED_NUM_20G;
2291 case I40E_LINK_SPEED_25GB:
2292 link.link_speed = ETH_SPEED_NUM_25G;
2294 case I40E_LINK_SPEED_40GB:
2295 link.link_speed = ETH_SPEED_NUM_40G;
2298 link.link_speed = ETH_SPEED_NUM_100M;
2302 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2303 ETH_LINK_SPEED_FIXED);
2306 rte_i40e_dev_atomic_write_link_status(dev, &link);
2307 if (link.link_status == old.link_status)
2313 /* Get all the statistics of a VSI */
2315 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2317 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2318 struct i40e_eth_stats *nes = &vsi->eth_stats;
2319 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2320 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2322 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2323 vsi->offset_loaded, &oes->rx_bytes,
2325 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2326 vsi->offset_loaded, &oes->rx_unicast,
2328 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2329 vsi->offset_loaded, &oes->rx_multicast,
2330 &nes->rx_multicast);
2331 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2332 vsi->offset_loaded, &oes->rx_broadcast,
2333 &nes->rx_broadcast);
2334 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2335 &oes->rx_discards, &nes->rx_discards);
2336 /* GLV_REPC not supported */
2337 /* GLV_RMPC not supported */
2338 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2339 &oes->rx_unknown_protocol,
2340 &nes->rx_unknown_protocol);
2341 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2342 vsi->offset_loaded, &oes->tx_bytes,
2344 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2345 vsi->offset_loaded, &oes->tx_unicast,
2347 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2348 vsi->offset_loaded, &oes->tx_multicast,
2349 &nes->tx_multicast);
2350 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2351 vsi->offset_loaded, &oes->tx_broadcast,
2352 &nes->tx_broadcast);
2353 /* GLV_TDPC not supported */
2354 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2355 &oes->tx_errors, &nes->tx_errors);
2356 vsi->offset_loaded = true;
2358 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2360 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2361 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2362 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2363 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2364 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2365 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2366 nes->rx_unknown_protocol);
2367 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2368 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2369 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2370 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2371 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2372 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2373 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2378 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2381 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2382 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2384 /* Get statistics of struct i40e_eth_stats */
2385 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2386 I40E_GLPRT_GORCL(hw->port),
2387 pf->offset_loaded, &os->eth.rx_bytes,
2389 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2390 I40E_GLPRT_UPRCL(hw->port),
2391 pf->offset_loaded, &os->eth.rx_unicast,
2392 &ns->eth.rx_unicast);
2393 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2394 I40E_GLPRT_MPRCL(hw->port),
2395 pf->offset_loaded, &os->eth.rx_multicast,
2396 &ns->eth.rx_multicast);
2397 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2398 I40E_GLPRT_BPRCL(hw->port),
2399 pf->offset_loaded, &os->eth.rx_broadcast,
2400 &ns->eth.rx_broadcast);
2401 /* Workaround: CRC size should not be included in byte statistics,
2402 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2404 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2405 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2407 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2408 pf->offset_loaded, &os->eth.rx_discards,
2409 &ns->eth.rx_discards);
2410 /* GLPRT_REPC not supported */
2411 /* GLPRT_RMPC not supported */
2412 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2414 &os->eth.rx_unknown_protocol,
2415 &ns->eth.rx_unknown_protocol);
2416 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2417 I40E_GLPRT_GOTCL(hw->port),
2418 pf->offset_loaded, &os->eth.tx_bytes,
2420 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2421 I40E_GLPRT_UPTCL(hw->port),
2422 pf->offset_loaded, &os->eth.tx_unicast,
2423 &ns->eth.tx_unicast);
2424 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2425 I40E_GLPRT_MPTCL(hw->port),
2426 pf->offset_loaded, &os->eth.tx_multicast,
2427 &ns->eth.tx_multicast);
2428 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2429 I40E_GLPRT_BPTCL(hw->port),
2430 pf->offset_loaded, &os->eth.tx_broadcast,
2431 &ns->eth.tx_broadcast);
2432 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2433 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2434 /* GLPRT_TEPC not supported */
2436 /* additional port specific stats */
2437 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2438 pf->offset_loaded, &os->tx_dropped_link_down,
2439 &ns->tx_dropped_link_down);
2440 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2441 pf->offset_loaded, &os->crc_errors,
2443 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2444 pf->offset_loaded, &os->illegal_bytes,
2445 &ns->illegal_bytes);
2446 /* GLPRT_ERRBC not supported */
2447 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2448 pf->offset_loaded, &os->mac_local_faults,
2449 &ns->mac_local_faults);
2450 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2451 pf->offset_loaded, &os->mac_remote_faults,
2452 &ns->mac_remote_faults);
2453 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2454 pf->offset_loaded, &os->rx_length_errors,
2455 &ns->rx_length_errors);
2456 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2457 pf->offset_loaded, &os->link_xon_rx,
2459 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2460 pf->offset_loaded, &os->link_xoff_rx,
2462 for (i = 0; i < 8; i++) {
2463 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2465 &os->priority_xon_rx[i],
2466 &ns->priority_xon_rx[i]);
2467 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2469 &os->priority_xoff_rx[i],
2470 &ns->priority_xoff_rx[i]);
2472 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2473 pf->offset_loaded, &os->link_xon_tx,
2475 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2476 pf->offset_loaded, &os->link_xoff_tx,
2478 for (i = 0; i < 8; i++) {
2479 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2481 &os->priority_xon_tx[i],
2482 &ns->priority_xon_tx[i]);
2483 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2485 &os->priority_xoff_tx[i],
2486 &ns->priority_xoff_tx[i]);
2487 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2489 &os->priority_xon_2_xoff[i],
2490 &ns->priority_xon_2_xoff[i]);
2492 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2493 I40E_GLPRT_PRC64L(hw->port),
2494 pf->offset_loaded, &os->rx_size_64,
2496 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2497 I40E_GLPRT_PRC127L(hw->port),
2498 pf->offset_loaded, &os->rx_size_127,
2500 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2501 I40E_GLPRT_PRC255L(hw->port),
2502 pf->offset_loaded, &os->rx_size_255,
2504 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2505 I40E_GLPRT_PRC511L(hw->port),
2506 pf->offset_loaded, &os->rx_size_511,
2508 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2509 I40E_GLPRT_PRC1023L(hw->port),
2510 pf->offset_loaded, &os->rx_size_1023,
2512 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2513 I40E_GLPRT_PRC1522L(hw->port),
2514 pf->offset_loaded, &os->rx_size_1522,
2516 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2517 I40E_GLPRT_PRC9522L(hw->port),
2518 pf->offset_loaded, &os->rx_size_big,
2520 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2521 pf->offset_loaded, &os->rx_undersize,
2523 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2524 pf->offset_loaded, &os->rx_fragments,
2526 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2527 pf->offset_loaded, &os->rx_oversize,
2529 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2530 pf->offset_loaded, &os->rx_jabber,
2532 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2533 I40E_GLPRT_PTC64L(hw->port),
2534 pf->offset_loaded, &os->tx_size_64,
2536 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2537 I40E_GLPRT_PTC127L(hw->port),
2538 pf->offset_loaded, &os->tx_size_127,
2540 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2541 I40E_GLPRT_PTC255L(hw->port),
2542 pf->offset_loaded, &os->tx_size_255,
2544 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2545 I40E_GLPRT_PTC511L(hw->port),
2546 pf->offset_loaded, &os->tx_size_511,
2548 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2549 I40E_GLPRT_PTC1023L(hw->port),
2550 pf->offset_loaded, &os->tx_size_1023,
2552 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2553 I40E_GLPRT_PTC1522L(hw->port),
2554 pf->offset_loaded, &os->tx_size_1522,
2556 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2557 I40E_GLPRT_PTC9522L(hw->port),
2558 pf->offset_loaded, &os->tx_size_big,
2560 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2562 &os->fd_sb_match, &ns->fd_sb_match);
2563 /* GLPRT_MSPDC not supported */
2564 /* GLPRT_XEC not supported */
2566 pf->offset_loaded = true;
2569 i40e_update_vsi_stats(pf->main_vsi);
2572 /* Get all statistics of a port */
2574 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2576 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2577 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2581 /* call read registers - updates values, now write them to struct */
2582 i40e_read_stats_registers(pf, hw);
2584 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2585 pf->main_vsi->eth_stats.rx_multicast +
2586 pf->main_vsi->eth_stats.rx_broadcast -
2587 pf->main_vsi->eth_stats.rx_discards;
2588 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2589 pf->main_vsi->eth_stats.tx_multicast +
2590 pf->main_vsi->eth_stats.tx_broadcast;
2591 stats->ibytes = ns->eth.rx_bytes;
2592 stats->obytes = ns->eth.tx_bytes;
2593 stats->oerrors = ns->eth.tx_errors +
2594 pf->main_vsi->eth_stats.tx_errors;
2597 stats->imissed = ns->eth.rx_discards +
2598 pf->main_vsi->eth_stats.rx_discards;
2599 stats->ierrors = ns->crc_errors +
2600 ns->rx_length_errors + ns->rx_undersize +
2601 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2603 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2604 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2605 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2606 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2607 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2608 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2609 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2610 ns->eth.rx_unknown_protocol);
2611 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2612 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2613 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2614 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2615 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2616 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2618 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2619 ns->tx_dropped_link_down);
2620 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2621 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2623 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2624 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2625 ns->mac_local_faults);
2626 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2627 ns->mac_remote_faults);
2628 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2629 ns->rx_length_errors);
2630 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2631 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2632 for (i = 0; i < 8; i++) {
2633 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2634 i, ns->priority_xon_rx[i]);
2635 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2636 i, ns->priority_xoff_rx[i]);
2638 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2639 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2640 for (i = 0; i < 8; i++) {
2641 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2642 i, ns->priority_xon_tx[i]);
2643 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2644 i, ns->priority_xoff_tx[i]);
2645 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2646 i, ns->priority_xon_2_xoff[i]);
2648 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2649 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2650 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2651 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2652 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2653 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2654 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2655 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2656 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2657 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2658 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2659 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2660 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2661 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2662 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2663 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2664 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2665 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2666 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2667 ns->mac_short_packet_dropped);
2668 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2669 ns->checksum_error);
2670 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2671 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2674 /* Reset the statistics */
2676 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2678 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2679 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681 /* Mark PF and VSI stats to update the offset, aka "reset" */
2682 pf->offset_loaded = false;
2684 pf->main_vsi->offset_loaded = false;
2686 /* read the stats, reading current register values into offset */
2687 i40e_read_stats_registers(pf, hw);
2691 i40e_xstats_calc_num(void)
2693 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2694 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2695 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2698 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2699 struct rte_eth_xstat_name *xstats_names,
2700 __rte_unused unsigned limit)
2705 if (xstats_names == NULL)
2706 return i40e_xstats_calc_num();
2708 /* Note: limit checked in rte_eth_xstats_names() */
2710 /* Get stats from i40e_eth_stats struct */
2711 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2712 snprintf(xstats_names[count].name,
2713 sizeof(xstats_names[count].name),
2714 "%s", rte_i40e_stats_strings[i].name);
2718 /* Get individiual stats from i40e_hw_port struct */
2719 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2720 snprintf(xstats_names[count].name,
2721 sizeof(xstats_names[count].name),
2722 "%s", rte_i40e_hw_port_strings[i].name);
2726 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2727 for (prio = 0; prio < 8; prio++) {
2728 snprintf(xstats_names[count].name,
2729 sizeof(xstats_names[count].name),
2730 "rx_priority%u_%s", prio,
2731 rte_i40e_rxq_prio_strings[i].name);
2736 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2737 for (prio = 0; prio < 8; prio++) {
2738 snprintf(xstats_names[count].name,
2739 sizeof(xstats_names[count].name),
2740 "tx_priority%u_%s", prio,
2741 rte_i40e_txq_prio_strings[i].name);
2749 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2752 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2753 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2754 unsigned i, count, prio;
2755 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2757 count = i40e_xstats_calc_num();
2761 i40e_read_stats_registers(pf, hw);
2768 /* Get stats from i40e_eth_stats struct */
2769 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2770 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2771 rte_i40e_stats_strings[i].offset);
2772 xstats[count].id = count;
2776 /* Get individiual stats from i40e_hw_port struct */
2777 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2778 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2779 rte_i40e_hw_port_strings[i].offset);
2780 xstats[count].id = count;
2784 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2785 for (prio = 0; prio < 8; prio++) {
2786 xstats[count].value =
2787 *(uint64_t *)(((char *)hw_stats) +
2788 rte_i40e_rxq_prio_strings[i].offset +
2789 (sizeof(uint64_t) * prio));
2790 xstats[count].id = count;
2795 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2796 for (prio = 0; prio < 8; prio++) {
2797 xstats[count].value =
2798 *(uint64_t *)(((char *)hw_stats) +
2799 rte_i40e_txq_prio_strings[i].offset +
2800 (sizeof(uint64_t) * prio));
2801 xstats[count].id = count;
2810 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2811 __rte_unused uint16_t queue_id,
2812 __rte_unused uint8_t stat_idx,
2813 __rte_unused uint8_t is_rx)
2815 PMD_INIT_FUNC_TRACE();
2821 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2823 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2829 full_ver = hw->nvm.oem_ver;
2830 ver = (u8)(full_ver >> 24);
2831 build = (u16)((full_ver >> 8) & 0xffff);
2832 patch = (u8)(full_ver & 0xff);
2834 ret = snprintf(fw_version, fw_size,
2835 "%d.%d%d 0x%08x %d.%d.%d",
2836 ((hw->nvm.version >> 12) & 0xf),
2837 ((hw->nvm.version >> 4) & 0xff),
2838 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2841 ret += 1; /* add the size of '\0' */
2842 if (fw_size < (u32)ret)
2849 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2851 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2852 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2853 struct i40e_vsi *vsi = pf->main_vsi;
2854 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2856 dev_info->pci_dev = pci_dev;
2857 dev_info->max_rx_queues = vsi->nb_qps;
2858 dev_info->max_tx_queues = vsi->nb_qps;
2859 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2860 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2861 dev_info->max_mac_addrs = vsi->max_macaddrs;
2862 dev_info->max_vfs = pci_dev->max_vfs;
2863 dev_info->rx_offload_capa =
2864 DEV_RX_OFFLOAD_VLAN_STRIP |
2865 DEV_RX_OFFLOAD_QINQ_STRIP |
2866 DEV_RX_OFFLOAD_IPV4_CKSUM |
2867 DEV_RX_OFFLOAD_UDP_CKSUM |
2868 DEV_RX_OFFLOAD_TCP_CKSUM;
2869 dev_info->tx_offload_capa =
2870 DEV_TX_OFFLOAD_VLAN_INSERT |
2871 DEV_TX_OFFLOAD_QINQ_INSERT |
2872 DEV_TX_OFFLOAD_IPV4_CKSUM |
2873 DEV_TX_OFFLOAD_UDP_CKSUM |
2874 DEV_TX_OFFLOAD_TCP_CKSUM |
2875 DEV_TX_OFFLOAD_SCTP_CKSUM |
2876 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2877 DEV_TX_OFFLOAD_TCP_TSO |
2878 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2879 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2880 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2881 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2882 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2884 dev_info->reta_size = pf->hash_lut_size;
2885 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2887 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2889 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2890 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2891 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2893 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2897 dev_info->default_txconf = (struct rte_eth_txconf) {
2899 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2900 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2901 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2903 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2904 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2905 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2906 ETH_TXQ_FLAGS_NOOFFLOADS,
2909 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2910 .nb_max = I40E_MAX_RING_DESC,
2911 .nb_min = I40E_MIN_RING_DESC,
2912 .nb_align = I40E_ALIGN_RING_DESC,
2915 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2916 .nb_max = I40E_MAX_RING_DESC,
2917 .nb_min = I40E_MIN_RING_DESC,
2918 .nb_align = I40E_ALIGN_RING_DESC,
2919 .nb_seg_max = I40E_TX_MAX_SEG,
2920 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2923 if (pf->flags & I40E_FLAG_VMDQ) {
2924 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2925 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2926 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2927 pf->max_nb_vmdq_vsi;
2928 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2929 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2930 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2933 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2935 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2936 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2938 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2941 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2945 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2947 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2948 struct i40e_vsi *vsi = pf->main_vsi;
2949 PMD_INIT_FUNC_TRACE();
2952 return i40e_vsi_add_vlan(vsi, vlan_id);
2954 return i40e_vsi_delete_vlan(vsi, vlan_id);
2958 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2959 enum rte_vlan_type vlan_type,
2962 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2963 uint64_t reg_r = 0, reg_w = 0;
2964 uint16_t reg_id = 0;
2966 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2968 switch (vlan_type) {
2969 case ETH_VLAN_TYPE_OUTER:
2975 case ETH_VLAN_TYPE_INNER:
2981 "Unsupported vlan type in single vlan.");
2987 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2990 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2992 if (ret != I40E_SUCCESS) {
2994 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3000 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3003 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3004 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3005 if (reg_r == reg_w) {
3007 PMD_DRV_LOG(DEBUG, "No need to write");
3011 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3013 if (ret != I40E_SUCCESS) {
3016 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3021 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3028 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3030 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3031 struct i40e_vsi *vsi = pf->main_vsi;
3033 if (mask & ETH_VLAN_FILTER_MASK) {
3034 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3035 i40e_vsi_config_vlan_filter(vsi, TRUE);
3037 i40e_vsi_config_vlan_filter(vsi, FALSE);
3040 if (mask & ETH_VLAN_STRIP_MASK) {
3041 /* Enable or disable VLAN stripping */
3042 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3043 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3045 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3048 if (mask & ETH_VLAN_EXTEND_MASK) {
3049 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3050 i40e_vsi_config_double_vlan(vsi, TRUE);
3051 /* Set global registers with default ether type value */
3052 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3054 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3058 i40e_vsi_config_double_vlan(vsi, FALSE);
3063 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3064 __rte_unused uint16_t queue,
3065 __rte_unused int on)
3067 PMD_INIT_FUNC_TRACE();
3071 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3073 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3074 struct i40e_vsi *vsi = pf->main_vsi;
3075 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3076 struct i40e_vsi_vlan_pvid_info info;
3078 memset(&info, 0, sizeof(info));
3081 info.config.pvid = pvid;
3083 info.config.reject.tagged =
3084 data->dev_conf.txmode.hw_vlan_reject_tagged;
3085 info.config.reject.untagged =
3086 data->dev_conf.txmode.hw_vlan_reject_untagged;
3089 return i40e_vsi_vlan_pvid_set(vsi, &info);
3093 i40e_dev_led_on(struct rte_eth_dev *dev)
3095 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3096 uint32_t mode = i40e_led_get(hw);
3099 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3105 i40e_dev_led_off(struct rte_eth_dev *dev)
3107 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3108 uint32_t mode = i40e_led_get(hw);
3111 i40e_led_set(hw, 0, false);
3117 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3119 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3122 fc_conf->pause_time = pf->fc_conf.pause_time;
3123 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3124 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3126 /* Return current mode according to actual setting*/
3127 switch (hw->fc.current_mode) {
3129 fc_conf->mode = RTE_FC_FULL;
3131 case I40E_FC_TX_PAUSE:
3132 fc_conf->mode = RTE_FC_TX_PAUSE;
3134 case I40E_FC_RX_PAUSE:
3135 fc_conf->mode = RTE_FC_RX_PAUSE;
3139 fc_conf->mode = RTE_FC_NONE;
3146 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3148 uint32_t mflcn_reg, fctrl_reg, reg;
3149 uint32_t max_high_water;
3150 uint8_t i, aq_failure;
3154 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3155 [RTE_FC_NONE] = I40E_FC_NONE,
3156 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3157 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3158 [RTE_FC_FULL] = I40E_FC_FULL
3161 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3163 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3164 if ((fc_conf->high_water > max_high_water) ||
3165 (fc_conf->high_water < fc_conf->low_water)) {
3167 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3172 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3173 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3174 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3176 pf->fc_conf.pause_time = fc_conf->pause_time;
3177 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3178 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3180 PMD_INIT_FUNC_TRACE();
3182 /* All the link flow control related enable/disable register
3183 * configuration is handle by the F/W
3185 err = i40e_set_fc(hw, &aq_failure, true);
3189 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3190 /* Configure flow control refresh threshold,
3191 * the value for stat_tx_pause_refresh_timer[8]
3192 * is used for global pause operation.
3196 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3197 pf->fc_conf.pause_time);
3199 /* configure the timer value included in transmitted pause
3201 * the value for stat_tx_pause_quanta[8] is used for global
3204 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3205 pf->fc_conf.pause_time);
3207 fctrl_reg = I40E_READ_REG(hw,
3208 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3210 if (fc_conf->mac_ctrl_frame_fwd != 0)
3211 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3213 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3215 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3218 /* Configure pause time (2 TCs per register) */
3219 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3220 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3221 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3223 /* Configure flow control refresh threshold value */
3224 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3225 pf->fc_conf.pause_time / 2);
3227 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3229 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3230 *depending on configuration
3232 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3233 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3234 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3236 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3237 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3240 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3243 /* config the water marker both based on the packets and bytes */
3244 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3245 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3246 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3247 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3248 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3249 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3250 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3251 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3253 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3254 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3257 I40E_WRITE_FLUSH(hw);
3263 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3264 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3266 PMD_INIT_FUNC_TRACE();
3271 /* Add a MAC address, and update filters */
3273 i40e_macaddr_add(struct rte_eth_dev *dev,
3274 struct ether_addr *mac_addr,
3275 __rte_unused uint32_t index,
3278 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3279 struct i40e_mac_filter_info mac_filter;
3280 struct i40e_vsi *vsi;
3283 /* If VMDQ not enabled or configured, return */
3284 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3285 !pf->nb_cfg_vmdq_vsi)) {
3286 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3287 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3292 if (pool > pf->nb_cfg_vmdq_vsi) {
3293 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3294 pool, pf->nb_cfg_vmdq_vsi);
3298 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3299 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3300 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3302 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3307 vsi = pf->vmdq[pool - 1].vsi;
3309 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3310 if (ret != I40E_SUCCESS) {
3311 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3316 /* Remove a MAC address, and update filters */
3318 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3320 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3321 struct i40e_vsi *vsi;
3322 struct rte_eth_dev_data *data = dev->data;
3323 struct ether_addr *macaddr;
3328 macaddr = &(data->mac_addrs[index]);
3330 pool_sel = dev->data->mac_pool_sel[index];
3332 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3333 if (pool_sel & (1ULL << i)) {
3337 /* No VMDQ pool enabled or configured */
3338 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3339 (i > pf->nb_cfg_vmdq_vsi)) {
3341 "No VMDQ pool enabled/configured");
3344 vsi = pf->vmdq[i - 1].vsi;
3346 ret = i40e_vsi_delete_mac(vsi, macaddr);
3349 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3356 /* Set perfect match or hash match of MAC and VLAN for a VF */
3358 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3359 struct rte_eth_mac_filter *filter,
3363 struct i40e_mac_filter_info mac_filter;
3364 struct ether_addr old_mac;
3365 struct ether_addr *new_mac;
3366 struct i40e_pf_vf *vf = NULL;
3371 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3374 hw = I40E_PF_TO_HW(pf);
3376 if (filter == NULL) {
3377 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3381 new_mac = &filter->mac_addr;
3383 if (is_zero_ether_addr(new_mac)) {
3384 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3388 vf_id = filter->dst_id;
3390 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3391 PMD_DRV_LOG(ERR, "Invalid argument.");
3394 vf = &pf->vfs[vf_id];
3396 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3397 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3402 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3403 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3405 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3408 mac_filter.filter_type = filter->filter_type;
3409 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3410 if (ret != I40E_SUCCESS) {
3411 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3414 ether_addr_copy(new_mac, &pf->dev_addr);
3416 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3418 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3419 if (ret != I40E_SUCCESS) {
3420 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3424 /* Clear device address as it has been removed */
3425 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3426 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3432 /* MAC filter handle */
3434 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3437 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3438 struct rte_eth_mac_filter *filter;
3439 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3440 int ret = I40E_NOT_SUPPORTED;
3442 filter = (struct rte_eth_mac_filter *)(arg);
3444 switch (filter_op) {
3445 case RTE_ETH_FILTER_NOP:
3448 case RTE_ETH_FILTER_ADD:
3449 i40e_pf_disable_irq0(hw);
3451 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3452 i40e_pf_enable_irq0(hw);
3454 case RTE_ETH_FILTER_DELETE:
3455 i40e_pf_disable_irq0(hw);
3457 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3458 i40e_pf_enable_irq0(hw);
3461 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3462 ret = I40E_ERR_PARAM;
3470 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3472 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3473 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3479 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3480 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3483 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3487 uint32_t *lut_dw = (uint32_t *)lut;
3488 uint16_t i, lut_size_dw = lut_size / 4;
3490 for (i = 0; i < lut_size_dw; i++)
3491 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3498 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3507 pf = I40E_VSI_TO_PF(vsi);
3508 hw = I40E_VSI_TO_HW(vsi);
3510 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3511 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3514 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3518 uint32_t *lut_dw = (uint32_t *)lut;
3519 uint16_t i, lut_size_dw = lut_size / 4;
3521 for (i = 0; i < lut_size_dw; i++)
3522 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3523 I40E_WRITE_FLUSH(hw);
3530 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3531 struct rte_eth_rss_reta_entry64 *reta_conf,
3534 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3535 uint16_t i, lut_size = pf->hash_lut_size;
3536 uint16_t idx, shift;
3540 if (reta_size != lut_size ||
3541 reta_size > ETH_RSS_RETA_SIZE_512) {
3543 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3544 reta_size, lut_size);
3548 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3550 PMD_DRV_LOG(ERR, "No memory can be allocated");
3553 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3556 for (i = 0; i < reta_size; i++) {
3557 idx = i / RTE_RETA_GROUP_SIZE;
3558 shift = i % RTE_RETA_GROUP_SIZE;
3559 if (reta_conf[idx].mask & (1ULL << shift))
3560 lut[i] = reta_conf[idx].reta[shift];
3562 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3571 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3572 struct rte_eth_rss_reta_entry64 *reta_conf,
3575 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3576 uint16_t i, lut_size = pf->hash_lut_size;
3577 uint16_t idx, shift;
3581 if (reta_size != lut_size ||
3582 reta_size > ETH_RSS_RETA_SIZE_512) {
3584 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3585 reta_size, lut_size);
3589 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3591 PMD_DRV_LOG(ERR, "No memory can be allocated");
3595 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3598 for (i = 0; i < reta_size; i++) {
3599 idx = i / RTE_RETA_GROUP_SIZE;
3600 shift = i % RTE_RETA_GROUP_SIZE;
3601 if (reta_conf[idx].mask & (1ULL << shift))
3602 reta_conf[idx].reta[shift] = lut[i];
3612 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3613 * @hw: pointer to the HW structure
3614 * @mem: pointer to mem struct to fill out
3615 * @size: size of memory requested
3616 * @alignment: what to align the allocation to
3618 enum i40e_status_code
3619 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3620 struct i40e_dma_mem *mem,
3624 const struct rte_memzone *mz = NULL;
3625 char z_name[RTE_MEMZONE_NAMESIZE];
3628 return I40E_ERR_PARAM;
3630 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3631 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3632 alignment, RTE_PGSIZE_2M);
3634 return I40E_ERR_NO_MEMORY;
3638 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3639 mem->zone = (const void *)mz;
3641 "memzone %s allocated with physical address: %"PRIu64,
3644 return I40E_SUCCESS;
3648 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3649 * @hw: pointer to the HW structure
3650 * @mem: ptr to mem struct to free
3652 enum i40e_status_code
3653 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3654 struct i40e_dma_mem *mem)
3657 return I40E_ERR_PARAM;
3660 "memzone %s to be freed with physical address: %"PRIu64,
3661 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3662 rte_memzone_free((const struct rte_memzone *)mem->zone);
3667 return I40E_SUCCESS;
3671 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3672 * @hw: pointer to the HW structure
3673 * @mem: pointer to mem struct to fill out
3674 * @size: size of memory requested
3676 enum i40e_status_code
3677 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3678 struct i40e_virt_mem *mem,
3682 return I40E_ERR_PARAM;
3685 mem->va = rte_zmalloc("i40e", size, 0);
3688 return I40E_SUCCESS;
3690 return I40E_ERR_NO_MEMORY;
3694 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3695 * @hw: pointer to the HW structure
3696 * @mem: pointer to mem struct to free
3698 enum i40e_status_code
3699 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3700 struct i40e_virt_mem *mem)
3703 return I40E_ERR_PARAM;
3708 return I40E_SUCCESS;
3712 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3714 rte_spinlock_init(&sp->spinlock);
3718 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3720 rte_spinlock_lock(&sp->spinlock);
3724 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3726 rte_spinlock_unlock(&sp->spinlock);
3730 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3736 * Get the hardware capabilities, which will be parsed
3737 * and saved into struct i40e_hw.
3740 i40e_get_cap(struct i40e_hw *hw)
3742 struct i40e_aqc_list_capabilities_element_resp *buf;
3743 uint16_t len, size = 0;
3746 /* Calculate a huge enough buff for saving response data temporarily */
3747 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3748 I40E_MAX_CAP_ELE_NUM;
3749 buf = rte_zmalloc("i40e", len, 0);
3751 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3752 return I40E_ERR_NO_MEMORY;
3755 /* Get, parse the capabilities and save it to hw */
3756 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3757 i40e_aqc_opc_list_func_capabilities, NULL);
3758 if (ret != I40E_SUCCESS)
3759 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3761 /* Free the temporary buffer after being used */
3768 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3770 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3771 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3772 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3773 uint16_t qp_count = 0, vsi_count = 0;
3775 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3776 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3779 /* Add the parameter init for LFC */
3780 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3781 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3782 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3784 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3785 pf->max_num_vsi = hw->func_caps.num_vsis;
3786 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3787 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3788 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3790 /* FDir queue/VSI allocation */
3791 pf->fdir_qp_offset = 0;
3792 if (hw->func_caps.fd) {
3793 pf->flags |= I40E_FLAG_FDIR;
3794 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3796 pf->fdir_nb_qps = 0;
3798 qp_count += pf->fdir_nb_qps;
3801 /* LAN queue/VSI allocation */
3802 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3803 if (!hw->func_caps.rss) {
3806 pf->flags |= I40E_FLAG_RSS;
3807 if (hw->mac.type == I40E_MAC_X722)
3808 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3809 pf->lan_nb_qps = pf->lan_nb_qp_max;
3811 qp_count += pf->lan_nb_qps;
3814 /* VF queue/VSI allocation */
3815 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3816 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3817 pf->flags |= I40E_FLAG_SRIOV;
3818 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3819 pf->vf_num = pci_dev->max_vfs;
3821 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3822 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3827 qp_count += pf->vf_nb_qps * pf->vf_num;
3828 vsi_count += pf->vf_num;
3830 /* VMDq queue/VSI allocation */
3831 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3832 pf->vmdq_nb_qps = 0;
3833 pf->max_nb_vmdq_vsi = 0;
3834 if (hw->func_caps.vmdq) {
3835 if (qp_count < hw->func_caps.num_tx_qp &&
3836 vsi_count < hw->func_caps.num_vsis) {
3837 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3838 qp_count) / pf->vmdq_nb_qp_max;
3840 /* Limit the maximum number of VMDq vsi to the maximum
3841 * ethdev can support
3843 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3844 hw->func_caps.num_vsis - vsi_count);
3845 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3847 if (pf->max_nb_vmdq_vsi) {
3848 pf->flags |= I40E_FLAG_VMDQ;
3849 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3851 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3852 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3853 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3856 "No enough queues left for VMDq");
3859 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3862 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3863 vsi_count += pf->max_nb_vmdq_vsi;
3865 if (hw->func_caps.dcb)
3866 pf->flags |= I40E_FLAG_DCB;
3868 if (qp_count > hw->func_caps.num_tx_qp) {
3870 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3871 qp_count, hw->func_caps.num_tx_qp);
3874 if (vsi_count > hw->func_caps.num_vsis) {
3876 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3877 vsi_count, hw->func_caps.num_vsis);
3885 i40e_pf_get_switch_config(struct i40e_pf *pf)
3887 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3888 struct i40e_aqc_get_switch_config_resp *switch_config;
3889 struct i40e_aqc_switch_config_element_resp *element;
3890 uint16_t start_seid = 0, num_reported;
3893 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3894 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3895 if (!switch_config) {
3896 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3900 /* Get the switch configurations */
3901 ret = i40e_aq_get_switch_config(hw, switch_config,
3902 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3903 if (ret != I40E_SUCCESS) {
3904 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3907 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3908 if (num_reported != 1) { /* The number should be 1 */
3909 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3913 /* Parse the switch configuration elements */
3914 element = &(switch_config->element[0]);
3915 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3916 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3917 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3919 PMD_DRV_LOG(INFO, "Unknown element type");
3922 rte_free(switch_config);
3928 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3931 struct pool_entry *entry;
3933 if (pool == NULL || num == 0)
3936 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3937 if (entry == NULL) {
3938 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3942 /* queue heap initialize */
3943 pool->num_free = num;
3944 pool->num_alloc = 0;
3946 LIST_INIT(&pool->alloc_list);
3947 LIST_INIT(&pool->free_list);
3949 /* Initialize element */
3953 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3958 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3960 struct pool_entry *entry, *next_entry;
3965 for (entry = LIST_FIRST(&pool->alloc_list);
3966 entry && (next_entry = LIST_NEXT(entry, next), 1);
3967 entry = next_entry) {
3968 LIST_REMOVE(entry, next);
3972 for (entry = LIST_FIRST(&pool->free_list);
3973 entry && (next_entry = LIST_NEXT(entry, next), 1);
3974 entry = next_entry) {
3975 LIST_REMOVE(entry, next);
3980 pool->num_alloc = 0;
3982 LIST_INIT(&pool->alloc_list);
3983 LIST_INIT(&pool->free_list);
3987 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3990 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3991 uint32_t pool_offset;
3995 PMD_DRV_LOG(ERR, "Invalid parameter");
3999 pool_offset = base - pool->base;
4000 /* Lookup in alloc list */
4001 LIST_FOREACH(entry, &pool->alloc_list, next) {
4002 if (entry->base == pool_offset) {
4003 valid_entry = entry;
4004 LIST_REMOVE(entry, next);
4009 /* Not find, return */
4010 if (valid_entry == NULL) {
4011 PMD_DRV_LOG(ERR, "Failed to find entry");
4016 * Found it, move it to free list and try to merge.
4017 * In order to make merge easier, always sort it by qbase.
4018 * Find adjacent prev and last entries.
4021 LIST_FOREACH(entry, &pool->free_list, next) {
4022 if (entry->base > valid_entry->base) {
4030 /* Try to merge with next one*/
4032 /* Merge with next one */
4033 if (valid_entry->base + valid_entry->len == next->base) {
4034 next->base = valid_entry->base;
4035 next->len += valid_entry->len;
4036 rte_free(valid_entry);
4043 /* Merge with previous one */
4044 if (prev->base + prev->len == valid_entry->base) {
4045 prev->len += valid_entry->len;
4046 /* If it merge with next one, remove next node */
4048 LIST_REMOVE(valid_entry, next);
4049 rte_free(valid_entry);
4051 rte_free(valid_entry);
4057 /* Not find any entry to merge, insert */
4060 LIST_INSERT_AFTER(prev, valid_entry, next);
4061 else if (next != NULL)
4062 LIST_INSERT_BEFORE(next, valid_entry, next);
4063 else /* It's empty list, insert to head */
4064 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4067 pool->num_free += valid_entry->len;
4068 pool->num_alloc -= valid_entry->len;
4074 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4077 struct pool_entry *entry, *valid_entry;
4079 if (pool == NULL || num == 0) {
4080 PMD_DRV_LOG(ERR, "Invalid parameter");
4084 if (pool->num_free < num) {
4085 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4086 num, pool->num_free);
4091 /* Lookup in free list and find most fit one */
4092 LIST_FOREACH(entry, &pool->free_list, next) {
4093 if (entry->len >= num) {
4095 if (entry->len == num) {
4096 valid_entry = entry;
4099 if (valid_entry == NULL || valid_entry->len > entry->len)
4100 valid_entry = entry;
4104 /* Not find one to satisfy the request, return */
4105 if (valid_entry == NULL) {
4106 PMD_DRV_LOG(ERR, "No valid entry found");
4110 * The entry have equal queue number as requested,
4111 * remove it from alloc_list.
4113 if (valid_entry->len == num) {
4114 LIST_REMOVE(valid_entry, next);
4117 * The entry have more numbers than requested,
4118 * create a new entry for alloc_list and minus its
4119 * queue base and number in free_list.
4121 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4122 if (entry == NULL) {
4124 "Failed to allocate memory for resource pool");
4127 entry->base = valid_entry->base;
4129 valid_entry->base += num;
4130 valid_entry->len -= num;
4131 valid_entry = entry;
4134 /* Insert it into alloc list, not sorted */
4135 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4137 pool->num_free -= valid_entry->len;
4138 pool->num_alloc += valid_entry->len;
4140 return valid_entry->base + pool->base;
4144 * bitmap_is_subset - Check whether src2 is subset of src1
4147 bitmap_is_subset(uint8_t src1, uint8_t src2)
4149 return !((src1 ^ src2) & src2);
4152 static enum i40e_status_code
4153 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4155 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4157 /* If DCB is not supported, only default TC is supported */
4158 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4159 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4160 return I40E_NOT_SUPPORTED;
4163 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4165 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4166 hw->func_caps.enabled_tcmap, enabled_tcmap);
4167 return I40E_NOT_SUPPORTED;
4169 return I40E_SUCCESS;
4173 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4174 struct i40e_vsi_vlan_pvid_info *info)
4177 struct i40e_vsi_context ctxt;
4178 uint8_t vlan_flags = 0;
4181 if (vsi == NULL || info == NULL) {
4182 PMD_DRV_LOG(ERR, "invalid parameters");
4183 return I40E_ERR_PARAM;
4187 vsi->info.pvid = info->config.pvid;
4189 * If insert pvid is enabled, only tagged pkts are
4190 * allowed to be sent out.
4192 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4193 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4196 if (info->config.reject.tagged == 0)
4197 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4199 if (info->config.reject.untagged == 0)
4200 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4202 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4203 I40E_AQ_VSI_PVLAN_MODE_MASK);
4204 vsi->info.port_vlan_flags |= vlan_flags;
4205 vsi->info.valid_sections =
4206 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4207 memset(&ctxt, 0, sizeof(ctxt));
4208 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4209 ctxt.seid = vsi->seid;
4211 hw = I40E_VSI_TO_HW(vsi);
4212 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4213 if (ret != I40E_SUCCESS)
4214 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4220 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4222 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4224 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4226 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4227 if (ret != I40E_SUCCESS)
4231 PMD_DRV_LOG(ERR, "seid not valid");
4235 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4236 tc_bw_data.tc_valid_bits = enabled_tcmap;
4237 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4238 tc_bw_data.tc_bw_credits[i] =
4239 (enabled_tcmap & (1 << i)) ? 1 : 0;
4241 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4242 if (ret != I40E_SUCCESS) {
4243 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4247 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4248 sizeof(vsi->info.qs_handle));
4249 return I40E_SUCCESS;
4252 static enum i40e_status_code
4253 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4254 struct i40e_aqc_vsi_properties_data *info,
4255 uint8_t enabled_tcmap)
4257 enum i40e_status_code ret;
4258 int i, total_tc = 0;
4259 uint16_t qpnum_per_tc, bsf, qp_idx;
4261 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4262 if (ret != I40E_SUCCESS)
4265 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4266 if (enabled_tcmap & (1 << i))
4268 vsi->enabled_tc = enabled_tcmap;
4270 /* Number of queues per enabled TC */
4271 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4272 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4273 bsf = rte_bsf32(qpnum_per_tc);
4275 /* Adjust the queue number to actual queues that can be applied */
4276 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4277 vsi->nb_qps = qpnum_per_tc * total_tc;
4280 * Configure TC and queue mapping parameters, for enabled TC,
4281 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4282 * default queue will serve it.
4285 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4286 if (vsi->enabled_tc & (1 << i)) {
4287 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4288 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4289 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4290 qp_idx += qpnum_per_tc;
4292 info->tc_mapping[i] = 0;
4295 /* Associate queue number with VSI */
4296 if (vsi->type == I40E_VSI_SRIOV) {
4297 info->mapping_flags |=
4298 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4299 for (i = 0; i < vsi->nb_qps; i++)
4300 info->queue_mapping[i] =
4301 rte_cpu_to_le_16(vsi->base_queue + i);
4303 info->mapping_flags |=
4304 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4305 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4307 info->valid_sections |=
4308 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4310 return I40E_SUCCESS;
4314 i40e_veb_release(struct i40e_veb *veb)
4316 struct i40e_vsi *vsi;
4322 if (!TAILQ_EMPTY(&veb->head)) {
4323 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4326 /* associate_vsi field is NULL for floating VEB */
4327 if (veb->associate_vsi != NULL) {
4328 vsi = veb->associate_vsi;
4329 hw = I40E_VSI_TO_HW(vsi);
4331 vsi->uplink_seid = veb->uplink_seid;
4334 veb->associate_pf->main_vsi->floating_veb = NULL;
4335 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4338 i40e_aq_delete_element(hw, veb->seid, NULL);
4340 return I40E_SUCCESS;
4344 static struct i40e_veb *
4345 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4347 struct i40e_veb *veb;
4353 "veb setup failed, associated PF shouldn't null");
4356 hw = I40E_PF_TO_HW(pf);
4358 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4360 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4364 veb->associate_vsi = vsi;
4365 veb->associate_pf = pf;
4366 TAILQ_INIT(&veb->head);
4367 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4369 /* create floating veb if vsi is NULL */
4371 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4372 I40E_DEFAULT_TCMAP, false,
4373 &veb->seid, false, NULL);
4375 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4376 true, &veb->seid, false, NULL);
4379 if (ret != I40E_SUCCESS) {
4380 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4381 hw->aq.asq_last_status);
4384 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4386 /* get statistics index */
4387 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4388 &veb->stats_idx, NULL, NULL, NULL);
4389 if (ret != I40E_SUCCESS) {
4390 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4391 hw->aq.asq_last_status);
4394 /* Get VEB bandwidth, to be implemented */
4395 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4397 vsi->uplink_seid = veb->seid;
4406 i40e_vsi_release(struct i40e_vsi *vsi)
4410 struct i40e_vsi_list *vsi_list;
4413 struct i40e_mac_filter *f;
4414 uint16_t user_param;
4417 return I40E_SUCCESS;
4422 user_param = vsi->user_param;
4424 pf = I40E_VSI_TO_PF(vsi);
4425 hw = I40E_VSI_TO_HW(vsi);
4427 /* VSI has child to attach, release child first */
4429 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4430 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4433 i40e_veb_release(vsi->veb);
4436 if (vsi->floating_veb) {
4437 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4438 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4443 /* Remove all macvlan filters of the VSI */
4444 i40e_vsi_remove_all_macvlan_filter(vsi);
4445 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4448 if (vsi->type != I40E_VSI_MAIN &&
4449 ((vsi->type != I40E_VSI_SRIOV) ||
4450 !pf->floating_veb_list[user_param])) {
4451 /* Remove vsi from parent's sibling list */
4452 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4453 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4454 return I40E_ERR_PARAM;
4456 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4457 &vsi->sib_vsi_list, list);
4459 /* Remove all switch element of the VSI */
4460 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4461 if (ret != I40E_SUCCESS)
4462 PMD_DRV_LOG(ERR, "Failed to delete element");
4465 if ((vsi->type == I40E_VSI_SRIOV) &&
4466 pf->floating_veb_list[user_param]) {
4467 /* Remove vsi from parent's sibling list */
4468 if (vsi->parent_vsi == NULL ||
4469 vsi->parent_vsi->floating_veb == NULL) {
4470 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4471 return I40E_ERR_PARAM;
4473 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4474 &vsi->sib_vsi_list, list);
4476 /* Remove all switch element of the VSI */
4477 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4478 if (ret != I40E_SUCCESS)
4479 PMD_DRV_LOG(ERR, "Failed to delete element");
4482 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4484 if (vsi->type != I40E_VSI_SRIOV)
4485 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4488 return I40E_SUCCESS;
4492 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4494 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4495 struct i40e_aqc_remove_macvlan_element_data def_filter;
4496 struct i40e_mac_filter_info filter;
4499 if (vsi->type != I40E_VSI_MAIN)
4500 return I40E_ERR_CONFIG;
4501 memset(&def_filter, 0, sizeof(def_filter));
4502 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4504 def_filter.vlan_tag = 0;
4505 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4506 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4507 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4508 if (ret != I40E_SUCCESS) {
4509 struct i40e_mac_filter *f;
4510 struct ether_addr *mac;
4512 PMD_DRV_LOG(WARNING,
4513 "Cannot remove the default macvlan filter");
4514 /* It needs to add the permanent mac into mac list */
4515 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4517 PMD_DRV_LOG(ERR, "failed to allocate memory");
4518 return I40E_ERR_NO_MEMORY;
4520 mac = &f->mac_info.mac_addr;
4521 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4523 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4524 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4529 (void)rte_memcpy(&filter.mac_addr,
4530 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4531 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4532 return i40e_vsi_add_mac(vsi, &filter);
4536 * i40e_vsi_get_bw_config - Query VSI BW Information
4537 * @vsi: the VSI to be queried
4539 * Returns 0 on success, negative value on failure
4541 static enum i40e_status_code
4542 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4544 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4545 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4546 struct i40e_hw *hw = &vsi->adapter->hw;
4551 memset(&bw_config, 0, sizeof(bw_config));
4552 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4553 if (ret != I40E_SUCCESS) {
4554 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4555 hw->aq.asq_last_status);
4559 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4560 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4561 &ets_sla_config, NULL);
4562 if (ret != I40E_SUCCESS) {
4564 "VSI failed to get TC bandwdith configuration %u",
4565 hw->aq.asq_last_status);
4569 /* store and print out BW info */
4570 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4571 vsi->bw_info.bw_max = bw_config.max_bw;
4572 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4573 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4574 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4575 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4577 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4578 vsi->bw_info.bw_ets_share_credits[i] =
4579 ets_sla_config.share_credits[i];
4580 vsi->bw_info.bw_ets_credits[i] =
4581 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4582 /* 4 bits per TC, 4th bit is reserved */
4583 vsi->bw_info.bw_ets_max[i] =
4584 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4585 RTE_LEN2MASK(3, uint8_t));
4586 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4587 vsi->bw_info.bw_ets_share_credits[i]);
4588 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4589 vsi->bw_info.bw_ets_credits[i]);
4590 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4591 vsi->bw_info.bw_ets_max[i]);
4594 return I40E_SUCCESS;
4597 /* i40e_enable_pf_lb
4598 * @pf: pointer to the pf structure
4600 * allow loopback on pf
4603 i40e_enable_pf_lb(struct i40e_pf *pf)
4605 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4606 struct i40e_vsi_context ctxt;
4609 /* Use the FW API if FW >= v5.0 */
4610 if (hw->aq.fw_maj_ver < 5) {
4611 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4615 memset(&ctxt, 0, sizeof(ctxt));
4616 ctxt.seid = pf->main_vsi_seid;
4617 ctxt.pf_num = hw->pf_id;
4618 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4620 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4621 ret, hw->aq.asq_last_status);
4624 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4625 ctxt.info.valid_sections =
4626 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4627 ctxt.info.switch_id |=
4628 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4630 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4632 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4633 hw->aq.asq_last_status);
4638 i40e_vsi_setup(struct i40e_pf *pf,
4639 enum i40e_vsi_type type,
4640 struct i40e_vsi *uplink_vsi,
4641 uint16_t user_param)
4643 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4644 struct i40e_vsi *vsi;
4645 struct i40e_mac_filter_info filter;
4647 struct i40e_vsi_context ctxt;
4648 struct ether_addr broadcast =
4649 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4651 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4652 uplink_vsi == NULL) {
4654 "VSI setup failed, VSI link shouldn't be NULL");
4658 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4660 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4665 * 1.type is not MAIN and uplink vsi is not NULL
4666 * If uplink vsi didn't setup VEB, create one first under veb field
4667 * 2.type is SRIOV and the uplink is NULL
4668 * If floating VEB is NULL, create one veb under floating veb field
4671 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4672 uplink_vsi->veb == NULL) {
4673 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4675 if (uplink_vsi->veb == NULL) {
4676 PMD_DRV_LOG(ERR, "VEB setup failed");
4679 /* set ALLOWLOOPBACk on pf, when veb is created */
4680 i40e_enable_pf_lb(pf);
4683 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4684 pf->main_vsi->floating_veb == NULL) {
4685 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4687 if (pf->main_vsi->floating_veb == NULL) {
4688 PMD_DRV_LOG(ERR, "VEB setup failed");
4693 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4695 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4698 TAILQ_INIT(&vsi->mac_list);
4700 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4701 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4702 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4703 vsi->user_param = user_param;
4704 vsi->vlan_anti_spoof_on = 0;
4705 vsi->vlan_filter_on = 0;
4706 /* Allocate queues */
4707 switch (vsi->type) {
4708 case I40E_VSI_MAIN :
4709 vsi->nb_qps = pf->lan_nb_qps;
4711 case I40E_VSI_SRIOV :
4712 vsi->nb_qps = pf->vf_nb_qps;
4714 case I40E_VSI_VMDQ2:
4715 vsi->nb_qps = pf->vmdq_nb_qps;
4718 vsi->nb_qps = pf->fdir_nb_qps;
4724 * The filter status descriptor is reported in rx queue 0,
4725 * while the tx queue for fdir filter programming has no
4726 * such constraints, can be non-zero queues.
4727 * To simplify it, choose FDIR vsi use queue 0 pair.
4728 * To make sure it will use queue 0 pair, queue allocation
4729 * need be done before this function is called
4731 if (type != I40E_VSI_FDIR) {
4732 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4734 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4738 vsi->base_queue = ret;
4740 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4742 /* VF has MSIX interrupt in VF range, don't allocate here */
4743 if (type == I40E_VSI_MAIN) {
4744 ret = i40e_res_pool_alloc(&pf->msix_pool,
4745 RTE_MIN(vsi->nb_qps,
4746 RTE_MAX_RXTX_INTR_VEC_ID));
4748 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4750 goto fail_queue_alloc;
4752 vsi->msix_intr = ret;
4753 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4754 } else if (type != I40E_VSI_SRIOV) {
4755 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4757 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4758 goto fail_queue_alloc;
4760 vsi->msix_intr = ret;
4768 if (type == I40E_VSI_MAIN) {
4769 /* For main VSI, no need to add since it's default one */
4770 vsi->uplink_seid = pf->mac_seid;
4771 vsi->seid = pf->main_vsi_seid;
4772 /* Bind queues with specific MSIX interrupt */
4774 * Needs 2 interrupt at least, one for misc cause which will
4775 * enabled from OS side, Another for queues binding the
4776 * interrupt from device side only.
4779 /* Get default VSI parameters from hardware */
4780 memset(&ctxt, 0, sizeof(ctxt));
4781 ctxt.seid = vsi->seid;
4782 ctxt.pf_num = hw->pf_id;
4783 ctxt.uplink_seid = vsi->uplink_seid;
4785 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4786 if (ret != I40E_SUCCESS) {
4787 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4788 goto fail_msix_alloc;
4790 (void)rte_memcpy(&vsi->info, &ctxt.info,
4791 sizeof(struct i40e_aqc_vsi_properties_data));
4792 vsi->vsi_id = ctxt.vsi_number;
4793 vsi->info.valid_sections = 0;
4795 /* Configure tc, enabled TC0 only */
4796 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4798 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4799 goto fail_msix_alloc;
4802 /* TC, queue mapping */
4803 memset(&ctxt, 0, sizeof(ctxt));
4804 vsi->info.valid_sections |=
4805 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4806 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4807 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4808 (void)rte_memcpy(&ctxt.info, &vsi->info,
4809 sizeof(struct i40e_aqc_vsi_properties_data));
4810 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4811 I40E_DEFAULT_TCMAP);
4812 if (ret != I40E_SUCCESS) {
4814 "Failed to configure TC queue mapping");
4815 goto fail_msix_alloc;
4817 ctxt.seid = vsi->seid;
4818 ctxt.pf_num = hw->pf_id;
4819 ctxt.uplink_seid = vsi->uplink_seid;
4822 /* Update VSI parameters */
4823 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4824 if (ret != I40E_SUCCESS) {
4825 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4826 goto fail_msix_alloc;
4829 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4830 sizeof(vsi->info.tc_mapping));
4831 (void)rte_memcpy(&vsi->info.queue_mapping,
4832 &ctxt.info.queue_mapping,
4833 sizeof(vsi->info.queue_mapping));
4834 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4835 vsi->info.valid_sections = 0;
4837 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4841 * Updating default filter settings are necessary to prevent
4842 * reception of tagged packets.
4843 * Some old firmware configurations load a default macvlan
4844 * filter which accepts both tagged and untagged packets.
4845 * The updating is to use a normal filter instead if needed.
4846 * For NVM 4.2.2 or after, the updating is not needed anymore.
4847 * The firmware with correct configurations load the default
4848 * macvlan filter which is expected and cannot be removed.
4850 i40e_update_default_filter_setting(vsi);
4851 i40e_config_qinq(hw, vsi);
4852 } else if (type == I40E_VSI_SRIOV) {
4853 memset(&ctxt, 0, sizeof(ctxt));
4855 * For other VSI, the uplink_seid equals to uplink VSI's
4856 * uplink_seid since they share same VEB
4858 if (uplink_vsi == NULL)
4859 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4861 vsi->uplink_seid = uplink_vsi->uplink_seid;
4862 ctxt.pf_num = hw->pf_id;
4863 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4864 ctxt.uplink_seid = vsi->uplink_seid;
4865 ctxt.connection_type = 0x1;
4866 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4868 /* Use the VEB configuration if FW >= v5.0 */
4869 if (hw->aq.fw_maj_ver >= 5) {
4870 /* Configure switch ID */
4871 ctxt.info.valid_sections |=
4872 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4873 ctxt.info.switch_id =
4874 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4877 /* Configure port/vlan */
4878 ctxt.info.valid_sections |=
4879 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4880 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4881 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4882 hw->func_caps.enabled_tcmap);
4883 if (ret != I40E_SUCCESS) {
4885 "Failed to configure TC queue mapping");
4886 goto fail_msix_alloc;
4889 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4890 ctxt.info.valid_sections |=
4891 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4893 * Since VSI is not created yet, only configure parameter,
4894 * will add vsi below.
4897 i40e_config_qinq(hw, vsi);
4898 } else if (type == I40E_VSI_VMDQ2) {
4899 memset(&ctxt, 0, sizeof(ctxt));
4901 * For other VSI, the uplink_seid equals to uplink VSI's
4902 * uplink_seid since they share same VEB
4904 vsi->uplink_seid = uplink_vsi->uplink_seid;
4905 ctxt.pf_num = hw->pf_id;
4907 ctxt.uplink_seid = vsi->uplink_seid;
4908 ctxt.connection_type = 0x1;
4909 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4911 ctxt.info.valid_sections |=
4912 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4913 /* user_param carries flag to enable loop back */
4915 ctxt.info.switch_id =
4916 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4917 ctxt.info.switch_id |=
4918 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4921 /* Configure port/vlan */
4922 ctxt.info.valid_sections |=
4923 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4924 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4925 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4926 I40E_DEFAULT_TCMAP);
4927 if (ret != I40E_SUCCESS) {
4929 "Failed to configure TC queue mapping");
4930 goto fail_msix_alloc;
4932 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4933 ctxt.info.valid_sections |=
4934 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4935 } else if (type == I40E_VSI_FDIR) {
4936 memset(&ctxt, 0, sizeof(ctxt));
4937 vsi->uplink_seid = uplink_vsi->uplink_seid;
4938 ctxt.pf_num = hw->pf_id;
4940 ctxt.uplink_seid = vsi->uplink_seid;
4941 ctxt.connection_type = 0x1; /* regular data port */
4942 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4943 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4944 I40E_DEFAULT_TCMAP);
4945 if (ret != I40E_SUCCESS) {
4947 "Failed to configure TC queue mapping.");
4948 goto fail_msix_alloc;
4950 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4951 ctxt.info.valid_sections |=
4952 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4954 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4955 goto fail_msix_alloc;
4958 if (vsi->type != I40E_VSI_MAIN) {
4959 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4960 if (ret != I40E_SUCCESS) {
4961 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4962 hw->aq.asq_last_status);
4963 goto fail_msix_alloc;
4965 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4966 vsi->info.valid_sections = 0;
4967 vsi->seid = ctxt.seid;
4968 vsi->vsi_id = ctxt.vsi_number;
4969 vsi->sib_vsi_list.vsi = vsi;
4970 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4971 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4972 &vsi->sib_vsi_list, list);
4974 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4975 &vsi->sib_vsi_list, list);
4979 /* MAC/VLAN configuration */
4980 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4981 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4983 ret = i40e_vsi_add_mac(vsi, &filter);
4984 if (ret != I40E_SUCCESS) {
4985 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4986 goto fail_msix_alloc;
4989 /* Get VSI BW information */
4990 i40e_vsi_get_bw_config(vsi);
4993 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4995 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5001 /* Configure vlan filter on or off */
5003 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5006 struct i40e_mac_filter *f;
5008 struct i40e_mac_filter_info *mac_filter;
5009 enum rte_mac_filter_type desired_filter;
5010 int ret = I40E_SUCCESS;
5013 /* Filter to match MAC and VLAN */
5014 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5016 /* Filter to match only MAC */
5017 desired_filter = RTE_MAC_PERFECT_MATCH;
5022 mac_filter = rte_zmalloc("mac_filter_info_data",
5023 num * sizeof(*mac_filter), 0);
5024 if (mac_filter == NULL) {
5025 PMD_DRV_LOG(ERR, "failed to allocate memory");
5026 return I40E_ERR_NO_MEMORY;
5031 /* Remove all existing mac */
5032 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5033 mac_filter[i] = f->mac_info;
5034 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5036 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5037 on ? "enable" : "disable");
5043 /* Override with new filter */
5044 for (i = 0; i < num; i++) {
5045 mac_filter[i].filter_type = desired_filter;
5046 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5048 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5049 on ? "enable" : "disable");
5055 rte_free(mac_filter);
5059 /* Configure vlan stripping on or off */
5061 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5063 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5064 struct i40e_vsi_context ctxt;
5066 int ret = I40E_SUCCESS;
5068 /* Check if it has been already on or off */
5069 if (vsi->info.valid_sections &
5070 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5072 if ((vsi->info.port_vlan_flags &
5073 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5074 return 0; /* already on */
5076 if ((vsi->info.port_vlan_flags &
5077 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5078 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5079 return 0; /* already off */
5084 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5086 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5087 vsi->info.valid_sections =
5088 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5089 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5090 vsi->info.port_vlan_flags |= vlan_flags;
5091 ctxt.seid = vsi->seid;
5092 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5093 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5095 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5096 on ? "enable" : "disable");
5102 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5104 struct rte_eth_dev_data *data = dev->data;
5108 /* Apply vlan offload setting */
5109 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5110 i40e_vlan_offload_set(dev, mask);
5112 /* Apply double-vlan setting, not implemented yet */
5114 /* Apply pvid setting */
5115 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5116 data->dev_conf.txmode.hw_vlan_insert_pvid);
5118 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5124 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5126 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5128 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5132 i40e_update_flow_control(struct i40e_hw *hw)
5134 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5135 struct i40e_link_status link_status;
5136 uint32_t rxfc = 0, txfc = 0, reg;
5140 memset(&link_status, 0, sizeof(link_status));
5141 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5142 if (ret != I40E_SUCCESS) {
5143 PMD_DRV_LOG(ERR, "Failed to get link status information");
5144 goto write_reg; /* Disable flow control */
5147 an_info = hw->phy.link_info.an_info;
5148 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5149 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5150 ret = I40E_ERR_NOT_READY;
5151 goto write_reg; /* Disable flow control */
5154 * If link auto negotiation is enabled, flow control needs to
5155 * be configured according to it
5157 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5158 case I40E_LINK_PAUSE_RXTX:
5161 hw->fc.current_mode = I40E_FC_FULL;
5163 case I40E_AQ_LINK_PAUSE_RX:
5165 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5167 case I40E_AQ_LINK_PAUSE_TX:
5169 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5172 hw->fc.current_mode = I40E_FC_NONE;
5177 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5178 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5179 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5180 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5181 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5182 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5189 i40e_pf_setup(struct i40e_pf *pf)
5191 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5192 struct i40e_filter_control_settings settings;
5193 struct i40e_vsi *vsi;
5196 /* Clear all stats counters */
5197 pf->offset_loaded = FALSE;
5198 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5199 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5201 ret = i40e_pf_get_switch_config(pf);
5202 if (ret != I40E_SUCCESS) {
5203 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5206 if (pf->flags & I40E_FLAG_FDIR) {
5207 /* make queue allocated first, let FDIR use queue pair 0*/
5208 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5209 if (ret != I40E_FDIR_QUEUE_ID) {
5211 "queue allocation fails for FDIR: ret =%d",
5213 pf->flags &= ~I40E_FLAG_FDIR;
5216 /* main VSI setup */
5217 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5219 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5220 return I40E_ERR_NOT_READY;
5224 /* Configure filter control */
5225 memset(&settings, 0, sizeof(settings));
5226 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5227 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5228 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5229 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5231 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5232 hw->func_caps.rss_table_size);
5233 return I40E_ERR_PARAM;
5235 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5236 hw->func_caps.rss_table_size);
5237 pf->hash_lut_size = hw->func_caps.rss_table_size;
5239 /* Enable ethtype and macvlan filters */
5240 settings.enable_ethtype = TRUE;
5241 settings.enable_macvlan = TRUE;
5242 ret = i40e_set_filter_control(hw, &settings);
5244 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5247 /* Update flow control according to the auto negotiation */
5248 i40e_update_flow_control(hw);
5250 return I40E_SUCCESS;
5254 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5260 * Set or clear TX Queue Disable flags,
5261 * which is required by hardware.
5263 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5264 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5266 /* Wait until the request is finished */
5267 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5268 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5269 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5270 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5271 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5277 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5278 return I40E_SUCCESS; /* already on, skip next steps */
5280 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5281 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5283 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5284 return I40E_SUCCESS; /* already off, skip next steps */
5285 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5287 /* Write the register */
5288 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5289 /* Check the result */
5290 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5291 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5292 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5294 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5295 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5298 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5299 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5303 /* Check if it is timeout */
5304 if (j >= I40E_CHK_Q_ENA_COUNT) {
5305 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5306 (on ? "enable" : "disable"), q_idx);
5307 return I40E_ERR_TIMEOUT;
5310 return I40E_SUCCESS;
5313 /* Swith on or off the tx queues */
5315 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5317 struct rte_eth_dev_data *dev_data = pf->dev_data;
5318 struct i40e_tx_queue *txq;
5319 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5323 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5324 txq = dev_data->tx_queues[i];
5325 /* Don't operate the queue if not configured or
5326 * if starting only per queue */
5327 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5330 ret = i40e_dev_tx_queue_start(dev, i);
5332 ret = i40e_dev_tx_queue_stop(dev, i);
5333 if ( ret != I40E_SUCCESS)
5337 return I40E_SUCCESS;
5341 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5346 /* Wait until the request is finished */
5347 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5348 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5349 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5350 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5351 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5356 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5357 return I40E_SUCCESS; /* Already on, skip next steps */
5358 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5360 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5361 return I40E_SUCCESS; /* Already off, skip next steps */
5362 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5365 /* Write the register */
5366 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5367 /* Check the result */
5368 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5369 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5370 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5372 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5373 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5376 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5377 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5382 /* Check if it is timeout */
5383 if (j >= I40E_CHK_Q_ENA_COUNT) {
5384 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5385 (on ? "enable" : "disable"), q_idx);
5386 return I40E_ERR_TIMEOUT;
5389 return I40E_SUCCESS;
5391 /* Switch on or off the rx queues */
5393 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5395 struct rte_eth_dev_data *dev_data = pf->dev_data;
5396 struct i40e_rx_queue *rxq;
5397 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5401 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5402 rxq = dev_data->rx_queues[i];
5403 /* Don't operate the queue if not configured or
5404 * if starting only per queue */
5405 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5408 ret = i40e_dev_rx_queue_start(dev, i);
5410 ret = i40e_dev_rx_queue_stop(dev, i);
5411 if (ret != I40E_SUCCESS)
5415 return I40E_SUCCESS;
5418 /* Switch on or off all the rx/tx queues */
5420 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5425 /* enable rx queues before enabling tx queues */
5426 ret = i40e_dev_switch_rx_queues(pf, on);
5428 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5431 ret = i40e_dev_switch_tx_queues(pf, on);
5433 /* Stop tx queues before stopping rx queues */
5434 ret = i40e_dev_switch_tx_queues(pf, on);
5436 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5439 ret = i40e_dev_switch_rx_queues(pf, on);
5445 /* Initialize VSI for TX */
5447 i40e_dev_tx_init(struct i40e_pf *pf)
5449 struct rte_eth_dev_data *data = pf->dev_data;
5451 uint32_t ret = I40E_SUCCESS;
5452 struct i40e_tx_queue *txq;
5454 for (i = 0; i < data->nb_tx_queues; i++) {
5455 txq = data->tx_queues[i];
5456 if (!txq || !txq->q_set)
5458 ret = i40e_tx_queue_init(txq);
5459 if (ret != I40E_SUCCESS)
5462 if (ret == I40E_SUCCESS)
5463 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5469 /* Initialize VSI for RX */
5471 i40e_dev_rx_init(struct i40e_pf *pf)
5473 struct rte_eth_dev_data *data = pf->dev_data;
5474 int ret = I40E_SUCCESS;
5476 struct i40e_rx_queue *rxq;
5478 i40e_pf_config_mq_rx(pf);
5479 for (i = 0; i < data->nb_rx_queues; i++) {
5480 rxq = data->rx_queues[i];
5481 if (!rxq || !rxq->q_set)
5484 ret = i40e_rx_queue_init(rxq);
5485 if (ret != I40E_SUCCESS) {
5487 "Failed to do RX queue initialization");
5491 if (ret == I40E_SUCCESS)
5492 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5499 i40e_dev_rxtx_init(struct i40e_pf *pf)
5503 err = i40e_dev_tx_init(pf);
5505 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5508 err = i40e_dev_rx_init(pf);
5510 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5518 i40e_vmdq_setup(struct rte_eth_dev *dev)
5520 struct rte_eth_conf *conf = &dev->data->dev_conf;
5521 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5522 int i, err, conf_vsis, j, loop;
5523 struct i40e_vsi *vsi;
5524 struct i40e_vmdq_info *vmdq_info;
5525 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5526 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5529 * Disable interrupt to avoid message from VF. Furthermore, it will
5530 * avoid race condition in VSI creation/destroy.
5532 i40e_pf_disable_irq0(hw);
5534 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5535 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5539 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5540 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5541 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5542 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5543 pf->max_nb_vmdq_vsi);
5547 if (pf->vmdq != NULL) {
5548 PMD_INIT_LOG(INFO, "VMDQ already configured");
5552 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5553 sizeof(*vmdq_info) * conf_vsis, 0);
5555 if (pf->vmdq == NULL) {
5556 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5560 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5562 /* Create VMDQ VSI */
5563 for (i = 0; i < conf_vsis; i++) {
5564 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5565 vmdq_conf->enable_loop_back);
5567 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5571 vmdq_info = &pf->vmdq[i];
5573 vmdq_info->vsi = vsi;
5575 pf->nb_cfg_vmdq_vsi = conf_vsis;
5577 /* Configure Vlan */
5578 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5579 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5580 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5581 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5582 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5583 vmdq_conf->pool_map[i].vlan_id, j);
5585 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5586 vmdq_conf->pool_map[i].vlan_id);
5588 PMD_INIT_LOG(ERR, "Failed to add vlan");
5596 i40e_pf_enable_irq0(hw);
5601 for (i = 0; i < conf_vsis; i++)
5602 if (pf->vmdq[i].vsi == NULL)
5605 i40e_vsi_release(pf->vmdq[i].vsi);
5609 i40e_pf_enable_irq0(hw);
5614 i40e_stat_update_32(struct i40e_hw *hw,
5622 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5626 if (new_data >= *offset)
5627 *stat = (uint64_t)(new_data - *offset);
5629 *stat = (uint64_t)((new_data +
5630 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5634 i40e_stat_update_48(struct i40e_hw *hw,
5643 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5644 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5645 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5650 if (new_data >= *offset)
5651 *stat = new_data - *offset;
5653 *stat = (uint64_t)((new_data +
5654 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5656 *stat &= I40E_48_BIT_MASK;
5661 i40e_pf_disable_irq0(struct i40e_hw *hw)
5663 /* Disable all interrupt types */
5664 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5665 I40E_WRITE_FLUSH(hw);
5670 i40e_pf_enable_irq0(struct i40e_hw *hw)
5672 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5673 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5674 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5675 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5676 I40E_WRITE_FLUSH(hw);
5680 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5682 /* read pending request and disable first */
5683 i40e_pf_disable_irq0(hw);
5684 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5685 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5686 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5689 /* Link no queues with irq0 */
5690 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5691 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5695 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5697 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5698 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5701 uint32_t index, offset, val;
5706 * Try to find which VF trigger a reset, use absolute VF id to access
5707 * since the reg is global register.
5709 for (i = 0; i < pf->vf_num; i++) {
5710 abs_vf_id = hw->func_caps.vf_base_id + i;
5711 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5712 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5713 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5714 /* VFR event occured */
5715 if (val & (0x1 << offset)) {
5718 /* Clear the event first */
5719 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5721 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5723 * Only notify a VF reset event occured,
5724 * don't trigger another SW reset
5726 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5727 if (ret != I40E_SUCCESS)
5728 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5734 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5736 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5737 struct i40e_virtchnl_pf_event event;
5740 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5741 event.event_data.link_event.link_status =
5742 dev->data->dev_link.link_status;
5743 event.event_data.link_event.link_speed =
5744 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5746 for (i = 0; i < pf->vf_num; i++)
5747 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5748 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5752 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5754 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5755 struct i40e_arq_event_info info;
5756 uint16_t pending, opcode;
5759 info.buf_len = I40E_AQ_BUF_SZ;
5760 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5761 if (!info.msg_buf) {
5762 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5768 ret = i40e_clean_arq_element(hw, &info, &pending);
5770 if (ret != I40E_SUCCESS) {
5772 "Failed to read msg from AdminQ, aq_err: %u",
5773 hw->aq.asq_last_status);
5776 opcode = rte_le_to_cpu_16(info.desc.opcode);
5779 case i40e_aqc_opc_send_msg_to_pf:
5780 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5781 i40e_pf_host_handle_vf_msg(dev,
5782 rte_le_to_cpu_16(info.desc.retval),
5783 rte_le_to_cpu_32(info.desc.cookie_high),
5784 rte_le_to_cpu_32(info.desc.cookie_low),
5788 case i40e_aqc_opc_get_link_status:
5789 ret = i40e_dev_link_update(dev, 0);
5791 i40e_notify_all_vfs_link_status(dev);
5792 _rte_eth_dev_callback_process(dev,
5793 RTE_ETH_EVENT_INTR_LSC, NULL);
5797 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5802 rte_free(info.msg_buf);
5806 * Interrupt handler triggered by NIC for handling
5807 * specific interrupt.
5810 * Pointer to interrupt handle.
5812 * The address of parameter (struct rte_eth_dev *) regsitered before.
5818 i40e_dev_interrupt_handler(void *param)
5820 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5821 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5824 /* Disable interrupt */
5825 i40e_pf_disable_irq0(hw);
5827 /* read out interrupt causes */
5828 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5830 /* No interrupt event indicated */
5831 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5832 PMD_DRV_LOG(INFO, "No interrupt event");
5835 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5836 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5837 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5838 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5839 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5840 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5841 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5842 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5843 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5844 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5845 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5846 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5847 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5848 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5850 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5851 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5852 i40e_dev_handle_vfr_event(dev);
5854 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5855 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5856 i40e_dev_handle_aq_msg(dev);
5860 /* Enable interrupt */
5861 i40e_pf_enable_irq0(hw);
5862 rte_intr_enable(dev->intr_handle);
5866 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5867 struct i40e_macvlan_filter *filter,
5870 int ele_num, ele_buff_size;
5871 int num, actual_num, i;
5873 int ret = I40E_SUCCESS;
5874 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5875 struct i40e_aqc_add_macvlan_element_data *req_list;
5877 if (filter == NULL || total == 0)
5878 return I40E_ERR_PARAM;
5879 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5880 ele_buff_size = hw->aq.asq_buf_size;
5882 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5883 if (req_list == NULL) {
5884 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5885 return I40E_ERR_NO_MEMORY;
5890 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5891 memset(req_list, 0, ele_buff_size);
5893 for (i = 0; i < actual_num; i++) {
5894 (void)rte_memcpy(req_list[i].mac_addr,
5895 &filter[num + i].macaddr, ETH_ADDR_LEN);
5896 req_list[i].vlan_tag =
5897 rte_cpu_to_le_16(filter[num + i].vlan_id);
5899 switch (filter[num + i].filter_type) {
5900 case RTE_MAC_PERFECT_MATCH:
5901 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5902 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5904 case RTE_MACVLAN_PERFECT_MATCH:
5905 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5907 case RTE_MAC_HASH_MATCH:
5908 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5909 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5911 case RTE_MACVLAN_HASH_MATCH:
5912 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5915 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5916 ret = I40E_ERR_PARAM;
5920 req_list[i].queue_number = 0;
5922 req_list[i].flags = rte_cpu_to_le_16(flags);
5925 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5927 if (ret != I40E_SUCCESS) {
5928 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5932 } while (num < total);
5940 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5941 struct i40e_macvlan_filter *filter,
5944 int ele_num, ele_buff_size;
5945 int num, actual_num, i;
5947 int ret = I40E_SUCCESS;
5948 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5949 struct i40e_aqc_remove_macvlan_element_data *req_list;
5951 if (filter == NULL || total == 0)
5952 return I40E_ERR_PARAM;
5954 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5955 ele_buff_size = hw->aq.asq_buf_size;
5957 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5958 if (req_list == NULL) {
5959 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5960 return I40E_ERR_NO_MEMORY;
5965 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5966 memset(req_list, 0, ele_buff_size);
5968 for (i = 0; i < actual_num; i++) {
5969 (void)rte_memcpy(req_list[i].mac_addr,
5970 &filter[num + i].macaddr, ETH_ADDR_LEN);
5971 req_list[i].vlan_tag =
5972 rte_cpu_to_le_16(filter[num + i].vlan_id);
5974 switch (filter[num + i].filter_type) {
5975 case RTE_MAC_PERFECT_MATCH:
5976 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5977 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5979 case RTE_MACVLAN_PERFECT_MATCH:
5980 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5982 case RTE_MAC_HASH_MATCH:
5983 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5984 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5986 case RTE_MACVLAN_HASH_MATCH:
5987 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5990 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5991 ret = I40E_ERR_PARAM;
5994 req_list[i].flags = rte_cpu_to_le_16(flags);
5997 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5999 if (ret != I40E_SUCCESS) {
6000 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6004 } while (num < total);
6011 /* Find out specific MAC filter */
6012 static struct i40e_mac_filter *
6013 i40e_find_mac_filter(struct i40e_vsi *vsi,
6014 struct ether_addr *macaddr)
6016 struct i40e_mac_filter *f;
6018 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6019 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6027 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6030 uint32_t vid_idx, vid_bit;
6032 if (vlan_id > ETH_VLAN_ID_MAX)
6035 vid_idx = I40E_VFTA_IDX(vlan_id);
6036 vid_bit = I40E_VFTA_BIT(vlan_id);
6038 if (vsi->vfta[vid_idx] & vid_bit)
6045 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6046 uint16_t vlan_id, bool on)
6048 uint32_t vid_idx, vid_bit;
6050 vid_idx = I40E_VFTA_IDX(vlan_id);
6051 vid_bit = I40E_VFTA_BIT(vlan_id);
6054 vsi->vfta[vid_idx] |= vid_bit;
6056 vsi->vfta[vid_idx] &= ~vid_bit;
6060 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6061 uint16_t vlan_id, bool on)
6063 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6064 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6067 if (vlan_id > ETH_VLAN_ID_MAX)
6070 i40e_store_vlan_filter(vsi, vlan_id, on);
6072 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6075 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6078 ret = i40e_aq_add_vlan(hw, vsi->seid,
6079 &vlan_data, 1, NULL);
6080 if (ret != I40E_SUCCESS)
6081 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6083 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6084 &vlan_data, 1, NULL);
6085 if (ret != I40E_SUCCESS)
6087 "Failed to remove vlan filter");
6092 * Find all vlan options for specific mac addr,
6093 * return with actual vlan found.
6096 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6097 struct i40e_macvlan_filter *mv_f,
6098 int num, struct ether_addr *addr)
6104 * Not to use i40e_find_vlan_filter to decrease the loop time,
6105 * although the code looks complex.
6107 if (num < vsi->vlan_num)
6108 return I40E_ERR_PARAM;
6111 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6113 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6114 if (vsi->vfta[j] & (1 << k)) {
6117 "vlan number doesn't match");
6118 return I40E_ERR_PARAM;
6120 (void)rte_memcpy(&mv_f[i].macaddr,
6121 addr, ETH_ADDR_LEN);
6123 j * I40E_UINT32_BIT_SIZE + k;
6129 return I40E_SUCCESS;
6133 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6134 struct i40e_macvlan_filter *mv_f,
6139 struct i40e_mac_filter *f;
6141 if (num < vsi->mac_num)
6142 return I40E_ERR_PARAM;
6144 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6146 PMD_DRV_LOG(ERR, "buffer number not match");
6147 return I40E_ERR_PARAM;
6149 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6151 mv_f[i].vlan_id = vlan;
6152 mv_f[i].filter_type = f->mac_info.filter_type;
6156 return I40E_SUCCESS;
6160 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6163 struct i40e_mac_filter *f;
6164 struct i40e_macvlan_filter *mv_f;
6165 int ret = I40E_SUCCESS;
6167 if (vsi == NULL || vsi->mac_num == 0)
6168 return I40E_ERR_PARAM;
6170 /* Case that no vlan is set */
6171 if (vsi->vlan_num == 0)
6174 num = vsi->mac_num * vsi->vlan_num;
6176 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6178 PMD_DRV_LOG(ERR, "failed to allocate memory");
6179 return I40E_ERR_NO_MEMORY;
6183 if (vsi->vlan_num == 0) {
6184 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6185 (void)rte_memcpy(&mv_f[i].macaddr,
6186 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6187 mv_f[i].filter_type = f->mac_info.filter_type;
6188 mv_f[i].vlan_id = 0;
6192 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6193 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6194 vsi->vlan_num, &f->mac_info.mac_addr);
6195 if (ret != I40E_SUCCESS)
6197 for (j = i; j < i + vsi->vlan_num; j++)
6198 mv_f[j].filter_type = f->mac_info.filter_type;
6203 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6211 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6213 struct i40e_macvlan_filter *mv_f;
6215 int ret = I40E_SUCCESS;
6217 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6218 return I40E_ERR_PARAM;
6220 /* If it's already set, just return */
6221 if (i40e_find_vlan_filter(vsi,vlan))
6222 return I40E_SUCCESS;
6224 mac_num = vsi->mac_num;
6227 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6228 return I40E_ERR_PARAM;
6231 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6234 PMD_DRV_LOG(ERR, "failed to allocate memory");
6235 return I40E_ERR_NO_MEMORY;
6238 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6240 if (ret != I40E_SUCCESS)
6243 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6245 if (ret != I40E_SUCCESS)
6248 i40e_set_vlan_filter(vsi, vlan, 1);
6258 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6260 struct i40e_macvlan_filter *mv_f;
6262 int ret = I40E_SUCCESS;
6265 * Vlan 0 is the generic filter for untagged packets
6266 * and can't be removed.
6268 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6269 return I40E_ERR_PARAM;
6271 /* If can't find it, just return */
6272 if (!i40e_find_vlan_filter(vsi, vlan))
6273 return I40E_ERR_PARAM;
6275 mac_num = vsi->mac_num;
6278 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6279 return I40E_ERR_PARAM;
6282 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6285 PMD_DRV_LOG(ERR, "failed to allocate memory");
6286 return I40E_ERR_NO_MEMORY;
6289 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6291 if (ret != I40E_SUCCESS)
6294 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6296 if (ret != I40E_SUCCESS)
6299 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6300 if (vsi->vlan_num == 1) {
6301 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6302 if (ret != I40E_SUCCESS)
6305 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6306 if (ret != I40E_SUCCESS)
6310 i40e_set_vlan_filter(vsi, vlan, 0);
6320 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6322 struct i40e_mac_filter *f;
6323 struct i40e_macvlan_filter *mv_f;
6324 int i, vlan_num = 0;
6325 int ret = I40E_SUCCESS;
6327 /* If it's add and we've config it, return */
6328 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6330 return I40E_SUCCESS;
6331 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6332 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6335 * If vlan_num is 0, that's the first time to add mac,
6336 * set mask for vlan_id 0.
6338 if (vsi->vlan_num == 0) {
6339 i40e_set_vlan_filter(vsi, 0, 1);
6342 vlan_num = vsi->vlan_num;
6343 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6344 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6347 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6349 PMD_DRV_LOG(ERR, "failed to allocate memory");
6350 return I40E_ERR_NO_MEMORY;
6353 for (i = 0; i < vlan_num; i++) {
6354 mv_f[i].filter_type = mac_filter->filter_type;
6355 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6359 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6360 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6361 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6362 &mac_filter->mac_addr);
6363 if (ret != I40E_SUCCESS)
6367 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6368 if (ret != I40E_SUCCESS)
6371 /* Add the mac addr into mac list */
6372 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6374 PMD_DRV_LOG(ERR, "failed to allocate memory");
6375 ret = I40E_ERR_NO_MEMORY;
6378 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6380 f->mac_info.filter_type = mac_filter->filter_type;
6381 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6392 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6394 struct i40e_mac_filter *f;
6395 struct i40e_macvlan_filter *mv_f;
6397 enum rte_mac_filter_type filter_type;
6398 int ret = I40E_SUCCESS;
6400 /* Can't find it, return an error */
6401 f = i40e_find_mac_filter(vsi, addr);
6403 return I40E_ERR_PARAM;
6405 vlan_num = vsi->vlan_num;
6406 filter_type = f->mac_info.filter_type;
6407 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6408 filter_type == RTE_MACVLAN_HASH_MATCH) {
6409 if (vlan_num == 0) {
6410 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6411 return I40E_ERR_PARAM;
6413 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6414 filter_type == RTE_MAC_HASH_MATCH)
6417 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6419 PMD_DRV_LOG(ERR, "failed to allocate memory");
6420 return I40E_ERR_NO_MEMORY;
6423 for (i = 0; i < vlan_num; i++) {
6424 mv_f[i].filter_type = filter_type;
6425 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6428 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6429 filter_type == RTE_MACVLAN_HASH_MATCH) {
6430 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6431 if (ret != I40E_SUCCESS)
6435 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6436 if (ret != I40E_SUCCESS)
6439 /* Remove the mac addr into mac list */
6440 TAILQ_REMOVE(&vsi->mac_list, f, next);
6450 /* Configure hash enable flags for RSS */
6452 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6459 if (flags & ETH_RSS_FRAG_IPV4)
6460 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6461 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6462 if (type == I40E_MAC_X722) {
6463 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6464 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6466 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6468 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6469 if (type == I40E_MAC_X722) {
6470 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6471 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6472 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6474 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6476 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6477 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6478 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6479 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6480 if (flags & ETH_RSS_FRAG_IPV6)
6481 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6482 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6483 if (type == I40E_MAC_X722) {
6484 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6485 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6487 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6489 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6490 if (type == I40E_MAC_X722) {
6491 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6492 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6493 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6495 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6497 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6498 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6499 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6500 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6501 if (flags & ETH_RSS_L2_PAYLOAD)
6502 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6507 /* Parse the hash enable flags */
6509 i40e_parse_hena(uint64_t flags)
6511 uint64_t rss_hf = 0;
6515 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6516 rss_hf |= ETH_RSS_FRAG_IPV4;
6517 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6518 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6519 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6520 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6521 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6522 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6523 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6524 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6525 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6526 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6527 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6528 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6529 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6530 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6531 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6532 rss_hf |= ETH_RSS_FRAG_IPV6;
6533 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6534 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6535 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6536 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6537 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6538 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6539 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6540 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6541 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6542 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6543 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6544 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6545 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6546 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6547 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6548 rss_hf |= ETH_RSS_L2_PAYLOAD;
6555 i40e_pf_disable_rss(struct i40e_pf *pf)
6557 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6560 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6561 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6562 if (hw->mac.type == I40E_MAC_X722)
6563 hena &= ~I40E_RSS_HENA_ALL_X722;
6565 hena &= ~I40E_RSS_HENA_ALL;
6566 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6567 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6568 I40E_WRITE_FLUSH(hw);
6572 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6574 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6575 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6578 if (!key || key_len == 0) {
6579 PMD_DRV_LOG(DEBUG, "No key to be configured");
6581 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6583 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6587 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6588 struct i40e_aqc_get_set_rss_key_data *key_dw =
6589 (struct i40e_aqc_get_set_rss_key_data *)key;
6591 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6593 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6595 uint32_t *hash_key = (uint32_t *)key;
6598 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6599 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6600 I40E_WRITE_FLUSH(hw);
6607 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6609 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6610 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6613 if (!key || !key_len)
6616 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6617 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6618 (struct i40e_aqc_get_set_rss_key_data *)key);
6620 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6624 uint32_t *key_dw = (uint32_t *)key;
6627 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6628 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6630 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6636 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6638 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6643 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6644 rss_conf->rss_key_len);
6648 rss_hf = rss_conf->rss_hf;
6649 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6650 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6651 if (hw->mac.type == I40E_MAC_X722)
6652 hena &= ~I40E_RSS_HENA_ALL_X722;
6654 hena &= ~I40E_RSS_HENA_ALL;
6655 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6656 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6657 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6658 I40E_WRITE_FLUSH(hw);
6664 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6665 struct rte_eth_rss_conf *rss_conf)
6667 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6668 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6669 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6672 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6673 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6674 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6675 ? I40E_RSS_HENA_ALL_X722
6676 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6677 if (rss_hf != 0) /* Enable RSS */
6679 return 0; /* Nothing to do */
6682 if (rss_hf == 0) /* Disable RSS */
6685 return i40e_hw_rss_hash_set(pf, rss_conf);
6689 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6690 struct rte_eth_rss_conf *rss_conf)
6692 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6693 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6696 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6697 &rss_conf->rss_key_len);
6699 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6700 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6701 rss_conf->rss_hf = i40e_parse_hena(hena);
6707 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6709 switch (filter_type) {
6710 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6711 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6713 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6714 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6716 case RTE_TUNNEL_FILTER_IMAC_TENID:
6717 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6719 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6720 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6722 case ETH_TUNNEL_FILTER_IMAC:
6723 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6725 case ETH_TUNNEL_FILTER_OIP:
6726 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6728 case ETH_TUNNEL_FILTER_IIP:
6729 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6732 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6739 /* Convert tunnel filter structure */
6741 i40e_tunnel_filter_convert(
6742 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6743 struct i40e_tunnel_filter *tunnel_filter)
6745 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6746 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6747 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6748 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6749 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6750 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6751 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6752 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6753 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6755 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6756 tunnel_filter->input.flags = cld_filter->element.flags;
6757 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6758 tunnel_filter->queue = cld_filter->element.queue_number;
6759 rte_memcpy(tunnel_filter->input.general_fields,
6760 cld_filter->general_fields,
6761 sizeof(cld_filter->general_fields));
6766 /* Check if there exists the tunnel filter */
6767 struct i40e_tunnel_filter *
6768 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6769 const struct i40e_tunnel_filter_input *input)
6773 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6777 return tunnel_rule->hash_map[ret];
6780 /* Add a tunnel filter into the SW list */
6782 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6783 struct i40e_tunnel_filter *tunnel_filter)
6785 struct i40e_tunnel_rule *rule = &pf->tunnel;
6788 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6791 "Failed to insert tunnel filter to hash table %d!",
6795 rule->hash_map[ret] = tunnel_filter;
6797 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6802 /* Delete a tunnel filter from the SW list */
6804 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6805 struct i40e_tunnel_filter_input *input)
6807 struct i40e_tunnel_rule *rule = &pf->tunnel;
6808 struct i40e_tunnel_filter *tunnel_filter;
6811 ret = rte_hash_del_key(rule->hash_table, input);
6814 "Failed to delete tunnel filter to hash table %d!",
6818 tunnel_filter = rule->hash_map[ret];
6819 rule->hash_map[ret] = NULL;
6821 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6822 rte_free(tunnel_filter);
6828 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6829 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6834 uint8_t i, tun_type = 0;
6835 /* internal varialbe to convert ipv6 byte order */
6836 uint32_t convert_ipv6[4];
6838 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6839 struct i40e_vsi *vsi = pf->main_vsi;
6840 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6841 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6842 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6843 struct i40e_tunnel_filter *tunnel, *node;
6844 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6846 cld_filter = rte_zmalloc("tunnel_filter",
6847 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6850 if (NULL == cld_filter) {
6851 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6854 pfilter = cld_filter;
6856 ether_addr_copy(&tunnel_filter->outer_mac,
6857 (struct ether_addr *)&pfilter->element.outer_mac);
6858 ether_addr_copy(&tunnel_filter->inner_mac,
6859 (struct ether_addr *)&pfilter->element.inner_mac);
6861 pfilter->element.inner_vlan =
6862 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6863 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6864 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6865 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6866 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6867 &rte_cpu_to_le_32(ipv4_addr),
6868 sizeof(pfilter->element.ipaddr.v4.data));
6870 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6871 for (i = 0; i < 4; i++) {
6873 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6875 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6877 sizeof(pfilter->element.ipaddr.v6.data));
6880 /* check tunneled type */
6881 switch (tunnel_filter->tunnel_type) {
6882 case RTE_TUNNEL_TYPE_VXLAN:
6883 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6885 case RTE_TUNNEL_TYPE_NVGRE:
6886 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6888 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6889 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6892 /* Other tunnel types is not supported. */
6893 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6894 rte_free(cld_filter);
6898 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6899 &pfilter->element.flags);
6901 rte_free(cld_filter);
6905 pfilter->element.flags |= rte_cpu_to_le_16(
6906 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6907 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6908 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6909 pfilter->element.queue_number =
6910 rte_cpu_to_le_16(tunnel_filter->queue_id);
6912 /* Check if there is the filter in SW list */
6913 memset(&check_filter, 0, sizeof(check_filter));
6914 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6915 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6917 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6921 if (!add && !node) {
6922 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6927 ret = i40e_aq_add_cloud_filters(hw,
6928 vsi->seid, &cld_filter->element, 1);
6930 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6933 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6934 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6935 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6937 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6938 &cld_filter->element, 1);
6940 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6943 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6946 rte_free(cld_filter);
6950 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6951 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
6952 #define I40E_TR_GENEVE_KEY_MASK 0x8
6953 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
6954 #define I40E_TR_GRE_KEY_MASK 0x400
6955 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
6956 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
6959 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6961 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6962 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6963 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6964 enum i40e_status_code status = I40E_SUCCESS;
6966 memset(&filter_replace, 0,
6967 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6968 memset(&filter_replace_buf, 0,
6969 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6971 /* create L1 filter */
6972 filter_replace.old_filter_type =
6973 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6974 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6975 filter_replace.tr_bit = 0;
6977 /* Prepare the buffer, 3 entries */
6978 filter_replace_buf.data[0] =
6979 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6980 filter_replace_buf.data[0] |=
6981 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6982 filter_replace_buf.data[2] = 0xFF;
6983 filter_replace_buf.data[3] = 0xFF;
6984 filter_replace_buf.data[4] =
6985 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6986 filter_replace_buf.data[4] |=
6987 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6988 filter_replace_buf.data[7] = 0xF0;
6989 filter_replace_buf.data[8]
6990 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6991 filter_replace_buf.data[8] |=
6992 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6993 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6994 I40E_TR_GENEVE_KEY_MASK |
6995 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6996 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6997 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
6998 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7000 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7001 &filter_replace_buf);
7006 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7008 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7009 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7010 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7011 enum i40e_status_code status = I40E_SUCCESS;
7014 memset(&filter_replace, 0,
7015 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7016 memset(&filter_replace_buf, 0,
7017 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7018 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7019 I40E_AQC_MIRROR_CLOUD_FILTER;
7020 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7021 filter_replace.new_filter_type =
7022 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7023 /* Prepare the buffer, 2 entries */
7024 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7025 filter_replace_buf.data[0] |=
7026 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7027 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7028 filter_replace_buf.data[4] |=
7029 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7030 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7031 &filter_replace_buf);
7036 memset(&filter_replace, 0,
7037 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7038 memset(&filter_replace_buf, 0,
7039 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7041 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7042 I40E_AQC_MIRROR_CLOUD_FILTER;
7043 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7044 filter_replace.new_filter_type =
7045 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7046 /* Prepare the buffer, 2 entries */
7047 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7048 filter_replace_buf.data[0] |=
7049 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7050 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7051 filter_replace_buf.data[4] |=
7052 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7054 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7055 &filter_replace_buf);
7060 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7061 struct i40e_tunnel_filter_conf *tunnel_filter,
7066 uint8_t i, tun_type = 0;
7067 /* internal variable to convert ipv6 byte order */
7068 uint32_t convert_ipv6[4];
7070 struct i40e_pf_vf *vf = NULL;
7071 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7072 struct i40e_vsi *vsi;
7073 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7074 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7075 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7076 struct i40e_tunnel_filter *tunnel, *node;
7077 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7079 bool big_buffer = 0;
7081 cld_filter = rte_zmalloc("tunnel_filter",
7082 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7085 if (cld_filter == NULL) {
7086 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7089 pfilter = cld_filter;
7091 ether_addr_copy(&tunnel_filter->outer_mac,
7092 (struct ether_addr *)&pfilter->element.outer_mac);
7093 ether_addr_copy(&tunnel_filter->inner_mac,
7094 (struct ether_addr *)&pfilter->element.inner_mac);
7096 pfilter->element.inner_vlan =
7097 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7098 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7099 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7100 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7101 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7102 &rte_cpu_to_le_32(ipv4_addr),
7103 sizeof(pfilter->element.ipaddr.v4.data));
7105 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7106 for (i = 0; i < 4; i++) {
7108 rte_cpu_to_le_32(rte_be_to_cpu_32(
7109 tunnel_filter->ip_addr.ipv6_addr[i]));
7111 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7113 sizeof(pfilter->element.ipaddr.v6.data));
7116 /* check tunneled type */
7117 switch (tunnel_filter->tunnel_type) {
7118 case I40E_TUNNEL_TYPE_VXLAN:
7119 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7121 case I40E_TUNNEL_TYPE_NVGRE:
7122 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7124 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7125 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7127 case I40E_TUNNEL_TYPE_MPLSoUDP:
7128 if (!pf->mpls_replace_flag) {
7129 i40e_replace_mpls_l1_filter(pf);
7130 i40e_replace_mpls_cloud_filter(pf);
7131 pf->mpls_replace_flag = 1;
7133 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7134 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7136 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7137 (teid_le & 0xF) << 12;
7138 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7141 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7143 case I40E_TUNNEL_TYPE_MPLSoGRE:
7144 if (!pf->mpls_replace_flag) {
7145 i40e_replace_mpls_l1_filter(pf);
7146 i40e_replace_mpls_cloud_filter(pf);
7147 pf->mpls_replace_flag = 1;
7149 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7150 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7152 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7153 (teid_le & 0xF) << 12;
7154 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7157 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7159 case I40E_TUNNEL_TYPE_QINQ:
7160 if (!pf->qinq_replace_flag) {
7161 ret = i40e_cloud_filter_qinq_create(pf);
7164 "Failed to create a qinq tunnel filter.");
7165 pf->qinq_replace_flag = 1;
7167 /* Add in the General fields the values of
7168 * the Outer and Inner VLAN
7169 * Big Buffer should be set, see changes in
7170 * i40e_aq_add_cloud_filters
7172 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7173 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7177 /* Other tunnel types is not supported. */
7178 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7179 rte_free(cld_filter);
7183 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7184 pfilter->element.flags =
7185 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7186 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7187 pfilter->element.flags =
7188 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7189 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7190 pfilter->element.flags |=
7191 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7193 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7194 &pfilter->element.flags);
7196 rte_free(cld_filter);
7201 pfilter->element.flags |= rte_cpu_to_le_16(
7202 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7203 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7204 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7205 pfilter->element.queue_number =
7206 rte_cpu_to_le_16(tunnel_filter->queue_id);
7208 if (!tunnel_filter->is_to_vf)
7211 if (tunnel_filter->vf_id >= pf->vf_num) {
7212 PMD_DRV_LOG(ERR, "Invalid argument.");
7215 vf = &pf->vfs[tunnel_filter->vf_id];
7219 /* Check if there is the filter in SW list */
7220 memset(&check_filter, 0, sizeof(check_filter));
7221 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7222 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7223 check_filter.vf_id = tunnel_filter->vf_id;
7224 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7226 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7230 if (!add && !node) {
7231 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7237 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7238 vsi->seid, cld_filter, 1);
7240 ret = i40e_aq_add_cloud_filters(hw,
7241 vsi->seid, &cld_filter->element, 1);
7243 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7246 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7247 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7248 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7251 ret = i40e_aq_remove_cloud_filters_big_buffer(
7252 hw, vsi->seid, cld_filter, 1);
7254 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7255 &cld_filter->element, 1);
7257 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7260 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7263 rte_free(cld_filter);
7268 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7272 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7273 if (pf->vxlan_ports[i] == port)
7281 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7285 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7287 idx = i40e_get_vxlan_port_idx(pf, port);
7289 /* Check if port already exists */
7291 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7295 /* Now check if there is space to add the new port */
7296 idx = i40e_get_vxlan_port_idx(pf, 0);
7299 "Maximum number of UDP ports reached, not adding port %d",
7304 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7307 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7311 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7314 /* New port: add it and mark its index in the bitmap */
7315 pf->vxlan_ports[idx] = port;
7316 pf->vxlan_bitmap |= (1 << idx);
7318 if (!(pf->flags & I40E_FLAG_VXLAN))
7319 pf->flags |= I40E_FLAG_VXLAN;
7325 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7328 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7330 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7331 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7335 idx = i40e_get_vxlan_port_idx(pf, port);
7338 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7342 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7343 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7347 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7350 pf->vxlan_ports[idx] = 0;
7351 pf->vxlan_bitmap &= ~(1 << idx);
7353 if (!pf->vxlan_bitmap)
7354 pf->flags &= ~I40E_FLAG_VXLAN;
7359 /* Add UDP tunneling port */
7361 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7362 struct rte_eth_udp_tunnel *udp_tunnel)
7365 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7367 if (udp_tunnel == NULL)
7370 switch (udp_tunnel->prot_type) {
7371 case RTE_TUNNEL_TYPE_VXLAN:
7372 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7375 case RTE_TUNNEL_TYPE_GENEVE:
7376 case RTE_TUNNEL_TYPE_TEREDO:
7377 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7382 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7390 /* Remove UDP tunneling port */
7392 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7393 struct rte_eth_udp_tunnel *udp_tunnel)
7396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7398 if (udp_tunnel == NULL)
7401 switch (udp_tunnel->prot_type) {
7402 case RTE_TUNNEL_TYPE_VXLAN:
7403 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7405 case RTE_TUNNEL_TYPE_GENEVE:
7406 case RTE_TUNNEL_TYPE_TEREDO:
7407 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7411 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7419 /* Calculate the maximum number of contiguous PF queues that are configured */
7421 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7423 struct rte_eth_dev_data *data = pf->dev_data;
7425 struct i40e_rx_queue *rxq;
7428 for (i = 0; i < pf->lan_nb_qps; i++) {
7429 rxq = data->rx_queues[i];
7430 if (rxq && rxq->q_set)
7441 i40e_pf_config_rss(struct i40e_pf *pf)
7443 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7444 struct rte_eth_rss_conf rss_conf;
7445 uint32_t i, lut = 0;
7449 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7450 * It's necessary to calulate the actual PF queues that are configured.
7452 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7453 num = i40e_pf_calc_configured_queues_num(pf);
7455 num = pf->dev_data->nb_rx_queues;
7457 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7458 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7462 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7466 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7469 lut = (lut << 8) | (j & ((0x1 <<
7470 hw->func_caps.rss_table_entry_width) - 1));
7472 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7475 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7476 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7477 i40e_pf_disable_rss(pf);
7480 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7481 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7482 /* Random default keys */
7483 static uint32_t rss_key_default[] = {0x6b793944,
7484 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7485 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7486 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7488 rss_conf.rss_key = (uint8_t *)rss_key_default;
7489 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7493 return i40e_hw_rss_hash_set(pf, &rss_conf);
7497 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7498 struct rte_eth_tunnel_filter_conf *filter)
7500 if (pf == NULL || filter == NULL) {
7501 PMD_DRV_LOG(ERR, "Invalid parameter");
7505 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7506 PMD_DRV_LOG(ERR, "Invalid queue ID");
7510 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7511 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7515 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7516 (is_zero_ether_addr(&filter->outer_mac))) {
7517 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7521 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7522 (is_zero_ether_addr(&filter->inner_mac))) {
7523 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7530 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7531 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7533 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7538 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7539 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7542 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7543 } else if (len == 4) {
7544 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7546 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7551 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7558 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7559 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7565 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7572 switch (cfg->cfg_type) {
7573 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7574 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7577 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7585 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7586 enum rte_filter_op filter_op,
7589 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7590 int ret = I40E_ERR_PARAM;
7592 switch (filter_op) {
7593 case RTE_ETH_FILTER_SET:
7594 ret = i40e_dev_global_config_set(hw,
7595 (struct rte_eth_global_cfg *)arg);
7598 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7606 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7607 enum rte_filter_op filter_op,
7610 struct rte_eth_tunnel_filter_conf *filter;
7611 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7612 int ret = I40E_SUCCESS;
7614 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7616 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7617 return I40E_ERR_PARAM;
7619 switch (filter_op) {
7620 case RTE_ETH_FILTER_NOP:
7621 if (!(pf->flags & I40E_FLAG_VXLAN))
7622 ret = I40E_NOT_SUPPORTED;
7624 case RTE_ETH_FILTER_ADD:
7625 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7627 case RTE_ETH_FILTER_DELETE:
7628 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7631 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7632 ret = I40E_ERR_PARAM;
7640 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7643 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7646 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7647 ret = i40e_pf_config_rss(pf);
7649 i40e_pf_disable_rss(pf);
7654 /* Get the symmetric hash enable configurations per port */
7656 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7658 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7660 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7663 /* Set the symmetric hash enable configurations per port */
7665 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7667 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7670 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7672 "Symmetric hash has already been enabled");
7675 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7677 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7679 "Symmetric hash has already been disabled");
7682 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7684 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7685 I40E_WRITE_FLUSH(hw);
7689 * Get global configurations of hash function type and symmetric hash enable
7690 * per flow type (pctype). Note that global configuration means it affects all
7691 * the ports on the same NIC.
7694 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7695 struct rte_eth_hash_global_conf *g_cfg)
7697 uint32_t reg, mask = I40E_FLOW_TYPES;
7699 enum i40e_filter_pctype pctype;
7701 memset(g_cfg, 0, sizeof(*g_cfg));
7702 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7703 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7704 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7706 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7707 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7708 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7710 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7711 if (!(mask & (1UL << i)))
7713 mask &= ~(1UL << i);
7714 /* Bit set indicats the coresponding flow type is supported */
7715 g_cfg->valid_bit_mask[0] |= (1UL << i);
7716 /* if flowtype is invalid, continue */
7717 if (!I40E_VALID_FLOW(i))
7719 pctype = i40e_flowtype_to_pctype(i);
7720 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7721 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7722 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7729 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7732 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7734 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7735 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7736 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7737 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7743 * As i40e supports less than 32 flow types, only first 32 bits need to
7746 mask0 = g_cfg->valid_bit_mask[0];
7747 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7749 /* Check if any unsupported flow type configured */
7750 if ((mask0 | i40e_mask) ^ i40e_mask)
7753 if (g_cfg->valid_bit_mask[i])
7761 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7767 * Set global configurations of hash function type and symmetric hash enable
7768 * per flow type (pctype). Note any modifying global configuration will affect
7769 * all the ports on the same NIC.
7772 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7773 struct rte_eth_hash_global_conf *g_cfg)
7778 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7779 enum i40e_filter_pctype pctype;
7781 /* Check the input parameters */
7782 ret = i40e_hash_global_config_check(g_cfg);
7786 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7787 if (!(mask0 & (1UL << i)))
7789 mask0 &= ~(1UL << i);
7790 /* if flowtype is invalid, continue */
7791 if (!I40E_VALID_FLOW(i))
7793 pctype = i40e_flowtype_to_pctype(i);
7794 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7795 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7796 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7799 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7800 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7802 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7804 "Hash function already set to Toeplitz");
7807 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7808 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7810 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7812 "Hash function already set to Simple XOR");
7815 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7817 /* Use the default, and keep it as it is */
7820 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7823 I40E_WRITE_FLUSH(hw);
7829 * Valid input sets for hash and flow director filters per PCTYPE
7832 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7833 enum rte_filter_type filter)
7837 static const uint64_t valid_hash_inset_table[] = {
7838 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7839 I40E_INSET_DMAC | I40E_INSET_SMAC |
7840 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7841 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7842 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7843 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7844 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7845 I40E_INSET_FLEX_PAYLOAD,
7846 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7847 I40E_INSET_DMAC | I40E_INSET_SMAC |
7848 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7849 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7850 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7851 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7852 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7853 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7854 I40E_INSET_FLEX_PAYLOAD,
7855 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7856 I40E_INSET_DMAC | I40E_INSET_SMAC |
7857 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7858 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7859 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7860 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7861 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7862 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7863 I40E_INSET_FLEX_PAYLOAD,
7864 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7865 I40E_INSET_DMAC | I40E_INSET_SMAC |
7866 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7867 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7868 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7869 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7870 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7871 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7872 I40E_INSET_FLEX_PAYLOAD,
7873 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7874 I40E_INSET_DMAC | I40E_INSET_SMAC |
7875 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7876 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7877 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7878 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7879 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7880 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7881 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7882 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7883 I40E_INSET_DMAC | I40E_INSET_SMAC |
7884 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7885 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7886 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7887 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7888 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7889 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7890 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7891 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7892 I40E_INSET_DMAC | I40E_INSET_SMAC |
7893 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7894 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7895 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7896 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7897 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7898 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7899 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7900 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7901 I40E_INSET_DMAC | I40E_INSET_SMAC |
7902 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7903 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7904 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7905 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7906 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7907 I40E_INSET_FLEX_PAYLOAD,
7908 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7909 I40E_INSET_DMAC | I40E_INSET_SMAC |
7910 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7911 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7912 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7913 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7914 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7915 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7916 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7917 I40E_INSET_DMAC | I40E_INSET_SMAC |
7918 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7919 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7920 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7921 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7922 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7923 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7924 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7925 I40E_INSET_DMAC | I40E_INSET_SMAC |
7926 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7927 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7928 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7929 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7930 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7931 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7932 I40E_INSET_FLEX_PAYLOAD,
7933 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7934 I40E_INSET_DMAC | I40E_INSET_SMAC |
7935 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7936 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7937 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7938 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7939 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7940 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7941 I40E_INSET_FLEX_PAYLOAD,
7942 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7943 I40E_INSET_DMAC | I40E_INSET_SMAC |
7944 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7945 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7946 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7947 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7948 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7949 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7950 I40E_INSET_FLEX_PAYLOAD,
7951 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7952 I40E_INSET_DMAC | I40E_INSET_SMAC |
7953 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7954 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7955 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7956 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7957 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7958 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7959 I40E_INSET_FLEX_PAYLOAD,
7960 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7961 I40E_INSET_DMAC | I40E_INSET_SMAC |
7962 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7963 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7964 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7965 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7966 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7967 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7968 I40E_INSET_FLEX_PAYLOAD,
7969 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7970 I40E_INSET_DMAC | I40E_INSET_SMAC |
7971 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7972 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7973 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7974 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7975 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7976 I40E_INSET_FLEX_PAYLOAD,
7977 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7978 I40E_INSET_DMAC | I40E_INSET_SMAC |
7979 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7980 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7981 I40E_INSET_FLEX_PAYLOAD,
7985 * Flow director supports only fields defined in
7986 * union rte_eth_fdir_flow.
7988 static const uint64_t valid_fdir_inset_table[] = {
7989 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7990 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7991 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7992 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7993 I40E_INSET_IPV4_TTL,
7994 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7995 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7996 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7997 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7998 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7999 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8000 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8001 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8002 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8003 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8004 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8005 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8006 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8007 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8008 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8009 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8010 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8011 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8012 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8013 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8014 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8015 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8016 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8017 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8018 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8019 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8020 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8021 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8022 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8023 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8025 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8026 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8027 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8028 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8029 I40E_INSET_IPV4_TTL,
8030 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8031 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8032 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8033 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8034 I40E_INSET_IPV6_HOP_LIMIT,
8035 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8036 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8037 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8038 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8039 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8040 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8041 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8042 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8043 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8044 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8045 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8046 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8047 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8048 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8049 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8050 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8051 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8052 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8053 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8054 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8055 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8056 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8057 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8058 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8059 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8060 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8061 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8062 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8063 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8064 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8066 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8067 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8068 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8069 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8070 I40E_INSET_IPV6_HOP_LIMIT,
8071 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8072 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8073 I40E_INSET_LAST_ETHER_TYPE,
8076 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8078 if (filter == RTE_ETH_FILTER_HASH)
8079 valid = valid_hash_inset_table[pctype];
8081 valid = valid_fdir_inset_table[pctype];
8087 * Validate if the input set is allowed for a specific PCTYPE
8090 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8091 enum rte_filter_type filter, uint64_t inset)
8095 valid = i40e_get_valid_input_set(pctype, filter);
8096 if (inset & (~valid))
8102 /* default input set fields combination per pctype */
8104 i40e_get_default_input_set(uint16_t pctype)
8106 static const uint64_t default_inset_table[] = {
8107 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8108 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8109 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8110 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8111 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8112 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8113 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8114 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8115 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8116 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8117 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8118 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8119 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8120 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8121 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8122 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8123 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8124 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8125 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8126 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8128 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8129 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8130 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8131 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8132 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8133 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8134 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8135 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8136 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8137 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8138 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8139 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8140 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8141 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8142 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8143 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8144 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8145 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8146 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8147 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8148 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8149 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8151 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8152 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8153 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8154 I40E_INSET_LAST_ETHER_TYPE,
8157 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8160 return default_inset_table[pctype];
8164 * Parse the input set from index to logical bit masks
8167 i40e_parse_input_set(uint64_t *inset,
8168 enum i40e_filter_pctype pctype,
8169 enum rte_eth_input_set_field *field,
8175 static const struct {
8176 enum rte_eth_input_set_field field;
8178 } inset_convert_table[] = {
8179 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8180 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8181 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8182 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8183 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8184 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8185 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8186 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8187 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8188 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8189 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8190 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8191 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8192 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8193 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8194 I40E_INSET_IPV6_NEXT_HDR},
8195 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8196 I40E_INSET_IPV6_HOP_LIMIT},
8197 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8198 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8199 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8200 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8201 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8202 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8203 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8204 I40E_INSET_SCTP_VT},
8205 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8206 I40E_INSET_TUNNEL_DMAC},
8207 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8208 I40E_INSET_VLAN_TUNNEL},
8209 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8210 I40E_INSET_TUNNEL_ID},
8211 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8212 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8213 I40E_INSET_FLEX_PAYLOAD_W1},
8214 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8215 I40E_INSET_FLEX_PAYLOAD_W2},
8216 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8217 I40E_INSET_FLEX_PAYLOAD_W3},
8218 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8219 I40E_INSET_FLEX_PAYLOAD_W4},
8220 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8221 I40E_INSET_FLEX_PAYLOAD_W5},
8222 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8223 I40E_INSET_FLEX_PAYLOAD_W6},
8224 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8225 I40E_INSET_FLEX_PAYLOAD_W7},
8226 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8227 I40E_INSET_FLEX_PAYLOAD_W8},
8230 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8233 /* Only one item allowed for default or all */
8235 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8236 *inset = i40e_get_default_input_set(pctype);
8238 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8239 *inset = I40E_INSET_NONE;
8244 for (i = 0, *inset = 0; i < size; i++) {
8245 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8246 if (field[i] == inset_convert_table[j].field) {
8247 *inset |= inset_convert_table[j].inset;
8252 /* It contains unsupported input set, return immediately */
8253 if (j == RTE_DIM(inset_convert_table))
8261 * Translate the input set from bit masks to register aware bit masks
8265 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8275 static const struct inset_map inset_map_common[] = {
8276 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8277 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8278 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8279 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8280 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8281 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8282 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8283 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8284 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8285 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8286 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8287 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8288 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8289 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8290 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8291 {I40E_INSET_TUNNEL_DMAC,
8292 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8293 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8294 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8295 {I40E_INSET_TUNNEL_SRC_PORT,
8296 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8297 {I40E_INSET_TUNNEL_DST_PORT,
8298 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8299 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8300 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8301 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8302 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8303 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8304 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8305 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8306 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8307 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8310 /* some different registers map in x722*/
8311 static const struct inset_map inset_map_diff_x722[] = {
8312 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8313 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8314 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8315 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8318 static const struct inset_map inset_map_diff_not_x722[] = {
8319 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8320 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8321 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8322 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8328 /* Translate input set to register aware inset */
8329 if (type == I40E_MAC_X722) {
8330 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8331 if (input & inset_map_diff_x722[i].inset)
8332 val |= inset_map_diff_x722[i].inset_reg;
8335 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8336 if (input & inset_map_diff_not_x722[i].inset)
8337 val |= inset_map_diff_not_x722[i].inset_reg;
8341 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8342 if (input & inset_map_common[i].inset)
8343 val |= inset_map_common[i].inset_reg;
8350 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8353 uint64_t inset_need_mask = inset;
8355 static const struct {
8358 } inset_mask_map[] = {
8359 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8360 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8361 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8362 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8363 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8364 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8365 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8366 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8369 if (!inset || !mask || !nb_elem)
8372 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8373 /* Clear the inset bit, if no MASK is required,
8374 * for example proto + ttl
8376 if ((inset & inset_mask_map[i].inset) ==
8377 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8378 inset_need_mask &= ~inset_mask_map[i].inset;
8379 if (!inset_need_mask)
8382 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8383 if ((inset_need_mask & inset_mask_map[i].inset) ==
8384 inset_mask_map[i].inset) {
8385 if (idx >= nb_elem) {
8386 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8389 mask[idx] = inset_mask_map[i].mask;
8398 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8400 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8402 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8404 i40e_write_rx_ctl(hw, addr, val);
8405 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8406 (uint32_t)i40e_read_rx_ctl(hw, addr));
8410 i40e_filter_input_set_init(struct i40e_pf *pf)
8412 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8413 enum i40e_filter_pctype pctype;
8414 uint64_t input_set, inset_reg;
8415 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8418 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8419 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8420 if (hw->mac.type == I40E_MAC_X722) {
8421 if (!I40E_VALID_PCTYPE_X722(pctype))
8424 if (!I40E_VALID_PCTYPE(pctype))
8428 input_set = i40e_get_default_input_set(pctype);
8430 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8431 I40E_INSET_MASK_NUM_REG);
8434 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8437 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8438 (uint32_t)(inset_reg & UINT32_MAX));
8439 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8440 (uint32_t)((inset_reg >>
8441 I40E_32_BIT_WIDTH) & UINT32_MAX));
8442 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8443 (uint32_t)(inset_reg & UINT32_MAX));
8444 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8445 (uint32_t)((inset_reg >>
8446 I40E_32_BIT_WIDTH) & UINT32_MAX));
8448 for (i = 0; i < num; i++) {
8449 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8451 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8454 /*clear unused mask registers of the pctype */
8455 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8456 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8458 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8461 I40E_WRITE_FLUSH(hw);
8463 /* store the default input set */
8464 pf->hash_input_set[pctype] = input_set;
8465 pf->fdir.input_set[pctype] = input_set;
8470 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8471 struct rte_eth_input_set_conf *conf)
8473 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8474 enum i40e_filter_pctype pctype;
8475 uint64_t input_set, inset_reg = 0;
8476 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8480 PMD_DRV_LOG(ERR, "Invalid pointer");
8483 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8484 conf->op != RTE_ETH_INPUT_SET_ADD) {
8485 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8489 if (!I40E_VALID_FLOW(conf->flow_type)) {
8490 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8494 if (hw->mac.type == I40E_MAC_X722) {
8495 /* get translated pctype value in fd pctype register */
8496 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8497 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8500 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8502 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8505 PMD_DRV_LOG(ERR, "Failed to parse input set");
8508 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8510 PMD_DRV_LOG(ERR, "Invalid input set");
8513 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8514 /* get inset value in register */
8515 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8516 inset_reg <<= I40E_32_BIT_WIDTH;
8517 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8518 input_set |= pf->hash_input_set[pctype];
8520 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8521 I40E_INSET_MASK_NUM_REG);
8525 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8527 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8528 (uint32_t)(inset_reg & UINT32_MAX));
8529 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8530 (uint32_t)((inset_reg >>
8531 I40E_32_BIT_WIDTH) & UINT32_MAX));
8533 for (i = 0; i < num; i++)
8534 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8536 /*clear unused mask registers of the pctype */
8537 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8538 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8540 I40E_WRITE_FLUSH(hw);
8542 pf->hash_input_set[pctype] = input_set;
8547 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8548 struct rte_eth_input_set_conf *conf)
8550 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8551 enum i40e_filter_pctype pctype;
8552 uint64_t input_set, inset_reg = 0;
8553 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8557 PMD_DRV_LOG(ERR, "Invalid pointer");
8560 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8561 conf->op != RTE_ETH_INPUT_SET_ADD) {
8562 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8566 if (!I40E_VALID_FLOW(conf->flow_type)) {
8567 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8571 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8573 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8576 PMD_DRV_LOG(ERR, "Failed to parse input set");
8579 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8581 PMD_DRV_LOG(ERR, "Invalid input set");
8585 /* get inset value in register */
8586 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8587 inset_reg <<= I40E_32_BIT_WIDTH;
8588 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8590 /* Can not change the inset reg for flex payload for fdir,
8591 * it is done by writing I40E_PRTQF_FD_FLXINSET
8592 * in i40e_set_flex_mask_on_pctype.
8594 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8595 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8597 input_set |= pf->fdir.input_set[pctype];
8598 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8599 I40E_INSET_MASK_NUM_REG);
8603 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8605 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8606 (uint32_t)(inset_reg & UINT32_MAX));
8607 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8608 (uint32_t)((inset_reg >>
8609 I40E_32_BIT_WIDTH) & UINT32_MAX));
8611 for (i = 0; i < num; i++)
8612 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8614 /*clear unused mask registers of the pctype */
8615 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8616 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8618 I40E_WRITE_FLUSH(hw);
8620 pf->fdir.input_set[pctype] = input_set;
8625 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8630 PMD_DRV_LOG(ERR, "Invalid pointer");
8634 switch (info->info_type) {
8635 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8636 i40e_get_symmetric_hash_enable_per_port(hw,
8637 &(info->info.enable));
8639 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8640 ret = i40e_get_hash_filter_global_config(hw,
8641 &(info->info.global_conf));
8644 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8654 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8659 PMD_DRV_LOG(ERR, "Invalid pointer");
8663 switch (info->info_type) {
8664 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8665 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8667 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8668 ret = i40e_set_hash_filter_global_config(hw,
8669 &(info->info.global_conf));
8671 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8672 ret = i40e_hash_filter_inset_select(hw,
8673 &(info->info.input_set_conf));
8677 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8686 /* Operations for hash function */
8688 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8689 enum rte_filter_op filter_op,
8692 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8695 switch (filter_op) {
8696 case RTE_ETH_FILTER_NOP:
8698 case RTE_ETH_FILTER_GET:
8699 ret = i40e_hash_filter_get(hw,
8700 (struct rte_eth_hash_filter_info *)arg);
8702 case RTE_ETH_FILTER_SET:
8703 ret = i40e_hash_filter_set(hw,
8704 (struct rte_eth_hash_filter_info *)arg);
8707 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8716 /* Convert ethertype filter structure */
8718 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8719 struct i40e_ethertype_filter *filter)
8721 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8722 filter->input.ether_type = input->ether_type;
8723 filter->flags = input->flags;
8724 filter->queue = input->queue;
8729 /* Check if there exists the ehtertype filter */
8730 struct i40e_ethertype_filter *
8731 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8732 const struct i40e_ethertype_filter_input *input)
8736 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8740 return ethertype_rule->hash_map[ret];
8743 /* Add ethertype filter in SW list */
8745 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8746 struct i40e_ethertype_filter *filter)
8748 struct i40e_ethertype_rule *rule = &pf->ethertype;
8751 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8754 "Failed to insert ethertype filter"
8755 " to hash table %d!",
8759 rule->hash_map[ret] = filter;
8761 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8766 /* Delete ethertype filter in SW list */
8768 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8769 struct i40e_ethertype_filter_input *input)
8771 struct i40e_ethertype_rule *rule = &pf->ethertype;
8772 struct i40e_ethertype_filter *filter;
8775 ret = rte_hash_del_key(rule->hash_table, input);
8778 "Failed to delete ethertype filter"
8779 " to hash table %d!",
8783 filter = rule->hash_map[ret];
8784 rule->hash_map[ret] = NULL;
8786 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8793 * Configure ethertype filter, which can director packet by filtering
8794 * with mac address and ether_type or only ether_type
8797 i40e_ethertype_filter_set(struct i40e_pf *pf,
8798 struct rte_eth_ethertype_filter *filter,
8801 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8802 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8803 struct i40e_ethertype_filter *ethertype_filter, *node;
8804 struct i40e_ethertype_filter check_filter;
8805 struct i40e_control_filter_stats stats;
8809 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8810 PMD_DRV_LOG(ERR, "Invalid queue ID");
8813 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8814 filter->ether_type == ETHER_TYPE_IPv6) {
8816 "unsupported ether_type(0x%04x) in control packet filter.",
8817 filter->ether_type);
8820 if (filter->ether_type == ETHER_TYPE_VLAN)
8821 PMD_DRV_LOG(WARNING,
8822 "filter vlan ether_type in first tag is not supported.");
8824 /* Check if there is the filter in SW list */
8825 memset(&check_filter, 0, sizeof(check_filter));
8826 i40e_ethertype_filter_convert(filter, &check_filter);
8827 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8828 &check_filter.input);
8830 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8834 if (!add && !node) {
8835 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8839 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8840 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8841 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8842 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8843 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8845 memset(&stats, 0, sizeof(stats));
8846 ret = i40e_aq_add_rem_control_packet_filter(hw,
8847 filter->mac_addr.addr_bytes,
8848 filter->ether_type, flags,
8850 filter->queue, add, &stats, NULL);
8853 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8854 ret, stats.mac_etype_used, stats.etype_used,
8855 stats.mac_etype_free, stats.etype_free);
8859 /* Add or delete a filter in SW list */
8861 ethertype_filter = rte_zmalloc("ethertype_filter",
8862 sizeof(*ethertype_filter), 0);
8863 rte_memcpy(ethertype_filter, &check_filter,
8864 sizeof(check_filter));
8865 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8867 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8874 * Handle operations for ethertype filter.
8877 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8878 enum rte_filter_op filter_op,
8881 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8884 if (filter_op == RTE_ETH_FILTER_NOP)
8888 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8893 switch (filter_op) {
8894 case RTE_ETH_FILTER_ADD:
8895 ret = i40e_ethertype_filter_set(pf,
8896 (struct rte_eth_ethertype_filter *)arg,
8899 case RTE_ETH_FILTER_DELETE:
8900 ret = i40e_ethertype_filter_set(pf,
8901 (struct rte_eth_ethertype_filter *)arg,
8905 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8913 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8914 enum rte_filter_type filter_type,
8915 enum rte_filter_op filter_op,
8923 switch (filter_type) {
8924 case RTE_ETH_FILTER_NONE:
8925 /* For global configuration */
8926 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8928 case RTE_ETH_FILTER_HASH:
8929 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8931 case RTE_ETH_FILTER_MACVLAN:
8932 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8934 case RTE_ETH_FILTER_ETHERTYPE:
8935 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8937 case RTE_ETH_FILTER_TUNNEL:
8938 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8940 case RTE_ETH_FILTER_FDIR:
8941 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8943 case RTE_ETH_FILTER_GENERIC:
8944 if (filter_op != RTE_ETH_FILTER_GET)
8946 *(const void **)arg = &i40e_flow_ops;
8949 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8959 * Check and enable Extended Tag.
8960 * Enabling Extended Tag is important for 40G performance.
8963 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8965 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8969 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8972 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8976 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8977 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8982 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8985 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8989 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8990 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8993 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8994 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8997 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9004 * As some registers wouldn't be reset unless a global hardware reset,
9005 * hardware initialization is needed to put those registers into an
9006 * expected initial state.
9009 i40e_hw_init(struct rte_eth_dev *dev)
9011 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9013 i40e_enable_extended_tag(dev);
9015 /* clear the PF Queue Filter control register */
9016 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9018 /* Disable symmetric hash per port */
9019 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9022 enum i40e_filter_pctype
9023 i40e_flowtype_to_pctype(uint16_t flow_type)
9025 static const enum i40e_filter_pctype pctype_table[] = {
9026 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9027 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9028 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9029 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9030 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9031 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9032 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9033 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9034 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9035 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9036 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9037 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9038 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9039 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9040 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9041 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9042 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9043 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9044 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9047 return pctype_table[flow_type];
9051 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9053 static const uint16_t flowtype_table[] = {
9054 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9055 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9056 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9057 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9058 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9059 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9060 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9061 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9062 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9063 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9064 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9065 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9066 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9067 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9068 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9069 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9070 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9071 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9072 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9073 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9074 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9075 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9076 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9077 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9078 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9079 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9080 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9081 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9082 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9083 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9084 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9087 return flowtype_table[pctype];
9091 * On X710, performance number is far from the expectation on recent firmware
9092 * versions; on XL710, performance number is also far from the expectation on
9093 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9094 * mode is enabled and port MAC address is equal to the packet destination MAC
9095 * address. The fix for this issue may not be integrated in the following
9096 * firmware version. So the workaround in software driver is needed. It needs
9097 * to modify the initial values of 3 internal only registers for both X710 and
9098 * XL710. Note that the values for X710 or XL710 could be different, and the
9099 * workaround can be removed when it is fixed in firmware in the future.
9102 /* For both X710 and XL710 */
9103 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9104 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9106 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9107 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9110 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9111 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9114 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9116 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9117 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9120 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9122 enum i40e_status_code status;
9123 struct i40e_aq_get_phy_abilities_resp phy_ab;
9126 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9136 i40e_configure_registers(struct i40e_hw *hw)
9142 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9143 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9144 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9150 for (i = 0; i < RTE_DIM(reg_table); i++) {
9151 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9152 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9154 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9155 else /* For X710/XL710/XXV710 */
9157 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9160 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9161 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9163 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9164 else /* For X710/XL710/XXV710 */
9166 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9169 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9170 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9171 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9173 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9176 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9179 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9182 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9186 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9187 reg_table[i].addr, reg);
9188 if (reg == reg_table[i].val)
9191 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9192 reg_table[i].val, NULL);
9195 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9196 reg_table[i].val, reg_table[i].addr);
9199 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9200 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9204 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9205 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9206 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9207 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9209 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9214 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9215 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9219 /* Configure for double VLAN RX stripping */
9220 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9221 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9222 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9223 ret = i40e_aq_debug_write_register(hw,
9224 I40E_VSI_TSR(vsi->vsi_id),
9227 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9229 return I40E_ERR_CONFIG;
9233 /* Configure for double VLAN TX insertion */
9234 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9235 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9236 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9237 ret = i40e_aq_debug_write_register(hw,
9238 I40E_VSI_L2TAGSTXVALID(
9239 vsi->vsi_id), reg, NULL);
9242 "Failed to update VSI_L2TAGSTXVALID[%d]",
9244 return I40E_ERR_CONFIG;
9252 * i40e_aq_add_mirror_rule
9253 * @hw: pointer to the hardware structure
9254 * @seid: VEB seid to add mirror rule to
9255 * @dst_id: destination vsi seid
9256 * @entries: Buffer which contains the entities to be mirrored
9257 * @count: number of entities contained in the buffer
9258 * @rule_id:the rule_id of the rule to be added
9260 * Add a mirror rule for a given veb.
9263 static enum i40e_status_code
9264 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9265 uint16_t seid, uint16_t dst_id,
9266 uint16_t rule_type, uint16_t *entries,
9267 uint16_t count, uint16_t *rule_id)
9269 struct i40e_aq_desc desc;
9270 struct i40e_aqc_add_delete_mirror_rule cmd;
9271 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9272 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9275 enum i40e_status_code status;
9277 i40e_fill_default_direct_cmd_desc(&desc,
9278 i40e_aqc_opc_add_mirror_rule);
9279 memset(&cmd, 0, sizeof(cmd));
9281 buff_len = sizeof(uint16_t) * count;
9282 desc.datalen = rte_cpu_to_le_16(buff_len);
9284 desc.flags |= rte_cpu_to_le_16(
9285 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9286 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9287 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9288 cmd.num_entries = rte_cpu_to_le_16(count);
9289 cmd.seid = rte_cpu_to_le_16(seid);
9290 cmd.destination = rte_cpu_to_le_16(dst_id);
9292 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9293 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9295 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9296 hw->aq.asq_last_status, resp->rule_id,
9297 resp->mirror_rules_used, resp->mirror_rules_free);
9298 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9304 * i40e_aq_del_mirror_rule
9305 * @hw: pointer to the hardware structure
9306 * @seid: VEB seid to add mirror rule to
9307 * @entries: Buffer which contains the entities to be mirrored
9308 * @count: number of entities contained in the buffer
9309 * @rule_id:the rule_id of the rule to be delete
9311 * Delete a mirror rule for a given veb.
9314 static enum i40e_status_code
9315 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9316 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9317 uint16_t count, uint16_t rule_id)
9319 struct i40e_aq_desc desc;
9320 struct i40e_aqc_add_delete_mirror_rule cmd;
9321 uint16_t buff_len = 0;
9322 enum i40e_status_code status;
9325 i40e_fill_default_direct_cmd_desc(&desc,
9326 i40e_aqc_opc_delete_mirror_rule);
9327 memset(&cmd, 0, sizeof(cmd));
9328 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9329 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9331 cmd.num_entries = count;
9332 buff_len = sizeof(uint16_t) * count;
9333 desc.datalen = rte_cpu_to_le_16(buff_len);
9334 buff = (void *)entries;
9336 /* rule id is filled in destination field for deleting mirror rule */
9337 cmd.destination = rte_cpu_to_le_16(rule_id);
9339 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9340 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9341 cmd.seid = rte_cpu_to_le_16(seid);
9343 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9344 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9350 * i40e_mirror_rule_set
9351 * @dev: pointer to the hardware structure
9352 * @mirror_conf: mirror rule info
9353 * @sw_id: mirror rule's sw_id
9354 * @on: enable/disable
9356 * set a mirror rule.
9360 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9361 struct rte_eth_mirror_conf *mirror_conf,
9362 uint8_t sw_id, uint8_t on)
9364 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9365 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9366 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9367 struct i40e_mirror_rule *parent = NULL;
9368 uint16_t seid, dst_seid, rule_id;
9372 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9374 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9376 "mirror rule can not be configured without veb or vfs.");
9379 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9380 PMD_DRV_LOG(ERR, "mirror table is full.");
9383 if (mirror_conf->dst_pool > pf->vf_num) {
9384 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9385 mirror_conf->dst_pool);
9389 seid = pf->main_vsi->veb->seid;
9391 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9392 if (sw_id <= it->index) {
9398 if (mirr_rule && sw_id == mirr_rule->index) {
9400 PMD_DRV_LOG(ERR, "mirror rule exists.");
9403 ret = i40e_aq_del_mirror_rule(hw, seid,
9404 mirr_rule->rule_type,
9406 mirr_rule->num_entries, mirr_rule->id);
9409 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9410 ret, hw->aq.asq_last_status);
9413 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9414 rte_free(mirr_rule);
9415 pf->nb_mirror_rule--;
9419 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9423 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9424 sizeof(struct i40e_mirror_rule) , 0);
9426 PMD_DRV_LOG(ERR, "failed to allocate memory");
9427 return I40E_ERR_NO_MEMORY;
9429 switch (mirror_conf->rule_type) {
9430 case ETH_MIRROR_VLAN:
9431 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9432 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9433 mirr_rule->entries[j] =
9434 mirror_conf->vlan.vlan_id[i];
9439 PMD_DRV_LOG(ERR, "vlan is not specified.");
9440 rte_free(mirr_rule);
9443 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9445 case ETH_MIRROR_VIRTUAL_POOL_UP:
9446 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9447 /* check if the specified pool bit is out of range */
9448 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9449 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9450 rte_free(mirr_rule);
9453 for (i = 0, j = 0; i < pf->vf_num; i++) {
9454 if (mirror_conf->pool_mask & (1ULL << i)) {
9455 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9459 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9460 /* add pf vsi to entries */
9461 mirr_rule->entries[j] = pf->main_vsi_seid;
9465 PMD_DRV_LOG(ERR, "pool is not specified.");
9466 rte_free(mirr_rule);
9469 /* egress and ingress in aq commands means from switch but not port */
9470 mirr_rule->rule_type =
9471 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9472 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9473 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9475 case ETH_MIRROR_UPLINK_PORT:
9476 /* egress and ingress in aq commands means from switch but not port*/
9477 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9479 case ETH_MIRROR_DOWNLINK_PORT:
9480 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9483 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9484 mirror_conf->rule_type);
9485 rte_free(mirr_rule);
9489 /* If the dst_pool is equal to vf_num, consider it as PF */
9490 if (mirror_conf->dst_pool == pf->vf_num)
9491 dst_seid = pf->main_vsi_seid;
9493 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9495 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9496 mirr_rule->rule_type, mirr_rule->entries,
9500 "failed to add mirror rule: ret = %d, aq_err = %d.",
9501 ret, hw->aq.asq_last_status);
9502 rte_free(mirr_rule);
9506 mirr_rule->index = sw_id;
9507 mirr_rule->num_entries = j;
9508 mirr_rule->id = rule_id;
9509 mirr_rule->dst_vsi_seid = dst_seid;
9512 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9514 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9516 pf->nb_mirror_rule++;
9521 * i40e_mirror_rule_reset
9522 * @dev: pointer to the device
9523 * @sw_id: mirror rule's sw_id
9525 * reset a mirror rule.
9529 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9531 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9532 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9533 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9537 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9539 seid = pf->main_vsi->veb->seid;
9541 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9542 if (sw_id == it->index) {
9548 ret = i40e_aq_del_mirror_rule(hw, seid,
9549 mirr_rule->rule_type,
9551 mirr_rule->num_entries, mirr_rule->id);
9554 "failed to remove mirror rule: status = %d, aq_err = %d.",
9555 ret, hw->aq.asq_last_status);
9558 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9559 rte_free(mirr_rule);
9560 pf->nb_mirror_rule--;
9562 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9569 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9571 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9572 uint64_t systim_cycles;
9574 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9575 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9578 return systim_cycles;
9582 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9584 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9587 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9588 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9595 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9597 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9600 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9601 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9608 i40e_start_timecounters(struct rte_eth_dev *dev)
9610 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9611 struct i40e_adapter *adapter =
9612 (struct i40e_adapter *)dev->data->dev_private;
9613 struct rte_eth_link link;
9614 uint32_t tsync_inc_l;
9615 uint32_t tsync_inc_h;
9617 /* Get current link speed. */
9618 memset(&link, 0, sizeof(link));
9619 i40e_dev_link_update(dev, 1);
9620 rte_i40e_dev_atomic_read_link_status(dev, &link);
9622 switch (link.link_speed) {
9623 case ETH_SPEED_NUM_40G:
9624 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9625 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9627 case ETH_SPEED_NUM_10G:
9628 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9629 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9631 case ETH_SPEED_NUM_1G:
9632 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9633 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9640 /* Set the timesync increment value. */
9641 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9642 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9644 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9645 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9646 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9648 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9649 adapter->systime_tc.cc_shift = 0;
9650 adapter->systime_tc.nsec_mask = 0;
9652 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9653 adapter->rx_tstamp_tc.cc_shift = 0;
9654 adapter->rx_tstamp_tc.nsec_mask = 0;
9656 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9657 adapter->tx_tstamp_tc.cc_shift = 0;
9658 adapter->tx_tstamp_tc.nsec_mask = 0;
9662 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9664 struct i40e_adapter *adapter =
9665 (struct i40e_adapter *)dev->data->dev_private;
9667 adapter->systime_tc.nsec += delta;
9668 adapter->rx_tstamp_tc.nsec += delta;
9669 adapter->tx_tstamp_tc.nsec += delta;
9675 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9678 struct i40e_adapter *adapter =
9679 (struct i40e_adapter *)dev->data->dev_private;
9681 ns = rte_timespec_to_ns(ts);
9683 /* Set the timecounters to a new value. */
9684 adapter->systime_tc.nsec = ns;
9685 adapter->rx_tstamp_tc.nsec = ns;
9686 adapter->tx_tstamp_tc.nsec = ns;
9692 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9694 uint64_t ns, systime_cycles;
9695 struct i40e_adapter *adapter =
9696 (struct i40e_adapter *)dev->data->dev_private;
9698 systime_cycles = i40e_read_systime_cyclecounter(dev);
9699 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9700 *ts = rte_ns_to_timespec(ns);
9706 i40e_timesync_enable(struct rte_eth_dev *dev)
9708 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9709 uint32_t tsync_ctl_l;
9710 uint32_t tsync_ctl_h;
9712 /* Stop the timesync system time. */
9713 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9714 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9715 /* Reset the timesync system time value. */
9716 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9717 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9719 i40e_start_timecounters(dev);
9721 /* Clear timesync registers. */
9722 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9723 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9724 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9725 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9726 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9727 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9729 /* Enable timestamping of PTP packets. */
9730 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9731 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9733 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9734 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9735 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9737 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9738 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9744 i40e_timesync_disable(struct rte_eth_dev *dev)
9746 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9747 uint32_t tsync_ctl_l;
9748 uint32_t tsync_ctl_h;
9750 /* Disable timestamping of transmitted PTP packets. */
9751 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9752 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9754 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9755 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9757 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9758 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9760 /* Reset the timesync increment value. */
9761 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9762 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9768 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9769 struct timespec *timestamp, uint32_t flags)
9771 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9772 struct i40e_adapter *adapter =
9773 (struct i40e_adapter *)dev->data->dev_private;
9775 uint32_t sync_status;
9776 uint32_t index = flags & 0x03;
9777 uint64_t rx_tstamp_cycles;
9780 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9781 if ((sync_status & (1 << index)) == 0)
9784 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9785 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9786 *timestamp = rte_ns_to_timespec(ns);
9792 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9793 struct timespec *timestamp)
9795 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9796 struct i40e_adapter *adapter =
9797 (struct i40e_adapter *)dev->data->dev_private;
9799 uint32_t sync_status;
9800 uint64_t tx_tstamp_cycles;
9803 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9804 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9807 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9808 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9809 *timestamp = rte_ns_to_timespec(ns);
9815 * i40e_parse_dcb_configure - parse dcb configure from user
9816 * @dev: the device being configured
9817 * @dcb_cfg: pointer of the result of parse
9818 * @*tc_map: bit map of enabled traffic classes
9820 * Returns 0 on success, negative value on failure
9823 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9824 struct i40e_dcbx_config *dcb_cfg,
9827 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9828 uint8_t i, tc_bw, bw_lf;
9830 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9832 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9833 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9834 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9838 /* assume each tc has the same bw */
9839 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9840 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9841 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9842 /* to ensure the sum of tcbw is equal to 100 */
9843 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9844 for (i = 0; i < bw_lf; i++)
9845 dcb_cfg->etscfg.tcbwtable[i]++;
9847 /* assume each tc has the same Transmission Selection Algorithm */
9848 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9849 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9851 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9852 dcb_cfg->etscfg.prioritytable[i] =
9853 dcb_rx_conf->dcb_tc[i];
9855 /* FW needs one App to configure HW */
9856 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9857 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9858 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9859 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9861 if (dcb_rx_conf->nb_tcs == 0)
9862 *tc_map = 1; /* tc0 only */
9864 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9866 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9867 dcb_cfg->pfc.willing = 0;
9868 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9869 dcb_cfg->pfc.pfcenable = *tc_map;
9875 static enum i40e_status_code
9876 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9877 struct i40e_aqc_vsi_properties_data *info,
9878 uint8_t enabled_tcmap)
9880 enum i40e_status_code ret;
9881 int i, total_tc = 0;
9882 uint16_t qpnum_per_tc, bsf, qp_idx;
9883 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9884 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9885 uint16_t used_queues;
9887 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9888 if (ret != I40E_SUCCESS)
9891 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9892 if (enabled_tcmap & (1 << i))
9897 vsi->enabled_tc = enabled_tcmap;
9899 /* different VSI has different queues assigned */
9900 if (vsi->type == I40E_VSI_MAIN)
9901 used_queues = dev_data->nb_rx_queues -
9902 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9903 else if (vsi->type == I40E_VSI_VMDQ2)
9904 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9906 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9907 return I40E_ERR_NO_AVAILABLE_VSI;
9910 qpnum_per_tc = used_queues / total_tc;
9911 /* Number of queues per enabled TC */
9912 if (qpnum_per_tc == 0) {
9913 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9914 return I40E_ERR_INVALID_QP_ID;
9916 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9918 bsf = rte_bsf32(qpnum_per_tc);
9921 * Configure TC and queue mapping parameters, for enabled TC,
9922 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9923 * default queue will serve it.
9926 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9927 if (vsi->enabled_tc & (1 << i)) {
9928 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9929 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9930 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9931 qp_idx += qpnum_per_tc;
9933 info->tc_mapping[i] = 0;
9936 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9937 if (vsi->type == I40E_VSI_SRIOV) {
9938 info->mapping_flags |=
9939 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9940 for (i = 0; i < vsi->nb_qps; i++)
9941 info->queue_mapping[i] =
9942 rte_cpu_to_le_16(vsi->base_queue + i);
9944 info->mapping_flags |=
9945 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9946 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9948 info->valid_sections |=
9949 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9951 return I40E_SUCCESS;
9955 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9956 * @veb: VEB to be configured
9957 * @tc_map: enabled TC bitmap
9959 * Returns 0 on success, negative value on failure
9961 static enum i40e_status_code
9962 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9964 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9965 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9966 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9967 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9968 enum i40e_status_code ret = I40E_SUCCESS;
9972 /* Check if enabled_tc is same as existing or new TCs */
9973 if (veb->enabled_tc == tc_map)
9976 /* configure tc bandwidth */
9977 memset(&veb_bw, 0, sizeof(veb_bw));
9978 veb_bw.tc_valid_bits = tc_map;
9979 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9980 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9981 if (tc_map & BIT_ULL(i))
9982 veb_bw.tc_bw_share_credits[i] = 1;
9984 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9988 "AQ command Config switch_comp BW allocation per TC failed = %d",
9989 hw->aq.asq_last_status);
9993 memset(&ets_query, 0, sizeof(ets_query));
9994 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9996 if (ret != I40E_SUCCESS) {
9998 "Failed to get switch_comp ETS configuration %u",
9999 hw->aq.asq_last_status);
10002 memset(&bw_query, 0, sizeof(bw_query));
10003 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10005 if (ret != I40E_SUCCESS) {
10007 "Failed to get switch_comp bandwidth configuration %u",
10008 hw->aq.asq_last_status);
10012 /* store and print out BW info */
10013 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10014 veb->bw_info.bw_max = ets_query.tc_bw_max;
10015 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10016 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10017 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10018 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10019 I40E_16_BIT_WIDTH);
10020 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10021 veb->bw_info.bw_ets_share_credits[i] =
10022 bw_query.tc_bw_share_credits[i];
10023 veb->bw_info.bw_ets_credits[i] =
10024 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10025 /* 4 bits per TC, 4th bit is reserved */
10026 veb->bw_info.bw_ets_max[i] =
10027 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10028 RTE_LEN2MASK(3, uint8_t));
10029 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10030 veb->bw_info.bw_ets_share_credits[i]);
10031 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10032 veb->bw_info.bw_ets_credits[i]);
10033 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10034 veb->bw_info.bw_ets_max[i]);
10037 veb->enabled_tc = tc_map;
10044 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10045 * @vsi: VSI to be configured
10046 * @tc_map: enabled TC bitmap
10048 * Returns 0 on success, negative value on failure
10050 static enum i40e_status_code
10051 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10053 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10054 struct i40e_vsi_context ctxt;
10055 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10056 enum i40e_status_code ret = I40E_SUCCESS;
10059 /* Check if enabled_tc is same as existing or new TCs */
10060 if (vsi->enabled_tc == tc_map)
10063 /* configure tc bandwidth */
10064 memset(&bw_data, 0, sizeof(bw_data));
10065 bw_data.tc_valid_bits = tc_map;
10066 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10067 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10068 if (tc_map & BIT_ULL(i))
10069 bw_data.tc_bw_credits[i] = 1;
10071 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10074 "AQ command Config VSI BW allocation per TC failed = %d",
10075 hw->aq.asq_last_status);
10078 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10079 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10081 /* Update Queue Pairs Mapping for currently enabled UPs */
10082 ctxt.seid = vsi->seid;
10083 ctxt.pf_num = hw->pf_id;
10085 ctxt.uplink_seid = vsi->uplink_seid;
10086 ctxt.info = vsi->info;
10088 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10092 /* Update the VSI after updating the VSI queue-mapping information */
10093 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10095 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10096 hw->aq.asq_last_status);
10099 /* update the local VSI info with updated queue map */
10100 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10101 sizeof(vsi->info.tc_mapping));
10102 (void)rte_memcpy(&vsi->info.queue_mapping,
10103 &ctxt.info.queue_mapping,
10104 sizeof(vsi->info.queue_mapping));
10105 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10106 vsi->info.valid_sections = 0;
10108 /* query and update current VSI BW information */
10109 ret = i40e_vsi_get_bw_config(vsi);
10112 "Failed updating vsi bw info, err %s aq_err %s",
10113 i40e_stat_str(hw, ret),
10114 i40e_aq_str(hw, hw->aq.asq_last_status));
10118 vsi->enabled_tc = tc_map;
10125 * i40e_dcb_hw_configure - program the dcb setting to hw
10126 * @pf: pf the configuration is taken on
10127 * @new_cfg: new configuration
10128 * @tc_map: enabled TC bitmap
10130 * Returns 0 on success, negative value on failure
10132 static enum i40e_status_code
10133 i40e_dcb_hw_configure(struct i40e_pf *pf,
10134 struct i40e_dcbx_config *new_cfg,
10137 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10138 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10139 struct i40e_vsi *main_vsi = pf->main_vsi;
10140 struct i40e_vsi_list *vsi_list;
10141 enum i40e_status_code ret;
10145 /* Use the FW API if FW > v4.4*/
10146 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10147 (hw->aq.fw_maj_ver >= 5))) {
10149 "FW < v4.4, can not use FW LLDP API to configure DCB");
10150 return I40E_ERR_FIRMWARE_API_VERSION;
10153 /* Check if need reconfiguration */
10154 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10155 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10156 return I40E_SUCCESS;
10159 /* Copy the new config to the current config */
10160 *old_cfg = *new_cfg;
10161 old_cfg->etsrec = old_cfg->etscfg;
10162 ret = i40e_set_dcb_config(hw);
10164 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10165 i40e_stat_str(hw, ret),
10166 i40e_aq_str(hw, hw->aq.asq_last_status));
10169 /* set receive Arbiter to RR mode and ETS scheme by default */
10170 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10171 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10172 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10173 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10174 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10175 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10176 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10177 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10178 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10179 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10180 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10181 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10182 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10184 /* get local mib to check whether it is configured correctly */
10186 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10187 /* Get Local DCB Config */
10188 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10189 &hw->local_dcbx_config);
10191 /* if Veb is created, need to update TC of it at first */
10192 if (main_vsi->veb) {
10193 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10195 PMD_INIT_LOG(WARNING,
10196 "Failed configuring TC for VEB seid=%d",
10197 main_vsi->veb->seid);
10199 /* Update each VSI */
10200 i40e_vsi_config_tc(main_vsi, tc_map);
10201 if (main_vsi->veb) {
10202 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10203 /* Beside main VSI and VMDQ VSIs, only enable default
10204 * TC for other VSIs
10206 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10207 ret = i40e_vsi_config_tc(vsi_list->vsi,
10210 ret = i40e_vsi_config_tc(vsi_list->vsi,
10211 I40E_DEFAULT_TCMAP);
10213 PMD_INIT_LOG(WARNING,
10214 "Failed configuring TC for VSI seid=%d",
10215 vsi_list->vsi->seid);
10219 return I40E_SUCCESS;
10223 * i40e_dcb_init_configure - initial dcb config
10224 * @dev: device being configured
10225 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10227 * Returns 0 on success, negative value on failure
10230 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10232 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10233 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10236 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10237 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10241 /* DCB initialization:
10242 * Update DCB configuration from the Firmware and configure
10243 * LLDP MIB change event.
10245 if (sw_dcb == TRUE) {
10246 ret = i40e_init_dcb(hw);
10247 /* If lldp agent is stopped, the return value from
10248 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10249 * adminq status. Otherwise, it should return success.
10251 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10252 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10253 memset(&hw->local_dcbx_config, 0,
10254 sizeof(struct i40e_dcbx_config));
10255 /* set dcb default configuration */
10256 hw->local_dcbx_config.etscfg.willing = 0;
10257 hw->local_dcbx_config.etscfg.maxtcs = 0;
10258 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10259 hw->local_dcbx_config.etscfg.tsatable[0] =
10261 /* all UPs mapping to TC0 */
10262 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10263 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10264 hw->local_dcbx_config.etsrec =
10265 hw->local_dcbx_config.etscfg;
10266 hw->local_dcbx_config.pfc.willing = 0;
10267 hw->local_dcbx_config.pfc.pfccap =
10268 I40E_MAX_TRAFFIC_CLASS;
10269 hw->local_dcbx_config.pfc.pfcenable =
10270 I40E_DEFAULT_TCMAP;
10271 /* FW needs one App to configure HW */
10272 hw->local_dcbx_config.numapps = 1;
10273 hw->local_dcbx_config.app[0].selector =
10274 I40E_APP_SEL_ETHTYPE;
10275 hw->local_dcbx_config.app[0].priority = 3;
10276 hw->local_dcbx_config.app[0].protocolid =
10277 I40E_APP_PROTOID_FCOE;
10278 ret = i40e_set_dcb_config(hw);
10281 "default dcb config fails. err = %d, aq_err = %d.",
10282 ret, hw->aq.asq_last_status);
10287 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10288 ret, hw->aq.asq_last_status);
10292 ret = i40e_aq_start_lldp(hw, NULL);
10293 if (ret != I40E_SUCCESS)
10294 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10296 ret = i40e_init_dcb(hw);
10298 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10300 "HW doesn't support DCBX offload.");
10305 "DCBX configuration failed, err = %d, aq_err = %d.",
10306 ret, hw->aq.asq_last_status);
10314 * i40e_dcb_setup - setup dcb related config
10315 * @dev: device being configured
10317 * Returns 0 on success, negative value on failure
10320 i40e_dcb_setup(struct rte_eth_dev *dev)
10322 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10323 struct i40e_dcbx_config dcb_cfg;
10324 uint8_t tc_map = 0;
10327 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10328 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10332 if (pf->vf_num != 0)
10333 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10335 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10337 PMD_INIT_LOG(ERR, "invalid dcb config");
10340 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10342 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10350 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10351 struct rte_eth_dcb_info *dcb_info)
10353 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10354 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10355 struct i40e_vsi *vsi = pf->main_vsi;
10356 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10357 uint16_t bsf, tc_mapping;
10360 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10361 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10363 dcb_info->nb_tcs = 1;
10364 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10365 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10366 for (i = 0; i < dcb_info->nb_tcs; i++)
10367 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10369 /* get queue mapping if vmdq is disabled */
10370 if (!pf->nb_cfg_vmdq_vsi) {
10371 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10372 if (!(vsi->enabled_tc & (1 << i)))
10374 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10375 dcb_info->tc_queue.tc_rxq[j][i].base =
10376 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10377 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10378 dcb_info->tc_queue.tc_txq[j][i].base =
10379 dcb_info->tc_queue.tc_rxq[j][i].base;
10380 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10381 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10382 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10383 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10384 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10389 /* get queue mapping if vmdq is enabled */
10391 vsi = pf->vmdq[j].vsi;
10392 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10393 if (!(vsi->enabled_tc & (1 << i)))
10395 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10396 dcb_info->tc_queue.tc_rxq[j][i].base =
10397 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10398 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10399 dcb_info->tc_queue.tc_txq[j][i].base =
10400 dcb_info->tc_queue.tc_rxq[j][i].base;
10401 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10402 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10403 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10404 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10405 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10408 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10413 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10415 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10416 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10417 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10418 uint16_t interval =
10419 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10420 uint16_t msix_intr;
10422 msix_intr = intr_handle->intr_vec[queue_id];
10423 if (msix_intr == I40E_MISC_VEC_ID)
10424 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10425 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10426 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10427 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10429 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10432 I40E_PFINT_DYN_CTLN(msix_intr -
10433 I40E_RX_VEC_START),
10434 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10435 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10436 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10438 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10440 I40E_WRITE_FLUSH(hw);
10441 rte_intr_enable(&pci_dev->intr_handle);
10447 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10449 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10450 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10451 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10452 uint16_t msix_intr;
10454 msix_intr = intr_handle->intr_vec[queue_id];
10455 if (msix_intr == I40E_MISC_VEC_ID)
10456 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10459 I40E_PFINT_DYN_CTLN(msix_intr -
10460 I40E_RX_VEC_START),
10462 I40E_WRITE_FLUSH(hw);
10467 static int i40e_get_regs(struct rte_eth_dev *dev,
10468 struct rte_dev_reg_info *regs)
10470 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10471 uint32_t *ptr_data = regs->data;
10472 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10473 const struct i40e_reg_info *reg_info;
10475 if (ptr_data == NULL) {
10476 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10477 regs->width = sizeof(uint32_t);
10481 /* The first few registers have to be read using AQ operations */
10483 while (i40e_regs_adminq[reg_idx].name) {
10484 reg_info = &i40e_regs_adminq[reg_idx++];
10485 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10487 arr_idx2 <= reg_info->count2;
10489 reg_offset = arr_idx * reg_info->stride1 +
10490 arr_idx2 * reg_info->stride2;
10491 reg_offset += reg_info->base_addr;
10492 ptr_data[reg_offset >> 2] =
10493 i40e_read_rx_ctl(hw, reg_offset);
10497 /* The remaining registers can be read using primitives */
10499 while (i40e_regs_others[reg_idx].name) {
10500 reg_info = &i40e_regs_others[reg_idx++];
10501 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10503 arr_idx2 <= reg_info->count2;
10505 reg_offset = arr_idx * reg_info->stride1 +
10506 arr_idx2 * reg_info->stride2;
10507 reg_offset += reg_info->base_addr;
10508 ptr_data[reg_offset >> 2] =
10509 I40E_READ_REG(hw, reg_offset);
10516 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10518 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10520 /* Convert word count to byte count */
10521 return hw->nvm.sr_size << 1;
10524 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10525 struct rte_dev_eeprom_info *eeprom)
10527 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10528 uint16_t *data = eeprom->data;
10529 uint16_t offset, length, cnt_words;
10532 offset = eeprom->offset >> 1;
10533 length = eeprom->length >> 1;
10534 cnt_words = length;
10536 if (offset > hw->nvm.sr_size ||
10537 offset + length > hw->nvm.sr_size) {
10538 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10542 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10544 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10545 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10546 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10553 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10554 struct ether_addr *mac_addr)
10556 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10558 if (!is_valid_assigned_ether_addr(mac_addr)) {
10559 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10563 /* Flags: 0x3 updates port address */
10564 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10568 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10571 struct rte_eth_dev_data *dev_data = pf->dev_data;
10572 uint32_t frame_size = mtu + ETHER_HDR_LEN
10573 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10576 /* check if mtu is within the allowed range */
10577 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10580 /* mtu setting is forbidden if port is start */
10581 if (dev_data->dev_started) {
10582 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10583 dev_data->port_id);
10587 if (frame_size > ETHER_MAX_LEN)
10588 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10590 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10592 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10597 /* Restore ethertype filter */
10599 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10601 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10602 struct i40e_ethertype_filter_list
10603 *ethertype_list = &pf->ethertype.ethertype_list;
10604 struct i40e_ethertype_filter *f;
10605 struct i40e_control_filter_stats stats;
10608 TAILQ_FOREACH(f, ethertype_list, rules) {
10610 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10611 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10612 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10613 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10614 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10616 memset(&stats, 0, sizeof(stats));
10617 i40e_aq_add_rem_control_packet_filter(hw,
10618 f->input.mac_addr.addr_bytes,
10619 f->input.ether_type,
10620 flags, pf->main_vsi->seid,
10621 f->queue, 1, &stats, NULL);
10623 PMD_DRV_LOG(INFO, "Ethertype filter:"
10624 " mac_etype_used = %u, etype_used = %u,"
10625 " mac_etype_free = %u, etype_free = %u",
10626 stats.mac_etype_used, stats.etype_used,
10627 stats.mac_etype_free, stats.etype_free);
10630 /* Restore tunnel filter */
10632 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10634 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10635 struct i40e_vsi *vsi;
10636 struct i40e_pf_vf *vf;
10637 struct i40e_tunnel_filter_list
10638 *tunnel_list = &pf->tunnel.tunnel_list;
10639 struct i40e_tunnel_filter *f;
10640 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10641 bool big_buffer = 0;
10643 TAILQ_FOREACH(f, tunnel_list, rules) {
10645 vsi = pf->main_vsi;
10647 vf = &pf->vfs[f->vf_id];
10650 memset(&cld_filter, 0, sizeof(cld_filter));
10651 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10652 (struct ether_addr *)&cld_filter.element.outer_mac);
10653 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10654 (struct ether_addr *)&cld_filter.element.inner_mac);
10655 cld_filter.element.inner_vlan = f->input.inner_vlan;
10656 cld_filter.element.flags = f->input.flags;
10657 cld_filter.element.tenant_id = f->input.tenant_id;
10658 cld_filter.element.queue_number = f->queue;
10659 rte_memcpy(cld_filter.general_fields,
10660 f->input.general_fields,
10661 sizeof(f->input.general_fields));
10663 if (((f->input.flags &
10664 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10665 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10667 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10668 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10670 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10671 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10675 i40e_aq_add_cloud_filters_big_buffer(hw,
10676 vsi->seid, &cld_filter, 1);
10678 i40e_aq_add_cloud_filters(hw, vsi->seid,
10679 &cld_filter.element, 1);
10684 i40e_filter_restore(struct i40e_pf *pf)
10686 i40e_ethertype_filter_restore(pf);
10687 i40e_tunnel_filter_restore(pf);
10688 i40e_fdir_filter_restore(pf);
10692 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10694 if (strcmp(dev->driver->pci_drv.driver.name,
10695 drv->pci_drv.driver.name))
10702 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10704 struct rte_eth_dev *dev;
10705 struct i40e_pf *pf;
10707 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10709 dev = &rte_eth_devices[port];
10711 if (!is_device_supported(dev, &rte_i40e_pmd))
10714 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10716 if (vf >= pf->vf_num || !pf->vfs) {
10717 PMD_DRV_LOG(ERR, "Invalid argument.");
10721 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10727 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10729 struct rte_eth_dev *dev;
10730 struct i40e_pf *pf;
10731 struct i40e_vsi *vsi;
10732 struct i40e_hw *hw;
10733 struct i40e_vsi_context ctxt;
10736 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10738 dev = &rte_eth_devices[port];
10740 if (!is_device_supported(dev, &rte_i40e_pmd))
10743 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10745 if (vf_id >= pf->vf_num || !pf->vfs) {
10746 PMD_DRV_LOG(ERR, "Invalid argument.");
10750 vsi = pf->vfs[vf_id].vsi;
10752 PMD_DRV_LOG(ERR, "Invalid VSI.");
10756 /* Check if it has been already on or off */
10757 if (vsi->info.valid_sections &
10758 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10760 if ((vsi->info.sec_flags &
10761 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10762 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10763 return 0; /* already on */
10765 if ((vsi->info.sec_flags &
10766 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10767 return 0; /* already off */
10771 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10773 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10775 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10777 memset(&ctxt, 0, sizeof(ctxt));
10778 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10779 ctxt.seid = vsi->seid;
10781 hw = I40E_VSI_TO_HW(vsi);
10782 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10783 if (ret != I40E_SUCCESS) {
10785 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10792 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10796 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10797 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10800 for (j = 0; j < I40E_VFTA_SIZE; j++) {
10804 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10805 if (!(vsi->vfta[j] & (1 << k)))
10808 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10812 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10814 ret = i40e_aq_add_vlan(hw, vsi->seid,
10815 &vlan_data, 1, NULL);
10817 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10818 &vlan_data, 1, NULL);
10819 if (ret != I40E_SUCCESS) {
10821 "Failed to add/rm vlan filter");
10827 return I40E_SUCCESS;
10831 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10833 struct rte_eth_dev *dev;
10834 struct i40e_pf *pf;
10835 struct i40e_vsi *vsi;
10836 struct i40e_hw *hw;
10837 struct i40e_vsi_context ctxt;
10840 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10842 dev = &rte_eth_devices[port];
10844 if (!is_device_supported(dev, &rte_i40e_pmd))
10847 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10849 if (vf_id >= pf->vf_num || !pf->vfs) {
10850 PMD_DRV_LOG(ERR, "Invalid argument.");
10854 vsi = pf->vfs[vf_id].vsi;
10856 PMD_DRV_LOG(ERR, "Invalid VSI.");
10860 /* Check if it has been already on or off */
10861 if (vsi->vlan_anti_spoof_on == on)
10862 return 0; /* already on or off */
10864 vsi->vlan_anti_spoof_on = on;
10865 if (!vsi->vlan_filter_on) {
10866 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10868 PMD_DRV_LOG(ERR, "Failed to add/remove VLAN filters.");
10873 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10875 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10877 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10879 memset(&ctxt, 0, sizeof(ctxt));
10880 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10881 ctxt.seid = vsi->seid;
10883 hw = I40E_VSI_TO_HW(vsi);
10884 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10885 if (ret != I40E_SUCCESS) {
10887 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10894 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10896 struct i40e_mac_filter *f;
10897 struct i40e_macvlan_filter *mv_f;
10899 enum rte_mac_filter_type filter_type;
10900 int ret = I40E_SUCCESS;
10903 /* remove all the MACs */
10904 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10905 vlan_num = vsi->vlan_num;
10906 filter_type = f->mac_info.filter_type;
10907 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10908 filter_type == RTE_MACVLAN_HASH_MATCH) {
10909 if (vlan_num == 0) {
10910 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10911 return I40E_ERR_PARAM;
10913 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10914 filter_type == RTE_MAC_HASH_MATCH)
10917 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10919 PMD_DRV_LOG(ERR, "failed to allocate memory");
10920 return I40E_ERR_NO_MEMORY;
10923 for (i = 0; i < vlan_num; i++) {
10924 mv_f[i].filter_type = filter_type;
10925 (void)rte_memcpy(&mv_f[i].macaddr,
10926 &f->mac_info.mac_addr,
10929 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10930 filter_type == RTE_MACVLAN_HASH_MATCH) {
10931 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10932 &f->mac_info.mac_addr);
10933 if (ret != I40E_SUCCESS) {
10939 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10940 if (ret != I40E_SUCCESS) {
10946 ret = I40E_SUCCESS;
10953 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10955 struct i40e_mac_filter *f;
10956 struct i40e_macvlan_filter *mv_f;
10957 int i, vlan_num = 0;
10958 int ret = I40E_SUCCESS;
10961 /* restore all the MACs */
10962 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10963 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10964 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10966 * If vlan_num is 0, that's the first time to add mac,
10967 * set mask for vlan_id 0.
10969 if (vsi->vlan_num == 0) {
10970 i40e_set_vlan_filter(vsi, 0, 1);
10973 vlan_num = vsi->vlan_num;
10974 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10975 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10978 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10980 PMD_DRV_LOG(ERR, "failed to allocate memory");
10981 return I40E_ERR_NO_MEMORY;
10984 for (i = 0; i < vlan_num; i++) {
10985 mv_f[i].filter_type = f->mac_info.filter_type;
10986 (void)rte_memcpy(&mv_f[i].macaddr,
10987 &f->mac_info.mac_addr,
10991 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10992 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10993 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10994 &f->mac_info.mac_addr);
10995 if (ret != I40E_SUCCESS) {
11001 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
11002 if (ret != I40E_SUCCESS) {
11008 ret = I40E_SUCCESS;
11015 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
11017 struct i40e_vsi_context ctxt;
11018 struct i40e_hw *hw;
11024 hw = I40E_VSI_TO_HW(vsi);
11026 /* Use the FW API if FW >= v5.0 */
11027 if (hw->aq.fw_maj_ver < 5) {
11028 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
11032 /* Check if it has been already on or off */
11033 if (vsi->info.valid_sections &
11034 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
11036 if ((vsi->info.switch_id &
11037 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
11038 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
11039 return 0; /* already on */
11041 if ((vsi->info.switch_id &
11042 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
11043 return 0; /* already off */
11047 /* remove all the MAC and VLAN first */
11048 ret = i40e_vsi_rm_mac_filter(vsi);
11050 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
11053 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11054 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
11056 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
11061 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
11063 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11065 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
11067 memset(&ctxt, 0, sizeof(ctxt));
11068 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11069 ctxt.seid = vsi->seid;
11071 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11072 if (ret != I40E_SUCCESS) {
11073 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11077 /* add all the MAC and VLAN back */
11078 ret = i40e_vsi_restore_mac_filter(vsi);
11081 if (vsi->vlan_anti_spoof_on || vsi->vlan_filter_on) {
11082 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
11091 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
11093 struct rte_eth_dev *dev;
11094 struct i40e_pf *pf;
11095 struct i40e_pf_vf *vf;
11096 struct i40e_vsi *vsi;
11100 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11102 dev = &rte_eth_devices[port];
11104 if (!is_device_supported(dev, &rte_i40e_pmd))
11107 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11109 /* setup PF TX loopback */
11110 vsi = pf->main_vsi;
11111 ret = i40e_vsi_set_tx_loopback(vsi, on);
11115 /* setup TX loopback for all the VFs */
11117 /* if no VF, do nothing. */
11121 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
11122 vf = &pf->vfs[vf_id];
11125 ret = i40e_vsi_set_tx_loopback(vsi, on);
11134 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11136 struct rte_eth_dev *dev;
11137 struct i40e_pf *pf;
11138 struct i40e_vsi *vsi;
11139 struct i40e_hw *hw;
11142 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11144 dev = &rte_eth_devices[port];
11146 if (!is_device_supported(dev, &rte_i40e_pmd))
11149 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11151 if (vf_id >= pf->vf_num || !pf->vfs) {
11152 PMD_DRV_LOG(ERR, "Invalid argument.");
11156 vsi = pf->vfs[vf_id].vsi;
11158 PMD_DRV_LOG(ERR, "Invalid VSI.");
11162 hw = I40E_VSI_TO_HW(vsi);
11164 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
11166 if (ret != I40E_SUCCESS) {
11168 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
11175 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
11177 struct rte_eth_dev *dev;
11178 struct i40e_pf *pf;
11179 struct i40e_vsi *vsi;
11180 struct i40e_hw *hw;
11183 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11185 dev = &rte_eth_devices[port];
11187 if (!is_device_supported(dev, &rte_i40e_pmd))
11190 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11192 if (vf_id >= pf->vf_num || !pf->vfs) {
11193 PMD_DRV_LOG(ERR, "Invalid argument.");
11197 vsi = pf->vfs[vf_id].vsi;
11199 PMD_DRV_LOG(ERR, "Invalid VSI.");
11203 hw = I40E_VSI_TO_HW(vsi);
11205 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
11207 if (ret != I40E_SUCCESS) {
11209 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
11216 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
11217 struct ether_addr *mac_addr)
11219 struct i40e_mac_filter *f;
11220 struct rte_eth_dev *dev;
11221 struct i40e_pf_vf *vf;
11222 struct i40e_vsi *vsi;
11223 struct i40e_pf *pf;
11226 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
11229 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11231 dev = &rte_eth_devices[port];
11233 if (!is_device_supported(dev, &rte_i40e_pmd))
11236 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11238 if (vf_id >= pf->vf_num || !pf->vfs)
11241 vf = &pf->vfs[vf_id];
11244 PMD_DRV_LOG(ERR, "Invalid VSI.");
11248 ether_addr_copy(mac_addr, &vf->mac_addr);
11250 /* Remove all existing mac */
11251 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
11252 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
11257 /* Set vlan strip on/off for specific VF from host */
11259 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
11261 struct rte_eth_dev *dev;
11262 struct i40e_pf *pf;
11263 struct i40e_vsi *vsi;
11266 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11268 dev = &rte_eth_devices[port];
11270 if (!is_device_supported(dev, &rte_i40e_pmd))
11273 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11275 if (vf_id >= pf->vf_num || !pf->vfs) {
11276 PMD_DRV_LOG(ERR, "Invalid argument.");
11280 vsi = pf->vfs[vf_id].vsi;
11285 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
11286 if (ret != I40E_SUCCESS) {
11288 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
11294 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
11297 struct rte_eth_dev *dev;
11298 struct i40e_pf *pf;
11299 struct i40e_hw *hw;
11300 struct i40e_vsi *vsi;
11301 struct i40e_vsi_context ctxt;
11304 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11306 if (vlan_id > ETHER_MAX_VLAN_ID) {
11307 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11311 dev = &rte_eth_devices[port];
11313 if (!is_device_supported(dev, &rte_i40e_pmd))
11316 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11317 hw = I40E_PF_TO_HW(pf);
11320 * return -ENODEV if SRIOV not enabled, VF number not configured
11321 * or no queue assigned.
11323 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11324 pf->vf_nb_qps == 0)
11327 if (vf_id >= pf->vf_num || !pf->vfs) {
11328 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11332 vsi = pf->vfs[vf_id].vsi;
11334 PMD_DRV_LOG(ERR, "Invalid VSI.");
11338 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11339 vsi->info.pvid = vlan_id;
11341 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
11343 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
11345 memset(&ctxt, 0, sizeof(ctxt));
11346 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11347 ctxt.seid = vsi->seid;
11349 hw = I40E_VSI_TO_HW(vsi);
11350 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11351 if (ret != I40E_SUCCESS) {
11353 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11359 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
11362 struct rte_eth_dev *dev;
11363 struct i40e_pf *pf;
11364 struct i40e_vsi *vsi;
11365 struct i40e_hw *hw;
11366 struct i40e_mac_filter_info filter;
11367 struct ether_addr broadcast = {
11368 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
11371 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11374 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11378 dev = &rte_eth_devices[port];
11380 if (!is_device_supported(dev, &rte_i40e_pmd))
11383 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11384 hw = I40E_PF_TO_HW(pf);
11386 if (vf_id >= pf->vf_num || !pf->vfs) {
11387 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11392 * return -ENODEV if SRIOV not enabled, VF number not configured
11393 * or no queue assigned.
11395 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11396 pf->vf_nb_qps == 0) {
11397 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11401 vsi = pf->vfs[vf_id].vsi;
11403 PMD_DRV_LOG(ERR, "Invalid VSI.");
11408 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11409 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11410 ret = i40e_vsi_add_mac(vsi, &filter);
11412 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11415 if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11417 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11425 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11427 struct rte_eth_dev *dev;
11428 struct i40e_pf *pf;
11429 struct i40e_hw *hw;
11430 struct i40e_vsi *vsi;
11431 struct i40e_vsi_context ctxt;
11434 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11437 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11441 dev = &rte_eth_devices[port];
11443 if (!is_device_supported(dev, &rte_i40e_pmd))
11446 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11447 hw = I40E_PF_TO_HW(pf);
11450 * return -ENODEV if SRIOV not enabled, VF number not configured
11451 * or no queue assigned.
11453 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11454 pf->vf_nb_qps == 0) {
11455 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11459 if (vf_id >= pf->vf_num || !pf->vfs) {
11460 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11464 vsi = pf->vfs[vf_id].vsi;
11466 PMD_DRV_LOG(ERR, "Invalid VSI.");
11470 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11472 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11473 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11475 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11476 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11479 memset(&ctxt, 0, sizeof(ctxt));
11480 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11481 ctxt.seid = vsi->seid;
11483 hw = I40E_VSI_TO_HW(vsi);
11484 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11485 if (ret != I40E_SUCCESS) {
11487 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11494 i40e_vlan_filter_count(struct i40e_vsi *vsi)
11500 for (j = 0; j < I40E_VFTA_SIZE; j++) {
11504 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
11505 if (!(vsi->vfta[j] & (1 << k)))
11508 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
11519 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11520 uint64_t vf_mask, uint8_t on)
11522 struct rte_eth_dev *dev;
11523 struct i40e_pf *pf;
11524 struct i40e_hw *hw;
11525 struct i40e_vsi *vsi;
11527 int ret = I40E_SUCCESS;
11529 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11531 dev = &rte_eth_devices[port];
11533 if (!is_device_supported(dev, &rte_i40e_pmd))
11536 if (vlan_id > ETHER_MAX_VLAN_ID || !vlan_id) {
11537 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11541 if (vf_mask == 0) {
11542 PMD_DRV_LOG(ERR, "No VF.");
11547 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11551 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11552 hw = I40E_PF_TO_HW(pf);
11555 * return -ENODEV if SRIOV not enabled, VF number not configured
11556 * or no queue assigned.
11558 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11559 pf->vf_nb_qps == 0) {
11560 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11564 for (vf_idx = 0; vf_idx < pf->vf_num && ret == I40E_SUCCESS; vf_idx++) {
11565 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11566 vsi = pf->vfs[vf_idx].vsi;
11568 if (!vsi->vlan_filter_on) {
11569 vsi->vlan_filter_on = true;
11570 i40e_aq_set_vsi_vlan_promisc(hw,
11574 if (!vsi->vlan_anti_spoof_on)
11575 i40e_add_rm_all_vlan_filter(
11578 ret = i40e_vsi_add_vlan(vsi, vlan_id);
11580 ret = i40e_vsi_delete_vlan(vsi, vlan_id);
11582 if (!i40e_vlan_filter_count(vsi)) {
11583 vsi->vlan_filter_on = false;
11584 i40e_aq_set_vsi_vlan_promisc(hw,
11593 if (ret != I40E_SUCCESS) {
11595 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11602 rte_pmd_i40e_get_vf_stats(uint8_t port,
11604 struct rte_eth_stats *stats)
11606 struct rte_eth_dev *dev;
11607 struct i40e_pf *pf;
11608 struct i40e_vsi *vsi;
11610 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11612 dev = &rte_eth_devices[port];
11614 if (!is_device_supported(dev, &rte_i40e_pmd))
11617 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11619 if (vf_id >= pf->vf_num || !pf->vfs) {
11620 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11624 vsi = pf->vfs[vf_id].vsi;
11626 PMD_DRV_LOG(ERR, "Invalid VSI.");
11630 i40e_update_vsi_stats(vsi);
11632 stats->ipackets = vsi->eth_stats.rx_unicast +
11633 vsi->eth_stats.rx_multicast +
11634 vsi->eth_stats.rx_broadcast;
11635 stats->opackets = vsi->eth_stats.tx_unicast +
11636 vsi->eth_stats.tx_multicast +
11637 vsi->eth_stats.tx_broadcast;
11638 stats->ibytes = vsi->eth_stats.rx_bytes;
11639 stats->obytes = vsi->eth_stats.tx_bytes;
11640 stats->ierrors = vsi->eth_stats.rx_discards;
11641 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11647 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11650 struct rte_eth_dev *dev;
11651 struct i40e_pf *pf;
11652 struct i40e_vsi *vsi;
11654 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11656 dev = &rte_eth_devices[port];
11658 if (!is_device_supported(dev, &rte_i40e_pmd))
11661 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11663 if (vf_id >= pf->vf_num || !pf->vfs) {
11664 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11668 vsi = pf->vfs[vf_id].vsi;
11670 PMD_DRV_LOG(ERR, "Invalid VSI.");
11674 vsi->offset_loaded = false;
11675 i40e_update_vsi_stats(vsi);
11681 rte_pmd_i40e_set_vf_max_bw(uint8_t port, uint16_t vf_id, uint32_t bw)
11683 struct rte_eth_dev *dev;
11684 struct i40e_pf *pf;
11685 struct i40e_vsi *vsi;
11686 struct i40e_hw *hw;
11690 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11692 dev = &rte_eth_devices[port];
11694 if (!is_device_supported(dev, &rte_i40e_pmd))
11697 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11699 if (vf_id >= pf->vf_num || !pf->vfs) {
11700 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11704 vsi = pf->vfs[vf_id].vsi;
11706 PMD_DRV_LOG(ERR, "Invalid VSI.");
11710 if (bw > I40E_QOS_BW_MAX) {
11711 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11716 if (bw % I40E_QOS_BW_GRANULARITY) {
11717 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11718 I40E_QOS_BW_GRANULARITY);
11722 bw /= I40E_QOS_BW_GRANULARITY;
11724 hw = I40E_VSI_TO_HW(vsi);
11727 if (bw == vsi->bw_info.bw_limit) {
11729 "No change for VF max bandwidth. Nothing to do.");
11734 * VF bandwidth limitation and TC bandwidth limitation cannot be
11735 * enabled in parallel, quit if TC bandwidth limitation is enabled.
11737 * If bw is 0, means disable bandwidth limitation. Then no need to
11738 * check TC bandwidth limitation.
11741 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11742 if ((vsi->enabled_tc & BIT_ULL(i)) &&
11743 vsi->bw_info.bw_ets_credits[i])
11746 if (i != I40E_MAX_TRAFFIC_CLASS) {
11748 "TC max bandwidth has been set on this VF,"
11749 " please disable it first.");
11754 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, (uint16_t)bw, 0, NULL);
11757 "Failed to set VF %d bandwidth, err(%d).",
11762 /* Store the configuration. */
11763 vsi->bw_info.bw_limit = (uint16_t)bw;
11764 vsi->bw_info.bw_max = 0;
11770 rte_pmd_i40e_set_vf_tc_bw_alloc(uint8_t port, uint16_t vf_id,
11771 uint8_t tc_num, uint8_t *bw_weight)
11773 struct rte_eth_dev *dev;
11774 struct i40e_pf *pf;
11775 struct i40e_vsi *vsi;
11776 struct i40e_hw *hw;
11777 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw;
11781 bool b_change = false;
11783 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11785 dev = &rte_eth_devices[port];
11787 if (!is_device_supported(dev, &rte_i40e_pmd))
11790 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11792 if (vf_id >= pf->vf_num || !pf->vfs) {
11793 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11797 vsi = pf->vfs[vf_id].vsi;
11799 PMD_DRV_LOG(ERR, "Invalid VSI.");
11803 if (tc_num > I40E_MAX_TRAFFIC_CLASS) {
11804 PMD_DRV_LOG(ERR, "TCs should be no more than %d.",
11805 I40E_MAX_TRAFFIC_CLASS);
11810 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11811 if (vsi->enabled_tc & BIT_ULL(i))
11814 if (sum != tc_num) {
11816 "Weight should be set for all %d enabled TCs.",
11822 for (i = 0; i < tc_num; i++) {
11823 if (!bw_weight[i]) {
11825 "The weight should be 1 at least.");
11828 sum += bw_weight[i];
11832 "The summary of the TC weight should be 100.");
11837 * Create the configuration for all the TCs.
11839 memset(&tc_bw, 0, sizeof(tc_bw));
11840 tc_bw.tc_valid_bits = vsi->enabled_tc;
11842 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11843 if (vsi->enabled_tc & BIT_ULL(i)) {
11844 if (bw_weight[j] !=
11845 vsi->bw_info.bw_ets_share_credits[i])
11848 tc_bw.tc_bw_credits[i] = bw_weight[j];
11856 "No change for TC allocated bandwidth."
11857 " Nothing to do.");
11861 hw = I40E_VSI_TO_HW(vsi);
11863 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw, NULL);
11866 "Failed to set VF %d TC bandwidth weight, err(%d).",
11871 /* Store the configuration. */
11873 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11874 if (vsi->enabled_tc & BIT_ULL(i)) {
11875 vsi->bw_info.bw_ets_share_credits[i] = bw_weight[j];
11884 rte_pmd_i40e_set_vf_tc_max_bw(uint8_t port, uint16_t vf_id,
11885 uint8_t tc_no, uint32_t bw)
11887 struct rte_eth_dev *dev;
11888 struct i40e_pf *pf;
11889 struct i40e_vsi *vsi;
11890 struct i40e_hw *hw;
11891 struct i40e_aqc_configure_vsi_ets_sla_bw_data tc_bw;
11895 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11897 dev = &rte_eth_devices[port];
11899 if (!is_device_supported(dev, &rte_i40e_pmd))
11902 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11904 if (vf_id >= pf->vf_num || !pf->vfs) {
11905 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11909 vsi = pf->vfs[vf_id].vsi;
11911 PMD_DRV_LOG(ERR, "Invalid VSI.");
11915 if (bw > I40E_QOS_BW_MAX) {
11916 PMD_DRV_LOG(ERR, "Bandwidth should not be larger than %dMbps.",
11921 if (bw % I40E_QOS_BW_GRANULARITY) {
11922 PMD_DRV_LOG(ERR, "Bandwidth should be the multiple of %dMbps.",
11923 I40E_QOS_BW_GRANULARITY);
11927 bw /= I40E_QOS_BW_GRANULARITY;
11929 if (tc_no >= I40E_MAX_TRAFFIC_CLASS) {
11930 PMD_DRV_LOG(ERR, "TC No. should be less than %d.",
11931 I40E_MAX_TRAFFIC_CLASS);
11935 hw = I40E_VSI_TO_HW(vsi);
11937 if (!(vsi->enabled_tc & BIT_ULL(tc_no))) {
11938 PMD_DRV_LOG(ERR, "VF %d TC %d isn't enabled.",
11944 if (bw == vsi->bw_info.bw_ets_credits[tc_no]) {
11946 "No change for TC max bandwidth. Nothing to do.");
11951 * VF bandwidth limitation and TC bandwidth limitation cannot be
11952 * enabled in parallel, disable VF bandwidth limitation if it's
11954 * If bw is 0, means disable bandwidth limitation. Then no need to
11955 * care about VF bandwidth limitation configuration.
11957 if (bw && vsi->bw_info.bw_limit) {
11958 ret = i40e_aq_config_vsi_bw_limit(hw, vsi->seid, 0, 0, NULL);
11961 "Failed to disable VF(%d)"
11962 " bandwidth limitation, err(%d).",
11968 "VF max bandwidth is disabled according"
11969 " to TC max bandwidth setting.");
11973 * Get all the TCs' info to create a whole picture.
11974 * Because the incremental change isn't permitted.
11976 memset(&tc_bw, 0, sizeof(tc_bw));
11977 tc_bw.tc_valid_bits = vsi->enabled_tc;
11978 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11979 if (vsi->enabled_tc & BIT_ULL(i)) {
11980 tc_bw.tc_bw_credits[i] =
11982 vsi->bw_info.bw_ets_credits[i]);
11985 tc_bw.tc_bw_credits[tc_no] = rte_cpu_to_le_16((uint16_t)bw);
11987 ret = i40e_aq_config_vsi_ets_sla_bw_limit(hw, vsi->seid, &tc_bw, NULL);
11990 "Failed to set VF %d TC %d max bandwidth, err(%d).",
11991 vf_id, tc_no, ret);
11995 /* Store the configuration. */
11996 vsi->bw_info.bw_ets_credits[tc_no] = (uint16_t)bw;
12002 rte_pmd_i40e_set_tc_strict_prio(uint8_t port, uint8_t tc_map)
12004 struct rte_eth_dev *dev;
12005 struct i40e_pf *pf;
12006 struct i40e_vsi *vsi;
12007 struct i40e_veb *veb;
12008 struct i40e_hw *hw;
12009 struct i40e_aqc_configure_switching_comp_ets_data ets_data;
12013 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12015 dev = &rte_eth_devices[port];
12017 if (!is_device_supported(dev, &rte_i40e_pmd))
12020 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12022 vsi = pf->main_vsi;
12024 PMD_DRV_LOG(ERR, "Invalid VSI.");
12030 PMD_DRV_LOG(ERR, "Invalid VEB.");
12034 if ((tc_map & veb->enabled_tc) != tc_map) {
12036 "TC bitmap isn't the subset of enabled TCs 0x%x.",
12041 if (tc_map == veb->strict_prio_tc) {
12042 PMD_DRV_LOG(INFO, "No change for TC bitmap. Nothing to do.");
12046 hw = I40E_VSI_TO_HW(vsi);
12048 /* Disable DCBx if it's the first time to set strict priority. */
12049 if (!veb->strict_prio_tc) {
12050 ret = i40e_aq_stop_lldp(hw, true, NULL);
12053 "Failed to disable DCBx as it's already"
12057 "DCBx is disabled according to strict"
12058 " priority setting.");
12061 memset(&ets_data, 0, sizeof(ets_data));
12062 ets_data.tc_valid_bits = veb->enabled_tc;
12063 ets_data.seepage = I40E_AQ_ETS_SEEPAGE_EN_MASK;
12064 ets_data.tc_strict_priority_flags = tc_map;
12065 /* Get all TCs' bandwidth. */
12066 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12067 if (veb->enabled_tc & BIT_ULL(i)) {
12068 /* For rubust, if bandwidth is 0, use 1 instead. */
12069 if (veb->bw_info.bw_ets_share_credits[i])
12070 ets_data.tc_bw_share_credits[i] =
12071 veb->bw_info.bw_ets_share_credits[i];
12073 ets_data.tc_bw_share_credits[i] =
12074 I40E_QOS_BW_WEIGHT_MIN;
12078 if (!veb->strict_prio_tc)
12079 ret = i40e_aq_config_switch_comp_ets(
12080 hw, veb->uplink_seid,
12081 &ets_data, i40e_aqc_opc_enable_switching_comp_ets,
12084 ret = i40e_aq_config_switch_comp_ets(
12085 hw, veb->uplink_seid,
12086 &ets_data, i40e_aqc_opc_modify_switching_comp_ets,
12089 ret = i40e_aq_config_switch_comp_ets(
12090 hw, veb->uplink_seid,
12091 &ets_data, i40e_aqc_opc_disable_switching_comp_ets,
12096 "Failed to set TCs' strict priority mode."
12101 veb->strict_prio_tc = tc_map;
12103 /* Enable DCBx again, if all the TCs' strict priority disabled. */
12105 ret = i40e_aq_start_lldp(hw, NULL);
12108 "Failed to enable DCBx, err(%d).", ret);
12113 "DCBx is enabled again according to strict"
12114 " priority setting.");
12120 #define I40E_PROFILE_INFO_SIZE 48
12121 #define I40E_MAX_PROFILE_NUM 16
12124 i40e_generate_profile_info_sec(char *name, struct i40e_ddp_version *version,
12125 uint32_t track_id, uint8_t *profile_info_sec,
12128 struct i40e_profile_section_header *sec = NULL;
12129 struct i40e_profile_info *pinfo;
12131 sec = (struct i40e_profile_section_header *)profile_info_sec;
12133 sec->data_end = sizeof(struct i40e_profile_section_header) +
12134 sizeof(struct i40e_profile_info);
12135 sec->section.type = SECTION_TYPE_INFO;
12136 sec->section.offset = sizeof(struct i40e_profile_section_header);
12137 sec->section.size = sizeof(struct i40e_profile_info);
12138 pinfo = (struct i40e_profile_info *)(profile_info_sec +
12139 sec->section.offset);
12140 pinfo->track_id = track_id;
12141 memcpy(pinfo->name, name, I40E_DDP_NAME_SIZE);
12142 memcpy(&pinfo->version, version, sizeof(struct i40e_ddp_version));
12144 pinfo->op = I40E_DDP_ADD_TRACKID;
12146 pinfo->op = I40E_DDP_REMOVE_TRACKID;
12149 static enum i40e_status_code
12150 i40e_add_rm_profile_info(struct i40e_hw *hw, uint8_t *profile_info_sec)
12152 enum i40e_status_code status = I40E_SUCCESS;
12153 struct i40e_profile_section_header *sec;
12155 uint32_t offset = 0;
12158 sec = (struct i40e_profile_section_header *)profile_info_sec;
12159 track_id = ((struct i40e_profile_info *)(profile_info_sec +
12160 sec->section.offset))->track_id;
12162 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
12163 track_id, &offset, &info, NULL);
12165 PMD_DRV_LOG(ERR, "Failed to add/remove profile info: "
12166 "offset %d, info %d",
12172 #define I40E_PROFILE_INFO_SIZE 48
12173 #define I40E_MAX_PROFILE_NUM 16
12175 /* Check if the profile info exists */
12177 i40e_check_profile_info(uint8_t port, uint8_t *profile_info_sec)
12179 struct rte_eth_dev *dev = &rte_eth_devices[port];
12180 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12182 struct rte_pmd_i40e_profile_list *p_list;
12183 struct rte_pmd_i40e_profile_info *pinfo, *p;
12187 buff = rte_zmalloc("pinfo_list",
12188 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12191 PMD_DRV_LOG(ERR, "failed to allocate memory");
12195 ret = i40e_aq_get_ddp_list(hw, (void *)buff,
12196 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4),
12199 PMD_DRV_LOG(ERR, "Failed to get profile info list.");
12203 p_list = (struct rte_pmd_i40e_profile_list *)buff;
12204 pinfo = (struct rte_pmd_i40e_profile_info *)(profile_info_sec +
12205 sizeof(struct i40e_profile_section_header));
12206 for (i = 0; i < p_list->p_count; i++) {
12207 p = &p_list->p_info[i];
12208 if ((pinfo->track_id == p->track_id) &&
12209 !memcmp(&pinfo->version, &p->version,
12210 sizeof(struct i40e_ddp_version)) &&
12211 !memcmp(&pinfo->name, &p->name,
12212 I40E_DDP_NAME_SIZE)) {
12213 PMD_DRV_LOG(INFO, "Profile exists.");
12224 rte_pmd_i40e_process_ddp_package(uint8_t port, uint8_t *buff,
12226 enum rte_pmd_i40e_package_op op)
12228 struct rte_eth_dev *dev;
12229 struct i40e_hw *hw;
12230 struct i40e_package_header *pkg_hdr;
12231 struct i40e_generic_seg_header *profile_seg_hdr;
12232 struct i40e_generic_seg_header *metadata_seg_hdr;
12234 uint8_t *profile_info_sec;
12236 enum i40e_status_code status = I40E_SUCCESS;
12238 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12240 dev = &rte_eth_devices[port];
12242 if (!is_device_supported(dev, &rte_i40e_pmd))
12245 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12247 if (size < (sizeof(struct i40e_package_header) +
12248 sizeof(struct i40e_metadata_segment) +
12249 sizeof(uint32_t) * 2)) {
12250 PMD_DRV_LOG(ERR, "Buff is invalid.");
12254 pkg_hdr = (struct i40e_package_header *)buff;
12257 PMD_DRV_LOG(ERR, "Failed to fill the package structure");
12261 if (pkg_hdr->segment_count < 2) {
12262 PMD_DRV_LOG(ERR, "Segment_count should be 2 at least.");
12266 /* Find metadata segment */
12267 metadata_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_METADATA,
12269 if (!metadata_seg_hdr) {
12270 PMD_DRV_LOG(ERR, "Failed to find metadata segment header");
12273 track_id = ((struct i40e_metadata_segment *)metadata_seg_hdr)->track_id;
12275 /* Find profile segment */
12276 profile_seg_hdr = i40e_find_segment_in_package(SEGMENT_TYPE_I40E,
12278 if (!profile_seg_hdr) {
12279 PMD_DRV_LOG(ERR, "Failed to find profile segment header");
12283 profile_info_sec = rte_zmalloc("i40e_profile_info",
12284 sizeof(struct i40e_profile_section_header) +
12285 sizeof(struct i40e_profile_info),
12287 if (!profile_info_sec) {
12288 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12292 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12293 /* Check if the profile exists */
12294 i40e_generate_profile_info_sec(
12295 ((struct i40e_profile_segment *)profile_seg_hdr)->name,
12296 &((struct i40e_profile_segment *)profile_seg_hdr)->version,
12297 track_id, profile_info_sec, 1);
12298 is_exist = i40e_check_profile_info(port, profile_info_sec);
12299 if (is_exist > 0) {
12300 PMD_DRV_LOG(ERR, "Profile already exists.");
12301 rte_free(profile_info_sec);
12303 } else if (is_exist < 0) {
12304 PMD_DRV_LOG(ERR, "Failed to check profile.");
12305 rte_free(profile_info_sec);
12309 /* Write profile to HW */
12310 status = i40e_write_profile(hw,
12311 (struct i40e_profile_segment *)profile_seg_hdr,
12314 PMD_DRV_LOG(ERR, "Failed to write profile.");
12315 rte_free(profile_info_sec);
12319 /* Add profile info to info list */
12320 status = i40e_add_rm_profile_info(hw, profile_info_sec);
12322 PMD_DRV_LOG(ERR, "Failed to add profile info.");
12324 PMD_DRV_LOG(ERR, "Operation not supported.");
12326 rte_free(profile_info_sec);
12331 rte_pmd_i40e_get_ddp_list(uint8_t port, uint8_t *buff, uint32_t size)
12333 struct rte_eth_dev *dev;
12334 struct i40e_hw *hw;
12335 enum i40e_status_code status = I40E_SUCCESS;
12337 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
12339 dev = &rte_eth_devices[port];
12341 if (!is_device_supported(dev, &rte_i40e_pmd))
12344 if (size < (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4))
12347 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12349 status = i40e_aq_get_ddp_list(hw, (void *)buff,
12355 /* Create a QinQ cloud filter
12357 * The Fortville NIC has limited resources for tunnel filters,
12358 * so we can only reuse existing filters.
12360 * In step 1 we define which Field Vector fields can be used for
12362 * As we do not have the inner tag defined as a field,
12363 * we have to define it first, by reusing one of L1 entries.
12365 * In step 2 we are replacing one of existing filter types with
12366 * a new one for QinQ.
12367 * As we reusing L1 and replacing L2, some of the default filter
12368 * types will disappear,which depends on L1 and L2 entries we reuse.
12370 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12372 * 1. Create L1 filter of outer vlan (12b) which will be in use
12373 * later when we define the cloud filter.
12374 * a. Valid_flags.replace_cloud = 0
12375 * b. Old_filter = 10 (Stag_Inner_Vlan)
12376 * c. New_filter = 0x10
12377 * d. TR bit = 0xff (optional, not used here)
12378 * e. Buffer – 2 entries:
12379 * i. Byte 0 = 8 (outer vlan FV index).
12381 * Byte 2-3 = 0x0fff
12382 * ii. Byte 0 = 37 (inner vlan FV index).
12384 * Byte 2-3 = 0x0fff
12387 * 2. Create cloud filter using two L1 filters entries: stag and
12388 * new filter(outer vlan+ inner vlan)
12389 * a. Valid_flags.replace_cloud = 1
12390 * b. Old_filter = 1 (instead of outer IP)
12391 * c. New_filter = 0x10
12392 * d. Buffer – 2 entries:
12393 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12394 * Byte 1-3 = 0 (rsv)
12395 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12396 * Byte 9-11 = 0 (rsv)
12399 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12401 int ret = -ENOTSUP;
12402 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12403 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12404 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12407 memset(&filter_replace, 0,
12408 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12409 memset(&filter_replace_buf, 0,
12410 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12412 /* create L1 filter */
12413 filter_replace.old_filter_type =
12414 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12415 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12416 filter_replace.tr_bit = 0;
12418 /* Prepare the buffer, 2 entries */
12419 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12420 filter_replace_buf.data[0] |=
12421 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12422 /* Field Vector 12b mask */
12423 filter_replace_buf.data[2] = 0xff;
12424 filter_replace_buf.data[3] = 0x0f;
12425 filter_replace_buf.data[4] =
12426 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12427 filter_replace_buf.data[4] |=
12428 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12429 /* Field Vector 12b mask */
12430 filter_replace_buf.data[6] = 0xff;
12431 filter_replace_buf.data[7] = 0x0f;
12432 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12433 &filter_replace_buf);
12434 if (ret != I40E_SUCCESS)
12437 /* Apply the second L2 cloud filter */
12438 memset(&filter_replace, 0,
12439 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12440 memset(&filter_replace_buf, 0,
12441 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12443 /* create L2 filter, input for L2 filter will be L1 filter */
12444 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12445 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12446 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12448 /* Prepare the buffer, 2 entries */
12449 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12450 filter_replace_buf.data[0] |=
12451 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12452 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
12453 filter_replace_buf.data[4] |=
12454 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12455 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12456 &filter_replace_buf);
12460 RTE_INIT(i40e_init_log);
12462 i40e_init_log(void)
12464 i40e_logtype_init = rte_log_register("pmd.i40e.init");
12465 if (i40e_logtype_init >= 0)
12466 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12467 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
12468 if (i40e_logtype_driver >= 0)
12469 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);