drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 415 static void i40e_configure_registers(struct i40e_hw *hw);
 416 static void i40e_hw_init(struct rte_eth_dev *dev);
 417 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 418 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 419                         struct rte_eth_mirror_conf *mirror_conf,
 420                         uint8_t sw_id, uint8_t on);
 421 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 422
 423 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 425 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 426                                            struct timespec *timestamp,
 427                                            uint32_t flags);
 428 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 429                                            struct timespec *timestamp);
 430 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 431
 432 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 433
 434 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 435                                    struct timespec *timestamp);
 436 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 437                                     const struct timespec *timestamp);
 438
 439 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 440                                          uint16_t queue_id);
 441 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 442                                           uint16_t queue_id);
 443
 444 static int i40e_get_regs(struct rte_eth_dev *dev,
 445                          struct rte_dev_reg_info *regs);
 446
 447 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 448
 449 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 450                            struct rte_dev_eeprom_info *eeprom);
 451
 452 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 453                                       struct ether_addr *mac_addr);
 454
 455 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 456
 457 static const struct rte_pci_id pci_id_i40e_map[] = {
 458         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 459         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 460         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 461         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 462         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 463         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 464         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct eth_dev_ops i40e_eth_dev_ops = {
 482         .dev_configure                = i40e_dev_configure,
 483         .dev_start                    = i40e_dev_start,
 484         .dev_stop                     = i40e_dev_stop,
 485         .dev_close                    = i40e_dev_close,
 486         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 487         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 488         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 489         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 490         .dev_set_link_up              = i40e_dev_set_link_up,
 491         .dev_set_link_down            = i40e_dev_set_link_down,
 492         .link_update                  = i40e_dev_link_update,
 493         .stats_get                    = i40e_dev_stats_get,
 494         .xstats_get                   = i40e_dev_xstats_get,
 495         .xstats_get_names             = i40e_dev_xstats_get_names,
 496         .stats_reset                  = i40e_dev_stats_reset,
 497         .xstats_reset                 = i40e_dev_stats_reset,
 498         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 499         .dev_infos_get                = i40e_dev_info_get,
 500         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 501         .vlan_filter_set              = i40e_vlan_filter_set,
 502         .vlan_tpid_set                = i40e_vlan_tpid_set,
 503         .vlan_offload_set             = i40e_vlan_offload_set,
 504         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 505         .vlan_pvid_set                = i40e_vlan_pvid_set,
 506         .rx_queue_start               = i40e_dev_rx_queue_start,
 507         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 508         .tx_queue_start               = i40e_dev_tx_queue_start,
 509         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 510         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 511         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 512         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 513         .rx_queue_release             = i40e_dev_rx_queue_release,
 514         .rx_queue_count               = i40e_dev_rx_queue_count,
 515         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 516         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 517         .tx_queue_release             = i40e_dev_tx_queue_release,
 518         .dev_led_on                   = i40e_dev_led_on,
 519         .dev_led_off                  = i40e_dev_led_off,
 520         .flow_ctrl_get                = i40e_flow_ctrl_get,
 521         .flow_ctrl_set                = i40e_flow_ctrl_set,
 522         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 523         .mac_addr_add                 = i40e_macaddr_add,
 524         .mac_addr_remove              = i40e_macaddr_remove,
 525         .reta_update                  = i40e_dev_rss_reta_update,
 526         .reta_query                   = i40e_dev_rss_reta_query,
 527         .rss_hash_update              = i40e_dev_rss_hash_update,
 528         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 529         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 530         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 531         .filter_ctrl                  = i40e_dev_filter_ctrl,
 532         .rxq_info_get                 = i40e_rxq_info_get,
 533         .txq_info_get                 = i40e_txq_info_get,
 534         .mirror_rule_set              = i40e_mirror_rule_set,
 535         .mirror_rule_reset            = i40e_mirror_rule_reset,
 536         .timesync_enable              = i40e_timesync_enable,
 537         .timesync_disable             = i40e_timesync_disable,
 538         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 539         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 540         .get_dcb_info                 = i40e_dev_get_dcb_info,
 541         .timesync_adjust_time         = i40e_timesync_adjust_time,
 542         .timesync_read_time           = i40e_timesync_read_time,
 543         .timesync_write_time          = i40e_timesync_write_time,
 544         .get_reg                      = i40e_get_regs,
 545         .get_eeprom_length            = i40e_get_eeprom_length,
 546         .get_eeprom                   = i40e_get_eeprom,
 547         .mac_addr_set                 = i40e_set_default_mac_addr,
 548         .mtu_set                      = i40e_dev_mtu_set,
 549 };
 550
 551 /* store statistics names and its offset in stats structure */
 552 struct rte_i40e_xstats_name_off {
 553         char name[RTE_ETH_XSTATS_NAME_SIZE];
 554         unsigned offset;
 555 };
 556
 557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 558         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 559         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 560         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 561         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 562         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 563                 rx_unknown_protocol)},
 564         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 565         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 566         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 567         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 568 };
 569
 570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 571                 sizeof(rte_i40e_stats_strings[0]))
 572
 573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 574         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 575                 tx_dropped_link_down)},
 576         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 577         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 578                 illegal_bytes)},
 579         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 580         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 581                 mac_local_faults)},
 582         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 583                 mac_remote_faults)},
 584         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_length_errors)},
 586         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 587         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 588         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 589         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 590         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 591         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 592                 rx_size_127)},
 593         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 594                 rx_size_255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 596                 rx_size_511)},
 597         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 598                 rx_size_1023)},
 599         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 600                 rx_size_1522)},
 601         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 602                 rx_size_big)},
 603         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 604                 rx_undersize)},
 605         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 606                 rx_oversize)},
 607         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 608                 mac_short_packet_dropped)},
 609         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 610                 rx_fragments)},
 611         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 612         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 614                 tx_size_127)},
 615         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 616                 tx_size_255)},
 617         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 618                 tx_size_511)},
 619         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 620                 tx_size_1023)},
 621         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 622                 tx_size_1522)},
 623         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 624                 tx_size_big)},
 625         {"rx_flow_director_atr_match_packets",
 626                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 627         {"rx_flow_director_sb_match_packets",
 628                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 629         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 630                 tx_lpi_status)},
 631         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 632                 rx_lpi_status)},
 633         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 634                 tx_lpi_count)},
 635         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 636                 rx_lpi_count)},
 637 };
 638
 639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 640                 sizeof(rte_i40e_hw_port_strings[0]))
 641
 642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 643         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 644                 priority_xon_rx)},
 645         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 646                 priority_xoff_rx)},
 647 };
 648
 649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 650                 sizeof(rte_i40e_rxq_prio_strings[0]))
 651
 652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 653         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 654                 priority_xon_tx)},
 655         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 656                 priority_xoff_tx)},
 657         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_2_xoff)},
 659 };
 660
 661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 662                 sizeof(rte_i40e_txq_prio_strings[0]))
 663
 664 static struct eth_driver rte_i40e_pmd = {
 665         .pci_drv = {
 666                 .id_table = pci_id_i40e_map,
 667                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 668                         RTE_PCI_DRV_DETACHABLE,
 669                 .probe = rte_eth_dev_pci_probe,
 670                 .remove = rte_eth_dev_pci_remove,
 671         },
 672         .eth_dev_init = eth_i40e_dev_init,
 673         .eth_dev_uninit = eth_i40e_dev_uninit,
 674         .dev_private_size = sizeof(struct i40e_adapter),
 675 };
 676
 677 static inline int
 678 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 679                                      struct rte_eth_link *link)
 680 {
 681         struct rte_eth_link *dst = link;
 682         struct rte_eth_link *src = &(dev->data->dev_link);
 683
 684         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 685                                         *(uint64_t *)src) == 0)
 686                 return -1;
 687
 688         return 0;
 689 }
 690
 691 static inline int
 692 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 693                                       struct rte_eth_link *link)
 694 {
 695         struct rte_eth_link *dst = &(dev->data->dev_link);
 696         struct rte_eth_link *src = link;
 697
 698         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 699                                         *(uint64_t *)src) == 0)
 700                 return -1;
 701
 702         return 0;
 703 }
 704
 705 DRIVER_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 706 DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 707
 708 #ifndef I40E_GLQF_ORT
 709 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 710 #endif
 711 #ifndef I40E_GLQF_PIT
 712 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 713 #endif
 714
 715 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 716 {
 717         /*
 718          * Initialize registers for flexible payload, which should be set by NVM.
 719          * This should be removed from code once it is fixed in NVM.
 720          */
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 731         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 732         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 733
 734         /* Initialize registers for parsing packet type of QinQ */
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 736         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 737 }
 738
 739 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 740
 741 /*
 742  * Add a ethertype filter to drop all flow control frames transmitted
 743  * from VSIs.
 744 */
 745 static void
 746 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 747 {
 748         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 749         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 750                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 751                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 752         int ret;
 753
 754         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 755                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 756                                 pf->main_vsi_seid, 0,
 757                                 TRUE, NULL, NULL);
 758         if (ret)
 759                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 760                                   " frames from VSIs.");
 761 }
 762
 763 static int
 764 floating_veb_list_handler(__rte_unused const char *key,
 765                           const char *floating_veb_value,
 766                           void *opaque)
 767 {
 768         int idx = 0;
 769         unsigned int count = 0;
 770         char *end = NULL;
 771         int min, max;
 772         bool *vf_floating_veb = opaque;
 773
 774         while (isblank(*floating_veb_value))
 775                 floating_veb_value++;
 776
 777         /* Reset floating VEB configuration for VFs */
 778         for (idx = 0; idx < I40E_MAX_VF; idx++)
 779                 vf_floating_veb[idx] = false;
 780
 781         min = I40E_MAX_VF;
 782         do {
 783                 while (isblank(*floating_veb_value))
 784                         floating_veb_value++;
 785                 if (*floating_veb_value == '\0')
 786                         return -1;
 787                 errno = 0;
 788                 idx = strtoul(floating_veb_value, &end, 10);
 789                 if (errno || end == NULL)
 790                         return -1;
 791                 while (isblank(*end))
 792                         end++;
 793                 if (*end == '-') {
 794                         min = idx;
 795                 } else if ((*end == ';') || (*end == '\0')) {
 796                         max = idx;
 797                         if (min == I40E_MAX_VF)
 798                                 min = idx;
 799                         if (max >= I40E_MAX_VF)
 800                                 max = I40E_MAX_VF - 1;
 801                         for (idx = min; idx <= max; idx++) {
 802                                 vf_floating_veb[idx] = true;
 803                                 count++;
 804                         }
 805                         min = I40E_MAX_VF;
 806                 } else {
 807                         return -1;
 808                 }
 809                 floating_veb_value = end + 1;
 810         } while (*end != '\0');
 811
 812         if (count == 0)
 813                 return -1;
 814
 815         return 0;
 816 }
 817
 818 static void
 819 config_vf_floating_veb(struct rte_devargs *devargs,
 820                        uint16_t floating_veb,
 821                        bool *vf_floating_veb)
 822 {
 823         struct rte_kvargs *kvlist;
 824         int i;
 825         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 826
 827         if (!floating_veb)
 828                 return;
 829         /* All the VFs attach to the floating VEB by default
 830          * when the floating VEB is enabled.
 831          */
 832         for (i = 0; i < I40E_MAX_VF; i++)
 833                 vf_floating_veb[i] = true;
 834
 835         if (devargs == NULL)
 836                 return;
 837
 838         kvlist = rte_kvargs_parse(devargs->args, NULL);
 839         if (kvlist == NULL)
 840                 return;
 841
 842         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 843                 rte_kvargs_free(kvlist);
 844                 return;
 845         }
 846         /* When the floating_veb_list parameter exists, all the VFs
 847          * will attach to the legacy VEB firstly, then configure VFs
 848          * to the floating VEB according to the floating_veb_list.
 849          */
 850         if (rte_kvargs_process(kvlist, floating_veb_list,
 851                                floating_veb_list_handler,
 852                                vf_floating_veb) < 0) {
 853                 rte_kvargs_free(kvlist);
 854                 return;
 855         }
 856         rte_kvargs_free(kvlist);
 857 }
 858
 859 static int
 860 i40e_check_floating_handler(__rte_unused const char *key,
 861                             const char *value,
 862                             __rte_unused void *opaque)
 863 {
 864         if (strcmp(value, "1"))
 865                 return -1;
 866
 867         return 0;
 868 }
 869
 870 static int
 871 is_floating_veb_supported(struct rte_devargs *devargs)
 872 {
 873         struct rte_kvargs *kvlist;
 874         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 875
 876         if (devargs == NULL)
 877                 return 0;
 878
 879         kvlist = rte_kvargs_parse(devargs->args, NULL);
 880         if (kvlist == NULL)
 881                 return 0;
 882
 883         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 884                 rte_kvargs_free(kvlist);
 885                 return 0;
 886         }
 887         /* Floating VEB is enabled when there's key-value:
 888          * enable_floating_veb=1
 889          */
 890         if (rte_kvargs_process(kvlist, floating_veb_key,
 891                                i40e_check_floating_handler, NULL) < 0) {
 892                 rte_kvargs_free(kvlist);
 893                 return 0;
 894         }
 895         rte_kvargs_free(kvlist);
 896
 897         return 1;
 898 }
 899
 900 static void
 901 config_floating_veb(struct rte_eth_dev *dev)
 902 {
 903         struct rte_pci_device *pci_dev = dev->pci_dev;
 904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 906
 907         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 908
 909         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 910                 pf->floating_veb =
 911                         is_floating_veb_supported(pci_dev->device.devargs);
 912                 config_vf_floating_veb(pci_dev->device.devargs,
 913                                        pf->floating_veb,
 914                                        pf->floating_veb_list);
 915         } else {
 916                 pf->floating_veb = false;
 917         }
 918 }
 919
 920 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 921 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 922
 923 static int
 924 eth_i40e_dev_init(struct rte_eth_dev *dev)
 925 {
 926         struct rte_pci_device *pci_dev;
 927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 929         struct i40e_vsi *vsi;
 930         int ret;
 931         uint32_t len;
 932         uint8_t aq_fail = 0;
 933
 934         PMD_INIT_FUNC_TRACE();
 935
 936         dev->dev_ops = &i40e_eth_dev_ops;
 937         dev->rx_pkt_burst = i40e_recv_pkts;
 938         dev->tx_pkt_burst = i40e_xmit_pkts;
 939
 940         /* for secondary processes, we don't initialise any further as primary
 941          * has already done this work. Only check we don't need a different
 942          * RX function */
 943         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 944                 i40e_set_rx_function(dev);
 945                 i40e_set_tx_function(dev);
 946                 return 0;
 947         }
 948         pci_dev = dev->pci_dev;
 949
 950         rte_eth_copy_pci_info(dev, pci_dev);
 951
 952         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 953         pf->adapter->eth_dev = dev;
 954         pf->dev_data = dev->data;
 955
 956         hw->back = I40E_PF_TO_ADAPTER(pf);
 957         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 958         if (!hw->hw_addr) {
 959                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 960                              "as address is NULL");
 961                 return -ENODEV;
 962         }
 963
 964         hw->vendor_id = pci_dev->id.vendor_id;
 965         hw->device_id = pci_dev->id.device_id;
 966         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 967         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 968         hw->bus.device = pci_dev->addr.devid;
 969         hw->bus.func = pci_dev->addr.function;
 970         hw->adapter_stopped = 0;
 971
 972         /* Make sure all is clean before doing PF reset */
 973         i40e_clear_hw(hw);
 974
 975         /* Initialize the hardware */
 976         i40e_hw_init(dev);
 977
 978         /* Reset here to make sure all is clean for each PF */
 979         ret = i40e_pf_reset(hw);
 980         if (ret) {
 981                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 982                 return ret;
 983         }
 984
 985         /* Initialize the shared code (base driver) */
 986         ret = i40e_init_shared_code(hw);
 987         if (ret) {
 988                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 989                 return ret;
 990         }
 991
 992         /*
 993          * To work around the NVM issue, initialize registers
 994          * for flexible payload and packet type of QinQ by
 995          * software. It should be removed once issues are fixed
 996          * in NVM.
 997          */
 998         i40e_GLQF_reg_init(hw);
 999
1000         /* Initialize the input set for filters (hash and fd) to default value */
1001         i40e_filter_input_set_init(pf);
1002
1003         /* Initialize the parameters for adminq */
1004         i40e_init_adminq_parameter(hw);
1005         ret = i40e_init_adminq(hw);
1006         if (ret != I40E_SUCCESS) {
1007                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1008                 return -EIO;
1009         }
1010         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1011                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1012                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1013                      ((hw->nvm.version >> 12) & 0xf),
1014                      ((hw->nvm.version >> 4) & 0xff),
1015                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1016
1017         /* Need the special FW version to support floating VEB */
1018         config_floating_veb(dev);
1019         /* Clear PXE mode */
1020         i40e_clear_pxe_mode(hw);
1021         ret = i40e_dev_sync_phy_type(hw);
1022         if (ret) {
1023                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1024                 goto err_sync_phy_type;
1025         }
1026         /*
1027          * On X710, performance number is far from the expectation on recent
1028          * firmware versions. The fix for this issue may not be integrated in
1029          * the following firmware version. So the workaround in software driver
1030          * is needed. It needs to modify the initial values of 3 internal only
1031          * registers. Note that the workaround can be removed when it is fixed
1032          * in firmware in the future.
1033          */
1034         i40e_configure_registers(hw);
1035
1036         /* Get hw capabilities */
1037         ret = i40e_get_cap(hw);
1038         if (ret != I40E_SUCCESS) {
1039                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1040                 goto err_get_capabilities;
1041         }
1042
1043         /* Initialize parameters for PF */
1044         ret = i40e_pf_parameter_init(dev);
1045         if (ret != 0) {
1046                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1047                 goto err_parameter_init;
1048         }
1049
1050         /* Initialize the queue management */
1051         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1052         if (ret < 0) {
1053                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1054                 goto err_qp_pool_init;
1055         }
1056         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1057                                 hw->func_caps.num_msix_vectors - 1);
1058         if (ret < 0) {
1059                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1060                 goto err_msix_pool_init;
1061         }
1062
1063         /* Initialize lan hmc */
1064         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1065                                 hw->func_caps.num_rx_qp, 0, 0);
1066         if (ret != I40E_SUCCESS) {
1067                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1068                 goto err_init_lan_hmc;
1069         }
1070
1071         /* Configure lan hmc */
1072         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1073         if (ret != I40E_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1075                 goto err_configure_lan_hmc;
1076         }
1077
1078         /* Get and check the mac address */
1079         i40e_get_mac_addr(hw, hw->mac.addr);
1080         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1081                 PMD_INIT_LOG(ERR, "mac address is not valid");
1082                 ret = -EIO;
1083                 goto err_get_mac_addr;
1084         }
1085         /* Copy the permanent MAC address */
1086         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1087                         (struct ether_addr *) hw->mac.perm_addr);
1088
1089         /* Disable flow control */
1090         hw->fc.requested_mode = I40E_FC_NONE;
1091         i40e_set_fc(hw, &aq_fail, TRUE);
1092
1093         /* Set the global registers with default ether type value */
1094         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1095         if (ret != I40E_SUCCESS) {
1096                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1097                              "VLAN ether type");
1098                 goto err_setup_pf_switch;
1099         }
1100
1101         /* PF setup, which includes VSI setup */
1102         ret = i40e_pf_setup(pf);
1103         if (ret) {
1104                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1105                 goto err_setup_pf_switch;
1106         }
1107
1108         /* reset all stats of the device, including pf and main vsi */
1109         i40e_dev_stats_reset(dev);
1110
1111         vsi = pf->main_vsi;
1112
1113         /* Disable double vlan by default */
1114         i40e_vsi_config_double_vlan(vsi, FALSE);
1115
1116         /* Disable S-TAG identification by default */
1117         ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1118         if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1119                 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1120                 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1121         }
1122
1123         if (!vsi->max_macaddrs)
1124                 len = ETHER_ADDR_LEN;
1125         else
1126                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1127
1128         /* Should be after VSI initialized */
1129         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1130         if (!dev->data->mac_addrs) {
1131                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1132                                         "for storing mac address");
1133                 goto err_mac_alloc;
1134         }
1135         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1136                                         &dev->data->mac_addrs[0]);
1137
1138         /* initialize pf host driver to setup SRIOV resource if applicable */
1139         i40e_pf_host_init(dev);
1140
1141         /* register callback func to eal lib */
1142         rte_intr_callback_register(&(pci_dev->intr_handle),
1143                 i40e_dev_interrupt_handler, (void *)dev);
1144
1145         /* configure and enable device interrupt */
1146         i40e_pf_config_irq0(hw, TRUE);
1147         i40e_pf_enable_irq0(hw);
1148
1149         /* enable uio intr after callback register */
1150         rte_intr_enable(&(pci_dev->intr_handle));
1151         /*
1152          * Add an ethertype filter to drop all flow control frames transmitted
1153          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1154          * frames to wire.
1155          */
1156         i40e_add_tx_flow_control_drop_filter(pf);
1157
1158         /* Set the max frame size to 0x2600 by default,
1159          * in case other drivers changed the default value.
1160          */
1161         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1162
1163         /* initialize mirror rule list */
1164         TAILQ_INIT(&pf->mirror_list);
1165
1166         /* Init dcb to sw mode by default */
1167         ret = i40e_dcb_init_configure(dev, TRUE);
1168         if (ret != I40E_SUCCESS) {
1169                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1170                 pf->flags &= ~I40E_FLAG_DCB;
1171         }
1172
1173         return 0;
1174
1175 err_mac_alloc:
1176         i40e_vsi_release(pf->main_vsi);
1177 err_setup_pf_switch:
1178 err_get_mac_addr:
1179 err_configure_lan_hmc:
1180         (void)i40e_shutdown_lan_hmc(hw);
1181 err_init_lan_hmc:
1182         i40e_res_pool_destroy(&pf->msix_pool);
1183 err_msix_pool_init:
1184         i40e_res_pool_destroy(&pf->qp_pool);
1185 err_qp_pool_init:
1186 err_parameter_init:
1187 err_get_capabilities:
1188 err_sync_phy_type:
1189         (void)i40e_shutdown_adminq(hw);
1190
1191         return ret;
1192 }
1193
1194 static int
1195 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1196 {
1197         struct rte_pci_device *pci_dev;
1198         struct i40e_hw *hw;
1199         struct i40e_filter_control_settings settings;
1200         int ret;
1201         uint8_t aq_fail = 0;
1202
1203         PMD_INIT_FUNC_TRACE();
1204
1205         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1206                 return 0;
1207
1208         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1209         pci_dev = dev->pci_dev;
1210
1211         if (hw->adapter_stopped == 0)
1212                 i40e_dev_close(dev);
1213
1214         dev->dev_ops = NULL;
1215         dev->rx_pkt_burst = NULL;
1216         dev->tx_pkt_burst = NULL;
1217
1218         /* Disable LLDP */
1219         ret = i40e_aq_stop_lldp(hw, true, NULL);
1220         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1221                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1222
1223         /* Clear PXE mode */
1224         i40e_clear_pxe_mode(hw);
1225
1226         /* Unconfigure filter control */
1227         memset(&settings, 0, sizeof(settings));
1228         ret = i40e_set_filter_control(hw, &settings);
1229         if (ret)
1230                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1231                                         ret);
1232
1233         /* Disable flow control */
1234         hw->fc.requested_mode = I40E_FC_NONE;
1235         i40e_set_fc(hw, &aq_fail, TRUE);
1236
1237         /* uninitialize pf host driver */
1238         i40e_pf_host_uninit(dev);
1239
1240         rte_free(dev->data->mac_addrs);
1241         dev->data->mac_addrs = NULL;
1242
1243         /* disable uio intr before callback unregister */
1244         rte_intr_disable(&(pci_dev->intr_handle));
1245
1246         /* register callback func to eal lib */
1247         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1248                 i40e_dev_interrupt_handler, (void *)dev);
1249
1250         return 0;
1251 }
1252
1253 static int
1254 i40e_dev_configure(struct rte_eth_dev *dev)
1255 {
1256         struct i40e_adapter *ad =
1257                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1258         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1259         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1260         int i, ret;
1261
1262         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1263          * bulk allocation or vector Rx preconditions we will reset it.
1264          */
1265         ad->rx_bulk_alloc_allowed = true;
1266         ad->rx_vec_allowed = true;
1267         ad->tx_simple_allowed = true;
1268         ad->tx_vec_allowed = true;
1269
1270         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1271                 ret = i40e_fdir_setup(pf);
1272                 if (ret != I40E_SUCCESS) {
1273                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1274                         return -ENOTSUP;
1275                 }
1276                 ret = i40e_fdir_configure(dev);
1277                 if (ret < 0) {
1278                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1279                         goto err;
1280                 }
1281         } else
1282                 i40e_fdir_teardown(pf);
1283
1284         ret = i40e_dev_init_vlan(dev);
1285         if (ret < 0)
1286                 goto err;
1287
1288         /* VMDQ setup.
1289          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1290          *  RSS setting have different requirements.
1291          *  General PMD driver call sequence are NIC init, configure,
1292          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1293          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1294          *  applicable. So, VMDQ setting has to be done before
1295          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1296          *  For RSS setting, it will try to calculate actual configured RX queue
1297          *  number, which will be available after rx_queue_setup(). dev_start()
1298          *  function is good to place RSS setup.
1299          */
1300         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1301                 ret = i40e_vmdq_setup(dev);
1302                 if (ret)
1303                         goto err;
1304         }
1305
1306         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1307                 ret = i40e_dcb_setup(dev);
1308                 if (ret) {
1309                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1310                         goto err_dcb;
1311                 }
1312         }
1313
1314         return 0;
1315
1316 err_dcb:
1317         /* need to release vmdq resource if exists */
1318         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1319                 i40e_vsi_release(pf->vmdq[i].vsi);
1320                 pf->vmdq[i].vsi = NULL;
1321         }
1322         rte_free(pf->vmdq);
1323         pf->vmdq = NULL;
1324 err:
1325         /* need to release fdir resource if exists */
1326         i40e_fdir_teardown(pf);
1327         return ret;
1328 }
1329
1330 void
1331 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1332 {
1333         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1334         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1335         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1336         uint16_t msix_vect = vsi->msix_intr;
1337         uint16_t i;
1338
1339         for (i = 0; i < vsi->nb_qps; i++) {
1340                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1341                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1342                 rte_wmb();
1343         }
1344
1345         if (vsi->type != I40E_VSI_SRIOV) {
1346                 if (!rte_intr_allow_others(intr_handle)) {
1347                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1348                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1349                         I40E_WRITE_REG(hw,
1350                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1351                                        0);
1352                 } else {
1353                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1354                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1355                         I40E_WRITE_REG(hw,
1356                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1357                                                        msix_vect - 1), 0);
1358                 }
1359         } else {
1360                 uint32_t reg;
1361                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1362                         vsi->user_param + (msix_vect - 1);
1363
1364                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1365                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1366         }
1367         I40E_WRITE_FLUSH(hw);
1368 }
1369
1370 static void
1371 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1372                        int base_queue, int nb_queue)
1373 {
1374         int i;
1375         uint32_t val;
1376         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1377
1378         /* Bind all RX queues to allocated MSIX interrupt */
1379         for (i = 0; i < nb_queue; i++) {
1380                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1381                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1382                         ((base_queue + i + 1) <<
1383                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1384                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1385                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1386
1387                 if (i == nb_queue - 1)
1388                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1389                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1390         }
1391
1392         /* Write first RX queue to Link list register as the head element */
1393         if (vsi->type != I40E_VSI_SRIOV) {
1394                 uint16_t interval =
1395                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1396
1397                 if (msix_vect == I40E_MISC_VEC_ID) {
1398                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1399                                        (base_queue <<
1400                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1401                                        (0x0 <<
1402                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1403                         I40E_WRITE_REG(hw,
1404                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1405                                        interval);
1406                 } else {
1407                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1408                                        (base_queue <<
1409                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1410                                        (0x0 <<
1411                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1412                         I40E_WRITE_REG(hw,
1413                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1414                                                        msix_vect - 1),
1415                                        interval);
1416                 }
1417         } else {
1418                 uint32_t reg;
1419
1420                 if (msix_vect == I40E_MISC_VEC_ID) {
1421                         I40E_WRITE_REG(hw,
1422                                        I40E_VPINT_LNKLST0(vsi->user_param),
1423                                        (base_queue <<
1424                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1425                                        (0x0 <<
1426                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1427                 } else {
1428                         /* num_msix_vectors_vf needs to minus irq0 */
1429                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1430                                 vsi->user_param + (msix_vect - 1);
1431
1432                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1433                                        (base_queue <<
1434                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1435                                        (0x0 <<
1436                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1437                 }
1438         }
1439
1440         I40E_WRITE_FLUSH(hw);
1441 }
1442
1443 void
1444 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1445 {
1446         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1447         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1448         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1449         uint16_t msix_vect = vsi->msix_intr;
1450         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1451         uint16_t queue_idx = 0;
1452         int record = 0;
1453         uint32_t val;
1454         int i;
1455
1456         for (i = 0; i < vsi->nb_qps; i++) {
1457                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1458                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1459         }
1460
1461         /* INTENA flag is not auto-cleared for interrupt */
1462         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1463         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1464                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1465                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1466         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1467
1468         /* VF bind interrupt */
1469         if (vsi->type == I40E_VSI_SRIOV) {
1470                 __vsi_queues_bind_intr(vsi, msix_vect,
1471                                        vsi->base_queue, vsi->nb_qps);
1472                 return;
1473         }
1474
1475         /* PF & VMDq bind interrupt */
1476         if (rte_intr_dp_is_en(intr_handle)) {
1477                 if (vsi->type == I40E_VSI_MAIN) {
1478                         queue_idx = 0;
1479                         record = 1;
1480                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1481                         struct i40e_vsi *main_vsi =
1482                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1483                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1484                         record = 1;
1485                 }
1486         }
1487
1488         for (i = 0; i < vsi->nb_used_qps; i++) {
1489                 if (nb_msix <= 1) {
1490                         if (!rte_intr_allow_others(intr_handle))
1491                                 /* allow to share MISC_VEC_ID */
1492                                 msix_vect = I40E_MISC_VEC_ID;
1493
1494                         /* no enough msix_vect, map all to one */
1495                         __vsi_queues_bind_intr(vsi, msix_vect,
1496                                                vsi->base_queue + i,
1497                                                vsi->nb_used_qps - i);
1498                         for (; !!record && i < vsi->nb_used_qps; i++)
1499                                 intr_handle->intr_vec[queue_idx + i] =
1500                                         msix_vect;
1501                         break;
1502                 }
1503                 /* 1:1 queue/msix_vect mapping */
1504                 __vsi_queues_bind_intr(vsi, msix_vect,
1505                                        vsi->base_queue + i, 1);
1506                 if (!!record)
1507                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1508
1509                 msix_vect++;
1510                 nb_msix--;
1511         }
1512 }
1513
1514 static void
1515 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1516 {
1517         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1518         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1519         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1520         uint16_t interval = i40e_calc_itr_interval(\
1521                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1522         uint16_t msix_intr, i;
1523
1524         if (rte_intr_allow_others(intr_handle))
1525                 for (i = 0; i < vsi->nb_msix; i++) {
1526                         msix_intr = vsi->msix_intr + i;
1527                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1528                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1529                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1530                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1531                                 (interval <<
1532                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1533                 }
1534         else
1535                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1536                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1537                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1538                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1539                                (interval <<
1540                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1541
1542         I40E_WRITE_FLUSH(hw);
1543 }
1544
1545 static void
1546 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1547 {
1548         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1549         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1550         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1551         uint16_t msix_intr, i;
1552
1553         if (rte_intr_allow_others(intr_handle))
1554                 for (i = 0; i < vsi->nb_msix; i++) {
1555                         msix_intr = vsi->msix_intr + i;
1556                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1557                                        0);
1558                 }
1559         else
1560                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1561
1562         I40E_WRITE_FLUSH(hw);
1563 }
1564
1565 static inline uint8_t
1566 i40e_parse_link_speeds(uint16_t link_speeds)
1567 {
1568         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1569
1570         if (link_speeds & ETH_LINK_SPEED_40G)
1571                 link_speed |= I40E_LINK_SPEED_40GB;
1572         if (link_speeds & ETH_LINK_SPEED_25G)
1573                 link_speed |= I40E_LINK_SPEED_25GB;
1574         if (link_speeds & ETH_LINK_SPEED_20G)
1575                 link_speed |= I40E_LINK_SPEED_20GB;
1576         if (link_speeds & ETH_LINK_SPEED_10G)
1577                 link_speed |= I40E_LINK_SPEED_10GB;
1578         if (link_speeds & ETH_LINK_SPEED_1G)
1579                 link_speed |= I40E_LINK_SPEED_1GB;
1580         if (link_speeds & ETH_LINK_SPEED_100M)
1581                 link_speed |= I40E_LINK_SPEED_100MB;
1582
1583         return link_speed;
1584 }
1585
1586 static int
1587 i40e_phy_conf_link(struct i40e_hw *hw,
1588                    uint8_t abilities,
1589                    uint8_t force_speed)
1590 {
1591         enum i40e_status_code status;
1592         struct i40e_aq_get_phy_abilities_resp phy_ab;
1593         struct i40e_aq_set_phy_config phy_conf;
1594         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1595                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1596                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1597                         I40E_AQ_PHY_FLAG_LOW_POWER;
1598         const uint8_t advt = I40E_LINK_SPEED_40GB |
1599                         I40E_LINK_SPEED_25GB |
1600                         I40E_LINK_SPEED_10GB |
1601                         I40E_LINK_SPEED_1GB |
1602                         I40E_LINK_SPEED_100MB;
1603         int ret = -ENOTSUP;
1604
1605
1606         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1607                                               NULL);
1608         if (status)
1609                 return ret;
1610
1611         memset(&phy_conf, 0, sizeof(phy_conf));
1612
1613         /* bits 0-2 use the values from get_phy_abilities_resp */
1614         abilities &= ~mask;
1615         abilities |= phy_ab.abilities & mask;
1616
1617         /* update ablities and speed */
1618         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1619                 phy_conf.link_speed = advt;
1620         else
1621                 phy_conf.link_speed = force_speed;
1622
1623         phy_conf.abilities = abilities;
1624
1625         /* use get_phy_abilities_resp value for the rest */
1626         phy_conf.phy_type = phy_ab.phy_type;
1627         phy_conf.eee_capability = phy_ab.eee_capability;
1628         phy_conf.eeer = phy_ab.eeer_val;
1629         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1630
1631         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1632                     phy_ab.abilities, phy_ab.link_speed);
1633         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1634                     phy_conf.abilities, phy_conf.link_speed);
1635
1636         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1637         if (status)
1638                 return ret;
1639
1640         return I40E_SUCCESS;
1641 }
1642
1643 static int
1644 i40e_apply_link_speed(struct rte_eth_dev *dev)
1645 {
1646         uint8_t speed;
1647         uint8_t abilities = 0;
1648         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649         struct rte_eth_conf *conf = &dev->data->dev_conf;
1650
1651         speed = i40e_parse_link_speeds(conf->link_speeds);
1652         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1653                 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1654         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1655                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1656         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1657
1658         /* Skip changing speed on 40G interfaces, FW does not support */
1659         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1660                 speed =  I40E_LINK_SPEED_UNKNOWN;
1661                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1662         }
1663
1664         return i40e_phy_conf_link(hw, abilities, speed);
1665 }
1666
1667 static int
1668 i40e_dev_start(struct rte_eth_dev *dev)
1669 {
1670         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1671         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1672         struct i40e_vsi *main_vsi = pf->main_vsi;
1673         int ret, i;
1674         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1675         uint32_t intr_vector = 0;
1676
1677         hw->adapter_stopped = 0;
1678
1679         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1680                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1681                              dev->data->port_id);
1682                 return -EINVAL;
1683         }
1684
1685         rte_intr_disable(intr_handle);
1686
1687         if ((rte_intr_cap_multiple(intr_handle) ||
1688              !RTE_ETH_DEV_SRIOV(dev).active) &&
1689             dev->data->dev_conf.intr_conf.rxq != 0) {
1690                 intr_vector = dev->data->nb_rx_queues;
1691                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1692                         return -1;
1693         }
1694
1695         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1696                 intr_handle->intr_vec =
1697                         rte_zmalloc("intr_vec",
1698                                     dev->data->nb_rx_queues * sizeof(int),
1699                                     0);
1700                 if (!intr_handle->intr_vec) {
1701                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1702                                      " intr_vec\n", dev->data->nb_rx_queues);
1703                         return -ENOMEM;
1704                 }
1705         }
1706
1707         /* Initialize VSI */
1708         ret = i40e_dev_rxtx_init(pf);
1709         if (ret != I40E_SUCCESS) {
1710                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1711                 goto err_up;
1712         }
1713
1714         /* Map queues with MSIX interrupt */
1715         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1716                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1717         i40e_vsi_queues_bind_intr(main_vsi);
1718         i40e_vsi_enable_queues_intr(main_vsi);
1719
1720         /* Map VMDQ VSI queues with MSIX interrupt */
1721         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1722                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1723                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1724                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1725         }
1726
1727         /* enable FDIR MSIX interrupt */
1728         if (pf->fdir.fdir_vsi) {
1729                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1730                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1731         }
1732
1733         /* Enable all queues which have been configured */
1734         ret = i40e_dev_switch_queues(pf, TRUE);
1735         if (ret != I40E_SUCCESS) {
1736                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1737                 goto err_up;
1738         }
1739
1740         /* Enable receiving broadcast packets */
1741         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1742         if (ret != I40E_SUCCESS)
1743                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1744
1745         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1746                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1747                                                 true, NULL);
1748                 if (ret != I40E_SUCCESS)
1749                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1750         }
1751
1752         /* Apply link configure */
1753         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1754                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1755                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1756                                 ETH_LINK_SPEED_40G)) {
1757                 PMD_DRV_LOG(ERR, "Invalid link setting");
1758                 goto err_up;
1759         }
1760         ret = i40e_apply_link_speed(dev);
1761         if (I40E_SUCCESS != ret) {
1762                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1763                 goto err_up;
1764         }
1765
1766         if (!rte_intr_allow_others(intr_handle)) {
1767                 rte_intr_callback_unregister(intr_handle,
1768                                              i40e_dev_interrupt_handler,
1769                                              (void *)dev);
1770                 /* configure and enable device interrupt */
1771                 i40e_pf_config_irq0(hw, FALSE);
1772                 i40e_pf_enable_irq0(hw);
1773
1774                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1775                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1776                                      " no intr multiplex\n");
1777         }
1778
1779         /* enable uio intr after callback register */
1780         rte_intr_enable(intr_handle);
1781
1782         return I40E_SUCCESS;
1783
1784 err_up:
1785         i40e_dev_switch_queues(pf, FALSE);
1786         i40e_dev_clear_queues(dev);
1787
1788         return ret;
1789 }
1790
1791 static void
1792 i40e_dev_stop(struct rte_eth_dev *dev)
1793 {
1794         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1795         struct i40e_vsi *main_vsi = pf->main_vsi;
1796         struct i40e_mirror_rule *p_mirror;
1797         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1798         int i;
1799
1800         /* Disable all queues */
1801         i40e_dev_switch_queues(pf, FALSE);
1802
1803         /* un-map queues with interrupt registers */
1804         i40e_vsi_disable_queues_intr(main_vsi);
1805         i40e_vsi_queues_unbind_intr(main_vsi);
1806
1807         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1808                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1809                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1810         }
1811
1812         if (pf->fdir.fdir_vsi) {
1813                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1814                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1815         }
1816         /* Clear all queues and release memory */
1817         i40e_dev_clear_queues(dev);
1818
1819         /* Set link down */
1820         i40e_dev_set_link_down(dev);
1821
1822         /* Remove all mirror rules */
1823         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1824                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1825                 rte_free(p_mirror);
1826         }
1827         pf->nb_mirror_rule = 0;
1828
1829         if (!rte_intr_allow_others(intr_handle))
1830                 /* resume to the default handler */
1831                 rte_intr_callback_register(intr_handle,
1832                                            i40e_dev_interrupt_handler,
1833                                            (void *)dev);
1834
1835         /* Clean datapath event and queue/vec mapping */
1836         rte_intr_efd_disable(intr_handle);
1837         if (intr_handle->intr_vec) {
1838                 rte_free(intr_handle->intr_vec);
1839                 intr_handle->intr_vec = NULL;
1840         }
1841 }
1842
1843 static void
1844 i40e_dev_close(struct rte_eth_dev *dev)
1845 {
1846         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848         uint32_t reg;
1849         int i;
1850
1851         PMD_INIT_FUNC_TRACE();
1852
1853         i40e_dev_stop(dev);
1854         hw->adapter_stopped = 1;
1855         i40e_dev_free_queues(dev);
1856
1857         /* Disable interrupt */
1858         i40e_pf_disable_irq0(hw);
1859         rte_intr_disable(&(dev->pci_dev->intr_handle));
1860
1861         /* shutdown and destroy the HMC */
1862         i40e_shutdown_lan_hmc(hw);
1863
1864         /* release all the existing VSIs and VEBs */
1865         i40e_fdir_teardown(pf);
1866         i40e_vsi_release(pf->main_vsi);
1867
1868         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1869                 i40e_vsi_release(pf->vmdq[i].vsi);
1870                 pf->vmdq[i].vsi = NULL;
1871         }
1872
1873         rte_free(pf->vmdq);
1874         pf->vmdq = NULL;
1875
1876         /* shutdown the adminq */
1877         i40e_aq_queue_shutdown(hw, true);
1878         i40e_shutdown_adminq(hw);
1879
1880         i40e_res_pool_destroy(&pf->qp_pool);
1881         i40e_res_pool_destroy(&pf->msix_pool);
1882
1883         /* force a PF reset to clean anything leftover */
1884         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1885         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1886                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1887         I40E_WRITE_FLUSH(hw);
1888 }
1889
1890 static void
1891 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1892 {
1893         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1894         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1895         struct i40e_vsi *vsi = pf->main_vsi;
1896         int status;
1897
1898         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1899                                                      true, NULL, true);
1900         if (status != I40E_SUCCESS)
1901                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1902
1903         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1904                                                         TRUE, NULL);
1905         if (status != I40E_SUCCESS)
1906                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1907
1908 }
1909
1910 static void
1911 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1912 {
1913         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1914         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1915         struct i40e_vsi *vsi = pf->main_vsi;
1916         int status;
1917
1918         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1919                                                      false, NULL, true);
1920         if (status != I40E_SUCCESS)
1921                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1922
1923         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1924                                                         false, NULL);
1925         if (status != I40E_SUCCESS)
1926                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1927 }
1928
1929 static void
1930 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1931 {
1932         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1933         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934         struct i40e_vsi *vsi = pf->main_vsi;
1935         int ret;
1936
1937         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1938         if (ret != I40E_SUCCESS)
1939                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1940 }
1941
1942 static void
1943 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1944 {
1945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1946         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1947         struct i40e_vsi *vsi = pf->main_vsi;
1948         int ret;
1949
1950         if (dev->data->promiscuous == 1)
1951                 return; /* must remain in all_multicast mode */
1952
1953         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1954                                 vsi->seid, FALSE, NULL);
1955         if (ret != I40E_SUCCESS)
1956                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1957 }
1958
1959 /*
1960  * Set device link up.
1961  */
1962 static int
1963 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1964 {
1965         /* re-apply link speed setting */
1966         return i40e_apply_link_speed(dev);
1967 }
1968
1969 /*
1970  * Set device link down.
1971  */
1972 static int
1973 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1974 {
1975         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1976         uint8_t abilities = 0;
1977         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978
1979         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1980                 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1981         return i40e_phy_conf_link(hw, abilities, speed);
1982 }
1983
1984 int
1985 i40e_dev_link_update(struct rte_eth_dev *dev,
1986                      int wait_to_complete)
1987 {
1988 #define CHECK_INTERVAL 100  /* 100ms */
1989 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1990         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         struct i40e_link_status link_status;
1992         struct rte_eth_link link, old;
1993         int status;
1994         unsigned rep_cnt = MAX_REPEAT_TIME;
1995
1996         memset(&link, 0, sizeof(link));
1997         memset(&old, 0, sizeof(old));
1998         memset(&link_status, 0, sizeof(link_status));
1999         rte_i40e_dev_atomic_read_link_status(dev, &old);
2000
2001         do {
2002                 /* Get link status information from hardware */
2003                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
2004                 if (status != I40E_SUCCESS) {
2005                         link.link_speed = ETH_SPEED_NUM_100M;
2006                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2007                         PMD_DRV_LOG(ERR, "Failed to get link info");
2008                         goto out;
2009                 }
2010
2011                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2012                 if (!wait_to_complete)
2013                         break;
2014
2015                 rte_delay_ms(CHECK_INTERVAL);
2016         } while (!link.link_status && rep_cnt--);
2017
2018         if (!link.link_status)
2019                 goto out;
2020
2021         /* i40e uses full duplex only */
2022         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2023
2024         /* Parse the link status */
2025         switch (link_status.link_speed) {
2026         case I40E_LINK_SPEED_100MB:
2027                 link.link_speed = ETH_SPEED_NUM_100M;
2028                 break;
2029         case I40E_LINK_SPEED_1GB:
2030                 link.link_speed = ETH_SPEED_NUM_1G;
2031                 break;
2032         case I40E_LINK_SPEED_10GB:
2033                 link.link_speed = ETH_SPEED_NUM_10G;
2034                 break;
2035         case I40E_LINK_SPEED_20GB:
2036                 link.link_speed = ETH_SPEED_NUM_20G;
2037                 break;
2038         case I40E_LINK_SPEED_25GB:
2039                 link.link_speed = ETH_SPEED_NUM_25G;
2040                 break;
2041         case I40E_LINK_SPEED_40GB:
2042                 link.link_speed = ETH_SPEED_NUM_40G;
2043                 break;
2044         default:
2045                 link.link_speed = ETH_SPEED_NUM_100M;
2046                 break;
2047         }
2048
2049         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2050                         ETH_LINK_SPEED_FIXED);
2051
2052 out:
2053         rte_i40e_dev_atomic_write_link_status(dev, &link);
2054         if (link.link_status == old.link_status)
2055                 return -1;
2056
2057         return 0;
2058 }
2059
2060 /* Get all the statistics of a VSI */
2061 void
2062 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2063 {
2064         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2065         struct i40e_eth_stats *nes = &vsi->eth_stats;
2066         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2067         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2068
2069         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2070                             vsi->offset_loaded, &oes->rx_bytes,
2071                             &nes->rx_bytes);
2072         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2073                             vsi->offset_loaded, &oes->rx_unicast,
2074                             &nes->rx_unicast);
2075         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2076                             vsi->offset_loaded, &oes->rx_multicast,
2077                             &nes->rx_multicast);
2078         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2079                             vsi->offset_loaded, &oes->rx_broadcast,
2080                             &nes->rx_broadcast);
2081         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2082                             &oes->rx_discards, &nes->rx_discards);
2083         /* GLV_REPC not supported */
2084         /* GLV_RMPC not supported */
2085         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2086                             &oes->rx_unknown_protocol,
2087                             &nes->rx_unknown_protocol);
2088         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2089                             vsi->offset_loaded, &oes->tx_bytes,
2090                             &nes->tx_bytes);
2091         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2092                             vsi->offset_loaded, &oes->tx_unicast,
2093                             &nes->tx_unicast);
2094         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2095                             vsi->offset_loaded, &oes->tx_multicast,
2096                             &nes->tx_multicast);
2097         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2098                             vsi->offset_loaded,  &oes->tx_broadcast,
2099                             &nes->tx_broadcast);
2100         /* GLV_TDPC not supported */
2101         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2102                             &oes->tx_errors, &nes->tx_errors);
2103         vsi->offset_loaded = true;
2104
2105         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2106                     vsi->vsi_id);
2107         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2108         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2109         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2110         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2111         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2112         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2113                     nes->rx_unknown_protocol);
2114         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2115         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2116         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2117         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2118         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2119         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2120         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2121                     vsi->vsi_id);
2122 }
2123
2124 static void
2125 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2126 {
2127         unsigned int i;
2128         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2129         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2130
2131         /* Get statistics of struct i40e_eth_stats */
2132         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2133                             I40E_GLPRT_GORCL(hw->port),
2134                             pf->offset_loaded, &os->eth.rx_bytes,
2135                             &ns->eth.rx_bytes);
2136         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2137                             I40E_GLPRT_UPRCL(hw->port),
2138                             pf->offset_loaded, &os->eth.rx_unicast,
2139                             &ns->eth.rx_unicast);
2140         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2141                             I40E_GLPRT_MPRCL(hw->port),
2142                             pf->offset_loaded, &os->eth.rx_multicast,
2143                             &ns->eth.rx_multicast);
2144         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2145                             I40E_GLPRT_BPRCL(hw->port),
2146                             pf->offset_loaded, &os->eth.rx_broadcast,
2147                             &ns->eth.rx_broadcast);
2148         /* Workaround: CRC size should not be included in byte statistics,
2149          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2150          */
2151         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2152                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2153
2154         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2155                             pf->offset_loaded, &os->eth.rx_discards,
2156                             &ns->eth.rx_discards);
2157         /* GLPRT_REPC not supported */
2158         /* GLPRT_RMPC not supported */
2159         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2160                             pf->offset_loaded,
2161                             &os->eth.rx_unknown_protocol,
2162                             &ns->eth.rx_unknown_protocol);
2163         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2164                             I40E_GLPRT_GOTCL(hw->port),
2165                             pf->offset_loaded, &os->eth.tx_bytes,
2166                             &ns->eth.tx_bytes);
2167         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2168                             I40E_GLPRT_UPTCL(hw->port),
2169                             pf->offset_loaded, &os->eth.tx_unicast,
2170                             &ns->eth.tx_unicast);
2171         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2172                             I40E_GLPRT_MPTCL(hw->port),
2173                             pf->offset_loaded, &os->eth.tx_multicast,
2174                             &ns->eth.tx_multicast);
2175         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2176                             I40E_GLPRT_BPTCL(hw->port),
2177                             pf->offset_loaded, &os->eth.tx_broadcast,
2178                             &ns->eth.tx_broadcast);
2179         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2180                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2181         /* GLPRT_TEPC not supported */
2182
2183         /* additional port specific stats */
2184         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2185                             pf->offset_loaded, &os->tx_dropped_link_down,
2186                             &ns->tx_dropped_link_down);
2187         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2188                             pf->offset_loaded, &os->crc_errors,
2189                             &ns->crc_errors);
2190         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2191                             pf->offset_loaded, &os->illegal_bytes,
2192                             &ns->illegal_bytes);
2193         /* GLPRT_ERRBC not supported */
2194         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2195                             pf->offset_loaded, &os->mac_local_faults,
2196                             &ns->mac_local_faults);
2197         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2198                             pf->offset_loaded, &os->mac_remote_faults,
2199                             &ns->mac_remote_faults);
2200         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2201                             pf->offset_loaded, &os->rx_length_errors,
2202                             &ns->rx_length_errors);
2203         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2204                             pf->offset_loaded, &os->link_xon_rx,
2205                             &ns->link_xon_rx);
2206         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2207                             pf->offset_loaded, &os->link_xoff_rx,
2208                             &ns->link_xoff_rx);
2209         for (i = 0; i < 8; i++) {
2210                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2211                                     pf->offset_loaded,
2212                                     &os->priority_xon_rx[i],
2213                                     &ns->priority_xon_rx[i]);
2214                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2215                                     pf->offset_loaded,
2216                                     &os->priority_xoff_rx[i],
2217                                     &ns->priority_xoff_rx[i]);
2218         }
2219         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2220                             pf->offset_loaded, &os->link_xon_tx,
2221                             &ns->link_xon_tx);
2222         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2223                             pf->offset_loaded, &os->link_xoff_tx,
2224                             &ns->link_xoff_tx);
2225         for (i = 0; i < 8; i++) {
2226                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2227                                     pf->offset_loaded,
2228                                     &os->priority_xon_tx[i],
2229                                     &ns->priority_xon_tx[i]);
2230                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2231                                     pf->offset_loaded,
2232                                     &os->priority_xoff_tx[i],
2233                                     &ns->priority_xoff_tx[i]);
2234                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2235                                     pf->offset_loaded,
2236                                     &os->priority_xon_2_xoff[i],
2237                                     &ns->priority_xon_2_xoff[i]);
2238         }
2239         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2240                             I40E_GLPRT_PRC64L(hw->port),
2241                             pf->offset_loaded, &os->rx_size_64,
2242                             &ns->rx_size_64);
2243         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2244                             I40E_GLPRT_PRC127L(hw->port),
2245                             pf->offset_loaded, &os->rx_size_127,
2246                             &ns->rx_size_127);
2247         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2248                             I40E_GLPRT_PRC255L(hw->port),
2249                             pf->offset_loaded, &os->rx_size_255,
2250                             &ns->rx_size_255);
2251         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2252                             I40E_GLPRT_PRC511L(hw->port),
2253                             pf->offset_loaded, &os->rx_size_511,
2254                             &ns->rx_size_511);
2255         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2256                             I40E_GLPRT_PRC1023L(hw->port),
2257                             pf->offset_loaded, &os->rx_size_1023,
2258                             &ns->rx_size_1023);
2259         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2260                             I40E_GLPRT_PRC1522L(hw->port),
2261                             pf->offset_loaded, &os->rx_size_1522,
2262                             &ns->rx_size_1522);
2263         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2264                             I40E_GLPRT_PRC9522L(hw->port),
2265                             pf->offset_loaded, &os->rx_size_big,
2266                             &ns->rx_size_big);
2267         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2268                             pf->offset_loaded, &os->rx_undersize,
2269                             &ns->rx_undersize);
2270         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2271                             pf->offset_loaded, &os->rx_fragments,
2272                             &ns->rx_fragments);
2273         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2274                             pf->offset_loaded, &os->rx_oversize,
2275                             &ns->rx_oversize);
2276         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2277                             pf->offset_loaded, &os->rx_jabber,
2278                             &ns->rx_jabber);
2279         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2280                             I40E_GLPRT_PTC64L(hw->port),
2281                             pf->offset_loaded, &os->tx_size_64,
2282                             &ns->tx_size_64);
2283         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2284                             I40E_GLPRT_PTC127L(hw->port),
2285                             pf->offset_loaded, &os->tx_size_127,
2286                             &ns->tx_size_127);
2287         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2288                             I40E_GLPRT_PTC255L(hw->port),
2289                             pf->offset_loaded, &os->tx_size_255,
2290                             &ns->tx_size_255);
2291         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2292                             I40E_GLPRT_PTC511L(hw->port),
2293                             pf->offset_loaded, &os->tx_size_511,
2294                             &ns->tx_size_511);
2295         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2296                             I40E_GLPRT_PTC1023L(hw->port),
2297                             pf->offset_loaded, &os->tx_size_1023,
2298                             &ns->tx_size_1023);
2299         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2300                             I40E_GLPRT_PTC1522L(hw->port),
2301                             pf->offset_loaded, &os->tx_size_1522,
2302                             &ns->tx_size_1522);
2303         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2304                             I40E_GLPRT_PTC9522L(hw->port),
2305                             pf->offset_loaded, &os->tx_size_big,
2306                             &ns->tx_size_big);
2307         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2308                            pf->offset_loaded,
2309                            &os->fd_sb_match, &ns->fd_sb_match);
2310         /* GLPRT_MSPDC not supported */
2311         /* GLPRT_XEC not supported */
2312
2313         pf->offset_loaded = true;
2314
2315         if (pf->main_vsi)
2316                 i40e_update_vsi_stats(pf->main_vsi);
2317 }
2318
2319 /* Get all statistics of a port */
2320 static void
2321 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2322 {
2323         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2324         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2325         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2326         unsigned i;
2327
2328         /* call read registers - updates values, now write them to struct */
2329         i40e_read_stats_registers(pf, hw);
2330
2331         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2332                         pf->main_vsi->eth_stats.rx_multicast +
2333                         pf->main_vsi->eth_stats.rx_broadcast -
2334                         pf->main_vsi->eth_stats.rx_discards;
2335         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2336                         pf->main_vsi->eth_stats.tx_multicast +
2337                         pf->main_vsi->eth_stats.tx_broadcast;
2338         stats->ibytes   = ns->eth.rx_bytes;
2339         stats->obytes   = ns->eth.tx_bytes;
2340         stats->oerrors  = ns->eth.tx_errors +
2341                         pf->main_vsi->eth_stats.tx_errors;
2342
2343         /* Rx Errors */
2344         stats->imissed  = ns->eth.rx_discards +
2345                         pf->main_vsi->eth_stats.rx_discards;
2346         stats->ierrors  = ns->crc_errors +
2347                         ns->rx_length_errors + ns->rx_undersize +
2348                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2349
2350         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2351         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2352         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2353         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2354         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2355         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2356         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2357                     ns->eth.rx_unknown_protocol);
2358         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2359         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2360         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2361         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2362         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2363         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2364
2365         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2366                     ns->tx_dropped_link_down);
2367         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2368         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2369                     ns->illegal_bytes);
2370         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2371         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2372                     ns->mac_local_faults);
2373         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2374                     ns->mac_remote_faults);
2375         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2376                     ns->rx_length_errors);
2377         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2378         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2379         for (i = 0; i < 8; i++) {
2380                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2381                                 i, ns->priority_xon_rx[i]);
2382                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2383                                 i, ns->priority_xoff_rx[i]);
2384         }
2385         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2386         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2387         for (i = 0; i < 8; i++) {
2388                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2389                                 i, ns->priority_xon_tx[i]);
2390                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2391                                 i, ns->priority_xoff_tx[i]);
2392                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2393                                 i, ns->priority_xon_2_xoff[i]);
2394         }
2395         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2396         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2397         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2398         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2399         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2400         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2401         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2402         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2403         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2404         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2405         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2406         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2407         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2408         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2409         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2410         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2411         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2412         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2413         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2414                         ns->mac_short_packet_dropped);
2415         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2416                     ns->checksum_error);
2417         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2418         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2419 }
2420
2421 /* Reset the statistics */
2422 static void
2423 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2424 {
2425         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2426         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427
2428         /* Mark PF and VSI stats to update the offset, aka "reset" */
2429         pf->offset_loaded = false;
2430         if (pf->main_vsi)
2431                 pf->main_vsi->offset_loaded = false;
2432
2433         /* read the stats, reading current register values into offset */
2434         i40e_read_stats_registers(pf, hw);
2435 }
2436
2437 static uint32_t
2438 i40e_xstats_calc_num(void)
2439 {
2440         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2441                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2442                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2443 }
2444
2445 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2446                                      struct rte_eth_xstat_name *xstats_names,
2447                                      __rte_unused unsigned limit)
2448 {
2449         unsigned count = 0;
2450         unsigned i, prio;
2451
2452         if (xstats_names == NULL)
2453                 return i40e_xstats_calc_num();
2454
2455         /* Note: limit checked in rte_eth_xstats_names() */
2456
2457         /* Get stats from i40e_eth_stats struct */
2458         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2459                 snprintf(xstats_names[count].name,
2460                          sizeof(xstats_names[count].name),
2461                          "%s", rte_i40e_stats_strings[i].name);
2462                 count++;
2463         }
2464
2465         /* Get individiual stats from i40e_hw_port struct */
2466         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2467                 snprintf(xstats_names[count].name,
2468                         sizeof(xstats_names[count].name),
2469                          "%s", rte_i40e_hw_port_strings[i].name);
2470                 count++;
2471         }
2472
2473         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2474                 for (prio = 0; prio < 8; prio++) {
2475                         snprintf(xstats_names[count].name,
2476                                  sizeof(xstats_names[count].name),
2477                                  "rx_priority%u_%s", prio,
2478                                  rte_i40e_rxq_prio_strings[i].name);
2479                         count++;
2480                 }
2481         }
2482
2483         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2484                 for (prio = 0; prio < 8; prio++) {
2485                         snprintf(xstats_names[count].name,
2486                                  sizeof(xstats_names[count].name),
2487                                  "tx_priority%u_%s", prio,
2488                                  rte_i40e_txq_prio_strings[i].name);
2489                         count++;
2490                 }
2491         }
2492         return count;
2493 }
2494
2495 static int
2496 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2497                     unsigned n)
2498 {
2499         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2500         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2501         unsigned i, count, prio;
2502         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2503
2504         count = i40e_xstats_calc_num();
2505         if (n < count)
2506                 return count;
2507
2508         i40e_read_stats_registers(pf, hw);
2509
2510         if (xstats == NULL)
2511                 return 0;
2512
2513         count = 0;
2514
2515         /* Get stats from i40e_eth_stats struct */
2516         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2517                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2518                         rte_i40e_stats_strings[i].offset);
2519                 count++;
2520         }
2521
2522         /* Get individiual stats from i40e_hw_port struct */
2523         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2524                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2525                         rte_i40e_hw_port_strings[i].offset);
2526                 count++;
2527         }
2528
2529         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2530                 for (prio = 0; prio < 8; prio++) {
2531                         xstats[count].value =
2532                                 *(uint64_t *)(((char *)hw_stats) +
2533                                 rte_i40e_rxq_prio_strings[i].offset +
2534                                 (sizeof(uint64_t) * prio));
2535                         count++;
2536                 }
2537         }
2538
2539         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2540                 for (prio = 0; prio < 8; prio++) {
2541                         xstats[count].value =
2542                                 *(uint64_t *)(((char *)hw_stats) +
2543                                 rte_i40e_txq_prio_strings[i].offset +
2544                                 (sizeof(uint64_t) * prio));
2545                         count++;
2546                 }
2547         }
2548
2549         return count;
2550 }
2551
2552 static int
2553 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2554                                  __rte_unused uint16_t queue_id,
2555                                  __rte_unused uint8_t stat_idx,
2556                                  __rte_unused uint8_t is_rx)
2557 {
2558         PMD_INIT_FUNC_TRACE();
2559
2560         return -ENOSYS;
2561 }
2562
2563 static void
2564 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2565 {
2566         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2567         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2568         struct i40e_vsi *vsi = pf->main_vsi;
2569
2570         dev_info->max_rx_queues = vsi->nb_qps;
2571         dev_info->max_tx_queues = vsi->nb_qps;
2572         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2573         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2574         dev_info->max_mac_addrs = vsi->max_macaddrs;
2575         dev_info->max_vfs = dev->pci_dev->max_vfs;
2576         dev_info->rx_offload_capa =
2577                 DEV_RX_OFFLOAD_VLAN_STRIP |
2578                 DEV_RX_OFFLOAD_QINQ_STRIP |
2579                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2580                 DEV_RX_OFFLOAD_UDP_CKSUM |
2581                 DEV_RX_OFFLOAD_TCP_CKSUM;
2582         dev_info->tx_offload_capa =
2583                 DEV_TX_OFFLOAD_VLAN_INSERT |
2584                 DEV_TX_OFFLOAD_QINQ_INSERT |
2585                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2586                 DEV_TX_OFFLOAD_UDP_CKSUM |
2587                 DEV_TX_OFFLOAD_TCP_CKSUM |
2588                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2589                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2590                 DEV_TX_OFFLOAD_TCP_TSO;
2591         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2592                                                 sizeof(uint32_t);
2593         dev_info->reta_size = pf->hash_lut_size;
2594         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2595
2596         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2597                 .rx_thresh = {
2598                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2599                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2600                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2601                 },
2602                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2603                 .rx_drop_en = 0,
2604         };
2605
2606         dev_info->default_txconf = (struct rte_eth_txconf) {
2607                 .tx_thresh = {
2608                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2609                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2610                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2611                 },
2612                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2613                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2614                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2615                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2616         };
2617
2618         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2619                 .nb_max = I40E_MAX_RING_DESC,
2620                 .nb_min = I40E_MIN_RING_DESC,
2621                 .nb_align = I40E_ALIGN_RING_DESC,
2622         };
2623
2624         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2625                 .nb_max = I40E_MAX_RING_DESC,
2626                 .nb_min = I40E_MIN_RING_DESC,
2627                 .nb_align = I40E_ALIGN_RING_DESC,
2628         };
2629
2630         if (pf->flags & I40E_FLAG_VMDQ) {
2631                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2632                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2633                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2634                                                 pf->max_nb_vmdq_vsi;
2635                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2636                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2637                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2638         }
2639
2640         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2641                 /* For XL710 */
2642                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2643         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2644                 /* For XXV710 */
2645                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2646         else
2647                 /* For X710 */
2648                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2649 }
2650
2651 static int
2652 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2653 {
2654         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2655         struct i40e_vsi *vsi = pf->main_vsi;
2656         PMD_INIT_FUNC_TRACE();
2657
2658         if (on)
2659                 return i40e_vsi_add_vlan(vsi, vlan_id);
2660         else
2661                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2662 }
2663
2664 static int
2665 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2666                    enum rte_vlan_type vlan_type,
2667                    uint16_t tpid)
2668 {
2669         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2670         uint64_t reg_r = 0, reg_w = 0;
2671         uint16_t reg_id = 0;
2672         int ret = 0;
2673         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2674
2675         switch (vlan_type) {
2676         case ETH_VLAN_TYPE_OUTER:
2677                 if (qinq)
2678                         reg_id = 2;
2679                 else
2680                         reg_id = 3;
2681                 break;
2682         case ETH_VLAN_TYPE_INNER:
2683                 if (qinq)
2684                         reg_id = 3;
2685                 else {
2686                         ret = -EINVAL;
2687                         PMD_DRV_LOG(ERR,
2688                                 "Unsupported vlan type in single vlan.\n");
2689                         return ret;
2690                 }
2691                 break;
2692         default:
2693                 ret = -EINVAL;
2694                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2695                 return ret;
2696         }
2697         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2698                                           &reg_r, NULL);
2699         if (ret != I40E_SUCCESS) {
2700                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2701                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2702                 ret = -EIO;
2703                 return ret;
2704         }
2705         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2706                     "0x%08"PRIx64"", reg_id, reg_r);
2707
2708         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2709         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2710         if (reg_r == reg_w) {
2711                 ret = 0;
2712                 PMD_DRV_LOG(DEBUG, "No need to write");
2713                 return ret;
2714         }
2715
2716         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2717                                            reg_w, NULL);
2718         if (ret != I40E_SUCCESS) {
2719                 ret = -EIO;
2720                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2721                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2722                 return ret;
2723         }
2724         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2725                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2726
2727         return ret;
2728 }
2729
2730 static void
2731 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2732 {
2733         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2734         struct i40e_vsi *vsi = pf->main_vsi;
2735
2736         if (mask & ETH_VLAN_FILTER_MASK) {
2737                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2738                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2739                 else
2740                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2741         }
2742
2743         if (mask & ETH_VLAN_STRIP_MASK) {
2744                 /* Enable or disable VLAN stripping */
2745                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2746                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2747                 else
2748                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2749         }
2750
2751         if (mask & ETH_VLAN_EXTEND_MASK) {
2752                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2753                         i40e_vsi_config_double_vlan(vsi, TRUE);
2754                         /* Set global registers with default ether type value */
2755                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2756                                            ETHER_TYPE_VLAN);
2757                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2758                                            ETHER_TYPE_VLAN);
2759                 }
2760                 else
2761                         i40e_vsi_config_double_vlan(vsi, FALSE);
2762         }
2763 }
2764
2765 static void
2766 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2767                           __rte_unused uint16_t queue,
2768                           __rte_unused int on)
2769 {
2770         PMD_INIT_FUNC_TRACE();
2771 }
2772
2773 static int
2774 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2775 {
2776         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2777         struct i40e_vsi *vsi = pf->main_vsi;
2778         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2779         struct i40e_vsi_vlan_pvid_info info;
2780
2781         memset(&info, 0, sizeof(info));
2782         info.on = on;
2783         if (info.on)
2784                 info.config.pvid = pvid;
2785         else {
2786                 info.config.reject.tagged =
2787                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2788                 info.config.reject.untagged =
2789                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2790         }
2791
2792         return i40e_vsi_vlan_pvid_set(vsi, &info);
2793 }
2794
2795 static int
2796 i40e_dev_led_on(struct rte_eth_dev *dev)
2797 {
2798         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2799         uint32_t mode = i40e_led_get(hw);
2800
2801         if (mode == 0)
2802                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2803
2804         return 0;
2805 }
2806
2807 static int
2808 i40e_dev_led_off(struct rte_eth_dev *dev)
2809 {
2810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         uint32_t mode = i40e_led_get(hw);
2812
2813         if (mode != 0)
2814                 i40e_led_set(hw, 0, false);
2815
2816         return 0;
2817 }
2818
2819 static int
2820 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2821 {
2822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2823         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2824
2825         fc_conf->pause_time = pf->fc_conf.pause_time;
2826         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2827         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2828
2829          /* Return current mode according to actual setting*/
2830         switch (hw->fc.current_mode) {
2831         case I40E_FC_FULL:
2832                 fc_conf->mode = RTE_FC_FULL;
2833                 break;
2834         case I40E_FC_TX_PAUSE:
2835                 fc_conf->mode = RTE_FC_TX_PAUSE;
2836                 break;
2837         case I40E_FC_RX_PAUSE:
2838                 fc_conf->mode = RTE_FC_RX_PAUSE;
2839                 break;
2840         case I40E_FC_NONE:
2841         default:
2842                 fc_conf->mode = RTE_FC_NONE;
2843         };
2844
2845         return 0;
2846 }
2847
2848 static int
2849 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2850 {
2851         uint32_t mflcn_reg, fctrl_reg, reg;
2852         uint32_t max_high_water;
2853         uint8_t i, aq_failure;
2854         int err;
2855         struct i40e_hw *hw;
2856         struct i40e_pf *pf;
2857         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2858                 [RTE_FC_NONE] = I40E_FC_NONE,
2859                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2860                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2861                 [RTE_FC_FULL] = I40E_FC_FULL
2862         };
2863
2864         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2865
2866         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2867         if ((fc_conf->high_water > max_high_water) ||
2868                         (fc_conf->high_water < fc_conf->low_water)) {
2869                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2870                         "High_water must <= %d.", max_high_water);
2871                 return -EINVAL;
2872         }
2873
2874         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2875         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2876         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2877
2878         pf->fc_conf.pause_time = fc_conf->pause_time;
2879         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2880         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2881
2882         PMD_INIT_FUNC_TRACE();
2883
2884         /* All the link flow control related enable/disable register
2885          * configuration is handle by the F/W
2886          */
2887         err = i40e_set_fc(hw, &aq_failure, true);
2888         if (err < 0)
2889                 return -ENOSYS;
2890
2891         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2892                 /* Configure flow control refresh threshold,
2893                  * the value for stat_tx_pause_refresh_timer[8]
2894                  * is used for global pause operation.
2895                  */
2896
2897                 I40E_WRITE_REG(hw,
2898                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2899                                pf->fc_conf.pause_time);
2900
2901                 /* configure the timer value included in transmitted pause
2902                  * frame,
2903                  * the value for stat_tx_pause_quanta[8] is used for global
2904                  * pause operation
2905                  */
2906                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2907                                pf->fc_conf.pause_time);
2908
2909                 fctrl_reg = I40E_READ_REG(hw,
2910                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2911
2912                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2913                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2914                 else
2915                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2916
2917                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2918                                fctrl_reg);
2919         } else {
2920                 /* Configure pause time (2 TCs per register) */
2921                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2922                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2923                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2924
2925                 /* Configure flow control refresh threshold value */
2926                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2927                                pf->fc_conf.pause_time / 2);
2928
2929                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2930
2931                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2932                  *depending on configuration
2933                  */
2934                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2935                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2936                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2937                 } else {
2938                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2939                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2940                 }
2941
2942                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2943         }
2944
2945         /* config the water marker both based on the packets and bytes */
2946         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2947                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2948                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2949         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2950                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2951                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2952         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2953                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2954                        << I40E_KILOSHIFT);
2955         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2956                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2957                        << I40E_KILOSHIFT);
2958
2959         I40E_WRITE_FLUSH(hw);
2960
2961         return 0;
2962 }
2963
2964 static int
2965 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2966                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2967 {
2968         PMD_INIT_FUNC_TRACE();
2969
2970         return -ENOSYS;
2971 }
2972
2973 /* Add a MAC address, and update filters */
2974 static void
2975 i40e_macaddr_add(struct rte_eth_dev *dev,
2976                  struct ether_addr *mac_addr,
2977                  __rte_unused uint32_t index,
2978                  uint32_t pool)
2979 {
2980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2981         struct i40e_mac_filter_info mac_filter;
2982         struct i40e_vsi *vsi;
2983         int ret;
2984
2985         /* If VMDQ not enabled or configured, return */
2986         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2987                           !pf->nb_cfg_vmdq_vsi)) {
2988                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2989                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2990                         pool);
2991                 return;
2992         }
2993
2994         if (pool > pf->nb_cfg_vmdq_vsi) {
2995                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2996                                 pool, pf->nb_cfg_vmdq_vsi);
2997                 return;
2998         }
2999
3000         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3001         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3002                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3003         else
3004                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3005
3006         if (pool == 0)
3007                 vsi = pf->main_vsi;
3008         else
3009                 vsi = pf->vmdq[pool - 1].vsi;
3010
3011         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3012         if (ret != I40E_SUCCESS) {
3013                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3014                 return;
3015         }
3016 }
3017
3018 /* Remove a MAC address, and update filters */
3019 static void
3020 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3021 {
3022         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3023         struct i40e_vsi *vsi;
3024         struct rte_eth_dev_data *data = dev->data;
3025         struct ether_addr *macaddr;
3026         int ret;
3027         uint32_t i;
3028         uint64_t pool_sel;
3029
3030         macaddr = &(data->mac_addrs[index]);
3031
3032         pool_sel = dev->data->mac_pool_sel[index];
3033
3034         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3035                 if (pool_sel & (1ULL << i)) {
3036                         if (i == 0)
3037                                 vsi = pf->main_vsi;
3038                         else {
3039                                 /* No VMDQ pool enabled or configured */
3040                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3041                                         (i > pf->nb_cfg_vmdq_vsi)) {
3042                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3043                                                         "/configured");
3044                                         return;
3045                                 }
3046                                 vsi = pf->vmdq[i - 1].vsi;
3047                         }
3048                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3049
3050                         if (ret) {
3051                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3052                                 return;
3053                         }
3054                 }
3055         }
3056 }
3057
3058 /* Set perfect match or hash match of MAC and VLAN for a VF */
3059 static int
3060 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3061                  struct rte_eth_mac_filter *filter,
3062                  bool add)
3063 {
3064         struct i40e_hw *hw;
3065         struct i40e_mac_filter_info mac_filter;
3066         struct ether_addr old_mac;
3067         struct ether_addr *new_mac;
3068         struct i40e_pf_vf *vf = NULL;
3069         uint16_t vf_id;
3070         int ret;
3071
3072         if (pf == NULL) {
3073                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3074                 return -EINVAL;
3075         }
3076         hw = I40E_PF_TO_HW(pf);
3077
3078         if (filter == NULL) {
3079                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3080                 return -EINVAL;
3081         }
3082
3083         new_mac = &filter->mac_addr;
3084
3085         if (is_zero_ether_addr(new_mac)) {
3086                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3087                 return -EINVAL;
3088         }
3089
3090         vf_id = filter->dst_id;
3091
3092         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3093                 PMD_DRV_LOG(ERR, "Invalid argument.");
3094                 return -EINVAL;
3095         }
3096         vf = &pf->vfs[vf_id];
3097
3098         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3099                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3100                 return -EINVAL;
3101         }
3102
3103         if (add) {
3104                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3105                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3106                                 ETHER_ADDR_LEN);
3107                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3108                                  ETHER_ADDR_LEN);
3109
3110                 mac_filter.filter_type = filter->filter_type;
3111                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3112                 if (ret != I40E_SUCCESS) {
3113                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3114                         return -1;
3115                 }
3116                 ether_addr_copy(new_mac, &pf->dev_addr);
3117         } else {
3118                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3119                                 ETHER_ADDR_LEN);
3120                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3121                 if (ret != I40E_SUCCESS) {
3122                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3123                         return -1;
3124                 }
3125
3126                 /* Clear device address as it has been removed */
3127                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3128                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3129         }
3130
3131         return 0;
3132 }
3133
3134 /* MAC filter handle */
3135 static int
3136 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3137                 void *arg)
3138 {
3139         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3140         struct rte_eth_mac_filter *filter;
3141         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3142         int ret = I40E_NOT_SUPPORTED;
3143
3144         filter = (struct rte_eth_mac_filter *)(arg);
3145
3146         switch (filter_op) {
3147         case RTE_ETH_FILTER_NOP:
3148                 ret = I40E_SUCCESS;
3149                 break;
3150         case RTE_ETH_FILTER_ADD:
3151                 i40e_pf_disable_irq0(hw);
3152                 if (filter->is_vf)
3153                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3154                 i40e_pf_enable_irq0(hw);
3155                 break;
3156         case RTE_ETH_FILTER_DELETE:
3157                 i40e_pf_disable_irq0(hw);
3158                 if (filter->is_vf)
3159                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3160                 i40e_pf_enable_irq0(hw);
3161                 break;
3162         default:
3163                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3164                 ret = I40E_ERR_PARAM;
3165                 break;
3166         }
3167
3168         return ret;
3169 }
3170
3171 static int
3172 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3173 {
3174         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3175         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3176         int ret;
3177
3178         if (!lut)
3179                 return -EINVAL;
3180
3181         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3182                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3183                                           lut, lut_size);
3184                 if (ret) {
3185                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3186                         return ret;
3187                 }
3188         } else {
3189                 uint32_t *lut_dw = (uint32_t *)lut;
3190                 uint16_t i, lut_size_dw = lut_size / 4;
3191
3192                 for (i = 0; i < lut_size_dw; i++)
3193                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3194         }
3195
3196         return 0;
3197 }
3198
3199 static int
3200 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3201 {
3202         struct i40e_pf *pf;
3203         struct i40e_hw *hw;
3204         int ret;
3205
3206         if (!vsi || !lut)
3207                 return -EINVAL;
3208
3209         pf = I40E_VSI_TO_PF(vsi);
3210         hw = I40E_VSI_TO_HW(vsi);
3211
3212         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3213                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3214                                           lut, lut_size);
3215                 if (ret) {
3216                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3217                         return ret;
3218                 }
3219         } else {
3220                 uint32_t *lut_dw = (uint32_t *)lut;
3221                 uint16_t i, lut_size_dw = lut_size / 4;
3222
3223                 for (i = 0; i < lut_size_dw; i++)
3224                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3225                 I40E_WRITE_FLUSH(hw);
3226         }
3227
3228         return 0;
3229 }
3230
3231 static int
3232 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3233                          struct rte_eth_rss_reta_entry64 *reta_conf,
3234                          uint16_t reta_size)
3235 {
3236         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3237         uint16_t i, lut_size = pf->hash_lut_size;
3238         uint16_t idx, shift;
3239         uint8_t *lut;
3240         int ret;
3241
3242         if (reta_size != lut_size ||
3243                 reta_size > ETH_RSS_RETA_SIZE_512) {
3244                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3245                         "(%d) doesn't match the number hardware can supported "
3246                                         "(%d)\n", reta_size, lut_size);
3247                 return -EINVAL;
3248         }
3249
3250         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3251         if (!lut) {
3252                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3253                 return -ENOMEM;
3254         }
3255         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3256         if (ret)
3257                 goto out;
3258         for (i = 0; i < reta_size; i++) {
3259                 idx = i / RTE_RETA_GROUP_SIZE;
3260                 shift = i % RTE_RETA_GROUP_SIZE;
3261                 if (reta_conf[idx].mask & (1ULL << shift))
3262                         lut[i] = reta_conf[idx].reta[shift];
3263         }
3264         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3265
3266 out:
3267         rte_free(lut);
3268
3269         return ret;
3270 }
3271
3272 static int
3273 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3274                         struct rte_eth_rss_reta_entry64 *reta_conf,
3275                         uint16_t reta_size)
3276 {
3277         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3278         uint16_t i, lut_size = pf->hash_lut_size;
3279         uint16_t idx, shift;
3280         uint8_t *lut;
3281         int ret;
3282
3283         if (reta_size != lut_size ||
3284                 reta_size > ETH_RSS_RETA_SIZE_512) {
3285                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3286                         "(%d) doesn't match the number hardware can supported "
3287                                         "(%d)\n", reta_size, lut_size);
3288                 return -EINVAL;
3289         }
3290
3291         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3292         if (!lut) {
3293                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3294                 return -ENOMEM;
3295         }
3296
3297         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3298         if (ret)
3299                 goto out;
3300         for (i = 0; i < reta_size; i++) {
3301                 idx = i / RTE_RETA_GROUP_SIZE;
3302                 shift = i % RTE_RETA_GROUP_SIZE;
3303                 if (reta_conf[idx].mask & (1ULL << shift))
3304                         reta_conf[idx].reta[shift] = lut[i];
3305         }
3306
3307 out:
3308         rte_free(lut);
3309
3310         return ret;
3311 }
3312
3313 /**
3314  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3315  * @hw:   pointer to the HW structure
3316  * @mem:  pointer to mem struct to fill out
3317  * @size: size of memory requested
3318  * @alignment: what to align the allocation to
3319  **/
3320 enum i40e_status_code
3321 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3322                         struct i40e_dma_mem *mem,
3323                         u64 size,
3324                         u32 alignment)
3325 {
3326         const struct rte_memzone *mz = NULL;
3327         char z_name[RTE_MEMZONE_NAMESIZE];
3328
3329         if (!mem)
3330                 return I40E_ERR_PARAM;
3331
3332         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3333         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3334                                          alignment, RTE_PGSIZE_2M);
3335         if (!mz)
3336                 return I40E_ERR_NO_MEMORY;
3337
3338         mem->size = size;
3339         mem->va = mz->addr;
3340         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3341         mem->zone = (const void *)mz;
3342         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3343                     "%"PRIu64, mz->name, mem->pa);
3344
3345         return I40E_SUCCESS;
3346 }
3347
3348 /**
3349  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3350  * @hw:   pointer to the HW structure
3351  * @mem:  ptr to mem struct to free
3352  **/
3353 enum i40e_status_code
3354 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3355                     struct i40e_dma_mem *mem)
3356 {
3357         if (!mem)
3358                 return I40E_ERR_PARAM;
3359
3360         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3361                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3362                     mem->pa);
3363         rte_memzone_free((const struct rte_memzone *)mem->zone);
3364         mem->zone = NULL;
3365         mem->va = NULL;
3366         mem->pa = (u64)0;
3367
3368         return I40E_SUCCESS;
3369 }
3370
3371 /**
3372  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3373  * @hw:   pointer to the HW structure
3374  * @mem:  pointer to mem struct to fill out
3375  * @size: size of memory requested
3376  **/
3377 enum i40e_status_code
3378 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3379                          struct i40e_virt_mem *mem,
3380                          u32 size)
3381 {
3382         if (!mem)
3383                 return I40E_ERR_PARAM;
3384
3385         mem->size = size;
3386         mem->va = rte_zmalloc("i40e", size, 0);
3387
3388         if (mem->va)
3389                 return I40E_SUCCESS;
3390         else
3391                 return I40E_ERR_NO_MEMORY;
3392 }
3393
3394 /**
3395  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3396  * @hw:   pointer to the HW structure
3397  * @mem:  pointer to mem struct to free
3398  **/
3399 enum i40e_status_code
3400 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3401                      struct i40e_virt_mem *mem)
3402 {
3403         if (!mem)
3404                 return I40E_ERR_PARAM;
3405
3406         rte_free(mem->va);
3407         mem->va = NULL;
3408
3409         return I40E_SUCCESS;
3410 }
3411
3412 void
3413 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3414 {
3415         rte_spinlock_init(&sp->spinlock);
3416 }
3417
3418 void
3419 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3420 {
3421         rte_spinlock_lock(&sp->spinlock);
3422 }
3423
3424 void
3425 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3426 {
3427         rte_spinlock_unlock(&sp->spinlock);
3428 }
3429
3430 void
3431 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3432 {
3433         return;
3434 }
3435
3436 /**
3437  * Get the hardware capabilities, which will be parsed
3438  * and saved into struct i40e_hw.
3439  */
3440 static int
3441 i40e_get_cap(struct i40e_hw *hw)
3442 {
3443         struct i40e_aqc_list_capabilities_element_resp *buf;
3444         uint16_t len, size = 0;
3445         int ret;
3446
3447         /* Calculate a huge enough buff for saving response data temporarily */
3448         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3449                                                 I40E_MAX_CAP_ELE_NUM;
3450         buf = rte_zmalloc("i40e", len, 0);
3451         if (!buf) {
3452                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3453                 return I40E_ERR_NO_MEMORY;
3454         }
3455
3456         /* Get, parse the capabilities and save it to hw */
3457         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3458                         i40e_aqc_opc_list_func_capabilities, NULL);
3459         if (ret != I40E_SUCCESS)
3460                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3461
3462         /* Free the temporary buffer after being used */
3463         rte_free(buf);
3464
3465         return ret;
3466 }
3467
3468 static int
3469 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3470 {
3471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3472         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3473         uint16_t qp_count = 0, vsi_count = 0;
3474
3475         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3476                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3477                 return -EINVAL;
3478         }
3479         /* Add the parameter init for LFC */
3480         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3481         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3482         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3483
3484         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3485         pf->max_num_vsi = hw->func_caps.num_vsis;
3486         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3487         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3488         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3489
3490         /* FDir queue/VSI allocation */
3491         pf->fdir_qp_offset = 0;
3492         if (hw->func_caps.fd) {
3493                 pf->flags |= I40E_FLAG_FDIR;
3494                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3495         } else {
3496                 pf->fdir_nb_qps = 0;
3497         }
3498         qp_count += pf->fdir_nb_qps;
3499         vsi_count += 1;
3500
3501         /* LAN queue/VSI allocation */
3502         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3503         if (!hw->func_caps.rss) {
3504                 pf->lan_nb_qps = 1;
3505         } else {
3506                 pf->flags |= I40E_FLAG_RSS;
3507                 if (hw->mac.type == I40E_MAC_X722)
3508                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3509                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3510         }
3511         qp_count += pf->lan_nb_qps;
3512         vsi_count += 1;
3513
3514         /* VF queue/VSI allocation */
3515         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3516         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3517                 pf->flags |= I40E_FLAG_SRIOV;
3518                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3519                 pf->vf_num = dev->pci_dev->max_vfs;
3520                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3521                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3522                             pf->vf_nb_qps * pf->vf_num);
3523         } else {
3524                 pf->vf_nb_qps = 0;
3525                 pf->vf_num = 0;
3526         }
3527         qp_count += pf->vf_nb_qps * pf->vf_num;
3528         vsi_count += pf->vf_num;
3529
3530         /* VMDq queue/VSI allocation */
3531         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3532         pf->vmdq_nb_qps = 0;
3533         pf->max_nb_vmdq_vsi = 0;
3534         if (hw->func_caps.vmdq) {
3535                 if (qp_count < hw->func_caps.num_tx_qp &&
3536                         vsi_count < hw->func_caps.num_vsis) {
3537                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3538                                 qp_count) / pf->vmdq_nb_qp_max;
3539
3540                         /* Limit the maximum number of VMDq vsi to the maximum
3541                          * ethdev can support
3542                          */
3543                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3544                                 hw->func_caps.num_vsis - vsi_count);
3545                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3546                                 ETH_64_POOLS);
3547                         if (pf->max_nb_vmdq_vsi) {
3548                                 pf->flags |= I40E_FLAG_VMDQ;
3549                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3550                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3551                                             "per VMDQ VSI, in total %u queues",
3552                                             pf->max_nb_vmdq_vsi,
3553                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3554                                             pf->max_nb_vmdq_vsi);
3555                         } else {
3556                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3557                                             "VMDq");
3558                         }
3559                 } else {
3560                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3561                 }
3562         }
3563         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3564         vsi_count += pf->max_nb_vmdq_vsi;
3565
3566         if (hw->func_caps.dcb)
3567                 pf->flags |= I40E_FLAG_DCB;
3568
3569         if (qp_count > hw->func_caps.num_tx_qp) {
3570                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3571                             "the hardware maximum %u", qp_count,
3572                             hw->func_caps.num_tx_qp);
3573                 return -EINVAL;
3574         }
3575         if (vsi_count > hw->func_caps.num_vsis) {
3576                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3577                             "the hardware maximum %u", vsi_count,
3578                             hw->func_caps.num_vsis);
3579                 return -EINVAL;
3580         }
3581
3582         return 0;
3583 }
3584
3585 static int
3586 i40e_pf_get_switch_config(struct i40e_pf *pf)
3587 {
3588         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3589         struct i40e_aqc_get_switch_config_resp *switch_config;
3590         struct i40e_aqc_switch_config_element_resp *element;
3591         uint16_t start_seid = 0, num_reported;
3592         int ret;
3593
3594         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3595                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3596         if (!switch_config) {
3597                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3598                 return -ENOMEM;
3599         }
3600
3601         /* Get the switch configurations */
3602         ret = i40e_aq_get_switch_config(hw, switch_config,
3603                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3604         if (ret != I40E_SUCCESS) {
3605                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3606                 goto fail;
3607         }
3608         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3609         if (num_reported != 1) { /* The number should be 1 */
3610                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3611                 goto fail;
3612         }
3613
3614         /* Parse the switch configuration elements */
3615         element = &(switch_config->element[0]);
3616         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3617                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3618                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3619         } else
3620                 PMD_DRV_LOG(INFO, "Unknown element type");
3621
3622 fail:
3623         rte_free(switch_config);
3624
3625         return ret;
3626 }
3627
3628 static int
3629 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3630                         uint32_t num)
3631 {
3632         struct pool_entry *entry;
3633
3634         if (pool == NULL || num == 0)
3635                 return -EINVAL;
3636
3637         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3638         if (entry == NULL) {
3639                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3640                 return -ENOMEM;
3641         }
3642
3643         /* queue heap initialize */
3644         pool->num_free = num;
3645         pool->num_alloc = 0;
3646         pool->base = base;
3647         LIST_INIT(&pool->alloc_list);
3648         LIST_INIT(&pool->free_list);
3649
3650         /* Initialize element  */
3651         entry->base = 0;
3652         entry->len = num;
3653
3654         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3655         return 0;
3656 }
3657
3658 static void
3659 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3660 {
3661         struct pool_entry *entry, *next_entry;
3662
3663         if (pool == NULL)
3664                 return;
3665
3666         for (entry = LIST_FIRST(&pool->alloc_list);
3667                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3668                         entry = next_entry) {
3669                 LIST_REMOVE(entry, next);
3670                 rte_free(entry);
3671         }
3672
3673         for (entry = LIST_FIRST(&pool->free_list);
3674                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3675                         entry = next_entry) {
3676                 LIST_REMOVE(entry, next);
3677                 rte_free(entry);
3678         }
3679
3680         pool->num_free = 0;
3681         pool->num_alloc = 0;
3682         pool->base = 0;
3683         LIST_INIT(&pool->alloc_list);
3684         LIST_INIT(&pool->free_list);
3685 }
3686
3687 static int
3688 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3689                        uint32_t base)
3690 {
3691         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3692         uint32_t pool_offset;
3693         int insert;
3694
3695         if (pool == NULL) {
3696                 PMD_DRV_LOG(ERR, "Invalid parameter");
3697                 return -EINVAL;
3698         }
3699
3700         pool_offset = base - pool->base;
3701         /* Lookup in alloc list */
3702         LIST_FOREACH(entry, &pool->alloc_list, next) {
3703                 if (entry->base == pool_offset) {
3704                         valid_entry = entry;
3705                         LIST_REMOVE(entry, next);
3706                         break;
3707                 }
3708         }
3709
3710         /* Not find, return */
3711         if (valid_entry == NULL) {
3712                 PMD_DRV_LOG(ERR, "Failed to find entry");
3713                 return -EINVAL;
3714         }
3715
3716         /**
3717          * Found it, move it to free list  and try to merge.
3718          * In order to make merge easier, always sort it by qbase.
3719          * Find adjacent prev and last entries.
3720          */
3721         prev = next = NULL;
3722         LIST_FOREACH(entry, &pool->free_list, next) {
3723                 if (entry->base > valid_entry->base) {
3724                         next = entry;
3725                         break;
3726                 }
3727                 prev = entry;
3728         }
3729
3730         insert = 0;
3731         /* Try to merge with next one*/
3732         if (next != NULL) {
3733                 /* Merge with next one */
3734                 if (valid_entry->base + valid_entry->len == next->base) {
3735                         next->base = valid_entry->base;
3736                         next->len += valid_entry->len;
3737                         rte_free(valid_entry);
3738                         valid_entry = next;
3739                         insert = 1;
3740                 }
3741         }
3742
3743         if (prev != NULL) {
3744                 /* Merge with previous one */
3745                 if (prev->base + prev->len == valid_entry->base) {
3746                         prev->len += valid_entry->len;
3747                         /* If it merge with next one, remove next node */
3748                         if (insert == 1) {
3749                                 LIST_REMOVE(valid_entry, next);
3750                                 rte_free(valid_entry);
3751                         } else {
3752                                 rte_free(valid_entry);
3753                                 insert = 1;
3754                         }
3755                 }
3756         }
3757
3758         /* Not find any entry to merge, insert */
3759         if (insert == 0) {
3760                 if (prev != NULL)
3761                         LIST_INSERT_AFTER(prev, valid_entry, next);
3762                 else if (next != NULL)
3763                         LIST_INSERT_BEFORE(next, valid_entry, next);
3764                 else /* It's empty list, insert to head */
3765                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3766         }
3767
3768         pool->num_free += valid_entry->len;
3769         pool->num_alloc -= valid_entry->len;
3770
3771         return 0;
3772 }
3773
3774 static int
3775 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3776                        uint16_t num)
3777 {
3778         struct pool_entry *entry, *valid_entry;
3779
3780         if (pool == NULL || num == 0) {
3781                 PMD_DRV_LOG(ERR, "Invalid parameter");
3782                 return -EINVAL;
3783         }
3784
3785         if (pool->num_free < num) {
3786                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3787                             num, pool->num_free);
3788                 return -ENOMEM;
3789         }
3790
3791         valid_entry = NULL;
3792         /* Lookup  in free list and find most fit one */
3793         LIST_FOREACH(entry, &pool->free_list, next) {
3794                 if (entry->len >= num) {
3795                         /* Find best one */
3796                         if (entry->len == num) {
3797                                 valid_entry = entry;
3798                                 break;
3799                         }
3800                         if (valid_entry == NULL || valid_entry->len > entry->len)
3801                                 valid_entry = entry;
3802                 }
3803         }
3804
3805         /* Not find one to satisfy the request, return */
3806         if (valid_entry == NULL) {
3807                 PMD_DRV_LOG(ERR, "No valid entry found");
3808                 return -ENOMEM;
3809         }
3810         /**
3811          * The entry have equal queue number as requested,
3812          * remove it from alloc_list.
3813          */
3814         if (valid_entry->len == num) {
3815                 LIST_REMOVE(valid_entry, next);
3816         } else {
3817                 /**
3818                  * The entry have more numbers than requested,
3819                  * create a new entry for alloc_list and minus its
3820                  * queue base and number in free_list.
3821                  */
3822                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3823                 if (entry == NULL) {
3824                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3825                                     "resource pool");
3826                         return -ENOMEM;
3827                 }
3828                 entry->base = valid_entry->base;
3829                 entry->len = num;
3830                 valid_entry->base += num;
3831                 valid_entry->len -= num;
3832                 valid_entry = entry;
3833         }
3834
3835         /* Insert it into alloc list, not sorted */
3836         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3837
3838         pool->num_free -= valid_entry->len;
3839         pool->num_alloc += valid_entry->len;
3840
3841         return valid_entry->base + pool->base;
3842 }
3843
3844 /**
3845  * bitmap_is_subset - Check whether src2 is subset of src1
3846  **/
3847 static inline int
3848 bitmap_is_subset(uint8_t src1, uint8_t src2)
3849 {
3850         return !((src1 ^ src2) & src2);
3851 }
3852
3853 static enum i40e_status_code
3854 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3855 {
3856         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3857
3858         /* If DCB is not supported, only default TC is supported */
3859         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3860                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3861                 return I40E_NOT_SUPPORTED;
3862         }
3863
3864         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3865                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3866                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3867                             enabled_tcmap);
3868                 return I40E_NOT_SUPPORTED;
3869         }
3870         return I40E_SUCCESS;
3871 }
3872
3873 int
3874 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3875                                 struct i40e_vsi_vlan_pvid_info *info)
3876 {
3877         struct i40e_hw *hw;
3878         struct i40e_vsi_context ctxt;
3879         uint8_t vlan_flags = 0;
3880         int ret;
3881
3882         if (vsi == NULL || info == NULL) {
3883                 PMD_DRV_LOG(ERR, "invalid parameters");
3884                 return I40E_ERR_PARAM;
3885         }
3886
3887         if (info->on) {
3888                 vsi->info.pvid = info->config.pvid;
3889                 /**
3890                  * If insert pvid is enabled, only tagged pkts are
3891                  * allowed to be sent out.
3892                  */
3893                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3894                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3895         } else {
3896                 vsi->info.pvid = 0;
3897                 if (info->config.reject.tagged == 0)
3898                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3899
3900                 if (info->config.reject.untagged == 0)
3901                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3902         }
3903         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3904                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3905         vsi->info.port_vlan_flags |= vlan_flags;
3906         vsi->info.valid_sections =
3907                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3908         memset(&ctxt, 0, sizeof(ctxt));
3909         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3910         ctxt.seid = vsi->seid;
3911
3912         hw = I40E_VSI_TO_HW(vsi);
3913         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3914         if (ret != I40E_SUCCESS)
3915                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3916
3917         return ret;
3918 }
3919
3920 static int
3921 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3922 {
3923         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3924         int i, ret;
3925         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3926
3927         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3928         if (ret != I40E_SUCCESS)
3929                 return ret;
3930
3931         if (!vsi->seid) {
3932                 PMD_DRV_LOG(ERR, "seid not valid");
3933                 return -EINVAL;
3934         }
3935
3936         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3937         tc_bw_data.tc_valid_bits = enabled_tcmap;
3938         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3939                 tc_bw_data.tc_bw_credits[i] =
3940                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3941
3942         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3943         if (ret != I40E_SUCCESS) {
3944                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3945                 return ret;
3946         }
3947
3948         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3949                                         sizeof(vsi->info.qs_handle));
3950         return I40E_SUCCESS;
3951 }
3952
3953 static enum i40e_status_code
3954 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3955                                  struct i40e_aqc_vsi_properties_data *info,
3956                                  uint8_t enabled_tcmap)
3957 {
3958         enum i40e_status_code ret;
3959         int i, total_tc = 0;
3960         uint16_t qpnum_per_tc, bsf, qp_idx;
3961
3962         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3963         if (ret != I40E_SUCCESS)
3964                 return ret;
3965
3966         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3967                 if (enabled_tcmap & (1 << i))
3968                         total_tc++;
3969         vsi->enabled_tc = enabled_tcmap;
3970
3971         /* Number of queues per enabled TC */
3972         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3973         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3974         bsf = rte_bsf32(qpnum_per_tc);
3975
3976         /* Adjust the queue number to actual queues that can be applied */
3977         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3978                 vsi->nb_qps = qpnum_per_tc * total_tc;
3979
3980         /**
3981          * Configure TC and queue mapping parameters, for enabled TC,
3982          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3983          * default queue will serve it.
3984          */
3985         qp_idx = 0;
3986         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3987                 if (vsi->enabled_tc & (1 << i)) {
3988                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3989                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3990                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3991                         qp_idx += qpnum_per_tc;
3992                 } else
3993                         info->tc_mapping[i] = 0;
3994         }
3995
3996         /* Associate queue number with VSI */
3997         if (vsi->type == I40E_VSI_SRIOV) {
3998                 info->mapping_flags |=
3999                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4000                 for (i = 0; i < vsi->nb_qps; i++)
4001                         info->queue_mapping[i] =
4002                                 rte_cpu_to_le_16(vsi->base_queue + i);
4003         } else {
4004                 info->mapping_flags |=
4005                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4006                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4007         }
4008         info->valid_sections |=
4009                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4010
4011         return I40E_SUCCESS;
4012 }
4013
4014 static int
4015 i40e_veb_release(struct i40e_veb *veb)
4016 {
4017         struct i40e_vsi *vsi;
4018         struct i40e_hw *hw;
4019
4020         if (veb == NULL)
4021                 return -EINVAL;
4022
4023         if (!TAILQ_EMPTY(&veb->head)) {
4024                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4025                 return -EACCES;
4026         }
4027         /* associate_vsi field is NULL for floating VEB */
4028         if (veb->associate_vsi != NULL) {
4029                 vsi = veb->associate_vsi;
4030                 hw = I40E_VSI_TO_HW(vsi);
4031
4032                 vsi->uplink_seid = veb->uplink_seid;
4033                 vsi->veb = NULL;
4034         } else {
4035                 veb->associate_pf->main_vsi->floating_veb = NULL;
4036                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4037         }
4038
4039         i40e_aq_delete_element(hw, veb->seid, NULL);
4040         rte_free(veb);
4041         return I40E_SUCCESS;
4042 }
4043
4044 /* Setup a veb */
4045 static struct i40e_veb *
4046 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4047 {
4048         struct i40e_veb *veb;
4049         int ret;
4050         struct i40e_hw *hw;
4051
4052         if (pf == NULL) {
4053                 PMD_DRV_LOG(ERR,
4054                             "veb setup failed, associated PF shouldn't null");
4055                 return NULL;
4056         }
4057         hw = I40E_PF_TO_HW(pf);
4058
4059         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4060         if (!veb) {
4061                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4062                 goto fail;
4063         }
4064
4065         veb->associate_vsi = vsi;
4066         veb->associate_pf = pf;
4067         TAILQ_INIT(&veb->head);
4068         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4069
4070         /* create floating veb if vsi is NULL */
4071         if (vsi != NULL) {
4072                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4073                                       I40E_DEFAULT_TCMAP, false,
4074                                       &veb->seid, false, NULL);
4075         } else {
4076                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4077                                       true, &veb->seid, false, NULL);
4078         }
4079
4080         if (ret != I40E_SUCCESS) {
4081                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4082                             hw->aq.asq_last_status);
4083                 goto fail;
4084         }
4085
4086         /* get statistics index */
4087         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4088                                 &veb->stats_idx, NULL, NULL, NULL);
4089         if (ret != I40E_SUCCESS) {
4090                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4091                             hw->aq.asq_last_status);
4092                 goto fail;
4093         }
4094         /* Get VEB bandwidth, to be implemented */
4095         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4096         if (vsi)
4097                 vsi->uplink_seid = veb->seid;
4098
4099         return veb;
4100 fail:
4101         rte_free(veb);
4102         return NULL;
4103 }
4104
4105 int
4106 i40e_vsi_release(struct i40e_vsi *vsi)
4107 {
4108         struct i40e_pf *pf;
4109         struct i40e_hw *hw;
4110         struct i40e_vsi_list *vsi_list;
4111         void *temp;
4112         int ret;
4113         struct i40e_mac_filter *f;
4114         uint16_t user_param = vsi->user_param;
4115
4116         if (!vsi)
4117                 return I40E_SUCCESS;
4118
4119         pf = I40E_VSI_TO_PF(vsi);
4120         hw = I40E_VSI_TO_HW(vsi);
4121
4122         /* VSI has child to attach, release child first */
4123         if (vsi->veb) {
4124                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4125                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4126                                 return -1;
4127                 }
4128                 i40e_veb_release(vsi->veb);
4129         }
4130
4131         if (vsi->floating_veb) {
4132                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4133                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4134                                 return -1;
4135                 }
4136         }
4137
4138         /* Remove all macvlan filters of the VSI */
4139         i40e_vsi_remove_all_macvlan_filter(vsi);
4140         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4141                 rte_free(f);
4142
4143         if (vsi->type != I40E_VSI_MAIN &&
4144             ((vsi->type != I40E_VSI_SRIOV) ||
4145             !pf->floating_veb_list[user_param])) {
4146                 /* Remove vsi from parent's sibling list */
4147                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4148                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4149                         return I40E_ERR_PARAM;
4150                 }
4151                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4152                                 &vsi->sib_vsi_list, list);
4153
4154                 /* Remove all switch element of the VSI */
4155                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4156                 if (ret != I40E_SUCCESS)
4157                         PMD_DRV_LOG(ERR, "Failed to delete element");
4158         }
4159
4160         if ((vsi->type == I40E_VSI_SRIOV) &&
4161             pf->floating_veb_list[user_param]) {
4162                 /* Remove vsi from parent's sibling list */
4163                 if (vsi->parent_vsi == NULL ||
4164                     vsi->parent_vsi->floating_veb == NULL) {
4165                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4166                         return I40E_ERR_PARAM;
4167                 }
4168                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4169                              &vsi->sib_vsi_list, list);
4170
4171                 /* Remove all switch element of the VSI */
4172                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4173                 if (ret != I40E_SUCCESS)
4174                         PMD_DRV_LOG(ERR, "Failed to delete element");
4175         }
4176
4177         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4178
4179         if (vsi->type != I40E_VSI_SRIOV)
4180                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4181         rte_free(vsi);
4182
4183         return I40E_SUCCESS;
4184 }
4185
4186 static int
4187 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4188 {
4189         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4190         struct i40e_aqc_remove_macvlan_element_data def_filter;
4191         struct i40e_mac_filter_info filter;
4192         int ret;
4193
4194         if (vsi->type != I40E_VSI_MAIN)
4195                 return I40E_ERR_CONFIG;
4196         memset(&def_filter, 0, sizeof(def_filter));
4197         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4198                                         ETH_ADDR_LEN);
4199         def_filter.vlan_tag = 0;
4200         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4201                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4202         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4203         if (ret != I40E_SUCCESS) {
4204                 struct i40e_mac_filter *f;
4205                 struct ether_addr *mac;
4206
4207                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4208                             "macvlan filter");
4209                 /* It needs to add the permanent mac into mac list */
4210                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4211                 if (f == NULL) {
4212                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4213                         return I40E_ERR_NO_MEMORY;
4214                 }
4215                 mac = &f->mac_info.mac_addr;
4216                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4217                                 ETH_ADDR_LEN);
4218                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4219                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4220                 vsi->mac_num++;
4221
4222                 return ret;
4223         }
4224         (void)rte_memcpy(&filter.mac_addr,
4225                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4226         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4227         return i40e_vsi_add_mac(vsi, &filter);
4228 }
4229
4230 /*
4231  * i40e_vsi_get_bw_config - Query VSI BW Information
4232  * @vsi: the VSI to be queried
4233  *
4234  * Returns 0 on success, negative value on failure
4235  */
4236 static enum i40e_status_code
4237 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4238 {
4239         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4240         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4241         struct i40e_hw *hw = &vsi->adapter->hw;
4242         i40e_status ret;
4243         int i;
4244         uint32_t bw_max;
4245
4246         memset(&bw_config, 0, sizeof(bw_config));
4247         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4248         if (ret != I40E_SUCCESS) {
4249                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4250                             hw->aq.asq_last_status);
4251                 return ret;
4252         }
4253
4254         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4255         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4256                                         &ets_sla_config, NULL);
4257         if (ret != I40E_SUCCESS) {
4258                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4259                             "configuration %u", hw->aq.asq_last_status);
4260                 return ret;
4261         }
4262
4263         /* store and print out BW info */
4264         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4265         vsi->bw_info.bw_max = bw_config.max_bw;
4266         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4267         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4268         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4269                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4270                      I40E_16_BIT_WIDTH);
4271         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4272                 vsi->bw_info.bw_ets_share_credits[i] =
4273                                 ets_sla_config.share_credits[i];
4274                 vsi->bw_info.bw_ets_credits[i] =
4275                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4276                 /* 4 bits per TC, 4th bit is reserved */
4277                 vsi->bw_info.bw_ets_max[i] =
4278                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4279                                   RTE_LEN2MASK(3, uint8_t));
4280                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4281                             vsi->bw_info.bw_ets_share_credits[i]);
4282                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4283                             vsi->bw_info.bw_ets_credits[i]);
4284                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4285                             vsi->bw_info.bw_ets_max[i]);
4286         }
4287
4288         return I40E_SUCCESS;
4289 }
4290
4291 /* i40e_enable_pf_lb
4292  * @pf: pointer to the pf structure
4293  *
4294  * allow loopback on pf
4295  */
4296 static inline void
4297 i40e_enable_pf_lb(struct i40e_pf *pf)
4298 {
4299         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4300         struct i40e_vsi_context ctxt;
4301         int ret;
4302
4303         /* Use the FW API if FW >= v5.0 */
4304         if (hw->aq.fw_maj_ver < 5) {
4305                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4306                 return;
4307         }
4308
4309         memset(&ctxt, 0, sizeof(ctxt));
4310         ctxt.seid = pf->main_vsi_seid;
4311         ctxt.pf_num = hw->pf_id;
4312         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4313         if (ret) {
4314                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4315                             ret, hw->aq.asq_last_status);
4316                 return;
4317         }
4318         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4319         ctxt.info.valid_sections =
4320                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4321         ctxt.info.switch_id |=
4322                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4323
4324         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4325         if (ret)
4326                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4327                             hw->aq.asq_last_status);
4328 }
4329
4330 /* Setup a VSI */
4331 struct i40e_vsi *
4332 i40e_vsi_setup(struct i40e_pf *pf,
4333                enum i40e_vsi_type type,
4334                struct i40e_vsi *uplink_vsi,
4335                uint16_t user_param)
4336 {
4337         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4338         struct i40e_vsi *vsi;
4339         struct i40e_mac_filter_info filter;
4340         int ret;
4341         struct i40e_vsi_context ctxt;
4342         struct ether_addr broadcast =
4343                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4344
4345         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4346             uplink_vsi == NULL) {
4347                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4348                             "VSI link shouldn't be NULL");
4349                 return NULL;
4350         }
4351
4352         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4353                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4354                             "uplink VSI should be NULL");
4355                 return NULL;
4356         }
4357
4358         /* two situations
4359          * 1.type is not MAIN and uplink vsi is not NULL
4360          * If uplink vsi didn't setup VEB, create one first under veb field
4361          * 2.type is SRIOV and the uplink is NULL
4362          * If floating VEB is NULL, create one veb under floating veb field
4363          */
4364
4365         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4366             uplink_vsi->veb == NULL) {
4367                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4368
4369                 if (uplink_vsi->veb == NULL) {
4370                         PMD_DRV_LOG(ERR, "VEB setup failed");
4371                         return NULL;
4372                 }
4373                 /* set ALLOWLOOPBACk on pf, when veb is created */
4374                 i40e_enable_pf_lb(pf);
4375         }
4376
4377         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4378             pf->main_vsi->floating_veb == NULL) {
4379                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4380
4381                 if (pf->main_vsi->floating_veb == NULL) {
4382                         PMD_DRV_LOG(ERR, "VEB setup failed");
4383                         return NULL;
4384                 }
4385         }
4386
4387         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4388         if (!vsi) {
4389                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4390                 return NULL;
4391         }
4392         TAILQ_INIT(&vsi->mac_list);
4393         vsi->type = type;
4394         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4395         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4396         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4397         vsi->user_param = user_param;
4398         /* Allocate queues */
4399         switch (vsi->type) {
4400         case I40E_VSI_MAIN  :
4401                 vsi->nb_qps = pf->lan_nb_qps;
4402                 break;
4403         case I40E_VSI_SRIOV :
4404                 vsi->nb_qps = pf->vf_nb_qps;
4405                 break;
4406         case I40E_VSI_VMDQ2:
4407                 vsi->nb_qps = pf->vmdq_nb_qps;
4408                 break;
4409         case I40E_VSI_FDIR:
4410                 vsi->nb_qps = pf->fdir_nb_qps;
4411                 break;
4412         default:
4413                 goto fail_mem;
4414         }
4415         /*
4416          * The filter status descriptor is reported in rx queue 0,
4417          * while the tx queue for fdir filter programming has no
4418          * such constraints, can be non-zero queues.
4419          * To simplify it, choose FDIR vsi use queue 0 pair.
4420          * To make sure it will use queue 0 pair, queue allocation
4421          * need be done before this function is called
4422          */
4423         if (type != I40E_VSI_FDIR) {
4424                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4425                         if (ret < 0) {
4426                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4427                                                 vsi->seid, ret);
4428                                 goto fail_mem;
4429                         }
4430                         vsi->base_queue = ret;
4431         } else
4432                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4433
4434         /* VF has MSIX interrupt in VF range, don't allocate here */
4435         if (type == I40E_VSI_MAIN) {
4436                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4437                                           RTE_MIN(vsi->nb_qps,
4438                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4439                 if (ret < 0) {
4440                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4441                                     vsi->seid, ret);
4442                         goto fail_queue_alloc;
4443                 }
4444                 vsi->msix_intr = ret;
4445                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4446         } else if (type != I40E_VSI_SRIOV) {
4447                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4448                 if (ret < 0) {
4449                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4450                         goto fail_queue_alloc;
4451                 }
4452                 vsi->msix_intr = ret;
4453                 vsi->nb_msix = 1;
4454         } else {
4455                 vsi->msix_intr = 0;
4456                 vsi->nb_msix = 0;
4457         }
4458
4459         /* Add VSI */
4460         if (type == I40E_VSI_MAIN) {
4461                 /* For main VSI, no need to add since it's default one */
4462                 vsi->uplink_seid = pf->mac_seid;
4463                 vsi->seid = pf->main_vsi_seid;
4464                 /* Bind queues with specific MSIX interrupt */
4465                 /**
4466                  * Needs 2 interrupt at least, one for misc cause which will
4467                  * enabled from OS side, Another for queues binding the
4468                  * interrupt from device side only.
4469                  */
4470
4471                 /* Get default VSI parameters from hardware */
4472                 memset(&ctxt, 0, sizeof(ctxt));
4473                 ctxt.seid = vsi->seid;
4474                 ctxt.pf_num = hw->pf_id;
4475                 ctxt.uplink_seid = vsi->uplink_seid;
4476                 ctxt.vf_num = 0;
4477                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4478                 if (ret != I40E_SUCCESS) {
4479                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4480                         goto fail_msix_alloc;
4481                 }
4482                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4483                         sizeof(struct i40e_aqc_vsi_properties_data));
4484                 vsi->vsi_id = ctxt.vsi_number;
4485                 vsi->info.valid_sections = 0;
4486
4487                 /* Configure tc, enabled TC0 only */
4488                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4489                         I40E_SUCCESS) {
4490                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4491                         goto fail_msix_alloc;
4492                 }
4493
4494                 /* TC, queue mapping */
4495                 memset(&ctxt, 0, sizeof(ctxt));
4496                 vsi->info.valid_sections |=
4497                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4498                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4499                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4500                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4501                         sizeof(struct i40e_aqc_vsi_properties_data));
4502                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4503                                                 I40E_DEFAULT_TCMAP);
4504                 if (ret != I40E_SUCCESS) {
4505                         PMD_DRV_LOG(ERR, "Failed to configure "
4506                                     "TC queue mapping");
4507                         goto fail_msix_alloc;
4508                 }
4509                 ctxt.seid = vsi->seid;
4510                 ctxt.pf_num = hw->pf_id;
4511                 ctxt.uplink_seid = vsi->uplink_seid;
4512                 ctxt.vf_num = 0;
4513
4514                 /* Update VSI parameters */
4515                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4516                 if (ret != I40E_SUCCESS) {
4517                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4518                         goto fail_msix_alloc;
4519                 }
4520
4521                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4522                                                 sizeof(vsi->info.tc_mapping));
4523                 (void)rte_memcpy(&vsi->info.queue_mapping,
4524                                 &ctxt.info.queue_mapping,
4525                         sizeof(vsi->info.queue_mapping));
4526                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4527                 vsi->info.valid_sections = 0;
4528
4529                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4530                                 ETH_ADDR_LEN);
4531
4532                 /**
4533                  * Updating default filter settings are necessary to prevent
4534                  * reception of tagged packets.
4535                  * Some old firmware configurations load a default macvlan
4536                  * filter which accepts both tagged and untagged packets.
4537                  * The updating is to use a normal filter instead if needed.
4538                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4539                  * The firmware with correct configurations load the default
4540                  * macvlan filter which is expected and cannot be removed.
4541                  */
4542                 i40e_update_default_filter_setting(vsi);
4543                 i40e_config_qinq(hw, vsi);
4544         } else if (type == I40E_VSI_SRIOV) {
4545                 memset(&ctxt, 0, sizeof(ctxt));
4546                 /**
4547                  * For other VSI, the uplink_seid equals to uplink VSI's
4548                  * uplink_seid since they share same VEB
4549                  */
4550                 if (uplink_vsi == NULL)
4551                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4552                 else
4553                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4554                 ctxt.pf_num = hw->pf_id;
4555                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4556                 ctxt.uplink_seid = vsi->uplink_seid;
4557                 ctxt.connection_type = 0x1;
4558                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4559
4560                 /* Use the VEB configuration if FW >= v5.0 */
4561                 if (hw->aq.fw_maj_ver >= 5) {
4562                         /* Configure switch ID */
4563                         ctxt.info.valid_sections |=
4564                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4565                         ctxt.info.switch_id =
4566                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4567                 }
4568
4569                 /* Configure port/vlan */
4570                 ctxt.info.valid_sections |=
4571                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4572                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4573                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4574                                                 I40E_DEFAULT_TCMAP);
4575                 if (ret != I40E_SUCCESS) {
4576                         PMD_DRV_LOG(ERR, "Failed to configure "
4577                                     "TC queue mapping");
4578                         goto fail_msix_alloc;
4579                 }
4580                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4581                 ctxt.info.valid_sections |=
4582                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4583                 /**
4584                  * Since VSI is not created yet, only configure parameter,
4585                  * will add vsi below.
4586                  */
4587
4588                 i40e_config_qinq(hw, vsi);
4589         } else if (type == I40E_VSI_VMDQ2) {
4590                 memset(&ctxt, 0, sizeof(ctxt));
4591                 /*
4592                  * For other VSI, the uplink_seid equals to uplink VSI's
4593                  * uplink_seid since they share same VEB
4594                  */
4595                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4596                 ctxt.pf_num = hw->pf_id;
4597                 ctxt.vf_num = 0;
4598                 ctxt.uplink_seid = vsi->uplink_seid;
4599                 ctxt.connection_type = 0x1;
4600                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4601
4602                 ctxt.info.valid_sections |=
4603                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4604                 /* user_param carries flag to enable loop back */
4605                 if (user_param) {
4606                         ctxt.info.switch_id =
4607                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4608                         ctxt.info.switch_id |=
4609                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4610                 }
4611
4612                 /* Configure port/vlan */
4613                 ctxt.info.valid_sections |=
4614                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4615                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4616                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4617                                                 I40E_DEFAULT_TCMAP);
4618                 if (ret != I40E_SUCCESS) {
4619                         PMD_DRV_LOG(ERR, "Failed to configure "
4620                                         "TC queue mapping");
4621                         goto fail_msix_alloc;
4622                 }
4623                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4624                 ctxt.info.valid_sections |=
4625                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4626         } else if (type == I40E_VSI_FDIR) {
4627                 memset(&ctxt, 0, sizeof(ctxt));
4628                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4629                 ctxt.pf_num = hw->pf_id;
4630                 ctxt.vf_num = 0;
4631                 ctxt.uplink_seid = vsi->uplink_seid;
4632                 ctxt.connection_type = 0x1;     /* regular data port */
4633                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4634                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4635                                                 I40E_DEFAULT_TCMAP);
4636                 if (ret != I40E_SUCCESS) {
4637                         PMD_DRV_LOG(ERR, "Failed to configure "
4638                                         "TC queue mapping.");
4639                         goto fail_msix_alloc;
4640                 }
4641                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4642                 ctxt.info.valid_sections |=
4643                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4644         } else {
4645                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4646                 goto fail_msix_alloc;
4647         }
4648
4649         if (vsi->type != I40E_VSI_MAIN) {
4650                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4651                 if (ret != I40E_SUCCESS) {
4652                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4653                                     hw->aq.asq_last_status);
4654                         goto fail_msix_alloc;
4655                 }
4656                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4657                 vsi->info.valid_sections = 0;
4658                 vsi->seid = ctxt.seid;
4659                 vsi->vsi_id = ctxt.vsi_number;
4660                 vsi->sib_vsi_list.vsi = vsi;
4661                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4662                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4663                                           &vsi->sib_vsi_list, list);
4664                 } else {
4665                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4666                                           &vsi->sib_vsi_list, list);
4667                 }
4668         }
4669
4670         /* MAC/VLAN configuration */
4671         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4672         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4673
4674         ret = i40e_vsi_add_mac(vsi, &filter);
4675         if (ret != I40E_SUCCESS) {
4676                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4677                 goto fail_msix_alloc;
4678         }
4679
4680         /* Get VSI BW information */
4681         i40e_vsi_get_bw_config(vsi);
4682         return vsi;
4683 fail_msix_alloc:
4684         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4685 fail_queue_alloc:
4686         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4687 fail_mem:
4688         rte_free(vsi);
4689         return NULL;
4690 }
4691
4692 /* Configure vlan filter on or off */
4693 int
4694 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4695 {
4696         int i, num;
4697         struct i40e_mac_filter *f;
4698         void *temp;
4699         struct i40e_mac_filter_info *mac_filter;
4700         enum rte_mac_filter_type desired_filter;
4701         int ret = I40E_SUCCESS;
4702
4703         if (on) {
4704                 /* Filter to match MAC and VLAN */
4705                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4706         } else {
4707                 /* Filter to match only MAC */
4708                 desired_filter = RTE_MAC_PERFECT_MATCH;
4709         }
4710
4711         num = vsi->mac_num;
4712
4713         mac_filter = rte_zmalloc("mac_filter_info_data",
4714                                  num * sizeof(*mac_filter), 0);
4715         if (mac_filter == NULL) {
4716                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4717                 return I40E_ERR_NO_MEMORY;
4718         }
4719
4720         i = 0;
4721
4722         /* Remove all existing mac */
4723         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4724                 mac_filter[i] = f->mac_info;
4725                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4726                 if (ret) {
4727                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4728                                     on ? "enable" : "disable");
4729                         goto DONE;
4730                 }
4731                 i++;
4732         }
4733
4734         /* Override with new filter */
4735         for (i = 0; i < num; i++) {
4736                 mac_filter[i].filter_type = desired_filter;
4737                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4738                 if (ret) {
4739                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4740                                     on ? "enable" : "disable");
4741                         goto DONE;
4742                 }
4743         }
4744
4745 DONE:
4746         rte_free(mac_filter);
4747         return ret;
4748 }
4749
4750 /* Configure vlan stripping on or off */
4751 int
4752 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4753 {
4754         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4755         struct i40e_vsi_context ctxt;
4756         uint8_t vlan_flags;
4757         int ret = I40E_SUCCESS;
4758
4759         /* Check if it has been already on or off */
4760         if (vsi->info.valid_sections &
4761                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4762                 if (on) {
4763                         if ((vsi->info.port_vlan_flags &
4764                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4765                                 return 0; /* already on */
4766                 } else {
4767                         if ((vsi->info.port_vlan_flags &
4768                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4769                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4770                                 return 0; /* already off */
4771                 }
4772         }
4773
4774         if (on)
4775                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4776         else
4777                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4778         vsi->info.valid_sections =
4779                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4780         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4781         vsi->info.port_vlan_flags |= vlan_flags;
4782         ctxt.seid = vsi->seid;
4783         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4784         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4785         if (ret)
4786                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4787                             on ? "enable" : "disable");
4788
4789         return ret;
4790 }
4791
4792 static int
4793 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4794 {
4795         struct rte_eth_dev_data *data = dev->data;
4796         int ret;
4797         int mask = 0;
4798
4799         /* Apply vlan offload setting */
4800         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4801         i40e_vlan_offload_set(dev, mask);
4802
4803         /* Apply double-vlan setting, not implemented yet */
4804
4805         /* Apply pvid setting */
4806         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4807                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4808         if (ret)
4809                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4810
4811         return ret;
4812 }
4813
4814 static int
4815 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4816 {
4817         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4818
4819         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4820 }
4821
4822 static int
4823 i40e_update_flow_control(struct i40e_hw *hw)
4824 {
4825 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4826         struct i40e_link_status link_status;
4827         uint32_t rxfc = 0, txfc = 0, reg;
4828         uint8_t an_info;
4829         int ret;
4830
4831         memset(&link_status, 0, sizeof(link_status));
4832         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4833         if (ret != I40E_SUCCESS) {
4834                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4835                 goto write_reg; /* Disable flow control */
4836         }
4837
4838         an_info = hw->phy.link_info.an_info;
4839         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4840                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4841                 ret = I40E_ERR_NOT_READY;
4842                 goto write_reg; /* Disable flow control */
4843         }
4844         /**
4845          * If link auto negotiation is enabled, flow control needs to
4846          * be configured according to it
4847          */
4848         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4849         case I40E_LINK_PAUSE_RXTX:
4850                 rxfc = 1;
4851                 txfc = 1;
4852                 hw->fc.current_mode = I40E_FC_FULL;
4853                 break;
4854         case I40E_AQ_LINK_PAUSE_RX:
4855                 rxfc = 1;
4856                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4857                 break;
4858         case I40E_AQ_LINK_PAUSE_TX:
4859                 txfc = 1;
4860                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4861                 break;
4862         default:
4863                 hw->fc.current_mode = I40E_FC_NONE;
4864                 break;
4865         }
4866
4867 write_reg:
4868         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4869                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4870         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4871         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4872         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4873         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4874
4875         return ret;
4876 }
4877
4878 /* PF setup */
4879 static int
4880 i40e_pf_setup(struct i40e_pf *pf)
4881 {
4882         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4883         struct i40e_filter_control_settings settings;
4884         struct i40e_vsi *vsi;
4885         int ret;
4886
4887         /* Clear all stats counters */
4888         pf->offset_loaded = FALSE;
4889         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4890         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4891
4892         ret = i40e_pf_get_switch_config(pf);
4893         if (ret != I40E_SUCCESS) {
4894                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4895                 return ret;
4896         }
4897         if (pf->flags & I40E_FLAG_FDIR) {
4898                 /* make queue allocated first, let FDIR use queue pair 0*/
4899                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4900                 if (ret != I40E_FDIR_QUEUE_ID) {
4901                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4902                                     " ret =%d", ret);
4903                         pf->flags &= ~I40E_FLAG_FDIR;
4904                 }
4905         }
4906         /*  main VSI setup */
4907         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4908         if (!vsi) {
4909                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4910                 return I40E_ERR_NOT_READY;
4911         }
4912         pf->main_vsi = vsi;
4913
4914         /* Configure filter control */
4915         memset(&settings, 0, sizeof(settings));
4916         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4917                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4918         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4919                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4920         else {
4921                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4922                                                 hw->func_caps.rss_table_size);
4923                 return I40E_ERR_PARAM;
4924         }
4925         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4926                         "size: %u\n", hw->func_caps.rss_table_size);
4927         pf->hash_lut_size = hw->func_caps.rss_table_size;
4928
4929         /* Enable ethtype and macvlan filters */
4930         settings.enable_ethtype = TRUE;
4931         settings.enable_macvlan = TRUE;
4932         ret = i40e_set_filter_control(hw, &settings);
4933         if (ret)
4934                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4935                                                                 ret);
4936
4937         /* Update flow control according to the auto negotiation */
4938         i40e_update_flow_control(hw);
4939
4940         return I40E_SUCCESS;
4941 }
4942
4943 int
4944 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4945 {
4946         uint32_t reg;
4947         uint16_t j;
4948
4949         /**
4950          * Set or clear TX Queue Disable flags,
4951          * which is required by hardware.
4952          */
4953         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4954         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4955
4956         /* Wait until the request is finished */
4957         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4958                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4959                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4960                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4961                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4962                                                         & 0x1))) {
4963                         break;
4964                 }
4965         }
4966         if (on) {
4967                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4968                         return I40E_SUCCESS; /* already on, skip next steps */
4969
4970                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4971                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4972         } else {
4973                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4974                         return I40E_SUCCESS; /* already off, skip next steps */
4975                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4976         }
4977         /* Write the register */
4978         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4979         /* Check the result */
4980         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4981                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4982                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4983                 if (on) {
4984                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4985                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4986                                 break;
4987                 } else {
4988                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4989                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4990                                 break;
4991                 }
4992         }
4993         /* Check if it is timeout */
4994         if (j >= I40E_CHK_Q_ENA_COUNT) {
4995                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4996                             (on ? "enable" : "disable"), q_idx);
4997                 return I40E_ERR_TIMEOUT;
4998         }
4999
5000         return I40E_SUCCESS;
5001 }
5002
5003 /* Swith on or off the tx queues */
5004 static int
5005 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5006 {
5007         struct rte_eth_dev_data *dev_data = pf->dev_data;
5008         struct i40e_tx_queue *txq;
5009         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5010         uint16_t i;
5011         int ret;
5012
5013         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5014                 txq = dev_data->tx_queues[i];
5015                 /* Don't operate the queue if not configured or
5016                  * if starting only per queue */
5017                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5018                         continue;
5019                 if (on)
5020                         ret = i40e_dev_tx_queue_start(dev, i);
5021                 else
5022                         ret = i40e_dev_tx_queue_stop(dev, i);
5023                 if ( ret != I40E_SUCCESS)
5024                         return ret;
5025         }
5026
5027         return I40E_SUCCESS;
5028 }
5029
5030 int
5031 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5032 {
5033         uint32_t reg;
5034         uint16_t j;
5035
5036         /* Wait until the request is finished */
5037         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5038                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5039                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5040                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5041                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5042                         break;
5043         }
5044
5045         if (on) {
5046                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5047                         return I40E_SUCCESS; /* Already on, skip next steps */
5048                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5049         } else {
5050                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5051                         return I40E_SUCCESS; /* Already off, skip next steps */
5052                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5053         }
5054
5055         /* Write the register */
5056         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5057         /* Check the result */
5058         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5059                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5060                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5061                 if (on) {
5062                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5063                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5064                                 break;
5065                 } else {
5066                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5067                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5068                                 break;
5069                 }
5070         }
5071
5072         /* Check if it is timeout */
5073         if (j >= I40E_CHK_Q_ENA_COUNT) {
5074                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5075                             (on ? "enable" : "disable"), q_idx);
5076                 return I40E_ERR_TIMEOUT;
5077         }
5078
5079         return I40E_SUCCESS;
5080 }
5081 /* Switch on or off the rx queues */
5082 static int
5083 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5084 {
5085         struct rte_eth_dev_data *dev_data = pf->dev_data;
5086         struct i40e_rx_queue *rxq;
5087         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5088         uint16_t i;
5089         int ret;
5090
5091         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5092                 rxq = dev_data->rx_queues[i];
5093                 /* Don't operate the queue if not configured or
5094                  * if starting only per queue */
5095                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5096                         continue;
5097                 if (on)
5098                         ret = i40e_dev_rx_queue_start(dev, i);
5099                 else
5100                         ret = i40e_dev_rx_queue_stop(dev, i);
5101                 if (ret != I40E_SUCCESS)
5102                         return ret;
5103         }
5104
5105         return I40E_SUCCESS;
5106 }
5107
5108 /* Switch on or off all the rx/tx queues */
5109 int
5110 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5111 {
5112         int ret;
5113
5114         if (on) {
5115                 /* enable rx queues before enabling tx queues */
5116                 ret = i40e_dev_switch_rx_queues(pf, on);
5117                 if (ret) {
5118                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5119                         return ret;
5120                 }
5121                 ret = i40e_dev_switch_tx_queues(pf, on);
5122         } else {
5123                 /* Stop tx queues before stopping rx queues */
5124                 ret = i40e_dev_switch_tx_queues(pf, on);
5125                 if (ret) {
5126                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5127                         return ret;
5128                 }
5129                 ret = i40e_dev_switch_rx_queues(pf, on);
5130         }
5131
5132         return ret;
5133 }
5134
5135 /* Initialize VSI for TX */
5136 static int
5137 i40e_dev_tx_init(struct i40e_pf *pf)
5138 {
5139         struct rte_eth_dev_data *data = pf->dev_data;
5140         uint16_t i;
5141         uint32_t ret = I40E_SUCCESS;
5142         struct i40e_tx_queue *txq;
5143
5144         for (i = 0; i < data->nb_tx_queues; i++) {
5145                 txq = data->tx_queues[i];
5146                 if (!txq || !txq->q_set)
5147                         continue;
5148                 ret = i40e_tx_queue_init(txq);
5149                 if (ret != I40E_SUCCESS)
5150                         break;
5151         }
5152         if (ret == I40E_SUCCESS)
5153                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5154                                      ->eth_dev);
5155
5156         return ret;
5157 }
5158
5159 /* Initialize VSI for RX */
5160 static int
5161 i40e_dev_rx_init(struct i40e_pf *pf)
5162 {
5163         struct rte_eth_dev_data *data = pf->dev_data;
5164         int ret = I40E_SUCCESS;
5165         uint16_t i;
5166         struct i40e_rx_queue *rxq;
5167
5168         i40e_pf_config_mq_rx(pf);
5169         for (i = 0; i < data->nb_rx_queues; i++) {
5170                 rxq = data->rx_queues[i];
5171                 if (!rxq || !rxq->q_set)
5172                         continue;
5173
5174                 ret = i40e_rx_queue_init(rxq);
5175                 if (ret != I40E_SUCCESS) {
5176                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5177                                     "initialization");
5178                         break;
5179                 }
5180         }
5181         if (ret == I40E_SUCCESS)
5182                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5183                                      ->eth_dev);
5184
5185         return ret;
5186 }
5187
5188 static int
5189 i40e_dev_rxtx_init(struct i40e_pf *pf)
5190 {
5191         int err;
5192
5193         err = i40e_dev_tx_init(pf);
5194         if (err) {
5195                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5196                 return err;
5197         }
5198         err = i40e_dev_rx_init(pf);
5199         if (err) {
5200                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5201                 return err;
5202         }
5203
5204         return err;
5205 }
5206
5207 static int
5208 i40e_vmdq_setup(struct rte_eth_dev *dev)
5209 {
5210         struct rte_eth_conf *conf = &dev->data->dev_conf;
5211         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5212         int i, err, conf_vsis, j, loop;
5213         struct i40e_vsi *vsi;
5214         struct i40e_vmdq_info *vmdq_info;
5215         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5216         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5217
5218         /*
5219          * Disable interrupt to avoid message from VF. Furthermore, it will
5220          * avoid race condition in VSI creation/destroy.
5221          */
5222         i40e_pf_disable_irq0(hw);
5223
5224         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5225                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5226                 return -ENOTSUP;
5227         }
5228
5229         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5230         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5231                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5232                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5233                         pf->max_nb_vmdq_vsi);
5234                 return -ENOTSUP;
5235         }
5236
5237         if (pf->vmdq != NULL) {
5238                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5239                 return 0;
5240         }
5241
5242         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5243                                 sizeof(*vmdq_info) * conf_vsis, 0);
5244
5245         if (pf->vmdq == NULL) {
5246                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5247                 return -ENOMEM;
5248         }
5249
5250         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5251
5252         /* Create VMDQ VSI */
5253         for (i = 0; i < conf_vsis; i++) {
5254                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5255                                 vmdq_conf->enable_loop_back);
5256                 if (vsi == NULL) {
5257                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5258                         err = -1;
5259                         goto err_vsi_setup;
5260                 }
5261                 vmdq_info = &pf->vmdq[i];
5262                 vmdq_info->pf = pf;
5263                 vmdq_info->vsi = vsi;
5264         }
5265         pf->nb_cfg_vmdq_vsi = conf_vsis;
5266
5267         /* Configure Vlan */
5268         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5269         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5270                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5271                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5272                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5273                                         vmdq_conf->pool_map[i].vlan_id, j);
5274
5275                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5276                                                 vmdq_conf->pool_map[i].vlan_id);
5277                                 if (err) {
5278                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5279                                         err = -1;
5280                                         goto err_vsi_setup;
5281                                 }
5282                         }
5283                 }
5284         }
5285
5286         i40e_pf_enable_irq0(hw);
5287
5288         return 0;
5289
5290 err_vsi_setup:
5291         for (i = 0; i < conf_vsis; i++)
5292                 if (pf->vmdq[i].vsi == NULL)
5293                         break;
5294                 else
5295                         i40e_vsi_release(pf->vmdq[i].vsi);
5296
5297         rte_free(pf->vmdq);
5298         pf->vmdq = NULL;
5299         i40e_pf_enable_irq0(hw);
5300         return err;
5301 }
5302
5303 static void
5304 i40e_stat_update_32(struct i40e_hw *hw,
5305                    uint32_t reg,
5306                    bool offset_loaded,
5307                    uint64_t *offset,
5308                    uint64_t *stat)
5309 {
5310         uint64_t new_data;
5311
5312         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5313         if (!offset_loaded)
5314                 *offset = new_data;
5315
5316         if (new_data >= *offset)
5317                 *stat = (uint64_t)(new_data - *offset);
5318         else
5319                 *stat = (uint64_t)((new_data +
5320                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5321 }
5322
5323 static void
5324 i40e_stat_update_48(struct i40e_hw *hw,
5325                    uint32_t hireg,
5326                    uint32_t loreg,
5327                    bool offset_loaded,
5328                    uint64_t *offset,
5329                    uint64_t *stat)
5330 {
5331         uint64_t new_data;
5332
5333         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5334         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5335                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5336
5337         if (!offset_loaded)
5338                 *offset = new_data;
5339
5340         if (new_data >= *offset)
5341                 *stat = new_data - *offset;
5342         else
5343                 *stat = (uint64_t)((new_data +
5344                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5345
5346         *stat &= I40E_48_BIT_MASK;
5347 }
5348
5349 /* Disable IRQ0 */
5350 void
5351 i40e_pf_disable_irq0(struct i40e_hw *hw)
5352 {
5353         /* Disable all interrupt types */
5354         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5355         I40E_WRITE_FLUSH(hw);
5356 }
5357
5358 /* Enable IRQ0 */
5359 void
5360 i40e_pf_enable_irq0(struct i40e_hw *hw)
5361 {
5362         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5363                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5364                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5365                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5366         I40E_WRITE_FLUSH(hw);
5367 }
5368
5369 static void
5370 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5371 {
5372         /* read pending request and disable first */
5373         i40e_pf_disable_irq0(hw);
5374         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5375         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5376                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5377
5378         if (no_queue)
5379                 /* Link no queues with irq0 */
5380                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5381                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5382 }
5383
5384 static void
5385 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5386 {
5387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5388         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5389         int i;
5390         uint16_t abs_vf_id;
5391         uint32_t index, offset, val;
5392
5393         if (!pf->vfs)
5394                 return;
5395         /**
5396          * Try to find which VF trigger a reset, use absolute VF id to access
5397          * since the reg is global register.
5398          */
5399         for (i = 0; i < pf->vf_num; i++) {
5400                 abs_vf_id = hw->func_caps.vf_base_id + i;
5401                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5402                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5403                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5404                 /* VFR event occured */
5405                 if (val & (0x1 << offset)) {
5406                         int ret;
5407
5408                         /* Clear the event first */
5409                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5410                                                         (0x1 << offset));
5411                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5412                         /**
5413                          * Only notify a VF reset event occured,
5414                          * don't trigger another SW reset
5415                          */
5416                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5417                         if (ret != I40E_SUCCESS)
5418                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5419                 }
5420         }
5421 }
5422
5423 static void
5424 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5425 {
5426         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5427         struct i40e_arq_event_info info;
5428         uint16_t pending, opcode;
5429         int ret;
5430
5431         info.buf_len = I40E_AQ_BUF_SZ;
5432         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5433         if (!info.msg_buf) {
5434                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5435                 return;
5436         }
5437
5438         pending = 1;
5439         while (pending) {
5440                 ret = i40e_clean_arq_element(hw, &info, &pending);
5441
5442                 if (ret != I40E_SUCCESS) {
5443                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5444                                     "aq_err: %u", hw->aq.asq_last_status);
5445                         break;
5446                 }
5447                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5448
5449                 switch (opcode) {
5450                 case i40e_aqc_opc_send_msg_to_pf:
5451                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5452                         i40e_pf_host_handle_vf_msg(dev,
5453                                         rte_le_to_cpu_16(info.desc.retval),
5454                                         rte_le_to_cpu_32(info.desc.cookie_high),
5455                                         rte_le_to_cpu_32(info.desc.cookie_low),
5456                                         info.msg_buf,
5457                                         info.msg_len);
5458                         break;
5459                 default:
5460                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5461                                     opcode);
5462                         break;
5463                 }
5464         }
5465         rte_free(info.msg_buf);
5466 }
5467
5468 /*
5469  * Interrupt handler is registered as the alarm callback for handling LSC
5470  * interrupt in a definite of time, in order to wait the NIC into a stable
5471  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5472  * no need for link down interrupt.
5473  */
5474 static void
5475 i40e_dev_interrupt_delayed_handler(void *param)
5476 {
5477         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5479         uint32_t icr0;
5480
5481         /* read interrupt causes again */
5482         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5483
5484 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5485         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5486                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5487         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5488                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5489         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5490                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5491         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5492                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5493         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5494                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5495                                                                 "state\n");
5496         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5497                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5498         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5499                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5500 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5501
5502         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5503                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5504                 i40e_dev_handle_vfr_event(dev);
5505         }
5506         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5507                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5508                 i40e_dev_handle_aq_msg(dev);
5509         }
5510
5511         /* handle the link up interrupt in an alarm callback */
5512         i40e_dev_link_update(dev, 0);
5513         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5514
5515         i40e_pf_enable_irq0(hw);
5516         rte_intr_enable(&(dev->pci_dev->intr_handle));
5517 }
5518
5519 /**
5520  * Interrupt handler triggered by NIC  for handling
5521  * specific interrupt.
5522  *
5523  * @param handle
5524  *  Pointer to interrupt handle.
5525  * @param param
5526  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5527  *
5528  * @return
5529  *  void
5530  */
5531 static void
5532 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5533                            void *param)
5534 {
5535         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5536         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5537         uint32_t icr0;
5538
5539         /* Disable interrupt */
5540         i40e_pf_disable_irq0(hw);
5541
5542         /* read out interrupt causes */
5543         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5544
5545         /* No interrupt event indicated */
5546         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5547                 PMD_DRV_LOG(INFO, "No interrupt event");
5548                 goto done;
5549         }
5550 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5551         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5552                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5553         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5554                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5555         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5556                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5557         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5558                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5559         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5560                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5561         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5562                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5563         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5564                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5565 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5566
5567         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5568                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5569                 i40e_dev_handle_vfr_event(dev);
5570         }
5571         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5572                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5573                 i40e_dev_handle_aq_msg(dev);
5574         }
5575
5576         /* Link Status Change interrupt */
5577         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5578 #define I40E_US_PER_SECOND 1000000
5579                 struct rte_eth_link link;
5580
5581                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5582                 memset(&link, 0, sizeof(link));
5583                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5584                 i40e_dev_link_update(dev, 0);
5585
5586                 /*
5587                  * For link up interrupt, it needs to wait 1 second to let the
5588                  * hardware be a stable state. Otherwise several consecutive
5589                  * interrupts can be observed.
5590                  * For link down interrupt, no need to wait.
5591                  */
5592                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5593                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5594                         return;
5595                 else
5596                         _rte_eth_dev_callback_process(dev,
5597                                 RTE_ETH_EVENT_INTR_LSC);
5598         }
5599
5600 done:
5601         /* Enable interrupt */
5602         i40e_pf_enable_irq0(hw);
5603         rte_intr_enable(&(dev->pci_dev->intr_handle));
5604 }
5605
5606 static int
5607 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5608                          struct i40e_macvlan_filter *filter,
5609                          int total)
5610 {
5611         int ele_num, ele_buff_size;
5612         int num, actual_num, i;
5613         uint16_t flags;
5614         int ret = I40E_SUCCESS;
5615         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5616         struct i40e_aqc_add_macvlan_element_data *req_list;
5617
5618         if (filter == NULL  || total == 0)
5619                 return I40E_ERR_PARAM;
5620         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5621         ele_buff_size = hw->aq.asq_buf_size;
5622
5623         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5624         if (req_list == NULL) {
5625                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5626                 return I40E_ERR_NO_MEMORY;
5627         }
5628
5629         num = 0;
5630         do {
5631                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5632                 memset(req_list, 0, ele_buff_size);
5633
5634                 for (i = 0; i < actual_num; i++) {
5635                         (void)rte_memcpy(req_list[i].mac_addr,
5636                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5637                         req_list[i].vlan_tag =
5638                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5639
5640                         switch (filter[num + i].filter_type) {
5641                         case RTE_MAC_PERFECT_MATCH:
5642                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5643                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5644                                 break;
5645                         case RTE_MACVLAN_PERFECT_MATCH:
5646                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5647                                 break;
5648                         case RTE_MAC_HASH_MATCH:
5649                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5650                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5651                                 break;
5652                         case RTE_MACVLAN_HASH_MATCH:
5653                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5654                                 break;
5655                         default:
5656                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5657                                 ret = I40E_ERR_PARAM;
5658                                 goto DONE;
5659                         }
5660
5661                         req_list[i].queue_number = 0;
5662
5663                         req_list[i].flags = rte_cpu_to_le_16(flags);
5664                 }
5665
5666                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5667                                                 actual_num, NULL);
5668                 if (ret != I40E_SUCCESS) {
5669                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5670                         goto DONE;
5671                 }
5672                 num += actual_num;
5673         } while (num < total);
5674
5675 DONE:
5676         rte_free(req_list);
5677         return ret;
5678 }
5679
5680 static int
5681 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5682                             struct i40e_macvlan_filter *filter,
5683                             int total)
5684 {
5685         int ele_num, ele_buff_size;
5686         int num, actual_num, i;
5687         uint16_t flags;
5688         int ret = I40E_SUCCESS;
5689         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5690         struct i40e_aqc_remove_macvlan_element_data *req_list;
5691
5692         if (filter == NULL  || total == 0)
5693                 return I40E_ERR_PARAM;
5694
5695         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5696         ele_buff_size = hw->aq.asq_buf_size;
5697
5698         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5699         if (req_list == NULL) {
5700                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5701                 return I40E_ERR_NO_MEMORY;
5702         }
5703
5704         num = 0;
5705         do {
5706                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5707                 memset(req_list, 0, ele_buff_size);
5708
5709                 for (i = 0; i < actual_num; i++) {
5710                         (void)rte_memcpy(req_list[i].mac_addr,
5711                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5712                         req_list[i].vlan_tag =
5713                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5714
5715                         switch (filter[num + i].filter_type) {
5716                         case RTE_MAC_PERFECT_MATCH:
5717                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5718                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5719                                 break;
5720                         case RTE_MACVLAN_PERFECT_MATCH:
5721                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5722                                 break;
5723                         case RTE_MAC_HASH_MATCH:
5724                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5725                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5726                                 break;
5727                         case RTE_MACVLAN_HASH_MATCH:
5728                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5729                                 break;
5730                         default:
5731                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5732                                 ret = I40E_ERR_PARAM;
5733                                 goto DONE;
5734                         }
5735                         req_list[i].flags = rte_cpu_to_le_16(flags);
5736                 }
5737
5738                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5739                                                 actual_num, NULL);
5740                 if (ret != I40E_SUCCESS) {
5741                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5742                         goto DONE;
5743                 }
5744                 num += actual_num;
5745         } while (num < total);
5746
5747 DONE:
5748         rte_free(req_list);
5749         return ret;
5750 }
5751
5752 /* Find out specific MAC filter */
5753 static struct i40e_mac_filter *
5754 i40e_find_mac_filter(struct i40e_vsi *vsi,
5755                          struct ether_addr *macaddr)
5756 {
5757         struct i40e_mac_filter *f;
5758
5759         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5760                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5761                         return f;
5762         }
5763
5764         return NULL;
5765 }
5766
5767 static bool
5768 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5769                          uint16_t vlan_id)
5770 {
5771         uint32_t vid_idx, vid_bit;
5772
5773         if (vlan_id > ETH_VLAN_ID_MAX)
5774                 return 0;
5775
5776         vid_idx = I40E_VFTA_IDX(vlan_id);
5777         vid_bit = I40E_VFTA_BIT(vlan_id);
5778
5779         if (vsi->vfta[vid_idx] & vid_bit)
5780                 return 1;
5781         else
5782                 return 0;
5783 }
5784
5785 static void
5786 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5787                          uint16_t vlan_id, bool on)
5788 {
5789         uint32_t vid_idx, vid_bit;
5790
5791         if (vlan_id > ETH_VLAN_ID_MAX)
5792                 return;
5793
5794         vid_idx = I40E_VFTA_IDX(vlan_id);
5795         vid_bit = I40E_VFTA_BIT(vlan_id);
5796
5797         if (on)
5798                 vsi->vfta[vid_idx] |= vid_bit;
5799         else
5800                 vsi->vfta[vid_idx] &= ~vid_bit;
5801 }
5802
5803 /**
5804  * Find all vlan options for specific mac addr,
5805  * return with actual vlan found.
5806  */
5807 static inline int
5808 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5809                            struct i40e_macvlan_filter *mv_f,
5810                            int num, struct ether_addr *addr)
5811 {
5812         int i;
5813         uint32_t j, k;
5814
5815         /**
5816          * Not to use i40e_find_vlan_filter to decrease the loop time,
5817          * although the code looks complex.
5818           */
5819         if (num < vsi->vlan_num)
5820                 return I40E_ERR_PARAM;
5821
5822         i = 0;
5823         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5824                 if (vsi->vfta[j]) {
5825                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5826                                 if (vsi->vfta[j] & (1 << k)) {
5827                                         if (i > num - 1) {
5828                                                 PMD_DRV_LOG(ERR, "vlan number "
5829                                                             "not match");
5830                                                 return I40E_ERR_PARAM;
5831                                         }
5832                                         (void)rte_memcpy(&mv_f[i].macaddr,
5833                                                         addr, ETH_ADDR_LEN);
5834                                         mv_f[i].vlan_id =
5835                                                 j * I40E_UINT32_BIT_SIZE + k;
5836                                         i++;
5837                                 }
5838                         }
5839                 }
5840         }
5841         return I40E_SUCCESS;
5842 }
5843
5844 static inline int
5845 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5846                            struct i40e_macvlan_filter *mv_f,
5847                            int num,
5848                            uint16_t vlan)
5849 {
5850         int i = 0;
5851         struct i40e_mac_filter *f;
5852
5853         if (num < vsi->mac_num)
5854                 return I40E_ERR_PARAM;
5855
5856         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5857                 if (i > num - 1) {
5858                         PMD_DRV_LOG(ERR, "buffer number not match");
5859                         return I40E_ERR_PARAM;
5860                 }
5861                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5862                                 ETH_ADDR_LEN);
5863                 mv_f[i].vlan_id = vlan;
5864                 mv_f[i].filter_type = f->mac_info.filter_type;
5865                 i++;
5866         }
5867
5868         return I40E_SUCCESS;
5869 }
5870
5871 static int
5872 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5873 {
5874         int i, num;
5875         struct i40e_mac_filter *f;
5876         struct i40e_macvlan_filter *mv_f;
5877         int ret = I40E_SUCCESS;
5878
5879         if (vsi == NULL || vsi->mac_num == 0)
5880                 return I40E_ERR_PARAM;
5881
5882         /* Case that no vlan is set */
5883         if (vsi->vlan_num == 0)
5884                 num = vsi->mac_num;
5885         else
5886                 num = vsi->mac_num * vsi->vlan_num;
5887
5888         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5889         if (mv_f == NULL) {
5890                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5891                 return I40E_ERR_NO_MEMORY;
5892         }
5893
5894         i = 0;
5895         if (vsi->vlan_num == 0) {
5896                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5897                         (void)rte_memcpy(&mv_f[i].macaddr,
5898                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5899                         mv_f[i].vlan_id = 0;
5900                         i++;
5901                 }
5902         } else {
5903                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5904                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5905                                         vsi->vlan_num, &f->mac_info.mac_addr);
5906                         if (ret != I40E_SUCCESS)
5907                                 goto DONE;
5908                         i += vsi->vlan_num;
5909                 }
5910         }
5911
5912         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5913 DONE:
5914         rte_free(mv_f);
5915
5916         return ret;
5917 }
5918
5919 int
5920 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5921 {
5922         struct i40e_macvlan_filter *mv_f;
5923         int mac_num;
5924         int ret = I40E_SUCCESS;
5925
5926         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5927                 return I40E_ERR_PARAM;
5928
5929         /* If it's already set, just return */
5930         if (i40e_find_vlan_filter(vsi,vlan))
5931                 return I40E_SUCCESS;
5932
5933         mac_num = vsi->mac_num;
5934
5935         if (mac_num == 0) {
5936                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5937                 return I40E_ERR_PARAM;
5938         }
5939
5940         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5941
5942         if (mv_f == NULL) {
5943                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5944                 return I40E_ERR_NO_MEMORY;
5945         }
5946
5947         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5948
5949         if (ret != I40E_SUCCESS)
5950                 goto DONE;
5951
5952         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5953
5954         if (ret != I40E_SUCCESS)
5955                 goto DONE;
5956
5957         i40e_set_vlan_filter(vsi, vlan, 1);
5958
5959         vsi->vlan_num++;
5960         ret = I40E_SUCCESS;
5961 DONE:
5962         rte_free(mv_f);
5963         return ret;
5964 }
5965
5966 int
5967 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5968 {
5969         struct i40e_macvlan_filter *mv_f;
5970         int mac_num;
5971         int ret = I40E_SUCCESS;
5972
5973         /**
5974          * Vlan 0 is the generic filter for untagged packets
5975          * and can't be removed.
5976          */
5977         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5978                 return I40E_ERR_PARAM;
5979
5980         /* If can't find it, just return */
5981         if (!i40e_find_vlan_filter(vsi, vlan))
5982                 return I40E_ERR_PARAM;
5983
5984         mac_num = vsi->mac_num;
5985
5986         if (mac_num == 0) {
5987                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5988                 return I40E_ERR_PARAM;
5989         }
5990
5991         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5992
5993         if (mv_f == NULL) {
5994                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5995                 return I40E_ERR_NO_MEMORY;
5996         }
5997
5998         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5999
6000         if (ret != I40E_SUCCESS)
6001                 goto DONE;
6002
6003         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6004
6005         if (ret != I40E_SUCCESS)
6006                 goto DONE;
6007
6008         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6009         if (vsi->vlan_num == 1) {
6010                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6011                 if (ret != I40E_SUCCESS)
6012                         goto DONE;
6013
6014                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6015                 if (ret != I40E_SUCCESS)
6016                         goto DONE;
6017         }
6018
6019         i40e_set_vlan_filter(vsi, vlan, 0);
6020
6021         vsi->vlan_num--;
6022         ret = I40E_SUCCESS;
6023 DONE:
6024         rte_free(mv_f);
6025         return ret;
6026 }
6027
6028 int
6029 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6030 {
6031         struct i40e_mac_filter *f;
6032         struct i40e_macvlan_filter *mv_f;
6033         int i, vlan_num = 0;
6034         int ret = I40E_SUCCESS;
6035
6036         /* If it's add and we've config it, return */
6037         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6038         if (f != NULL)
6039                 return I40E_SUCCESS;
6040         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6041                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6042
6043                 /**
6044                  * If vlan_num is 0, that's the first time to add mac,
6045                  * set mask for vlan_id 0.
6046                  */
6047                 if (vsi->vlan_num == 0) {
6048                         i40e_set_vlan_filter(vsi, 0, 1);
6049                         vsi->vlan_num = 1;
6050                 }
6051                 vlan_num = vsi->vlan_num;
6052         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6053                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6054                 vlan_num = 1;
6055
6056         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6057         if (mv_f == NULL) {
6058                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6059                 return I40E_ERR_NO_MEMORY;
6060         }
6061
6062         for (i = 0; i < vlan_num; i++) {
6063                 mv_f[i].filter_type = mac_filter->filter_type;
6064                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6065                                 ETH_ADDR_LEN);
6066         }
6067
6068         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6069                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6070                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6071                                         &mac_filter->mac_addr);
6072                 if (ret != I40E_SUCCESS)
6073                         goto DONE;
6074         }
6075
6076         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6077         if (ret != I40E_SUCCESS)
6078                 goto DONE;
6079
6080         /* Add the mac addr into mac list */
6081         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6082         if (f == NULL) {
6083                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6084                 ret = I40E_ERR_NO_MEMORY;
6085                 goto DONE;
6086         }
6087         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6088                         ETH_ADDR_LEN);
6089         f->mac_info.filter_type = mac_filter->filter_type;
6090         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6091         vsi->mac_num++;
6092
6093         ret = I40E_SUCCESS;
6094 DONE:
6095         rte_free(mv_f);
6096
6097         return ret;
6098 }
6099
6100 int
6101 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6102 {
6103         struct i40e_mac_filter *f;
6104         struct i40e_macvlan_filter *mv_f;
6105         int i, vlan_num;
6106         enum rte_mac_filter_type filter_type;
6107         int ret = I40E_SUCCESS;
6108
6109         /* Can't find it, return an error */
6110         f = i40e_find_mac_filter(vsi, addr);
6111         if (f == NULL)
6112                 return I40E_ERR_PARAM;
6113
6114         vlan_num = vsi->vlan_num;
6115         filter_type = f->mac_info.filter_type;
6116         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6117                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6118                 if (vlan_num == 0) {
6119                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6120                         return I40E_ERR_PARAM;
6121                 }
6122         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6123                         filter_type == RTE_MAC_HASH_MATCH)
6124                 vlan_num = 1;
6125
6126         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6127         if (mv_f == NULL) {
6128                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6129                 return I40E_ERR_NO_MEMORY;
6130         }
6131
6132         for (i = 0; i < vlan_num; i++) {
6133                 mv_f[i].filter_type = filter_type;
6134                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6135                                 ETH_ADDR_LEN);
6136         }
6137         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6138                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6139                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6140                 if (ret != I40E_SUCCESS)
6141                         goto DONE;
6142         }
6143
6144         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6145         if (ret != I40E_SUCCESS)
6146                 goto DONE;
6147
6148         /* Remove the mac addr into mac list */
6149         TAILQ_REMOVE(&vsi->mac_list, f, next);
6150         rte_free(f);
6151         vsi->mac_num--;
6152
6153         ret = I40E_SUCCESS;
6154 DONE:
6155         rte_free(mv_f);
6156         return ret;
6157 }
6158
6159 /* Configure hash enable flags for RSS */
6160 uint64_t
6161 i40e_config_hena(uint64_t flags)
6162 {
6163         uint64_t hena = 0;
6164
6165         if (!flags)
6166                 return hena;
6167
6168         if (flags & ETH_RSS_FRAG_IPV4)
6169                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6170         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6171 #ifdef X722_SUPPORT
6172                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6173                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6174 #else
6175                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6176 #endif
6177         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6178 #ifdef X722_SUPPORT
6179                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6180                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6181                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6182 #else
6183                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6184 #endif
6185         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6186                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6187         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6188                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6189         if (flags & ETH_RSS_FRAG_IPV6)
6190                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6191         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6192 #ifdef X722_SUPPORT
6193                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6194                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6195 #else
6196                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6197 #endif
6198         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6199 #ifdef X722_SUPPORT
6200                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6201                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6202                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6203 #else
6204                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6205 #endif
6206         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6207                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6208         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6209                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6210         if (flags & ETH_RSS_L2_PAYLOAD)
6211                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6212
6213         return hena;
6214 }
6215
6216 /* Parse the hash enable flags */
6217 uint64_t
6218 i40e_parse_hena(uint64_t flags)
6219 {
6220         uint64_t rss_hf = 0;
6221
6222         if (!flags)
6223                 return rss_hf;
6224         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6225                 rss_hf |= ETH_RSS_FRAG_IPV4;
6226         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6227                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6228 #ifdef X722_SUPPORT
6229         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6230                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6231 #endif
6232         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6233                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6234 #ifdef X722_SUPPORT
6235         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6236                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6237         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6238                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6239 #endif
6240         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6241                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6242         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6243                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6244         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6245                 rss_hf |= ETH_RSS_FRAG_IPV6;
6246         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6247                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6248 #ifdef X722_SUPPORT
6249         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6250                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6251 #endif
6252         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6253                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6254 #ifdef X722_SUPPORT
6255         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6256                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6257         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6258                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6259 #endif
6260         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6261                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6262         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6263                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6264         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6265                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6266
6267         return rss_hf;
6268 }
6269
6270 /* Disable RSS */
6271 static void
6272 i40e_pf_disable_rss(struct i40e_pf *pf)
6273 {
6274         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6275         uint64_t hena;
6276
6277         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6278         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6279         hena &= ~I40E_RSS_HENA_ALL;
6280         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6281         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6282         I40E_WRITE_FLUSH(hw);
6283 }
6284
6285 static int
6286 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6287 {
6288         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6289         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6290         int ret = 0;
6291
6292         if (!key || key_len == 0) {
6293                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6294                 return 0;
6295         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6296                 sizeof(uint32_t)) {
6297                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6298                 return -EINVAL;
6299         }
6300
6301         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6302                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6303                         (struct i40e_aqc_get_set_rss_key_data *)key;
6304
6305                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6306                 if (ret)
6307                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6308                                      "via AQ");
6309         } else {
6310                 uint32_t *hash_key = (uint32_t *)key;
6311                 uint16_t i;
6312
6313                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6314                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6315                 I40E_WRITE_FLUSH(hw);
6316         }
6317
6318         return ret;
6319 }
6320
6321 static int
6322 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6323 {
6324         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6325         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6326         int ret;
6327
6328         if (!key || !key_len)
6329                 return -EINVAL;
6330
6331         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6332                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6333                         (struct i40e_aqc_get_set_rss_key_data *)key);
6334                 if (ret) {
6335                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6336                         return ret;
6337                 }
6338         } else {
6339                 uint32_t *key_dw = (uint32_t *)key;
6340                 uint16_t i;
6341
6342                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6343                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6344         }
6345         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6346
6347         return 0;
6348 }
6349
6350 static int
6351 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6352 {
6353         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6354         uint64_t rss_hf;
6355         uint64_t hena;
6356         int ret;
6357
6358         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6359                                rss_conf->rss_key_len);
6360         if (ret)
6361                 return ret;
6362
6363         rss_hf = rss_conf->rss_hf;
6364         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6365         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6366         hena &= ~I40E_RSS_HENA_ALL;
6367         hena |= i40e_config_hena(rss_hf);
6368         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6369         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6370         I40E_WRITE_FLUSH(hw);
6371
6372         return 0;
6373 }
6374
6375 static int
6376 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6377                          struct rte_eth_rss_conf *rss_conf)
6378 {
6379         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6380         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6381         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6382         uint64_t hena;
6383
6384         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6385         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6386         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6387                 if (rss_hf != 0) /* Enable RSS */
6388                         return -EINVAL;
6389                 return 0; /* Nothing to do */
6390         }
6391         /* RSS enabled */
6392         if (rss_hf == 0) /* Disable RSS */
6393                 return -EINVAL;
6394
6395         return i40e_hw_rss_hash_set(pf, rss_conf);
6396 }
6397
6398 static int
6399 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6400                            struct rte_eth_rss_conf *rss_conf)
6401 {
6402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6404         uint64_t hena;
6405
6406         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6407                          &rss_conf->rss_key_len);
6408
6409         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6410         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6411         rss_conf->rss_hf = i40e_parse_hena(hena);
6412
6413         return 0;
6414 }
6415
6416 static int
6417 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6418 {
6419         switch (filter_type) {
6420         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6421                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6422                 break;
6423         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6424                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6425                 break;
6426         case RTE_TUNNEL_FILTER_IMAC_TENID:
6427                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6428                 break;
6429         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6430                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6431                 break;
6432         case ETH_TUNNEL_FILTER_IMAC:
6433                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6434                 break;
6435         case ETH_TUNNEL_FILTER_OIP:
6436                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6437                 break;
6438         case ETH_TUNNEL_FILTER_IIP:
6439                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6440                 break;
6441         default:
6442                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6443                 return -EINVAL;
6444         }
6445
6446         return 0;
6447 }
6448
6449 static int
6450 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6451                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6452                         uint8_t add)
6453 {
6454         uint16_t ip_type;
6455         uint32_t ipv4_addr;
6456         uint8_t i, tun_type = 0;
6457         /* internal varialbe to convert ipv6 byte order */
6458         uint32_t convert_ipv6[4];
6459         int val, ret = 0;
6460         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6461         struct i40e_vsi *vsi = pf->main_vsi;
6462         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6463         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6464
6465         cld_filter = rte_zmalloc("tunnel_filter",
6466                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6467                 0);
6468
6469         if (NULL == cld_filter) {
6470                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6471                 return -EINVAL;
6472         }
6473         pfilter = cld_filter;
6474
6475         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6476         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6477
6478         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6479         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6480                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6481                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6482                 rte_memcpy(&pfilter->ipaddr.v4.data,
6483                                 &rte_cpu_to_le_32(ipv4_addr),
6484                                 sizeof(pfilter->ipaddr.v4.data));
6485         } else {
6486                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6487                 for (i = 0; i < 4; i++) {
6488                         convert_ipv6[i] =
6489                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6490                 }
6491                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6492                                 sizeof(pfilter->ipaddr.v6.data));
6493         }
6494
6495         /* check tunneled type */
6496         switch (tunnel_filter->tunnel_type) {
6497         case RTE_TUNNEL_TYPE_VXLAN:
6498                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6499                 break;
6500         case RTE_TUNNEL_TYPE_NVGRE:
6501                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6502                 break;
6503         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6504                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6505                 break;
6506         default:
6507                 /* Other tunnel types is not supported. */
6508                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6509                 rte_free(cld_filter);
6510                 return -EINVAL;
6511         }
6512
6513         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6514                                                 &pfilter->flags);
6515         if (val < 0) {
6516                 rte_free(cld_filter);
6517                 return -EINVAL;
6518         }
6519
6520         pfilter->flags |= rte_cpu_to_le_16(
6521                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6522                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6523         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6524         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6525
6526         if (add)
6527                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6528         else
6529                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6530                                                 cld_filter, 1);
6531
6532         rte_free(cld_filter);
6533         return ret;
6534 }
6535
6536 static int
6537 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6538 {
6539         uint8_t i;
6540
6541         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6542                 if (pf->vxlan_ports[i] == port)
6543                         return i;
6544         }
6545
6546         return -1;
6547 }
6548
6549 static int
6550 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6551 {
6552         int  idx, ret;
6553         uint8_t filter_idx;
6554         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6555
6556         idx = i40e_get_vxlan_port_idx(pf, port);
6557
6558         /* Check if port already exists */
6559         if (idx >= 0) {
6560                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6561                 return -EINVAL;
6562         }
6563
6564         /* Now check if there is space to add the new port */
6565         idx = i40e_get_vxlan_port_idx(pf, 0);
6566         if (idx < 0) {
6567                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6568                         "not adding port %d", port);
6569                 return -ENOSPC;
6570         }
6571
6572         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6573                                         &filter_idx, NULL);
6574         if (ret < 0) {
6575                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6576                 return -1;
6577         }
6578
6579         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6580                          port,  filter_idx);
6581
6582         /* New port: add it and mark its index in the bitmap */
6583         pf->vxlan_ports[idx] = port;
6584         pf->vxlan_bitmap |= (1 << idx);
6585
6586         if (!(pf->flags & I40E_FLAG_VXLAN))
6587                 pf->flags |= I40E_FLAG_VXLAN;
6588
6589         return 0;
6590 }
6591
6592 static int
6593 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6594 {
6595         int idx;
6596         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6597
6598         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6599                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6600                 return -EINVAL;
6601         }
6602
6603         idx = i40e_get_vxlan_port_idx(pf, port);
6604
6605         if (idx < 0) {
6606                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6607                 return -EINVAL;
6608         }
6609
6610         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6611                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6612                 return -1;
6613         }
6614
6615         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6616                         port, idx);
6617
6618         pf->vxlan_ports[idx] = 0;
6619         pf->vxlan_bitmap &= ~(1 << idx);
6620
6621         if (!pf->vxlan_bitmap)
6622                 pf->flags &= ~I40E_FLAG_VXLAN;
6623
6624         return 0;
6625 }
6626
6627 /* Add UDP tunneling port */
6628 static int
6629 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6630                              struct rte_eth_udp_tunnel *udp_tunnel)
6631 {
6632         int ret = 0;
6633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6634
6635         if (udp_tunnel == NULL)
6636                 return -EINVAL;
6637
6638         switch (udp_tunnel->prot_type) {
6639         case RTE_TUNNEL_TYPE_VXLAN:
6640                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6641                 break;
6642
6643         case RTE_TUNNEL_TYPE_GENEVE:
6644         case RTE_TUNNEL_TYPE_TEREDO:
6645                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6646                 ret = -1;
6647                 break;
6648
6649         default:
6650                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6651                 ret = -1;
6652                 break;
6653         }
6654
6655         return ret;
6656 }
6657
6658 /* Remove UDP tunneling port */
6659 static int
6660 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6661                              struct rte_eth_udp_tunnel *udp_tunnel)
6662 {
6663         int ret = 0;
6664         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6665
6666         if (udp_tunnel == NULL)
6667                 return -EINVAL;
6668
6669         switch (udp_tunnel->prot_type) {
6670         case RTE_TUNNEL_TYPE_VXLAN:
6671                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6672                 break;
6673         case RTE_TUNNEL_TYPE_GENEVE:
6674         case RTE_TUNNEL_TYPE_TEREDO:
6675                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6676                 ret = -1;
6677                 break;
6678         default:
6679                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6680                 ret = -1;
6681                 break;
6682         }
6683
6684         return ret;
6685 }
6686
6687 /* Calculate the maximum number of contiguous PF queues that are configured */
6688 static int
6689 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6690 {
6691         struct rte_eth_dev_data *data = pf->dev_data;
6692         int i, num;
6693         struct i40e_rx_queue *rxq;
6694
6695         num = 0;
6696         for (i = 0; i < pf->lan_nb_qps; i++) {
6697                 rxq = data->rx_queues[i];
6698                 if (rxq && rxq->q_set)
6699                         num++;
6700                 else
6701                         break;
6702         }
6703
6704         return num;
6705 }
6706
6707 /* Configure RSS */
6708 static int
6709 i40e_pf_config_rss(struct i40e_pf *pf)
6710 {
6711         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6712         struct rte_eth_rss_conf rss_conf;
6713         uint32_t i, lut = 0;
6714         uint16_t j, num;
6715
6716         /*
6717          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6718          * It's necessary to calulate the actual PF queues that are configured.
6719          */
6720         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6721                 num = i40e_pf_calc_configured_queues_num(pf);
6722         else
6723                 num = pf->dev_data->nb_rx_queues;
6724
6725         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6726         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6727                         num);
6728
6729         if (num == 0) {
6730                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6731                 return -ENOTSUP;
6732         }
6733
6734         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6735                 if (j == num)
6736                         j = 0;
6737                 lut = (lut << 8) | (j & ((0x1 <<
6738                         hw->func_caps.rss_table_entry_width) - 1));
6739                 if ((i & 3) == 3)
6740                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6741         }
6742
6743         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6744         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6745                 i40e_pf_disable_rss(pf);
6746                 return 0;
6747         }
6748         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6749                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6750                 /* Random default keys */
6751                 static uint32_t rss_key_default[] = {0x6b793944,
6752                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6753                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6754                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6755
6756                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6757                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6758                                                         sizeof(uint32_t);
6759         }
6760
6761         return i40e_hw_rss_hash_set(pf, &rss_conf);
6762 }
6763
6764 static int
6765 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6766                                struct rte_eth_tunnel_filter_conf *filter)
6767 {
6768         if (pf == NULL || filter == NULL) {
6769                 PMD_DRV_LOG(ERR, "Invalid parameter");
6770                 return -EINVAL;
6771         }
6772
6773         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6774                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6775                 return -EINVAL;
6776         }
6777
6778         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6779                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6780                 return -EINVAL;
6781         }
6782
6783         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6784                 (is_zero_ether_addr(&filter->outer_mac))) {
6785                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6786                 return -EINVAL;
6787         }
6788
6789         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6790                 (is_zero_ether_addr(&filter->inner_mac))) {
6791                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6792                 return -EINVAL;
6793         }
6794
6795         return 0;
6796 }
6797
6798 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6799 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6800 static int
6801 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6802 {
6803         uint32_t val, reg;
6804         int ret = -EINVAL;
6805
6806         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6807         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6808
6809         if (len == 3) {
6810                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6811         } else if (len == 4) {
6812                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6813         } else {
6814                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6815                 return ret;
6816         }
6817
6818         if (reg != val) {
6819                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6820                                                    reg, NULL);
6821                 if (ret != 0)
6822                         return ret;
6823         } else {
6824                 ret = 0;
6825         }
6826         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6827                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6828
6829         return ret;
6830 }
6831
6832 static int
6833 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6834 {
6835         int ret = -EINVAL;
6836
6837         if (!hw || !cfg)
6838                 return -EINVAL;
6839
6840         switch (cfg->cfg_type) {
6841         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6842                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6843                 break;
6844         default:
6845                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6846                 break;
6847         }
6848
6849         return ret;
6850 }
6851
6852 static int
6853 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6854                                enum rte_filter_op filter_op,
6855                                void *arg)
6856 {
6857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6858         int ret = I40E_ERR_PARAM;
6859
6860         switch (filter_op) {
6861         case RTE_ETH_FILTER_SET:
6862                 ret = i40e_dev_global_config_set(hw,
6863                         (struct rte_eth_global_cfg *)arg);
6864                 break;
6865         default:
6866                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6867                 break;
6868         }
6869
6870         return ret;
6871 }
6872
6873 static int
6874 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6875                           enum rte_filter_op filter_op,
6876                           void *arg)
6877 {
6878         struct rte_eth_tunnel_filter_conf *filter;
6879         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6880         int ret = I40E_SUCCESS;
6881
6882         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6883
6884         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6885                 return I40E_ERR_PARAM;
6886
6887         switch (filter_op) {
6888         case RTE_ETH_FILTER_NOP:
6889                 if (!(pf->flags & I40E_FLAG_VXLAN))
6890                         ret = I40E_NOT_SUPPORTED;
6891                 break;
6892         case RTE_ETH_FILTER_ADD:
6893                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6894                 break;
6895         case RTE_ETH_FILTER_DELETE:
6896                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6897                 break;
6898         default:
6899                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6900                 ret = I40E_ERR_PARAM;
6901                 break;
6902         }
6903
6904         return ret;
6905 }
6906
6907 static int
6908 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6909 {
6910         int ret = 0;
6911         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6912
6913         /* RSS setup */
6914         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6915                 ret = i40e_pf_config_rss(pf);
6916         else
6917                 i40e_pf_disable_rss(pf);
6918
6919         return ret;
6920 }
6921
6922 /* Get the symmetric hash enable configurations per port */
6923 static void
6924 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6925 {
6926         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6927
6928         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6929 }
6930
6931 /* Set the symmetric hash enable configurations per port */
6932 static void
6933 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6934 {
6935         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6936
6937         if (enable > 0) {
6938                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6939                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6940                                                         "been enabled");
6941                         return;
6942                 }
6943                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6944         } else {
6945                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6946                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6947                                                         "been disabled");
6948                         return;
6949                 }
6950                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6951         }
6952         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6953         I40E_WRITE_FLUSH(hw);
6954 }
6955
6956 /*
6957  * Get global configurations of hash function type and symmetric hash enable
6958  * per flow type (pctype). Note that global configuration means it affects all
6959  * the ports on the same NIC.
6960  */
6961 static int
6962 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6963                                    struct rte_eth_hash_global_conf *g_cfg)
6964 {
6965         uint32_t reg, mask = I40E_FLOW_TYPES;
6966         uint16_t i;
6967         enum i40e_filter_pctype pctype;
6968
6969         memset(g_cfg, 0, sizeof(*g_cfg));
6970         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6971         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6972                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6973         else
6974                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6975         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6976                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6977
6978         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6979                 if (!(mask & (1UL << i)))
6980                         continue;
6981                 mask &= ~(1UL << i);
6982                 /* Bit set indicats the coresponding flow type is supported */
6983                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6984                 /* if flowtype is invalid, continue */
6985                 if (!I40E_VALID_FLOW(i))
6986                         continue;
6987                 pctype = i40e_flowtype_to_pctype(i);
6988                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6989                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6990                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6991         }
6992
6993         return 0;
6994 }
6995
6996 static int
6997 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6998 {
6999         uint32_t i;
7000         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7001
7002         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7003                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7004                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7005                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7006                                                 g_cfg->hash_func);
7007                 return -EINVAL;
7008         }
7009
7010         /*
7011          * As i40e supports less than 32 flow types, only first 32 bits need to
7012          * be checked.
7013          */
7014         mask0 = g_cfg->valid_bit_mask[0];
7015         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7016                 if (i == 0) {
7017                         /* Check if any unsupported flow type configured */
7018                         if ((mask0 | i40e_mask) ^ i40e_mask)
7019                                 goto mask_err;
7020                 } else {
7021                         if (g_cfg->valid_bit_mask[i])
7022                                 goto mask_err;
7023                 }
7024         }
7025
7026         return 0;
7027
7028 mask_err:
7029         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7030
7031         return -EINVAL;
7032 }
7033
7034 /*
7035  * Set global configurations of hash function type and symmetric hash enable
7036  * per flow type (pctype). Note any modifying global configuration will affect
7037  * all the ports on the same NIC.
7038  */
7039 static int
7040 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7041                                    struct rte_eth_hash_global_conf *g_cfg)
7042 {
7043         int ret;
7044         uint16_t i;
7045         uint32_t reg;
7046         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7047         enum i40e_filter_pctype pctype;
7048
7049         /* Check the input parameters */
7050         ret = i40e_hash_global_config_check(g_cfg);
7051         if (ret < 0)
7052                 return ret;
7053
7054         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7055                 if (!(mask0 & (1UL << i)))
7056                         continue;
7057                 mask0 &= ~(1UL << i);
7058                 /* if flowtype is invalid, continue */
7059                 if (!I40E_VALID_FLOW(i))
7060                         continue;
7061                 pctype = i40e_flowtype_to_pctype(i);
7062                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7063                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7064                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7065         }
7066
7067         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7068         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7069                 /* Toeplitz */
7070                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7071                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7072                                                                 "Toeplitz");
7073                         goto out;
7074                 }
7075                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7076         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7077                 /* Simple XOR */
7078                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7079                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7080                                                         "Simple XOR");
7081                         goto out;
7082                 }
7083                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7084         } else
7085                 /* Use the default, and keep it as it is */
7086                 goto out;
7087
7088         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7089
7090 out:
7091         I40E_WRITE_FLUSH(hw);
7092
7093         return 0;
7094 }
7095
7096 /**
7097  * Valid input sets for hash and flow director filters per PCTYPE
7098  */
7099 static uint64_t
7100 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7101                 enum rte_filter_type filter)
7102 {
7103         uint64_t valid;
7104
7105         static const uint64_t valid_hash_inset_table[] = {
7106                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7107                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7108                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7109                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7110                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7111                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7112                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7113                         I40E_INSET_FLEX_PAYLOAD,
7114                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7118                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7119                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7120                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7121                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7122                         I40E_INSET_FLEX_PAYLOAD,
7123 #ifdef X722_SUPPORT
7124                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7125                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7126                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7127                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7128                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7129                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7130                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7131                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7132                         I40E_INSET_FLEX_PAYLOAD,
7133                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7134                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7135                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7136                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7137                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7138                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7139                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7140                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7141                         I40E_INSET_FLEX_PAYLOAD,
7142 #endif
7143                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7144                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7145                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7146                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7147                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7148                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7149                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7150                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7151                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7152 #ifdef X722_SUPPORT
7153                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7154                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7155                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7156                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7157                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7158                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7159                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7160                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7161                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7162 #endif
7163                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7164                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7165                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7166                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7167                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7168                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7169                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7170                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7171                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7172                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7173                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7174                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7175                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7176                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7177                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7178                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7179                         I40E_INSET_FLEX_PAYLOAD,
7180                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7181                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7182                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7183                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7184                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7185                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7186                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7187                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7188                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7189                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7190                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7191                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7192                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7193                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7194                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7195                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7196 #ifdef X722_SUPPORT
7197                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7198                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7199                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7200                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7201                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7202                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7203                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7204                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7205                         I40E_INSET_FLEX_PAYLOAD,
7206                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7207                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7208                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7209                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7210                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7211                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7212                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7213                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7214                         I40E_INSET_FLEX_PAYLOAD,
7215 #endif
7216                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7217                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7218                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7219                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7220                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7221                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7222                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7223                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7224                         I40E_INSET_FLEX_PAYLOAD,
7225 #ifdef X722_SUPPORT
7226                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7227                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7228                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7229                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7230                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7231                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7232                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7233                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7234                         I40E_INSET_FLEX_PAYLOAD,
7235 #endif
7236                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7237                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7238                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7239                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7240                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7241                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7242                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7243                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7244                         I40E_INSET_FLEX_PAYLOAD,
7245                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7246                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7247                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7248                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7249                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7250                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7251                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7252                         I40E_INSET_FLEX_PAYLOAD,
7253                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7254                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7255                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7256                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7257                         I40E_INSET_FLEX_PAYLOAD,
7258         };
7259
7260         /**
7261          * Flow director supports only fields defined in
7262          * union rte_eth_fdir_flow.
7263          */
7264         static const uint64_t valid_fdir_inset_table[] = {
7265                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7266                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7267                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7268                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7269                 I40E_INSET_IPV4_TTL,
7270                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7271                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7272                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7273                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7274                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7275 #ifdef X722_SUPPORT
7276                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7277                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7278                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7279                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7280                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7281                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7282                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7283                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7284                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7285                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7286 #endif
7287                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7288                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7289                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7290                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7291                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7292 #ifdef X722_SUPPORT
7293                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7294                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7295                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7296                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7297                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7298 #endif
7299                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7300                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7301                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7302                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7303                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7304                 I40E_INSET_SCTP_VT,
7305                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7306                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7307                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7308                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7309                 I40E_INSET_IPV4_TTL,
7310                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7311                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7312                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7313                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7314                 I40E_INSET_IPV6_HOP_LIMIT,
7315                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7316                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7317                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7318                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7319                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7320 #ifdef X722_SUPPORT
7321                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7322                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7323                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7324                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7325                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7326                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7327                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7328                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7329                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7330                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7331 #endif
7332                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7333                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7334                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7335                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7336                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7337 #ifdef X722_SUPPORT
7338                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7339                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7340                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7341                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7342                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7343 #endif
7344                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7345                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7346                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7347                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7348                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7349                 I40E_INSET_SCTP_VT,
7350                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7351                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7352                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7353                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7354                 I40E_INSET_IPV6_HOP_LIMIT,
7355                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7356                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7357                 I40E_INSET_LAST_ETHER_TYPE,
7358         };
7359
7360         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7361                 return 0;
7362         if (filter == RTE_ETH_FILTER_HASH)
7363                 valid = valid_hash_inset_table[pctype];
7364         else
7365                 valid = valid_fdir_inset_table[pctype];
7366
7367         return valid;
7368 }
7369
7370 /**
7371  * Validate if the input set is allowed for a specific PCTYPE
7372  */
7373 static int
7374 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7375                 enum rte_filter_type filter, uint64_t inset)
7376 {
7377         uint64_t valid;
7378
7379         valid = i40e_get_valid_input_set(pctype, filter);
7380         if (inset & (~valid))
7381                 return -EINVAL;
7382
7383         return 0;
7384 }
7385
7386 /* default input set fields combination per pctype */
7387 static uint64_t
7388 i40e_get_default_input_set(uint16_t pctype)
7389 {
7390         static const uint64_t default_inset_table[] = {
7391                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7392                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7393                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7394                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7395                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7396 #ifdef X722_SUPPORT
7397                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7398                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7399                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7400                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7401                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7402                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7403 #endif
7404                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7405                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7406                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7407 #ifdef X722_SUPPORT
7408                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7409                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7410                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7411 #endif
7412                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7413                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7414                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7415                         I40E_INSET_SCTP_VT,
7416                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7417                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7418                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7419                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7420                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7421                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7422                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7423 #ifdef X722_SUPPORT
7424                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7425                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7426                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7427                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7428                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7429                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7430 #endif
7431                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7432                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7433                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7434 #ifdef X722_SUPPORT
7435                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7436                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7437                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7438 #endif
7439                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7440                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7441                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7442                         I40E_INSET_SCTP_VT,
7443                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7444                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7445                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7446                         I40E_INSET_LAST_ETHER_TYPE,
7447         };
7448
7449         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7450                 return 0;
7451
7452         return default_inset_table[pctype];
7453 }
7454
7455 /**
7456  * Parse the input set from index to logical bit masks
7457  */
7458 static int
7459 i40e_parse_input_set(uint64_t *inset,
7460                      enum i40e_filter_pctype pctype,
7461                      enum rte_eth_input_set_field *field,
7462                      uint16_t size)
7463 {
7464         uint16_t i, j;
7465         int ret = -EINVAL;
7466
7467         static const struct {
7468                 enum rte_eth_input_set_field field;
7469                 uint64_t inset;
7470         } inset_convert_table[] = {
7471                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7472                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7473                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7474                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7475                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7476                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7477                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7478                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7479                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7480                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7481                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7482                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7483                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7484                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7485                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7486                         I40E_INSET_IPV6_NEXT_HDR},
7487                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7488                         I40E_INSET_IPV6_HOP_LIMIT},
7489                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7490                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7491                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7492                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7493                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7494                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7495                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7496                         I40E_INSET_SCTP_VT},
7497                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7498                         I40E_INSET_TUNNEL_DMAC},
7499                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7500                         I40E_INSET_VLAN_TUNNEL},
7501                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7502                         I40E_INSET_TUNNEL_ID},
7503                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7504                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7505                         I40E_INSET_FLEX_PAYLOAD_W1},
7506                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7507                         I40E_INSET_FLEX_PAYLOAD_W2},
7508                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7509                         I40E_INSET_FLEX_PAYLOAD_W3},
7510                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7511                         I40E_INSET_FLEX_PAYLOAD_W4},
7512                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7513                         I40E_INSET_FLEX_PAYLOAD_W5},
7514                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7515                         I40E_INSET_FLEX_PAYLOAD_W6},
7516                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7517                         I40E_INSET_FLEX_PAYLOAD_W7},
7518                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7519                         I40E_INSET_FLEX_PAYLOAD_W8},
7520         };
7521
7522         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7523                 return ret;
7524
7525         /* Only one item allowed for default or all */
7526         if (size == 1) {
7527                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7528                         *inset = i40e_get_default_input_set(pctype);
7529                         return 0;
7530                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7531                         *inset = I40E_INSET_NONE;
7532                         return 0;
7533                 }
7534         }
7535
7536         for (i = 0, *inset = 0; i < size; i++) {
7537                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7538                         if (field[i] == inset_convert_table[j].field) {
7539                                 *inset |= inset_convert_table[j].inset;
7540                                 break;
7541                         }
7542                 }
7543
7544                 /* It contains unsupported input set, return immediately */
7545                 if (j == RTE_DIM(inset_convert_table))
7546                         return ret;
7547         }
7548
7549         return 0;
7550 }
7551
7552 /**
7553  * Translate the input set from bit masks to register aware bit masks
7554  * and vice versa
7555  */
7556 static uint64_t
7557 i40e_translate_input_set_reg(uint64_t input)
7558 {
7559         uint64_t val = 0;
7560         uint16_t i;
7561
7562         static const struct {
7563                 uint64_t inset;
7564                 uint64_t inset_reg;
7565         } inset_map[] = {
7566                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7567                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7568                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7569                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7570                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7571                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7572                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7573                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7574                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7575                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7576                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7577                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7578                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7579                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7580                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7581                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7582                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7583                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7584                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7585                 {I40E_INSET_TUNNEL_DMAC,
7586                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7587                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7588                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7589                 {I40E_INSET_TUNNEL_SRC_PORT,
7590                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7591                 {I40E_INSET_TUNNEL_DST_PORT,
7592                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7593                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7594                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7595                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7596                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7597                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7598                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7599                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7600                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7601                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7602         };
7603
7604         if (input == 0)
7605                 return val;
7606
7607         /* Translate input set to register aware inset */
7608         for (i = 0; i < RTE_DIM(inset_map); i++) {
7609                 if (input & inset_map[i].inset)
7610                         val |= inset_map[i].inset_reg;
7611         }
7612
7613         return val;
7614 }
7615
7616 static int
7617 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7618 {
7619         uint8_t i, idx = 0;
7620         uint64_t inset_need_mask = inset;
7621
7622         static const struct {
7623                 uint64_t inset;
7624                 uint32_t mask;
7625         } inset_mask_map[] = {
7626                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7627                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7628                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7629                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7630                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7631                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7632                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7633                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7634         };
7635
7636         if (!inset || !mask || !nb_elem)
7637                 return 0;
7638
7639         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7640                 /* Clear the inset bit, if no MASK is required,
7641                  * for example proto + ttl
7642                  */
7643                 if ((inset & inset_mask_map[i].inset) ==
7644                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7645                         inset_need_mask &= ~inset_mask_map[i].inset;
7646                 if (!inset_need_mask)
7647                         return 0;
7648         }
7649         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7650                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7651                     inset_mask_map[i].inset) {
7652                         if (idx >= nb_elem) {
7653                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7654                                 return -EINVAL;
7655                         }
7656                         mask[idx] = inset_mask_map[i].mask;
7657                         idx++;
7658                 }
7659         }
7660
7661         return idx;
7662 }
7663
7664 static void
7665 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7666 {
7667         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7668
7669         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7670         if (reg != val)
7671                 i40e_write_rx_ctl(hw, addr, val);
7672         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7673                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7674 }
7675
7676 static void
7677 i40e_filter_input_set_init(struct i40e_pf *pf)
7678 {
7679         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7680         enum i40e_filter_pctype pctype;
7681         uint64_t input_set, inset_reg;
7682         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7683         int num, i;
7684
7685         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7686              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7687                 if (!I40E_VALID_PCTYPE(pctype))
7688                         continue;
7689                 input_set = i40e_get_default_input_set(pctype);
7690
7691                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7692                                                    I40E_INSET_MASK_NUM_REG);
7693                 if (num < 0)
7694                         return;
7695                 inset_reg = i40e_translate_input_set_reg(input_set);
7696
7697                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7698                                       (uint32_t)(inset_reg & UINT32_MAX));
7699                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7700                                      (uint32_t)((inset_reg >>
7701                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7702                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7703                                       (uint32_t)(inset_reg & UINT32_MAX));
7704                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7705                                      (uint32_t)((inset_reg >>
7706                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7707
7708                 for (i = 0; i < num; i++) {
7709                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7710                                              mask_reg[i]);
7711                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7712                                              mask_reg[i]);
7713                 }
7714                 /*clear unused mask registers of the pctype */
7715                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7716                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7717                                              0);
7718                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7719                                              0);
7720                 }
7721                 I40E_WRITE_FLUSH(hw);
7722
7723                 /* store the default input set */
7724                 pf->hash_input_set[pctype] = input_set;
7725                 pf->fdir.input_set[pctype] = input_set;
7726         }
7727 }
7728
7729 int
7730 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7731                          struct rte_eth_input_set_conf *conf)
7732 {
7733         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7734         enum i40e_filter_pctype pctype;
7735         uint64_t input_set, inset_reg = 0;
7736         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7737         int ret, i, num;
7738
7739         if (!conf) {
7740                 PMD_DRV_LOG(ERR, "Invalid pointer");
7741                 return -EFAULT;
7742         }
7743         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7744             conf->op != RTE_ETH_INPUT_SET_ADD) {
7745                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7746                 return -EINVAL;
7747         }
7748
7749         if (!I40E_VALID_FLOW(conf->flow_type)) {
7750                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7751                 return -EINVAL;
7752         }
7753
7754 #ifdef X722_SUPPORT
7755         /* get translated pctype value in fd pctype register */
7756         pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7757                 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7758                 conf->flow_type)));
7759 #else
7760         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7761 #endif
7762
7763         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7764                                    conf->inset_size);
7765         if (ret) {
7766                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7767                 return -EINVAL;
7768         }
7769         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7770                                     input_set) != 0) {
7771                 PMD_DRV_LOG(ERR, "Invalid input set");
7772                 return -EINVAL;
7773         }
7774         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7775                 /* get inset value in register */
7776                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7777                 inset_reg <<= I40E_32_BIT_WIDTH;
7778                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7779                 input_set |= pf->hash_input_set[pctype];
7780         }
7781         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7782                                            I40E_INSET_MASK_NUM_REG);
7783         if (num < 0)
7784                 return -EINVAL;
7785
7786         inset_reg |= i40e_translate_input_set_reg(input_set);
7787
7788         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7789                               (uint32_t)(inset_reg & UINT32_MAX));
7790         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7791                              (uint32_t)((inset_reg >>
7792                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7793
7794         for (i = 0; i < num; i++)
7795                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7796                                      mask_reg[i]);
7797         /*clear unused mask registers of the pctype */
7798         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7799                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7800                                      0);
7801         I40E_WRITE_FLUSH(hw);
7802
7803         pf->hash_input_set[pctype] = input_set;
7804         return 0;
7805 }
7806
7807 int
7808 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7809                          struct rte_eth_input_set_conf *conf)
7810 {
7811         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7812         enum i40e_filter_pctype pctype;
7813         uint64_t input_set, inset_reg = 0;
7814         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7815         int ret, i, num;
7816
7817         if (!hw || !conf) {
7818                 PMD_DRV_LOG(ERR, "Invalid pointer");
7819                 return -EFAULT;
7820         }
7821         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7822             conf->op != RTE_ETH_INPUT_SET_ADD) {
7823                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7824                 return -EINVAL;
7825         }
7826
7827         if (!I40E_VALID_FLOW(conf->flow_type)) {
7828                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7829                 return -EINVAL;
7830         }
7831
7832         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7833
7834         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7835                                    conf->inset_size);
7836         if (ret) {
7837                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7838                 return -EINVAL;
7839         }
7840         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7841                                     input_set) != 0) {
7842                 PMD_DRV_LOG(ERR, "Invalid input set");
7843                 return -EINVAL;
7844         }
7845
7846         /* get inset value in register */
7847         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7848         inset_reg <<= I40E_32_BIT_WIDTH;
7849         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7850
7851         /* Can not change the inset reg for flex payload for fdir,
7852          * it is done by writing I40E_PRTQF_FD_FLXINSET
7853          * in i40e_set_flex_mask_on_pctype.
7854          */
7855         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7856                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7857         else
7858                 input_set |= pf->fdir.input_set[pctype];
7859         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7860                                            I40E_INSET_MASK_NUM_REG);
7861         if (num < 0)
7862                 return -EINVAL;
7863
7864         inset_reg |= i40e_translate_input_set_reg(input_set);
7865
7866         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7867                               (uint32_t)(inset_reg & UINT32_MAX));
7868         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7869                              (uint32_t)((inset_reg >>
7870                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7871
7872         for (i = 0; i < num; i++)
7873                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7874                                      mask_reg[i]);
7875         /*clear unused mask registers of the pctype */
7876         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7877                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7878                                      0);
7879         I40E_WRITE_FLUSH(hw);
7880
7881         pf->fdir.input_set[pctype] = input_set;
7882         return 0;
7883 }
7884
7885 static int
7886 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7887 {
7888         int ret = 0;
7889
7890         if (!hw || !info) {
7891                 PMD_DRV_LOG(ERR, "Invalid pointer");
7892                 return -EFAULT;
7893         }
7894
7895         switch (info->info_type) {
7896         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7897                 i40e_get_symmetric_hash_enable_per_port(hw,
7898                                         &(info->info.enable));
7899                 break;
7900         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7901                 ret = i40e_get_hash_filter_global_config(hw,
7902                                 &(info->info.global_conf));
7903                 break;
7904         default:
7905                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7906                                                         info->info_type);
7907                 ret = -EINVAL;
7908                 break;
7909         }
7910
7911         return ret;
7912 }
7913
7914 static int
7915 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7916 {
7917         int ret = 0;
7918
7919         if (!hw || !info) {
7920                 PMD_DRV_LOG(ERR, "Invalid pointer");
7921                 return -EFAULT;
7922         }
7923
7924         switch (info->info_type) {
7925         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7926                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7927                 break;
7928         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7929                 ret = i40e_set_hash_filter_global_config(hw,
7930                                 &(info->info.global_conf));
7931                 break;
7932         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7933                 ret = i40e_hash_filter_inset_select(hw,
7934                                                &(info->info.input_set_conf));
7935                 break;
7936
7937         default:
7938                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7939                                                         info->info_type);
7940                 ret = -EINVAL;
7941                 break;
7942         }
7943
7944         return ret;
7945 }
7946
7947 /* Operations for hash function */
7948 static int
7949 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7950                       enum rte_filter_op filter_op,
7951                       void *arg)
7952 {
7953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7954         int ret = 0;
7955
7956         switch (filter_op) {
7957         case RTE_ETH_FILTER_NOP:
7958                 break;
7959         case RTE_ETH_FILTER_GET:
7960                 ret = i40e_hash_filter_get(hw,
7961                         (struct rte_eth_hash_filter_info *)arg);
7962                 break;
7963         case RTE_ETH_FILTER_SET:
7964                 ret = i40e_hash_filter_set(hw,
7965                         (struct rte_eth_hash_filter_info *)arg);
7966                 break;
7967         default:
7968                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7969                                                                 filter_op);
7970                 ret = -ENOTSUP;
7971                 break;
7972         }
7973
7974         return ret;
7975 }
7976
7977 /*
7978  * Configure ethertype filter, which can director packet by filtering
7979  * with mac address and ether_type or only ether_type
7980  */
7981 static int
7982 i40e_ethertype_filter_set(struct i40e_pf *pf,
7983                         struct rte_eth_ethertype_filter *filter,
7984                         bool add)
7985 {
7986         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7987         struct i40e_control_filter_stats stats;
7988         uint16_t flags = 0;
7989         int ret;
7990
7991         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7992                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7993                 return -EINVAL;
7994         }
7995         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7996                 filter->ether_type == ETHER_TYPE_IPv6) {
7997                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7998                         " control packet filter.", filter->ether_type);
7999                 return -EINVAL;
8000         }
8001         if (filter->ether_type == ETHER_TYPE_VLAN)
8002                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8003                         " not supported.");
8004
8005         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8006                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8007         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8008                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8009         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8010
8011         memset(&stats, 0, sizeof(stats));
8012         ret = i40e_aq_add_rem_control_packet_filter(hw,
8013                         filter->mac_addr.addr_bytes,
8014                         filter->ether_type, flags,
8015                         pf->main_vsi->seid,
8016                         filter->queue, add, &stats, NULL);
8017
8018         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8019                          " mac_etype_used = %u, etype_used = %u,"
8020                          " mac_etype_free = %u, etype_free = %u\n",
8021                          ret, stats.mac_etype_used, stats.etype_used,
8022                          stats.mac_etype_free, stats.etype_free);
8023         if (ret < 0)
8024                 return -ENOSYS;
8025         return 0;
8026 }
8027
8028 /*
8029  * Handle operations for ethertype filter.
8030  */
8031 static int
8032 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8033                                 enum rte_filter_op filter_op,
8034                                 void *arg)
8035 {
8036         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8037         int ret = 0;
8038
8039         if (filter_op == RTE_ETH_FILTER_NOP)
8040                 return ret;
8041
8042         if (arg == NULL) {
8043                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8044                             filter_op);
8045                 return -EINVAL;
8046         }
8047
8048         switch (filter_op) {
8049         case RTE_ETH_FILTER_ADD:
8050                 ret = i40e_ethertype_filter_set(pf,
8051                         (struct rte_eth_ethertype_filter *)arg,
8052                         TRUE);
8053                 break;
8054         case RTE_ETH_FILTER_DELETE:
8055                 ret = i40e_ethertype_filter_set(pf,
8056                         (struct rte_eth_ethertype_filter *)arg,
8057                         FALSE);
8058                 break;
8059         default:
8060                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8061                 ret = -ENOSYS;
8062                 break;
8063         }
8064         return ret;
8065 }
8066
8067 static int
8068 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8069                      enum rte_filter_type filter_type,
8070                      enum rte_filter_op filter_op,
8071                      void *arg)
8072 {
8073         int ret = 0;
8074
8075         if (dev == NULL)
8076                 return -EINVAL;
8077
8078         switch (filter_type) {
8079         case RTE_ETH_FILTER_NONE:
8080                 /* For global configuration */
8081                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8082                 break;
8083         case RTE_ETH_FILTER_HASH:
8084                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8085                 break;
8086         case RTE_ETH_FILTER_MACVLAN:
8087                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8088                 break;
8089         case RTE_ETH_FILTER_ETHERTYPE:
8090                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8091                 break;
8092         case RTE_ETH_FILTER_TUNNEL:
8093                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8094                 break;
8095         case RTE_ETH_FILTER_FDIR:
8096                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8097                 break;
8098         default:
8099                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8100                                                         filter_type);
8101                 ret = -EINVAL;
8102                 break;
8103         }
8104
8105         return ret;
8106 }
8107
8108 /*
8109  * Check and enable Extended Tag.
8110  * Enabling Extended Tag is important for 40G performance.
8111  */
8112 static void
8113 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8114 {
8115         uint32_t buf = 0;
8116         int ret;
8117
8118         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8119                                       PCI_DEV_CAP_REG);
8120         if (ret < 0) {
8121                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8122                             PCI_DEV_CAP_REG);
8123                 return;
8124         }
8125         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8126                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8127                 return;
8128         }
8129
8130         buf = 0;
8131         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8132                                       PCI_DEV_CTRL_REG);
8133         if (ret < 0) {
8134                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8135                             PCI_DEV_CTRL_REG);
8136                 return;
8137         }
8138         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8139                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8140                 return;
8141         }
8142         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8143         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8144                                        PCI_DEV_CTRL_REG);
8145         if (ret < 0) {
8146                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8147                             PCI_DEV_CTRL_REG);
8148                 return;
8149         }
8150 }
8151
8152 /*
8153  * As some registers wouldn't be reset unless a global hardware reset,
8154  * hardware initialization is needed to put those registers into an
8155  * expected initial state.
8156  */
8157 static void
8158 i40e_hw_init(struct rte_eth_dev *dev)
8159 {
8160         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8161
8162         i40e_enable_extended_tag(dev);
8163
8164         /* clear the PF Queue Filter control register */
8165         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8166
8167         /* Disable symmetric hash per port */
8168         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8169 }
8170
8171 enum i40e_filter_pctype
8172 i40e_flowtype_to_pctype(uint16_t flow_type)
8173 {
8174         static const enum i40e_filter_pctype pctype_table[] = {
8175                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8176                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8177                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8178                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8179                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8180                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8181                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8182                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8183                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8184                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8185                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8186                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8187                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8188                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8189                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8190                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8191                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8192                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8193                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8194         };
8195
8196         return pctype_table[flow_type];
8197 }
8198
8199 uint16_t
8200 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8201 {
8202         static const uint16_t flowtype_table[] = {
8203                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8204                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8205                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8206 #ifdef X722_SUPPORT
8207                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8208                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8209                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8210                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8211 #endif
8212                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8213                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8214 #ifdef X722_SUPPORT
8215                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8216                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8217 #endif
8218                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8219                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8220                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8221                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8222                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8223                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8224                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8225 #ifdef X722_SUPPORT
8226                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8227                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8228                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8229                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8230 #endif
8231                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8232                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8233 #ifdef X722_SUPPORT
8234                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8235                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8236 #endif
8237                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8238                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8239                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8240                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8241                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8242         };
8243
8244         return flowtype_table[pctype];
8245 }
8246
8247 /*
8248  * On X710, performance number is far from the expectation on recent firmware
8249  * versions; on XL710, performance number is also far from the expectation on
8250  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8251  * mode is enabled and port MAC address is equal to the packet destination MAC
8252  * address. The fix for this issue may not be integrated in the following
8253  * firmware version. So the workaround in software driver is needed. It needs
8254  * to modify the initial values of 3 internal only registers for both X710 and
8255  * XL710. Note that the values for X710 or XL710 could be different, and the
8256  * workaround can be removed when it is fixed in firmware in the future.
8257  */
8258
8259 /* For both X710 and XL710 */
8260 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8261 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8262
8263 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8264 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8265
8266 /* For X710 */
8267 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8268 /* For XL710 */
8269 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8270 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8271
8272 static int
8273 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8274 {
8275         enum i40e_status_code status;
8276         struct i40e_aq_get_phy_abilities_resp phy_ab;
8277         int ret = -ENOTSUP;
8278
8279         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8280                                               NULL);
8281
8282         if (status)
8283                 return ret;
8284
8285         return 0;
8286 }
8287
8288
8289 static void
8290 i40e_configure_registers(struct i40e_hw *hw)
8291 {
8292         static struct {
8293                 uint32_t addr;
8294                 uint64_t val;
8295         } reg_table[] = {
8296                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8297                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8298                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8299         };
8300         uint64_t reg;
8301         uint32_t i;
8302         int ret;
8303
8304         for (i = 0; i < RTE_DIM(reg_table); i++) {
8305                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8306                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8307                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8308                                 reg_table[i].val =
8309                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8310                         else /* For X710 */
8311                                 reg_table[i].val =
8312                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8313                 }
8314
8315                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8316                                                         &reg, NULL);
8317                 if (ret < 0) {
8318                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8319                                                         reg_table[i].addr);
8320                         break;
8321                 }
8322                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8323                                                 reg_table[i].addr, reg);
8324                 if (reg == reg_table[i].val)
8325                         continue;
8326
8327                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8328                                                 reg_table[i].val, NULL);
8329                 if (ret < 0) {
8330                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8331                                 "address of 0x%"PRIx32, reg_table[i].val,
8332                                                         reg_table[i].addr);
8333                         break;
8334                 }
8335                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8336                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8337         }
8338 }
8339
8340 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8341 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8342 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8343 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8344 static int
8345 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8346 {
8347         uint32_t reg;
8348         int ret;
8349
8350         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8351                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8352                 return -EINVAL;
8353         }
8354
8355         /* Configure for double VLAN RX stripping */
8356         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8357         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8358                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8359                 ret = i40e_aq_debug_write_register(hw,
8360                                                    I40E_VSI_TSR(vsi->vsi_id),
8361                                                    reg, NULL);
8362                 if (ret < 0) {
8363                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8364                                     vsi->vsi_id);
8365                         return I40E_ERR_CONFIG;
8366                 }
8367         }
8368
8369         /* Configure for double VLAN TX insertion */
8370         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8371         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8372                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8373                 ret = i40e_aq_debug_write_register(hw,
8374                                                    I40E_VSI_L2TAGSTXVALID(
8375                                                    vsi->vsi_id), reg, NULL);
8376                 if (ret < 0) {
8377                         PMD_DRV_LOG(ERR, "Failed to update "
8378                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8379                         return I40E_ERR_CONFIG;
8380                 }
8381         }
8382
8383         return 0;
8384 }
8385
8386 /**
8387  * i40e_aq_add_mirror_rule
8388  * @hw: pointer to the hardware structure
8389  * @seid: VEB seid to add mirror rule to
8390  * @dst_id: destination vsi seid
8391  * @entries: Buffer which contains the entities to be mirrored
8392  * @count: number of entities contained in the buffer
8393  * @rule_id:the rule_id of the rule to be added
8394  *
8395  * Add a mirror rule for a given veb.
8396  *
8397  **/
8398 static enum i40e_status_code
8399 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8400                         uint16_t seid, uint16_t dst_id,
8401                         uint16_t rule_type, uint16_t *entries,
8402                         uint16_t count, uint16_t *rule_id)
8403 {
8404         struct i40e_aq_desc desc;
8405         struct i40e_aqc_add_delete_mirror_rule cmd;
8406         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8407                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8408                 &desc.params.raw;
8409         uint16_t buff_len;
8410         enum i40e_status_code status;
8411
8412         i40e_fill_default_direct_cmd_desc(&desc,
8413                                           i40e_aqc_opc_add_mirror_rule);
8414         memset(&cmd, 0, sizeof(cmd));
8415
8416         buff_len = sizeof(uint16_t) * count;
8417         desc.datalen = rte_cpu_to_le_16(buff_len);
8418         if (buff_len > 0)
8419                 desc.flags |= rte_cpu_to_le_16(
8420                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8421         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8422                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8423         cmd.num_entries = rte_cpu_to_le_16(count);
8424         cmd.seid = rte_cpu_to_le_16(seid);
8425         cmd.destination = rte_cpu_to_le_16(dst_id);
8426
8427         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8428         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8429         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8430                          "rule_id = %u"
8431                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8432                          hw->aq.asq_last_status, resp->rule_id,
8433                          resp->mirror_rules_used, resp->mirror_rules_free);
8434         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8435
8436         return status;
8437 }
8438
8439 /**
8440  * i40e_aq_del_mirror_rule
8441  * @hw: pointer to the hardware structure
8442  * @seid: VEB seid to add mirror rule to
8443  * @entries: Buffer which contains the entities to be mirrored
8444  * @count: number of entities contained in the buffer
8445  * @rule_id:the rule_id of the rule to be delete
8446  *
8447  * Delete a mirror rule for a given veb.
8448  *
8449  **/
8450 static enum i40e_status_code
8451 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8452                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8453                 uint16_t count, uint16_t rule_id)
8454 {
8455         struct i40e_aq_desc desc;
8456         struct i40e_aqc_add_delete_mirror_rule cmd;
8457         uint16_t buff_len = 0;
8458         enum i40e_status_code status;
8459         void *buff = NULL;
8460
8461         i40e_fill_default_direct_cmd_desc(&desc,
8462                                           i40e_aqc_opc_delete_mirror_rule);
8463         memset(&cmd, 0, sizeof(cmd));
8464         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8465                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8466                                                           I40E_AQ_FLAG_RD));
8467                 cmd.num_entries = count;
8468                 buff_len = sizeof(uint16_t) * count;
8469                 desc.datalen = rte_cpu_to_le_16(buff_len);
8470                 buff = (void *)entries;
8471         } else
8472                 /* rule id is filled in destination field for deleting mirror rule */
8473                 cmd.destination = rte_cpu_to_le_16(rule_id);
8474
8475         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8476                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8477         cmd.seid = rte_cpu_to_le_16(seid);
8478
8479         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8480         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8481
8482         return status;
8483 }
8484
8485 /**
8486  * i40e_mirror_rule_set
8487  * @dev: pointer to the hardware structure
8488  * @mirror_conf: mirror rule info
8489  * @sw_id: mirror rule's sw_id
8490  * @on: enable/disable
8491  *
8492  * set a mirror rule.
8493  *
8494  **/
8495 static int
8496 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8497                         struct rte_eth_mirror_conf *mirror_conf,
8498                         uint8_t sw_id, uint8_t on)
8499 {
8500         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8501         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8502         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8503         struct i40e_mirror_rule *parent = NULL;
8504         uint16_t seid, dst_seid, rule_id;
8505         uint16_t i, j = 0;
8506         int ret;
8507
8508         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8509
8510         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8511                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8512                         " without veb or vfs.");
8513                 return -ENOSYS;
8514         }
8515         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8516                 PMD_DRV_LOG(ERR, "mirror table is full.");
8517                 return -ENOSPC;
8518         }
8519         if (mirror_conf->dst_pool > pf->vf_num) {
8520                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8521                                  mirror_conf->dst_pool);
8522                 return -EINVAL;
8523         }
8524
8525         seid = pf->main_vsi->veb->seid;
8526
8527         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8528                 if (sw_id <= it->index) {
8529                         mirr_rule = it;
8530                         break;
8531                 }
8532                 parent = it;
8533         }
8534         if (mirr_rule && sw_id == mirr_rule->index) {
8535                 if (on) {
8536                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8537                         return -EEXIST;
8538                 } else {
8539                         ret = i40e_aq_del_mirror_rule(hw, seid,
8540                                         mirr_rule->rule_type,
8541                                         mirr_rule->entries,
8542                                         mirr_rule->num_entries, mirr_rule->id);
8543                         if (ret < 0) {
8544                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8545                                                    " ret = %d, aq_err = %d.",
8546                                                    ret, hw->aq.asq_last_status);
8547                                 return -ENOSYS;
8548                         }
8549                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8550                         rte_free(mirr_rule);
8551                         pf->nb_mirror_rule--;
8552                         return 0;
8553                 }
8554         } else if (!on) {
8555                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8556                 return -ENOENT;
8557         }
8558
8559         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8560                                 sizeof(struct i40e_mirror_rule) , 0);
8561         if (!mirr_rule) {
8562                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8563                 return I40E_ERR_NO_MEMORY;
8564         }
8565         switch (mirror_conf->rule_type) {
8566         case ETH_MIRROR_VLAN:
8567                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8568                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8569                                 mirr_rule->entries[j] =
8570                                         mirror_conf->vlan.vlan_id[i];
8571                                 j++;
8572                         }
8573                 }
8574                 if (j == 0) {
8575                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8576                         rte_free(mirr_rule);
8577                         return -EINVAL;
8578                 }
8579                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8580                 break;
8581         case ETH_MIRROR_VIRTUAL_POOL_UP:
8582         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8583                 /* check if the specified pool bit is out of range */
8584                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8585                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8586                         rte_free(mirr_rule);
8587                         return -EINVAL;
8588                 }
8589                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8590                         if (mirror_conf->pool_mask & (1ULL << i)) {
8591                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8592                                 j++;
8593                         }
8594                 }
8595                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8596                         /* add pf vsi to entries */
8597                         mirr_rule->entries[j] = pf->main_vsi_seid;
8598                         j++;
8599                 }
8600                 if (j == 0) {
8601                         PMD_DRV_LOG(ERR, "pool is not specified.");
8602                         rte_free(mirr_rule);
8603                         return -EINVAL;
8604                 }
8605                 /* egress and ingress in aq commands means from switch but not port */
8606                 mirr_rule->rule_type =
8607                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8608                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8609                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8610                 break;
8611         case ETH_MIRROR_UPLINK_PORT:
8612                 /* egress and ingress in aq commands means from switch but not port*/
8613                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8614                 break;
8615         case ETH_MIRROR_DOWNLINK_PORT:
8616                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8617                 break;
8618         default:
8619                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8620                         mirror_conf->rule_type);
8621                 rte_free(mirr_rule);
8622                 return -EINVAL;
8623         }
8624
8625         /* If the dst_pool is equal to vf_num, consider it as PF */
8626         if (mirror_conf->dst_pool == pf->vf_num)
8627                 dst_seid = pf->main_vsi_seid;
8628         else
8629                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8630
8631         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8632                                       mirr_rule->rule_type, mirr_rule->entries,
8633                                       j, &rule_id);
8634         if (ret < 0) {
8635                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8636                                    " ret = %d, aq_err = %d.",
8637                                    ret, hw->aq.asq_last_status);
8638                 rte_free(mirr_rule);
8639                 return -ENOSYS;
8640         }
8641
8642         mirr_rule->index = sw_id;
8643         mirr_rule->num_entries = j;
8644         mirr_rule->id = rule_id;
8645         mirr_rule->dst_vsi_seid = dst_seid;
8646
8647         if (parent)
8648                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8649         else
8650                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8651
8652         pf->nb_mirror_rule++;
8653         return 0;
8654 }
8655
8656 /**
8657  * i40e_mirror_rule_reset
8658  * @dev: pointer to the device
8659  * @sw_id: mirror rule's sw_id
8660  *
8661  * reset a mirror rule.
8662  *
8663  **/
8664 static int
8665 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8666 {
8667         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8668         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8669         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8670         uint16_t seid;
8671         int ret;
8672
8673         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8674
8675         seid = pf->main_vsi->veb->seid;
8676
8677         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8678                 if (sw_id == it->index) {
8679                         mirr_rule = it;
8680                         break;
8681                 }
8682         }
8683         if (mirr_rule) {
8684                 ret = i40e_aq_del_mirror_rule(hw, seid,
8685                                 mirr_rule->rule_type,
8686                                 mirr_rule->entries,
8687                                 mirr_rule->num_entries, mirr_rule->id);
8688                 if (ret < 0) {
8689                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8690                                            " status = %d, aq_err = %d.",
8691                                            ret, hw->aq.asq_last_status);
8692                         return -ENOSYS;
8693                 }
8694                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8695                 rte_free(mirr_rule);
8696                 pf->nb_mirror_rule--;
8697         } else {
8698                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8699                 return -ENOENT;
8700         }
8701         return 0;
8702 }
8703
8704 static uint64_t
8705 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8706 {
8707         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8708         uint64_t systim_cycles;
8709
8710         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8711         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8712                         << 32;
8713
8714         return systim_cycles;
8715 }
8716
8717 static uint64_t
8718 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8719 {
8720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8721         uint64_t rx_tstamp;
8722
8723         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8724         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8725                         << 32;
8726
8727         return rx_tstamp;
8728 }
8729
8730 static uint64_t
8731 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8732 {
8733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8734         uint64_t tx_tstamp;
8735
8736         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8737         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8738                         << 32;
8739
8740         return tx_tstamp;
8741 }
8742
8743 static void
8744 i40e_start_timecounters(struct rte_eth_dev *dev)
8745 {
8746         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8747         struct i40e_adapter *adapter =
8748                         (struct i40e_adapter *)dev->data->dev_private;
8749         struct rte_eth_link link;
8750         uint32_t tsync_inc_l;
8751         uint32_t tsync_inc_h;
8752
8753         /* Get current link speed. */
8754         memset(&link, 0, sizeof(link));
8755         i40e_dev_link_update(dev, 1);
8756         rte_i40e_dev_atomic_read_link_status(dev, &link);
8757
8758         switch (link.link_speed) {
8759         case ETH_SPEED_NUM_40G:
8760                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8761                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8762                 break;
8763         case ETH_SPEED_NUM_10G:
8764                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8765                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8766                 break;
8767         case ETH_SPEED_NUM_1G:
8768                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8769                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8770                 break;
8771         default:
8772                 tsync_inc_l = 0x0;
8773                 tsync_inc_h = 0x0;
8774         }
8775
8776         /* Set the timesync increment value. */
8777         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8778         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8779
8780         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8781         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8782         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8783
8784         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8785         adapter->systime_tc.cc_shift = 0;
8786         adapter->systime_tc.nsec_mask = 0;
8787
8788         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8789         adapter->rx_tstamp_tc.cc_shift = 0;
8790         adapter->rx_tstamp_tc.nsec_mask = 0;
8791
8792         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8793         adapter->tx_tstamp_tc.cc_shift = 0;
8794         adapter->tx_tstamp_tc.nsec_mask = 0;
8795 }
8796
8797 static int
8798 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8799 {
8800         struct i40e_adapter *adapter =
8801                         (struct i40e_adapter *)dev->data->dev_private;
8802
8803         adapter->systime_tc.nsec += delta;
8804         adapter->rx_tstamp_tc.nsec += delta;
8805         adapter->tx_tstamp_tc.nsec += delta;
8806
8807         return 0;
8808 }
8809
8810 static int
8811 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8812 {
8813         uint64_t ns;
8814         struct i40e_adapter *adapter =
8815                         (struct i40e_adapter *)dev->data->dev_private;
8816
8817         ns = rte_timespec_to_ns(ts);
8818
8819         /* Set the timecounters to a new value. */
8820         adapter->systime_tc.nsec = ns;
8821         adapter->rx_tstamp_tc.nsec = ns;
8822         adapter->tx_tstamp_tc.nsec = ns;
8823
8824         return 0;
8825 }
8826
8827 static int
8828 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8829 {
8830         uint64_t ns, systime_cycles;
8831         struct i40e_adapter *adapter =
8832                         (struct i40e_adapter *)dev->data->dev_private;
8833
8834         systime_cycles = i40e_read_systime_cyclecounter(dev);
8835         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8836         *ts = rte_ns_to_timespec(ns);
8837
8838         return 0;
8839 }
8840
8841 static int
8842 i40e_timesync_enable(struct rte_eth_dev *dev)
8843 {
8844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8845         uint32_t tsync_ctl_l;
8846         uint32_t tsync_ctl_h;
8847
8848         /* Stop the timesync system time. */
8849         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8850         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8851         /* Reset the timesync system time value. */
8852         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8853         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8854
8855         i40e_start_timecounters(dev);
8856
8857         /* Clear timesync registers. */
8858         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8859         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8860         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8861         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8862         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8863         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8864
8865         /* Enable timestamping of PTP packets. */
8866         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8867         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8868
8869         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8870         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8871         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8872
8873         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8874         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8875
8876         return 0;
8877 }
8878
8879 static int
8880 i40e_timesync_disable(struct rte_eth_dev *dev)
8881 {
8882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8883         uint32_t tsync_ctl_l;
8884         uint32_t tsync_ctl_h;
8885
8886         /* Disable timestamping of transmitted PTP packets. */
8887         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8888         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8889
8890         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8891         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8892
8893         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8894         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8895
8896         /* Reset the timesync increment value. */
8897         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8898         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8899
8900         return 0;
8901 }
8902
8903 static int
8904 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8905                                 struct timespec *timestamp, uint32_t flags)
8906 {
8907         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8908         struct i40e_adapter *adapter =
8909                 (struct i40e_adapter *)dev->data->dev_private;
8910
8911         uint32_t sync_status;
8912         uint32_t index = flags & 0x03;
8913         uint64_t rx_tstamp_cycles;
8914         uint64_t ns;
8915
8916         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8917         if ((sync_status & (1 << index)) == 0)
8918                 return -EINVAL;
8919
8920         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8921         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8922         *timestamp = rte_ns_to_timespec(ns);
8923
8924         return 0;
8925 }
8926
8927 static int
8928 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8929                                 struct timespec *timestamp)
8930 {
8931         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8932         struct i40e_adapter *adapter =
8933                 (struct i40e_adapter *)dev->data->dev_private;
8934
8935         uint32_t sync_status;
8936         uint64_t tx_tstamp_cycles;
8937         uint64_t ns;
8938
8939         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8940         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8941                 return -EINVAL;
8942
8943         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8944         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8945         *timestamp = rte_ns_to_timespec(ns);
8946
8947         return 0;
8948 }
8949
8950 /*
8951  * i40e_parse_dcb_configure - parse dcb configure from user
8952  * @dev: the device being configured
8953  * @dcb_cfg: pointer of the result of parse
8954  * @*tc_map: bit map of enabled traffic classes
8955  *
8956  * Returns 0 on success, negative value on failure
8957  */
8958 static int
8959 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8960                          struct i40e_dcbx_config *dcb_cfg,
8961                          uint8_t *tc_map)
8962 {
8963         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8964         uint8_t i, tc_bw, bw_lf;
8965
8966         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8967
8968         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8969         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8970                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8971                 return -EINVAL;
8972         }
8973
8974         /* assume each tc has the same bw */
8975         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8976         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8977                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8978         /* to ensure the sum of tcbw is equal to 100 */
8979         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8980         for (i = 0; i < bw_lf; i++)
8981                 dcb_cfg->etscfg.tcbwtable[i]++;
8982
8983         /* assume each tc has the same Transmission Selection Algorithm */
8984         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8985                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8986
8987         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8988                 dcb_cfg->etscfg.prioritytable[i] =
8989                                 dcb_rx_conf->dcb_tc[i];
8990
8991         /* FW needs one App to configure HW */
8992         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8993         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8994         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8995         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8996
8997         if (dcb_rx_conf->nb_tcs == 0)
8998                 *tc_map = 1; /* tc0 only */
8999         else
9000                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9001
9002         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9003                 dcb_cfg->pfc.willing = 0;
9004                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9005                 dcb_cfg->pfc.pfcenable = *tc_map;
9006         }
9007         return 0;
9008 }
9009
9010
9011 static enum i40e_status_code
9012 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9013                               struct i40e_aqc_vsi_properties_data *info,
9014                               uint8_t enabled_tcmap)
9015 {
9016         enum i40e_status_code ret;
9017         int i, total_tc = 0;
9018         uint16_t qpnum_per_tc, bsf, qp_idx;
9019         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9020         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9021         uint16_t used_queues;
9022
9023         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9024         if (ret != I40E_SUCCESS)
9025                 return ret;
9026
9027         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9028                 if (enabled_tcmap & (1 << i))
9029                         total_tc++;
9030         }
9031         if (total_tc == 0)
9032                 total_tc = 1;
9033         vsi->enabled_tc = enabled_tcmap;
9034
9035         /* different VSI has different queues assigned */
9036         if (vsi->type == I40E_VSI_MAIN)
9037                 used_queues = dev_data->nb_rx_queues -
9038                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9039         else if (vsi->type == I40E_VSI_VMDQ2)
9040                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9041         else {
9042                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9043                 return I40E_ERR_NO_AVAILABLE_VSI;
9044         }
9045
9046         qpnum_per_tc = used_queues / total_tc;
9047         /* Number of queues per enabled TC */
9048         if (qpnum_per_tc == 0) {
9049                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9050                 return I40E_ERR_INVALID_QP_ID;
9051         }
9052         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9053                                 I40E_MAX_Q_PER_TC);
9054         bsf = rte_bsf32(qpnum_per_tc);
9055
9056         /**
9057          * Configure TC and queue mapping parameters, for enabled TC,
9058          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9059          * default queue will serve it.
9060          */
9061         qp_idx = 0;
9062         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9063                 if (vsi->enabled_tc & (1 << i)) {
9064                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9065                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9066                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9067                         qp_idx += qpnum_per_tc;
9068                 } else
9069                         info->tc_mapping[i] = 0;
9070         }
9071
9072         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9073         if (vsi->type == I40E_VSI_SRIOV) {
9074                 info->mapping_flags |=
9075                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9076                 for (i = 0; i < vsi->nb_qps; i++)
9077                         info->queue_mapping[i] =
9078                                 rte_cpu_to_le_16(vsi->base_queue + i);
9079         } else {
9080                 info->mapping_flags |=
9081                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9082                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9083         }
9084         info->valid_sections |=
9085                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9086
9087         return I40E_SUCCESS;
9088 }
9089
9090 /*
9091  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9092  * @veb: VEB to be configured
9093  * @tc_map: enabled TC bitmap
9094  *
9095  * Returns 0 on success, negative value on failure
9096  */
9097 static enum i40e_status_code
9098 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9099 {
9100         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9101         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9102         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9103         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9104         enum i40e_status_code ret = I40E_SUCCESS;
9105         int i;
9106         uint32_t bw_max;
9107
9108         /* Check if enabled_tc is same as existing or new TCs */
9109         if (veb->enabled_tc == tc_map)
9110                 return ret;
9111
9112         /* configure tc bandwidth */
9113         memset(&veb_bw, 0, sizeof(veb_bw));
9114         veb_bw.tc_valid_bits = tc_map;
9115         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9116         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9117                 if (tc_map & BIT_ULL(i))
9118                         veb_bw.tc_bw_share_credits[i] = 1;
9119         }
9120         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9121                                                    &veb_bw, NULL);
9122         if (ret) {
9123                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9124                                   " per TC failed = %d",
9125                                   hw->aq.asq_last_status);
9126                 return ret;
9127         }
9128
9129         memset(&ets_query, 0, sizeof(ets_query));
9130         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9131                                                    &ets_query, NULL);
9132         if (ret != I40E_SUCCESS) {
9133                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9134                                  " configuration %u", hw->aq.asq_last_status);
9135                 return ret;
9136         }
9137         memset(&bw_query, 0, sizeof(bw_query));
9138         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9139                                                   &bw_query, NULL);
9140         if (ret != I40E_SUCCESS) {
9141                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9142                                  " configuration %u", hw->aq.asq_last_status);
9143                 return ret;
9144         }
9145
9146         /* store and print out BW info */
9147         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9148         veb->bw_info.bw_max = ets_query.tc_bw_max;
9149         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9150         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9151         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9152                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9153                      I40E_16_BIT_WIDTH);
9154         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9155                 veb->bw_info.bw_ets_share_credits[i] =
9156                                 bw_query.tc_bw_share_credits[i];
9157                 veb->bw_info.bw_ets_credits[i] =
9158                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9159                 /* 4 bits per TC, 4th bit is reserved */
9160                 veb->bw_info.bw_ets_max[i] =
9161                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9162                                   RTE_LEN2MASK(3, uint8_t));
9163                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9164                             veb->bw_info.bw_ets_share_credits[i]);
9165                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9166                             veb->bw_info.bw_ets_credits[i]);
9167                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9168                             veb->bw_info.bw_ets_max[i]);
9169         }
9170
9171         veb->enabled_tc = tc_map;
9172
9173         return ret;
9174 }
9175
9176
9177 /*
9178  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9179  * @vsi: VSI to be configured
9180  * @tc_map: enabled TC bitmap
9181  *
9182  * Returns 0 on success, negative value on failure
9183  */
9184 static enum i40e_status_code
9185 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9186 {
9187         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9188         struct i40e_vsi_context ctxt;
9189         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9190         enum i40e_status_code ret = I40E_SUCCESS;
9191         int i;
9192
9193         /* Check if enabled_tc is same as existing or new TCs */
9194         if (vsi->enabled_tc == tc_map)
9195                 return ret;
9196
9197         /* configure tc bandwidth */
9198         memset(&bw_data, 0, sizeof(bw_data));
9199         bw_data.tc_valid_bits = tc_map;
9200         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9201         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9202                 if (tc_map & BIT_ULL(i))
9203                         bw_data.tc_bw_credits[i] = 1;
9204         }
9205         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9206         if (ret) {
9207                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9208                         " per TC failed = %d",
9209                         hw->aq.asq_last_status);
9210                 goto out;
9211         }
9212         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9213                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9214
9215         /* Update Queue Pairs Mapping for currently enabled UPs */
9216         ctxt.seid = vsi->seid;
9217         ctxt.pf_num = hw->pf_id;
9218         ctxt.vf_num = 0;
9219         ctxt.uplink_seid = vsi->uplink_seid;
9220         ctxt.info = vsi->info;
9221         i40e_get_cap(hw);
9222         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9223         if (ret)
9224                 goto out;
9225
9226         /* Update the VSI after updating the VSI queue-mapping information */
9227         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9228         if (ret) {
9229                 PMD_INIT_LOG(ERR, "Failed to configure "
9230                             "TC queue mapping = %d",
9231                             hw->aq.asq_last_status);
9232                 goto out;
9233         }
9234         /* update the local VSI info with updated queue map */
9235         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9236                                         sizeof(vsi->info.tc_mapping));
9237         (void)rte_memcpy(&vsi->info.queue_mapping,
9238                         &ctxt.info.queue_mapping,
9239                 sizeof(vsi->info.queue_mapping));
9240         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9241         vsi->info.valid_sections = 0;
9242
9243         /* query and update current VSI BW information */
9244         ret = i40e_vsi_get_bw_config(vsi);
9245         if (ret) {
9246                 PMD_INIT_LOG(ERR,
9247                          "Failed updating vsi bw info, err %s aq_err %s",
9248                          i40e_stat_str(hw, ret),
9249                          i40e_aq_str(hw, hw->aq.asq_last_status));
9250                 goto out;
9251         }
9252
9253         vsi->enabled_tc = tc_map;
9254
9255 out:
9256         return ret;
9257 }
9258
9259 /*
9260  * i40e_dcb_hw_configure - program the dcb setting to hw
9261  * @pf: pf the configuration is taken on
9262  * @new_cfg: new configuration
9263  * @tc_map: enabled TC bitmap
9264  *
9265  * Returns 0 on success, negative value on failure
9266  */
9267 static enum i40e_status_code
9268 i40e_dcb_hw_configure(struct i40e_pf *pf,
9269                       struct i40e_dcbx_config *new_cfg,
9270                       uint8_t tc_map)
9271 {
9272         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9273         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9274         struct i40e_vsi *main_vsi = pf->main_vsi;
9275         struct i40e_vsi_list *vsi_list;
9276         enum i40e_status_code ret;
9277         int i;
9278         uint32_t val;
9279
9280         /* Use the FW API if FW > v4.4*/
9281         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9282               (hw->aq.fw_maj_ver >= 5))) {
9283                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9284                                   " to configure DCB");
9285                 return I40E_ERR_FIRMWARE_API_VERSION;
9286         }
9287
9288         /* Check if need reconfiguration */
9289         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9290                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9291                 return I40E_SUCCESS;
9292         }
9293
9294         /* Copy the new config to the current config */
9295         *old_cfg = *new_cfg;
9296         old_cfg->etsrec = old_cfg->etscfg;
9297         ret = i40e_set_dcb_config(hw);
9298         if (ret) {
9299                 PMD_INIT_LOG(ERR,
9300                          "Set DCB Config failed, err %s aq_err %s\n",
9301                          i40e_stat_str(hw, ret),
9302                          i40e_aq_str(hw, hw->aq.asq_last_status));
9303                 return ret;
9304         }
9305         /* set receive Arbiter to RR mode and ETS scheme by default */
9306         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9307                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9308                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9309                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9310                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9311                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9312                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9313                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9314                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9315                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9316                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9317                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9318                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9319         }
9320         /* get local mib to check whether it is configured correctly */
9321         /* IEEE mode */
9322         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9323         /* Get Local DCB Config */
9324         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9325                                      &hw->local_dcbx_config);
9326
9327         /* if Veb is created, need to update TC of it at first */
9328         if (main_vsi->veb) {
9329                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9330                 if (ret)
9331                         PMD_INIT_LOG(WARNING,
9332                                  "Failed configuring TC for VEB seid=%d\n",
9333                                  main_vsi->veb->seid);
9334         }
9335         /* Update each VSI */
9336         i40e_vsi_config_tc(main_vsi, tc_map);
9337         if (main_vsi->veb) {
9338                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9339                         /* Beside main VSI and VMDQ VSIs, only enable default
9340                          * TC for other VSIs
9341                          */
9342                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9343                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9344                                                          tc_map);
9345                         else
9346                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9347                                                          I40E_DEFAULT_TCMAP);
9348                         if (ret)
9349                                 PMD_INIT_LOG(WARNING,
9350                                          "Failed configuring TC for VSI seid=%d\n",
9351                                          vsi_list->vsi->seid);
9352                         /* continue */
9353                 }
9354         }
9355         return I40E_SUCCESS;
9356 }
9357
9358 /*
9359  * i40e_dcb_init_configure - initial dcb config
9360  * @dev: device being configured
9361  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9362  *
9363  * Returns 0 on success, negative value on failure
9364  */
9365 static int
9366 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9367 {
9368         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9369         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9370         int ret = 0;
9371
9372         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9373                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9374                 return -ENOTSUP;
9375         }
9376
9377         /* DCB initialization:
9378          * Update DCB configuration from the Firmware and configure
9379          * LLDP MIB change event.
9380          */
9381         if (sw_dcb == TRUE) {
9382                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9383                 if (ret != I40E_SUCCESS)
9384                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9385
9386                 ret = i40e_init_dcb(hw);
9387                 /* if sw_dcb, lldp agent is stopped, the return from
9388                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9389                  * adminq status.
9390                  */
9391                 if (ret != I40E_SUCCESS &&
9392                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9393                         memset(&hw->local_dcbx_config, 0,
9394                                 sizeof(struct i40e_dcbx_config));
9395                         /* set dcb default configuration */
9396                         hw->local_dcbx_config.etscfg.willing = 0;
9397                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9398                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9399                         hw->local_dcbx_config.etscfg.tsatable[0] =
9400                                                 I40E_IEEE_TSA_ETS;
9401                         hw->local_dcbx_config.etsrec =
9402                                 hw->local_dcbx_config.etscfg;
9403                         hw->local_dcbx_config.pfc.willing = 0;
9404                         hw->local_dcbx_config.pfc.pfccap =
9405                                                 I40E_MAX_TRAFFIC_CLASS;
9406                         /* FW needs one App to configure HW */
9407                         hw->local_dcbx_config.numapps = 1;
9408                         hw->local_dcbx_config.app[0].selector =
9409                                                 I40E_APP_SEL_ETHTYPE;
9410                         hw->local_dcbx_config.app[0].priority = 3;
9411                         hw->local_dcbx_config.app[0].protocolid =
9412                                                 I40E_APP_PROTOID_FCOE;
9413                         ret = i40e_set_dcb_config(hw);
9414                         if (ret) {
9415                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9416                                         " err = %d, aq_err = %d.", ret,
9417                                           hw->aq.asq_last_status);
9418                                 return -ENOSYS;
9419                         }
9420                 } else {
9421                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9422                                           " aq_err = %d.", ret,
9423                                           hw->aq.asq_last_status);
9424                         return -ENOTSUP;
9425                 }
9426         } else {
9427                 ret = i40e_aq_start_lldp(hw, NULL);
9428                 if (ret != I40E_SUCCESS)
9429                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9430
9431                 ret = i40e_init_dcb(hw);
9432                 if (!ret) {
9433                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9434                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9435                                                   " DCBX offload.");
9436                                 return -ENOTSUP;
9437                         }
9438                 } else {
9439                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9440                                           " aq_err = %d.", ret,
9441                                           hw->aq.asq_last_status);
9442                         return -ENOTSUP;
9443                 }
9444         }
9445         return 0;
9446 }
9447
9448 /*
9449  * i40e_dcb_setup - setup dcb related config
9450  * @dev: device being configured
9451  *
9452  * Returns 0 on success, negative value on failure
9453  */
9454 static int
9455 i40e_dcb_setup(struct rte_eth_dev *dev)
9456 {
9457         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9458         struct i40e_dcbx_config dcb_cfg;
9459         uint8_t tc_map = 0;
9460         int ret = 0;
9461
9462         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9463                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9464                 return -ENOTSUP;
9465         }
9466
9467         if (pf->vf_num != 0)
9468                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9469
9470         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9471         if (ret) {
9472                 PMD_INIT_LOG(ERR, "invalid dcb config");
9473                 return -EINVAL;
9474         }
9475         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9476         if (ret) {
9477                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9478                 return -ENOSYS;
9479         }
9480
9481         return 0;
9482 }
9483
9484 static int
9485 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9486                       struct rte_eth_dcb_info *dcb_info)
9487 {
9488         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9490         struct i40e_vsi *vsi = pf->main_vsi;
9491         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9492         uint16_t bsf, tc_mapping;
9493         int i, j = 0;
9494
9495         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9496                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9497         else
9498                 dcb_info->nb_tcs = 1;
9499         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9500                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9501         for (i = 0; i < dcb_info->nb_tcs; i++)
9502                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9503
9504         /* get queue mapping if vmdq is disabled */
9505         if (!pf->nb_cfg_vmdq_vsi) {
9506                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9507                         if (!(vsi->enabled_tc & (1 << i)))
9508                                 continue;
9509                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9510                         dcb_info->tc_queue.tc_rxq[j][i].base =
9511                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9512                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9513                         dcb_info->tc_queue.tc_txq[j][i].base =
9514                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9515                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9516                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9517                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9518                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9519                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9520                 }
9521                 return 0;
9522         }
9523
9524         /* get queue mapping if vmdq is enabled */
9525         do {
9526                 vsi = pf->vmdq[j].vsi;
9527                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9528                         if (!(vsi->enabled_tc & (1 << i)))
9529                                 continue;
9530                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9531                         dcb_info->tc_queue.tc_rxq[j][i].base =
9532                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9533                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9534                         dcb_info->tc_queue.tc_txq[j][i].base =
9535                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9536                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9537                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9538                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9539                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9540                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9541                 }
9542                 j++;
9543         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9544         return 0;
9545 }
9546
9547 static int
9548 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9549 {
9550         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9551         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9552         uint16_t interval =
9553                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9554         uint16_t msix_intr;
9555
9556         msix_intr = intr_handle->intr_vec[queue_id];
9557         if (msix_intr == I40E_MISC_VEC_ID)
9558                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9559                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9560                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9561                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9562                                (interval <<
9563                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9564         else
9565                 I40E_WRITE_REG(hw,
9566                                I40E_PFINT_DYN_CTLN(msix_intr -
9567                                                    I40E_RX_VEC_START),
9568                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9569                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9570                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9571                                (interval <<
9572                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9573
9574         I40E_WRITE_FLUSH(hw);
9575         rte_intr_enable(&dev->pci_dev->intr_handle);
9576
9577         return 0;
9578 }
9579
9580 static int
9581 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9582 {
9583         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9585         uint16_t msix_intr;
9586
9587         msix_intr = intr_handle->intr_vec[queue_id];
9588         if (msix_intr == I40E_MISC_VEC_ID)
9589                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9590         else
9591                 I40E_WRITE_REG(hw,
9592                                I40E_PFINT_DYN_CTLN(msix_intr -
9593                                                    I40E_RX_VEC_START),
9594                                0);
9595         I40E_WRITE_FLUSH(hw);
9596
9597         return 0;
9598 }
9599
9600 static int i40e_get_regs(struct rte_eth_dev *dev,
9601                          struct rte_dev_reg_info *regs)
9602 {
9603         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9604         uint32_t *ptr_data = regs->data;
9605         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9606         const struct i40e_reg_info *reg_info;
9607
9608         if (ptr_data == NULL) {
9609                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9610                 regs->width = sizeof(uint32_t);
9611                 return 0;
9612         }
9613
9614         /* The first few registers have to be read using AQ operations */
9615         reg_idx = 0;
9616         while (i40e_regs_adminq[reg_idx].name) {
9617                 reg_info = &i40e_regs_adminq[reg_idx++];
9618                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9619                         for (arr_idx2 = 0;
9620                                         arr_idx2 <= reg_info->count2;
9621                                         arr_idx2++) {
9622                                 reg_offset = arr_idx * reg_info->stride1 +
9623                                         arr_idx2 * reg_info->stride2;
9624                                 reg_offset += reg_info->base_addr;
9625                                 ptr_data[reg_offset >> 2] =
9626                                         i40e_read_rx_ctl(hw, reg_offset);
9627                         }
9628         }
9629
9630         /* The remaining registers can be read using primitives */
9631         reg_idx = 0;
9632         while (i40e_regs_others[reg_idx].name) {
9633                 reg_info = &i40e_regs_others[reg_idx++];
9634                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9635                         for (arr_idx2 = 0;
9636                                         arr_idx2 <= reg_info->count2;
9637                                         arr_idx2++) {
9638                                 reg_offset = arr_idx * reg_info->stride1 +
9639                                         arr_idx2 * reg_info->stride2;
9640                                 reg_offset += reg_info->base_addr;
9641                                 ptr_data[reg_offset >> 2] =
9642                                         I40E_READ_REG(hw, reg_offset);
9643                         }
9644         }
9645
9646         return 0;
9647 }
9648
9649 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9650 {
9651         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9652
9653         /* Convert word count to byte count */
9654         return hw->nvm.sr_size << 1;
9655 }
9656
9657 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9658                            struct rte_dev_eeprom_info *eeprom)
9659 {
9660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9661         uint16_t *data = eeprom->data;
9662         uint16_t offset, length, cnt_words;
9663         int ret_code;
9664
9665         offset = eeprom->offset >> 1;
9666         length = eeprom->length >> 1;
9667         cnt_words = length;
9668
9669         if (offset > hw->nvm.sr_size ||
9670                 offset + length > hw->nvm.sr_size) {
9671                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9672                 return -EINVAL;
9673         }
9674
9675         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9676
9677         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9678         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9679                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9680                 return -EIO;
9681         }
9682
9683         return 0;
9684 }
9685
9686 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9687                                       struct ether_addr *mac_addr)
9688 {
9689         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9690
9691         if (!is_valid_assigned_ether_addr(mac_addr)) {
9692                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9693                 return;
9694         }
9695
9696         /* Flags: 0x3 updates port address */
9697         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9698 }
9699
9700 static int
9701 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9702 {
9703         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9704         struct rte_eth_dev_data *dev_data = pf->dev_data;
9705         uint32_t frame_size = mtu + ETHER_HDR_LEN
9706                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9707         int ret = 0;
9708
9709         /* check if mtu is within the allowed range */
9710         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9711                 return -EINVAL;
9712
9713         /* mtu setting is forbidden if port is start */
9714         if (dev_data->dev_started) {
9715                 PMD_DRV_LOG(ERR,
9716                             "port %d must be stopped before configuration\n",
9717                             dev_data->port_id);
9718                 return -EBUSY;
9719         }
9720
9721         if (frame_size > ETHER_MAX_LEN)
9722                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9723         else
9724                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9725
9726         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9727
9728         return ret;
9729 }