drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 /* Additional timesync values. */
 129 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 130 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 131 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 132 #define I40E_PRTTSYN_TSYNENA     0x80000000
 133 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 134 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffff
 135
 136 #define I40E_MAX_PERCENT            100
 137 #define I40E_DEFAULT_DCB_APP_NUM    1
 138 #define I40E_DEFAULT_DCB_APP_PRIO   3
 139
 140 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 141 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 143 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 144 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 145 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 146
 147 #define I40E_INSET_NONE            0x00000000000000000ULL
 148
 149 /* bit0 ~ bit 7 */
 150 #define I40E_INSET_DMAC            0x0000000000000001ULL
 151 #define I40E_INSET_SMAC            0x0000000000000002ULL
 152 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 153 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 154 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 155
 156 /* bit 8 ~ bit 15 */
 157 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 158 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 159 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 160 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 161 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 162 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 163 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 164
 165 /* bit 16 ~ bit 31 */
 166 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 167 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 168 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 169 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 170 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 171 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 172 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 173 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 174
 175 /* bit 32 ~ bit 47, tunnel fields */
 176 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 177 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 178 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 179 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 180 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 181 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 182
 183 /* bit 48 ~ bit 55 */
 184 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 185
 186 /* bit 56 ~ bit 63, Flex Payload */
 187 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 194 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 195 #define I40E_INSET_FLEX_PAYLOAD \
 196         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 197         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 198         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 199         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 200
 201 /**
 202  * Below are values for writing un-exposed registers suggested
 203  * by silicon experts
 204  */
 205 /* Destination MAC address */
 206 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 207 /* Source MAC address */
 208 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 209 /* VLAN tag in the outer L2 header */
 210 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 211 /* VLAN tag in the inner L2 header */
 212 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 213 /* Source IPv4 address */
 214 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 215 /* Destination IPv4 address */
 216 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 217 /* IPv4 Type of Service (TOS) */
 218 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 219 /* IPv4 Protocol */
 220 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 221 /* Source IPv6 address */
 222 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 223 /* Destination IPv6 address */
 224 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 225 /* IPv6 Traffic Class (TC) */
 226 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 227 /* IPv6 Next Header */
 228 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 229 /* Source L4 port */
 230 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 231 /* Destination L4 port */
 232 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 233 /* SCTP verification tag */
 234 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 235 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 236 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 237 /* Source port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 239 /* Destination port of tunneling UDP */
 240 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 241 /* UDP Tunneling ID, NVGRE/GRE key */
 242 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 243 /* Last ether type */
 244 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 245 /* Tunneling outer destination IPv4 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 247 /* Tunneling outer destination IPv6 address */
 248 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 249 /* 1st word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 251 /* 2nd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 253 /* 3rd word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 255 /* 4th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 257 /* 5th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 259 /* 6th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 261 /* 7th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 263 /* 8th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 265
 266 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 267
 268 #define I40E_TRANSLATE_INSET 0
 269 #define I40E_TRANSLATE_REG   1
 270
 271 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 272 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 273 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 274 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 275
 276 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 277 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 278 static int i40e_dev_configure(struct rte_eth_dev *dev);
 279 static int i40e_dev_start(struct rte_eth_dev *dev);
 280 static void i40e_dev_stop(struct rte_eth_dev *dev);
 281 static void i40e_dev_close(struct rte_eth_dev *dev);
 282 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 284 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 285 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 286 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 287 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 288 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_stats *stats);
 290 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 291                                struct rte_eth_xstats *xstats, unsigned n);
 292 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 293 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 294                                             uint16_t queue_id,
 295                                             uint8_t stat_idx,
 296                                             uint8_t is_rx);
 297 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 298                               struct rte_eth_dev_info *dev_info);
 299 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 300                                 uint16_t vlan_id,
 301                                 int on);
 302 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 303 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 304 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 305                                       uint16_t queue,
 306                                       int on);
 307 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 308 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 309 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 310 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 311                               struct rte_eth_fc_conf *fc_conf);
 312 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 313                               struct rte_eth_fc_conf *fc_conf);
 314 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 315                                        struct rte_eth_pfc_conf *pfc_conf);
 316 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 317                           struct ether_addr *mac_addr,
 318                           uint32_t index,
 319                           uint32_t pool);
 320 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 321 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 322                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 323                                     uint16_t reta_size);
 324 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 325                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 326                                    uint16_t reta_size);
 327
 328 static int i40e_get_cap(struct i40e_hw *hw);
 329 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 330 static int i40e_pf_setup(struct i40e_pf *pf);
 331 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 332 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 333 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 334 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 335 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 336                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 337 static void i40e_stat_update_48(struct i40e_hw *hw,
 338                                uint32_t hireg,
 339                                uint32_t loreg,
 340                                bool offset_loaded,
 341                                uint64_t *offset,
 342                                uint64_t *stat);
 343 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 344 static void i40e_dev_interrupt_handler(
 345                 __rte_unused struct rte_intr_handle *handle, void *param);
 346 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 347                                 uint32_t base, uint32_t num);
 348 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 349 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 350                         uint32_t base);
 351 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 352                         uint16_t num);
 353 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 354 static int i40e_veb_release(struct i40e_veb *veb);
 355 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 356                                                 struct i40e_vsi *vsi);
 357 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 358 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 359 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 360                                              struct i40e_macvlan_filter *mv_f,
 361                                              int num,
 362                                              struct ether_addr *addr);
 363 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 364                                              struct i40e_macvlan_filter *mv_f,
 365                                              int num,
 366                                              uint16_t vlan);
 367 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 368 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 369                                     struct rte_eth_rss_conf *rss_conf);
 370 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 371                                       struct rte_eth_rss_conf *rss_conf);
 372 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 373                                 struct rte_eth_udp_tunnel *udp_tunnel);
 374 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 375                                 struct rte_eth_udp_tunnel *udp_tunnel);
 376 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 377                         struct rte_eth_ethertype_filter *filter,
 378                         bool add);
 379 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 380                                 enum rte_filter_op filter_op,
 381                                 void *arg);
 382 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 383                                 enum rte_filter_type filter_type,
 384                                 enum rte_filter_op filter_op,
 385                                 void *arg);
 386 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 387                                   struct rte_eth_dcb_info *dcb_info);
 388 static void i40e_configure_registers(struct i40e_hw *hw);
 389 static void i40e_hw_init(struct i40e_hw *hw);
 390 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 391 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 392                         struct rte_eth_mirror_conf *mirror_conf,
 393                         uint8_t sw_id, uint8_t on);
 394 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 395
 396 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 397 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 398 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 399                                            struct timespec *timestamp,
 400                                            uint32_t flags);
 401 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 402                                            struct timespec *timestamp);
 403 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 404
 405 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 406
 407 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 408                                    struct timespec *timestamp);
 409 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 410                                     const struct timespec *timestamp);
 411
 412 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 413                                          uint16_t queue_id);
 414 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 415                                           uint16_t queue_id);
 416
 417
 418 static const struct rte_pci_id pci_id_i40e_map[] = {
 419 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 420 #include "rte_pci_dev_ids.h"
 421 { .vendor_id = 0, /* sentinel */ },
 422 };
 423
 424 static const struct eth_dev_ops i40e_eth_dev_ops = {
 425         .dev_configure                = i40e_dev_configure,
 426         .dev_start                    = i40e_dev_start,
 427         .dev_stop                     = i40e_dev_stop,
 428         .dev_close                    = i40e_dev_close,
 429         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 430         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 431         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 432         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 433         .dev_set_link_up              = i40e_dev_set_link_up,
 434         .dev_set_link_down            = i40e_dev_set_link_down,
 435         .link_update                  = i40e_dev_link_update,
 436         .stats_get                    = i40e_dev_stats_get,
 437         .xstats_get                   = i40e_dev_xstats_get,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .dev_infos_get                = i40e_dev_info_get,
 442         .vlan_filter_set              = i40e_vlan_filter_set,
 443         .vlan_tpid_set                = i40e_vlan_tpid_set,
 444         .vlan_offload_set             = i40e_vlan_offload_set,
 445         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 446         .vlan_pvid_set                = i40e_vlan_pvid_set,
 447         .rx_queue_start               = i40e_dev_rx_queue_start,
 448         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 449         .tx_queue_start               = i40e_dev_tx_queue_start,
 450         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 451         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 452         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 453         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 454         .rx_queue_release             = i40e_dev_rx_queue_release,
 455         .rx_queue_count               = i40e_dev_rx_queue_count,
 456         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 457         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 458         .tx_queue_release             = i40e_dev_tx_queue_release,
 459         .dev_led_on                   = i40e_dev_led_on,
 460         .dev_led_off                  = i40e_dev_led_off,
 461         .flow_ctrl_get                = i40e_flow_ctrl_get,
 462         .flow_ctrl_set                = i40e_flow_ctrl_set,
 463         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 464         .mac_addr_add                 = i40e_macaddr_add,
 465         .mac_addr_remove              = i40e_macaddr_remove,
 466         .reta_update                  = i40e_dev_rss_reta_update,
 467         .reta_query                   = i40e_dev_rss_reta_query,
 468         .rss_hash_update              = i40e_dev_rss_hash_update,
 469         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 470         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 471         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 472         .filter_ctrl                  = i40e_dev_filter_ctrl,
 473         .rxq_info_get                 = i40e_rxq_info_get,
 474         .txq_info_get                 = i40e_txq_info_get,
 475         .mirror_rule_set              = i40e_mirror_rule_set,
 476         .mirror_rule_reset            = i40e_mirror_rule_reset,
 477         .timesync_enable              = i40e_timesync_enable,
 478         .timesync_disable             = i40e_timesync_disable,
 479         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 480         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 481         .get_dcb_info                 = i40e_dev_get_dcb_info,
 482         .timesync_adjust_time         = i40e_timesync_adjust_time,
 483         .timesync_read_time           = i40e_timesync_read_time,
 484         .timesync_write_time          = i40e_timesync_write_time,
 485 };
 486
 487 /* store statistics names and its offset in stats structure */
 488 struct rte_i40e_xstats_name_off {
 489         char name[RTE_ETH_XSTATS_NAME_SIZE];
 490         unsigned offset;
 491 };
 492
 493 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 494         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 495         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 496         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 497         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 498         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 499                 rx_unknown_protocol)},
 500         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 501         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 502         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 503         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 504 };
 505
 506 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 507                 sizeof(rte_i40e_stats_strings[0]))
 508
 509 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 510         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 511                 tx_dropped_link_down)},
 512         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 513         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 514                 illegal_bytes)},
 515         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 516         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 517                 mac_local_faults)},
 518         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 519                 mac_remote_faults)},
 520         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 521                 rx_length_errors)},
 522         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 523         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 524         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 525         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 526         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 527         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 528                 rx_size_127)},
 529         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 530                 rx_size_255)},
 531         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 532                 rx_size_511)},
 533         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 534                 rx_size_1023)},
 535         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 536                 rx_size_1522)},
 537         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_big)},
 539         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 540                 rx_undersize)},
 541         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 542                 rx_oversize)},
 543         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 544                 mac_short_packet_dropped)},
 545         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 546                 rx_fragments)},
 547         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 548         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 549         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 550                 tx_size_127)},
 551         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 552                 tx_size_255)},
 553         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 554                 tx_size_511)},
 555         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 556                 tx_size_1023)},
 557         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 558                 tx_size_1522)},
 559         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_big)},
 561         {"rx_flow_director_atr_match_packets",
 562                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 563         {"rx_flow_director_sb_match_packets",
 564                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 565         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 566                 tx_lpi_status)},
 567         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 568                 rx_lpi_status)},
 569         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 570                 tx_lpi_count)},
 571         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 572                 rx_lpi_count)},
 573 };
 574
 575 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 576                 sizeof(rte_i40e_hw_port_strings[0]))
 577
 578 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 579         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 580                 priority_xon_rx)},
 581         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 582                 priority_xoff_rx)},
 583 };
 584
 585 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 586                 sizeof(rte_i40e_rxq_prio_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_tx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_tx)},
 593         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 594                 priority_xon_2_xoff)},
 595 };
 596
 597 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 598                 sizeof(rte_i40e_txq_prio_strings[0]))
 599
 600 static struct eth_driver rte_i40e_pmd = {
 601         .pci_drv = {
 602                 .name = "rte_i40e_pmd",
 603                 .id_table = pci_id_i40e_map,
 604                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 605                         RTE_PCI_DRV_DETACHABLE,
 606         },
 607         .eth_dev_init = eth_i40e_dev_init,
 608         .eth_dev_uninit = eth_i40e_dev_uninit,
 609         .dev_private_size = sizeof(struct i40e_adapter),
 610 };
 611
 612 static inline int
 613 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 614                                      struct rte_eth_link *link)
 615 {
 616         struct rte_eth_link *dst = link;
 617         struct rte_eth_link *src = &(dev->data->dev_link);
 618
 619         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 620                                         *(uint64_t *)src) == 0)
 621                 return -1;
 622
 623         return 0;
 624 }
 625
 626 static inline int
 627 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 628                                       struct rte_eth_link *link)
 629 {
 630         struct rte_eth_link *dst = &(dev->data->dev_link);
 631         struct rte_eth_link *src = link;
 632
 633         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 634                                         *(uint64_t *)src) == 0)
 635                 return -1;
 636
 637         return 0;
 638 }
 639
 640 /*
 641  * Driver initialization routine.
 642  * Invoked once at EAL init time.
 643  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 644  */
 645 static int
 646 rte_i40e_pmd_init(const char *name __rte_unused,
 647                   const char *params __rte_unused)
 648 {
 649         PMD_INIT_FUNC_TRACE();
 650         rte_eth_driver_register(&rte_i40e_pmd);
 651
 652         return 0;
 653 }
 654
 655 static struct rte_driver rte_i40e_driver = {
 656         .type = PMD_PDEV,
 657         .init = rte_i40e_pmd_init,
 658 };
 659
 660 PMD_REGISTER_DRIVER(rte_i40e_driver);
 661
 662 /*
 663  * Initialize registers for flexible payload, which should be set by NVM.
 664  * This should be removed from code once it is fixed in NVM.
 665  */
 666 #ifndef I40E_GLQF_ORT
 667 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 668 #endif
 669 #ifndef I40E_GLQF_PIT
 670 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 671 #endif
 672
 673 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 674 {
 675         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 676         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 677         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 678         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 679         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 680         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 681         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 682         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 683         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 684         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 685
 686         /* GLQF_PIT Registers */
 687         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 688         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 689 }
 690
 691 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 692
 693 /*
 694  * Add a ethertype filter to drop all flow control frames transmitted
 695  * from VSIs.
 696 */
 697 static void
 698 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 699 {
 700         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 701         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 702                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 703                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 704         int ret;
 705
 706         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 707                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 708                                 pf->main_vsi_seid, 0,
 709                                 TRUE, NULL, NULL);
 710         if (ret)
 711                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 712                                   " frames from VSIs.");
 713 }
 714
 715 static int
 716 eth_i40e_dev_init(struct rte_eth_dev *dev)
 717 {
 718         struct rte_pci_device *pci_dev;
 719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 721         struct i40e_vsi *vsi;
 722         int ret;
 723         uint32_t len;
 724         uint8_t aq_fail = 0;
 725
 726         PMD_INIT_FUNC_TRACE();
 727
 728         dev->dev_ops = &i40e_eth_dev_ops;
 729         dev->rx_pkt_burst = i40e_recv_pkts;
 730         dev->tx_pkt_burst = i40e_xmit_pkts;
 731
 732         /* for secondary processes, we don't initialise any further as primary
 733          * has already done this work. Only check we don't need a different
 734          * RX function */
 735         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 736                 i40e_set_rx_function(dev);
 737                 i40e_set_tx_function(dev);
 738                 return 0;
 739         }
 740         pci_dev = dev->pci_dev;
 741
 742         rte_eth_copy_pci_info(dev, pci_dev);
 743
 744         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 745         pf->adapter->eth_dev = dev;
 746         pf->dev_data = dev->data;
 747
 748         hw->back = I40E_PF_TO_ADAPTER(pf);
 749         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 750         if (!hw->hw_addr) {
 751                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 752                              "as address is NULL");
 753                 return -ENODEV;
 754         }
 755
 756         hw->vendor_id = pci_dev->id.vendor_id;
 757         hw->device_id = pci_dev->id.device_id;
 758         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 759         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 760         hw->bus.device = pci_dev->addr.devid;
 761         hw->bus.func = pci_dev->addr.function;
 762         hw->adapter_stopped = 0;
 763
 764         /* Make sure all is clean before doing PF reset */
 765         i40e_clear_hw(hw);
 766
 767         /* Initialize the hardware */
 768         i40e_hw_init(hw);
 769
 770         /* Reset here to make sure all is clean for each PF */
 771         ret = i40e_pf_reset(hw);
 772         if (ret) {
 773                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 774                 return ret;
 775         }
 776
 777         /* Initialize the shared code (base driver) */
 778         ret = i40e_init_shared_code(hw);
 779         if (ret) {
 780                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 781                 return ret;
 782         }
 783
 784         /*
 785          * To work around the NVM issue,initialize registers
 786          * for flexible payload by software.
 787          * It should be removed once issues are fixed in NVM.
 788          */
 789         i40e_flex_payload_reg_init(hw);
 790
 791         /* Initialize the parameters for adminq */
 792         i40e_init_adminq_parameter(hw);
 793         ret = i40e_init_adminq(hw);
 794         if (ret != I40E_SUCCESS) {
 795                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 796                 return -EIO;
 797         }
 798         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 799                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 800                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 801                      ((hw->nvm.version >> 12) & 0xf),
 802                      ((hw->nvm.version >> 4) & 0xff),
 803                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 804
 805         /* Clear PXE mode */
 806         i40e_clear_pxe_mode(hw);
 807
 808         /*
 809          * On X710, performance number is far from the expectation on recent
 810          * firmware versions. The fix for this issue may not be integrated in
 811          * the following firmware version. So the workaround in software driver
 812          * is needed. It needs to modify the initial values of 3 internal only
 813          * registers. Note that the workaround can be removed when it is fixed
 814          * in firmware in the future.
 815          */
 816         i40e_configure_registers(hw);
 817
 818         /* Get hw capabilities */
 819         ret = i40e_get_cap(hw);
 820         if (ret != I40E_SUCCESS) {
 821                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 822                 goto err_get_capabilities;
 823         }
 824
 825         /* Initialize parameters for PF */
 826         ret = i40e_pf_parameter_init(dev);
 827         if (ret != 0) {
 828                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 829                 goto err_parameter_init;
 830         }
 831
 832         /* Initialize the queue management */
 833         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 834         if (ret < 0) {
 835                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 836                 goto err_qp_pool_init;
 837         }
 838         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 839                                 hw->func_caps.num_msix_vectors - 1);
 840         if (ret < 0) {
 841                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 842                 goto err_msix_pool_init;
 843         }
 844
 845         /* Initialize lan hmc */
 846         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 847                                 hw->func_caps.num_rx_qp, 0, 0);
 848         if (ret != I40E_SUCCESS) {
 849                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 850                 goto err_init_lan_hmc;
 851         }
 852
 853         /* Configure lan hmc */
 854         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 855         if (ret != I40E_SUCCESS) {
 856                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 857                 goto err_configure_lan_hmc;
 858         }
 859
 860         /* Get and check the mac address */
 861         i40e_get_mac_addr(hw, hw->mac.addr);
 862         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 863                 PMD_INIT_LOG(ERR, "mac address is not valid");
 864                 ret = -EIO;
 865                 goto err_get_mac_addr;
 866         }
 867         /* Copy the permanent MAC address */
 868         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 869                         (struct ether_addr *) hw->mac.perm_addr);
 870
 871         /* Disable flow control */
 872         hw->fc.requested_mode = I40E_FC_NONE;
 873         i40e_set_fc(hw, &aq_fail, TRUE);
 874
 875         /* PF setup, which includes VSI setup */
 876         ret = i40e_pf_setup(pf);
 877         if (ret) {
 878                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 879                 goto err_setup_pf_switch;
 880         }
 881
 882         vsi = pf->main_vsi;
 883
 884         /* Disable double vlan by default */
 885         i40e_vsi_config_double_vlan(vsi, FALSE);
 886
 887         if (!vsi->max_macaddrs)
 888                 len = ETHER_ADDR_LEN;
 889         else
 890                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 891
 892         /* Should be after VSI initialized */
 893         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 894         if (!dev->data->mac_addrs) {
 895                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 896                                         "for storing mac address");
 897                 goto err_mac_alloc;
 898         }
 899         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 900                                         &dev->data->mac_addrs[0]);
 901
 902         /* initialize pf host driver to setup SRIOV resource if applicable */
 903         i40e_pf_host_init(dev);
 904
 905         /* register callback func to eal lib */
 906         rte_intr_callback_register(&(pci_dev->intr_handle),
 907                 i40e_dev_interrupt_handler, (void *)dev);
 908
 909         /* configure and enable device interrupt */
 910         i40e_pf_config_irq0(hw, TRUE);
 911         i40e_pf_enable_irq0(hw);
 912
 913         /* enable uio intr after callback register */
 914         rte_intr_enable(&(pci_dev->intr_handle));
 915         /*
 916          * Add an ethertype filter to drop all flow control frames transmitted
 917          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 918          * frames to wire.
 919          */
 920         i40e_add_tx_flow_control_drop_filter(pf);
 921
 922         /* initialize mirror rule list */
 923         TAILQ_INIT(&pf->mirror_list);
 924
 925         /* Init dcb to sw mode by default */
 926         ret = i40e_dcb_init_configure(dev, TRUE);
 927         if (ret != I40E_SUCCESS) {
 928                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 929                 pf->flags &= ~I40E_FLAG_DCB;
 930         }
 931
 932         return 0;
 933
 934 err_mac_alloc:
 935         i40e_vsi_release(pf->main_vsi);
 936 err_setup_pf_switch:
 937 err_get_mac_addr:
 938 err_configure_lan_hmc:
 939         (void)i40e_shutdown_lan_hmc(hw);
 940 err_init_lan_hmc:
 941         i40e_res_pool_destroy(&pf->msix_pool);
 942 err_msix_pool_init:
 943         i40e_res_pool_destroy(&pf->qp_pool);
 944 err_qp_pool_init:
 945 err_parameter_init:
 946 err_get_capabilities:
 947         (void)i40e_shutdown_adminq(hw);
 948
 949         return ret;
 950 }
 951
 952 static int
 953 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 954 {
 955         struct rte_pci_device *pci_dev;
 956         struct i40e_hw *hw;
 957         struct i40e_filter_control_settings settings;
 958         int ret;
 959         uint8_t aq_fail = 0;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 964                 return 0;
 965
 966         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 967         pci_dev = dev->pci_dev;
 968
 969         if (hw->adapter_stopped == 0)
 970                 i40e_dev_close(dev);
 971
 972         dev->dev_ops = NULL;
 973         dev->rx_pkt_burst = NULL;
 974         dev->tx_pkt_burst = NULL;
 975
 976         /* Disable LLDP */
 977         ret = i40e_aq_stop_lldp(hw, true, NULL);
 978         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 979                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 980
 981         /* Clear PXE mode */
 982         i40e_clear_pxe_mode(hw);
 983
 984         /* Unconfigure filter control */
 985         memset(&settings, 0, sizeof(settings));
 986         ret = i40e_set_filter_control(hw, &settings);
 987         if (ret)
 988                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 989                                         ret);
 990
 991         /* Disable flow control */
 992         hw->fc.requested_mode = I40E_FC_NONE;
 993         i40e_set_fc(hw, &aq_fail, TRUE);
 994
 995         /* uninitialize pf host driver */
 996         i40e_pf_host_uninit(dev);
 997
 998         rte_free(dev->data->mac_addrs);
 999         dev->data->mac_addrs = NULL;
1000
1001         /* disable uio intr before callback unregister */
1002         rte_intr_disable(&(pci_dev->intr_handle));
1003
1004         /* register callback func to eal lib */
1005         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1006                 i40e_dev_interrupt_handler, (void *)dev);
1007
1008         return 0;
1009 }
1010
1011 static int
1012 i40e_dev_configure(struct rte_eth_dev *dev)
1013 {
1014         struct i40e_adapter *ad =
1015                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1016         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1018         int i, ret;
1019
1020         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1021          * bulk allocation or vector Rx preconditions we will reset it.
1022          */
1023         ad->rx_bulk_alloc_allowed = true;
1024         ad->rx_vec_allowed = true;
1025         ad->tx_simple_allowed = true;
1026         ad->tx_vec_allowed = true;
1027
1028         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1029                 ret = i40e_fdir_setup(pf);
1030                 if (ret != I40E_SUCCESS) {
1031                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1032                         return -ENOTSUP;
1033                 }
1034                 ret = i40e_fdir_configure(dev);
1035                 if (ret < 0) {
1036                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1037                         goto err;
1038                 }
1039         } else
1040                 i40e_fdir_teardown(pf);
1041
1042         ret = i40e_dev_init_vlan(dev);
1043         if (ret < 0)
1044                 goto err;
1045
1046         /* VMDQ setup.
1047          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1048          *  RSS setting have different requirements.
1049          *  General PMD driver call sequence are NIC init, configure,
1050          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1051          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1052          *  applicable. So, VMDQ setting has to be done before
1053          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1054          *  For RSS setting, it will try to calculate actual configured RX queue
1055          *  number, which will be available after rx_queue_setup(). dev_start()
1056          *  function is good to place RSS setup.
1057          */
1058         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1059                 ret = i40e_vmdq_setup(dev);
1060                 if (ret)
1061                         goto err;
1062         }
1063
1064         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1065                 ret = i40e_dcb_setup(dev);
1066                 if (ret) {
1067                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1068                         goto err_dcb;
1069                 }
1070         }
1071
1072         return 0;
1073
1074 err_dcb:
1075         /* need to release vmdq resource if exists */
1076         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1077                 i40e_vsi_release(pf->vmdq[i].vsi);
1078                 pf->vmdq[i].vsi = NULL;
1079         }
1080         rte_free(pf->vmdq);
1081         pf->vmdq = NULL;
1082 err:
1083         /* need to release fdir resource if exists */
1084         i40e_fdir_teardown(pf);
1085         return ret;
1086 }
1087
1088 void
1089 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1090 {
1091         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1092         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1093         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1094         uint16_t msix_vect = vsi->msix_intr;
1095         uint16_t i;
1096
1097         for (i = 0; i < vsi->nb_qps; i++) {
1098                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1099                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1100                 rte_wmb();
1101         }
1102
1103         if (vsi->type != I40E_VSI_SRIOV) {
1104                 if (!rte_intr_allow_others(intr_handle)) {
1105                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1106                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1107                         I40E_WRITE_REG(hw,
1108                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1109                                        0);
1110                 } else {
1111                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1112                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1113                         I40E_WRITE_REG(hw,
1114                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1115                                                        msix_vect - 1), 0);
1116                 }
1117         } else {
1118                 uint32_t reg;
1119                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1120                         vsi->user_param + (msix_vect - 1);
1121
1122                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1123                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1124         }
1125         I40E_WRITE_FLUSH(hw);
1126 }
1127
1128 static void
1129 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1130                        int base_queue, int nb_queue)
1131 {
1132         int i;
1133         uint32_t val;
1134         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1135
1136         /* Bind all RX queues to allocated MSIX interrupt */
1137         for (i = 0; i < nb_queue; i++) {
1138                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1139                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1140                         ((base_queue + i + 1) <<
1141                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1142                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1143                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1144
1145                 if (i == nb_queue - 1)
1146                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1147                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1148         }
1149
1150         /* Write first RX queue to Link list register as the head element */
1151         if (vsi->type != I40E_VSI_SRIOV) {
1152                 uint16_t interval =
1153                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1154
1155                 if (msix_vect == I40E_MISC_VEC_ID) {
1156                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1157                                        (base_queue <<
1158                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1159                                        (0x0 <<
1160                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1161                         I40E_WRITE_REG(hw,
1162                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1163                                        interval);
1164                 } else {
1165                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1166                                        (base_queue <<
1167                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1168                                        (0x0 <<
1169                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1170                         I40E_WRITE_REG(hw,
1171                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1172                                                        msix_vect - 1),
1173                                        interval);
1174                 }
1175         } else {
1176                 uint32_t reg;
1177
1178                 if (msix_vect == I40E_MISC_VEC_ID) {
1179                         I40E_WRITE_REG(hw,
1180                                        I40E_VPINT_LNKLST0(vsi->user_param),
1181                                        (base_queue <<
1182                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1183                                        (0x0 <<
1184                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1185                 } else {
1186                         /* num_msix_vectors_vf needs to minus irq0 */
1187                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1188                                 vsi->user_param + (msix_vect - 1);
1189
1190                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1191                                        (base_queue <<
1192                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1193                                        (0x0 <<
1194                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1195                 }
1196         }
1197
1198         I40E_WRITE_FLUSH(hw);
1199 }
1200
1201 void
1202 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1203 {
1204         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1205         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1206         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1207         uint16_t msix_vect = vsi->msix_intr;
1208         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1209         uint16_t queue_idx = 0;
1210         int record = 0;
1211         uint32_t val;
1212         int i;
1213
1214         for (i = 0; i < vsi->nb_qps; i++) {
1215                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1216                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1217         }
1218
1219         /* INTENA flag is not auto-cleared for interrupt */
1220         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1221         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1222                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1223                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1224         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1225
1226         /* VF bind interrupt */
1227         if (vsi->type == I40E_VSI_SRIOV) {
1228                 __vsi_queues_bind_intr(vsi, msix_vect,
1229                                        vsi->base_queue, vsi->nb_qps);
1230                 return;
1231         }
1232
1233         /* PF & VMDq bind interrupt */
1234         if (rte_intr_dp_is_en(intr_handle)) {
1235                 if (vsi->type == I40E_VSI_MAIN) {
1236                         queue_idx = 0;
1237                         record = 1;
1238                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1239                         struct i40e_vsi *main_vsi =
1240                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1241                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1242                         record = 1;
1243                 }
1244         }
1245
1246         for (i = 0; i < vsi->nb_used_qps; i++) {
1247                 if (nb_msix <= 1) {
1248                         if (!rte_intr_allow_others(intr_handle))
1249                                 /* allow to share MISC_VEC_ID */
1250                                 msix_vect = I40E_MISC_VEC_ID;
1251
1252                         /* no enough msix_vect, map all to one */
1253                         __vsi_queues_bind_intr(vsi, msix_vect,
1254                                                vsi->base_queue + i,
1255                                                vsi->nb_used_qps - i);
1256                         for (; !!record && i < vsi->nb_used_qps; i++)
1257                                 intr_handle->intr_vec[queue_idx + i] =
1258                                         msix_vect;
1259                         break;
1260                 }
1261                 /* 1:1 queue/msix_vect mapping */
1262                 __vsi_queues_bind_intr(vsi, msix_vect,
1263                                        vsi->base_queue + i, 1);
1264                 if (!!record)
1265                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1266
1267                 msix_vect++;
1268                 nb_msix--;
1269         }
1270 }
1271
1272 static void
1273 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1274 {
1275         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1276         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1277         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1278         uint16_t interval = i40e_calc_itr_interval(\
1279                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1280         uint16_t msix_intr, i;
1281
1282         if (rte_intr_allow_others(intr_handle))
1283                 for (i = 0; i < vsi->nb_msix; i++) {
1284                         msix_intr = vsi->msix_intr + i;
1285                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1286                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1287                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1288                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1289                                 (interval <<
1290                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1291                 }
1292         else
1293                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1294                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1295                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1296                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1297                                (interval <<
1298                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1299
1300         I40E_WRITE_FLUSH(hw);
1301 }
1302
1303 static void
1304 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1305 {
1306         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1307         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1308         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1309         uint16_t msix_intr, i;
1310
1311         if (rte_intr_allow_others(intr_handle))
1312                 for (i = 0; i < vsi->nb_msix; i++) {
1313                         msix_intr = vsi->msix_intr + i;
1314                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1315                                        0);
1316                 }
1317         else
1318                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1319
1320         I40E_WRITE_FLUSH(hw);
1321 }
1322
1323 static inline uint8_t
1324 i40e_parse_link_speed(uint16_t eth_link_speed)
1325 {
1326         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1327
1328         switch (eth_link_speed) {
1329         case ETH_LINK_SPEED_40G:
1330                 link_speed = I40E_LINK_SPEED_40GB;
1331                 break;
1332         case ETH_LINK_SPEED_20G:
1333                 link_speed = I40E_LINK_SPEED_20GB;
1334                 break;
1335         case ETH_LINK_SPEED_10G:
1336                 link_speed = I40E_LINK_SPEED_10GB;
1337                 break;
1338         case ETH_LINK_SPEED_1000:
1339                 link_speed = I40E_LINK_SPEED_1GB;
1340                 break;
1341         case ETH_LINK_SPEED_100:
1342                 link_speed = I40E_LINK_SPEED_100MB;
1343                 break;
1344         }
1345
1346         return link_speed;
1347 }
1348
1349 static int
1350 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1351 {
1352         enum i40e_status_code status;
1353         struct i40e_aq_get_phy_abilities_resp phy_ab;
1354         struct i40e_aq_set_phy_config phy_conf;
1355         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1356                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1357                         I40E_AQ_PHY_FLAG_LOW_POWER;
1358         const uint8_t advt = I40E_LINK_SPEED_40GB |
1359                         I40E_LINK_SPEED_10GB |
1360                         I40E_LINK_SPEED_1GB |
1361                         I40E_LINK_SPEED_100MB;
1362         int ret = -ENOTSUP;
1363
1364         /* Skip it on 40G interfaces, as a workaround for the link issue */
1365         if (i40e_is_40G_device(hw->device_id))
1366                 return I40E_SUCCESS;
1367
1368         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1369                                               NULL);
1370         if (status)
1371                 return ret;
1372
1373         memset(&phy_conf, 0, sizeof(phy_conf));
1374
1375         /* bits 0-2 use the values from get_phy_abilities_resp */
1376         abilities &= ~mask;
1377         abilities |= phy_ab.abilities & mask;
1378
1379         /* update ablities and speed */
1380         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1381                 phy_conf.link_speed = advt;
1382         else
1383                 phy_conf.link_speed = force_speed;
1384
1385         phy_conf.abilities = abilities;
1386
1387         /* use get_phy_abilities_resp value for the rest */
1388         phy_conf.phy_type = phy_ab.phy_type;
1389         phy_conf.eee_capability = phy_ab.eee_capability;
1390         phy_conf.eeer = phy_ab.eeer_val;
1391         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1392
1393         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1394                     phy_ab.abilities, phy_ab.link_speed);
1395         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1396                     phy_conf.abilities, phy_conf.link_speed);
1397
1398         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1399         if (status)
1400                 return ret;
1401
1402         return I40E_SUCCESS;
1403 }
1404
1405 static int
1406 i40e_apply_link_speed(struct rte_eth_dev *dev)
1407 {
1408         uint8_t speed;
1409         uint8_t abilities = 0;
1410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1411         struct rte_eth_conf *conf = &dev->data->dev_conf;
1412
1413         speed = i40e_parse_link_speed(conf->link_speed);
1414         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1415         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1416                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1417         else
1418                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1419
1420         return i40e_phy_conf_link(hw, abilities, speed);
1421 }
1422
1423 static int
1424 i40e_dev_start(struct rte_eth_dev *dev)
1425 {
1426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         struct i40e_vsi *main_vsi = pf->main_vsi;
1429         int ret, i;
1430         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1431         uint32_t intr_vector = 0;
1432
1433         hw->adapter_stopped = 0;
1434
1435         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1436                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1437                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1438                              dev->data->dev_conf.link_duplex,
1439                              dev->data->port_id);
1440                 return -EINVAL;
1441         }
1442
1443         rte_intr_disable(intr_handle);
1444
1445         if ((rte_intr_cap_multiple(intr_handle) ||
1446              !RTE_ETH_DEV_SRIOV(dev).active) &&
1447             dev->data->dev_conf.intr_conf.rxq != 0) {
1448                 intr_vector = dev->data->nb_rx_queues;
1449                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1450                         return -1;
1451         }
1452
1453         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1454                 intr_handle->intr_vec =
1455                         rte_zmalloc("intr_vec",
1456                                     dev->data->nb_rx_queues * sizeof(int),
1457                                     0);
1458                 if (!intr_handle->intr_vec) {
1459                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1460                                      " intr_vec\n", dev->data->nb_rx_queues);
1461                         return -ENOMEM;
1462                 }
1463         }
1464
1465         /* Initialize VSI */
1466         ret = i40e_dev_rxtx_init(pf);
1467         if (ret != I40E_SUCCESS) {
1468                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1469                 goto err_up;
1470         }
1471
1472         /* Map queues with MSIX interrupt */
1473         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1474                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1475         i40e_vsi_queues_bind_intr(main_vsi);
1476         i40e_vsi_enable_queues_intr(main_vsi);
1477
1478         /* Map VMDQ VSI queues with MSIX interrupt */
1479         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1480                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1481                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1482                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1483         }
1484
1485         /* enable FDIR MSIX interrupt */
1486         if (pf->fdir.fdir_vsi) {
1487                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1488                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1489         }
1490
1491         /* Enable all queues which have been configured */
1492         ret = i40e_dev_switch_queues(pf, TRUE);
1493         if (ret != I40E_SUCCESS) {
1494                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1495                 goto err_up;
1496         }
1497
1498         /* Enable receiving broadcast packets */
1499         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1500         if (ret != I40E_SUCCESS)
1501                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1502
1503         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1504                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1505                                                 true, NULL);
1506                 if (ret != I40E_SUCCESS)
1507                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1508         }
1509
1510         /* Apply link configure */
1511         ret = i40e_apply_link_speed(dev);
1512         if (I40E_SUCCESS != ret) {
1513                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1514                 goto err_up;
1515         }
1516
1517         if (!rte_intr_allow_others(intr_handle)) {
1518                 rte_intr_callback_unregister(intr_handle,
1519                                              i40e_dev_interrupt_handler,
1520                                              (void *)dev);
1521                 /* configure and enable device interrupt */
1522                 i40e_pf_config_irq0(hw, FALSE);
1523                 i40e_pf_enable_irq0(hw);
1524
1525                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1526                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1527                                      " no intr multiplex\n");
1528         }
1529
1530         /* enable uio intr after callback register */
1531         rte_intr_enable(intr_handle);
1532
1533         return I40E_SUCCESS;
1534
1535 err_up:
1536         i40e_dev_switch_queues(pf, FALSE);
1537         i40e_dev_clear_queues(dev);
1538
1539         return ret;
1540 }
1541
1542 static void
1543 i40e_dev_stop(struct rte_eth_dev *dev)
1544 {
1545         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1546         struct i40e_vsi *main_vsi = pf->main_vsi;
1547         struct i40e_mirror_rule *p_mirror;
1548         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1549         int i;
1550
1551         /* Disable all queues */
1552         i40e_dev_switch_queues(pf, FALSE);
1553
1554         /* un-map queues with interrupt registers */
1555         i40e_vsi_disable_queues_intr(main_vsi);
1556         i40e_vsi_queues_unbind_intr(main_vsi);
1557
1558         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1559                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1560                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1561         }
1562
1563         if (pf->fdir.fdir_vsi) {
1564                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1565                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1566         }
1567         /* Clear all queues and release memory */
1568         i40e_dev_clear_queues(dev);
1569
1570         /* Set link down */
1571         i40e_dev_set_link_down(dev);
1572
1573         /* Remove all mirror rules */
1574         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1575                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1576                 rte_free(p_mirror);
1577         }
1578         pf->nb_mirror_rule = 0;
1579
1580         if (!rte_intr_allow_others(intr_handle))
1581                 /* resume to the default handler */
1582                 rte_intr_callback_register(intr_handle,
1583                                            i40e_dev_interrupt_handler,
1584                                            (void *)dev);
1585
1586         /* Clean datapath event and queue/vec mapping */
1587         rte_intr_efd_disable(intr_handle);
1588         if (intr_handle->intr_vec) {
1589                 rte_free(intr_handle->intr_vec);
1590                 intr_handle->intr_vec = NULL;
1591         }
1592 }
1593
1594 static void
1595 i40e_dev_close(struct rte_eth_dev *dev)
1596 {
1597         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1598         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599         uint32_t reg;
1600         int i;
1601
1602         PMD_INIT_FUNC_TRACE();
1603
1604         i40e_dev_stop(dev);
1605         hw->adapter_stopped = 1;
1606         i40e_dev_free_queues(dev);
1607
1608         /* Disable interrupt */
1609         i40e_pf_disable_irq0(hw);
1610         rte_intr_disable(&(dev->pci_dev->intr_handle));
1611
1612         /* shutdown and destroy the HMC */
1613         i40e_shutdown_lan_hmc(hw);
1614
1615         /* release all the existing VSIs and VEBs */
1616         i40e_fdir_teardown(pf);
1617         i40e_vsi_release(pf->main_vsi);
1618
1619         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1620                 i40e_vsi_release(pf->vmdq[i].vsi);
1621                 pf->vmdq[i].vsi = NULL;
1622         }
1623
1624         rte_free(pf->vmdq);
1625         pf->vmdq = NULL;
1626
1627         /* shutdown the adminq */
1628         i40e_aq_queue_shutdown(hw, true);
1629         i40e_shutdown_adminq(hw);
1630
1631         i40e_res_pool_destroy(&pf->qp_pool);
1632         i40e_res_pool_destroy(&pf->msix_pool);
1633
1634         /* force a PF reset to clean anything leftover */
1635         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1636         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1637                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1638         I40E_WRITE_FLUSH(hw);
1639 }
1640
1641 static void
1642 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1643 {
1644         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1645         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646         struct i40e_vsi *vsi = pf->main_vsi;
1647         int status;
1648
1649         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1650                                                         true, NULL);
1651         if (status != I40E_SUCCESS)
1652                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1653
1654         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1655                                                         TRUE, NULL);
1656         if (status != I40E_SUCCESS)
1657                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1658
1659 }
1660
1661 static void
1662 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1663 {
1664         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1665         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666         struct i40e_vsi *vsi = pf->main_vsi;
1667         int status;
1668
1669         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1670                                                         false, NULL);
1671         if (status != I40E_SUCCESS)
1672                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1673
1674         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1675                                                         false, NULL);
1676         if (status != I40E_SUCCESS)
1677                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1678 }
1679
1680 static void
1681 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1682 {
1683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         struct i40e_vsi *vsi = pf->main_vsi;
1686         int ret;
1687
1688         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1689         if (ret != I40E_SUCCESS)
1690                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1691 }
1692
1693 static void
1694 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1695 {
1696         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698         struct i40e_vsi *vsi = pf->main_vsi;
1699         int ret;
1700
1701         if (dev->data->promiscuous == 1)
1702                 return; /* must remain in all_multicast mode */
1703
1704         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1705                                 vsi->seid, FALSE, NULL);
1706         if (ret != I40E_SUCCESS)
1707                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1708 }
1709
1710 /*
1711  * Set device link up.
1712  */
1713 static int
1714 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1715 {
1716         /* re-apply link speed setting */
1717         return i40e_apply_link_speed(dev);
1718 }
1719
1720 /*
1721  * Set device link down.
1722  */
1723 static int
1724 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1725 {
1726         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1727         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1728         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1729
1730         return i40e_phy_conf_link(hw, abilities, speed);
1731 }
1732
1733 int
1734 i40e_dev_link_update(struct rte_eth_dev *dev,
1735                      int wait_to_complete)
1736 {
1737 #define CHECK_INTERVAL 100  /* 100ms */
1738 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1739         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740         struct i40e_link_status link_status;
1741         struct rte_eth_link link, old;
1742         int status;
1743         unsigned rep_cnt = MAX_REPEAT_TIME;
1744
1745         memset(&link, 0, sizeof(link));
1746         memset(&old, 0, sizeof(old));
1747         memset(&link_status, 0, sizeof(link_status));
1748         rte_i40e_dev_atomic_read_link_status(dev, &old);
1749
1750         do {
1751                 /* Get link status information from hardware */
1752                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1753                 if (status != I40E_SUCCESS) {
1754                         link.link_speed = ETH_LINK_SPEED_100;
1755                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1756                         PMD_DRV_LOG(ERR, "Failed to get link info");
1757                         goto out;
1758                 }
1759
1760                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1761                 if (!wait_to_complete)
1762                         break;
1763
1764                 rte_delay_ms(CHECK_INTERVAL);
1765         } while (!link.link_status && rep_cnt--);
1766
1767         if (!link.link_status)
1768                 goto out;
1769
1770         /* i40e uses full duplex only */
1771         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1772
1773         /* Parse the link status */
1774         switch (link_status.link_speed) {
1775         case I40E_LINK_SPEED_100MB:
1776                 link.link_speed = ETH_LINK_SPEED_100;
1777                 break;
1778         case I40E_LINK_SPEED_1GB:
1779                 link.link_speed = ETH_LINK_SPEED_1000;
1780                 break;
1781         case I40E_LINK_SPEED_10GB:
1782                 link.link_speed = ETH_LINK_SPEED_10G;
1783                 break;
1784         case I40E_LINK_SPEED_20GB:
1785                 link.link_speed = ETH_LINK_SPEED_20G;
1786                 break;
1787         case I40E_LINK_SPEED_40GB:
1788                 link.link_speed = ETH_LINK_SPEED_40G;
1789                 break;
1790         default:
1791                 link.link_speed = ETH_LINK_SPEED_100;
1792                 break;
1793         }
1794
1795 out:
1796         rte_i40e_dev_atomic_write_link_status(dev, &link);
1797         if (link.link_status == old.link_status)
1798                 return -1;
1799
1800         return 0;
1801 }
1802
1803 /* Get all the statistics of a VSI */
1804 void
1805 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1806 {
1807         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1808         struct i40e_eth_stats *nes = &vsi->eth_stats;
1809         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1810         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1811
1812         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1813                             vsi->offset_loaded, &oes->rx_bytes,
1814                             &nes->rx_bytes);
1815         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1816                             vsi->offset_loaded, &oes->rx_unicast,
1817                             &nes->rx_unicast);
1818         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1819                             vsi->offset_loaded, &oes->rx_multicast,
1820                             &nes->rx_multicast);
1821         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1822                             vsi->offset_loaded, &oes->rx_broadcast,
1823                             &nes->rx_broadcast);
1824         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1825                             &oes->rx_discards, &nes->rx_discards);
1826         /* GLV_REPC not supported */
1827         /* GLV_RMPC not supported */
1828         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1829                             &oes->rx_unknown_protocol,
1830                             &nes->rx_unknown_protocol);
1831         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1832                             vsi->offset_loaded, &oes->tx_bytes,
1833                             &nes->tx_bytes);
1834         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1835                             vsi->offset_loaded, &oes->tx_unicast,
1836                             &nes->tx_unicast);
1837         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1838                             vsi->offset_loaded, &oes->tx_multicast,
1839                             &nes->tx_multicast);
1840         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1841                             vsi->offset_loaded,  &oes->tx_broadcast,
1842                             &nes->tx_broadcast);
1843         /* GLV_TDPC not supported */
1844         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1845                             &oes->tx_errors, &nes->tx_errors);
1846         vsi->offset_loaded = true;
1847
1848         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1849                     vsi->vsi_id);
1850         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1851         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1852         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1853         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1854         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1855         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1856                     nes->rx_unknown_protocol);
1857         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1858         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1859         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1860         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1861         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1862         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1863         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1864                     vsi->vsi_id);
1865 }
1866
1867 static void
1868 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1869 {
1870         unsigned int i;
1871         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1872         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1873
1874         /* Get statistics of struct i40e_eth_stats */
1875         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1876                             I40E_GLPRT_GORCL(hw->port),
1877                             pf->offset_loaded, &os->eth.rx_bytes,
1878                             &ns->eth.rx_bytes);
1879         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1880                             I40E_GLPRT_UPRCL(hw->port),
1881                             pf->offset_loaded, &os->eth.rx_unicast,
1882                             &ns->eth.rx_unicast);
1883         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1884                             I40E_GLPRT_MPRCL(hw->port),
1885                             pf->offset_loaded, &os->eth.rx_multicast,
1886                             &ns->eth.rx_multicast);
1887         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1888                             I40E_GLPRT_BPRCL(hw->port),
1889                             pf->offset_loaded, &os->eth.rx_broadcast,
1890                             &ns->eth.rx_broadcast);
1891         /* Workaround: CRC size should not be included in byte statistics,
1892          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1893          */
1894         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1895                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1896
1897         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1898                             pf->offset_loaded, &os->eth.rx_discards,
1899                             &ns->eth.rx_discards);
1900         /* GLPRT_REPC not supported */
1901         /* GLPRT_RMPC not supported */
1902         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1903                             pf->offset_loaded,
1904                             &os->eth.rx_unknown_protocol,
1905                             &ns->eth.rx_unknown_protocol);
1906         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1907                             I40E_GLPRT_GOTCL(hw->port),
1908                             pf->offset_loaded, &os->eth.tx_bytes,
1909                             &ns->eth.tx_bytes);
1910         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1911                             I40E_GLPRT_UPTCL(hw->port),
1912                             pf->offset_loaded, &os->eth.tx_unicast,
1913                             &ns->eth.tx_unicast);
1914         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1915                             I40E_GLPRT_MPTCL(hw->port),
1916                             pf->offset_loaded, &os->eth.tx_multicast,
1917                             &ns->eth.tx_multicast);
1918         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1919                             I40E_GLPRT_BPTCL(hw->port),
1920                             pf->offset_loaded, &os->eth.tx_broadcast,
1921                             &ns->eth.tx_broadcast);
1922         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1923                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1924         /* GLPRT_TEPC not supported */
1925
1926         /* additional port specific stats */
1927         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1928                             pf->offset_loaded, &os->tx_dropped_link_down,
1929                             &ns->tx_dropped_link_down);
1930         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1931                             pf->offset_loaded, &os->crc_errors,
1932                             &ns->crc_errors);
1933         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1934                             pf->offset_loaded, &os->illegal_bytes,
1935                             &ns->illegal_bytes);
1936         /* GLPRT_ERRBC not supported */
1937         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1938                             pf->offset_loaded, &os->mac_local_faults,
1939                             &ns->mac_local_faults);
1940         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1941                             pf->offset_loaded, &os->mac_remote_faults,
1942                             &ns->mac_remote_faults);
1943         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1944                             pf->offset_loaded, &os->rx_length_errors,
1945                             &ns->rx_length_errors);
1946         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1947                             pf->offset_loaded, &os->link_xon_rx,
1948                             &ns->link_xon_rx);
1949         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1950                             pf->offset_loaded, &os->link_xoff_rx,
1951                             &ns->link_xoff_rx);
1952         for (i = 0; i < 8; i++) {
1953                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1954                                     pf->offset_loaded,
1955                                     &os->priority_xon_rx[i],
1956                                     &ns->priority_xon_rx[i]);
1957                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1958                                     pf->offset_loaded,
1959                                     &os->priority_xoff_rx[i],
1960                                     &ns->priority_xoff_rx[i]);
1961         }
1962         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1963                             pf->offset_loaded, &os->link_xon_tx,
1964                             &ns->link_xon_tx);
1965         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1966                             pf->offset_loaded, &os->link_xoff_tx,
1967                             &ns->link_xoff_tx);
1968         for (i = 0; i < 8; i++) {
1969                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1970                                     pf->offset_loaded,
1971                                     &os->priority_xon_tx[i],
1972                                     &ns->priority_xon_tx[i]);
1973                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1974                                     pf->offset_loaded,
1975                                     &os->priority_xoff_tx[i],
1976                                     &ns->priority_xoff_tx[i]);
1977                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1978                                     pf->offset_loaded,
1979                                     &os->priority_xon_2_xoff[i],
1980                                     &ns->priority_xon_2_xoff[i]);
1981         }
1982         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1983                             I40E_GLPRT_PRC64L(hw->port),
1984                             pf->offset_loaded, &os->rx_size_64,
1985                             &ns->rx_size_64);
1986         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1987                             I40E_GLPRT_PRC127L(hw->port),
1988                             pf->offset_loaded, &os->rx_size_127,
1989                             &ns->rx_size_127);
1990         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1991                             I40E_GLPRT_PRC255L(hw->port),
1992                             pf->offset_loaded, &os->rx_size_255,
1993                             &ns->rx_size_255);
1994         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1995                             I40E_GLPRT_PRC511L(hw->port),
1996                             pf->offset_loaded, &os->rx_size_511,
1997                             &ns->rx_size_511);
1998         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1999                             I40E_GLPRT_PRC1023L(hw->port),
2000                             pf->offset_loaded, &os->rx_size_1023,
2001                             &ns->rx_size_1023);
2002         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2003                             I40E_GLPRT_PRC1522L(hw->port),
2004                             pf->offset_loaded, &os->rx_size_1522,
2005                             &ns->rx_size_1522);
2006         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2007                             I40E_GLPRT_PRC9522L(hw->port),
2008                             pf->offset_loaded, &os->rx_size_big,
2009                             &ns->rx_size_big);
2010         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2011                             pf->offset_loaded, &os->rx_undersize,
2012                             &ns->rx_undersize);
2013         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2014                             pf->offset_loaded, &os->rx_fragments,
2015                             &ns->rx_fragments);
2016         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2017                             pf->offset_loaded, &os->rx_oversize,
2018                             &ns->rx_oversize);
2019         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2020                             pf->offset_loaded, &os->rx_jabber,
2021                             &ns->rx_jabber);
2022         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2023                             I40E_GLPRT_PTC64L(hw->port),
2024                             pf->offset_loaded, &os->tx_size_64,
2025                             &ns->tx_size_64);
2026         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2027                             I40E_GLPRT_PTC127L(hw->port),
2028                             pf->offset_loaded, &os->tx_size_127,
2029                             &ns->tx_size_127);
2030         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2031                             I40E_GLPRT_PTC255L(hw->port),
2032                             pf->offset_loaded, &os->tx_size_255,
2033                             &ns->tx_size_255);
2034         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2035                             I40E_GLPRT_PTC511L(hw->port),
2036                             pf->offset_loaded, &os->tx_size_511,
2037                             &ns->tx_size_511);
2038         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2039                             I40E_GLPRT_PTC1023L(hw->port),
2040                             pf->offset_loaded, &os->tx_size_1023,
2041                             &ns->tx_size_1023);
2042         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2043                             I40E_GLPRT_PTC1522L(hw->port),
2044                             pf->offset_loaded, &os->tx_size_1522,
2045                             &ns->tx_size_1522);
2046         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2047                             I40E_GLPRT_PTC9522L(hw->port),
2048                             pf->offset_loaded, &os->tx_size_big,
2049                             &ns->tx_size_big);
2050         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2051                            pf->offset_loaded,
2052                            &os->fd_sb_match, &ns->fd_sb_match);
2053         /* GLPRT_MSPDC not supported */
2054         /* GLPRT_XEC not supported */
2055
2056         pf->offset_loaded = true;
2057
2058         if (pf->main_vsi)
2059                 i40e_update_vsi_stats(pf->main_vsi);
2060 }
2061
2062 /* Get all statistics of a port */
2063 static void
2064 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2065 {
2066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2068         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2069         unsigned i;
2070
2071         /* call read registers - updates values, now write them to struct */
2072         i40e_read_stats_registers(pf, hw);
2073
2074         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2075                         pf->main_vsi->eth_stats.rx_multicast +
2076                         pf->main_vsi->eth_stats.rx_broadcast -
2077                         pf->main_vsi->eth_stats.rx_discards;
2078         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2079                         pf->main_vsi->eth_stats.tx_multicast +
2080                         pf->main_vsi->eth_stats.tx_broadcast;
2081         stats->ibytes   = ns->eth.rx_bytes;
2082         stats->obytes   = ns->eth.tx_bytes;
2083         stats->oerrors  = ns->eth.tx_errors +
2084                         pf->main_vsi->eth_stats.tx_errors;
2085         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2086
2087         /* Rx Errors */
2088         stats->imissed  = ns->eth.rx_discards +
2089                         pf->main_vsi->eth_stats.rx_discards;
2090         stats->ierrors  = ns->crc_errors +
2091                         ns->rx_length_errors + ns->rx_undersize +
2092                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2093                         stats->imissed;
2094
2095         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2096         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2097         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2098         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2099         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2100         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2101         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2102                     ns->eth.rx_unknown_protocol);
2103         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2104         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2105         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2106         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2107         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2108         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2109
2110         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2111                     ns->tx_dropped_link_down);
2112         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2113         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2114                     ns->illegal_bytes);
2115         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2116         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2117                     ns->mac_local_faults);
2118         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2119                     ns->mac_remote_faults);
2120         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2121                     ns->rx_length_errors);
2122         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2123         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2124         for (i = 0; i < 8; i++) {
2125                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2126                                 i, ns->priority_xon_rx[i]);
2127                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2128                                 i, ns->priority_xoff_rx[i]);
2129         }
2130         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2131         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2132         for (i = 0; i < 8; i++) {
2133                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2134                                 i, ns->priority_xon_tx[i]);
2135                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2136                                 i, ns->priority_xoff_tx[i]);
2137                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2138                                 i, ns->priority_xon_2_xoff[i]);
2139         }
2140         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2141         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2142         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2143         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2144         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2145         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2146         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2147         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2148         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2149         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2150         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2151         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2152         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2153         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2154         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2155         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2156         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2157         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2158         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2159                         ns->mac_short_packet_dropped);
2160         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2161                     ns->checksum_error);
2162         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2163         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2164 }
2165
2166 /* Reset the statistics */
2167 static void
2168 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2169 {
2170         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2171         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2172
2173         /* Mark PF and VSI stats to update the offset, aka "reset" */
2174         pf->offset_loaded = false;
2175         if (pf->main_vsi)
2176                 pf->main_vsi->offset_loaded = false;
2177
2178         /* read the stats, reading current register values into offset */
2179         i40e_read_stats_registers(pf, hw);
2180 }
2181
2182 static uint32_t
2183 i40e_xstats_calc_num(void)
2184 {
2185         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2186                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2187                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2188 }
2189
2190 static int
2191 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2192                     unsigned n)
2193 {
2194         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2195         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196         unsigned i, count, prio;
2197         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2198
2199         count = i40e_xstats_calc_num();
2200         if (n < count)
2201                 return count;
2202
2203         i40e_read_stats_registers(pf, hw);
2204
2205         if (xstats == NULL)
2206                 return 0;
2207
2208         count = 0;
2209
2210         /* Get stats from i40e_eth_stats struct */
2211         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2212                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2213                          "%s", rte_i40e_stats_strings[i].name);
2214                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2215                         rte_i40e_stats_strings[i].offset);
2216                 count++;
2217         }
2218
2219         /* Get individiual stats from i40e_hw_port struct */
2220         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2221                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2222                          "%s", rte_i40e_hw_port_strings[i].name);
2223                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2224                                 rte_i40e_hw_port_strings[i].offset);
2225                 count++;
2226         }
2227
2228         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2229                 for (prio = 0; prio < 8; prio++) {
2230                         snprintf(xstats[count].name,
2231                                  sizeof(xstats[count].name),
2232                                  "rx_priority%u_%s", prio,
2233                                  rte_i40e_rxq_prio_strings[i].name);
2234                         xstats[count].value =
2235                                 *(uint64_t *)(((char *)hw_stats) +
2236                                 rte_i40e_rxq_prio_strings[i].offset +
2237                                 (sizeof(uint64_t) * prio));
2238                         count++;
2239                 }
2240         }
2241
2242         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2243                 for (prio = 0; prio < 8; prio++) {
2244                         snprintf(xstats[count].name,
2245                                  sizeof(xstats[count].name),
2246                                  "tx_priority%u_%s", prio,
2247                                  rte_i40e_txq_prio_strings[i].name);
2248                         xstats[count].value =
2249                                 *(uint64_t *)(((char *)hw_stats) +
2250                                 rte_i40e_txq_prio_strings[i].offset +
2251                                 (sizeof(uint64_t) * prio));
2252                         count++;
2253                 }
2254         }
2255
2256         return count;
2257 }
2258
2259 static int
2260 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2261                                  __rte_unused uint16_t queue_id,
2262                                  __rte_unused uint8_t stat_idx,
2263                                  __rte_unused uint8_t is_rx)
2264 {
2265         PMD_INIT_FUNC_TRACE();
2266
2267         return -ENOSYS;
2268 }
2269
2270 static void
2271 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2272 {
2273         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2274         struct i40e_vsi *vsi = pf->main_vsi;
2275
2276         dev_info->max_rx_queues = vsi->nb_qps;
2277         dev_info->max_tx_queues = vsi->nb_qps;
2278         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2279         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2280         dev_info->max_mac_addrs = vsi->max_macaddrs;
2281         dev_info->max_vfs = dev->pci_dev->max_vfs;
2282         dev_info->rx_offload_capa =
2283                 DEV_RX_OFFLOAD_VLAN_STRIP |
2284                 DEV_RX_OFFLOAD_QINQ_STRIP |
2285                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2286                 DEV_RX_OFFLOAD_UDP_CKSUM |
2287                 DEV_RX_OFFLOAD_TCP_CKSUM;
2288         dev_info->tx_offload_capa =
2289                 DEV_TX_OFFLOAD_VLAN_INSERT |
2290                 DEV_TX_OFFLOAD_QINQ_INSERT |
2291                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2292                 DEV_TX_OFFLOAD_UDP_CKSUM |
2293                 DEV_TX_OFFLOAD_TCP_CKSUM |
2294                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2295                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2296                 DEV_TX_OFFLOAD_TCP_TSO;
2297         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2298                                                 sizeof(uint32_t);
2299         dev_info->reta_size = pf->hash_lut_size;
2300         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2301
2302         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2303                 .rx_thresh = {
2304                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2305                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2306                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2307                 },
2308                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2309                 .rx_drop_en = 0,
2310         };
2311
2312         dev_info->default_txconf = (struct rte_eth_txconf) {
2313                 .tx_thresh = {
2314                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2315                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2316                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2317                 },
2318                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2319                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2320                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2321                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2322         };
2323
2324         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2325                 .nb_max = I40E_MAX_RING_DESC,
2326                 .nb_min = I40E_MIN_RING_DESC,
2327                 .nb_align = I40E_ALIGN_RING_DESC,
2328         };
2329
2330         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2331                 .nb_max = I40E_MAX_RING_DESC,
2332                 .nb_min = I40E_MIN_RING_DESC,
2333                 .nb_align = I40E_ALIGN_RING_DESC,
2334         };
2335
2336         if (pf->flags & I40E_FLAG_VMDQ) {
2337                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2338                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2339                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2340                                                 pf->max_nb_vmdq_vsi;
2341                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2342                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2343                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2344         }
2345 }
2346
2347 static int
2348 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2349 {
2350         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2351         struct i40e_vsi *vsi = pf->main_vsi;
2352         PMD_INIT_FUNC_TRACE();
2353
2354         if (on)
2355                 return i40e_vsi_add_vlan(vsi, vlan_id);
2356         else
2357                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2358 }
2359
2360 static void
2361 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2362                    __rte_unused uint16_t tpid)
2363 {
2364         PMD_INIT_FUNC_TRACE();
2365 }
2366
2367 static void
2368 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2369 {
2370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2371         struct i40e_vsi *vsi = pf->main_vsi;
2372
2373         if (mask & ETH_VLAN_STRIP_MASK) {
2374                 /* Enable or disable VLAN stripping */
2375                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2376                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2377                 else
2378                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2379         }
2380
2381         if (mask & ETH_VLAN_EXTEND_MASK) {
2382                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2383                         i40e_vsi_config_double_vlan(vsi, TRUE);
2384                 else
2385                         i40e_vsi_config_double_vlan(vsi, FALSE);
2386         }
2387 }
2388
2389 static void
2390 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2391                           __rte_unused uint16_t queue,
2392                           __rte_unused int on)
2393 {
2394         PMD_INIT_FUNC_TRACE();
2395 }
2396
2397 static int
2398 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2399 {
2400         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2401         struct i40e_vsi *vsi = pf->main_vsi;
2402         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2403         struct i40e_vsi_vlan_pvid_info info;
2404
2405         memset(&info, 0, sizeof(info));
2406         info.on = on;
2407         if (info.on)
2408                 info.config.pvid = pvid;
2409         else {
2410                 info.config.reject.tagged =
2411                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2412                 info.config.reject.untagged =
2413                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2414         }
2415
2416         return i40e_vsi_vlan_pvid_set(vsi, &info);
2417 }
2418
2419 static int
2420 i40e_dev_led_on(struct rte_eth_dev *dev)
2421 {
2422         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         uint32_t mode = i40e_led_get(hw);
2424
2425         if (mode == 0)
2426                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2427
2428         return 0;
2429 }
2430
2431 static int
2432 i40e_dev_led_off(struct rte_eth_dev *dev)
2433 {
2434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         uint32_t mode = i40e_led_get(hw);
2436
2437         if (mode != 0)
2438                 i40e_led_set(hw, 0, false);
2439
2440         return 0;
2441 }
2442
2443 static int
2444 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2445 {
2446         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2447         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2448
2449         fc_conf->pause_time = pf->fc_conf.pause_time;
2450         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2451         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2452
2453          /* Return current mode according to actual setting*/
2454         switch (hw->fc.current_mode) {
2455         case I40E_FC_FULL:
2456                 fc_conf->mode = RTE_FC_FULL;
2457                 break;
2458         case I40E_FC_TX_PAUSE:
2459                 fc_conf->mode = RTE_FC_TX_PAUSE;
2460                 break;
2461         case I40E_FC_RX_PAUSE:
2462                 fc_conf->mode = RTE_FC_RX_PAUSE;
2463                 break;
2464         case I40E_FC_NONE:
2465         default:
2466                 fc_conf->mode = RTE_FC_NONE;
2467         };
2468
2469         return 0;
2470 }
2471
2472 static int
2473 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2474 {
2475         uint32_t mflcn_reg, fctrl_reg, reg;
2476         uint32_t max_high_water;
2477         uint8_t i, aq_failure;
2478         int err;
2479         struct i40e_hw *hw;
2480         struct i40e_pf *pf;
2481         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2482                 [RTE_FC_NONE] = I40E_FC_NONE,
2483                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2484                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2485                 [RTE_FC_FULL] = I40E_FC_FULL
2486         };
2487
2488         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2489
2490         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2491         if ((fc_conf->high_water > max_high_water) ||
2492                         (fc_conf->high_water < fc_conf->low_water)) {
2493                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2494                         "High_water must <= %d.", max_high_water);
2495                 return -EINVAL;
2496         }
2497
2498         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2499         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2500         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2501
2502         pf->fc_conf.pause_time = fc_conf->pause_time;
2503         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2504         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2505
2506         PMD_INIT_FUNC_TRACE();
2507
2508         /* All the link flow control related enable/disable register
2509          * configuration is handle by the F/W
2510          */
2511         err = i40e_set_fc(hw, &aq_failure, true);
2512         if (err < 0)
2513                 return -ENOSYS;
2514
2515         if (i40e_is_40G_device(hw->device_id)) {
2516                 /* Configure flow control refresh threshold,
2517                  * the value for stat_tx_pause_refresh_timer[8]
2518                  * is used for global pause operation.
2519                  */
2520
2521                 I40E_WRITE_REG(hw,
2522                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2523                                pf->fc_conf.pause_time);
2524
2525                 /* configure the timer value included in transmitted pause
2526                  * frame,
2527                  * the value for stat_tx_pause_quanta[8] is used for global
2528                  * pause operation
2529                  */
2530                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2531                                pf->fc_conf.pause_time);
2532
2533                 fctrl_reg = I40E_READ_REG(hw,
2534                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2535
2536                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2537                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2538                 else
2539                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2540
2541                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2542                                fctrl_reg);
2543         } else {
2544                 /* Configure pause time (2 TCs per register) */
2545                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2546                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2547                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2548
2549                 /* Configure flow control refresh threshold value */
2550                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2551                                pf->fc_conf.pause_time / 2);
2552
2553                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2554
2555                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2556                  *depending on configuration
2557                  */
2558                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2559                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2560                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2561                 } else {
2562                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2563                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2564                 }
2565
2566                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2567         }
2568
2569         /* config the water marker both based on the packets and bytes */
2570         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2571                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2572                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2573         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2574                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2575                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2576         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2577                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2578                        << I40E_KILOSHIFT);
2579         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2580                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2581                        << I40E_KILOSHIFT);
2582
2583         I40E_WRITE_FLUSH(hw);
2584
2585         return 0;
2586 }
2587
2588 static int
2589 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2590                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2591 {
2592         PMD_INIT_FUNC_TRACE();
2593
2594         return -ENOSYS;
2595 }
2596
2597 /* Add a MAC address, and update filters */
2598 static void
2599 i40e_macaddr_add(struct rte_eth_dev *dev,
2600                  struct ether_addr *mac_addr,
2601                  __rte_unused uint32_t index,
2602                  uint32_t pool)
2603 {
2604         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2605         struct i40e_mac_filter_info mac_filter;
2606         struct i40e_vsi *vsi;
2607         int ret;
2608
2609         /* If VMDQ not enabled or configured, return */
2610         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2611                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2612                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2613                         pool);
2614                 return;
2615         }
2616
2617         if (pool > pf->nb_cfg_vmdq_vsi) {
2618                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2619                                 pool, pf->nb_cfg_vmdq_vsi);
2620                 return;
2621         }
2622
2623         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2624         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2625
2626         if (pool == 0)
2627                 vsi = pf->main_vsi;
2628         else
2629                 vsi = pf->vmdq[pool - 1].vsi;
2630
2631         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2632         if (ret != I40E_SUCCESS) {
2633                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2634                 return;
2635         }
2636 }
2637
2638 /* Remove a MAC address, and update filters */
2639 static void
2640 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2641 {
2642         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2643         struct i40e_vsi *vsi;
2644         struct rte_eth_dev_data *data = dev->data;
2645         struct ether_addr *macaddr;
2646         int ret;
2647         uint32_t i;
2648         uint64_t pool_sel;
2649
2650         macaddr = &(data->mac_addrs[index]);
2651
2652         pool_sel = dev->data->mac_pool_sel[index];
2653
2654         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2655                 if (pool_sel & (1ULL << i)) {
2656                         if (i == 0)
2657                                 vsi = pf->main_vsi;
2658                         else {
2659                                 /* No VMDQ pool enabled or configured */
2660                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2661                                         (i > pf->nb_cfg_vmdq_vsi)) {
2662                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2663                                                         "/configured");
2664                                         return;
2665                                 }
2666                                 vsi = pf->vmdq[i - 1].vsi;
2667                         }
2668                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2669
2670                         if (ret) {
2671                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2672                                 return;
2673                         }
2674                 }
2675         }
2676 }
2677
2678 /* Set perfect match or hash match of MAC and VLAN for a VF */
2679 static int
2680 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2681                  struct rte_eth_mac_filter *filter,
2682                  bool add)
2683 {
2684         struct i40e_hw *hw;
2685         struct i40e_mac_filter_info mac_filter;
2686         struct ether_addr old_mac;
2687         struct ether_addr *new_mac;
2688         struct i40e_pf_vf *vf = NULL;
2689         uint16_t vf_id;
2690         int ret;
2691
2692         if (pf == NULL) {
2693                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2694                 return -EINVAL;
2695         }
2696         hw = I40E_PF_TO_HW(pf);
2697
2698         if (filter == NULL) {
2699                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2700                 return -EINVAL;
2701         }
2702
2703         new_mac = &filter->mac_addr;
2704
2705         if (is_zero_ether_addr(new_mac)) {
2706                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2707                 return -EINVAL;
2708         }
2709
2710         vf_id = filter->dst_id;
2711
2712         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2713                 PMD_DRV_LOG(ERR, "Invalid argument.");
2714                 return -EINVAL;
2715         }
2716         vf = &pf->vfs[vf_id];
2717
2718         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2719                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2720                 return -EINVAL;
2721         }
2722
2723         if (add) {
2724                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2725                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2726                                 ETHER_ADDR_LEN);
2727                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2728                                  ETHER_ADDR_LEN);
2729
2730                 mac_filter.filter_type = filter->filter_type;
2731                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2732                 if (ret != I40E_SUCCESS) {
2733                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2734                         return -1;
2735                 }
2736                 ether_addr_copy(new_mac, &pf->dev_addr);
2737         } else {
2738                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2739                                 ETHER_ADDR_LEN);
2740                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2741                 if (ret != I40E_SUCCESS) {
2742                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2743                         return -1;
2744                 }
2745
2746                 /* Clear device address as it has been removed */
2747                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2748                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2749         }
2750
2751         return 0;
2752 }
2753
2754 /* MAC filter handle */
2755 static int
2756 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2757                 void *arg)
2758 {
2759         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2760         struct rte_eth_mac_filter *filter;
2761         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2762         int ret = I40E_NOT_SUPPORTED;
2763
2764         filter = (struct rte_eth_mac_filter *)(arg);
2765
2766         switch (filter_op) {
2767         case RTE_ETH_FILTER_NOP:
2768                 ret = I40E_SUCCESS;
2769                 break;
2770         case RTE_ETH_FILTER_ADD:
2771                 i40e_pf_disable_irq0(hw);
2772                 if (filter->is_vf)
2773                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2774                 i40e_pf_enable_irq0(hw);
2775                 break;
2776         case RTE_ETH_FILTER_DELETE:
2777                 i40e_pf_disable_irq0(hw);
2778                 if (filter->is_vf)
2779                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2780                 i40e_pf_enable_irq0(hw);
2781                 break;
2782         default:
2783                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2784                 ret = I40E_ERR_PARAM;
2785                 break;
2786         }
2787
2788         return ret;
2789 }
2790
2791 static int
2792 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2793 {
2794         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2795         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2796         int ret;
2797
2798         if (!lut)
2799                 return -EINVAL;
2800
2801         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2802                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2803                                           lut, lut_size);
2804                 if (ret) {
2805                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2806                         return ret;
2807                 }
2808         } else {
2809                 uint32_t *lut_dw = (uint32_t *)lut;
2810                 uint16_t i, lut_size_dw = lut_size / 4;
2811
2812                 for (i = 0; i < lut_size_dw; i++)
2813                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2814         }
2815
2816         return 0;
2817 }
2818
2819 static int
2820 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2821 {
2822         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2823         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2824         int ret;
2825
2826         if (!vsi || !lut)
2827                 return -EINVAL;
2828
2829         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2830                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2831                                           lut, lut_size);
2832                 if (ret) {
2833                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2834                         return ret;
2835                 }
2836         } else {
2837                 uint32_t *lut_dw = (uint32_t *)lut;
2838                 uint16_t i, lut_size_dw = lut_size / 4;
2839
2840                 for (i = 0; i < lut_size_dw; i++)
2841                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2842                 I40E_WRITE_FLUSH(hw);
2843         }
2844
2845         return 0;
2846 }
2847
2848 static int
2849 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2850                          struct rte_eth_rss_reta_entry64 *reta_conf,
2851                          uint16_t reta_size)
2852 {
2853         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2854         uint16_t i, lut_size = pf->hash_lut_size;
2855         uint16_t idx, shift;
2856         uint8_t *lut;
2857         int ret;
2858
2859         if (reta_size != lut_size ||
2860                 reta_size > ETH_RSS_RETA_SIZE_512) {
2861                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2862                         "(%d) doesn't match the number hardware can supported "
2863                                         "(%d)\n", reta_size, lut_size);
2864                 return -EINVAL;
2865         }
2866
2867         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2868         if (!lut) {
2869                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2870                 return -ENOMEM;
2871         }
2872         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2873         if (ret)
2874                 goto out;
2875         for (i = 0; i < reta_size; i++) {
2876                 idx = i / RTE_RETA_GROUP_SIZE;
2877                 shift = i % RTE_RETA_GROUP_SIZE;
2878                 if (reta_conf[idx].mask & (1ULL << shift))
2879                         lut[i] = reta_conf[idx].reta[shift];
2880         }
2881         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2882
2883 out:
2884         rte_free(lut);
2885
2886         return ret;
2887 }
2888
2889 static int
2890 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2891                         struct rte_eth_rss_reta_entry64 *reta_conf,
2892                         uint16_t reta_size)
2893 {
2894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2895         uint16_t i, lut_size = pf->hash_lut_size;
2896         uint16_t idx, shift;
2897         uint8_t *lut;
2898         int ret;
2899
2900         if (reta_size != lut_size ||
2901                 reta_size > ETH_RSS_RETA_SIZE_512) {
2902                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2903                         "(%d) doesn't match the number hardware can supported "
2904                                         "(%d)\n", reta_size, lut_size);
2905                 return -EINVAL;
2906         }
2907
2908         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2909         if (!lut) {
2910                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2911                 return -ENOMEM;
2912         }
2913
2914         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2915         if (ret)
2916                 goto out;
2917         for (i = 0; i < reta_size; i++) {
2918                 idx = i / RTE_RETA_GROUP_SIZE;
2919                 shift = i % RTE_RETA_GROUP_SIZE;
2920                 if (reta_conf[idx].mask & (1ULL << shift))
2921                         reta_conf[idx].reta[shift] = lut[i];
2922         }
2923
2924 out:
2925         rte_free(lut);
2926
2927         return ret;
2928 }
2929
2930 /**
2931  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2932  * @hw:   pointer to the HW structure
2933  * @mem:  pointer to mem struct to fill out
2934  * @size: size of memory requested
2935  * @alignment: what to align the allocation to
2936  **/
2937 enum i40e_status_code
2938 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2939                         struct i40e_dma_mem *mem,
2940                         u64 size,
2941                         u32 alignment)
2942 {
2943         const struct rte_memzone *mz = NULL;
2944         char z_name[RTE_MEMZONE_NAMESIZE];
2945
2946         if (!mem)
2947                 return I40E_ERR_PARAM;
2948
2949         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2950         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2951                                          alignment, RTE_PGSIZE_2M);
2952         if (!mz)
2953                 return I40E_ERR_NO_MEMORY;
2954
2955         mem->size = size;
2956         mem->va = mz->addr;
2957         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2958         mem->zone = (const void *)mz;
2959         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
2960                     "%"PRIu64, mz->name, mem->pa);
2961
2962         return I40E_SUCCESS;
2963 }
2964
2965 /**
2966  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2967  * @hw:   pointer to the HW structure
2968  * @mem:  ptr to mem struct to free
2969  **/
2970 enum i40e_status_code
2971 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2972                     struct i40e_dma_mem *mem)
2973 {
2974         if (!mem)
2975                 return I40E_ERR_PARAM;
2976
2977         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
2978                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
2979                     mem->pa);
2980         rte_memzone_free((const struct rte_memzone *)mem->zone);
2981         mem->zone = NULL;
2982         mem->va = NULL;
2983         mem->pa = (u64)0;
2984
2985         return I40E_SUCCESS;
2986 }
2987
2988 /**
2989  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2990  * @hw:   pointer to the HW structure
2991  * @mem:  pointer to mem struct to fill out
2992  * @size: size of memory requested
2993  **/
2994 enum i40e_status_code
2995 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2996                          struct i40e_virt_mem *mem,
2997                          u32 size)
2998 {
2999         if (!mem)
3000                 return I40E_ERR_PARAM;
3001
3002         mem->size = size;
3003         mem->va = rte_zmalloc("i40e", size, 0);
3004
3005         if (mem->va)
3006                 return I40E_SUCCESS;
3007         else
3008                 return I40E_ERR_NO_MEMORY;
3009 }
3010
3011 /**
3012  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3013  * @hw:   pointer to the HW structure
3014  * @mem:  pointer to mem struct to free
3015  **/
3016 enum i40e_status_code
3017 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3018                      struct i40e_virt_mem *mem)
3019 {
3020         if (!mem)
3021                 return I40E_ERR_PARAM;
3022
3023         rte_free(mem->va);
3024         mem->va = NULL;
3025
3026         return I40E_SUCCESS;
3027 }
3028
3029 void
3030 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3031 {
3032         rte_spinlock_init(&sp->spinlock);
3033 }
3034
3035 void
3036 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3037 {
3038         rte_spinlock_lock(&sp->spinlock);
3039 }
3040
3041 void
3042 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3043 {
3044         rte_spinlock_unlock(&sp->spinlock);
3045 }
3046
3047 void
3048 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3049 {
3050         return;
3051 }
3052
3053 /**
3054  * Get the hardware capabilities, which will be parsed
3055  * and saved into struct i40e_hw.
3056  */
3057 static int
3058 i40e_get_cap(struct i40e_hw *hw)
3059 {
3060         struct i40e_aqc_list_capabilities_element_resp *buf;
3061         uint16_t len, size = 0;
3062         int ret;
3063
3064         /* Calculate a huge enough buff for saving response data temporarily */
3065         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3066                                                 I40E_MAX_CAP_ELE_NUM;
3067         buf = rte_zmalloc("i40e", len, 0);
3068         if (!buf) {
3069                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3070                 return I40E_ERR_NO_MEMORY;
3071         }
3072
3073         /* Get, parse the capabilities and save it to hw */
3074         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3075                         i40e_aqc_opc_list_func_capabilities, NULL);
3076         if (ret != I40E_SUCCESS)
3077                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3078
3079         /* Free the temporary buffer after being used */
3080         rte_free(buf);
3081
3082         return ret;
3083 }
3084
3085 static int
3086 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3087 {
3088         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3089         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3090         uint16_t qp_count = 0, vsi_count = 0;
3091
3092         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3093                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3094                 return -EINVAL;
3095         }
3096         /* Add the parameter init for LFC */
3097         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3098         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3099         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3100
3101         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3102         pf->max_num_vsi = hw->func_caps.num_vsis;
3103         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3104         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3105         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3106
3107         /* FDir queue/VSI allocation */
3108         pf->fdir_qp_offset = 0;
3109         if (hw->func_caps.fd) {
3110                 pf->flags |= I40E_FLAG_FDIR;
3111                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3112         } else {
3113                 pf->fdir_nb_qps = 0;
3114         }
3115         qp_count += pf->fdir_nb_qps;
3116         vsi_count += 1;
3117
3118         /* LAN queue/VSI allocation */
3119         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3120         if (!hw->func_caps.rss) {
3121                 pf->lan_nb_qps = 1;
3122         } else {
3123                 pf->flags |= I40E_FLAG_RSS;
3124                 if (hw->mac.type == I40E_MAC_X722)
3125                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3126                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3127         }
3128         qp_count += pf->lan_nb_qps;
3129         vsi_count += 1;
3130
3131         /* VF queue/VSI allocation */
3132         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3133         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3134                 pf->flags |= I40E_FLAG_SRIOV;
3135                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3136                 pf->vf_num = dev->pci_dev->max_vfs;
3137                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3138                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3139                             pf->vf_nb_qps * pf->vf_num);
3140         } else {
3141                 pf->vf_nb_qps = 0;
3142                 pf->vf_num = 0;
3143         }
3144         qp_count += pf->vf_nb_qps * pf->vf_num;
3145         vsi_count += pf->vf_num;
3146
3147         /* VMDq queue/VSI allocation */
3148         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3149         pf->vmdq_nb_qps = 0;
3150         pf->max_nb_vmdq_vsi = 0;
3151         if (hw->func_caps.vmdq) {
3152                 if (qp_count < hw->func_caps.num_tx_qp &&
3153                         vsi_count < hw->func_caps.num_vsis) {
3154                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3155                                 qp_count) / pf->vmdq_nb_qp_max;
3156
3157                         /* Limit the maximum number of VMDq vsi to the maximum
3158                          * ethdev can support
3159                          */
3160                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3161                                 hw->func_caps.num_vsis - vsi_count);
3162                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3163                                 ETH_64_POOLS);
3164                         if (pf->max_nb_vmdq_vsi) {
3165                                 pf->flags |= I40E_FLAG_VMDQ;
3166                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3167                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3168                                             "per VMDQ VSI, in total %u queues",
3169                                             pf->max_nb_vmdq_vsi,
3170                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3171                                             pf->max_nb_vmdq_vsi);
3172                         } else {
3173                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3174                                             "VMDq");
3175                         }
3176                 } else {
3177                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3178                 }
3179         }
3180         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3181         vsi_count += pf->max_nb_vmdq_vsi;
3182
3183         if (hw->func_caps.dcb)
3184                 pf->flags |= I40E_FLAG_DCB;
3185
3186         if (qp_count > hw->func_caps.num_tx_qp) {
3187                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3188                             "the hardware maximum %u", qp_count,
3189                             hw->func_caps.num_tx_qp);
3190                 return -EINVAL;
3191         }
3192         if (vsi_count > hw->func_caps.num_vsis) {
3193                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3194                             "the hardware maximum %u", vsi_count,
3195                             hw->func_caps.num_vsis);
3196                 return -EINVAL;
3197         }
3198
3199         return 0;
3200 }
3201
3202 static int
3203 i40e_pf_get_switch_config(struct i40e_pf *pf)
3204 {
3205         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3206         struct i40e_aqc_get_switch_config_resp *switch_config;
3207         struct i40e_aqc_switch_config_element_resp *element;
3208         uint16_t start_seid = 0, num_reported;
3209         int ret;
3210
3211         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3212                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3213         if (!switch_config) {
3214                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3215                 return -ENOMEM;
3216         }
3217
3218         /* Get the switch configurations */
3219         ret = i40e_aq_get_switch_config(hw, switch_config,
3220                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3221         if (ret != I40E_SUCCESS) {
3222                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3223                 goto fail;
3224         }
3225         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3226         if (num_reported != 1) { /* The number should be 1 */
3227                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3228                 goto fail;
3229         }
3230
3231         /* Parse the switch configuration elements */
3232         element = &(switch_config->element[0]);
3233         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3234                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3235                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3236         } else
3237                 PMD_DRV_LOG(INFO, "Unknown element type");
3238
3239 fail:
3240         rte_free(switch_config);
3241
3242         return ret;
3243 }
3244
3245 static int
3246 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3247                         uint32_t num)
3248 {
3249         struct pool_entry *entry;
3250
3251         if (pool == NULL || num == 0)
3252                 return -EINVAL;
3253
3254         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3255         if (entry == NULL) {
3256                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3257                 return -ENOMEM;
3258         }
3259
3260         /* queue heap initialize */
3261         pool->num_free = num;
3262         pool->num_alloc = 0;
3263         pool->base = base;
3264         LIST_INIT(&pool->alloc_list);
3265         LIST_INIT(&pool->free_list);
3266
3267         /* Initialize element  */
3268         entry->base = 0;
3269         entry->len = num;
3270
3271         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3272         return 0;
3273 }
3274
3275 static void
3276 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3277 {
3278         struct pool_entry *entry;
3279
3280         if (pool == NULL)
3281                 return;
3282
3283         LIST_FOREACH(entry, &pool->alloc_list, next) {
3284                 LIST_REMOVE(entry, next);
3285                 rte_free(entry);
3286         }
3287
3288         LIST_FOREACH(entry, &pool->free_list, next) {
3289                 LIST_REMOVE(entry, next);
3290                 rte_free(entry);
3291         }
3292
3293         pool->num_free = 0;
3294         pool->num_alloc = 0;
3295         pool->base = 0;
3296         LIST_INIT(&pool->alloc_list);
3297         LIST_INIT(&pool->free_list);
3298 }
3299
3300 static int
3301 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3302                        uint32_t base)
3303 {
3304         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3305         uint32_t pool_offset;
3306         int insert;
3307
3308         if (pool == NULL) {
3309                 PMD_DRV_LOG(ERR, "Invalid parameter");
3310                 return -EINVAL;
3311         }
3312
3313         pool_offset = base - pool->base;
3314         /* Lookup in alloc list */
3315         LIST_FOREACH(entry, &pool->alloc_list, next) {
3316                 if (entry->base == pool_offset) {
3317                         valid_entry = entry;
3318                         LIST_REMOVE(entry, next);
3319                         break;
3320                 }
3321         }
3322
3323         /* Not find, return */
3324         if (valid_entry == NULL) {
3325                 PMD_DRV_LOG(ERR, "Failed to find entry");
3326                 return -EINVAL;
3327         }
3328
3329         /**
3330          * Found it, move it to free list  and try to merge.
3331          * In order to make merge easier, always sort it by qbase.
3332          * Find adjacent prev and last entries.
3333          */
3334         prev = next = NULL;
3335         LIST_FOREACH(entry, &pool->free_list, next) {
3336                 if (entry->base > valid_entry->base) {
3337                         next = entry;
3338                         break;
3339                 }
3340                 prev = entry;
3341         }
3342
3343         insert = 0;
3344         /* Try to merge with next one*/
3345         if (next != NULL) {
3346                 /* Merge with next one */
3347                 if (valid_entry->base + valid_entry->len == next->base) {
3348                         next->base = valid_entry->base;
3349                         next->len += valid_entry->len;
3350                         rte_free(valid_entry);
3351                         valid_entry = next;
3352                         insert = 1;
3353                 }
3354         }
3355
3356         if (prev != NULL) {
3357                 /* Merge with previous one */
3358                 if (prev->base + prev->len == valid_entry->base) {
3359                         prev->len += valid_entry->len;
3360                         /* If it merge with next one, remove next node */
3361                         if (insert == 1) {
3362                                 LIST_REMOVE(valid_entry, next);
3363                                 rte_free(valid_entry);
3364                         } else {
3365                                 rte_free(valid_entry);
3366                                 insert = 1;
3367                         }
3368                 }
3369         }
3370
3371         /* Not find any entry to merge, insert */
3372         if (insert == 0) {
3373                 if (prev != NULL)
3374                         LIST_INSERT_AFTER(prev, valid_entry, next);
3375                 else if (next != NULL)
3376                         LIST_INSERT_BEFORE(next, valid_entry, next);
3377                 else /* It's empty list, insert to head */
3378                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3379         }
3380
3381         pool->num_free += valid_entry->len;
3382         pool->num_alloc -= valid_entry->len;
3383
3384         return 0;
3385 }
3386
3387 static int
3388 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3389                        uint16_t num)
3390 {
3391         struct pool_entry *entry, *valid_entry;
3392
3393         if (pool == NULL || num == 0) {
3394                 PMD_DRV_LOG(ERR, "Invalid parameter");
3395                 return -EINVAL;
3396         }
3397
3398         if (pool->num_free < num) {
3399                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3400                             num, pool->num_free);
3401                 return -ENOMEM;
3402         }
3403
3404         valid_entry = NULL;
3405         /* Lookup  in free list and find most fit one */
3406         LIST_FOREACH(entry, &pool->free_list, next) {
3407                 if (entry->len >= num) {
3408                         /* Find best one */
3409                         if (entry->len == num) {
3410                                 valid_entry = entry;
3411                                 break;
3412                         }
3413                         if (valid_entry == NULL || valid_entry->len > entry->len)
3414                                 valid_entry = entry;
3415                 }
3416         }
3417
3418         /* Not find one to satisfy the request, return */
3419         if (valid_entry == NULL) {
3420                 PMD_DRV_LOG(ERR, "No valid entry found");
3421                 return -ENOMEM;
3422         }
3423         /**
3424          * The entry have equal queue number as requested,
3425          * remove it from alloc_list.
3426          */
3427         if (valid_entry->len == num) {
3428                 LIST_REMOVE(valid_entry, next);
3429         } else {
3430                 /**
3431                  * The entry have more numbers than requested,
3432                  * create a new entry for alloc_list and minus its
3433                  * queue base and number in free_list.
3434                  */
3435                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3436                 if (entry == NULL) {
3437                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3438                                     "resource pool");
3439                         return -ENOMEM;
3440                 }
3441                 entry->base = valid_entry->base;
3442                 entry->len = num;
3443                 valid_entry->base += num;
3444                 valid_entry->len -= num;
3445                 valid_entry = entry;
3446         }
3447
3448         /* Insert it into alloc list, not sorted */
3449         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3450
3451         pool->num_free -= valid_entry->len;
3452         pool->num_alloc += valid_entry->len;
3453
3454         return (valid_entry->base + pool->base);
3455 }
3456
3457 /**
3458  * bitmap_is_subset - Check whether src2 is subset of src1
3459  **/
3460 static inline int
3461 bitmap_is_subset(uint8_t src1, uint8_t src2)
3462 {
3463         return !((src1 ^ src2) & src2);
3464 }
3465
3466 static enum i40e_status_code
3467 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3468 {
3469         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3470
3471         /* If DCB is not supported, only default TC is supported */
3472         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3473                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3474                 return I40E_NOT_SUPPORTED;
3475         }
3476
3477         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3478                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3479                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3480                             enabled_tcmap);
3481                 return I40E_NOT_SUPPORTED;
3482         }
3483         return I40E_SUCCESS;
3484 }
3485
3486 int
3487 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3488                                 struct i40e_vsi_vlan_pvid_info *info)
3489 {
3490         struct i40e_hw *hw;
3491         struct i40e_vsi_context ctxt;
3492         uint8_t vlan_flags = 0;
3493         int ret;
3494
3495         if (vsi == NULL || info == NULL) {
3496                 PMD_DRV_LOG(ERR, "invalid parameters");
3497                 return I40E_ERR_PARAM;
3498         }
3499
3500         if (info->on) {
3501                 vsi->info.pvid = info->config.pvid;
3502                 /**
3503                  * If insert pvid is enabled, only tagged pkts are
3504                  * allowed to be sent out.
3505                  */
3506                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3507                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3508         } else {
3509                 vsi->info.pvid = 0;
3510                 if (info->config.reject.tagged == 0)
3511                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3512
3513                 if (info->config.reject.untagged == 0)
3514                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3515         }
3516         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3517                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3518         vsi->info.port_vlan_flags |= vlan_flags;
3519         vsi->info.valid_sections =
3520                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3521         memset(&ctxt, 0, sizeof(ctxt));
3522         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3523         ctxt.seid = vsi->seid;
3524
3525         hw = I40E_VSI_TO_HW(vsi);
3526         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3527         if (ret != I40E_SUCCESS)
3528                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3529
3530         return ret;
3531 }
3532
3533 static int
3534 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3535 {
3536         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3537         int i, ret;
3538         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3539
3540         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3541         if (ret != I40E_SUCCESS)
3542                 return ret;
3543
3544         if (!vsi->seid) {
3545                 PMD_DRV_LOG(ERR, "seid not valid");
3546                 return -EINVAL;
3547         }
3548
3549         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3550         tc_bw_data.tc_valid_bits = enabled_tcmap;
3551         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3552                 tc_bw_data.tc_bw_credits[i] =
3553                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3554
3555         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3556         if (ret != I40E_SUCCESS) {
3557                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3558                 return ret;
3559         }
3560
3561         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3562                                         sizeof(vsi->info.qs_handle));
3563         return I40E_SUCCESS;
3564 }
3565
3566 static enum i40e_status_code
3567 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3568                                  struct i40e_aqc_vsi_properties_data *info,
3569                                  uint8_t enabled_tcmap)
3570 {
3571         enum i40e_status_code ret;
3572         int i, total_tc = 0;
3573         uint16_t qpnum_per_tc, bsf, qp_idx;
3574
3575         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3576         if (ret != I40E_SUCCESS)
3577                 return ret;
3578
3579         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3580                 if (enabled_tcmap & (1 << i))
3581                         total_tc++;
3582         vsi->enabled_tc = enabled_tcmap;
3583
3584         /* Number of queues per enabled TC */
3585         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3586         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3587         bsf = rte_bsf32(qpnum_per_tc);
3588
3589         /* Adjust the queue number to actual queues that can be applied */
3590         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3591                 vsi->nb_qps = qpnum_per_tc * total_tc;
3592
3593         /**
3594          * Configure TC and queue mapping parameters, for enabled TC,
3595          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3596          * default queue will serve it.
3597          */
3598         qp_idx = 0;
3599         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3600                 if (vsi->enabled_tc & (1 << i)) {
3601                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3602                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3603                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3604                         qp_idx += qpnum_per_tc;
3605                 } else
3606                         info->tc_mapping[i] = 0;
3607         }
3608
3609         /* Associate queue number with VSI */
3610         if (vsi->type == I40E_VSI_SRIOV) {
3611                 info->mapping_flags |=
3612                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3613                 for (i = 0; i < vsi->nb_qps; i++)
3614                         info->queue_mapping[i] =
3615                                 rte_cpu_to_le_16(vsi->base_queue + i);
3616         } else {
3617                 info->mapping_flags |=
3618                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3619                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3620         }
3621         info->valid_sections |=
3622                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3623
3624         return I40E_SUCCESS;
3625 }
3626
3627 static int
3628 i40e_veb_release(struct i40e_veb *veb)
3629 {
3630         struct i40e_vsi *vsi;
3631         struct i40e_hw *hw;
3632
3633         if (veb == NULL || veb->associate_vsi == NULL)
3634                 return -EINVAL;
3635
3636         if (!TAILQ_EMPTY(&veb->head)) {
3637                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3638                 return -EACCES;
3639         }
3640
3641         vsi = veb->associate_vsi;
3642         hw = I40E_VSI_TO_HW(vsi);
3643
3644         vsi->uplink_seid = veb->uplink_seid;
3645         i40e_aq_delete_element(hw, veb->seid, NULL);
3646         rte_free(veb);
3647         vsi->veb = NULL;
3648         return I40E_SUCCESS;
3649 }
3650
3651 /* Setup a veb */
3652 static struct i40e_veb *
3653 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3654 {
3655         struct i40e_veb *veb;
3656         int ret;
3657         struct i40e_hw *hw;
3658
3659         if (NULL == pf || vsi == NULL) {
3660                 PMD_DRV_LOG(ERR, "veb setup failed, "
3661                             "associated VSI shouldn't null");
3662                 return NULL;
3663         }
3664         hw = I40E_PF_TO_HW(pf);
3665
3666         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3667         if (!veb) {
3668                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3669                 goto fail;
3670         }
3671
3672         veb->associate_vsi = vsi;
3673         TAILQ_INIT(&veb->head);
3674         veb->uplink_seid = vsi->uplink_seid;
3675
3676         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3677                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3678
3679         if (ret != I40E_SUCCESS) {
3680                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3681                             hw->aq.asq_last_status);
3682                 goto fail;
3683         }
3684
3685         /* get statistics index */
3686         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3687                                 &veb->stats_idx, NULL, NULL, NULL);
3688         if (ret != I40E_SUCCESS) {
3689                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3690                             hw->aq.asq_last_status);
3691                 goto fail;
3692         }
3693
3694         /* Get VEB bandwidth, to be implemented */
3695         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3696         vsi->uplink_seid = veb->seid;
3697
3698         return veb;
3699 fail:
3700         rte_free(veb);
3701         return NULL;
3702 }
3703
3704 int
3705 i40e_vsi_release(struct i40e_vsi *vsi)
3706 {
3707         struct i40e_pf *pf;
3708         struct i40e_hw *hw;
3709         struct i40e_vsi_list *vsi_list;
3710         int ret;
3711         struct i40e_mac_filter *f;
3712
3713         if (!vsi)
3714                 return I40E_SUCCESS;
3715
3716         pf = I40E_VSI_TO_PF(vsi);
3717         hw = I40E_VSI_TO_HW(vsi);
3718
3719         /* VSI has child to attach, release child first */
3720         if (vsi->veb) {
3721                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3722                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3723                                 return -1;
3724                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3725                 }
3726                 i40e_veb_release(vsi->veb);
3727         }
3728
3729         /* Remove all macvlan filters of the VSI */
3730         i40e_vsi_remove_all_macvlan_filter(vsi);
3731         TAILQ_FOREACH(f, &vsi->mac_list, next)
3732                 rte_free(f);
3733
3734         if (vsi->type != I40E_VSI_MAIN) {
3735                 /* Remove vsi from parent's sibling list */
3736                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3737                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3738                         return I40E_ERR_PARAM;
3739                 }
3740                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3741                                 &vsi->sib_vsi_list, list);
3742
3743                 /* Remove all switch element of the VSI */
3744                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3745                 if (ret != I40E_SUCCESS)
3746                         PMD_DRV_LOG(ERR, "Failed to delete element");
3747         }
3748         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3749
3750         if (vsi->type != I40E_VSI_SRIOV)
3751                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3752         rte_free(vsi);
3753
3754         return I40E_SUCCESS;
3755 }
3756
3757 static int
3758 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3759 {
3760         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3761         struct i40e_aqc_remove_macvlan_element_data def_filter;
3762         struct i40e_mac_filter_info filter;
3763         int ret;
3764
3765         if (vsi->type != I40E_VSI_MAIN)
3766                 return I40E_ERR_CONFIG;
3767         memset(&def_filter, 0, sizeof(def_filter));
3768         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3769                                         ETH_ADDR_LEN);
3770         def_filter.vlan_tag = 0;
3771         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3772                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3773         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3774         if (ret != I40E_SUCCESS) {
3775                 struct i40e_mac_filter *f;
3776                 struct ether_addr *mac;
3777
3778                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3779                             "macvlan filter");
3780                 /* It needs to add the permanent mac into mac list */
3781                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3782                 if (f == NULL) {
3783                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3784                         return I40E_ERR_NO_MEMORY;
3785                 }
3786                 mac = &f->mac_info.mac_addr;
3787                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3788                                 ETH_ADDR_LEN);
3789                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3790                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3791                 vsi->mac_num++;
3792
3793                 return ret;
3794         }
3795         (void)rte_memcpy(&filter.mac_addr,
3796                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3797         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3798         return i40e_vsi_add_mac(vsi, &filter);
3799 }
3800
3801 static int
3802 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3803 {
3804         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3805         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3806         struct i40e_hw *hw = &vsi->adapter->hw;
3807         i40e_status ret;
3808         int i;
3809
3810         memset(&bw_config, 0, sizeof(bw_config));
3811         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3812         if (ret != I40E_SUCCESS) {
3813                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3814                             hw->aq.asq_last_status);
3815                 return ret;
3816         }
3817
3818         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3819         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3820                                         &ets_sla_config, NULL);
3821         if (ret != I40E_SUCCESS) {
3822                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3823                             "configuration %u", hw->aq.asq_last_status);
3824                 return ret;
3825         }
3826
3827         /* Not store the info yet, just print out */
3828         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3829         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3830         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3831                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3832                             ets_sla_config.share_credits[i]);
3833                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3834                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3835                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3836                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3837                             (i * 4));
3838         }
3839
3840         return 0;
3841 }
3842
3843 /* Setup a VSI */
3844 struct i40e_vsi *
3845 i40e_vsi_setup(struct i40e_pf *pf,
3846                enum i40e_vsi_type type,
3847                struct i40e_vsi *uplink_vsi,
3848                uint16_t user_param)
3849 {
3850         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3851         struct i40e_vsi *vsi;
3852         struct i40e_mac_filter_info filter;
3853         int ret;
3854         struct i40e_vsi_context ctxt;
3855         struct ether_addr broadcast =
3856                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3857
3858         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3859                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3860                             "VSI link shouldn't be NULL");
3861                 return NULL;
3862         }
3863
3864         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3865                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3866                             "uplink VSI should be NULL");
3867                 return NULL;
3868         }
3869
3870         /* If uplink vsi didn't setup VEB, create one first */
3871         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3872                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3873
3874                 if (NULL == uplink_vsi->veb) {
3875                         PMD_DRV_LOG(ERR, "VEB setup failed");
3876                         return NULL;
3877                 }
3878         }
3879
3880         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3881         if (!vsi) {
3882                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3883                 return NULL;
3884         }
3885         TAILQ_INIT(&vsi->mac_list);
3886         vsi->type = type;
3887         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3888         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3889         vsi->parent_vsi = uplink_vsi;
3890         vsi->user_param = user_param;
3891         /* Allocate queues */
3892         switch (vsi->type) {
3893         case I40E_VSI_MAIN  :
3894                 vsi->nb_qps = pf->lan_nb_qps;
3895                 break;
3896         case I40E_VSI_SRIOV :
3897                 vsi->nb_qps = pf->vf_nb_qps;
3898                 break;
3899         case I40E_VSI_VMDQ2:
3900                 vsi->nb_qps = pf->vmdq_nb_qps;
3901                 break;
3902         case I40E_VSI_FDIR:
3903                 vsi->nb_qps = pf->fdir_nb_qps;
3904                 break;
3905         default:
3906                 goto fail_mem;
3907         }
3908         /*
3909          * The filter status descriptor is reported in rx queue 0,
3910          * while the tx queue for fdir filter programming has no
3911          * such constraints, can be non-zero queues.
3912          * To simplify it, choose FDIR vsi use queue 0 pair.
3913          * To make sure it will use queue 0 pair, queue allocation
3914          * need be done before this function is called
3915          */
3916         if (type != I40E_VSI_FDIR) {
3917                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3918                         if (ret < 0) {
3919                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3920                                                 vsi->seid, ret);
3921                                 goto fail_mem;
3922                         }
3923                         vsi->base_queue = ret;
3924         } else
3925                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3926
3927         /* VF has MSIX interrupt in VF range, don't allocate here */
3928         if (type == I40E_VSI_MAIN) {
3929                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3930                                           RTE_MIN(vsi->nb_qps,
3931                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3932                 if (ret < 0) {
3933                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3934                                     vsi->seid, ret);
3935                         goto fail_queue_alloc;
3936                 }
3937                 vsi->msix_intr = ret;
3938                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3939         } else if (type != I40E_VSI_SRIOV) {
3940                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3941                 if (ret < 0) {
3942                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3943                         goto fail_queue_alloc;
3944                 }
3945                 vsi->msix_intr = ret;
3946                 vsi->nb_msix = 1;
3947         } else {
3948                 vsi->msix_intr = 0;
3949                 vsi->nb_msix = 0;
3950         }
3951
3952         /* Add VSI */
3953         if (type == I40E_VSI_MAIN) {
3954                 /* For main VSI, no need to add since it's default one */
3955                 vsi->uplink_seid = pf->mac_seid;
3956                 vsi->seid = pf->main_vsi_seid;
3957                 /* Bind queues with specific MSIX interrupt */
3958                 /**
3959                  * Needs 2 interrupt at least, one for misc cause which will
3960                  * enabled from OS side, Another for queues binding the
3961                  * interrupt from device side only.
3962                  */
3963
3964                 /* Get default VSI parameters from hardware */
3965                 memset(&ctxt, 0, sizeof(ctxt));
3966                 ctxt.seid = vsi->seid;
3967                 ctxt.pf_num = hw->pf_id;
3968                 ctxt.uplink_seid = vsi->uplink_seid;
3969                 ctxt.vf_num = 0;
3970                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3971                 if (ret != I40E_SUCCESS) {
3972                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3973                         goto fail_msix_alloc;
3974                 }
3975                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3976                         sizeof(struct i40e_aqc_vsi_properties_data));
3977                 vsi->vsi_id = ctxt.vsi_number;
3978                 vsi->info.valid_sections = 0;
3979
3980                 /* Configure tc, enabled TC0 only */
3981                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3982                         I40E_SUCCESS) {
3983                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3984                         goto fail_msix_alloc;
3985                 }
3986
3987                 /* TC, queue mapping */
3988                 memset(&ctxt, 0, sizeof(ctxt));
3989                 vsi->info.valid_sections |=
3990                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3991                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3992                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3993                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3994                         sizeof(struct i40e_aqc_vsi_properties_data));
3995                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3996                                                 I40E_DEFAULT_TCMAP);
3997                 if (ret != I40E_SUCCESS) {
3998                         PMD_DRV_LOG(ERR, "Failed to configure "
3999                                     "TC queue mapping");
4000                         goto fail_msix_alloc;
4001                 }
4002                 ctxt.seid = vsi->seid;
4003                 ctxt.pf_num = hw->pf_id;
4004                 ctxt.uplink_seid = vsi->uplink_seid;
4005                 ctxt.vf_num = 0;
4006
4007                 /* Update VSI parameters */
4008                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4009                 if (ret != I40E_SUCCESS) {
4010                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4011                         goto fail_msix_alloc;
4012                 }
4013
4014                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4015                                                 sizeof(vsi->info.tc_mapping));
4016                 (void)rte_memcpy(&vsi->info.queue_mapping,
4017                                 &ctxt.info.queue_mapping,
4018                         sizeof(vsi->info.queue_mapping));
4019                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4020                 vsi->info.valid_sections = 0;
4021
4022                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4023                                 ETH_ADDR_LEN);
4024
4025                 /**
4026                  * Updating default filter settings are necessary to prevent
4027                  * reception of tagged packets.
4028                  * Some old firmware configurations load a default macvlan
4029                  * filter which accepts both tagged and untagged packets.
4030                  * The updating is to use a normal filter instead if needed.
4031                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4032                  * The firmware with correct configurations load the default
4033                  * macvlan filter which is expected and cannot be removed.
4034                  */
4035                 i40e_update_default_filter_setting(vsi);
4036                 i40e_config_qinq(hw, vsi);
4037         } else if (type == I40E_VSI_SRIOV) {
4038                 memset(&ctxt, 0, sizeof(ctxt));
4039                 /**
4040                  * For other VSI, the uplink_seid equals to uplink VSI's
4041                  * uplink_seid since they share same VEB
4042                  */
4043                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4044                 ctxt.pf_num = hw->pf_id;
4045                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4046                 ctxt.uplink_seid = vsi->uplink_seid;
4047                 ctxt.connection_type = 0x1;
4048                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4049
4050                 /**
4051                  * Do not configure switch ID to enable VEB switch by
4052                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4053                  * if the source mac address of packet sent from VF is not
4054                  * listed in the VEB's mac table, the VEB will switch the
4055                  * packet back to the VF. Need to enable it when HW issue
4056                  * is fixed.
4057                  */
4058
4059                 /* Configure port/vlan */
4060                 ctxt.info.valid_sections |=
4061                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4062                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4063                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4064                                                 I40E_DEFAULT_TCMAP);
4065                 if (ret != I40E_SUCCESS) {
4066                         PMD_DRV_LOG(ERR, "Failed to configure "
4067                                     "TC queue mapping");
4068                         goto fail_msix_alloc;
4069                 }
4070                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4071                 ctxt.info.valid_sections |=
4072                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4073                 /**
4074                  * Since VSI is not created yet, only configure parameter,
4075                  * will add vsi below.
4076                  */
4077
4078                 i40e_config_qinq(hw, vsi);
4079         } else if (type == I40E_VSI_VMDQ2) {
4080                 memset(&ctxt, 0, sizeof(ctxt));
4081                 /*
4082                  * For other VSI, the uplink_seid equals to uplink VSI's
4083                  * uplink_seid since they share same VEB
4084                  */
4085                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4086                 ctxt.pf_num = hw->pf_id;
4087                 ctxt.vf_num = 0;
4088                 ctxt.uplink_seid = vsi->uplink_seid;
4089                 ctxt.connection_type = 0x1;
4090                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4091
4092                 ctxt.info.valid_sections |=
4093                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4094                 /* user_param carries flag to enable loop back */
4095                 if (user_param) {
4096                         ctxt.info.switch_id =
4097                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4098                         ctxt.info.switch_id |=
4099                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4100                 }
4101
4102                 /* Configure port/vlan */
4103                 ctxt.info.valid_sections |=
4104                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4105                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4106                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4107                                                 I40E_DEFAULT_TCMAP);
4108                 if (ret != I40E_SUCCESS) {
4109                         PMD_DRV_LOG(ERR, "Failed to configure "
4110                                         "TC queue mapping");
4111                         goto fail_msix_alloc;
4112                 }
4113                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4114                 ctxt.info.valid_sections |=
4115                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4116         } else if (type == I40E_VSI_FDIR) {
4117                 memset(&ctxt, 0, sizeof(ctxt));
4118                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4119                 ctxt.pf_num = hw->pf_id;
4120                 ctxt.vf_num = 0;
4121                 ctxt.uplink_seid = vsi->uplink_seid;
4122                 ctxt.connection_type = 0x1;     /* regular data port */
4123                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4124                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4125                                                 I40E_DEFAULT_TCMAP);
4126                 if (ret != I40E_SUCCESS) {
4127                         PMD_DRV_LOG(ERR, "Failed to configure "
4128                                         "TC queue mapping.");
4129                         goto fail_msix_alloc;
4130                 }
4131                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4132                 ctxt.info.valid_sections |=
4133                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4134         } else {
4135                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4136                 goto fail_msix_alloc;
4137         }
4138
4139         if (vsi->type != I40E_VSI_MAIN) {
4140                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4141                 if (ret != I40E_SUCCESS) {
4142                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4143                                     hw->aq.asq_last_status);
4144                         goto fail_msix_alloc;
4145                 }
4146                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4147                 vsi->info.valid_sections = 0;
4148                 vsi->seid = ctxt.seid;
4149                 vsi->vsi_id = ctxt.vsi_number;
4150                 vsi->sib_vsi_list.vsi = vsi;
4151                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4152                                 &vsi->sib_vsi_list, list);
4153         }
4154
4155         /* MAC/VLAN configuration */
4156         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4157         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4158
4159         ret = i40e_vsi_add_mac(vsi, &filter);
4160         if (ret != I40E_SUCCESS) {
4161                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4162                 goto fail_msix_alloc;
4163         }
4164
4165         /* Get VSI BW information */
4166         i40e_vsi_dump_bw_config(vsi);
4167         return vsi;
4168 fail_msix_alloc:
4169         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4170 fail_queue_alloc:
4171         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4172 fail_mem:
4173         rte_free(vsi);
4174         return NULL;
4175 }
4176
4177 /* Configure vlan stripping on or off */
4178 int
4179 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4180 {
4181         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4182         struct i40e_vsi_context ctxt;
4183         uint8_t vlan_flags;
4184         int ret = I40E_SUCCESS;
4185
4186         /* Check if it has been already on or off */
4187         if (vsi->info.valid_sections &
4188                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4189                 if (on) {
4190                         if ((vsi->info.port_vlan_flags &
4191                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4192                                 return 0; /* already on */
4193                 } else {
4194                         if ((vsi->info.port_vlan_flags &
4195                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4196                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4197                                 return 0; /* already off */
4198                 }
4199         }
4200
4201         if (on)
4202                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4203         else
4204                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4205         vsi->info.valid_sections =
4206                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4207         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4208         vsi->info.port_vlan_flags |= vlan_flags;
4209         ctxt.seid = vsi->seid;
4210         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4211         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4212         if (ret)
4213                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4214                             on ? "enable" : "disable");
4215
4216         return ret;
4217 }
4218
4219 static int
4220 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4221 {
4222         struct rte_eth_dev_data *data = dev->data;
4223         int ret;
4224
4225         /* Apply vlan offload setting */
4226         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4227
4228         /* Apply double-vlan setting, not implemented yet */
4229
4230         /* Apply pvid setting */
4231         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4232                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4233         if (ret)
4234                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4235
4236         return ret;
4237 }
4238
4239 static int
4240 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4241 {
4242         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4243
4244         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4245 }
4246
4247 static int
4248 i40e_update_flow_control(struct i40e_hw *hw)
4249 {
4250 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4251         struct i40e_link_status link_status;
4252         uint32_t rxfc = 0, txfc = 0, reg;
4253         uint8_t an_info;
4254         int ret;
4255
4256         memset(&link_status, 0, sizeof(link_status));
4257         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4258         if (ret != I40E_SUCCESS) {
4259                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4260                 goto write_reg; /* Disable flow control */
4261         }
4262
4263         an_info = hw->phy.link_info.an_info;
4264         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4265                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4266                 ret = I40E_ERR_NOT_READY;
4267                 goto write_reg; /* Disable flow control */
4268         }
4269         /**
4270          * If link auto negotiation is enabled, flow control needs to
4271          * be configured according to it
4272          */
4273         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4274         case I40E_LINK_PAUSE_RXTX:
4275                 rxfc = 1;
4276                 txfc = 1;
4277                 hw->fc.current_mode = I40E_FC_FULL;
4278                 break;
4279         case I40E_AQ_LINK_PAUSE_RX:
4280                 rxfc = 1;
4281                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4282                 break;
4283         case I40E_AQ_LINK_PAUSE_TX:
4284                 txfc = 1;
4285                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4286                 break;
4287         default:
4288                 hw->fc.current_mode = I40E_FC_NONE;
4289                 break;
4290         }
4291
4292 write_reg:
4293         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4294                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4295         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4296         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4297         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4298         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4299
4300         return ret;
4301 }
4302
4303 /* PF setup */
4304 static int
4305 i40e_pf_setup(struct i40e_pf *pf)
4306 {
4307         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4308         struct i40e_filter_control_settings settings;
4309         struct i40e_vsi *vsi;
4310         int ret;
4311
4312         /* Clear all stats counters */
4313         pf->offset_loaded = FALSE;
4314         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4315         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4316
4317         ret = i40e_pf_get_switch_config(pf);
4318         if (ret != I40E_SUCCESS) {
4319                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4320                 return ret;
4321         }
4322         if (pf->flags & I40E_FLAG_FDIR) {
4323                 /* make queue allocated first, let FDIR use queue pair 0*/
4324                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4325                 if (ret != I40E_FDIR_QUEUE_ID) {
4326                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4327                                     " ret =%d", ret);
4328                         pf->flags &= ~I40E_FLAG_FDIR;
4329                 }
4330         }
4331         /*  main VSI setup */
4332         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4333         if (!vsi) {
4334                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4335                 return I40E_ERR_NOT_READY;
4336         }
4337         pf->main_vsi = vsi;
4338
4339         /* Configure filter control */
4340         memset(&settings, 0, sizeof(settings));
4341         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4342                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4343         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4344                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4345         else {
4346                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4347                                                 hw->func_caps.rss_table_size);
4348                 return I40E_ERR_PARAM;
4349         }
4350         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4351                         "size: %u\n", hw->func_caps.rss_table_size);
4352         pf->hash_lut_size = hw->func_caps.rss_table_size;
4353
4354         /* Enable ethtype and macvlan filters */
4355         settings.enable_ethtype = TRUE;
4356         settings.enable_macvlan = TRUE;
4357         ret = i40e_set_filter_control(hw, &settings);
4358         if (ret)
4359                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4360                                                                 ret);
4361
4362         /* Update flow control according to the auto negotiation */
4363         i40e_update_flow_control(hw);
4364
4365         return I40E_SUCCESS;
4366 }
4367
4368 int
4369 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4370 {
4371         uint32_t reg;
4372         uint16_t j;
4373
4374         /**
4375          * Set or clear TX Queue Disable flags,
4376          * which is required by hardware.
4377          */
4378         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4379         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4380
4381         /* Wait until the request is finished */
4382         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4383                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4384                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4385                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4386                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4387                                                         & 0x1))) {
4388                         break;
4389                 }
4390         }
4391         if (on) {
4392                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4393                         return I40E_SUCCESS; /* already on, skip next steps */
4394
4395                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4396                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4397         } else {
4398                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4399                         return I40E_SUCCESS; /* already off, skip next steps */
4400                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4401         }
4402         /* Write the register */
4403         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4404         /* Check the result */
4405         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4406                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4407                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4408                 if (on) {
4409                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4410                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4411                                 break;
4412                 } else {
4413                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4414                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4415                                 break;
4416                 }
4417         }
4418         /* Check if it is timeout */
4419         if (j >= I40E_CHK_Q_ENA_COUNT) {
4420                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4421                             (on ? "enable" : "disable"), q_idx);
4422                 return I40E_ERR_TIMEOUT;
4423         }
4424
4425         return I40E_SUCCESS;
4426 }
4427
4428 /* Swith on or off the tx queues */
4429 static int
4430 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4431 {
4432         struct rte_eth_dev_data *dev_data = pf->dev_data;
4433         struct i40e_tx_queue *txq;
4434         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4435         uint16_t i;
4436         int ret;
4437
4438         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4439                 txq = dev_data->tx_queues[i];
4440                 /* Don't operate the queue if not configured or
4441                  * if starting only per queue */
4442                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4443                         continue;
4444                 if (on)
4445                         ret = i40e_dev_tx_queue_start(dev, i);
4446                 else
4447                         ret = i40e_dev_tx_queue_stop(dev, i);
4448                 if ( ret != I40E_SUCCESS)
4449                         return ret;
4450         }
4451
4452         return I40E_SUCCESS;
4453 }
4454
4455 int
4456 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4457 {
4458         uint32_t reg;
4459         uint16_t j;
4460
4461         /* Wait until the request is finished */
4462         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4463                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4464                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4465                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4466                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4467                         break;
4468         }
4469
4470         if (on) {
4471                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4472                         return I40E_SUCCESS; /* Already on, skip next steps */
4473                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4474         } else {
4475                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4476                         return I40E_SUCCESS; /* Already off, skip next steps */
4477                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4478         }
4479
4480         /* Write the register */
4481         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4482         /* Check the result */
4483         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4484                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4485                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4486                 if (on) {
4487                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4488                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4489                                 break;
4490                 } else {
4491                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4492                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4493                                 break;
4494                 }
4495         }
4496
4497         /* Check if it is timeout */
4498         if (j >= I40E_CHK_Q_ENA_COUNT) {
4499                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4500                             (on ? "enable" : "disable"), q_idx);
4501                 return I40E_ERR_TIMEOUT;
4502         }
4503
4504         return I40E_SUCCESS;
4505 }
4506 /* Switch on or off the rx queues */
4507 static int
4508 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4509 {
4510         struct rte_eth_dev_data *dev_data = pf->dev_data;
4511         struct i40e_rx_queue *rxq;
4512         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4513         uint16_t i;
4514         int ret;
4515
4516         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4517                 rxq = dev_data->rx_queues[i];
4518                 /* Don't operate the queue if not configured or
4519                  * if starting only per queue */
4520                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4521                         continue;
4522                 if (on)
4523                         ret = i40e_dev_rx_queue_start(dev, i);
4524                 else
4525                         ret = i40e_dev_rx_queue_stop(dev, i);
4526                 if (ret != I40E_SUCCESS)
4527                         return ret;
4528         }
4529
4530         return I40E_SUCCESS;
4531 }
4532
4533 /* Switch on or off all the rx/tx queues */
4534 int
4535 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4536 {
4537         int ret;
4538
4539         if (on) {
4540                 /* enable rx queues before enabling tx queues */
4541                 ret = i40e_dev_switch_rx_queues(pf, on);
4542                 if (ret) {
4543                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4544                         return ret;
4545                 }
4546                 ret = i40e_dev_switch_tx_queues(pf, on);
4547         } else {
4548                 /* Stop tx queues before stopping rx queues */
4549                 ret = i40e_dev_switch_tx_queues(pf, on);
4550                 if (ret) {
4551                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4552                         return ret;
4553                 }
4554                 ret = i40e_dev_switch_rx_queues(pf, on);
4555         }
4556
4557         return ret;
4558 }
4559
4560 /* Initialize VSI for TX */
4561 static int
4562 i40e_dev_tx_init(struct i40e_pf *pf)
4563 {
4564         struct rte_eth_dev_data *data = pf->dev_data;
4565         uint16_t i;
4566         uint32_t ret = I40E_SUCCESS;
4567         struct i40e_tx_queue *txq;
4568
4569         for (i = 0; i < data->nb_tx_queues; i++) {
4570                 txq = data->tx_queues[i];
4571                 if (!txq || !txq->q_set)
4572                         continue;
4573                 ret = i40e_tx_queue_init(txq);
4574                 if (ret != I40E_SUCCESS)
4575                         break;
4576         }
4577         if (ret == I40E_SUCCESS)
4578                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4579                                      ->eth_dev);
4580
4581         return ret;
4582 }
4583
4584 /* Initialize VSI for RX */
4585 static int
4586 i40e_dev_rx_init(struct i40e_pf *pf)
4587 {
4588         struct rte_eth_dev_data *data = pf->dev_data;
4589         int ret = I40E_SUCCESS;
4590         uint16_t i;
4591         struct i40e_rx_queue *rxq;
4592
4593         i40e_pf_config_mq_rx(pf);
4594         for (i = 0; i < data->nb_rx_queues; i++) {
4595                 rxq = data->rx_queues[i];
4596                 if (!rxq || !rxq->q_set)
4597                         continue;
4598
4599                 ret = i40e_rx_queue_init(rxq);
4600                 if (ret != I40E_SUCCESS) {
4601                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4602                                     "initialization");
4603                         break;
4604                 }
4605         }
4606         if (ret == I40E_SUCCESS)
4607                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4608                                      ->eth_dev);
4609
4610         return ret;
4611 }
4612
4613 static int
4614 i40e_dev_rxtx_init(struct i40e_pf *pf)
4615 {
4616         int err;
4617
4618         err = i40e_dev_tx_init(pf);
4619         if (err) {
4620                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4621                 return err;
4622         }
4623         err = i40e_dev_rx_init(pf);
4624         if (err) {
4625                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4626                 return err;
4627         }
4628
4629         return err;
4630 }
4631
4632 static int
4633 i40e_vmdq_setup(struct rte_eth_dev *dev)
4634 {
4635         struct rte_eth_conf *conf = &dev->data->dev_conf;
4636         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4637         int i, err, conf_vsis, j, loop;
4638         struct i40e_vsi *vsi;
4639         struct i40e_vmdq_info *vmdq_info;
4640         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4641         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4642
4643         /*
4644          * Disable interrupt to avoid message from VF. Furthermore, it will
4645          * avoid race condition in VSI creation/destroy.
4646          */
4647         i40e_pf_disable_irq0(hw);
4648
4649         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4650                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4651                 return -ENOTSUP;
4652         }
4653
4654         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4655         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4656                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4657                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4658                         pf->max_nb_vmdq_vsi);
4659                 return -ENOTSUP;
4660         }
4661
4662         if (pf->vmdq != NULL) {
4663                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4664                 return 0;
4665         }
4666
4667         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4668                                 sizeof(*vmdq_info) * conf_vsis, 0);
4669
4670         if (pf->vmdq == NULL) {
4671                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4672                 return -ENOMEM;
4673         }
4674
4675         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4676
4677         /* Create VMDQ VSI */
4678         for (i = 0; i < conf_vsis; i++) {
4679                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4680                                 vmdq_conf->enable_loop_back);
4681                 if (vsi == NULL) {
4682                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4683                         err = -1;
4684                         goto err_vsi_setup;
4685                 }
4686                 vmdq_info = &pf->vmdq[i];
4687                 vmdq_info->pf = pf;
4688                 vmdq_info->vsi = vsi;
4689         }
4690         pf->nb_cfg_vmdq_vsi = conf_vsis;
4691
4692         /* Configure Vlan */
4693         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4694         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4695                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4696                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4697                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4698                                         vmdq_conf->pool_map[i].vlan_id, j);
4699
4700                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4701                                                 vmdq_conf->pool_map[i].vlan_id);
4702                                 if (err) {
4703                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4704                                         err = -1;
4705                                         goto err_vsi_setup;
4706                                 }
4707                         }
4708                 }
4709         }
4710
4711         i40e_pf_enable_irq0(hw);
4712
4713         return 0;
4714
4715 err_vsi_setup:
4716         for (i = 0; i < conf_vsis; i++)
4717                 if (pf->vmdq[i].vsi == NULL)
4718                         break;
4719                 else
4720                         i40e_vsi_release(pf->vmdq[i].vsi);
4721
4722         rte_free(pf->vmdq);
4723         pf->vmdq = NULL;
4724         i40e_pf_enable_irq0(hw);
4725         return err;
4726 }
4727
4728 static void
4729 i40e_stat_update_32(struct i40e_hw *hw,
4730                    uint32_t reg,
4731                    bool offset_loaded,
4732                    uint64_t *offset,
4733                    uint64_t *stat)
4734 {
4735         uint64_t new_data;
4736
4737         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4738         if (!offset_loaded)
4739                 *offset = new_data;
4740
4741         if (new_data >= *offset)
4742                 *stat = (uint64_t)(new_data - *offset);
4743         else
4744                 *stat = (uint64_t)((new_data +
4745                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4746 }
4747
4748 static void
4749 i40e_stat_update_48(struct i40e_hw *hw,
4750                    uint32_t hireg,
4751                    uint32_t loreg,
4752                    bool offset_loaded,
4753                    uint64_t *offset,
4754                    uint64_t *stat)
4755 {
4756         uint64_t new_data;
4757
4758         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4759         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4760                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4761
4762         if (!offset_loaded)
4763                 *offset = new_data;
4764
4765         if (new_data >= *offset)
4766                 *stat = new_data - *offset;
4767         else
4768                 *stat = (uint64_t)((new_data +
4769                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4770
4771         *stat &= I40E_48_BIT_MASK;
4772 }
4773
4774 /* Disable IRQ0 */
4775 void
4776 i40e_pf_disable_irq0(struct i40e_hw *hw)
4777 {
4778         /* Disable all interrupt types */
4779         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4780         I40E_WRITE_FLUSH(hw);
4781 }
4782
4783 /* Enable IRQ0 */
4784 void
4785 i40e_pf_enable_irq0(struct i40e_hw *hw)
4786 {
4787         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4788                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4789                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4790                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4791         I40E_WRITE_FLUSH(hw);
4792 }
4793
4794 static void
4795 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4796 {
4797         /* read pending request and disable first */
4798         i40e_pf_disable_irq0(hw);
4799         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4800         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4801                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4802
4803         if (no_queue)
4804                 /* Link no queues with irq0 */
4805                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4806                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4807 }
4808
4809 static void
4810 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4811 {
4812         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4813         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4814         int i;
4815         uint16_t abs_vf_id;
4816         uint32_t index, offset, val;
4817
4818         if (!pf->vfs)
4819                 return;
4820         /**
4821          * Try to find which VF trigger a reset, use absolute VF id to access
4822          * since the reg is global register.
4823          */
4824         for (i = 0; i < pf->vf_num; i++) {
4825                 abs_vf_id = hw->func_caps.vf_base_id + i;
4826                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4827                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4828                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4829                 /* VFR event occured */
4830                 if (val & (0x1 << offset)) {
4831                         int ret;
4832
4833                         /* Clear the event first */
4834                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4835                                                         (0x1 << offset));
4836                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4837                         /**
4838                          * Only notify a VF reset event occured,
4839                          * don't trigger another SW reset
4840                          */
4841                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4842                         if (ret != I40E_SUCCESS)
4843                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4844                 }
4845         }
4846 }
4847
4848 static void
4849 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4850 {
4851         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4852         struct i40e_arq_event_info info;
4853         uint16_t pending, opcode;
4854         int ret;
4855
4856         info.buf_len = I40E_AQ_BUF_SZ;
4857         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4858         if (!info.msg_buf) {
4859                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4860                 return;
4861         }
4862
4863         pending = 1;
4864         while (pending) {
4865                 ret = i40e_clean_arq_element(hw, &info, &pending);
4866
4867                 if (ret != I40E_SUCCESS) {
4868                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4869                                     "aq_err: %u", hw->aq.asq_last_status);
4870                         break;
4871                 }
4872                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4873
4874                 switch (opcode) {
4875                 case i40e_aqc_opc_send_msg_to_pf:
4876                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4877                         i40e_pf_host_handle_vf_msg(dev,
4878                                         rte_le_to_cpu_16(info.desc.retval),
4879                                         rte_le_to_cpu_32(info.desc.cookie_high),
4880                                         rte_le_to_cpu_32(info.desc.cookie_low),
4881                                         info.msg_buf,
4882                                         info.msg_len);
4883                         break;
4884                 default:
4885                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4886                                     opcode);
4887                         break;
4888                 }
4889         }
4890         rte_free(info.msg_buf);
4891 }
4892
4893 /*
4894  * Interrupt handler is registered as the alarm callback for handling LSC
4895  * interrupt in a definite of time, in order to wait the NIC into a stable
4896  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4897  * no need for link down interrupt.
4898  */
4899 static void
4900 i40e_dev_interrupt_delayed_handler(void *param)
4901 {
4902         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4903         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4904         uint32_t icr0;
4905
4906         /* read interrupt causes again */
4907         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4908
4909 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4910         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4911                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4912         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4913                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4914         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4915                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4916         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4917                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4918         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4919                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4920                                                                 "state\n");
4921         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4922                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4923         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4924                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4925 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4926
4927         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4928                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4929                 i40e_dev_handle_vfr_event(dev);
4930         }
4931         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4932                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4933                 i40e_dev_handle_aq_msg(dev);
4934         }
4935
4936         /* handle the link up interrupt in an alarm callback */
4937         i40e_dev_link_update(dev, 0);
4938         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4939
4940         i40e_pf_enable_irq0(hw);
4941         rte_intr_enable(&(dev->pci_dev->intr_handle));
4942 }
4943
4944 /**
4945  * Interrupt handler triggered by NIC  for handling
4946  * specific interrupt.
4947  *
4948  * @param handle
4949  *  Pointer to interrupt handle.
4950  * @param param
4951  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4952  *
4953  * @return
4954  *  void
4955  */
4956 static void
4957 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4958                            void *param)
4959 {
4960         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4962         uint32_t icr0;
4963
4964         /* Disable interrupt */
4965         i40e_pf_disable_irq0(hw);
4966
4967         /* read out interrupt causes */
4968         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4969
4970         /* No interrupt event indicated */
4971         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4972                 PMD_DRV_LOG(INFO, "No interrupt event");
4973                 goto done;
4974         }
4975 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4976         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4977                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4978         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4979                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4980         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4981                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4982         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4983                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4984         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4985                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4986         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4987                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4988         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4989                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4990 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4991
4992         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4993                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4994                 i40e_dev_handle_vfr_event(dev);
4995         }
4996         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4997                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4998                 i40e_dev_handle_aq_msg(dev);
4999         }
5000
5001         /* Link Status Change interrupt */
5002         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5003 #define I40E_US_PER_SECOND 1000000
5004                 struct rte_eth_link link;
5005
5006                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5007                 memset(&link, 0, sizeof(link));
5008                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5009                 i40e_dev_link_update(dev, 0);
5010
5011                 /*
5012                  * For link up interrupt, it needs to wait 1 second to let the
5013                  * hardware be a stable state. Otherwise several consecutive
5014                  * interrupts can be observed.
5015                  * For link down interrupt, no need to wait.
5016                  */
5017                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5018                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5019                         return;
5020                 else
5021                         _rte_eth_dev_callback_process(dev,
5022                                 RTE_ETH_EVENT_INTR_LSC);
5023         }
5024
5025 done:
5026         /* Enable interrupt */
5027         i40e_pf_enable_irq0(hw);
5028         rte_intr_enable(&(dev->pci_dev->intr_handle));
5029 }
5030
5031 static int
5032 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5033                          struct i40e_macvlan_filter *filter,
5034                          int total)
5035 {
5036         int ele_num, ele_buff_size;
5037         int num, actual_num, i;
5038         uint16_t flags;
5039         int ret = I40E_SUCCESS;
5040         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5041         struct i40e_aqc_add_macvlan_element_data *req_list;
5042
5043         if (filter == NULL  || total == 0)
5044                 return I40E_ERR_PARAM;
5045         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5046         ele_buff_size = hw->aq.asq_buf_size;
5047
5048         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5049         if (req_list == NULL) {
5050                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5051                 return I40E_ERR_NO_MEMORY;
5052         }
5053
5054         num = 0;
5055         do {
5056                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5057                 memset(req_list, 0, ele_buff_size);
5058
5059                 for (i = 0; i < actual_num; i++) {
5060                         (void)rte_memcpy(req_list[i].mac_addr,
5061                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5062                         req_list[i].vlan_tag =
5063                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5064
5065                         switch (filter[num + i].filter_type) {
5066                         case RTE_MAC_PERFECT_MATCH:
5067                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5068                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5069                                 break;
5070                         case RTE_MACVLAN_PERFECT_MATCH:
5071                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5072                                 break;
5073                         case RTE_MAC_HASH_MATCH:
5074                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5075                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5076                                 break;
5077                         case RTE_MACVLAN_HASH_MATCH:
5078                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5079                                 break;
5080                         default:
5081                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5082                                 ret = I40E_ERR_PARAM;
5083                                 goto DONE;
5084                         }
5085
5086                         req_list[i].queue_number = 0;
5087
5088                         req_list[i].flags = rte_cpu_to_le_16(flags);
5089                 }
5090
5091                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5092                                                 actual_num, NULL);
5093                 if (ret != I40E_SUCCESS) {
5094                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5095                         goto DONE;
5096                 }
5097                 num += actual_num;
5098         } while (num < total);
5099
5100 DONE:
5101         rte_free(req_list);
5102         return ret;
5103 }
5104
5105 static int
5106 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5107                             struct i40e_macvlan_filter *filter,
5108                             int total)
5109 {
5110         int ele_num, ele_buff_size;
5111         int num, actual_num, i;
5112         uint16_t flags;
5113         int ret = I40E_SUCCESS;
5114         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5115         struct i40e_aqc_remove_macvlan_element_data *req_list;
5116
5117         if (filter == NULL  || total == 0)
5118                 return I40E_ERR_PARAM;
5119
5120         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5121         ele_buff_size = hw->aq.asq_buf_size;
5122
5123         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5124         if (req_list == NULL) {
5125                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5126                 return I40E_ERR_NO_MEMORY;
5127         }
5128
5129         num = 0;
5130         do {
5131                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5132                 memset(req_list, 0, ele_buff_size);
5133
5134                 for (i = 0; i < actual_num; i++) {
5135                         (void)rte_memcpy(req_list[i].mac_addr,
5136                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5137                         req_list[i].vlan_tag =
5138                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5139
5140                         switch (filter[num + i].filter_type) {
5141                         case RTE_MAC_PERFECT_MATCH:
5142                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5143                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5144                                 break;
5145                         case RTE_MACVLAN_PERFECT_MATCH:
5146                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5147                                 break;
5148                         case RTE_MAC_HASH_MATCH:
5149                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5150                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5151                                 break;
5152                         case RTE_MACVLAN_HASH_MATCH:
5153                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5154                                 break;
5155                         default:
5156                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5157                                 ret = I40E_ERR_PARAM;
5158                                 goto DONE;
5159                         }
5160                         req_list[i].flags = rte_cpu_to_le_16(flags);
5161                 }
5162
5163                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5164                                                 actual_num, NULL);
5165                 if (ret != I40E_SUCCESS) {
5166                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5167                         goto DONE;
5168                 }
5169                 num += actual_num;
5170         } while (num < total);
5171
5172 DONE:
5173         rte_free(req_list);
5174         return ret;
5175 }
5176
5177 /* Find out specific MAC filter */
5178 static struct i40e_mac_filter *
5179 i40e_find_mac_filter(struct i40e_vsi *vsi,
5180                          struct ether_addr *macaddr)
5181 {
5182         struct i40e_mac_filter *f;
5183
5184         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5185                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5186                         return f;
5187         }
5188
5189         return NULL;
5190 }
5191
5192 static bool
5193 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5194                          uint16_t vlan_id)
5195 {
5196         uint32_t vid_idx, vid_bit;
5197
5198         if (vlan_id > ETH_VLAN_ID_MAX)
5199                 return 0;
5200
5201         vid_idx = I40E_VFTA_IDX(vlan_id);
5202         vid_bit = I40E_VFTA_BIT(vlan_id);
5203
5204         if (vsi->vfta[vid_idx] & vid_bit)
5205                 return 1;
5206         else
5207                 return 0;
5208 }
5209
5210 static void
5211 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5212                          uint16_t vlan_id, bool on)
5213 {
5214         uint32_t vid_idx, vid_bit;
5215
5216         if (vlan_id > ETH_VLAN_ID_MAX)
5217                 return;
5218
5219         vid_idx = I40E_VFTA_IDX(vlan_id);
5220         vid_bit = I40E_VFTA_BIT(vlan_id);
5221
5222         if (on)
5223                 vsi->vfta[vid_idx] |= vid_bit;
5224         else
5225                 vsi->vfta[vid_idx] &= ~vid_bit;
5226 }
5227
5228 /**
5229  * Find all vlan options for specific mac addr,
5230  * return with actual vlan found.
5231  */
5232 static inline int
5233 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5234                            struct i40e_macvlan_filter *mv_f,
5235                            int num, struct ether_addr *addr)
5236 {
5237         int i;
5238         uint32_t j, k;
5239
5240         /**
5241          * Not to use i40e_find_vlan_filter to decrease the loop time,
5242          * although the code looks complex.
5243           */
5244         if (num < vsi->vlan_num)
5245                 return I40E_ERR_PARAM;
5246
5247         i = 0;
5248         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5249                 if (vsi->vfta[j]) {
5250                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5251                                 if (vsi->vfta[j] & (1 << k)) {
5252                                         if (i > num - 1) {
5253                                                 PMD_DRV_LOG(ERR, "vlan number "
5254                                                             "not match");
5255                                                 return I40E_ERR_PARAM;
5256                                         }
5257                                         (void)rte_memcpy(&mv_f[i].macaddr,
5258                                                         addr, ETH_ADDR_LEN);
5259                                         mv_f[i].vlan_id =
5260                                                 j * I40E_UINT32_BIT_SIZE + k;
5261                                         i++;
5262                                 }
5263                         }
5264                 }
5265         }
5266         return I40E_SUCCESS;
5267 }
5268
5269 static inline int
5270 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5271                            struct i40e_macvlan_filter *mv_f,
5272                            int num,
5273                            uint16_t vlan)
5274 {
5275         int i = 0;
5276         struct i40e_mac_filter *f;
5277
5278         if (num < vsi->mac_num)
5279                 return I40E_ERR_PARAM;
5280
5281         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5282                 if (i > num - 1) {
5283                         PMD_DRV_LOG(ERR, "buffer number not match");
5284                         return I40E_ERR_PARAM;
5285                 }
5286                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5287                                 ETH_ADDR_LEN);
5288                 mv_f[i].vlan_id = vlan;
5289                 mv_f[i].filter_type = f->mac_info.filter_type;
5290                 i++;
5291         }
5292
5293         return I40E_SUCCESS;
5294 }
5295
5296 static int
5297 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5298 {
5299         int i, num;
5300         struct i40e_mac_filter *f;
5301         struct i40e_macvlan_filter *mv_f;
5302         int ret = I40E_SUCCESS;
5303
5304         if (vsi == NULL || vsi->mac_num == 0)
5305                 return I40E_ERR_PARAM;
5306
5307         /* Case that no vlan is set */
5308         if (vsi->vlan_num == 0)
5309                 num = vsi->mac_num;
5310         else
5311                 num = vsi->mac_num * vsi->vlan_num;
5312
5313         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5314         if (mv_f == NULL) {
5315                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5316                 return I40E_ERR_NO_MEMORY;
5317         }
5318
5319         i = 0;
5320         if (vsi->vlan_num == 0) {
5321                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5322                         (void)rte_memcpy(&mv_f[i].macaddr,
5323                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5324                         mv_f[i].vlan_id = 0;
5325                         i++;
5326                 }
5327         } else {
5328                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5329                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5330                                         vsi->vlan_num, &f->mac_info.mac_addr);
5331                         if (ret != I40E_SUCCESS)
5332                                 goto DONE;
5333                         i += vsi->vlan_num;
5334                 }
5335         }
5336
5337         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5338 DONE:
5339         rte_free(mv_f);
5340
5341         return ret;
5342 }
5343
5344 int
5345 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5346 {
5347         struct i40e_macvlan_filter *mv_f;
5348         int mac_num;
5349         int ret = I40E_SUCCESS;
5350
5351         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5352                 return I40E_ERR_PARAM;
5353
5354         /* If it's already set, just return */
5355         if (i40e_find_vlan_filter(vsi,vlan))
5356                 return I40E_SUCCESS;
5357
5358         mac_num = vsi->mac_num;
5359
5360         if (mac_num == 0) {
5361                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5362                 return I40E_ERR_PARAM;
5363         }
5364
5365         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5366
5367         if (mv_f == NULL) {
5368                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5369                 return I40E_ERR_NO_MEMORY;
5370         }
5371
5372         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5373
5374         if (ret != I40E_SUCCESS)
5375                 goto DONE;
5376
5377         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5378
5379         if (ret != I40E_SUCCESS)
5380                 goto DONE;
5381
5382         i40e_set_vlan_filter(vsi, vlan, 1);
5383
5384         vsi->vlan_num++;
5385         ret = I40E_SUCCESS;
5386 DONE:
5387         rte_free(mv_f);
5388         return ret;
5389 }
5390
5391 int
5392 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5393 {
5394         struct i40e_macvlan_filter *mv_f;
5395         int mac_num;
5396         int ret = I40E_SUCCESS;
5397
5398         /**
5399          * Vlan 0 is the generic filter for untagged packets
5400          * and can't be removed.
5401          */
5402         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5403                 return I40E_ERR_PARAM;
5404
5405         /* If can't find it, just return */
5406         if (!i40e_find_vlan_filter(vsi, vlan))
5407                 return I40E_ERR_PARAM;
5408
5409         mac_num = vsi->mac_num;
5410
5411         if (mac_num == 0) {
5412                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5413                 return I40E_ERR_PARAM;
5414         }
5415
5416         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5417
5418         if (mv_f == NULL) {
5419                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5420                 return I40E_ERR_NO_MEMORY;
5421         }
5422
5423         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5424
5425         if (ret != I40E_SUCCESS)
5426                 goto DONE;
5427
5428         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5429
5430         if (ret != I40E_SUCCESS)
5431                 goto DONE;
5432
5433         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5434         if (vsi->vlan_num == 1) {
5435                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5436                 if (ret != I40E_SUCCESS)
5437                         goto DONE;
5438
5439                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5440                 if (ret != I40E_SUCCESS)
5441                         goto DONE;
5442         }
5443
5444         i40e_set_vlan_filter(vsi, vlan, 0);
5445
5446         vsi->vlan_num--;
5447         ret = I40E_SUCCESS;
5448 DONE:
5449         rte_free(mv_f);
5450         return ret;
5451 }
5452
5453 int
5454 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5455 {
5456         struct i40e_mac_filter *f;
5457         struct i40e_macvlan_filter *mv_f;
5458         int i, vlan_num = 0;
5459         int ret = I40E_SUCCESS;
5460
5461         /* If it's add and we've config it, return */
5462         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5463         if (f != NULL)
5464                 return I40E_SUCCESS;
5465         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5466                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5467
5468                 /**
5469                  * If vlan_num is 0, that's the first time to add mac,
5470                  * set mask for vlan_id 0.
5471                  */
5472                 if (vsi->vlan_num == 0) {
5473                         i40e_set_vlan_filter(vsi, 0, 1);
5474                         vsi->vlan_num = 1;
5475                 }
5476                 vlan_num = vsi->vlan_num;
5477         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5478                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5479                 vlan_num = 1;
5480
5481         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5482         if (mv_f == NULL) {
5483                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5484                 return I40E_ERR_NO_MEMORY;
5485         }
5486
5487         for (i = 0; i < vlan_num; i++) {
5488                 mv_f[i].filter_type = mac_filter->filter_type;
5489                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5490                                 ETH_ADDR_LEN);
5491         }
5492
5493         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5494                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5495                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5496                                         &mac_filter->mac_addr);
5497                 if (ret != I40E_SUCCESS)
5498                         goto DONE;
5499         }
5500
5501         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5502         if (ret != I40E_SUCCESS)
5503                 goto DONE;
5504
5505         /* Add the mac addr into mac list */
5506         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5507         if (f == NULL) {
5508                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5509                 ret = I40E_ERR_NO_MEMORY;
5510                 goto DONE;
5511         }
5512         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5513                         ETH_ADDR_LEN);
5514         f->mac_info.filter_type = mac_filter->filter_type;
5515         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5516         vsi->mac_num++;
5517
5518         ret = I40E_SUCCESS;
5519 DONE:
5520         rte_free(mv_f);
5521
5522         return ret;
5523 }
5524
5525 int
5526 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5527 {
5528         struct i40e_mac_filter *f;
5529         struct i40e_macvlan_filter *mv_f;
5530         int i, vlan_num;
5531         enum rte_mac_filter_type filter_type;
5532         int ret = I40E_SUCCESS;
5533
5534         /* Can't find it, return an error */
5535         f = i40e_find_mac_filter(vsi, addr);
5536         if (f == NULL)
5537                 return I40E_ERR_PARAM;
5538
5539         vlan_num = vsi->vlan_num;
5540         filter_type = f->mac_info.filter_type;
5541         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5542                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5543                 if (vlan_num == 0) {
5544                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5545                         return I40E_ERR_PARAM;
5546                 }
5547         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5548                         filter_type == RTE_MAC_HASH_MATCH)
5549                 vlan_num = 1;
5550
5551         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5552         if (mv_f == NULL) {
5553                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5554                 return I40E_ERR_NO_MEMORY;
5555         }
5556
5557         for (i = 0; i < vlan_num; i++) {
5558                 mv_f[i].filter_type = filter_type;
5559                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5560                                 ETH_ADDR_LEN);
5561         }
5562         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5563                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5564                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5565                 if (ret != I40E_SUCCESS)
5566                         goto DONE;
5567         }
5568
5569         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5570         if (ret != I40E_SUCCESS)
5571                 goto DONE;
5572
5573         /* Remove the mac addr into mac list */
5574         TAILQ_REMOVE(&vsi->mac_list, f, next);
5575         rte_free(f);
5576         vsi->mac_num--;
5577
5578         ret = I40E_SUCCESS;
5579 DONE:
5580         rte_free(mv_f);
5581         return ret;
5582 }
5583
5584 /* Configure hash enable flags for RSS */
5585 uint64_t
5586 i40e_config_hena(uint64_t flags)
5587 {
5588         uint64_t hena = 0;
5589
5590         if (!flags)
5591                 return hena;
5592
5593         if (flags & ETH_RSS_FRAG_IPV4)
5594                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5595         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5596                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5597         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5598                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5599         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5600                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5601         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5602                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5603         if (flags & ETH_RSS_FRAG_IPV6)
5604                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5605         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5606                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5607         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5608                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5609         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5610                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5611         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5612                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5613         if (flags & ETH_RSS_L2_PAYLOAD)
5614                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5615
5616         return hena;
5617 }
5618
5619 /* Parse the hash enable flags */
5620 uint64_t
5621 i40e_parse_hena(uint64_t flags)
5622 {
5623         uint64_t rss_hf = 0;
5624
5625         if (!flags)
5626                 return rss_hf;
5627         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5628                 rss_hf |= ETH_RSS_FRAG_IPV4;
5629         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5630                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5631         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5632                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5633         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5634                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5635         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5636                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5637         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5638                 rss_hf |= ETH_RSS_FRAG_IPV6;
5639         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5640                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5641         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5642                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5643         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5644                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5645         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5646                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5647         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5648                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5649
5650         return rss_hf;
5651 }
5652
5653 /* Disable RSS */
5654 static void
5655 i40e_pf_disable_rss(struct i40e_pf *pf)
5656 {
5657         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5658         uint64_t hena;
5659
5660         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5661         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5662         hena &= ~I40E_RSS_HENA_ALL;
5663         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5664         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5665         I40E_WRITE_FLUSH(hw);
5666 }
5667
5668 static int
5669 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5670 {
5671         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5672         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5673         int ret = 0;
5674
5675         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5676                 sizeof(uint32_t)))
5677                 return -EINVAL;
5678
5679         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5680                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5681                         (struct i40e_aqc_get_set_rss_key_data *)key;
5682
5683                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5684                 if (ret)
5685                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5686                                      "via AQ");
5687         } else {
5688                 uint32_t *hash_key = (uint32_t *)key;
5689                 uint16_t i;
5690
5691                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5692                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5693                 I40E_WRITE_FLUSH(hw);
5694         }
5695
5696         return ret;
5697 }
5698
5699 static int
5700 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5701 {
5702         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5703         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5704         int ret;
5705
5706         if (!key || !key_len)
5707                 return -EINVAL;
5708
5709         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5710                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5711                         (struct i40e_aqc_get_set_rss_key_data *)key);
5712                 if (ret) {
5713                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5714                         return ret;
5715                 }
5716         } else {
5717                 uint32_t *key_dw = (uint32_t *)key;
5718                 uint16_t i;
5719
5720                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5721                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5722         }
5723         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5724
5725         return 0;
5726 }
5727
5728 static int
5729 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5730 {
5731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5732         uint64_t rss_hf;
5733         uint64_t hena;
5734         int ret;
5735
5736         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5737                                rss_conf->rss_key_len);
5738         if (ret)
5739                 return ret;
5740
5741         rss_hf = rss_conf->rss_hf;
5742         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5743         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5744         hena &= ~I40E_RSS_HENA_ALL;
5745         hena |= i40e_config_hena(rss_hf);
5746         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5747         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5748         I40E_WRITE_FLUSH(hw);
5749
5750         return 0;
5751 }
5752
5753 static int
5754 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5755                          struct rte_eth_rss_conf *rss_conf)
5756 {
5757         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5759         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5760         uint64_t hena;
5761
5762         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5763         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5764         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5765                 if (rss_hf != 0) /* Enable RSS */
5766                         return -EINVAL;
5767                 return 0; /* Nothing to do */
5768         }
5769         /* RSS enabled */
5770         if (rss_hf == 0) /* Disable RSS */
5771                 return -EINVAL;
5772
5773         return i40e_hw_rss_hash_set(pf, rss_conf);
5774 }
5775
5776 static int
5777 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5778                            struct rte_eth_rss_conf *rss_conf)
5779 {
5780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5782         uint64_t hena;
5783
5784         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5785                          &rss_conf->rss_key_len);
5786
5787         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5788         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5789         rss_conf->rss_hf = i40e_parse_hena(hena);
5790
5791         return 0;
5792 }
5793
5794 static int
5795 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5796 {
5797         switch (filter_type) {
5798         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5799                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5800                 break;
5801         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5802                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5803                 break;
5804         case RTE_TUNNEL_FILTER_IMAC_TENID:
5805                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5806                 break;
5807         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5808                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5809                 break;
5810         case ETH_TUNNEL_FILTER_IMAC:
5811                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5812                 break;
5813         default:
5814                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5815                 return -EINVAL;
5816         }
5817
5818         return 0;
5819 }
5820
5821 static int
5822 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5823                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5824                         uint8_t add)
5825 {
5826         uint16_t ip_type;
5827         uint8_t tun_type = 0;
5828         int val, ret = 0;
5829         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5830         struct i40e_vsi *vsi = pf->main_vsi;
5831         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5832         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5833
5834         cld_filter = rte_zmalloc("tunnel_filter",
5835                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5836                 0);
5837
5838         if (NULL == cld_filter) {
5839                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5840                 return -EINVAL;
5841         }
5842         pfilter = cld_filter;
5843
5844         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5845                         sizeof(struct ether_addr));
5846         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5847                         sizeof(struct ether_addr));
5848
5849         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5850         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5851                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5852                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5853                                 &tunnel_filter->ip_addr,
5854                                 sizeof(pfilter->ipaddr.v4.data));
5855         } else {
5856                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5857                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5858                                 &tunnel_filter->ip_addr,
5859                                 sizeof(pfilter->ipaddr.v6.data));
5860         }
5861
5862         /* check tunneled type */
5863         switch (tunnel_filter->tunnel_type) {
5864         case RTE_TUNNEL_TYPE_VXLAN:
5865                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5866                 break;
5867         case RTE_TUNNEL_TYPE_NVGRE:
5868                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5869                 break;
5870         default:
5871                 /* Other tunnel types is not supported. */
5872                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5873                 rte_free(cld_filter);
5874                 return -EINVAL;
5875         }
5876
5877         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5878                                                 &pfilter->flags);
5879         if (val < 0) {
5880                 rte_free(cld_filter);
5881                 return -EINVAL;
5882         }
5883
5884         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5885                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5886         pfilter->tenant_id = tunnel_filter->tenant_id;
5887         pfilter->queue_number = tunnel_filter->queue_id;
5888
5889         if (add)
5890                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5891         else
5892                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5893                                                 cld_filter, 1);
5894
5895         rte_free(cld_filter);
5896         return ret;
5897 }
5898
5899 static int
5900 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5901 {
5902         uint8_t i;
5903
5904         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5905                 if (pf->vxlan_ports[i] == port)
5906                         return i;
5907         }
5908
5909         return -1;
5910 }
5911
5912 static int
5913 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5914 {
5915         int  idx, ret;
5916         uint8_t filter_idx;
5917         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5918
5919         idx = i40e_get_vxlan_port_idx(pf, port);
5920
5921         /* Check if port already exists */
5922         if (idx >= 0) {
5923                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5924                 return -EINVAL;
5925         }
5926
5927         /* Now check if there is space to add the new port */
5928         idx = i40e_get_vxlan_port_idx(pf, 0);
5929         if (idx < 0) {
5930                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5931                         "not adding port %d", port);
5932                 return -ENOSPC;
5933         }
5934
5935         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5936                                         &filter_idx, NULL);
5937         if (ret < 0) {
5938                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5939                 return -1;
5940         }
5941
5942         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5943                          port,  filter_idx);
5944
5945         /* New port: add it and mark its index in the bitmap */
5946         pf->vxlan_ports[idx] = port;
5947         pf->vxlan_bitmap |= (1 << idx);
5948
5949         if (!(pf->flags & I40E_FLAG_VXLAN))
5950                 pf->flags |= I40E_FLAG_VXLAN;
5951
5952         return 0;
5953 }
5954
5955 static int
5956 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5957 {
5958         int idx;
5959         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5960
5961         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5962                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5963                 return -EINVAL;
5964         }
5965
5966         idx = i40e_get_vxlan_port_idx(pf, port);
5967
5968         if (idx < 0) {
5969                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5970                 return -EINVAL;
5971         }
5972
5973         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5974                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5975                 return -1;
5976         }
5977
5978         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5979                         port, idx);
5980
5981         pf->vxlan_ports[idx] = 0;
5982         pf->vxlan_bitmap &= ~(1 << idx);
5983
5984         if (!pf->vxlan_bitmap)
5985                 pf->flags &= ~I40E_FLAG_VXLAN;
5986
5987         return 0;
5988 }
5989
5990 /* Add UDP tunneling port */
5991 static int
5992 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5993                         struct rte_eth_udp_tunnel *udp_tunnel)
5994 {
5995         int ret = 0;
5996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5997
5998         if (udp_tunnel == NULL)
5999                 return -EINVAL;
6000
6001         switch (udp_tunnel->prot_type) {
6002         case RTE_TUNNEL_TYPE_VXLAN:
6003                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6004                 break;
6005
6006         case RTE_TUNNEL_TYPE_GENEVE:
6007         case RTE_TUNNEL_TYPE_TEREDO:
6008                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6009                 ret = -1;
6010                 break;
6011
6012         default:
6013                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6014                 ret = -1;
6015                 break;
6016         }
6017
6018         return ret;
6019 }
6020
6021 /* Remove UDP tunneling port */
6022 static int
6023 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
6024                         struct rte_eth_udp_tunnel *udp_tunnel)
6025 {
6026         int ret = 0;
6027         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6028
6029         if (udp_tunnel == NULL)
6030                 return -EINVAL;
6031
6032         switch (udp_tunnel->prot_type) {
6033         case RTE_TUNNEL_TYPE_VXLAN:
6034                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6035                 break;
6036         case RTE_TUNNEL_TYPE_GENEVE:
6037         case RTE_TUNNEL_TYPE_TEREDO:
6038                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6039                 ret = -1;
6040                 break;
6041         default:
6042                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6043                 ret = -1;
6044                 break;
6045         }
6046
6047         return ret;
6048 }
6049
6050 /* Calculate the maximum number of contiguous PF queues that are configured */
6051 static int
6052 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6053 {
6054         struct rte_eth_dev_data *data = pf->dev_data;
6055         int i, num;
6056         struct i40e_rx_queue *rxq;
6057
6058         num = 0;
6059         for (i = 0; i < pf->lan_nb_qps; i++) {
6060                 rxq = data->rx_queues[i];
6061                 if (rxq && rxq->q_set)
6062                         num++;
6063                 else
6064                         break;
6065         }
6066
6067         return num;
6068 }
6069
6070 /* Configure RSS */
6071 static int
6072 i40e_pf_config_rss(struct i40e_pf *pf)
6073 {
6074         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6075         struct rte_eth_rss_conf rss_conf;
6076         uint32_t i, lut = 0;
6077         uint16_t j, num;
6078
6079         /*
6080          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6081          * It's necessary to calulate the actual PF queues that are configured.
6082          */
6083         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6084                 num = i40e_pf_calc_configured_queues_num(pf);
6085         else
6086                 num = pf->dev_data->nb_rx_queues;
6087
6088         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6089         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6090                         num);
6091
6092         if (num == 0) {
6093                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6094                 return -ENOTSUP;
6095         }
6096
6097         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6098                 if (j == num)
6099                         j = 0;
6100                 lut = (lut << 8) | (j & ((0x1 <<
6101                         hw->func_caps.rss_table_entry_width) - 1));
6102                 if ((i & 3) == 3)
6103                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6104         }
6105
6106         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6107         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6108                 i40e_pf_disable_rss(pf);
6109                 return 0;
6110         }
6111         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6112                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6113                 /* Random default keys */
6114                 static uint32_t rss_key_default[] = {0x6b793944,
6115                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6116                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6117                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6118
6119                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6120                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6121                                                         sizeof(uint32_t);
6122         }
6123
6124         return i40e_hw_rss_hash_set(pf, &rss_conf);
6125 }
6126
6127 static int
6128 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6129                                struct rte_eth_tunnel_filter_conf *filter)
6130 {
6131         if (pf == NULL || filter == NULL) {
6132                 PMD_DRV_LOG(ERR, "Invalid parameter");
6133                 return -EINVAL;
6134         }
6135
6136         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6137                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6138                 return -EINVAL;
6139         }
6140
6141         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6142                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6143                 return -EINVAL;
6144         }
6145
6146         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6147                 (is_zero_ether_addr(filter->outer_mac))) {
6148                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6149                 return -EINVAL;
6150         }
6151
6152         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6153                 (is_zero_ether_addr(filter->inner_mac))) {
6154                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6155                 return -EINVAL;
6156         }
6157
6158         return 0;
6159 }
6160
6161 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6162 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6163 static int
6164 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6165 {
6166         uint32_t val, reg;
6167         int ret = -EINVAL;
6168
6169         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6170         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6171
6172         if (len == 3) {
6173                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6174         } else if (len == 4) {
6175                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6176         } else {
6177                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6178                 return ret;
6179         }
6180
6181         if (reg != val) {
6182                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6183                                                    reg, NULL);
6184                 if (ret != 0)
6185                         return ret;
6186         } else {
6187                 ret = 0;
6188         }
6189         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6190                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6191
6192         return ret;
6193 }
6194
6195 static int
6196 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6197 {
6198         int ret = -EINVAL;
6199
6200         if (!hw || !cfg)
6201                 return -EINVAL;
6202
6203         switch (cfg->cfg_type) {
6204         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6205                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6206                 break;
6207         default:
6208                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6209                 break;
6210         }
6211
6212         return ret;
6213 }
6214
6215 static int
6216 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6217                                enum rte_filter_op filter_op,
6218                                void *arg)
6219 {
6220         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6221         int ret = I40E_ERR_PARAM;
6222
6223         switch (filter_op) {
6224         case RTE_ETH_FILTER_SET:
6225                 ret = i40e_dev_global_config_set(hw,
6226                         (struct rte_eth_global_cfg *)arg);
6227                 break;
6228         default:
6229                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6230                 break;
6231         }
6232
6233         return ret;
6234 }
6235
6236 static int
6237 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6238                           enum rte_filter_op filter_op,
6239                           void *arg)
6240 {
6241         struct rte_eth_tunnel_filter_conf *filter;
6242         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6243         int ret = I40E_SUCCESS;
6244
6245         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6246
6247         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6248                 return I40E_ERR_PARAM;
6249
6250         switch (filter_op) {
6251         case RTE_ETH_FILTER_NOP:
6252                 if (!(pf->flags & I40E_FLAG_VXLAN))
6253                         ret = I40E_NOT_SUPPORTED;
6254                 break;
6255         case RTE_ETH_FILTER_ADD:
6256                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6257                 break;
6258         case RTE_ETH_FILTER_DELETE:
6259                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6260                 break;
6261         default:
6262                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6263                 ret = I40E_ERR_PARAM;
6264                 break;
6265         }
6266
6267         return ret;
6268 }
6269
6270 static int
6271 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6272 {
6273         int ret = 0;
6274         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6275
6276         /* RSS setup */
6277         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6278                 ret = i40e_pf_config_rss(pf);
6279         else
6280                 i40e_pf_disable_rss(pf);
6281
6282         return ret;
6283 }
6284
6285 /* Get the symmetric hash enable configurations per port */
6286 static void
6287 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6288 {
6289         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6290
6291         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6292 }
6293
6294 /* Set the symmetric hash enable configurations per port */
6295 static void
6296 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6297 {
6298         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6299
6300         if (enable > 0) {
6301                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6302                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6303                                                         "been enabled");
6304                         return;
6305                 }
6306                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6307         } else {
6308                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6309                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6310                                                         "been disabled");
6311                         return;
6312                 }
6313                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6314         }
6315         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6316         I40E_WRITE_FLUSH(hw);
6317 }
6318
6319 /*
6320  * Get global configurations of hash function type and symmetric hash enable
6321  * per flow type (pctype). Note that global configuration means it affects all
6322  * the ports on the same NIC.
6323  */
6324 static int
6325 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6326                                    struct rte_eth_hash_global_conf *g_cfg)
6327 {
6328         uint32_t reg, mask = I40E_FLOW_TYPES;
6329         uint16_t i;
6330         enum i40e_filter_pctype pctype;
6331
6332         memset(g_cfg, 0, sizeof(*g_cfg));
6333         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6334         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6335                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6336         else
6337                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6338         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6339                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6340
6341         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6342                 if (!(mask & (1UL << i)))
6343                         continue;
6344                 mask &= ~(1UL << i);
6345                 /* Bit set indicats the coresponding flow type is supported */
6346                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6347                 pctype = i40e_flowtype_to_pctype(i);
6348                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6349                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6350                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6351         }
6352
6353         return 0;
6354 }
6355
6356 static int
6357 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6358 {
6359         uint32_t i;
6360         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6361
6362         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6363                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6364                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6365                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6366                                                 g_cfg->hash_func);
6367                 return -EINVAL;
6368         }
6369
6370         /*
6371          * As i40e supports less than 32 flow types, only first 32 bits need to
6372          * be checked.
6373          */
6374         mask0 = g_cfg->valid_bit_mask[0];
6375         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6376                 if (i == 0) {
6377                         /* Check if any unsupported flow type configured */
6378                         if ((mask0 | i40e_mask) ^ i40e_mask)
6379                                 goto mask_err;
6380                 } else {
6381                         if (g_cfg->valid_bit_mask[i])
6382                                 goto mask_err;
6383                 }
6384         }
6385
6386         return 0;
6387
6388 mask_err:
6389         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6390
6391         return -EINVAL;
6392 }
6393
6394 /*
6395  * Set global configurations of hash function type and symmetric hash enable
6396  * per flow type (pctype). Note any modifying global configuration will affect
6397  * all the ports on the same NIC.
6398  */
6399 static int
6400 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6401                                    struct rte_eth_hash_global_conf *g_cfg)
6402 {
6403         int ret;
6404         uint16_t i;
6405         uint32_t reg;
6406         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6407         enum i40e_filter_pctype pctype;
6408
6409         /* Check the input parameters */
6410         ret = i40e_hash_global_config_check(g_cfg);
6411         if (ret < 0)
6412                 return ret;
6413
6414         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6415                 if (!(mask0 & (1UL << i)))
6416                         continue;
6417                 mask0 &= ~(1UL << i);
6418                 pctype = i40e_flowtype_to_pctype(i);
6419                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6420                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6421                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6422         }
6423
6424         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6425         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6426                 /* Toeplitz */
6427                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6428                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6429                                                                 "Toeplitz");
6430                         goto out;
6431                 }
6432                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6433         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6434                 /* Simple XOR */
6435                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6436                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6437                                                         "Simple XOR");
6438                         goto out;
6439                 }
6440                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6441         } else
6442                 /* Use the default, and keep it as it is */
6443                 goto out;
6444
6445         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6446
6447 out:
6448         I40E_WRITE_FLUSH(hw);
6449
6450         return 0;
6451 }
6452
6453 /**
6454  * Valid input sets for hash and flow director filters per PCTYPE
6455  */
6456 static uint64_t
6457 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6458                 enum rte_filter_type filter)
6459 {
6460         uint64_t valid;
6461
6462         static const uint64_t valid_hash_inset_table[] = {
6463                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6464                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6465                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6466                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6467                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6468                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6469                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6470                         I40E_INSET_FLEX_PAYLOAD,
6471                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6472                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6473                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6474                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6475                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6476                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6477                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6478                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6479                         I40E_INSET_FLEX_PAYLOAD,
6480                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6481                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6482                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6483                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6484                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6485                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6486                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6487                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6488                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6489                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6490                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6491                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6492                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6493                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6494                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6495                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6496                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6497                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6498                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6499                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6500                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6501                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6502                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6503                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6504                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6505                         I40E_INSET_FLEX_PAYLOAD,
6506                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6507                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6508                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6509                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6510                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6511                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6512                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6513                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6514                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6515                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6516                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6517                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6518                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6519                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6520                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6521                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6522                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6523                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6524                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6525                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6526                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6527                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6528                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6529                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6530                         I40E_INSET_FLEX_PAYLOAD,
6531                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6532                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6533                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6534                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6535                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6536                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6537                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6538                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6539                         I40E_INSET_FLEX_PAYLOAD,
6540                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6541                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6542                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6543                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6544                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6545                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6546                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6547                         I40E_INSET_FLEX_PAYLOAD,
6548                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6549                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6550                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6551                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6552                         I40E_INSET_FLEX_PAYLOAD,
6553         };
6554
6555         /**
6556          * Flow director supports only fields defined in
6557          * union rte_eth_fdir_flow.
6558          */
6559         static const uint64_t valid_fdir_inset_table[] = {
6560                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6561                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6562                 I40E_INSET_FLEX_PAYLOAD,
6563                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6564                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6565                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6566                 I40E_INSET_FLEX_PAYLOAD,
6567                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6568                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6569                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6570                 I40E_INSET_FLEX_PAYLOAD,
6571                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6572                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6573                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6574                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6575                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6576                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6577                 I40E_INSET_FLEX_PAYLOAD,
6578                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6579                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6580                 I40E_INSET_FLEX_PAYLOAD,
6581                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6582                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6583                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6584                 I40E_INSET_FLEX_PAYLOAD,
6585                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6586                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6587                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6588                 I40E_INSET_FLEX_PAYLOAD,
6589                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6590                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6591                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6592                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6593                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6594                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6595                 I40E_INSET_FLEX_PAYLOAD,
6596                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6597                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6598         };
6599
6600         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6601                 return 0;
6602         if (filter == RTE_ETH_FILTER_HASH)
6603                 valid = valid_hash_inset_table[pctype];
6604         else
6605                 valid = valid_fdir_inset_table[pctype];
6606
6607         return valid;
6608 }
6609
6610 /**
6611  * Validate if the input set is allowed for a specific PCTYPE
6612  */
6613 static int
6614 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6615                 enum rte_filter_type filter, uint64_t inset)
6616 {
6617         uint64_t valid;
6618
6619         valid = i40e_get_valid_input_set(pctype, filter);
6620         if (inset & (~valid))
6621                 return -EINVAL;
6622
6623         return 0;
6624 }
6625
6626 /* default input set fields combination per pctype */
6627 static uint64_t
6628 i40e_get_default_input_set(uint16_t pctype)
6629 {
6630         static const uint64_t default_inset_table[] = {
6631                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6632                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6633                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6634                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6635                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6636                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6637                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6638                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6639                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6640                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6641                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6642                         I40E_INSET_SCTP_VT,
6643                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6644                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6645                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6646                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6647                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6648                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6649                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6650                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6651                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6652                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6653                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6654                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6655                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6656                         I40E_INSET_SCTP_VT,
6657                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6658                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6659                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6660                         I40E_INSET_LAST_ETHER_TYPE,
6661         };
6662
6663         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6664                 return 0;
6665
6666         return default_inset_table[pctype];
6667 }
6668
6669 /**
6670  * Parse the input set from index to logical bit masks
6671  */
6672 static int
6673 i40e_parse_input_set(uint64_t *inset,
6674                      enum i40e_filter_pctype pctype,
6675                      enum rte_eth_input_set_field *field,
6676                      uint16_t size)
6677 {
6678         uint16_t i, j;
6679         int ret = -EINVAL;
6680
6681         static const struct {
6682                 enum rte_eth_input_set_field field;
6683                 uint64_t inset;
6684         } inset_convert_table[] = {
6685                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6686                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6687                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6688                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6689                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6690                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6691                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6692                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6693                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6694                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6695                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6696                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6697                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6698                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6699                         I40E_INSET_IPV6_NEXT_HDR},
6700                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6701                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6702                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6703                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6704                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6705                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6706                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6707                         I40E_INSET_SCTP_VT},
6708                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6709                         I40E_INSET_TUNNEL_DMAC},
6710                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6711                         I40E_INSET_VLAN_TUNNEL},
6712                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6713                         I40E_INSET_TUNNEL_ID},
6714                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6715                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6716                         I40E_INSET_FLEX_PAYLOAD_W1},
6717                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6718                         I40E_INSET_FLEX_PAYLOAD_W2},
6719                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6720                         I40E_INSET_FLEX_PAYLOAD_W3},
6721                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6722                         I40E_INSET_FLEX_PAYLOAD_W4},
6723                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6724                         I40E_INSET_FLEX_PAYLOAD_W5},
6725                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6726                         I40E_INSET_FLEX_PAYLOAD_W6},
6727                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6728                         I40E_INSET_FLEX_PAYLOAD_W7},
6729                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6730                         I40E_INSET_FLEX_PAYLOAD_W8},
6731         };
6732
6733         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6734                 return ret;
6735
6736         /* Only one item allowed for default or all */
6737         if (size == 1) {
6738                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6739                         *inset = i40e_get_default_input_set(pctype);
6740                         return 0;
6741                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6742                         *inset = I40E_INSET_NONE;
6743                         return 0;
6744                 }
6745         }
6746
6747         for (i = 0, *inset = 0; i < size; i++) {
6748                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6749                         if (field[i] == inset_convert_table[j].field) {
6750                                 *inset |= inset_convert_table[j].inset;
6751                                 break;
6752                         }
6753                 }
6754
6755                 /* It contains unsupported input set, return immediately */
6756                 if (j == RTE_DIM(inset_convert_table))
6757                         return ret;
6758         }
6759
6760         return 0;
6761 }
6762
6763 /**
6764  * Translate the input set from bit masks to register aware bit masks
6765  * and vice versa
6766  */
6767 static uint64_t
6768 i40e_translate_input_set_reg(uint64_t input)
6769 {
6770         uint64_t val = 0;
6771         uint16_t i;
6772
6773         static const struct {
6774                 uint64_t inset;
6775                 uint64_t inset_reg;
6776         } inset_map[] = {
6777                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6778                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6779                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6780                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6781                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6782                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6783                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6784                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6785                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6786                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6787                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6788                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6789                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6790                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6791                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6792                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6793                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6794                 {I40E_INSET_TUNNEL_DMAC,
6795                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6796                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6797                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6798                 {I40E_INSET_TUNNEL_SRC_PORT,
6799                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6800                 {I40E_INSET_TUNNEL_DST_PORT,
6801                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6802                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6803                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6804                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6805                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6806                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6807                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6808                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6809                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6810                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6811         };
6812
6813         if (input == 0)
6814                 return val;
6815
6816         /* Translate input set to register aware inset */
6817         for (i = 0; i < RTE_DIM(inset_map); i++) {
6818                 if (input & inset_map[i].inset)
6819                         val |= inset_map[i].inset_reg;
6820         }
6821
6822         return val;
6823 }
6824
6825 static uint8_t
6826 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6827 {
6828         uint8_t i, idx = 0;
6829
6830         static const struct {
6831                 uint64_t inset;
6832                 uint32_t mask;
6833         } inset_mask_map[] = {
6834                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6835                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6836                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6837                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6838         };
6839
6840         if (!inset || !mask || !nb_elem)
6841                 return 0;
6842
6843         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6844                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6845                         mask[i] = 0;
6846                 return I40E_INSET_MASK_NUM_REG;
6847         }
6848
6849         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6850                 if (idx >= nb_elem)
6851                         break;
6852                 if (inset & inset_mask_map[i].inset) {
6853                         mask[idx] = inset_mask_map[i].mask;
6854                         idx++;
6855                 }
6856         }
6857
6858         return idx;
6859 }
6860
6861 static uint64_t
6862 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6863                             enum i40e_filter_pctype pctype)
6864 {
6865         uint64_t reg = 0;
6866
6867         if (filter == RTE_ETH_FILTER_HASH) {
6868                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6869                 reg <<= I40E_32_BIT_WIDTH;
6870                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6871         } else if (filter == RTE_ETH_FILTER_FDIR) {
6872                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6873                 reg <<= I40E_32_BIT_WIDTH;
6874                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6875         }
6876
6877         return reg;
6878 }
6879
6880 static void
6881 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6882 {
6883         uint32_t reg = I40E_READ_REG(hw, addr);
6884
6885         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6886         if (reg != val)
6887                 I40E_WRITE_REG(hw, addr, val);
6888         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6889                     (uint32_t)I40E_READ_REG(hw, addr));
6890 }
6891
6892 static int
6893 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6894                          enum i40e_filter_pctype pctype,
6895                          enum rte_filter_input_set_op op,
6896                          uint32_t *mask_reg,
6897                          uint8_t num)
6898 {
6899         uint32_t reg;
6900         uint8_t i;
6901
6902         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6903                 return -EINVAL;
6904
6905         if (op == RTE_ETH_INPUT_SET_SELECT) {
6906                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6907                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6908                                              0);
6909                         if (i >= num)
6910                                 continue;
6911                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6912                                              mask_reg[i]);
6913                 }
6914         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6915                 uint8_t j, count = 0;
6916
6917                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6918                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6919                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6920                                 count++;
6921                 }
6922                 if (count + num > I40E_INSET_MASK_NUM_REG)
6923                         return -EINVAL;
6924
6925                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6926                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6927                                              mask_reg[j]);
6928         }
6929
6930         return 0;
6931 }
6932
6933 static int
6934 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6935                        enum i40e_filter_pctype pctype,
6936                        enum rte_filter_input_set_op op,
6937                        uint32_t *mask_reg,
6938                        uint8_t num)
6939 {
6940         uint32_t reg;
6941         uint8_t i;
6942
6943         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6944                 return -EINVAL;
6945
6946         if (op == RTE_ETH_INPUT_SET_SELECT) {
6947                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6948                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6949                                              0);
6950                         if (i >= num)
6951                                 continue;
6952                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6953                                              mask_reg[i]);
6954                 }
6955         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6956                 uint8_t j, count = 0;
6957
6958                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6959                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6960                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6961                                 count++;
6962                 }
6963                 if (count + num > I40E_INSET_MASK_NUM_REG)
6964                         return -EINVAL;
6965
6966                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6967                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6968                                              mask_reg[j]);
6969         }
6970
6971         return 0;
6972 }
6973
6974 int
6975 i40e_filter_inset_select(struct i40e_hw *hw,
6976                          struct rte_eth_input_set_conf *conf,
6977                          enum rte_filter_type filter)
6978 {
6979         enum i40e_filter_pctype pctype;
6980         uint64_t inset_reg = 0, input_set;
6981         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6982         uint8_t num;
6983         int ret;
6984
6985         if (!hw || !conf) {
6986                 PMD_DRV_LOG(ERR, "Invalid pointer");
6987                 return -EFAULT;
6988         }
6989
6990         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6991         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6992                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6993                             conf->flow_type);
6994                 return -EINVAL;
6995         }
6996         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6997                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6998                 return -EINVAL;
6999         }
7000
7001         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7002                                    conf->inset_size);
7003         if (ret) {
7004                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7005                 return -EINVAL;
7006         }
7007         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
7008                 PMD_DRV_LOG(ERR, "Invalid input set");
7009                 return -EINVAL;
7010         }
7011
7012         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7013                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7014         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7015                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7016                 return -EINVAL;
7017         }
7018         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7019                                            I40E_INSET_MASK_NUM_REG);
7020         inset_reg |= i40e_translate_input_set_reg(input_set);
7021
7022         if (filter == RTE_ETH_FILTER_HASH) {
7023                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7024                                                num);
7025                 if (ret)
7026                         return -EINVAL;
7027
7028                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7029                                       (uint32_t)(inset_reg & UINT32_MAX));
7030                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7031                                      (uint32_t)((inset_reg >>
7032                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7033         } else if (filter == RTE_ETH_FILTER_FDIR) {
7034                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7035                                              num);
7036                 if (ret)
7037                         return -EINVAL;
7038
7039                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7040                                       (uint32_t)(inset_reg & UINT32_MAX));
7041                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7042                                      (uint32_t)((inset_reg >>
7043                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7044         } else {
7045                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7046                 return -EINVAL;
7047         }
7048         I40E_WRITE_FLUSH(hw);
7049
7050         return 0;
7051 }
7052
7053 static int
7054 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7055 {
7056         int ret = 0;
7057
7058         if (!hw || !info) {
7059                 PMD_DRV_LOG(ERR, "Invalid pointer");
7060                 return -EFAULT;
7061         }
7062
7063         switch (info->info_type) {
7064         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7065                 i40e_get_symmetric_hash_enable_per_port(hw,
7066                                         &(info->info.enable));
7067                 break;
7068         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7069                 ret = i40e_get_hash_filter_global_config(hw,
7070                                 &(info->info.global_conf));
7071                 break;
7072         default:
7073                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7074                                                         info->info_type);
7075                 ret = -EINVAL;
7076                 break;
7077         }
7078
7079         return ret;
7080 }
7081
7082 static int
7083 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7084 {
7085         int ret = 0;
7086
7087         if (!hw || !info) {
7088                 PMD_DRV_LOG(ERR, "Invalid pointer");
7089                 return -EFAULT;
7090         }
7091
7092         switch (info->info_type) {
7093         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7094                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7095                 break;
7096         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7097                 ret = i40e_set_hash_filter_global_config(hw,
7098                                 &(info->info.global_conf));
7099                 break;
7100         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7101                 ret = i40e_filter_inset_select(hw,
7102                                                &(info->info.input_set_conf),
7103                                                RTE_ETH_FILTER_HASH);
7104                 break;
7105
7106         default:
7107                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7108                                                         info->info_type);
7109                 ret = -EINVAL;
7110                 break;
7111         }
7112
7113         return ret;
7114 }
7115
7116 /* Operations for hash function */
7117 static int
7118 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7119                       enum rte_filter_op filter_op,
7120                       void *arg)
7121 {
7122         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7123         int ret = 0;
7124
7125         switch (filter_op) {
7126         case RTE_ETH_FILTER_NOP:
7127                 break;
7128         case RTE_ETH_FILTER_GET:
7129                 ret = i40e_hash_filter_get(hw,
7130                         (struct rte_eth_hash_filter_info *)arg);
7131                 break;
7132         case RTE_ETH_FILTER_SET:
7133                 ret = i40e_hash_filter_set(hw,
7134                         (struct rte_eth_hash_filter_info *)arg);
7135                 break;
7136         default:
7137                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7138                                                                 filter_op);
7139                 ret = -ENOTSUP;
7140                 break;
7141         }
7142
7143         return ret;
7144 }
7145
7146 /*
7147  * Configure ethertype filter, which can director packet by filtering
7148  * with mac address and ether_type or only ether_type
7149  */
7150 static int
7151 i40e_ethertype_filter_set(struct i40e_pf *pf,
7152                         struct rte_eth_ethertype_filter *filter,
7153                         bool add)
7154 {
7155         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7156         struct i40e_control_filter_stats stats;
7157         uint16_t flags = 0;
7158         int ret;
7159
7160         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7161                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7162                 return -EINVAL;
7163         }
7164         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7165                 filter->ether_type == ETHER_TYPE_IPv6) {
7166                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7167                         " control packet filter.", filter->ether_type);
7168                 return -EINVAL;
7169         }
7170         if (filter->ether_type == ETHER_TYPE_VLAN)
7171                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7172                         " not supported.");
7173
7174         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7175                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7176         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7177                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7178         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7179
7180         memset(&stats, 0, sizeof(stats));
7181         ret = i40e_aq_add_rem_control_packet_filter(hw,
7182                         filter->mac_addr.addr_bytes,
7183                         filter->ether_type, flags,
7184                         pf->main_vsi->seid,
7185                         filter->queue, add, &stats, NULL);
7186
7187         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7188                          " mac_etype_used = %u, etype_used = %u,"
7189                          " mac_etype_free = %u, etype_free = %u\n",
7190                          ret, stats.mac_etype_used, stats.etype_used,
7191                          stats.mac_etype_free, stats.etype_free);
7192         if (ret < 0)
7193                 return -ENOSYS;
7194         return 0;
7195 }
7196
7197 /*
7198  * Handle operations for ethertype filter.
7199  */
7200 static int
7201 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7202                                 enum rte_filter_op filter_op,
7203                                 void *arg)
7204 {
7205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7206         int ret = 0;
7207
7208         if (filter_op == RTE_ETH_FILTER_NOP)
7209                 return ret;
7210
7211         if (arg == NULL) {
7212                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7213                             filter_op);
7214                 return -EINVAL;
7215         }
7216
7217         switch (filter_op) {
7218         case RTE_ETH_FILTER_ADD:
7219                 ret = i40e_ethertype_filter_set(pf,
7220                         (struct rte_eth_ethertype_filter *)arg,
7221                         TRUE);
7222                 break;
7223         case RTE_ETH_FILTER_DELETE:
7224                 ret = i40e_ethertype_filter_set(pf,
7225                         (struct rte_eth_ethertype_filter *)arg,
7226                         FALSE);
7227                 break;
7228         default:
7229                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7230                 ret = -ENOSYS;
7231                 break;
7232         }
7233         return ret;
7234 }
7235
7236 static int
7237 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7238                      enum rte_filter_type filter_type,
7239                      enum rte_filter_op filter_op,
7240                      void *arg)
7241 {
7242         int ret = 0;
7243
7244         if (dev == NULL)
7245                 return -EINVAL;
7246
7247         switch (filter_type) {
7248         case RTE_ETH_FILTER_NONE:
7249                 /* For global configuration */
7250                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7251                 break;
7252         case RTE_ETH_FILTER_HASH:
7253                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7254                 break;
7255         case RTE_ETH_FILTER_MACVLAN:
7256                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7257                 break;
7258         case RTE_ETH_FILTER_ETHERTYPE:
7259                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7260                 break;
7261         case RTE_ETH_FILTER_TUNNEL:
7262                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7263                 break;
7264         case RTE_ETH_FILTER_FDIR:
7265                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7266                 break;
7267         default:
7268                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7269                                                         filter_type);
7270                 ret = -EINVAL;
7271                 break;
7272         }
7273
7274         return ret;
7275 }
7276
7277 /*
7278  * As some registers wouldn't be reset unless a global hardware reset,
7279  * hardware initialization is needed to put those registers into an
7280  * expected initial state.
7281  */
7282 static void
7283 i40e_hw_init(struct i40e_hw *hw)
7284 {
7285         /* clear the PF Queue Filter control register */
7286         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7287
7288         /* Disable symmetric hash per port */
7289         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7290 }
7291
7292 enum i40e_filter_pctype
7293 i40e_flowtype_to_pctype(uint16_t flow_type)
7294 {
7295         static const enum i40e_filter_pctype pctype_table[] = {
7296                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7297                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7298                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7299                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7300                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7301                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7302                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7303                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7304                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7305                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7306                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7307                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7308                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7309                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7310                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7311                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7312                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7313                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7314                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7315         };
7316
7317         return pctype_table[flow_type];
7318 }
7319
7320 uint16_t
7321 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7322 {
7323         static const uint16_t flowtype_table[] = {
7324                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7325                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7326                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7327                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7328                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7329                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7330                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7331                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7332                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7333                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7334                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7335                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7336                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7337                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7338                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7339                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7340                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7341                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7342                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7343         };
7344
7345         return flowtype_table[pctype];
7346 }
7347
7348 /*
7349  * On X710, performance number is far from the expectation on recent firmware
7350  * versions; on XL710, performance number is also far from the expectation on
7351  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7352  * mode is enabled and port MAC address is equal to the packet destination MAC
7353  * address. The fix for this issue may not be integrated in the following
7354  * firmware version. So the workaround in software driver is needed. It needs
7355  * to modify the initial values of 3 internal only registers for both X710 and
7356  * XL710. Note that the values for X710 or XL710 could be different, and the
7357  * workaround can be removed when it is fixed in firmware in the future.
7358  */
7359
7360 /* For both X710 and XL710 */
7361 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7362 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7363
7364 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7365 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7366
7367 /* For X710 */
7368 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7369 /* For XL710 */
7370 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7371 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7372
7373 static void
7374 i40e_configure_registers(struct i40e_hw *hw)
7375 {
7376         static struct {
7377                 uint32_t addr;
7378                 uint64_t val;
7379         } reg_table[] = {
7380                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7381                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7382                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7383         };
7384         uint64_t reg;
7385         uint32_t i;
7386         int ret;
7387
7388         for (i = 0; i < RTE_DIM(reg_table); i++) {
7389                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7390                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7391                                 reg_table[i].val =
7392                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7393                         else /* For X710 */
7394                                 reg_table[i].val =
7395                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7396                 }
7397
7398                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7399                                                         &reg, NULL);
7400                 if (ret < 0) {
7401                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7402                                                         reg_table[i].addr);
7403                         break;
7404                 }
7405                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7406                                                 reg_table[i].addr, reg);
7407                 if (reg == reg_table[i].val)
7408                         continue;
7409
7410                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7411                                                 reg_table[i].val, NULL);
7412                 if (ret < 0) {
7413                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7414                                 "address of 0x%"PRIx32, reg_table[i].val,
7415                                                         reg_table[i].addr);
7416                         break;
7417                 }
7418                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7419                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7420         }
7421 }
7422
7423 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7424 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7425 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7426 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7427 static int
7428 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7429 {
7430         uint32_t reg;
7431         int ret;
7432
7433         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7434                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7435                 return -EINVAL;
7436         }
7437
7438         /* Configure for double VLAN RX stripping */
7439         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7440         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7441                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7442                 ret = i40e_aq_debug_write_register(hw,
7443                                                    I40E_VSI_TSR(vsi->vsi_id),
7444                                                    reg, NULL);
7445                 if (ret < 0) {
7446                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7447                                     vsi->vsi_id);
7448                         return I40E_ERR_CONFIG;
7449                 }
7450         }
7451
7452         /* Configure for double VLAN TX insertion */
7453         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7454         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7455                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7456                 ret = i40e_aq_debug_write_register(hw,
7457                                                    I40E_VSI_L2TAGSTXVALID(
7458                                                    vsi->vsi_id), reg, NULL);
7459                 if (ret < 0) {
7460                         PMD_DRV_LOG(ERR, "Failed to update "
7461                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7462                         return I40E_ERR_CONFIG;
7463                 }
7464         }
7465
7466         return 0;
7467 }
7468
7469 /**
7470  * i40e_aq_add_mirror_rule
7471  * @hw: pointer to the hardware structure
7472  * @seid: VEB seid to add mirror rule to
7473  * @dst_id: destination vsi seid
7474  * @entries: Buffer which contains the entities to be mirrored
7475  * @count: number of entities contained in the buffer
7476  * @rule_id:the rule_id of the rule to be added
7477  *
7478  * Add a mirror rule for a given veb.
7479  *
7480  **/
7481 static enum i40e_status_code
7482 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7483                         uint16_t seid, uint16_t dst_id,
7484                         uint16_t rule_type, uint16_t *entries,
7485                         uint16_t count, uint16_t *rule_id)
7486 {
7487         struct i40e_aq_desc desc;
7488         struct i40e_aqc_add_delete_mirror_rule cmd;
7489         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7490                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7491                 &desc.params.raw;
7492         uint16_t buff_len;
7493         enum i40e_status_code status;
7494
7495         i40e_fill_default_direct_cmd_desc(&desc,
7496                                           i40e_aqc_opc_add_mirror_rule);
7497         memset(&cmd, 0, sizeof(cmd));
7498
7499         buff_len = sizeof(uint16_t) * count;
7500         desc.datalen = rte_cpu_to_le_16(buff_len);
7501         if (buff_len > 0)
7502                 desc.flags |= rte_cpu_to_le_16(
7503                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7504         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7505                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7506         cmd.num_entries = rte_cpu_to_le_16(count);
7507         cmd.seid = rte_cpu_to_le_16(seid);
7508         cmd.destination = rte_cpu_to_le_16(dst_id);
7509
7510         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7511         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7512         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7513                          "rule_id = %u"
7514                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7515                          hw->aq.asq_last_status, resp->rule_id,
7516                          resp->mirror_rules_used, resp->mirror_rules_free);
7517         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7518
7519         return status;
7520 }
7521
7522 /**
7523  * i40e_aq_del_mirror_rule
7524  * @hw: pointer to the hardware structure
7525  * @seid: VEB seid to add mirror rule to
7526  * @entries: Buffer which contains the entities to be mirrored
7527  * @count: number of entities contained in the buffer
7528  * @rule_id:the rule_id of the rule to be delete
7529  *
7530  * Delete a mirror rule for a given veb.
7531  *
7532  **/
7533 static enum i40e_status_code
7534 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7535                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7536                 uint16_t count, uint16_t rule_id)
7537 {
7538         struct i40e_aq_desc desc;
7539         struct i40e_aqc_add_delete_mirror_rule cmd;
7540         uint16_t buff_len = 0;
7541         enum i40e_status_code status;
7542         void *buff = NULL;
7543
7544         i40e_fill_default_direct_cmd_desc(&desc,
7545                                           i40e_aqc_opc_delete_mirror_rule);
7546         memset(&cmd, 0, sizeof(cmd));
7547         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7548                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7549                                                           I40E_AQ_FLAG_RD));
7550                 cmd.num_entries = count;
7551                 buff_len = sizeof(uint16_t) * count;
7552                 desc.datalen = rte_cpu_to_le_16(buff_len);
7553                 buff = (void *)entries;
7554         } else
7555                 /* rule id is filled in destination field for deleting mirror rule */
7556                 cmd.destination = rte_cpu_to_le_16(rule_id);
7557
7558         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7559                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7560         cmd.seid = rte_cpu_to_le_16(seid);
7561
7562         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7563         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7564
7565         return status;
7566 }
7567
7568 /**
7569  * i40e_mirror_rule_set
7570  * @dev: pointer to the hardware structure
7571  * @mirror_conf: mirror rule info
7572  * @sw_id: mirror rule's sw_id
7573  * @on: enable/disable
7574  *
7575  * set a mirror rule.
7576  *
7577  **/
7578 static int
7579 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7580                         struct rte_eth_mirror_conf *mirror_conf,
7581                         uint8_t sw_id, uint8_t on)
7582 {
7583         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7585         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7586         struct i40e_mirror_rule *parent = NULL;
7587         uint16_t seid, dst_seid, rule_id;
7588         uint16_t i, j = 0;
7589         int ret;
7590
7591         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7592
7593         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7594                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7595                         " without veb or vfs.");
7596                 return -ENOSYS;
7597         }
7598         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7599                 PMD_DRV_LOG(ERR, "mirror table is full.");
7600                 return -ENOSPC;
7601         }
7602         if (mirror_conf->dst_pool > pf->vf_num) {
7603                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7604                                  mirror_conf->dst_pool);
7605                 return -EINVAL;
7606         }
7607
7608         seid = pf->main_vsi->veb->seid;
7609
7610         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7611                 if (sw_id <= it->index) {
7612                         mirr_rule = it;
7613                         break;
7614                 }
7615                 parent = it;
7616         }
7617         if (mirr_rule && sw_id == mirr_rule->index) {
7618                 if (on) {
7619                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7620                         return -EEXIST;
7621                 } else {
7622                         ret = i40e_aq_del_mirror_rule(hw, seid,
7623                                         mirr_rule->rule_type,
7624                                         mirr_rule->entries,
7625                                         mirr_rule->num_entries, mirr_rule->id);
7626                         if (ret < 0) {
7627                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7628                                                    " ret = %d, aq_err = %d.",
7629                                                    ret, hw->aq.asq_last_status);
7630                                 return -ENOSYS;
7631                         }
7632                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7633                         rte_free(mirr_rule);
7634                         pf->nb_mirror_rule--;
7635                         return 0;
7636                 }
7637         } else if (!on) {
7638                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7639                 return -ENOENT;
7640         }
7641
7642         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7643                                 sizeof(struct i40e_mirror_rule) , 0);
7644         if (!mirr_rule) {
7645                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7646                 return I40E_ERR_NO_MEMORY;
7647         }
7648         switch (mirror_conf->rule_type) {
7649         case ETH_MIRROR_VLAN:
7650                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7651                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7652                                 mirr_rule->entries[j] =
7653                                         mirror_conf->vlan.vlan_id[i];
7654                                 j++;
7655                         }
7656                 }
7657                 if (j == 0) {
7658                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7659                         rte_free(mirr_rule);
7660                         return -EINVAL;
7661                 }
7662                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7663                 break;
7664         case ETH_MIRROR_VIRTUAL_POOL_UP:
7665         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7666                 /* check if the specified pool bit is out of range */
7667                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7668                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7669                         rte_free(mirr_rule);
7670                         return -EINVAL;
7671                 }
7672                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7673                         if (mirror_conf->pool_mask & (1ULL << i)) {
7674                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7675                                 j++;
7676                         }
7677                 }
7678                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7679                         /* add pf vsi to entries */
7680                         mirr_rule->entries[j] = pf->main_vsi_seid;
7681                         j++;
7682                 }
7683                 if (j == 0) {
7684                         PMD_DRV_LOG(ERR, "pool is not specified.");
7685                         rte_free(mirr_rule);
7686                         return -EINVAL;
7687                 }
7688                 /* egress and ingress in aq commands means from switch but not port */
7689                 mirr_rule->rule_type =
7690                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7691                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7692                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7693                 break;
7694         case ETH_MIRROR_UPLINK_PORT:
7695                 /* egress and ingress in aq commands means from switch but not port*/
7696                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7697                 break;
7698         case ETH_MIRROR_DOWNLINK_PORT:
7699                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7700                 break;
7701         default:
7702                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7703                         mirror_conf->rule_type);
7704                 rte_free(mirr_rule);
7705                 return -EINVAL;
7706         }
7707
7708         /* If the dst_pool is equal to vf_num, consider it as PF */
7709         if (mirror_conf->dst_pool == pf->vf_num)
7710                 dst_seid = pf->main_vsi_seid;
7711         else
7712                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7713
7714         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7715                                       mirr_rule->rule_type, mirr_rule->entries,
7716                                       j, &rule_id);
7717         if (ret < 0) {
7718                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7719                                    " ret = %d, aq_err = %d.",
7720                                    ret, hw->aq.asq_last_status);
7721                 rte_free(mirr_rule);
7722                 return -ENOSYS;
7723         }
7724
7725         mirr_rule->index = sw_id;
7726         mirr_rule->num_entries = j;
7727         mirr_rule->id = rule_id;
7728         mirr_rule->dst_vsi_seid = dst_seid;
7729
7730         if (parent)
7731                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7732         else
7733                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7734
7735         pf->nb_mirror_rule++;
7736         return 0;
7737 }
7738
7739 /**
7740  * i40e_mirror_rule_reset
7741  * @dev: pointer to the device
7742  * @sw_id: mirror rule's sw_id
7743  *
7744  * reset a mirror rule.
7745  *
7746  **/
7747 static int
7748 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7749 {
7750         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7752         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7753         uint16_t seid;
7754         int ret;
7755
7756         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7757
7758         seid = pf->main_vsi->veb->seid;
7759
7760         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7761                 if (sw_id == it->index) {
7762                         mirr_rule = it;
7763                         break;
7764                 }
7765         }
7766         if (mirr_rule) {
7767                 ret = i40e_aq_del_mirror_rule(hw, seid,
7768                                 mirr_rule->rule_type,
7769                                 mirr_rule->entries,
7770                                 mirr_rule->num_entries, mirr_rule->id);
7771                 if (ret < 0) {
7772                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7773                                            " status = %d, aq_err = %d.",
7774                                            ret, hw->aq.asq_last_status);
7775                         return -ENOSYS;
7776                 }
7777                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7778                 rte_free(mirr_rule);
7779                 pf->nb_mirror_rule--;
7780         } else {
7781                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7782                 return -ENOENT;
7783         }
7784         return 0;
7785 }
7786
7787 static uint64_t
7788 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
7789 {
7790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7791         uint64_t systim_cycles;
7792
7793         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
7794         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
7795                         << 32;
7796
7797         return systim_cycles;
7798 }
7799
7800 static uint64_t
7801 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
7802 {
7803         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7804         uint64_t rx_tstamp;
7805
7806         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7807         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
7808                         << 32;
7809
7810         return rx_tstamp;
7811 }
7812
7813 static uint64_t
7814 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7815 {
7816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7817         uint64_t tx_tstamp;
7818
7819         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7820         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
7821                         << 32;
7822
7823         return tx_tstamp;
7824 }
7825
7826 static void
7827 i40e_start_timecounters(struct rte_eth_dev *dev)
7828 {
7829         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7830         struct i40e_adapter *adapter =
7831                         (struct i40e_adapter *)dev->data->dev_private;
7832         struct rte_eth_link link;
7833         uint32_t tsync_inc_l;
7834         uint32_t tsync_inc_h;
7835
7836         /* Get current link speed. */
7837         memset(&link, 0, sizeof(link));
7838         i40e_dev_link_update(dev, 1);
7839         rte_i40e_dev_atomic_read_link_status(dev, &link);
7840
7841         switch (link.link_speed) {
7842         case ETH_LINK_SPEED_40G:
7843                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7844                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7845                 break;
7846         case ETH_LINK_SPEED_10G:
7847                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7848                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7849                 break;
7850         case ETH_LINK_SPEED_1000:
7851                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7852                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7853                 break;
7854         default:
7855                 tsync_inc_l = 0x0;
7856                 tsync_inc_h = 0x0;
7857         }
7858
7859         /* Set the timesync increment value. */
7860         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7861         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7862
7863         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7864         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7865         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7866
7867         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7868         adapter->systime_tc.cc_shift = 0;
7869         adapter->systime_tc.nsec_mask = 0;
7870
7871         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7872         adapter->rx_tstamp_tc.cc_shift = 0;
7873         adapter->rx_tstamp_tc.nsec_mask = 0;
7874
7875         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7876         adapter->tx_tstamp_tc.cc_shift = 0;
7877         adapter->tx_tstamp_tc.nsec_mask = 0;
7878 }
7879
7880 static int
7881 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7882 {
7883         struct i40e_adapter *adapter =
7884                         (struct i40e_adapter *)dev->data->dev_private;
7885
7886         adapter->systime_tc.nsec += delta;
7887         adapter->rx_tstamp_tc.nsec += delta;
7888         adapter->tx_tstamp_tc.nsec += delta;
7889
7890         return 0;
7891 }
7892
7893 static int
7894 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7895 {
7896         uint64_t ns;
7897         struct i40e_adapter *adapter =
7898                         (struct i40e_adapter *)dev->data->dev_private;
7899
7900         ns = rte_timespec_to_ns(ts);
7901
7902         /* Set the timecounters to a new value. */
7903         adapter->systime_tc.nsec = ns;
7904         adapter->rx_tstamp_tc.nsec = ns;
7905         adapter->tx_tstamp_tc.nsec = ns;
7906
7907         return 0;
7908 }
7909
7910 static int
7911 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7912 {
7913         uint64_t ns, systime_cycles;
7914         struct i40e_adapter *adapter =
7915                         (struct i40e_adapter *)dev->data->dev_private;
7916
7917         systime_cycles = i40e_read_systime_cyclecounter(dev);
7918         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7919         *ts = rte_ns_to_timespec(ns);
7920
7921         return 0;
7922 }
7923
7924 static int
7925 i40e_timesync_enable(struct rte_eth_dev *dev)
7926 {
7927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7928         uint32_t tsync_ctl_l;
7929         uint32_t tsync_ctl_h;
7930
7931         /* Stop the timesync system time. */
7932         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7933         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7934         /* Reset the timesync system time value. */
7935         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
7936         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
7937
7938         i40e_start_timecounters(dev);
7939
7940         /* Clear timesync registers. */
7941         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7942         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7943         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
7944         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
7945         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
7946         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
7947
7948         /* Enable timestamping of PTP packets. */
7949         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7950         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7951
7952         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7953         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7954         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7955
7956         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7957         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7958
7959         return 0;
7960 }
7961
7962 static int
7963 i40e_timesync_disable(struct rte_eth_dev *dev)
7964 {
7965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7966         uint32_t tsync_ctl_l;
7967         uint32_t tsync_ctl_h;
7968
7969         /* Disable timestamping of transmitted PTP packets. */
7970         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7971         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7972
7973         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7974         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7975
7976         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7977         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7978
7979         /* Reset the timesync increment value. */
7980         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7981         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7982
7983         return 0;
7984 }
7985
7986 static int
7987 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7988                                 struct timespec *timestamp, uint32_t flags)
7989 {
7990         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7991         struct i40e_adapter *adapter =
7992                 (struct i40e_adapter *)dev->data->dev_private;
7993
7994         uint32_t sync_status;
7995         uint32_t index = flags & 0x03;
7996         uint64_t rx_tstamp_cycles;
7997         uint64_t ns;
7998
7999         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8000         if ((sync_status & (1 << index)) == 0)
8001                 return -EINVAL;
8002
8003         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8004         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8005         *timestamp = rte_ns_to_timespec(ns);
8006
8007         return 0;
8008 }
8009
8010 static int
8011 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8012                                 struct timespec *timestamp)
8013 {
8014         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8015         struct i40e_adapter *adapter =
8016                 (struct i40e_adapter *)dev->data->dev_private;
8017
8018         uint32_t sync_status;
8019         uint64_t tx_tstamp_cycles;
8020         uint64_t ns;
8021
8022         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8023         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8024                 return -EINVAL;
8025
8026         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8027         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8028         *timestamp = rte_ns_to_timespec(ns);
8029
8030         return 0;
8031 }
8032
8033 /*
8034  * i40e_parse_dcb_configure - parse dcb configure from user
8035  * @dev: the device being configured
8036  * @dcb_cfg: pointer of the result of parse
8037  * @*tc_map: bit map of enabled traffic classes
8038  *
8039  * Returns 0 on success, negative value on failure
8040  */
8041 static int
8042 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8043                          struct i40e_dcbx_config *dcb_cfg,
8044                          uint8_t *tc_map)
8045 {
8046         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8047         uint8_t i, tc_bw, bw_lf;
8048
8049         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8050
8051         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8052         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8053                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8054                 return -EINVAL;
8055         }
8056
8057         /* assume each tc has the same bw */
8058         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8059         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8060                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8061         /* to ensure the sum of tcbw is equal to 100 */
8062         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8063         for (i = 0; i < bw_lf; i++)
8064                 dcb_cfg->etscfg.tcbwtable[i]++;
8065
8066         /* assume each tc has the same Transmission Selection Algorithm */
8067         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8068                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8069
8070         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8071                 dcb_cfg->etscfg.prioritytable[i] =
8072                                 dcb_rx_conf->dcb_tc[i];
8073
8074         /* FW needs one App to configure HW */
8075         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8076         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8077         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8078         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8079
8080         if (dcb_rx_conf->nb_tcs == 0)
8081                 *tc_map = 1; /* tc0 only */
8082         else
8083                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8084
8085         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8086                 dcb_cfg->pfc.willing = 0;
8087                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8088                 dcb_cfg->pfc.pfcenable = *tc_map;
8089         }
8090         return 0;
8091 }
8092
8093 /*
8094  * i40e_vsi_get_bw_info - Query VSI BW Information
8095  * @vsi: the VSI being queried
8096  *
8097  * Returns 0 on success, negative value on failure
8098  */
8099 static enum i40e_status_code
8100 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
8101 {
8102         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
8103         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
8104         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8105         enum i40e_status_code ret;
8106         int i;
8107         uint32_t tc_bw_max;
8108
8109         /* Get the VSI level BW configuration */
8110         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
8111         if (ret) {
8112                 PMD_INIT_LOG(ERR,
8113                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
8114                          i40e_stat_str(hw, ret),
8115                          i40e_aq_str(hw, hw->aq.asq_last_status));
8116                 return ret;
8117         }
8118
8119         /* Get the VSI level BW configuration per TC */
8120         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
8121                                                   NULL);
8122         if (ret) {
8123                 PMD_INIT_LOG(ERR,
8124                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
8125                          i40e_stat_str(hw, ret),
8126                          i40e_aq_str(hw, hw->aq.asq_last_status));
8127                 return ret;
8128         }
8129
8130         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
8131                 PMD_INIT_LOG(WARNING,
8132                          "Enabled TCs mismatch from querying VSI BW info"
8133                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
8134                          bw_ets_config.tc_valid_bits);
8135                 /* Still continuing */
8136         }
8137
8138         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
8139         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
8140         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
8141                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
8142         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8143                 vsi->bw_info.bw_ets_share_credits[i] =
8144                                 bw_ets_config.share_credits[i];
8145                 vsi->bw_info.bw_ets_limit_credits[i] =
8146                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
8147                 /* 3 bits out of 4 for each TC */
8148                 vsi->bw_info.bw_ets_max_quanta[i] =
8149                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
8150                 PMD_INIT_LOG(DEBUG,
8151                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
8152                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
8153         }
8154
8155         return ret;
8156 }
8157
8158 static enum i40e_status_code
8159 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8160                               struct i40e_aqc_vsi_properties_data *info,
8161                               uint8_t enabled_tcmap)
8162 {
8163         enum i40e_status_code ret;
8164         int i, total_tc = 0;
8165         uint16_t qpnum_per_tc, bsf, qp_idx;
8166         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8167
8168         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8169         if (ret != I40E_SUCCESS)
8170                 return ret;
8171
8172         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8173                 if (enabled_tcmap & (1 << i))
8174                         total_tc++;
8175         }
8176         if (total_tc == 0)
8177                 total_tc = 1;
8178         vsi->enabled_tc = enabled_tcmap;
8179
8180         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8181         /* Number of queues per enabled TC */
8182         if (qpnum_per_tc == 0) {
8183                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8184                 return I40E_ERR_INVALID_QP_ID;
8185         }
8186         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8187                                 I40E_MAX_Q_PER_TC);
8188         bsf = rte_bsf32(qpnum_per_tc);
8189
8190         /**
8191          * Configure TC and queue mapping parameters, for enabled TC,
8192          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8193          * default queue will serve it.
8194          */
8195         qp_idx = 0;
8196         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8197                 if (vsi->enabled_tc & (1 << i)) {
8198                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8199                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8200                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8201                         qp_idx += qpnum_per_tc;
8202                 } else
8203                         info->tc_mapping[i] = 0;
8204         }
8205
8206         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8207         if (vsi->type == I40E_VSI_SRIOV) {
8208                 info->mapping_flags |=
8209                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8210                 for (i = 0; i < vsi->nb_qps; i++)
8211                         info->queue_mapping[i] =
8212                                 rte_cpu_to_le_16(vsi->base_queue + i);
8213         } else {
8214                 info->mapping_flags |=
8215                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8216                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8217         }
8218         info->valid_sections |=
8219                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8220
8221         return I40E_SUCCESS;
8222 }
8223
8224 /*
8225  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8226  * @vsi: VSI to be configured
8227  * @tc_map: enabled TC bitmap
8228  *
8229  * Returns 0 on success, negative value on failure
8230  */
8231 static enum i40e_status_code
8232 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8233 {
8234         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8235         struct i40e_vsi_context ctxt;
8236         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8237         enum i40e_status_code ret = I40E_SUCCESS;
8238         int i;
8239
8240         /* Check if enabled_tc is same as existing or new TCs */
8241         if (vsi->enabled_tc == tc_map)
8242                 return ret;
8243
8244         /* configure tc bandwidth */
8245         memset(&bw_data, 0, sizeof(bw_data));
8246         bw_data.tc_valid_bits = tc_map;
8247         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8248         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8249                 if (tc_map & BIT_ULL(i))
8250                         bw_data.tc_bw_credits[i] = 1;
8251         }
8252         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8253         if (ret) {
8254                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8255                         " per TC failed = %d",
8256                         hw->aq.asq_last_status);
8257                 goto out;
8258         }
8259         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8260                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8261
8262         /* Update Queue Pairs Mapping for currently enabled UPs */
8263         ctxt.seid = vsi->seid;
8264         ctxt.pf_num = hw->pf_id;
8265         ctxt.vf_num = 0;
8266         ctxt.uplink_seid = vsi->uplink_seid;
8267         ctxt.info = vsi->info;
8268         i40e_get_cap(hw);
8269         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8270         if (ret)
8271                 goto out;
8272
8273         /* Update the VSI after updating the VSI queue-mapping information */
8274         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8275         if (ret) {
8276                 PMD_INIT_LOG(ERR, "Failed to configure "
8277                             "TC queue mapping = %d",
8278                             hw->aq.asq_last_status);
8279                 goto out;
8280         }
8281         /* update the local VSI info with updated queue map */
8282         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8283                                         sizeof(vsi->info.tc_mapping));
8284         (void)rte_memcpy(&vsi->info.queue_mapping,
8285                         &ctxt.info.queue_mapping,
8286                 sizeof(vsi->info.queue_mapping));
8287         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8288         vsi->info.valid_sections = 0;
8289
8290         /* Update current VSI BW information */
8291         ret = i40e_vsi_get_bw_info(vsi);
8292         if (ret) {
8293                 PMD_INIT_LOG(ERR,
8294                          "Failed updating vsi bw info, err %s aq_err %s",
8295                          i40e_stat_str(hw, ret),
8296                          i40e_aq_str(hw, hw->aq.asq_last_status));
8297                 goto out;
8298         }
8299
8300         vsi->enabled_tc = tc_map;
8301
8302 out:
8303         return ret;
8304 }
8305
8306 /*
8307  * i40e_dcb_hw_configure - program the dcb setting to hw
8308  * @pf: pf the configuration is taken on
8309  * @new_cfg: new configuration
8310  * @tc_map: enabled TC bitmap
8311  *
8312  * Returns 0 on success, negative value on failure
8313  */
8314 static enum i40e_status_code
8315 i40e_dcb_hw_configure(struct i40e_pf *pf,
8316                       struct i40e_dcbx_config *new_cfg,
8317                       uint8_t tc_map)
8318 {
8319         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8320         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8321         struct i40e_vsi *main_vsi = pf->main_vsi;
8322         struct i40e_vsi_list *vsi_list;
8323         enum i40e_status_code ret;
8324         int i;
8325         uint32_t val;
8326
8327         /* Use the FW API if FW > v4.4*/
8328         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8329                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8330                                   " to configure DCB");
8331                 return I40E_ERR_FIRMWARE_API_VERSION;
8332         }
8333
8334         /* Check if need reconfiguration */
8335         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8336                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8337                 return I40E_SUCCESS;
8338         }
8339
8340         /* Copy the new config to the current config */
8341         *old_cfg = *new_cfg;
8342         old_cfg->etsrec = old_cfg->etscfg;
8343         ret = i40e_set_dcb_config(hw);
8344         if (ret) {
8345                 PMD_INIT_LOG(ERR,
8346                          "Set DCB Config failed, err %s aq_err %s\n",
8347                          i40e_stat_str(hw, ret),
8348                          i40e_aq_str(hw, hw->aq.asq_last_status));
8349                 return ret;
8350         }
8351         /* set receive Arbiter to RR mode and ETS scheme by default */
8352         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8353                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8354                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8355                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8356                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8357                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8358                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8359                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8360                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8361                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8362                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8363                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8364                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8365         }
8366         /* get local mib to check whether it is configured correctly */
8367         /* IEEE mode */
8368         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8369         /* Get Local DCB Config */
8370         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8371                                      &hw->local_dcbx_config);
8372
8373         /* Update each VSI */
8374         i40e_vsi_config_tc(main_vsi, tc_map);
8375         if (main_vsi->veb) {
8376                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8377                         /* Beside main VSI, only enable default
8378                          * TC for other VSIs
8379                          */
8380                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8381                                                 I40E_DEFAULT_TCMAP);
8382                         if (ret)
8383                                 PMD_INIT_LOG(WARNING,
8384                                          "Failed configuring TC for VSI seid=%d\n",
8385                                          vsi_list->vsi->seid);
8386                         /* continue */
8387                 }
8388         }
8389         return I40E_SUCCESS;
8390 }
8391
8392 /*
8393  * i40e_dcb_init_configure - initial dcb config
8394  * @dev: device being configured
8395  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8396  *
8397  * Returns 0 on success, negative value on failure
8398  */
8399 static int
8400 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8401 {
8402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8404         int ret = 0;
8405
8406         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8407                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8408                 return -ENOTSUP;
8409         }
8410
8411         /* DCB initialization:
8412          * Update DCB configuration from the Firmware and configure
8413          * LLDP MIB change event.
8414          */
8415         if (sw_dcb == TRUE) {
8416                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8417                 if (ret != I40E_SUCCESS)
8418                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8419
8420                 ret = i40e_init_dcb(hw);
8421                 /* if sw_dcb, lldp agent is stopped, the return from
8422                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8423                  * adminq status.
8424                  */
8425                 if (ret != I40E_SUCCESS &&
8426                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8427                         memset(&hw->local_dcbx_config, 0,
8428                                 sizeof(struct i40e_dcbx_config));
8429                         /* set dcb default configuration */
8430                         hw->local_dcbx_config.etscfg.willing = 0;
8431                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8432                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8433                         hw->local_dcbx_config.etscfg.tsatable[0] =
8434                                                 I40E_IEEE_TSA_ETS;
8435                         hw->local_dcbx_config.etsrec =
8436                                 hw->local_dcbx_config.etscfg;
8437                         hw->local_dcbx_config.pfc.willing = 0;
8438                         hw->local_dcbx_config.pfc.pfccap =
8439                                                 I40E_MAX_TRAFFIC_CLASS;
8440                         /* FW needs one App to configure HW */
8441                         hw->local_dcbx_config.numapps = 1;
8442                         hw->local_dcbx_config.app[0].selector =
8443                                                 I40E_APP_SEL_ETHTYPE;
8444                         hw->local_dcbx_config.app[0].priority = 3;
8445                         hw->local_dcbx_config.app[0].protocolid =
8446                                                 I40E_APP_PROTOID_FCOE;
8447                         ret = i40e_set_dcb_config(hw);
8448                         if (ret) {
8449                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8450                                         " err = %d, aq_err = %d.", ret,
8451                                           hw->aq.asq_last_status);
8452                                 return -ENOSYS;
8453                         }
8454                 } else {
8455                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8456                                           " aq_err = %d.", ret,
8457                                           hw->aq.asq_last_status);
8458                         return -ENOTSUP;
8459                 }
8460         } else {
8461                 ret = i40e_aq_start_lldp(hw, NULL);
8462                 if (ret != I40E_SUCCESS)
8463                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8464
8465                 ret = i40e_init_dcb(hw);
8466                 if (!ret) {
8467                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8468                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8469                                                   " DCBX offload.");
8470                                 return -ENOTSUP;
8471                         }
8472                 } else {
8473                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8474                                           " aq_err = %d.", ret,
8475                                           hw->aq.asq_last_status);
8476                         return -ENOTSUP;
8477                 }
8478         }
8479         return 0;
8480 }
8481
8482 /*
8483  * i40e_dcb_setup - setup dcb related config
8484  * @dev: device being configured
8485  *
8486  * Returns 0 on success, negative value on failure
8487  */
8488 static int
8489 i40e_dcb_setup(struct rte_eth_dev *dev)
8490 {
8491         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8492         struct i40e_dcbx_config dcb_cfg;
8493         uint8_t tc_map = 0;
8494         int ret = 0;
8495
8496         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8497                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8498                 return -ENOTSUP;
8499         }
8500
8501         if (pf->vf_num != 0 ||
8502             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8503                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8504
8505         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8506         if (ret) {
8507                 PMD_INIT_LOG(ERR, "invalid dcb config");
8508                 return -EINVAL;
8509         }
8510         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8511         if (ret) {
8512                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8513                 return -ENOSYS;
8514         }
8515
8516         return 0;
8517 }
8518
8519 static int
8520 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8521                       struct rte_eth_dcb_info *dcb_info)
8522 {
8523         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8524         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8525         struct i40e_vsi *vsi = pf->main_vsi;
8526         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8527         uint16_t bsf, tc_mapping;
8528         int i;
8529
8530         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8531                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8532         else
8533                 dcb_info->nb_tcs = 1;
8534         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8535                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8536         for (i = 0; i < dcb_info->nb_tcs; i++)
8537                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8538
8539         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8540                 if (vsi->enabled_tc & (1 << i)) {
8541                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8542                         /* only main vsi support multi TCs */
8543                         dcb_info->tc_queue.tc_rxq[0][i].base =
8544                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8545                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8546                         dcb_info->tc_queue.tc_txq[0][i].base =
8547                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8548                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8549                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8550                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8551                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8552                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8553                 }
8554         }
8555
8556         return 0;
8557 }
8558
8559 static int
8560 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8561 {
8562         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8563         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8564         uint16_t interval =
8565                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8566         uint16_t msix_intr;
8567
8568         msix_intr = intr_handle->intr_vec[queue_id];
8569         if (msix_intr == I40E_MISC_VEC_ID)
8570                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8571                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8572                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8573                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8574                                (interval <<
8575                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8576         else
8577                 I40E_WRITE_REG(hw,
8578                                I40E_PFINT_DYN_CTLN(msix_intr -
8579                                                    I40E_RX_VEC_START),
8580                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8581                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8582                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8583                                (interval <<
8584                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8585
8586         I40E_WRITE_FLUSH(hw);
8587         rte_intr_enable(&dev->pci_dev->intr_handle);
8588
8589         return 0;
8590 }
8591
8592 static int
8593 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8594 {
8595         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8596         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8597         uint16_t msix_intr;
8598
8599         msix_intr = intr_handle->intr_vec[queue_id];
8600         if (msix_intr == I40E_MISC_VEC_ID)
8601                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8602         else
8603                 I40E_WRITE_REG(hw,
8604                                I40E_PFINT_DYN_CTLN(msix_intr -
8605                                                    I40E_RX_VEC_START),
8606                                0);
8607         I40E_WRITE_FLUSH(hw);
8608
8609         return 0;
8610 }