4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and interval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control default high water */
90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
92 /* Flow control default low water */
93 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
95 /* Flow control enable fwd bit */
96 #define I40E_PRTMAC_FWD_CTRL 0x00000001
98 /* Receive Packet Buffer size */
99 #define I40E_RXPBSIZE (968 * 1024)
101 /* Kilobytes shift */
102 #define I40E_KILOSHIFT 10
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int i40e_dev_configure(struct rte_eth_dev *dev);
250 static int i40e_dev_start(struct rte_eth_dev *dev);
251 static void i40e_dev_stop(struct rte_eth_dev *dev);
252 static void i40e_dev_close(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
260 struct rte_eth_stats *stats);
261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
262 struct rte_eth_xstat *xstats, unsigned n);
263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
264 struct rte_eth_xstat_name *xstats_names,
266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
272 char *fw_version, size_t fw_size);
273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
274 struct rte_eth_dev_info *dev_info);
275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
279 enum rte_vlan_type vlan_type,
281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
289 struct rte_eth_fc_conf *fc_conf);
290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
291 struct rte_eth_fc_conf *fc_conf);
292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
293 struct rte_eth_pfc_conf *pfc_conf);
294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
295 struct ether_addr *mac_addr,
298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
300 struct rte_eth_rss_reta_entry64 *reta_conf,
302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
303 struct rte_eth_rss_reta_entry64 *reta_conf,
306 static int i40e_get_cap(struct i40e_hw *hw);
307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
308 static int i40e_pf_setup(struct i40e_pf *pf);
309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
314 bool offset_loaded, uint64_t *offset, uint64_t *stat);
315 static void i40e_stat_update_48(struct i40e_hw *hw,
321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
322 static void i40e_dev_interrupt_handler(void *param);
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
342 struct rte_eth_rss_conf *rss_conf);
343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
344 struct rte_eth_rss_conf *rss_conf);
345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
346 struct rte_eth_udp_tunnel *udp_tunnel);
347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
348 struct rte_eth_udp_tunnel *udp_tunnel);
349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
351 enum rte_filter_op filter_op,
353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
354 enum rte_filter_type filter_type,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
358 struct rte_eth_dcb_info *dcb_info);
359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
360 static void i40e_configure_registers(struct i40e_hw *hw);
361 static void i40e_hw_init(struct rte_eth_dev *dev);
362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
364 struct rte_eth_mirror_conf *mirror_conf,
365 uint8_t sw_id, uint8_t on);
366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
371 struct timespec *timestamp,
373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
374 struct timespec *timestamp);
375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
380 struct timespec *timestamp);
381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
382 const struct timespec *timestamp);
384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
389 static int i40e_get_regs(struct rte_eth_dev *dev,
390 struct rte_dev_reg_info *regs);
392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
395 struct rte_dev_eeprom_info *eeprom);
397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
398 struct ether_addr *mac_addr);
400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
402 static int i40e_ethertype_filter_convert(
403 const struct rte_eth_ethertype_filter *input,
404 struct i40e_ethertype_filter *filter);
405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
406 struct i40e_ethertype_filter *filter);
408 static int i40e_tunnel_filter_convert(
409 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
410 struct i40e_tunnel_filter *tunnel_filter);
411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
412 struct i40e_tunnel_filter *tunnel_filter);
413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
417 static void i40e_filter_restore(struct i40e_pf *pf);
418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
420 int i40e_logtype_init;
421 int i40e_logtype_driver;
423 static const struct rte_pci_id pci_id_i40e_map[] = {
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
444 { .vendor_id = 0, /* sentinel */ },
447 static const struct eth_dev_ops i40e_eth_dev_ops = {
448 .dev_configure = i40e_dev_configure,
449 .dev_start = i40e_dev_start,
450 .dev_stop = i40e_dev_stop,
451 .dev_close = i40e_dev_close,
452 .promiscuous_enable = i40e_dev_promiscuous_enable,
453 .promiscuous_disable = i40e_dev_promiscuous_disable,
454 .allmulticast_enable = i40e_dev_allmulticast_enable,
455 .allmulticast_disable = i40e_dev_allmulticast_disable,
456 .dev_set_link_up = i40e_dev_set_link_up,
457 .dev_set_link_down = i40e_dev_set_link_down,
458 .link_update = i40e_dev_link_update,
459 .stats_get = i40e_dev_stats_get,
460 .xstats_get = i40e_dev_xstats_get,
461 .xstats_get_names = i40e_dev_xstats_get_names,
462 .stats_reset = i40e_dev_stats_reset,
463 .xstats_reset = i40e_dev_stats_reset,
464 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
465 .fw_version_get = i40e_fw_version_get,
466 .dev_infos_get = i40e_dev_info_get,
467 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
468 .vlan_filter_set = i40e_vlan_filter_set,
469 .vlan_tpid_set = i40e_vlan_tpid_set,
470 .vlan_offload_set = i40e_vlan_offload_set,
471 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
472 .vlan_pvid_set = i40e_vlan_pvid_set,
473 .rx_queue_start = i40e_dev_rx_queue_start,
474 .rx_queue_stop = i40e_dev_rx_queue_stop,
475 .tx_queue_start = i40e_dev_tx_queue_start,
476 .tx_queue_stop = i40e_dev_tx_queue_stop,
477 .rx_queue_setup = i40e_dev_rx_queue_setup,
478 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
479 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
480 .rx_queue_release = i40e_dev_rx_queue_release,
481 .rx_queue_count = i40e_dev_rx_queue_count,
482 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
483 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
484 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
485 .tx_queue_setup = i40e_dev_tx_queue_setup,
486 .tx_queue_release = i40e_dev_tx_queue_release,
487 .dev_led_on = i40e_dev_led_on,
488 .dev_led_off = i40e_dev_led_off,
489 .flow_ctrl_get = i40e_flow_ctrl_get,
490 .flow_ctrl_set = i40e_flow_ctrl_set,
491 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
492 .mac_addr_add = i40e_macaddr_add,
493 .mac_addr_remove = i40e_macaddr_remove,
494 .reta_update = i40e_dev_rss_reta_update,
495 .reta_query = i40e_dev_rss_reta_query,
496 .rss_hash_update = i40e_dev_rss_hash_update,
497 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
498 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
499 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
500 .filter_ctrl = i40e_dev_filter_ctrl,
501 .rxq_info_get = i40e_rxq_info_get,
502 .txq_info_get = i40e_txq_info_get,
503 .mirror_rule_set = i40e_mirror_rule_set,
504 .mirror_rule_reset = i40e_mirror_rule_reset,
505 .timesync_enable = i40e_timesync_enable,
506 .timesync_disable = i40e_timesync_disable,
507 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
508 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
509 .get_dcb_info = i40e_dev_get_dcb_info,
510 .timesync_adjust_time = i40e_timesync_adjust_time,
511 .timesync_read_time = i40e_timesync_read_time,
512 .timesync_write_time = i40e_timesync_write_time,
513 .get_reg = i40e_get_regs,
514 .get_eeprom_length = i40e_get_eeprom_length,
515 .get_eeprom = i40e_get_eeprom,
516 .mac_addr_set = i40e_set_default_mac_addr,
517 .mtu_set = i40e_dev_mtu_set,
520 /* store statistics names and its offset in stats structure */
521 struct rte_i40e_xstats_name_off {
522 char name[RTE_ETH_XSTATS_NAME_SIZE];
526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
527 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
528 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
529 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
530 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
531 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
532 rx_unknown_protocol)},
533 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
534 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
535 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
536 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
540 sizeof(rte_i40e_stats_strings[0]))
542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
543 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
544 tx_dropped_link_down)},
545 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
546 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
548 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
549 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
551 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
555 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
556 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
557 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
558 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
559 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
560 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
577 mac_short_packet_dropped)},
578 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
580 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
581 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
582 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
594 {"rx_flow_director_atr_match_packets",
595 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
596 {"rx_flow_director_sb_match_packets",
597 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
598 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
600 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
602 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
604 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
609 sizeof(rte_i40e_hw_port_strings[0]))
611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
612 {"xon_packets", offsetof(struct i40e_hw_port_stats,
614 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
619 sizeof(rte_i40e_rxq_prio_strings[0]))
621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
622 {"xon_packets", offsetof(struct i40e_hw_port_stats,
624 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
626 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
627 priority_xon_2_xoff)},
630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
631 sizeof(rte_i40e_txq_prio_strings[0]))
633 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
634 struct rte_pci_device *pci_dev)
636 return rte_eth_dev_pci_generic_probe(pci_dev,
637 sizeof(struct i40e_adapter), eth_i40e_dev_init);
640 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
642 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
645 static struct rte_pci_driver rte_i40e_pmd = {
646 .id_table = pci_id_i40e_map,
647 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
648 .probe = eth_i40e_pci_probe,
649 .remove = eth_i40e_pci_remove,
653 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
654 struct rte_eth_link *link)
656 struct rte_eth_link *dst = link;
657 struct rte_eth_link *src = &(dev->data->dev_link);
659 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
660 *(uint64_t *)src) == 0)
667 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
668 struct rte_eth_link *link)
670 struct rte_eth_link *dst = &(dev->data->dev_link);
671 struct rte_eth_link *src = link;
673 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
674 *(uint64_t *)src) == 0)
680 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
681 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
682 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
684 #ifndef I40E_GLQF_ORT
685 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
687 #ifndef I40E_GLQF_PIT
688 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
690 #ifndef I40E_GLQF_L3_MAP
691 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
694 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
697 * Initialize registers for flexible payload, which should be set by NVM.
698 * This should be removed from code once it is fixed in NVM.
700 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
702 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
710 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
711 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
713 /* Initialize registers for parsing packet type of QinQ */
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
715 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
718 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
721 * Add a ethertype filter to drop all flow control frames transmitted
725 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
727 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
728 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
729 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
730 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
733 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
734 I40E_FLOW_CONTROL_ETHERTYPE, flags,
735 pf->main_vsi_seid, 0,
739 "Failed to add filter to drop flow control frames from VSIs.");
743 floating_veb_list_handler(__rte_unused const char *key,
744 const char *floating_veb_value,
748 unsigned int count = 0;
751 bool *vf_floating_veb = opaque;
753 while (isblank(*floating_veb_value))
754 floating_veb_value++;
756 /* Reset floating VEB configuration for VFs */
757 for (idx = 0; idx < I40E_MAX_VF; idx++)
758 vf_floating_veb[idx] = false;
762 while (isblank(*floating_veb_value))
763 floating_veb_value++;
764 if (*floating_veb_value == '\0')
767 idx = strtoul(floating_veb_value, &end, 10);
768 if (errno || end == NULL)
770 while (isblank(*end))
774 } else if ((*end == ';') || (*end == '\0')) {
776 if (min == I40E_MAX_VF)
778 if (max >= I40E_MAX_VF)
779 max = I40E_MAX_VF - 1;
780 for (idx = min; idx <= max; idx++) {
781 vf_floating_veb[idx] = true;
788 floating_veb_value = end + 1;
789 } while (*end != '\0');
798 config_vf_floating_veb(struct rte_devargs *devargs,
799 uint16_t floating_veb,
800 bool *vf_floating_veb)
802 struct rte_kvargs *kvlist;
804 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
808 /* All the VFs attach to the floating VEB by default
809 * when the floating VEB is enabled.
811 for (i = 0; i < I40E_MAX_VF; i++)
812 vf_floating_veb[i] = true;
817 kvlist = rte_kvargs_parse(devargs->args, NULL);
821 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
822 rte_kvargs_free(kvlist);
825 /* When the floating_veb_list parameter exists, all the VFs
826 * will attach to the legacy VEB firstly, then configure VFs
827 * to the floating VEB according to the floating_veb_list.
829 if (rte_kvargs_process(kvlist, floating_veb_list,
830 floating_veb_list_handler,
831 vf_floating_veb) < 0) {
832 rte_kvargs_free(kvlist);
835 rte_kvargs_free(kvlist);
839 i40e_check_floating_handler(__rte_unused const char *key,
841 __rte_unused void *opaque)
843 if (strcmp(value, "1"))
850 is_floating_veb_supported(struct rte_devargs *devargs)
852 struct rte_kvargs *kvlist;
853 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
858 kvlist = rte_kvargs_parse(devargs->args, NULL);
862 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
863 rte_kvargs_free(kvlist);
866 /* Floating VEB is enabled when there's key-value:
867 * enable_floating_veb=1
869 if (rte_kvargs_process(kvlist, floating_veb_key,
870 i40e_check_floating_handler, NULL) < 0) {
871 rte_kvargs_free(kvlist);
874 rte_kvargs_free(kvlist);
880 config_floating_veb(struct rte_eth_dev *dev)
882 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
883 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
884 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
886 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
888 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
890 is_floating_veb_supported(pci_dev->device.devargs);
891 config_vf_floating_veb(pci_dev->device.devargs,
893 pf->floating_veb_list);
895 pf->floating_veb = false;
899 #define I40E_L2_TAGS_S_TAG_SHIFT 1
900 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
903 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
905 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
906 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
907 char ethertype_hash_name[RTE_HASH_NAMESIZE];
910 struct rte_hash_parameters ethertype_hash_params = {
911 .name = ethertype_hash_name,
912 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
913 .key_len = sizeof(struct i40e_ethertype_filter_input),
914 .hash_func = rte_hash_crc,
915 .hash_func_init_val = 0,
916 .socket_id = rte_socket_id(),
919 /* Initialize ethertype filter rule list and hash */
920 TAILQ_INIT(ðertype_rule->ethertype_list);
921 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
922 "ethertype_%s", dev->device->name);
923 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
924 if (!ethertype_rule->hash_table) {
925 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
928 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
929 sizeof(struct i40e_ethertype_filter *) *
930 I40E_MAX_ETHERTYPE_FILTER_NUM,
932 if (!ethertype_rule->hash_map) {
934 "Failed to allocate memory for ethertype hash map!");
936 goto err_ethertype_hash_map_alloc;
941 err_ethertype_hash_map_alloc:
942 rte_hash_free(ethertype_rule->hash_table);
948 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
950 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
951 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
952 char tunnel_hash_name[RTE_HASH_NAMESIZE];
955 struct rte_hash_parameters tunnel_hash_params = {
956 .name = tunnel_hash_name,
957 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
958 .key_len = sizeof(struct i40e_tunnel_filter_input),
959 .hash_func = rte_hash_crc,
960 .hash_func_init_val = 0,
961 .socket_id = rte_socket_id(),
964 /* Initialize tunnel filter rule list and hash */
965 TAILQ_INIT(&tunnel_rule->tunnel_list);
966 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
967 "tunnel_%s", dev->device->name);
968 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
969 if (!tunnel_rule->hash_table) {
970 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
973 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
974 sizeof(struct i40e_tunnel_filter *) *
975 I40E_MAX_TUNNEL_FILTER_NUM,
977 if (!tunnel_rule->hash_map) {
979 "Failed to allocate memory for tunnel hash map!");
981 goto err_tunnel_hash_map_alloc;
986 err_tunnel_hash_map_alloc:
987 rte_hash_free(tunnel_rule->hash_table);
993 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
995 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
996 struct i40e_fdir_info *fdir_info = &pf->fdir;
997 char fdir_hash_name[RTE_HASH_NAMESIZE];
1000 struct rte_hash_parameters fdir_hash_params = {
1001 .name = fdir_hash_name,
1002 .entries = I40E_MAX_FDIR_FILTER_NUM,
1003 .key_len = sizeof(struct rte_eth_fdir_input),
1004 .hash_func = rte_hash_crc,
1005 .hash_func_init_val = 0,
1006 .socket_id = rte_socket_id(),
1009 /* Initialize flow director filter rule list and hash */
1010 TAILQ_INIT(&fdir_info->fdir_list);
1011 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1012 "fdir_%s", dev->device->name);
1013 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1014 if (!fdir_info->hash_table) {
1015 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1018 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1019 sizeof(struct i40e_fdir_filter *) *
1020 I40E_MAX_FDIR_FILTER_NUM,
1022 if (!fdir_info->hash_map) {
1024 "Failed to allocate memory for fdir hash map!");
1026 goto err_fdir_hash_map_alloc;
1030 err_fdir_hash_map_alloc:
1031 rte_hash_free(fdir_info->hash_table);
1037 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 struct rte_pci_device *pci_dev;
1040 struct rte_intr_handle *intr_handle;
1041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043 struct i40e_vsi *vsi;
1046 uint8_t aq_fail = 0;
1048 PMD_INIT_FUNC_TRACE();
1050 dev->dev_ops = &i40e_eth_dev_ops;
1051 dev->rx_pkt_burst = i40e_recv_pkts;
1052 dev->tx_pkt_burst = i40e_xmit_pkts;
1053 dev->tx_pkt_prepare = i40e_prep_pkts;
1055 /* for secondary processes, we don't initialise any further as primary
1056 * has already done this work. Only check we don't need a different
1058 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1059 i40e_set_rx_function(dev);
1060 i40e_set_tx_function(dev);
1063 i40e_set_default_ptype_table(dev);
1064 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1065 intr_handle = &pci_dev->intr_handle;
1067 rte_eth_copy_pci_info(dev, pci_dev);
1068 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1071 pf->adapter->eth_dev = dev;
1072 pf->dev_data = dev->data;
1074 hw->back = I40E_PF_TO_ADAPTER(pf);
1075 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1078 "Hardware is not available, as address is NULL");
1082 hw->vendor_id = pci_dev->id.vendor_id;
1083 hw->device_id = pci_dev->id.device_id;
1084 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1085 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1086 hw->bus.device = pci_dev->addr.devid;
1087 hw->bus.func = pci_dev->addr.function;
1088 hw->adapter_stopped = 0;
1090 /* Make sure all is clean before doing PF reset */
1093 /* Initialize the hardware */
1096 /* Reset here to make sure all is clean for each PF */
1097 ret = i40e_pf_reset(hw);
1099 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1103 /* Initialize the shared code (base driver) */
1104 ret = i40e_init_shared_code(hw);
1106 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1111 * To work around the NVM issue, initialize registers
1112 * for flexible payload and packet type of QinQ by
1113 * software. It should be removed once issues are fixed
1116 i40e_GLQF_reg_init(hw);
1118 /* Initialize the input set for filters (hash and fd) to default value */
1119 i40e_filter_input_set_init(pf);
1121 /* Initialize the parameters for adminq */
1122 i40e_init_adminq_parameter(hw);
1123 ret = i40e_init_adminq(hw);
1124 if (ret != I40E_SUCCESS) {
1125 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1128 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1129 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1130 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1131 ((hw->nvm.version >> 12) & 0xf),
1132 ((hw->nvm.version >> 4) & 0xff),
1133 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135 /* initialise the L3_MAP register */
1136 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1139 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141 /* Need the special FW version to support floating VEB */
1142 config_floating_veb(dev);
1143 /* Clear PXE mode */
1144 i40e_clear_pxe_mode(hw);
1145 i40e_dev_sync_phy_type(hw);
1148 * On X710, performance number is far from the expectation on recent
1149 * firmware versions. The fix for this issue may not be integrated in
1150 * the following firmware version. So the workaround in software driver
1151 * is needed. It needs to modify the initial values of 3 internal only
1152 * registers. Note that the workaround can be removed when it is fixed
1153 * in firmware in the future.
1155 i40e_configure_registers(hw);
1157 /* Get hw capabilities */
1158 ret = i40e_get_cap(hw);
1159 if (ret != I40E_SUCCESS) {
1160 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1161 goto err_get_capabilities;
1164 /* Initialize parameters for PF */
1165 ret = i40e_pf_parameter_init(dev);
1167 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1168 goto err_parameter_init;
1171 /* Initialize the queue management */
1172 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1174 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1175 goto err_qp_pool_init;
1177 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1178 hw->func_caps.num_msix_vectors - 1);
1180 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1181 goto err_msix_pool_init;
1184 /* Initialize lan hmc */
1185 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1186 hw->func_caps.num_rx_qp, 0, 0);
1187 if (ret != I40E_SUCCESS) {
1188 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1189 goto err_init_lan_hmc;
1192 /* Configure lan hmc */
1193 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1194 if (ret != I40E_SUCCESS) {
1195 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1196 goto err_configure_lan_hmc;
1199 /* Get and check the mac address */
1200 i40e_get_mac_addr(hw, hw->mac.addr);
1201 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1202 PMD_INIT_LOG(ERR, "mac address is not valid");
1204 goto err_get_mac_addr;
1206 /* Copy the permanent MAC address */
1207 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1208 (struct ether_addr *) hw->mac.perm_addr);
1210 /* Disable flow control */
1211 hw->fc.requested_mode = I40E_FC_NONE;
1212 i40e_set_fc(hw, &aq_fail, TRUE);
1214 /* Set the global registers with default ether type value */
1215 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1216 if (ret != I40E_SUCCESS) {
1218 "Failed to set the default outer VLAN ether type");
1219 goto err_setup_pf_switch;
1222 /* PF setup, which includes VSI setup */
1223 ret = i40e_pf_setup(pf);
1225 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1226 goto err_setup_pf_switch;
1229 /* reset all stats of the device, including pf and main vsi */
1230 i40e_dev_stats_reset(dev);
1234 /* Disable double vlan by default */
1235 i40e_vsi_config_double_vlan(vsi, FALSE);
1237 /* Disable S-TAG identification when floating_veb is disabled */
1238 if (!pf->floating_veb) {
1239 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1240 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1241 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1242 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1246 if (!vsi->max_macaddrs)
1247 len = ETHER_ADDR_LEN;
1249 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1251 /* Should be after VSI initialized */
1252 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1253 if (!dev->data->mac_addrs) {
1255 "Failed to allocated memory for storing mac address");
1258 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1259 &dev->data->mac_addrs[0]);
1261 /* Init dcb to sw mode by default */
1262 ret = i40e_dcb_init_configure(dev, TRUE);
1263 if (ret != I40E_SUCCESS) {
1264 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1265 pf->flags &= ~I40E_FLAG_DCB;
1267 /* Update HW struct after DCB configuration */
1270 /* initialize pf host driver to setup SRIOV resource if applicable */
1271 i40e_pf_host_init(dev);
1273 /* register callback func to eal lib */
1274 rte_intr_callback_register(intr_handle,
1275 i40e_dev_interrupt_handler, dev);
1277 /* configure and enable device interrupt */
1278 i40e_pf_config_irq0(hw, TRUE);
1279 i40e_pf_enable_irq0(hw);
1281 /* enable uio intr after callback register */
1282 rte_intr_enable(intr_handle);
1284 * Add an ethertype filter to drop all flow control frames transmitted
1285 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1288 i40e_add_tx_flow_control_drop_filter(pf);
1290 /* Set the max frame size to 0x2600 by default,
1291 * in case other drivers changed the default value.
1293 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1295 /* initialize mirror rule list */
1296 TAILQ_INIT(&pf->mirror_list);
1298 ret = i40e_init_ethtype_filter_list(dev);
1300 goto err_init_ethtype_filter_list;
1301 ret = i40e_init_tunnel_filter_list(dev);
1303 goto err_init_tunnel_filter_list;
1304 ret = i40e_init_fdir_filter_list(dev);
1306 goto err_init_fdir_filter_list;
1310 err_init_fdir_filter_list:
1311 rte_free(pf->tunnel.hash_table);
1312 rte_free(pf->tunnel.hash_map);
1313 err_init_tunnel_filter_list:
1314 rte_free(pf->ethertype.hash_table);
1315 rte_free(pf->ethertype.hash_map);
1316 err_init_ethtype_filter_list:
1317 rte_free(dev->data->mac_addrs);
1319 i40e_vsi_release(pf->main_vsi);
1320 err_setup_pf_switch:
1322 err_configure_lan_hmc:
1323 (void)i40e_shutdown_lan_hmc(hw);
1325 i40e_res_pool_destroy(&pf->msix_pool);
1327 i40e_res_pool_destroy(&pf->qp_pool);
1330 err_get_capabilities:
1331 (void)i40e_shutdown_adminq(hw);
1337 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1339 struct i40e_ethertype_filter *p_ethertype;
1340 struct i40e_ethertype_rule *ethertype_rule;
1342 ethertype_rule = &pf->ethertype;
1343 /* Remove all ethertype filter rules and hash */
1344 if (ethertype_rule->hash_map)
1345 rte_free(ethertype_rule->hash_map);
1346 if (ethertype_rule->hash_table)
1347 rte_hash_free(ethertype_rule->hash_table);
1349 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1350 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1351 p_ethertype, rules);
1352 rte_free(p_ethertype);
1357 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1359 struct i40e_tunnel_filter *p_tunnel;
1360 struct i40e_tunnel_rule *tunnel_rule;
1362 tunnel_rule = &pf->tunnel;
1363 /* Remove all tunnel director rules and hash */
1364 if (tunnel_rule->hash_map)
1365 rte_free(tunnel_rule->hash_map);
1366 if (tunnel_rule->hash_table)
1367 rte_hash_free(tunnel_rule->hash_table);
1369 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1370 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1376 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1378 struct i40e_fdir_filter *p_fdir;
1379 struct i40e_fdir_info *fdir_info;
1381 fdir_info = &pf->fdir;
1382 /* Remove all flow director rules and hash */
1383 if (fdir_info->hash_map)
1384 rte_free(fdir_info->hash_map);
1385 if (fdir_info->hash_table)
1386 rte_hash_free(fdir_info->hash_table);
1388 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1389 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1395 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1398 struct rte_pci_device *pci_dev;
1399 struct rte_intr_handle *intr_handle;
1401 struct i40e_filter_control_settings settings;
1402 struct rte_flow *p_flow;
1404 uint8_t aq_fail = 0;
1406 PMD_INIT_FUNC_TRACE();
1408 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1411 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1412 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1414 intr_handle = &pci_dev->intr_handle;
1416 if (hw->adapter_stopped == 0)
1417 i40e_dev_close(dev);
1419 dev->dev_ops = NULL;
1420 dev->rx_pkt_burst = NULL;
1421 dev->tx_pkt_burst = NULL;
1423 /* Clear PXE mode */
1424 i40e_clear_pxe_mode(hw);
1426 /* Unconfigure filter control */
1427 memset(&settings, 0, sizeof(settings));
1428 ret = i40e_set_filter_control(hw, &settings);
1430 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1433 /* Disable flow control */
1434 hw->fc.requested_mode = I40E_FC_NONE;
1435 i40e_set_fc(hw, &aq_fail, TRUE);
1437 /* uninitialize pf host driver */
1438 i40e_pf_host_uninit(dev);
1440 rte_free(dev->data->mac_addrs);
1441 dev->data->mac_addrs = NULL;
1443 /* disable uio intr before callback unregister */
1444 rte_intr_disable(intr_handle);
1446 /* register callback func to eal lib */
1447 rte_intr_callback_unregister(intr_handle,
1448 i40e_dev_interrupt_handler, dev);
1450 i40e_rm_ethtype_filter_list(pf);
1451 i40e_rm_tunnel_filter_list(pf);
1452 i40e_rm_fdir_filter_list(pf);
1454 /* Remove all flows */
1455 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1456 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1464 i40e_dev_configure(struct rte_eth_dev *dev)
1466 struct i40e_adapter *ad =
1467 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1468 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1469 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1470 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1473 ret = i40e_dev_sync_phy_type(hw);
1477 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1478 * bulk allocation or vector Rx preconditions we will reset it.
1480 ad->rx_bulk_alloc_allowed = true;
1481 ad->rx_vec_allowed = true;
1482 ad->tx_simple_allowed = true;
1483 ad->tx_vec_allowed = true;
1485 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1486 ret = i40e_fdir_setup(pf);
1487 if (ret != I40E_SUCCESS) {
1488 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1491 ret = i40e_fdir_configure(dev);
1493 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1497 i40e_fdir_teardown(pf);
1499 ret = i40e_dev_init_vlan(dev);
1504 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1505 * RSS setting have different requirements.
1506 * General PMD driver call sequence are NIC init, configure,
1507 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1508 * will try to lookup the VSI that specific queue belongs to if VMDQ
1509 * applicable. So, VMDQ setting has to be done before
1510 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1511 * For RSS setting, it will try to calculate actual configured RX queue
1512 * number, which will be available after rx_queue_setup(). dev_start()
1513 * function is good to place RSS setup.
1515 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1516 ret = i40e_vmdq_setup(dev);
1521 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1522 ret = i40e_dcb_setup(dev);
1524 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1529 TAILQ_INIT(&pf->flow_list);
1534 /* need to release vmdq resource if exists */
1535 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1536 i40e_vsi_release(pf->vmdq[i].vsi);
1537 pf->vmdq[i].vsi = NULL;
1542 /* need to release fdir resource if exists */
1543 i40e_fdir_teardown(pf);
1548 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1550 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1551 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1552 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1553 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1554 uint16_t msix_vect = vsi->msix_intr;
1557 for (i = 0; i < vsi->nb_qps; i++) {
1558 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1559 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1563 if (vsi->type != I40E_VSI_SRIOV) {
1564 if (!rte_intr_allow_others(intr_handle)) {
1565 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1566 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1568 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1571 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1572 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1574 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1579 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1580 vsi->user_param + (msix_vect - 1);
1582 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1583 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1585 I40E_WRITE_FLUSH(hw);
1589 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1590 int base_queue, int nb_queue)
1594 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1596 /* Bind all RX queues to allocated MSIX interrupt */
1597 for (i = 0; i < nb_queue; i++) {
1598 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1599 I40E_QINT_RQCTL_ITR_INDX_MASK |
1600 ((base_queue + i + 1) <<
1601 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1602 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1603 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1605 if (i == nb_queue - 1)
1606 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1607 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1610 /* Write first RX queue to Link list register as the head element */
1611 if (vsi->type != I40E_VSI_SRIOV) {
1613 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1615 if (msix_vect == I40E_MISC_VEC_ID) {
1616 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1618 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1620 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1622 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1625 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1627 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1629 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1631 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1638 if (msix_vect == I40E_MISC_VEC_ID) {
1640 I40E_VPINT_LNKLST0(vsi->user_param),
1642 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1644 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1646 /* num_msix_vectors_vf needs to minus irq0 */
1647 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1648 vsi->user_param + (msix_vect - 1);
1650 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1652 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1654 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1658 I40E_WRITE_FLUSH(hw);
1662 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1664 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1665 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1666 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1667 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1668 uint16_t msix_vect = vsi->msix_intr;
1669 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1670 uint16_t queue_idx = 0;
1675 for (i = 0; i < vsi->nb_qps; i++) {
1676 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1677 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1680 /* INTENA flag is not auto-cleared for interrupt */
1681 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1682 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1683 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1684 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1685 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1687 /* VF bind interrupt */
1688 if (vsi->type == I40E_VSI_SRIOV) {
1689 __vsi_queues_bind_intr(vsi, msix_vect,
1690 vsi->base_queue, vsi->nb_qps);
1694 /* PF & VMDq bind interrupt */
1695 if (rte_intr_dp_is_en(intr_handle)) {
1696 if (vsi->type == I40E_VSI_MAIN) {
1699 } else if (vsi->type == I40E_VSI_VMDQ2) {
1700 struct i40e_vsi *main_vsi =
1701 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1702 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1707 for (i = 0; i < vsi->nb_used_qps; i++) {
1709 if (!rte_intr_allow_others(intr_handle))
1710 /* allow to share MISC_VEC_ID */
1711 msix_vect = I40E_MISC_VEC_ID;
1713 /* no enough msix_vect, map all to one */
1714 __vsi_queues_bind_intr(vsi, msix_vect,
1715 vsi->base_queue + i,
1716 vsi->nb_used_qps - i);
1717 for (; !!record && i < vsi->nb_used_qps; i++)
1718 intr_handle->intr_vec[queue_idx + i] =
1722 /* 1:1 queue/msix_vect mapping */
1723 __vsi_queues_bind_intr(vsi, msix_vect,
1724 vsi->base_queue + i, 1);
1726 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1734 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1736 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1737 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1738 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1739 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1740 uint16_t interval = i40e_calc_itr_interval(\
1741 RTE_LIBRTE_I40E_ITR_INTERVAL);
1742 uint16_t msix_intr, i;
1744 if (rte_intr_allow_others(intr_handle))
1745 for (i = 0; i < vsi->nb_msix; i++) {
1746 msix_intr = vsi->msix_intr + i;
1747 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1748 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1749 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1750 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1752 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1755 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1756 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1757 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1758 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1760 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1762 I40E_WRITE_FLUSH(hw);
1766 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1768 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1769 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1770 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1771 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1772 uint16_t msix_intr, i;
1774 if (rte_intr_allow_others(intr_handle))
1775 for (i = 0; i < vsi->nb_msix; i++) {
1776 msix_intr = vsi->msix_intr + i;
1777 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1781 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1783 I40E_WRITE_FLUSH(hw);
1786 static inline uint8_t
1787 i40e_parse_link_speeds(uint16_t link_speeds)
1789 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1791 if (link_speeds & ETH_LINK_SPEED_40G)
1792 link_speed |= I40E_LINK_SPEED_40GB;
1793 if (link_speeds & ETH_LINK_SPEED_25G)
1794 link_speed |= I40E_LINK_SPEED_25GB;
1795 if (link_speeds & ETH_LINK_SPEED_20G)
1796 link_speed |= I40E_LINK_SPEED_20GB;
1797 if (link_speeds & ETH_LINK_SPEED_10G)
1798 link_speed |= I40E_LINK_SPEED_10GB;
1799 if (link_speeds & ETH_LINK_SPEED_1G)
1800 link_speed |= I40E_LINK_SPEED_1GB;
1801 if (link_speeds & ETH_LINK_SPEED_100M)
1802 link_speed |= I40E_LINK_SPEED_100MB;
1808 i40e_phy_conf_link(struct i40e_hw *hw,
1810 uint8_t force_speed)
1812 enum i40e_status_code status;
1813 struct i40e_aq_get_phy_abilities_resp phy_ab;
1814 struct i40e_aq_set_phy_config phy_conf;
1815 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1816 I40E_AQ_PHY_FLAG_PAUSE_RX |
1817 I40E_AQ_PHY_FLAG_PAUSE_RX |
1818 I40E_AQ_PHY_FLAG_LOW_POWER;
1819 const uint8_t advt = I40E_LINK_SPEED_40GB |
1820 I40E_LINK_SPEED_25GB |
1821 I40E_LINK_SPEED_10GB |
1822 I40E_LINK_SPEED_1GB |
1823 I40E_LINK_SPEED_100MB;
1827 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1832 memset(&phy_conf, 0, sizeof(phy_conf));
1834 /* bits 0-2 use the values from get_phy_abilities_resp */
1836 abilities |= phy_ab.abilities & mask;
1838 /* update ablities and speed */
1839 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1840 phy_conf.link_speed = advt;
1842 phy_conf.link_speed = force_speed;
1844 phy_conf.abilities = abilities;
1846 /* use get_phy_abilities_resp value for the rest */
1847 phy_conf.phy_type = phy_ab.phy_type;
1848 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1849 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1850 phy_conf.eee_capability = phy_ab.eee_capability;
1851 phy_conf.eeer = phy_ab.eeer_val;
1852 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1854 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1855 phy_ab.abilities, phy_ab.link_speed);
1856 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1857 phy_conf.abilities, phy_conf.link_speed);
1859 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1863 return I40E_SUCCESS;
1867 i40e_apply_link_speed(struct rte_eth_dev *dev)
1870 uint8_t abilities = 0;
1871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872 struct rte_eth_conf *conf = &dev->data->dev_conf;
1874 speed = i40e_parse_link_speeds(conf->link_speeds);
1875 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1876 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1877 abilities |= I40E_AQ_PHY_AN_ENABLED;
1878 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1880 /* Skip changing speed on 40G interfaces, FW does not support */
1881 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1882 speed = I40E_LINK_SPEED_UNKNOWN;
1883 abilities |= I40E_AQ_PHY_AN_ENABLED;
1886 return i40e_phy_conf_link(hw, abilities, speed);
1890 i40e_dev_start(struct rte_eth_dev *dev)
1892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1894 struct i40e_vsi *main_vsi = pf->main_vsi;
1896 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1897 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1898 uint32_t intr_vector = 0;
1899 struct i40e_vsi *vsi;
1901 hw->adapter_stopped = 0;
1903 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1904 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1905 dev->data->port_id);
1909 rte_intr_disable(intr_handle);
1911 if ((rte_intr_cap_multiple(intr_handle) ||
1912 !RTE_ETH_DEV_SRIOV(dev).active) &&
1913 dev->data->dev_conf.intr_conf.rxq != 0) {
1914 intr_vector = dev->data->nb_rx_queues;
1915 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1920 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1921 intr_handle->intr_vec =
1922 rte_zmalloc("intr_vec",
1923 dev->data->nb_rx_queues * sizeof(int),
1925 if (!intr_handle->intr_vec) {
1927 "Failed to allocate %d rx_queues intr_vec",
1928 dev->data->nb_rx_queues);
1933 /* Initialize VSI */
1934 ret = i40e_dev_rxtx_init(pf);
1935 if (ret != I40E_SUCCESS) {
1936 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1940 /* Map queues with MSIX interrupt */
1941 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1942 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1943 i40e_vsi_queues_bind_intr(main_vsi);
1944 i40e_vsi_enable_queues_intr(main_vsi);
1946 /* Map VMDQ VSI queues with MSIX interrupt */
1947 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1948 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1949 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1950 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1953 /* enable FDIR MSIX interrupt */
1954 if (pf->fdir.fdir_vsi) {
1955 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1956 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1959 /* Enable all queues which have been configured */
1960 ret = i40e_dev_switch_queues(pf, TRUE);
1961 if (ret != I40E_SUCCESS) {
1962 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1966 /* Enable receiving broadcast packets */
1967 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1968 if (ret != I40E_SUCCESS)
1969 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1971 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1972 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1974 if (ret != I40E_SUCCESS)
1975 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1978 /* Enable the VLAN promiscuous mode. */
1980 for (i = 0; i < pf->vf_num; i++) {
1981 vsi = pf->vfs[i].vsi;
1982 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1987 /* Apply link configure */
1988 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1989 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1990 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1991 ETH_LINK_SPEED_40G)) {
1992 PMD_DRV_LOG(ERR, "Invalid link setting");
1995 ret = i40e_apply_link_speed(dev);
1996 if (I40E_SUCCESS != ret) {
1997 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2001 if (!rte_intr_allow_others(intr_handle)) {
2002 rte_intr_callback_unregister(intr_handle,
2003 i40e_dev_interrupt_handler,
2005 /* configure and enable device interrupt */
2006 i40e_pf_config_irq0(hw, FALSE);
2007 i40e_pf_enable_irq0(hw);
2009 if (dev->data->dev_conf.intr_conf.lsc != 0)
2011 "lsc won't enable because of no intr multiplex");
2012 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2013 ret = i40e_aq_set_phy_int_mask(hw,
2014 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2015 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2016 I40E_AQ_EVENT_MEDIA_NA), NULL);
2017 if (ret != I40E_SUCCESS)
2018 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2020 /* Call get_link_info aq commond to enable LSE */
2021 i40e_dev_link_update(dev, 0);
2024 /* enable uio intr after callback register */
2025 rte_intr_enable(intr_handle);
2027 i40e_filter_restore(pf);
2029 return I40E_SUCCESS;
2032 i40e_dev_switch_queues(pf, FALSE);
2033 i40e_dev_clear_queues(dev);
2039 i40e_dev_stop(struct rte_eth_dev *dev)
2041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2042 struct i40e_vsi *main_vsi = pf->main_vsi;
2043 struct i40e_mirror_rule *p_mirror;
2044 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2045 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2048 /* Disable all queues */
2049 i40e_dev_switch_queues(pf, FALSE);
2051 /* un-map queues with interrupt registers */
2052 i40e_vsi_disable_queues_intr(main_vsi);
2053 i40e_vsi_queues_unbind_intr(main_vsi);
2055 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2056 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2057 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2060 if (pf->fdir.fdir_vsi) {
2061 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2062 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2064 /* Clear all queues and release memory */
2065 i40e_dev_clear_queues(dev);
2068 i40e_dev_set_link_down(dev);
2070 /* Remove all mirror rules */
2071 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2072 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2075 pf->nb_mirror_rule = 0;
2077 if (!rte_intr_allow_others(intr_handle))
2078 /* resume to the default handler */
2079 rte_intr_callback_register(intr_handle,
2080 i40e_dev_interrupt_handler,
2083 /* Clean datapath event and queue/vec mapping */
2084 rte_intr_efd_disable(intr_handle);
2085 if (intr_handle->intr_vec) {
2086 rte_free(intr_handle->intr_vec);
2087 intr_handle->intr_vec = NULL;
2092 i40e_dev_close(struct rte_eth_dev *dev)
2094 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2095 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2097 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2101 PMD_INIT_FUNC_TRACE();
2104 hw->adapter_stopped = 1;
2105 i40e_dev_free_queues(dev);
2107 /* Disable interrupt */
2108 i40e_pf_disable_irq0(hw);
2109 rte_intr_disable(intr_handle);
2111 /* shutdown and destroy the HMC */
2112 i40e_shutdown_lan_hmc(hw);
2114 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2115 i40e_vsi_release(pf->vmdq[i].vsi);
2116 pf->vmdq[i].vsi = NULL;
2121 /* release all the existing VSIs and VEBs */
2122 i40e_fdir_teardown(pf);
2123 i40e_vsi_release(pf->main_vsi);
2125 /* shutdown the adminq */
2126 i40e_aq_queue_shutdown(hw, true);
2127 i40e_shutdown_adminq(hw);
2129 i40e_res_pool_destroy(&pf->qp_pool);
2130 i40e_res_pool_destroy(&pf->msix_pool);
2132 /* force a PF reset to clean anything leftover */
2133 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2134 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2135 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2136 I40E_WRITE_FLUSH(hw);
2140 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2142 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2143 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2144 struct i40e_vsi *vsi = pf->main_vsi;
2147 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2149 if (status != I40E_SUCCESS)
2150 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2152 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2154 if (status != I40E_SUCCESS)
2155 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2160 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2162 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2163 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 struct i40e_vsi *vsi = pf->main_vsi;
2167 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2169 if (status != I40E_SUCCESS)
2170 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2172 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2174 if (status != I40E_SUCCESS)
2175 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2179 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2181 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183 struct i40e_vsi *vsi = pf->main_vsi;
2186 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2187 if (ret != I40E_SUCCESS)
2188 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2192 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2194 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2195 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196 struct i40e_vsi *vsi = pf->main_vsi;
2199 if (dev->data->promiscuous == 1)
2200 return; /* must remain in all_multicast mode */
2202 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2203 vsi->seid, FALSE, NULL);
2204 if (ret != I40E_SUCCESS)
2205 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2209 * Set device link up.
2212 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2214 /* re-apply link speed setting */
2215 return i40e_apply_link_speed(dev);
2219 * Set device link down.
2222 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2224 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2225 uint8_t abilities = 0;
2226 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2228 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2229 return i40e_phy_conf_link(hw, abilities, speed);
2233 i40e_dev_link_update(struct rte_eth_dev *dev,
2234 int wait_to_complete)
2236 #define CHECK_INTERVAL 100 /* 100ms */
2237 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 struct i40e_link_status link_status;
2240 struct rte_eth_link link, old;
2242 unsigned rep_cnt = MAX_REPEAT_TIME;
2243 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2245 memset(&link, 0, sizeof(link));
2246 memset(&old, 0, sizeof(old));
2247 memset(&link_status, 0, sizeof(link_status));
2248 rte_i40e_dev_atomic_read_link_status(dev, &old);
2251 /* Get link status information from hardware */
2252 status = i40e_aq_get_link_info(hw, enable_lse,
2253 &link_status, NULL);
2254 if (status != I40E_SUCCESS) {
2255 link.link_speed = ETH_SPEED_NUM_100M;
2256 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2257 PMD_DRV_LOG(ERR, "Failed to get link info");
2261 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2262 if (!wait_to_complete || link.link_status)
2265 rte_delay_ms(CHECK_INTERVAL);
2266 } while (--rep_cnt);
2268 if (!link.link_status)
2271 /* i40e uses full duplex only */
2272 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2274 /* Parse the link status */
2275 switch (link_status.link_speed) {
2276 case I40E_LINK_SPEED_100MB:
2277 link.link_speed = ETH_SPEED_NUM_100M;
2279 case I40E_LINK_SPEED_1GB:
2280 link.link_speed = ETH_SPEED_NUM_1G;
2282 case I40E_LINK_SPEED_10GB:
2283 link.link_speed = ETH_SPEED_NUM_10G;
2285 case I40E_LINK_SPEED_20GB:
2286 link.link_speed = ETH_SPEED_NUM_20G;
2288 case I40E_LINK_SPEED_25GB:
2289 link.link_speed = ETH_SPEED_NUM_25G;
2291 case I40E_LINK_SPEED_40GB:
2292 link.link_speed = ETH_SPEED_NUM_40G;
2295 link.link_speed = ETH_SPEED_NUM_100M;
2299 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2300 ETH_LINK_SPEED_FIXED);
2303 rte_i40e_dev_atomic_write_link_status(dev, &link);
2304 if (link.link_status == old.link_status)
2307 i40e_notify_all_vfs_link_status(dev);
2312 /* Get all the statistics of a VSI */
2314 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2316 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2317 struct i40e_eth_stats *nes = &vsi->eth_stats;
2318 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2319 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2321 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2322 vsi->offset_loaded, &oes->rx_bytes,
2324 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2325 vsi->offset_loaded, &oes->rx_unicast,
2327 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2328 vsi->offset_loaded, &oes->rx_multicast,
2329 &nes->rx_multicast);
2330 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2331 vsi->offset_loaded, &oes->rx_broadcast,
2332 &nes->rx_broadcast);
2333 /* exclude CRC bytes */
2334 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2335 nes->rx_broadcast) * ETHER_CRC_LEN;
2337 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2338 &oes->rx_discards, &nes->rx_discards);
2339 /* GLV_REPC not supported */
2340 /* GLV_RMPC not supported */
2341 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2342 &oes->rx_unknown_protocol,
2343 &nes->rx_unknown_protocol);
2344 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2345 vsi->offset_loaded, &oes->tx_bytes,
2347 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2348 vsi->offset_loaded, &oes->tx_unicast,
2350 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2351 vsi->offset_loaded, &oes->tx_multicast,
2352 &nes->tx_multicast);
2353 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2354 vsi->offset_loaded, &oes->tx_broadcast,
2355 &nes->tx_broadcast);
2356 /* exclude CRC bytes */
2357 nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2358 nes->tx_broadcast) * ETHER_CRC_LEN;
2359 /* GLV_TDPC not supported */
2360 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2361 &oes->tx_errors, &nes->tx_errors);
2362 vsi->offset_loaded = true;
2364 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2366 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2367 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2368 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2369 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2370 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2371 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2372 nes->rx_unknown_protocol);
2373 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2374 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2375 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2376 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2377 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2378 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2379 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2384 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2387 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2388 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2390 /* Get rx/tx bytes of internal transfer packets */
2391 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2392 I40E_GLV_GORCL(hw->port),
2394 &pf->internal_stats_offset.rx_bytes,
2395 &pf->internal_stats.rx_bytes);
2397 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2398 I40E_GLV_GOTCL(hw->port),
2400 &pf->internal_stats_offset.tx_bytes,
2401 &pf->internal_stats.tx_bytes);
2402 /* Get total internal rx packet count */
2403 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2404 I40E_GLV_UPRCL(hw->port),
2406 &pf->internal_stats_offset.rx_unicast,
2407 &pf->internal_stats.rx_unicast);
2408 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2409 I40E_GLV_MPRCL(hw->port),
2411 &pf->internal_stats_offset.rx_multicast,
2412 &pf->internal_stats.rx_multicast);
2413 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2414 I40E_GLV_BPRCL(hw->port),
2416 &pf->internal_stats_offset.rx_broadcast,
2417 &pf->internal_stats.rx_broadcast);
2419 /* exclude CRC size */
2420 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2421 pf->internal_stats.rx_multicast +
2422 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2424 /* Get statistics of struct i40e_eth_stats */
2425 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2426 I40E_GLPRT_GORCL(hw->port),
2427 pf->offset_loaded, &os->eth.rx_bytes,
2429 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2430 I40E_GLPRT_UPRCL(hw->port),
2431 pf->offset_loaded, &os->eth.rx_unicast,
2432 &ns->eth.rx_unicast);
2433 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2434 I40E_GLPRT_MPRCL(hw->port),
2435 pf->offset_loaded, &os->eth.rx_multicast,
2436 &ns->eth.rx_multicast);
2437 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2438 I40E_GLPRT_BPRCL(hw->port),
2439 pf->offset_loaded, &os->eth.rx_broadcast,
2440 &ns->eth.rx_broadcast);
2441 /* Workaround: CRC size should not be included in byte statistics,
2442 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2444 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2445 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2447 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2448 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2451 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2452 ns->eth.rx_bytes = 0;
2453 /* exlude internal rx bytes */
2455 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2457 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2458 pf->offset_loaded, &os->eth.rx_discards,
2459 &ns->eth.rx_discards);
2460 /* GLPRT_REPC not supported */
2461 /* GLPRT_RMPC not supported */
2462 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2464 &os->eth.rx_unknown_protocol,
2465 &ns->eth.rx_unknown_protocol);
2466 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2467 I40E_GLPRT_GOTCL(hw->port),
2468 pf->offset_loaded, &os->eth.tx_bytes,
2470 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2471 I40E_GLPRT_UPTCL(hw->port),
2472 pf->offset_loaded, &os->eth.tx_unicast,
2473 &ns->eth.tx_unicast);
2474 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2475 I40E_GLPRT_MPTCL(hw->port),
2476 pf->offset_loaded, &os->eth.tx_multicast,
2477 &ns->eth.tx_multicast);
2478 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2479 I40E_GLPRT_BPTCL(hw->port),
2480 pf->offset_loaded, &os->eth.tx_broadcast,
2481 &ns->eth.tx_broadcast);
2482 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2483 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2485 /* exclude internal tx bytes */
2486 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2487 ns->eth.tx_bytes = 0;
2489 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2491 /* GLPRT_TEPC not supported */
2493 /* additional port specific stats */
2494 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2495 pf->offset_loaded, &os->tx_dropped_link_down,
2496 &ns->tx_dropped_link_down);
2497 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2498 pf->offset_loaded, &os->crc_errors,
2500 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2501 pf->offset_loaded, &os->illegal_bytes,
2502 &ns->illegal_bytes);
2503 /* GLPRT_ERRBC not supported */
2504 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2505 pf->offset_loaded, &os->mac_local_faults,
2506 &ns->mac_local_faults);
2507 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2508 pf->offset_loaded, &os->mac_remote_faults,
2509 &ns->mac_remote_faults);
2510 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2511 pf->offset_loaded, &os->rx_length_errors,
2512 &ns->rx_length_errors);
2513 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2514 pf->offset_loaded, &os->link_xon_rx,
2516 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2517 pf->offset_loaded, &os->link_xoff_rx,
2519 for (i = 0; i < 8; i++) {
2520 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2522 &os->priority_xon_rx[i],
2523 &ns->priority_xon_rx[i]);
2524 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2526 &os->priority_xoff_rx[i],
2527 &ns->priority_xoff_rx[i]);
2529 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2530 pf->offset_loaded, &os->link_xon_tx,
2532 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2533 pf->offset_loaded, &os->link_xoff_tx,
2535 for (i = 0; i < 8; i++) {
2536 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2538 &os->priority_xon_tx[i],
2539 &ns->priority_xon_tx[i]);
2540 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2542 &os->priority_xoff_tx[i],
2543 &ns->priority_xoff_tx[i]);
2544 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2546 &os->priority_xon_2_xoff[i],
2547 &ns->priority_xon_2_xoff[i]);
2549 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2550 I40E_GLPRT_PRC64L(hw->port),
2551 pf->offset_loaded, &os->rx_size_64,
2553 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2554 I40E_GLPRT_PRC127L(hw->port),
2555 pf->offset_loaded, &os->rx_size_127,
2557 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2558 I40E_GLPRT_PRC255L(hw->port),
2559 pf->offset_loaded, &os->rx_size_255,
2561 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2562 I40E_GLPRT_PRC511L(hw->port),
2563 pf->offset_loaded, &os->rx_size_511,
2565 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2566 I40E_GLPRT_PRC1023L(hw->port),
2567 pf->offset_loaded, &os->rx_size_1023,
2569 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2570 I40E_GLPRT_PRC1522L(hw->port),
2571 pf->offset_loaded, &os->rx_size_1522,
2573 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2574 I40E_GLPRT_PRC9522L(hw->port),
2575 pf->offset_loaded, &os->rx_size_big,
2577 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2578 pf->offset_loaded, &os->rx_undersize,
2580 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2581 pf->offset_loaded, &os->rx_fragments,
2583 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2584 pf->offset_loaded, &os->rx_oversize,
2586 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2587 pf->offset_loaded, &os->rx_jabber,
2589 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2590 I40E_GLPRT_PTC64L(hw->port),
2591 pf->offset_loaded, &os->tx_size_64,
2593 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2594 I40E_GLPRT_PTC127L(hw->port),
2595 pf->offset_loaded, &os->tx_size_127,
2597 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2598 I40E_GLPRT_PTC255L(hw->port),
2599 pf->offset_loaded, &os->tx_size_255,
2601 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2602 I40E_GLPRT_PTC511L(hw->port),
2603 pf->offset_loaded, &os->tx_size_511,
2605 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2606 I40E_GLPRT_PTC1023L(hw->port),
2607 pf->offset_loaded, &os->tx_size_1023,
2609 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2610 I40E_GLPRT_PTC1522L(hw->port),
2611 pf->offset_loaded, &os->tx_size_1522,
2613 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2614 I40E_GLPRT_PTC9522L(hw->port),
2615 pf->offset_loaded, &os->tx_size_big,
2617 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2619 &os->fd_sb_match, &ns->fd_sb_match);
2620 /* GLPRT_MSPDC not supported */
2621 /* GLPRT_XEC not supported */
2623 pf->offset_loaded = true;
2626 i40e_update_vsi_stats(pf->main_vsi);
2629 /* Get all statistics of a port */
2631 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2633 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2635 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2638 /* call read registers - updates values, now write them to struct */
2639 i40e_read_stats_registers(pf, hw);
2641 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2642 pf->main_vsi->eth_stats.rx_multicast +
2643 pf->main_vsi->eth_stats.rx_broadcast -
2644 pf->main_vsi->eth_stats.rx_discards;
2645 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2646 pf->main_vsi->eth_stats.tx_multicast +
2647 pf->main_vsi->eth_stats.tx_broadcast;
2648 stats->ibytes = ns->eth.rx_bytes;
2649 stats->obytes = ns->eth.tx_bytes;
2650 stats->oerrors = ns->eth.tx_errors +
2651 pf->main_vsi->eth_stats.tx_errors;
2654 stats->imissed = ns->eth.rx_discards +
2655 pf->main_vsi->eth_stats.rx_discards;
2656 stats->ierrors = ns->crc_errors +
2657 ns->rx_length_errors + ns->rx_undersize +
2658 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2660 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2661 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2662 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2663 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2664 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2665 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2666 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2667 ns->eth.rx_unknown_protocol);
2668 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2669 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2670 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2671 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2672 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2673 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2675 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2676 ns->tx_dropped_link_down);
2677 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2678 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2680 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2681 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2682 ns->mac_local_faults);
2683 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2684 ns->mac_remote_faults);
2685 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2686 ns->rx_length_errors);
2687 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2688 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2689 for (i = 0; i < 8; i++) {
2690 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2691 i, ns->priority_xon_rx[i]);
2692 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2693 i, ns->priority_xoff_rx[i]);
2695 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2696 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2697 for (i = 0; i < 8; i++) {
2698 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2699 i, ns->priority_xon_tx[i]);
2700 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2701 i, ns->priority_xoff_tx[i]);
2702 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2703 i, ns->priority_xon_2_xoff[i]);
2705 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2706 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2707 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2708 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2709 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2710 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2711 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2712 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2713 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2714 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2715 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2716 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2717 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2718 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2719 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2720 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2721 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2722 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2723 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2724 ns->mac_short_packet_dropped);
2725 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2726 ns->checksum_error);
2727 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2728 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2731 /* Reset the statistics */
2733 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2735 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2736 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738 /* Mark PF and VSI stats to update the offset, aka "reset" */
2739 pf->offset_loaded = false;
2741 pf->main_vsi->offset_loaded = false;
2743 /* read the stats, reading current register values into offset */
2744 i40e_read_stats_registers(pf, hw);
2748 i40e_xstats_calc_num(void)
2750 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2751 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2752 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2755 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2756 struct rte_eth_xstat_name *xstats_names,
2757 __rte_unused unsigned limit)
2762 if (xstats_names == NULL)
2763 return i40e_xstats_calc_num();
2765 /* Note: limit checked in rte_eth_xstats_names() */
2767 /* Get stats from i40e_eth_stats struct */
2768 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2769 snprintf(xstats_names[count].name,
2770 sizeof(xstats_names[count].name),
2771 "%s", rte_i40e_stats_strings[i].name);
2775 /* Get individiual stats from i40e_hw_port struct */
2776 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2777 snprintf(xstats_names[count].name,
2778 sizeof(xstats_names[count].name),
2779 "%s", rte_i40e_hw_port_strings[i].name);
2783 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2784 for (prio = 0; prio < 8; prio++) {
2785 snprintf(xstats_names[count].name,
2786 sizeof(xstats_names[count].name),
2787 "rx_priority%u_%s", prio,
2788 rte_i40e_rxq_prio_strings[i].name);
2793 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2794 for (prio = 0; prio < 8; prio++) {
2795 snprintf(xstats_names[count].name,
2796 sizeof(xstats_names[count].name),
2797 "tx_priority%u_%s", prio,
2798 rte_i40e_txq_prio_strings[i].name);
2806 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2809 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2810 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811 unsigned i, count, prio;
2812 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2814 count = i40e_xstats_calc_num();
2818 i40e_read_stats_registers(pf, hw);
2825 /* Get stats from i40e_eth_stats struct */
2826 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2827 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2828 rte_i40e_stats_strings[i].offset);
2829 xstats[count].id = count;
2833 /* Get individiual stats from i40e_hw_port struct */
2834 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2835 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2836 rte_i40e_hw_port_strings[i].offset);
2837 xstats[count].id = count;
2841 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2842 for (prio = 0; prio < 8; prio++) {
2843 xstats[count].value =
2844 *(uint64_t *)(((char *)hw_stats) +
2845 rte_i40e_rxq_prio_strings[i].offset +
2846 (sizeof(uint64_t) * prio));
2847 xstats[count].id = count;
2852 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2853 for (prio = 0; prio < 8; prio++) {
2854 xstats[count].value =
2855 *(uint64_t *)(((char *)hw_stats) +
2856 rte_i40e_txq_prio_strings[i].offset +
2857 (sizeof(uint64_t) * prio));
2858 xstats[count].id = count;
2867 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2868 __rte_unused uint16_t queue_id,
2869 __rte_unused uint8_t stat_idx,
2870 __rte_unused uint8_t is_rx)
2872 PMD_INIT_FUNC_TRACE();
2878 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2880 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2886 full_ver = hw->nvm.oem_ver;
2887 ver = (u8)(full_ver >> 24);
2888 build = (u16)((full_ver >> 8) & 0xffff);
2889 patch = (u8)(full_ver & 0xff);
2891 ret = snprintf(fw_version, fw_size,
2892 "%d.%d%d 0x%08x %d.%d.%d",
2893 ((hw->nvm.version >> 12) & 0xf),
2894 ((hw->nvm.version >> 4) & 0xff),
2895 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2898 ret += 1; /* add the size of '\0' */
2899 if (fw_size < (u32)ret)
2906 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910 struct i40e_vsi *vsi = pf->main_vsi;
2911 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2913 dev_info->pci_dev = pci_dev;
2914 dev_info->max_rx_queues = vsi->nb_qps;
2915 dev_info->max_tx_queues = vsi->nb_qps;
2916 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2917 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2918 dev_info->max_mac_addrs = vsi->max_macaddrs;
2919 dev_info->max_vfs = pci_dev->max_vfs;
2920 dev_info->rx_offload_capa =
2921 DEV_RX_OFFLOAD_VLAN_STRIP |
2922 DEV_RX_OFFLOAD_QINQ_STRIP |
2923 DEV_RX_OFFLOAD_IPV4_CKSUM |
2924 DEV_RX_OFFLOAD_UDP_CKSUM |
2925 DEV_RX_OFFLOAD_TCP_CKSUM;
2926 dev_info->tx_offload_capa =
2927 DEV_TX_OFFLOAD_VLAN_INSERT |
2928 DEV_TX_OFFLOAD_QINQ_INSERT |
2929 DEV_TX_OFFLOAD_IPV4_CKSUM |
2930 DEV_TX_OFFLOAD_UDP_CKSUM |
2931 DEV_TX_OFFLOAD_TCP_CKSUM |
2932 DEV_TX_OFFLOAD_SCTP_CKSUM |
2933 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2934 DEV_TX_OFFLOAD_TCP_TSO |
2935 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2936 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2937 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2938 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2939 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2941 dev_info->reta_size = pf->hash_lut_size;
2942 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2944 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2946 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2947 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2948 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2950 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2954 dev_info->default_txconf = (struct rte_eth_txconf) {
2956 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2957 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2958 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2960 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2961 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2962 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2963 ETH_TXQ_FLAGS_NOOFFLOADS,
2966 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2967 .nb_max = I40E_MAX_RING_DESC,
2968 .nb_min = I40E_MIN_RING_DESC,
2969 .nb_align = I40E_ALIGN_RING_DESC,
2972 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2973 .nb_max = I40E_MAX_RING_DESC,
2974 .nb_min = I40E_MIN_RING_DESC,
2975 .nb_align = I40E_ALIGN_RING_DESC,
2976 .nb_seg_max = I40E_TX_MAX_SEG,
2977 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2980 if (pf->flags & I40E_FLAG_VMDQ) {
2981 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2982 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2983 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2984 pf->max_nb_vmdq_vsi;
2985 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2986 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2987 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2990 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2992 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2993 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2995 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2998 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3002 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3004 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3005 struct i40e_vsi *vsi = pf->main_vsi;
3006 PMD_INIT_FUNC_TRACE();
3009 return i40e_vsi_add_vlan(vsi, vlan_id);
3011 return i40e_vsi_delete_vlan(vsi, vlan_id);
3015 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3016 enum rte_vlan_type vlan_type,
3017 uint16_t tpid, int qinq)
3019 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3022 uint16_t reg_id = 3;
3026 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3030 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3032 if (ret != I40E_SUCCESS) {
3034 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3039 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3042 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3043 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3044 if (reg_r == reg_w) {
3045 PMD_DRV_LOG(DEBUG, "No need to write");
3049 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3051 if (ret != I40E_SUCCESS) {
3053 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3058 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3065 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3066 enum rte_vlan_type vlan_type,
3069 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3070 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3073 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3074 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3075 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3077 "Unsupported vlan type.");
3080 /* 802.1ad frames ability is added in NVM API 1.7*/
3081 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3083 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3084 hw->first_tag = rte_cpu_to_le_16(tpid);
3085 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3086 hw->second_tag = rte_cpu_to_le_16(tpid);
3088 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3089 hw->second_tag = rte_cpu_to_le_16(tpid);
3091 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3092 if (ret != I40E_SUCCESS) {
3094 "Set switch config failed aq_err: %d",
3095 hw->aq.asq_last_status);
3099 /* If NVM API < 1.7, keep the register setting */
3100 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3107 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3109 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3110 struct i40e_vsi *vsi = pf->main_vsi;
3112 if (mask & ETH_VLAN_FILTER_MASK) {
3113 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3114 i40e_vsi_config_vlan_filter(vsi, TRUE);
3116 i40e_vsi_config_vlan_filter(vsi, FALSE);
3119 if (mask & ETH_VLAN_STRIP_MASK) {
3120 /* Enable or disable VLAN stripping */
3121 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3122 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3124 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3127 if (mask & ETH_VLAN_EXTEND_MASK) {
3128 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3129 i40e_vsi_config_double_vlan(vsi, TRUE);
3130 /* Set global registers with default ethertype. */
3131 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3133 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3137 i40e_vsi_config_double_vlan(vsi, FALSE);
3142 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3143 __rte_unused uint16_t queue,
3144 __rte_unused int on)
3146 PMD_INIT_FUNC_TRACE();
3150 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3152 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3153 struct i40e_vsi *vsi = pf->main_vsi;
3154 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3155 struct i40e_vsi_vlan_pvid_info info;
3157 memset(&info, 0, sizeof(info));
3160 info.config.pvid = pvid;
3162 info.config.reject.tagged =
3163 data->dev_conf.txmode.hw_vlan_reject_tagged;
3164 info.config.reject.untagged =
3165 data->dev_conf.txmode.hw_vlan_reject_untagged;
3168 return i40e_vsi_vlan_pvid_set(vsi, &info);
3172 i40e_dev_led_on(struct rte_eth_dev *dev)
3174 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3175 uint32_t mode = i40e_led_get(hw);
3178 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3184 i40e_dev_led_off(struct rte_eth_dev *dev)
3186 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3187 uint32_t mode = i40e_led_get(hw);
3190 i40e_led_set(hw, 0, false);
3196 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3198 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3199 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3201 fc_conf->pause_time = pf->fc_conf.pause_time;
3202 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3203 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3205 /* Return current mode according to actual setting*/
3206 switch (hw->fc.current_mode) {
3208 fc_conf->mode = RTE_FC_FULL;
3210 case I40E_FC_TX_PAUSE:
3211 fc_conf->mode = RTE_FC_TX_PAUSE;
3213 case I40E_FC_RX_PAUSE:
3214 fc_conf->mode = RTE_FC_RX_PAUSE;
3218 fc_conf->mode = RTE_FC_NONE;
3225 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3227 uint32_t mflcn_reg, fctrl_reg, reg;
3228 uint32_t max_high_water;
3229 uint8_t i, aq_failure;
3233 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3234 [RTE_FC_NONE] = I40E_FC_NONE,
3235 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3236 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3237 [RTE_FC_FULL] = I40E_FC_FULL
3240 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3242 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3243 if ((fc_conf->high_water > max_high_water) ||
3244 (fc_conf->high_water < fc_conf->low_water)) {
3246 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3251 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3252 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3253 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3255 pf->fc_conf.pause_time = fc_conf->pause_time;
3256 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3257 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3259 PMD_INIT_FUNC_TRACE();
3261 /* All the link flow control related enable/disable register
3262 * configuration is handle by the F/W
3264 err = i40e_set_fc(hw, &aq_failure, true);
3268 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3269 /* Configure flow control refresh threshold,
3270 * the value for stat_tx_pause_refresh_timer[8]
3271 * is used for global pause operation.
3275 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3276 pf->fc_conf.pause_time);
3278 /* configure the timer value included in transmitted pause
3280 * the value for stat_tx_pause_quanta[8] is used for global
3283 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3284 pf->fc_conf.pause_time);
3286 fctrl_reg = I40E_READ_REG(hw,
3287 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3289 if (fc_conf->mac_ctrl_frame_fwd != 0)
3290 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3292 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3294 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3297 /* Configure pause time (2 TCs per register) */
3298 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3299 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3300 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3302 /* Configure flow control refresh threshold value */
3303 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3304 pf->fc_conf.pause_time / 2);
3306 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3308 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3309 *depending on configuration
3311 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3312 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3313 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3315 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3316 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3319 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3322 /* config the water marker both based on the packets and bytes */
3323 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3324 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3325 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3326 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3327 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3328 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3329 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3330 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3332 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3333 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3336 I40E_WRITE_FLUSH(hw);
3342 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3343 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3345 PMD_INIT_FUNC_TRACE();
3350 /* Add a MAC address, and update filters */
3352 i40e_macaddr_add(struct rte_eth_dev *dev,
3353 struct ether_addr *mac_addr,
3354 __rte_unused uint32_t index,
3357 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3358 struct i40e_mac_filter_info mac_filter;
3359 struct i40e_vsi *vsi;
3362 /* If VMDQ not enabled or configured, return */
3363 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3364 !pf->nb_cfg_vmdq_vsi)) {
3365 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3366 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3371 if (pool > pf->nb_cfg_vmdq_vsi) {
3372 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3373 pool, pf->nb_cfg_vmdq_vsi);
3377 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3378 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3379 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3381 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3386 vsi = pf->vmdq[pool - 1].vsi;
3388 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3389 if (ret != I40E_SUCCESS) {
3390 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3396 /* Remove a MAC address, and update filters */
3398 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3400 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3401 struct i40e_vsi *vsi;
3402 struct rte_eth_dev_data *data = dev->data;
3403 struct ether_addr *macaddr;
3408 macaddr = &(data->mac_addrs[index]);
3410 pool_sel = dev->data->mac_pool_sel[index];
3412 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3413 if (pool_sel & (1ULL << i)) {
3417 /* No VMDQ pool enabled or configured */
3418 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3419 (i > pf->nb_cfg_vmdq_vsi)) {
3421 "No VMDQ pool enabled/configured");
3424 vsi = pf->vmdq[i - 1].vsi;
3426 ret = i40e_vsi_delete_mac(vsi, macaddr);
3429 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3436 /* Set perfect match or hash match of MAC and VLAN for a VF */
3438 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3439 struct rte_eth_mac_filter *filter,
3443 struct i40e_mac_filter_info mac_filter;
3444 struct ether_addr old_mac;
3445 struct ether_addr *new_mac;
3446 struct i40e_pf_vf *vf = NULL;
3451 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3454 hw = I40E_PF_TO_HW(pf);
3456 if (filter == NULL) {
3457 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3461 new_mac = &filter->mac_addr;
3463 if (is_zero_ether_addr(new_mac)) {
3464 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3468 vf_id = filter->dst_id;
3470 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3471 PMD_DRV_LOG(ERR, "Invalid argument.");
3474 vf = &pf->vfs[vf_id];
3476 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3477 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3482 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3483 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3485 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3488 mac_filter.filter_type = filter->filter_type;
3489 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3490 if (ret != I40E_SUCCESS) {
3491 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3494 ether_addr_copy(new_mac, &pf->dev_addr);
3496 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3498 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3499 if (ret != I40E_SUCCESS) {
3500 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3504 /* Clear device address as it has been removed */
3505 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3506 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3512 /* MAC filter handle */
3514 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3517 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3518 struct rte_eth_mac_filter *filter;
3519 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3520 int ret = I40E_NOT_SUPPORTED;
3522 filter = (struct rte_eth_mac_filter *)(arg);
3524 switch (filter_op) {
3525 case RTE_ETH_FILTER_NOP:
3528 case RTE_ETH_FILTER_ADD:
3529 i40e_pf_disable_irq0(hw);
3531 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3532 i40e_pf_enable_irq0(hw);
3534 case RTE_ETH_FILTER_DELETE:
3535 i40e_pf_disable_irq0(hw);
3537 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3538 i40e_pf_enable_irq0(hw);
3541 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3542 ret = I40E_ERR_PARAM;
3550 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3552 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3553 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3559 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3560 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3563 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3567 uint32_t *lut_dw = (uint32_t *)lut;
3568 uint16_t i, lut_size_dw = lut_size / 4;
3570 for (i = 0; i < lut_size_dw; i++)
3571 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3578 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3587 pf = I40E_VSI_TO_PF(vsi);
3588 hw = I40E_VSI_TO_HW(vsi);
3590 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3591 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3594 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3598 uint32_t *lut_dw = (uint32_t *)lut;
3599 uint16_t i, lut_size_dw = lut_size / 4;
3601 for (i = 0; i < lut_size_dw; i++)
3602 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3603 I40E_WRITE_FLUSH(hw);
3610 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3611 struct rte_eth_rss_reta_entry64 *reta_conf,
3614 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3615 uint16_t i, lut_size = pf->hash_lut_size;
3616 uint16_t idx, shift;
3620 if (reta_size != lut_size ||
3621 reta_size > ETH_RSS_RETA_SIZE_512) {
3623 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3624 reta_size, lut_size);
3628 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3630 PMD_DRV_LOG(ERR, "No memory can be allocated");
3633 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3636 for (i = 0; i < reta_size; i++) {
3637 idx = i / RTE_RETA_GROUP_SIZE;
3638 shift = i % RTE_RETA_GROUP_SIZE;
3639 if (reta_conf[idx].mask & (1ULL << shift))
3640 lut[i] = reta_conf[idx].reta[shift];
3642 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3651 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3652 struct rte_eth_rss_reta_entry64 *reta_conf,
3655 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3656 uint16_t i, lut_size = pf->hash_lut_size;
3657 uint16_t idx, shift;
3661 if (reta_size != lut_size ||
3662 reta_size > ETH_RSS_RETA_SIZE_512) {
3664 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3665 reta_size, lut_size);
3669 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3671 PMD_DRV_LOG(ERR, "No memory can be allocated");
3675 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3678 for (i = 0; i < reta_size; i++) {
3679 idx = i / RTE_RETA_GROUP_SIZE;
3680 shift = i % RTE_RETA_GROUP_SIZE;
3681 if (reta_conf[idx].mask & (1ULL << shift))
3682 reta_conf[idx].reta[shift] = lut[i];
3692 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3693 * @hw: pointer to the HW structure
3694 * @mem: pointer to mem struct to fill out
3695 * @size: size of memory requested
3696 * @alignment: what to align the allocation to
3698 enum i40e_status_code
3699 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3700 struct i40e_dma_mem *mem,
3704 const struct rte_memzone *mz = NULL;
3705 char z_name[RTE_MEMZONE_NAMESIZE];
3708 return I40E_ERR_PARAM;
3710 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3711 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3712 alignment, RTE_PGSIZE_2M);
3714 return I40E_ERR_NO_MEMORY;
3718 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3719 mem->zone = (const void *)mz;
3721 "memzone %s allocated with physical address: %"PRIu64,
3724 return I40E_SUCCESS;
3728 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3729 * @hw: pointer to the HW structure
3730 * @mem: ptr to mem struct to free
3732 enum i40e_status_code
3733 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3734 struct i40e_dma_mem *mem)
3737 return I40E_ERR_PARAM;
3740 "memzone %s to be freed with physical address: %"PRIu64,
3741 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3742 rte_memzone_free((const struct rte_memzone *)mem->zone);
3747 return I40E_SUCCESS;
3751 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3752 * @hw: pointer to the HW structure
3753 * @mem: pointer to mem struct to fill out
3754 * @size: size of memory requested
3756 enum i40e_status_code
3757 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3758 struct i40e_virt_mem *mem,
3762 return I40E_ERR_PARAM;
3765 mem->va = rte_zmalloc("i40e", size, 0);
3768 return I40E_SUCCESS;
3770 return I40E_ERR_NO_MEMORY;
3774 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3775 * @hw: pointer to the HW structure
3776 * @mem: pointer to mem struct to free
3778 enum i40e_status_code
3779 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3780 struct i40e_virt_mem *mem)
3783 return I40E_ERR_PARAM;
3788 return I40E_SUCCESS;
3792 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3794 rte_spinlock_init(&sp->spinlock);
3798 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3800 rte_spinlock_lock(&sp->spinlock);
3804 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3806 rte_spinlock_unlock(&sp->spinlock);
3810 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3816 * Get the hardware capabilities, which will be parsed
3817 * and saved into struct i40e_hw.
3820 i40e_get_cap(struct i40e_hw *hw)
3822 struct i40e_aqc_list_capabilities_element_resp *buf;
3823 uint16_t len, size = 0;
3826 /* Calculate a huge enough buff for saving response data temporarily */
3827 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3828 I40E_MAX_CAP_ELE_NUM;
3829 buf = rte_zmalloc("i40e", len, 0);
3831 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3832 return I40E_ERR_NO_MEMORY;
3835 /* Get, parse the capabilities and save it to hw */
3836 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3837 i40e_aqc_opc_list_func_capabilities, NULL);
3838 if (ret != I40E_SUCCESS)
3839 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3841 /* Free the temporary buffer after being used */
3848 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3850 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3851 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3852 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3853 uint16_t qp_count = 0, vsi_count = 0;
3855 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3856 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3859 /* Add the parameter init for LFC */
3860 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3861 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3862 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3864 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3865 pf->max_num_vsi = hw->func_caps.num_vsis;
3866 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3867 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3868 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3870 /* FDir queue/VSI allocation */
3871 pf->fdir_qp_offset = 0;
3872 if (hw->func_caps.fd) {
3873 pf->flags |= I40E_FLAG_FDIR;
3874 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3876 pf->fdir_nb_qps = 0;
3878 qp_count += pf->fdir_nb_qps;
3881 /* LAN queue/VSI allocation */
3882 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3883 if (!hw->func_caps.rss) {
3886 pf->flags |= I40E_FLAG_RSS;
3887 if (hw->mac.type == I40E_MAC_X722)
3888 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3889 pf->lan_nb_qps = pf->lan_nb_qp_max;
3891 qp_count += pf->lan_nb_qps;
3894 /* VF queue/VSI allocation */
3895 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3896 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3897 pf->flags |= I40E_FLAG_SRIOV;
3898 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3899 pf->vf_num = pci_dev->max_vfs;
3901 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3902 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3907 qp_count += pf->vf_nb_qps * pf->vf_num;
3908 vsi_count += pf->vf_num;
3910 /* VMDq queue/VSI allocation */
3911 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3912 pf->vmdq_nb_qps = 0;
3913 pf->max_nb_vmdq_vsi = 0;
3914 if (hw->func_caps.vmdq) {
3915 if (qp_count < hw->func_caps.num_tx_qp &&
3916 vsi_count < hw->func_caps.num_vsis) {
3917 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3918 qp_count) / pf->vmdq_nb_qp_max;
3920 /* Limit the maximum number of VMDq vsi to the maximum
3921 * ethdev can support
3923 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3924 hw->func_caps.num_vsis - vsi_count);
3925 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3927 if (pf->max_nb_vmdq_vsi) {
3928 pf->flags |= I40E_FLAG_VMDQ;
3929 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3931 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3932 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3933 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3936 "No enough queues left for VMDq");
3939 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3942 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3943 vsi_count += pf->max_nb_vmdq_vsi;
3945 if (hw->func_caps.dcb)
3946 pf->flags |= I40E_FLAG_DCB;
3948 if (qp_count > hw->func_caps.num_tx_qp) {
3950 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3951 qp_count, hw->func_caps.num_tx_qp);
3954 if (vsi_count > hw->func_caps.num_vsis) {
3956 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3957 vsi_count, hw->func_caps.num_vsis);
3965 i40e_pf_get_switch_config(struct i40e_pf *pf)
3967 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3968 struct i40e_aqc_get_switch_config_resp *switch_config;
3969 struct i40e_aqc_switch_config_element_resp *element;
3970 uint16_t start_seid = 0, num_reported;
3973 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3974 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3975 if (!switch_config) {
3976 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3980 /* Get the switch configurations */
3981 ret = i40e_aq_get_switch_config(hw, switch_config,
3982 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3983 if (ret != I40E_SUCCESS) {
3984 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3987 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3988 if (num_reported != 1) { /* The number should be 1 */
3989 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3993 /* Parse the switch configuration elements */
3994 element = &(switch_config->element[0]);
3995 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3996 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3997 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3999 PMD_DRV_LOG(INFO, "Unknown element type");
4002 rte_free(switch_config);
4008 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4011 struct pool_entry *entry;
4013 if (pool == NULL || num == 0)
4016 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4017 if (entry == NULL) {
4018 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4022 /* queue heap initialize */
4023 pool->num_free = num;
4024 pool->num_alloc = 0;
4026 LIST_INIT(&pool->alloc_list);
4027 LIST_INIT(&pool->free_list);
4029 /* Initialize element */
4033 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4038 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4040 struct pool_entry *entry, *next_entry;
4045 for (entry = LIST_FIRST(&pool->alloc_list);
4046 entry && (next_entry = LIST_NEXT(entry, next), 1);
4047 entry = next_entry) {
4048 LIST_REMOVE(entry, next);
4052 for (entry = LIST_FIRST(&pool->free_list);
4053 entry && (next_entry = LIST_NEXT(entry, next), 1);
4054 entry = next_entry) {
4055 LIST_REMOVE(entry, next);
4060 pool->num_alloc = 0;
4062 LIST_INIT(&pool->alloc_list);
4063 LIST_INIT(&pool->free_list);
4067 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4070 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4071 uint32_t pool_offset;
4075 PMD_DRV_LOG(ERR, "Invalid parameter");
4079 pool_offset = base - pool->base;
4080 /* Lookup in alloc list */
4081 LIST_FOREACH(entry, &pool->alloc_list, next) {
4082 if (entry->base == pool_offset) {
4083 valid_entry = entry;
4084 LIST_REMOVE(entry, next);
4089 /* Not find, return */
4090 if (valid_entry == NULL) {
4091 PMD_DRV_LOG(ERR, "Failed to find entry");
4096 * Found it, move it to free list and try to merge.
4097 * In order to make merge easier, always sort it by qbase.
4098 * Find adjacent prev and last entries.
4101 LIST_FOREACH(entry, &pool->free_list, next) {
4102 if (entry->base > valid_entry->base) {
4110 /* Try to merge with next one*/
4112 /* Merge with next one */
4113 if (valid_entry->base + valid_entry->len == next->base) {
4114 next->base = valid_entry->base;
4115 next->len += valid_entry->len;
4116 rte_free(valid_entry);
4123 /* Merge with previous one */
4124 if (prev->base + prev->len == valid_entry->base) {
4125 prev->len += valid_entry->len;
4126 /* If it merge with next one, remove next node */
4128 LIST_REMOVE(valid_entry, next);
4129 rte_free(valid_entry);
4131 rte_free(valid_entry);
4137 /* Not find any entry to merge, insert */
4140 LIST_INSERT_AFTER(prev, valid_entry, next);
4141 else if (next != NULL)
4142 LIST_INSERT_BEFORE(next, valid_entry, next);
4143 else /* It's empty list, insert to head */
4144 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4147 pool->num_free += valid_entry->len;
4148 pool->num_alloc -= valid_entry->len;
4154 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4157 struct pool_entry *entry, *valid_entry;
4159 if (pool == NULL || num == 0) {
4160 PMD_DRV_LOG(ERR, "Invalid parameter");
4164 if (pool->num_free < num) {
4165 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4166 num, pool->num_free);
4171 /* Lookup in free list and find most fit one */
4172 LIST_FOREACH(entry, &pool->free_list, next) {
4173 if (entry->len >= num) {
4175 if (entry->len == num) {
4176 valid_entry = entry;
4179 if (valid_entry == NULL || valid_entry->len > entry->len)
4180 valid_entry = entry;
4184 /* Not find one to satisfy the request, return */
4185 if (valid_entry == NULL) {
4186 PMD_DRV_LOG(ERR, "No valid entry found");
4190 * The entry have equal queue number as requested,
4191 * remove it from alloc_list.
4193 if (valid_entry->len == num) {
4194 LIST_REMOVE(valid_entry, next);
4197 * The entry have more numbers than requested,
4198 * create a new entry for alloc_list and minus its
4199 * queue base and number in free_list.
4201 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4202 if (entry == NULL) {
4204 "Failed to allocate memory for resource pool");
4207 entry->base = valid_entry->base;
4209 valid_entry->base += num;
4210 valid_entry->len -= num;
4211 valid_entry = entry;
4214 /* Insert it into alloc list, not sorted */
4215 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4217 pool->num_free -= valid_entry->len;
4218 pool->num_alloc += valid_entry->len;
4220 return valid_entry->base + pool->base;
4224 * bitmap_is_subset - Check whether src2 is subset of src1
4227 bitmap_is_subset(uint8_t src1, uint8_t src2)
4229 return !((src1 ^ src2) & src2);
4232 static enum i40e_status_code
4233 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4235 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4237 /* If DCB is not supported, only default TC is supported */
4238 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4239 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4240 return I40E_NOT_SUPPORTED;
4243 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4245 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4246 hw->func_caps.enabled_tcmap, enabled_tcmap);
4247 return I40E_NOT_SUPPORTED;
4249 return I40E_SUCCESS;
4253 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4254 struct i40e_vsi_vlan_pvid_info *info)
4257 struct i40e_vsi_context ctxt;
4258 uint8_t vlan_flags = 0;
4261 if (vsi == NULL || info == NULL) {
4262 PMD_DRV_LOG(ERR, "invalid parameters");
4263 return I40E_ERR_PARAM;
4267 vsi->info.pvid = info->config.pvid;
4269 * If insert pvid is enabled, only tagged pkts are
4270 * allowed to be sent out.
4272 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4273 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4276 if (info->config.reject.tagged == 0)
4277 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4279 if (info->config.reject.untagged == 0)
4280 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4282 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4283 I40E_AQ_VSI_PVLAN_MODE_MASK);
4284 vsi->info.port_vlan_flags |= vlan_flags;
4285 vsi->info.valid_sections =
4286 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4287 memset(&ctxt, 0, sizeof(ctxt));
4288 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4289 ctxt.seid = vsi->seid;
4291 hw = I40E_VSI_TO_HW(vsi);
4292 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4293 if (ret != I40E_SUCCESS)
4294 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4300 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4302 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4304 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4306 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4307 if (ret != I40E_SUCCESS)
4311 PMD_DRV_LOG(ERR, "seid not valid");
4315 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4316 tc_bw_data.tc_valid_bits = enabled_tcmap;
4317 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4318 tc_bw_data.tc_bw_credits[i] =
4319 (enabled_tcmap & (1 << i)) ? 1 : 0;
4321 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4322 if (ret != I40E_SUCCESS) {
4323 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4327 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4328 sizeof(vsi->info.qs_handle));
4329 return I40E_SUCCESS;
4332 static enum i40e_status_code
4333 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4334 struct i40e_aqc_vsi_properties_data *info,
4335 uint8_t enabled_tcmap)
4337 enum i40e_status_code ret;
4338 int i, total_tc = 0;
4339 uint16_t qpnum_per_tc, bsf, qp_idx;
4341 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4342 if (ret != I40E_SUCCESS)
4345 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4346 if (enabled_tcmap & (1 << i))
4350 vsi->enabled_tc = enabled_tcmap;
4352 /* Number of queues per enabled TC */
4353 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4354 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4355 bsf = rte_bsf32(qpnum_per_tc);
4357 /* Adjust the queue number to actual queues that can be applied */
4358 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4359 vsi->nb_qps = qpnum_per_tc * total_tc;
4362 * Configure TC and queue mapping parameters, for enabled TC,
4363 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4364 * default queue will serve it.
4367 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4368 if (vsi->enabled_tc & (1 << i)) {
4369 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4370 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4371 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4372 qp_idx += qpnum_per_tc;
4374 info->tc_mapping[i] = 0;
4377 /* Associate queue number with VSI */
4378 if (vsi->type == I40E_VSI_SRIOV) {
4379 info->mapping_flags |=
4380 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4381 for (i = 0; i < vsi->nb_qps; i++)
4382 info->queue_mapping[i] =
4383 rte_cpu_to_le_16(vsi->base_queue + i);
4385 info->mapping_flags |=
4386 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4387 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4389 info->valid_sections |=
4390 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4392 return I40E_SUCCESS;
4396 i40e_veb_release(struct i40e_veb *veb)
4398 struct i40e_vsi *vsi;
4404 if (!TAILQ_EMPTY(&veb->head)) {
4405 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4408 /* associate_vsi field is NULL for floating VEB */
4409 if (veb->associate_vsi != NULL) {
4410 vsi = veb->associate_vsi;
4411 hw = I40E_VSI_TO_HW(vsi);
4413 vsi->uplink_seid = veb->uplink_seid;
4416 veb->associate_pf->main_vsi->floating_veb = NULL;
4417 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4420 i40e_aq_delete_element(hw, veb->seid, NULL);
4422 return I40E_SUCCESS;
4426 static struct i40e_veb *
4427 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4429 struct i40e_veb *veb;
4435 "veb setup failed, associated PF shouldn't null");
4438 hw = I40E_PF_TO_HW(pf);
4440 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4442 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4446 veb->associate_vsi = vsi;
4447 veb->associate_pf = pf;
4448 TAILQ_INIT(&veb->head);
4449 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4451 /* create floating veb if vsi is NULL */
4453 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4454 I40E_DEFAULT_TCMAP, false,
4455 &veb->seid, false, NULL);
4457 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4458 true, &veb->seid, false, NULL);
4461 if (ret != I40E_SUCCESS) {
4462 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4463 hw->aq.asq_last_status);
4466 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4468 /* get statistics index */
4469 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4470 &veb->stats_idx, NULL, NULL, NULL);
4471 if (ret != I40E_SUCCESS) {
4472 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4473 hw->aq.asq_last_status);
4476 /* Get VEB bandwidth, to be implemented */
4477 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4479 vsi->uplink_seid = veb->seid;
4488 i40e_vsi_release(struct i40e_vsi *vsi)
4492 struct i40e_vsi_list *vsi_list;
4495 struct i40e_mac_filter *f;
4496 uint16_t user_param;
4499 return I40E_SUCCESS;
4504 user_param = vsi->user_param;
4506 pf = I40E_VSI_TO_PF(vsi);
4507 hw = I40E_VSI_TO_HW(vsi);
4509 /* VSI has child to attach, release child first */
4511 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4512 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4515 i40e_veb_release(vsi->veb);
4518 if (vsi->floating_veb) {
4519 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4520 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4525 /* Remove all macvlan filters of the VSI */
4526 i40e_vsi_remove_all_macvlan_filter(vsi);
4527 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4530 if (vsi->type != I40E_VSI_MAIN &&
4531 ((vsi->type != I40E_VSI_SRIOV) ||
4532 !pf->floating_veb_list[user_param])) {
4533 /* Remove vsi from parent's sibling list */
4534 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4535 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4536 return I40E_ERR_PARAM;
4538 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4539 &vsi->sib_vsi_list, list);
4541 /* Remove all switch element of the VSI */
4542 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4543 if (ret != I40E_SUCCESS)
4544 PMD_DRV_LOG(ERR, "Failed to delete element");
4547 if ((vsi->type == I40E_VSI_SRIOV) &&
4548 pf->floating_veb_list[user_param]) {
4549 /* Remove vsi from parent's sibling list */
4550 if (vsi->parent_vsi == NULL ||
4551 vsi->parent_vsi->floating_veb == NULL) {
4552 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4553 return I40E_ERR_PARAM;
4555 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4556 &vsi->sib_vsi_list, list);
4558 /* Remove all switch element of the VSI */
4559 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4560 if (ret != I40E_SUCCESS)
4561 PMD_DRV_LOG(ERR, "Failed to delete element");
4564 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4566 if (vsi->type != I40E_VSI_SRIOV)
4567 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4570 return I40E_SUCCESS;
4574 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4576 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4577 struct i40e_aqc_remove_macvlan_element_data def_filter;
4578 struct i40e_mac_filter_info filter;
4581 if (vsi->type != I40E_VSI_MAIN)
4582 return I40E_ERR_CONFIG;
4583 memset(&def_filter, 0, sizeof(def_filter));
4584 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4586 def_filter.vlan_tag = 0;
4587 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4588 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4589 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4590 if (ret != I40E_SUCCESS) {
4591 struct i40e_mac_filter *f;
4592 struct ether_addr *mac;
4595 "Cannot remove the default macvlan filter");
4596 /* It needs to add the permanent mac into mac list */
4597 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4599 PMD_DRV_LOG(ERR, "failed to allocate memory");
4600 return I40E_ERR_NO_MEMORY;
4602 mac = &f->mac_info.mac_addr;
4603 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4605 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4606 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4611 (void)rte_memcpy(&filter.mac_addr,
4612 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4613 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4614 return i40e_vsi_add_mac(vsi, &filter);
4618 * i40e_vsi_get_bw_config - Query VSI BW Information
4619 * @vsi: the VSI to be queried
4621 * Returns 0 on success, negative value on failure
4623 static enum i40e_status_code
4624 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4626 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4627 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4628 struct i40e_hw *hw = &vsi->adapter->hw;
4633 memset(&bw_config, 0, sizeof(bw_config));
4634 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4635 if (ret != I40E_SUCCESS) {
4636 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4637 hw->aq.asq_last_status);
4641 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4642 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4643 &ets_sla_config, NULL);
4644 if (ret != I40E_SUCCESS) {
4646 "VSI failed to get TC bandwdith configuration %u",
4647 hw->aq.asq_last_status);
4651 /* store and print out BW info */
4652 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4653 vsi->bw_info.bw_max = bw_config.max_bw;
4654 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4655 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4656 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4657 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4659 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4660 vsi->bw_info.bw_ets_share_credits[i] =
4661 ets_sla_config.share_credits[i];
4662 vsi->bw_info.bw_ets_credits[i] =
4663 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4664 /* 4 bits per TC, 4th bit is reserved */
4665 vsi->bw_info.bw_ets_max[i] =
4666 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4667 RTE_LEN2MASK(3, uint8_t));
4668 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4669 vsi->bw_info.bw_ets_share_credits[i]);
4670 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4671 vsi->bw_info.bw_ets_credits[i]);
4672 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4673 vsi->bw_info.bw_ets_max[i]);
4676 return I40E_SUCCESS;
4679 /* i40e_enable_pf_lb
4680 * @pf: pointer to the pf structure
4682 * allow loopback on pf
4685 i40e_enable_pf_lb(struct i40e_pf *pf)
4687 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4688 struct i40e_vsi_context ctxt;
4691 /* Use the FW API if FW >= v5.0 */
4692 if (hw->aq.fw_maj_ver < 5) {
4693 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4697 memset(&ctxt, 0, sizeof(ctxt));
4698 ctxt.seid = pf->main_vsi_seid;
4699 ctxt.pf_num = hw->pf_id;
4700 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4702 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4703 ret, hw->aq.asq_last_status);
4706 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4707 ctxt.info.valid_sections =
4708 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4709 ctxt.info.switch_id |=
4710 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4712 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4714 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4715 hw->aq.asq_last_status);
4720 i40e_vsi_setup(struct i40e_pf *pf,
4721 enum i40e_vsi_type type,
4722 struct i40e_vsi *uplink_vsi,
4723 uint16_t user_param)
4725 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4726 struct i40e_vsi *vsi;
4727 struct i40e_mac_filter_info filter;
4729 struct i40e_vsi_context ctxt;
4730 struct ether_addr broadcast =
4731 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4733 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4734 uplink_vsi == NULL) {
4736 "VSI setup failed, VSI link shouldn't be NULL");
4740 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4742 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4747 * 1.type is not MAIN and uplink vsi is not NULL
4748 * If uplink vsi didn't setup VEB, create one first under veb field
4749 * 2.type is SRIOV and the uplink is NULL
4750 * If floating VEB is NULL, create one veb under floating veb field
4753 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4754 uplink_vsi->veb == NULL) {
4755 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4757 if (uplink_vsi->veb == NULL) {
4758 PMD_DRV_LOG(ERR, "VEB setup failed");
4761 /* set ALLOWLOOPBACk on pf, when veb is created */
4762 i40e_enable_pf_lb(pf);
4765 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4766 pf->main_vsi->floating_veb == NULL) {
4767 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4769 if (pf->main_vsi->floating_veb == NULL) {
4770 PMD_DRV_LOG(ERR, "VEB setup failed");
4775 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4777 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4780 TAILQ_INIT(&vsi->mac_list);
4782 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4783 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4784 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4785 vsi->user_param = user_param;
4786 vsi->vlan_anti_spoof_on = 0;
4787 vsi->vlan_filter_on = 0;
4788 /* Allocate queues */
4789 switch (vsi->type) {
4790 case I40E_VSI_MAIN :
4791 vsi->nb_qps = pf->lan_nb_qps;
4793 case I40E_VSI_SRIOV :
4794 vsi->nb_qps = pf->vf_nb_qps;
4796 case I40E_VSI_VMDQ2:
4797 vsi->nb_qps = pf->vmdq_nb_qps;
4800 vsi->nb_qps = pf->fdir_nb_qps;
4806 * The filter status descriptor is reported in rx queue 0,
4807 * while the tx queue for fdir filter programming has no
4808 * such constraints, can be non-zero queues.
4809 * To simplify it, choose FDIR vsi use queue 0 pair.
4810 * To make sure it will use queue 0 pair, queue allocation
4811 * need be done before this function is called
4813 if (type != I40E_VSI_FDIR) {
4814 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4816 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4820 vsi->base_queue = ret;
4822 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4824 /* VF has MSIX interrupt in VF range, don't allocate here */
4825 if (type == I40E_VSI_MAIN) {
4826 ret = i40e_res_pool_alloc(&pf->msix_pool,
4827 RTE_MIN(vsi->nb_qps,
4828 RTE_MAX_RXTX_INTR_VEC_ID));
4830 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4832 goto fail_queue_alloc;
4834 vsi->msix_intr = ret;
4835 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4836 } else if (type != I40E_VSI_SRIOV) {
4837 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4839 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4840 goto fail_queue_alloc;
4842 vsi->msix_intr = ret;
4850 if (type == I40E_VSI_MAIN) {
4851 /* For main VSI, no need to add since it's default one */
4852 vsi->uplink_seid = pf->mac_seid;
4853 vsi->seid = pf->main_vsi_seid;
4854 /* Bind queues with specific MSIX interrupt */
4856 * Needs 2 interrupt at least, one for misc cause which will
4857 * enabled from OS side, Another for queues binding the
4858 * interrupt from device side only.
4861 /* Get default VSI parameters from hardware */
4862 memset(&ctxt, 0, sizeof(ctxt));
4863 ctxt.seid = vsi->seid;
4864 ctxt.pf_num = hw->pf_id;
4865 ctxt.uplink_seid = vsi->uplink_seid;
4867 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4868 if (ret != I40E_SUCCESS) {
4869 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4870 goto fail_msix_alloc;
4872 (void)rte_memcpy(&vsi->info, &ctxt.info,
4873 sizeof(struct i40e_aqc_vsi_properties_data));
4874 vsi->vsi_id = ctxt.vsi_number;
4875 vsi->info.valid_sections = 0;
4877 /* Configure tc, enabled TC0 only */
4878 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4880 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4881 goto fail_msix_alloc;
4884 /* TC, queue mapping */
4885 memset(&ctxt, 0, sizeof(ctxt));
4886 vsi->info.valid_sections |=
4887 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4888 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4889 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4890 (void)rte_memcpy(&ctxt.info, &vsi->info,
4891 sizeof(struct i40e_aqc_vsi_properties_data));
4892 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4893 I40E_DEFAULT_TCMAP);
4894 if (ret != I40E_SUCCESS) {
4896 "Failed to configure TC queue mapping");
4897 goto fail_msix_alloc;
4899 ctxt.seid = vsi->seid;
4900 ctxt.pf_num = hw->pf_id;
4901 ctxt.uplink_seid = vsi->uplink_seid;
4904 /* Update VSI parameters */
4905 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4906 if (ret != I40E_SUCCESS) {
4907 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4908 goto fail_msix_alloc;
4911 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4912 sizeof(vsi->info.tc_mapping));
4913 (void)rte_memcpy(&vsi->info.queue_mapping,
4914 &ctxt.info.queue_mapping,
4915 sizeof(vsi->info.queue_mapping));
4916 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4917 vsi->info.valid_sections = 0;
4919 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4923 * Updating default filter settings are necessary to prevent
4924 * reception of tagged packets.
4925 * Some old firmware configurations load a default macvlan
4926 * filter which accepts both tagged and untagged packets.
4927 * The updating is to use a normal filter instead if needed.
4928 * For NVM 4.2.2 or after, the updating is not needed anymore.
4929 * The firmware with correct configurations load the default
4930 * macvlan filter which is expected and cannot be removed.
4932 i40e_update_default_filter_setting(vsi);
4933 i40e_config_qinq(hw, vsi);
4934 } else if (type == I40E_VSI_SRIOV) {
4935 memset(&ctxt, 0, sizeof(ctxt));
4937 * For other VSI, the uplink_seid equals to uplink VSI's
4938 * uplink_seid since they share same VEB
4940 if (uplink_vsi == NULL)
4941 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4943 vsi->uplink_seid = uplink_vsi->uplink_seid;
4944 ctxt.pf_num = hw->pf_id;
4945 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4946 ctxt.uplink_seid = vsi->uplink_seid;
4947 ctxt.connection_type = 0x1;
4948 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4950 /* Use the VEB configuration if FW >= v5.0 */
4951 if (hw->aq.fw_maj_ver >= 5) {
4952 /* Configure switch ID */
4953 ctxt.info.valid_sections |=
4954 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4955 ctxt.info.switch_id =
4956 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4959 /* Configure port/vlan */
4960 ctxt.info.valid_sections |=
4961 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4962 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4963 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4964 hw->func_caps.enabled_tcmap);
4965 if (ret != I40E_SUCCESS) {
4967 "Failed to configure TC queue mapping");
4968 goto fail_msix_alloc;
4971 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4972 ctxt.info.valid_sections |=
4973 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4975 * Since VSI is not created yet, only configure parameter,
4976 * will add vsi below.
4979 i40e_config_qinq(hw, vsi);
4980 } else if (type == I40E_VSI_VMDQ2) {
4981 memset(&ctxt, 0, sizeof(ctxt));
4983 * For other VSI, the uplink_seid equals to uplink VSI's
4984 * uplink_seid since they share same VEB
4986 vsi->uplink_seid = uplink_vsi->uplink_seid;
4987 ctxt.pf_num = hw->pf_id;
4989 ctxt.uplink_seid = vsi->uplink_seid;
4990 ctxt.connection_type = 0x1;
4991 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4993 ctxt.info.valid_sections |=
4994 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4995 /* user_param carries flag to enable loop back */
4997 ctxt.info.switch_id =
4998 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4999 ctxt.info.switch_id |=
5000 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5003 /* Configure port/vlan */
5004 ctxt.info.valid_sections |=
5005 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5006 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5007 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5008 I40E_DEFAULT_TCMAP);
5009 if (ret != I40E_SUCCESS) {
5011 "Failed to configure TC queue mapping");
5012 goto fail_msix_alloc;
5014 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5015 ctxt.info.valid_sections |=
5016 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5017 } else if (type == I40E_VSI_FDIR) {
5018 memset(&ctxt, 0, sizeof(ctxt));
5019 vsi->uplink_seid = uplink_vsi->uplink_seid;
5020 ctxt.pf_num = hw->pf_id;
5022 ctxt.uplink_seid = vsi->uplink_seid;
5023 ctxt.connection_type = 0x1; /* regular data port */
5024 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5025 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5026 I40E_DEFAULT_TCMAP);
5027 if (ret != I40E_SUCCESS) {
5029 "Failed to configure TC queue mapping.");
5030 goto fail_msix_alloc;
5032 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5033 ctxt.info.valid_sections |=
5034 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5036 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5037 goto fail_msix_alloc;
5040 if (vsi->type != I40E_VSI_MAIN) {
5041 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5042 if (ret != I40E_SUCCESS) {
5043 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5044 hw->aq.asq_last_status);
5045 goto fail_msix_alloc;
5047 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5048 vsi->info.valid_sections = 0;
5049 vsi->seid = ctxt.seid;
5050 vsi->vsi_id = ctxt.vsi_number;
5051 vsi->sib_vsi_list.vsi = vsi;
5052 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5053 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5054 &vsi->sib_vsi_list, list);
5056 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5057 &vsi->sib_vsi_list, list);
5061 /* MAC/VLAN configuration */
5062 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5063 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5065 ret = i40e_vsi_add_mac(vsi, &filter);
5066 if (ret != I40E_SUCCESS) {
5067 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5068 goto fail_msix_alloc;
5071 /* Get VSI BW information */
5072 i40e_vsi_get_bw_config(vsi);
5075 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5077 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5083 /* Configure vlan filter on or off */
5085 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5088 struct i40e_mac_filter *f;
5090 struct i40e_mac_filter_info *mac_filter;
5091 enum rte_mac_filter_type desired_filter;
5092 int ret = I40E_SUCCESS;
5095 /* Filter to match MAC and VLAN */
5096 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5098 /* Filter to match only MAC */
5099 desired_filter = RTE_MAC_PERFECT_MATCH;
5104 mac_filter = rte_zmalloc("mac_filter_info_data",
5105 num * sizeof(*mac_filter), 0);
5106 if (mac_filter == NULL) {
5107 PMD_DRV_LOG(ERR, "failed to allocate memory");
5108 return I40E_ERR_NO_MEMORY;
5113 /* Remove all existing mac */
5114 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5115 mac_filter[i] = f->mac_info;
5116 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5118 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5119 on ? "enable" : "disable");
5125 /* Override with new filter */
5126 for (i = 0; i < num; i++) {
5127 mac_filter[i].filter_type = desired_filter;
5128 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5130 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5131 on ? "enable" : "disable");
5137 rte_free(mac_filter);
5141 /* Configure vlan stripping on or off */
5143 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5145 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5146 struct i40e_vsi_context ctxt;
5148 int ret = I40E_SUCCESS;
5150 /* Check if it has been already on or off */
5151 if (vsi->info.valid_sections &
5152 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5154 if ((vsi->info.port_vlan_flags &
5155 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5156 return 0; /* already on */
5158 if ((vsi->info.port_vlan_flags &
5159 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5160 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5161 return 0; /* already off */
5166 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5168 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5169 vsi->info.valid_sections =
5170 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5171 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5172 vsi->info.port_vlan_flags |= vlan_flags;
5173 ctxt.seid = vsi->seid;
5174 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5175 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5177 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5178 on ? "enable" : "disable");
5184 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5186 struct rte_eth_dev_data *data = dev->data;
5190 /* Apply vlan offload setting */
5191 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5192 i40e_vlan_offload_set(dev, mask);
5194 /* Apply double-vlan setting, not implemented yet */
5196 /* Apply pvid setting */
5197 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5198 data->dev_conf.txmode.hw_vlan_insert_pvid);
5200 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5206 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5208 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5210 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5214 i40e_update_flow_control(struct i40e_hw *hw)
5216 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5217 struct i40e_link_status link_status;
5218 uint32_t rxfc = 0, txfc = 0, reg;
5222 memset(&link_status, 0, sizeof(link_status));
5223 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5224 if (ret != I40E_SUCCESS) {
5225 PMD_DRV_LOG(ERR, "Failed to get link status information");
5226 goto write_reg; /* Disable flow control */
5229 an_info = hw->phy.link_info.an_info;
5230 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5231 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5232 ret = I40E_ERR_NOT_READY;
5233 goto write_reg; /* Disable flow control */
5236 * If link auto negotiation is enabled, flow control needs to
5237 * be configured according to it
5239 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5240 case I40E_LINK_PAUSE_RXTX:
5243 hw->fc.current_mode = I40E_FC_FULL;
5245 case I40E_AQ_LINK_PAUSE_RX:
5247 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5249 case I40E_AQ_LINK_PAUSE_TX:
5251 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5254 hw->fc.current_mode = I40E_FC_NONE;
5259 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5260 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5261 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5262 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5263 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5264 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5271 i40e_pf_setup(struct i40e_pf *pf)
5273 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5274 struct i40e_filter_control_settings settings;
5275 struct i40e_vsi *vsi;
5278 /* Clear all stats counters */
5279 pf->offset_loaded = FALSE;
5280 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5281 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5282 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5283 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5285 ret = i40e_pf_get_switch_config(pf);
5286 if (ret != I40E_SUCCESS) {
5287 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5290 if (pf->flags & I40E_FLAG_FDIR) {
5291 /* make queue allocated first, let FDIR use queue pair 0*/
5292 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5293 if (ret != I40E_FDIR_QUEUE_ID) {
5295 "queue allocation fails for FDIR: ret =%d",
5297 pf->flags &= ~I40E_FLAG_FDIR;
5300 /* main VSI setup */
5301 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5303 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5304 return I40E_ERR_NOT_READY;
5308 /* Configure filter control */
5309 memset(&settings, 0, sizeof(settings));
5310 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5311 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5312 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5313 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5315 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5316 hw->func_caps.rss_table_size);
5317 return I40E_ERR_PARAM;
5319 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5320 hw->func_caps.rss_table_size);
5321 pf->hash_lut_size = hw->func_caps.rss_table_size;
5323 /* Enable ethtype and macvlan filters */
5324 settings.enable_ethtype = TRUE;
5325 settings.enable_macvlan = TRUE;
5326 ret = i40e_set_filter_control(hw, &settings);
5328 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5331 /* Update flow control according to the auto negotiation */
5332 i40e_update_flow_control(hw);
5334 return I40E_SUCCESS;
5338 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5344 * Set or clear TX Queue Disable flags,
5345 * which is required by hardware.
5347 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5348 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5350 /* Wait until the request is finished */
5351 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5352 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5353 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5354 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5355 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5361 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5362 return I40E_SUCCESS; /* already on, skip next steps */
5364 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5365 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5367 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5368 return I40E_SUCCESS; /* already off, skip next steps */
5369 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5371 /* Write the register */
5372 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5373 /* Check the result */
5374 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5375 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5376 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5378 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5379 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5382 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5383 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5387 /* Check if it is timeout */
5388 if (j >= I40E_CHK_Q_ENA_COUNT) {
5389 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5390 (on ? "enable" : "disable"), q_idx);
5391 return I40E_ERR_TIMEOUT;
5394 return I40E_SUCCESS;
5397 /* Swith on or off the tx queues */
5399 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5401 struct rte_eth_dev_data *dev_data = pf->dev_data;
5402 struct i40e_tx_queue *txq;
5403 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5407 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5408 txq = dev_data->tx_queues[i];
5409 /* Don't operate the queue if not configured or
5410 * if starting only per queue */
5411 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5414 ret = i40e_dev_tx_queue_start(dev, i);
5416 ret = i40e_dev_tx_queue_stop(dev, i);
5417 if ( ret != I40E_SUCCESS)
5421 return I40E_SUCCESS;
5425 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5430 /* Wait until the request is finished */
5431 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5432 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5433 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5434 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5435 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5440 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5441 return I40E_SUCCESS; /* Already on, skip next steps */
5442 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5444 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5445 return I40E_SUCCESS; /* Already off, skip next steps */
5446 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5449 /* Write the register */
5450 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5451 /* Check the result */
5452 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5453 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5454 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5456 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5457 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5460 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5461 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5466 /* Check if it is timeout */
5467 if (j >= I40E_CHK_Q_ENA_COUNT) {
5468 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5469 (on ? "enable" : "disable"), q_idx);
5470 return I40E_ERR_TIMEOUT;
5473 return I40E_SUCCESS;
5475 /* Switch on or off the rx queues */
5477 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5479 struct rte_eth_dev_data *dev_data = pf->dev_data;
5480 struct i40e_rx_queue *rxq;
5481 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5485 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5486 rxq = dev_data->rx_queues[i];
5487 /* Don't operate the queue if not configured or
5488 * if starting only per queue */
5489 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5492 ret = i40e_dev_rx_queue_start(dev, i);
5494 ret = i40e_dev_rx_queue_stop(dev, i);
5495 if (ret != I40E_SUCCESS)
5499 return I40E_SUCCESS;
5502 /* Switch on or off all the rx/tx queues */
5504 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5509 /* enable rx queues before enabling tx queues */
5510 ret = i40e_dev_switch_rx_queues(pf, on);
5512 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5515 ret = i40e_dev_switch_tx_queues(pf, on);
5517 /* Stop tx queues before stopping rx queues */
5518 ret = i40e_dev_switch_tx_queues(pf, on);
5520 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5523 ret = i40e_dev_switch_rx_queues(pf, on);
5529 /* Initialize VSI for TX */
5531 i40e_dev_tx_init(struct i40e_pf *pf)
5533 struct rte_eth_dev_data *data = pf->dev_data;
5535 uint32_t ret = I40E_SUCCESS;
5536 struct i40e_tx_queue *txq;
5538 for (i = 0; i < data->nb_tx_queues; i++) {
5539 txq = data->tx_queues[i];
5540 if (!txq || !txq->q_set)
5542 ret = i40e_tx_queue_init(txq);
5543 if (ret != I40E_SUCCESS)
5546 if (ret == I40E_SUCCESS)
5547 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5553 /* Initialize VSI for RX */
5555 i40e_dev_rx_init(struct i40e_pf *pf)
5557 struct rte_eth_dev_data *data = pf->dev_data;
5558 int ret = I40E_SUCCESS;
5560 struct i40e_rx_queue *rxq;
5562 i40e_pf_config_mq_rx(pf);
5563 for (i = 0; i < data->nb_rx_queues; i++) {
5564 rxq = data->rx_queues[i];
5565 if (!rxq || !rxq->q_set)
5568 ret = i40e_rx_queue_init(rxq);
5569 if (ret != I40E_SUCCESS) {
5571 "Failed to do RX queue initialization");
5575 if (ret == I40E_SUCCESS)
5576 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5583 i40e_dev_rxtx_init(struct i40e_pf *pf)
5587 err = i40e_dev_tx_init(pf);
5589 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5592 err = i40e_dev_rx_init(pf);
5594 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5602 i40e_vmdq_setup(struct rte_eth_dev *dev)
5604 struct rte_eth_conf *conf = &dev->data->dev_conf;
5605 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5606 int i, err, conf_vsis, j, loop;
5607 struct i40e_vsi *vsi;
5608 struct i40e_vmdq_info *vmdq_info;
5609 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5610 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5613 * Disable interrupt to avoid message from VF. Furthermore, it will
5614 * avoid race condition in VSI creation/destroy.
5616 i40e_pf_disable_irq0(hw);
5618 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5619 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5623 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5624 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5625 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5626 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5627 pf->max_nb_vmdq_vsi);
5631 if (pf->vmdq != NULL) {
5632 PMD_INIT_LOG(INFO, "VMDQ already configured");
5636 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5637 sizeof(*vmdq_info) * conf_vsis, 0);
5639 if (pf->vmdq == NULL) {
5640 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5644 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5646 /* Create VMDQ VSI */
5647 for (i = 0; i < conf_vsis; i++) {
5648 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5649 vmdq_conf->enable_loop_back);
5651 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5655 vmdq_info = &pf->vmdq[i];
5657 vmdq_info->vsi = vsi;
5659 pf->nb_cfg_vmdq_vsi = conf_vsis;
5661 /* Configure Vlan */
5662 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5663 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5664 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5665 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5666 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5667 vmdq_conf->pool_map[i].vlan_id, j);
5669 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5670 vmdq_conf->pool_map[i].vlan_id);
5672 PMD_INIT_LOG(ERR, "Failed to add vlan");
5680 i40e_pf_enable_irq0(hw);
5685 for (i = 0; i < conf_vsis; i++)
5686 if (pf->vmdq[i].vsi == NULL)
5689 i40e_vsi_release(pf->vmdq[i].vsi);
5693 i40e_pf_enable_irq0(hw);
5698 i40e_stat_update_32(struct i40e_hw *hw,
5706 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5710 if (new_data >= *offset)
5711 *stat = (uint64_t)(new_data - *offset);
5713 *stat = (uint64_t)((new_data +
5714 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5718 i40e_stat_update_48(struct i40e_hw *hw,
5727 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5728 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5729 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5734 if (new_data >= *offset)
5735 *stat = new_data - *offset;
5737 *stat = (uint64_t)((new_data +
5738 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5740 *stat &= I40E_48_BIT_MASK;
5745 i40e_pf_disable_irq0(struct i40e_hw *hw)
5747 /* Disable all interrupt types */
5748 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5749 I40E_WRITE_FLUSH(hw);
5754 i40e_pf_enable_irq0(struct i40e_hw *hw)
5756 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5757 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5758 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5759 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5760 I40E_WRITE_FLUSH(hw);
5764 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5766 /* read pending request and disable first */
5767 i40e_pf_disable_irq0(hw);
5768 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5769 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5770 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5773 /* Link no queues with irq0 */
5774 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5775 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5779 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5782 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5785 uint32_t index, offset, val;
5790 * Try to find which VF trigger a reset, use absolute VF id to access
5791 * since the reg is global register.
5793 for (i = 0; i < pf->vf_num; i++) {
5794 abs_vf_id = hw->func_caps.vf_base_id + i;
5795 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5796 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5797 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5798 /* VFR event occurred */
5799 if (val & (0x1 << offset)) {
5802 /* Clear the event first */
5803 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5805 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5807 * Only notify a VF reset event occurred,
5808 * don't trigger another SW reset
5810 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5811 if (ret != I40E_SUCCESS)
5812 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5818 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5820 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5823 for (i = 0; i < pf->vf_num; i++)
5824 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5828 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5830 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5831 struct i40e_arq_event_info info;
5832 uint16_t pending, opcode;
5835 info.buf_len = I40E_AQ_BUF_SZ;
5836 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5837 if (!info.msg_buf) {
5838 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5844 ret = i40e_clean_arq_element(hw, &info, &pending);
5846 if (ret != I40E_SUCCESS) {
5848 "Failed to read msg from AdminQ, aq_err: %u",
5849 hw->aq.asq_last_status);
5852 opcode = rte_le_to_cpu_16(info.desc.opcode);
5855 case i40e_aqc_opc_send_msg_to_pf:
5856 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5857 i40e_pf_host_handle_vf_msg(dev,
5858 rte_le_to_cpu_16(info.desc.retval),
5859 rte_le_to_cpu_32(info.desc.cookie_high),
5860 rte_le_to_cpu_32(info.desc.cookie_low),
5864 case i40e_aqc_opc_get_link_status:
5865 ret = i40e_dev_link_update(dev, 0);
5867 _rte_eth_dev_callback_process(dev,
5868 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5871 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5876 rte_free(info.msg_buf);
5880 * Interrupt handler triggered by NIC for handling
5881 * specific interrupt.
5884 * Pointer to interrupt handle.
5886 * The address of parameter (struct rte_eth_dev *) regsitered before.
5892 i40e_dev_interrupt_handler(void *param)
5894 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5895 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5898 /* Disable interrupt */
5899 i40e_pf_disable_irq0(hw);
5901 /* read out interrupt causes */
5902 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5904 /* No interrupt event indicated */
5905 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5906 PMD_DRV_LOG(INFO, "No interrupt event");
5909 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5910 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5911 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5912 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5913 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5914 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5915 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5916 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5917 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5918 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5919 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5920 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5921 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5922 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5924 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5925 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5926 i40e_dev_handle_vfr_event(dev);
5928 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5929 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5930 i40e_dev_handle_aq_msg(dev);
5934 /* Enable interrupt */
5935 i40e_pf_enable_irq0(hw);
5936 rte_intr_enable(dev->intr_handle);
5940 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5941 struct i40e_macvlan_filter *filter,
5944 int ele_num, ele_buff_size;
5945 int num, actual_num, i;
5947 int ret = I40E_SUCCESS;
5948 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5949 struct i40e_aqc_add_macvlan_element_data *req_list;
5951 if (filter == NULL || total == 0)
5952 return I40E_ERR_PARAM;
5953 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5954 ele_buff_size = hw->aq.asq_buf_size;
5956 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5957 if (req_list == NULL) {
5958 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5959 return I40E_ERR_NO_MEMORY;
5964 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5965 memset(req_list, 0, ele_buff_size);
5967 for (i = 0; i < actual_num; i++) {
5968 (void)rte_memcpy(req_list[i].mac_addr,
5969 &filter[num + i].macaddr, ETH_ADDR_LEN);
5970 req_list[i].vlan_tag =
5971 rte_cpu_to_le_16(filter[num + i].vlan_id);
5973 switch (filter[num + i].filter_type) {
5974 case RTE_MAC_PERFECT_MATCH:
5975 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5976 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5978 case RTE_MACVLAN_PERFECT_MATCH:
5979 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5981 case RTE_MAC_HASH_MATCH:
5982 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5983 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5985 case RTE_MACVLAN_HASH_MATCH:
5986 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5989 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5990 ret = I40E_ERR_PARAM;
5994 req_list[i].queue_number = 0;
5996 req_list[i].flags = rte_cpu_to_le_16(flags);
5999 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6001 if (ret != I40E_SUCCESS) {
6002 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6006 } while (num < total);
6014 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6015 struct i40e_macvlan_filter *filter,
6018 int ele_num, ele_buff_size;
6019 int num, actual_num, i;
6021 int ret = I40E_SUCCESS;
6022 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6023 struct i40e_aqc_remove_macvlan_element_data *req_list;
6025 if (filter == NULL || total == 0)
6026 return I40E_ERR_PARAM;
6028 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6029 ele_buff_size = hw->aq.asq_buf_size;
6031 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6032 if (req_list == NULL) {
6033 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6034 return I40E_ERR_NO_MEMORY;
6039 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6040 memset(req_list, 0, ele_buff_size);
6042 for (i = 0; i < actual_num; i++) {
6043 (void)rte_memcpy(req_list[i].mac_addr,
6044 &filter[num + i].macaddr, ETH_ADDR_LEN);
6045 req_list[i].vlan_tag =
6046 rte_cpu_to_le_16(filter[num + i].vlan_id);
6048 switch (filter[num + i].filter_type) {
6049 case RTE_MAC_PERFECT_MATCH:
6050 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6051 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6053 case RTE_MACVLAN_PERFECT_MATCH:
6054 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6056 case RTE_MAC_HASH_MATCH:
6057 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6058 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6060 case RTE_MACVLAN_HASH_MATCH:
6061 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6064 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6065 ret = I40E_ERR_PARAM;
6068 req_list[i].flags = rte_cpu_to_le_16(flags);
6071 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6073 if (ret != I40E_SUCCESS) {
6074 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6078 } while (num < total);
6085 /* Find out specific MAC filter */
6086 static struct i40e_mac_filter *
6087 i40e_find_mac_filter(struct i40e_vsi *vsi,
6088 struct ether_addr *macaddr)
6090 struct i40e_mac_filter *f;
6092 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6093 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6101 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6104 uint32_t vid_idx, vid_bit;
6106 if (vlan_id > ETH_VLAN_ID_MAX)
6109 vid_idx = I40E_VFTA_IDX(vlan_id);
6110 vid_bit = I40E_VFTA_BIT(vlan_id);
6112 if (vsi->vfta[vid_idx] & vid_bit)
6119 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6120 uint16_t vlan_id, bool on)
6122 uint32_t vid_idx, vid_bit;
6124 vid_idx = I40E_VFTA_IDX(vlan_id);
6125 vid_bit = I40E_VFTA_BIT(vlan_id);
6128 vsi->vfta[vid_idx] |= vid_bit;
6130 vsi->vfta[vid_idx] &= ~vid_bit;
6134 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6135 uint16_t vlan_id, bool on)
6137 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6138 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6141 if (vlan_id > ETH_VLAN_ID_MAX)
6144 i40e_store_vlan_filter(vsi, vlan_id, on);
6146 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6149 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6152 ret = i40e_aq_add_vlan(hw, vsi->seid,
6153 &vlan_data, 1, NULL);
6154 if (ret != I40E_SUCCESS)
6155 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6157 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6158 &vlan_data, 1, NULL);
6159 if (ret != I40E_SUCCESS)
6161 "Failed to remove vlan filter");
6166 * Find all vlan options for specific mac addr,
6167 * return with actual vlan found.
6170 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6171 struct i40e_macvlan_filter *mv_f,
6172 int num, struct ether_addr *addr)
6178 * Not to use i40e_find_vlan_filter to decrease the loop time,
6179 * although the code looks complex.
6181 if (num < vsi->vlan_num)
6182 return I40E_ERR_PARAM;
6185 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6187 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6188 if (vsi->vfta[j] & (1 << k)) {
6191 "vlan number doesn't match");
6192 return I40E_ERR_PARAM;
6194 (void)rte_memcpy(&mv_f[i].macaddr,
6195 addr, ETH_ADDR_LEN);
6197 j * I40E_UINT32_BIT_SIZE + k;
6203 return I40E_SUCCESS;
6207 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6208 struct i40e_macvlan_filter *mv_f,
6213 struct i40e_mac_filter *f;
6215 if (num < vsi->mac_num)
6216 return I40E_ERR_PARAM;
6218 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6220 PMD_DRV_LOG(ERR, "buffer number not match");
6221 return I40E_ERR_PARAM;
6223 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6225 mv_f[i].vlan_id = vlan;
6226 mv_f[i].filter_type = f->mac_info.filter_type;
6230 return I40E_SUCCESS;
6234 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6237 struct i40e_mac_filter *f;
6238 struct i40e_macvlan_filter *mv_f;
6239 int ret = I40E_SUCCESS;
6241 if (vsi == NULL || vsi->mac_num == 0)
6242 return I40E_ERR_PARAM;
6244 /* Case that no vlan is set */
6245 if (vsi->vlan_num == 0)
6248 num = vsi->mac_num * vsi->vlan_num;
6250 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6252 PMD_DRV_LOG(ERR, "failed to allocate memory");
6253 return I40E_ERR_NO_MEMORY;
6257 if (vsi->vlan_num == 0) {
6258 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6259 (void)rte_memcpy(&mv_f[i].macaddr,
6260 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6261 mv_f[i].filter_type = f->mac_info.filter_type;
6262 mv_f[i].vlan_id = 0;
6266 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6267 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6268 vsi->vlan_num, &f->mac_info.mac_addr);
6269 if (ret != I40E_SUCCESS)
6271 for (j = i; j < i + vsi->vlan_num; j++)
6272 mv_f[j].filter_type = f->mac_info.filter_type;
6277 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6285 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6287 struct i40e_macvlan_filter *mv_f;
6289 int ret = I40E_SUCCESS;
6291 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6292 return I40E_ERR_PARAM;
6294 /* If it's already set, just return */
6295 if (i40e_find_vlan_filter(vsi,vlan))
6296 return I40E_SUCCESS;
6298 mac_num = vsi->mac_num;
6301 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6302 return I40E_ERR_PARAM;
6305 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6308 PMD_DRV_LOG(ERR, "failed to allocate memory");
6309 return I40E_ERR_NO_MEMORY;
6312 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6314 if (ret != I40E_SUCCESS)
6317 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6319 if (ret != I40E_SUCCESS)
6322 i40e_set_vlan_filter(vsi, vlan, 1);
6332 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6334 struct i40e_macvlan_filter *mv_f;
6336 int ret = I40E_SUCCESS;
6339 * Vlan 0 is the generic filter for untagged packets
6340 * and can't be removed.
6342 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6343 return I40E_ERR_PARAM;
6345 /* If can't find it, just return */
6346 if (!i40e_find_vlan_filter(vsi, vlan))
6347 return I40E_ERR_PARAM;
6349 mac_num = vsi->mac_num;
6352 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6353 return I40E_ERR_PARAM;
6356 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6359 PMD_DRV_LOG(ERR, "failed to allocate memory");
6360 return I40E_ERR_NO_MEMORY;
6363 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6365 if (ret != I40E_SUCCESS)
6368 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6370 if (ret != I40E_SUCCESS)
6373 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6374 if (vsi->vlan_num == 1) {
6375 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6376 if (ret != I40E_SUCCESS)
6379 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6380 if (ret != I40E_SUCCESS)
6384 i40e_set_vlan_filter(vsi, vlan, 0);
6394 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6396 struct i40e_mac_filter *f;
6397 struct i40e_macvlan_filter *mv_f;
6398 int i, vlan_num = 0;
6399 int ret = I40E_SUCCESS;
6401 /* If it's add and we've config it, return */
6402 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6404 return I40E_SUCCESS;
6405 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6406 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6409 * If vlan_num is 0, that's the first time to add mac,
6410 * set mask for vlan_id 0.
6412 if (vsi->vlan_num == 0) {
6413 i40e_set_vlan_filter(vsi, 0, 1);
6416 vlan_num = vsi->vlan_num;
6417 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6418 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6421 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6423 PMD_DRV_LOG(ERR, "failed to allocate memory");
6424 return I40E_ERR_NO_MEMORY;
6427 for (i = 0; i < vlan_num; i++) {
6428 mv_f[i].filter_type = mac_filter->filter_type;
6429 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6433 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6434 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6435 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6436 &mac_filter->mac_addr);
6437 if (ret != I40E_SUCCESS)
6441 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6442 if (ret != I40E_SUCCESS)
6445 /* Add the mac addr into mac list */
6446 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6448 PMD_DRV_LOG(ERR, "failed to allocate memory");
6449 ret = I40E_ERR_NO_MEMORY;
6452 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6454 f->mac_info.filter_type = mac_filter->filter_type;
6455 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6466 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6468 struct i40e_mac_filter *f;
6469 struct i40e_macvlan_filter *mv_f;
6471 enum rte_mac_filter_type filter_type;
6472 int ret = I40E_SUCCESS;
6474 /* Can't find it, return an error */
6475 f = i40e_find_mac_filter(vsi, addr);
6477 return I40E_ERR_PARAM;
6479 vlan_num = vsi->vlan_num;
6480 filter_type = f->mac_info.filter_type;
6481 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6482 filter_type == RTE_MACVLAN_HASH_MATCH) {
6483 if (vlan_num == 0) {
6484 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6485 return I40E_ERR_PARAM;
6487 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6488 filter_type == RTE_MAC_HASH_MATCH)
6491 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6493 PMD_DRV_LOG(ERR, "failed to allocate memory");
6494 return I40E_ERR_NO_MEMORY;
6497 for (i = 0; i < vlan_num; i++) {
6498 mv_f[i].filter_type = filter_type;
6499 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6502 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6503 filter_type == RTE_MACVLAN_HASH_MATCH) {
6504 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6505 if (ret != I40E_SUCCESS)
6509 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6510 if (ret != I40E_SUCCESS)
6513 /* Remove the mac addr into mac list */
6514 TAILQ_REMOVE(&vsi->mac_list, f, next);
6524 /* Configure hash enable flags for RSS */
6526 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6533 if (flags & ETH_RSS_FRAG_IPV4)
6534 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6535 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6536 if (type == I40E_MAC_X722) {
6537 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6538 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6540 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6542 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6543 if (type == I40E_MAC_X722) {
6544 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6545 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6546 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6548 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6550 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6551 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6552 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6553 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6554 if (flags & ETH_RSS_FRAG_IPV6)
6555 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6556 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6557 if (type == I40E_MAC_X722) {
6558 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6559 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6561 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6563 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6564 if (type == I40E_MAC_X722) {
6565 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6566 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6567 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6569 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6571 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6572 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6573 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6574 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6575 if (flags & ETH_RSS_L2_PAYLOAD)
6576 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6581 /* Parse the hash enable flags */
6583 i40e_parse_hena(uint64_t flags)
6585 uint64_t rss_hf = 0;
6589 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6590 rss_hf |= ETH_RSS_FRAG_IPV4;
6591 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6592 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6593 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6594 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6595 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6596 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6597 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6598 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6599 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6600 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6601 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6602 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6603 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6604 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6605 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6606 rss_hf |= ETH_RSS_FRAG_IPV6;
6607 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6608 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6609 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6610 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6611 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6612 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6613 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6614 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6615 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6616 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6617 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6618 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6619 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6620 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6621 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6622 rss_hf |= ETH_RSS_L2_PAYLOAD;
6629 i40e_pf_disable_rss(struct i40e_pf *pf)
6631 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6634 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6635 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6636 if (hw->mac.type == I40E_MAC_X722)
6637 hena &= ~I40E_RSS_HENA_ALL_X722;
6639 hena &= ~I40E_RSS_HENA_ALL;
6640 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6641 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6642 I40E_WRITE_FLUSH(hw);
6646 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6648 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6649 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6652 if (!key || key_len == 0) {
6653 PMD_DRV_LOG(DEBUG, "No key to be configured");
6655 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6657 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6661 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6662 struct i40e_aqc_get_set_rss_key_data *key_dw =
6663 (struct i40e_aqc_get_set_rss_key_data *)key;
6665 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6667 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6669 uint32_t *hash_key = (uint32_t *)key;
6672 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6673 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6674 I40E_WRITE_FLUSH(hw);
6681 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6683 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6684 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6687 if (!key || !key_len)
6690 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6691 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6692 (struct i40e_aqc_get_set_rss_key_data *)key);
6694 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6698 uint32_t *key_dw = (uint32_t *)key;
6701 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6702 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6704 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6710 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6712 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6717 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6718 rss_conf->rss_key_len);
6722 rss_hf = rss_conf->rss_hf;
6723 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6724 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6725 if (hw->mac.type == I40E_MAC_X722)
6726 hena &= ~I40E_RSS_HENA_ALL_X722;
6728 hena &= ~I40E_RSS_HENA_ALL;
6729 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6730 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6731 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6732 I40E_WRITE_FLUSH(hw);
6738 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6739 struct rte_eth_rss_conf *rss_conf)
6741 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6743 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6746 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6747 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6748 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6749 ? I40E_RSS_HENA_ALL_X722
6750 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6751 if (rss_hf != 0) /* Enable RSS */
6753 return 0; /* Nothing to do */
6756 if (rss_hf == 0) /* Disable RSS */
6759 return i40e_hw_rss_hash_set(pf, rss_conf);
6763 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6764 struct rte_eth_rss_conf *rss_conf)
6766 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6767 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6770 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6771 &rss_conf->rss_key_len);
6773 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6774 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6775 rss_conf->rss_hf = i40e_parse_hena(hena);
6781 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6783 switch (filter_type) {
6784 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6785 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6787 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6788 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6790 case RTE_TUNNEL_FILTER_IMAC_TENID:
6791 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6793 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6794 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6796 case ETH_TUNNEL_FILTER_IMAC:
6797 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6799 case ETH_TUNNEL_FILTER_OIP:
6800 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6802 case ETH_TUNNEL_FILTER_IIP:
6803 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6806 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6813 /* Convert tunnel filter structure */
6815 i40e_tunnel_filter_convert(
6816 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6817 struct i40e_tunnel_filter *tunnel_filter)
6819 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6820 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6821 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6822 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6823 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6824 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6825 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6826 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6827 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6829 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6830 tunnel_filter->input.flags = cld_filter->element.flags;
6831 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6832 tunnel_filter->queue = cld_filter->element.queue_number;
6833 rte_memcpy(tunnel_filter->input.general_fields,
6834 cld_filter->general_fields,
6835 sizeof(cld_filter->general_fields));
6840 /* Check if there exists the tunnel filter */
6841 struct i40e_tunnel_filter *
6842 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6843 const struct i40e_tunnel_filter_input *input)
6847 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6851 return tunnel_rule->hash_map[ret];
6854 /* Add a tunnel filter into the SW list */
6856 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6857 struct i40e_tunnel_filter *tunnel_filter)
6859 struct i40e_tunnel_rule *rule = &pf->tunnel;
6862 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6865 "Failed to insert tunnel filter to hash table %d!",
6869 rule->hash_map[ret] = tunnel_filter;
6871 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6876 /* Delete a tunnel filter from the SW list */
6878 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6879 struct i40e_tunnel_filter_input *input)
6881 struct i40e_tunnel_rule *rule = &pf->tunnel;
6882 struct i40e_tunnel_filter *tunnel_filter;
6885 ret = rte_hash_del_key(rule->hash_table, input);
6888 "Failed to delete tunnel filter to hash table %d!",
6892 tunnel_filter = rule->hash_map[ret];
6893 rule->hash_map[ret] = NULL;
6895 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6896 rte_free(tunnel_filter);
6902 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6903 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6908 uint8_t i, tun_type = 0;
6909 /* internal varialbe to convert ipv6 byte order */
6910 uint32_t convert_ipv6[4];
6912 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6913 struct i40e_vsi *vsi = pf->main_vsi;
6914 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6915 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6916 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6917 struct i40e_tunnel_filter *tunnel, *node;
6918 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6920 cld_filter = rte_zmalloc("tunnel_filter",
6921 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6924 if (NULL == cld_filter) {
6925 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6928 pfilter = cld_filter;
6930 ether_addr_copy(&tunnel_filter->outer_mac,
6931 (struct ether_addr *)&pfilter->element.outer_mac);
6932 ether_addr_copy(&tunnel_filter->inner_mac,
6933 (struct ether_addr *)&pfilter->element.inner_mac);
6935 pfilter->element.inner_vlan =
6936 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6937 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6938 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6939 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6940 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6941 &rte_cpu_to_le_32(ipv4_addr),
6942 sizeof(pfilter->element.ipaddr.v4.data));
6944 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6945 for (i = 0; i < 4; i++) {
6947 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6949 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6951 sizeof(pfilter->element.ipaddr.v6.data));
6954 /* check tunneled type */
6955 switch (tunnel_filter->tunnel_type) {
6956 case RTE_TUNNEL_TYPE_VXLAN:
6957 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6959 case RTE_TUNNEL_TYPE_NVGRE:
6960 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6962 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6963 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6966 /* Other tunnel types is not supported. */
6967 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6968 rte_free(cld_filter);
6972 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6973 &pfilter->element.flags);
6975 rte_free(cld_filter);
6979 pfilter->element.flags |= rte_cpu_to_le_16(
6980 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6981 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6982 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6983 pfilter->element.queue_number =
6984 rte_cpu_to_le_16(tunnel_filter->queue_id);
6986 /* Check if there is the filter in SW list */
6987 memset(&check_filter, 0, sizeof(check_filter));
6988 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6989 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6991 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6995 if (!add && !node) {
6996 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7001 ret = i40e_aq_add_cloud_filters(hw,
7002 vsi->seid, &cld_filter->element, 1);
7004 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7007 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7008 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7009 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7011 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7012 &cld_filter->element, 1);
7014 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7017 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7020 rte_free(cld_filter);
7024 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7025 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7026 #define I40E_TR_GENEVE_KEY_MASK 0x8
7027 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7028 #define I40E_TR_GRE_KEY_MASK 0x400
7029 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7030 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7033 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7035 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7036 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7037 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7038 enum i40e_status_code status = I40E_SUCCESS;
7040 memset(&filter_replace, 0,
7041 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7042 memset(&filter_replace_buf, 0,
7043 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7045 /* create L1 filter */
7046 filter_replace.old_filter_type =
7047 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7048 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7049 filter_replace.tr_bit = 0;
7051 /* Prepare the buffer, 3 entries */
7052 filter_replace_buf.data[0] =
7053 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7054 filter_replace_buf.data[0] |=
7055 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7056 filter_replace_buf.data[2] = 0xFF;
7057 filter_replace_buf.data[3] = 0xFF;
7058 filter_replace_buf.data[4] =
7059 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7060 filter_replace_buf.data[4] |=
7061 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7062 filter_replace_buf.data[7] = 0xF0;
7063 filter_replace_buf.data[8]
7064 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7065 filter_replace_buf.data[8] |=
7066 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7067 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7068 I40E_TR_GENEVE_KEY_MASK |
7069 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7070 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7071 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7072 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7074 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7075 &filter_replace_buf);
7080 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7082 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7083 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7084 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7085 enum i40e_status_code status = I40E_SUCCESS;
7088 memset(&filter_replace, 0,
7089 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7090 memset(&filter_replace_buf, 0,
7091 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7092 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7093 I40E_AQC_MIRROR_CLOUD_FILTER;
7094 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7095 filter_replace.new_filter_type =
7096 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7097 /* Prepare the buffer, 2 entries */
7098 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7099 filter_replace_buf.data[0] |=
7100 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7101 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7102 filter_replace_buf.data[4] |=
7103 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7104 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7105 &filter_replace_buf);
7110 memset(&filter_replace, 0,
7111 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7112 memset(&filter_replace_buf, 0,
7113 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7115 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7116 I40E_AQC_MIRROR_CLOUD_FILTER;
7117 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7118 filter_replace.new_filter_type =
7119 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7120 /* Prepare the buffer, 2 entries */
7121 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7122 filter_replace_buf.data[0] |=
7123 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7124 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7125 filter_replace_buf.data[4] |=
7126 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7128 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7129 &filter_replace_buf);
7134 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7135 struct i40e_tunnel_filter_conf *tunnel_filter,
7140 uint8_t i, tun_type = 0;
7141 /* internal variable to convert ipv6 byte order */
7142 uint32_t convert_ipv6[4];
7144 struct i40e_pf_vf *vf = NULL;
7145 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7146 struct i40e_vsi *vsi;
7147 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7148 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7149 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7150 struct i40e_tunnel_filter *tunnel, *node;
7151 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7153 bool big_buffer = 0;
7155 cld_filter = rte_zmalloc("tunnel_filter",
7156 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7159 if (cld_filter == NULL) {
7160 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7163 pfilter = cld_filter;
7165 ether_addr_copy(&tunnel_filter->outer_mac,
7166 (struct ether_addr *)&pfilter->element.outer_mac);
7167 ether_addr_copy(&tunnel_filter->inner_mac,
7168 (struct ether_addr *)&pfilter->element.inner_mac);
7170 pfilter->element.inner_vlan =
7171 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7172 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7173 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7174 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7175 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7176 &rte_cpu_to_le_32(ipv4_addr),
7177 sizeof(pfilter->element.ipaddr.v4.data));
7179 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7180 for (i = 0; i < 4; i++) {
7182 rte_cpu_to_le_32(rte_be_to_cpu_32(
7183 tunnel_filter->ip_addr.ipv6_addr[i]));
7185 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7187 sizeof(pfilter->element.ipaddr.v6.data));
7190 /* check tunneled type */
7191 switch (tunnel_filter->tunnel_type) {
7192 case I40E_TUNNEL_TYPE_VXLAN:
7193 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7195 case I40E_TUNNEL_TYPE_NVGRE:
7196 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7198 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7199 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7201 case I40E_TUNNEL_TYPE_MPLSoUDP:
7202 if (!pf->mpls_replace_flag) {
7203 i40e_replace_mpls_l1_filter(pf);
7204 i40e_replace_mpls_cloud_filter(pf);
7205 pf->mpls_replace_flag = 1;
7207 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7208 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7210 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7211 (teid_le & 0xF) << 12;
7212 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7215 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7217 case I40E_TUNNEL_TYPE_MPLSoGRE:
7218 if (!pf->mpls_replace_flag) {
7219 i40e_replace_mpls_l1_filter(pf);
7220 i40e_replace_mpls_cloud_filter(pf);
7221 pf->mpls_replace_flag = 1;
7223 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7224 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7226 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7227 (teid_le & 0xF) << 12;
7228 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7231 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7233 case I40E_TUNNEL_TYPE_QINQ:
7234 if (!pf->qinq_replace_flag) {
7235 ret = i40e_cloud_filter_qinq_create(pf);
7238 "QinQ tunnel filter already created.");
7239 pf->qinq_replace_flag = 1;
7241 /* Add in the General fields the values of
7242 * the Outer and Inner VLAN
7243 * Big Buffer should be set, see changes in
7244 * i40e_aq_add_cloud_filters
7246 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7247 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7251 /* Other tunnel types is not supported. */
7252 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7253 rte_free(cld_filter);
7257 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7258 pfilter->element.flags =
7259 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7260 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7261 pfilter->element.flags =
7262 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7263 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7264 pfilter->element.flags |=
7265 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7267 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7268 &pfilter->element.flags);
7270 rte_free(cld_filter);
7275 pfilter->element.flags |= rte_cpu_to_le_16(
7276 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7277 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7278 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7279 pfilter->element.queue_number =
7280 rte_cpu_to_le_16(tunnel_filter->queue_id);
7282 if (!tunnel_filter->is_to_vf)
7285 if (tunnel_filter->vf_id >= pf->vf_num) {
7286 PMD_DRV_LOG(ERR, "Invalid argument.");
7289 vf = &pf->vfs[tunnel_filter->vf_id];
7293 /* Check if there is the filter in SW list */
7294 memset(&check_filter, 0, sizeof(check_filter));
7295 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7296 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7297 check_filter.vf_id = tunnel_filter->vf_id;
7298 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7300 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7304 if (!add && !node) {
7305 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7311 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7312 vsi->seid, cld_filter, 1);
7314 ret = i40e_aq_add_cloud_filters(hw,
7315 vsi->seid, &cld_filter->element, 1);
7317 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7320 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7321 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7322 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7325 ret = i40e_aq_remove_cloud_filters_big_buffer(
7326 hw, vsi->seid, cld_filter, 1);
7328 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7329 &cld_filter->element, 1);
7331 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7334 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7337 rte_free(cld_filter);
7342 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7346 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7347 if (pf->vxlan_ports[i] == port)
7355 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7359 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7361 idx = i40e_get_vxlan_port_idx(pf, port);
7363 /* Check if port already exists */
7365 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7369 /* Now check if there is space to add the new port */
7370 idx = i40e_get_vxlan_port_idx(pf, 0);
7373 "Maximum number of UDP ports reached, not adding port %d",
7378 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7381 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7385 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7388 /* New port: add it and mark its index in the bitmap */
7389 pf->vxlan_ports[idx] = port;
7390 pf->vxlan_bitmap |= (1 << idx);
7392 if (!(pf->flags & I40E_FLAG_VXLAN))
7393 pf->flags |= I40E_FLAG_VXLAN;
7399 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7402 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7404 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7405 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7409 idx = i40e_get_vxlan_port_idx(pf, port);
7412 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7416 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7417 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7421 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7424 pf->vxlan_ports[idx] = 0;
7425 pf->vxlan_bitmap &= ~(1 << idx);
7427 if (!pf->vxlan_bitmap)
7428 pf->flags &= ~I40E_FLAG_VXLAN;
7433 /* Add UDP tunneling port */
7435 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7436 struct rte_eth_udp_tunnel *udp_tunnel)
7439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7441 if (udp_tunnel == NULL)
7444 switch (udp_tunnel->prot_type) {
7445 case RTE_TUNNEL_TYPE_VXLAN:
7446 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7449 case RTE_TUNNEL_TYPE_GENEVE:
7450 case RTE_TUNNEL_TYPE_TEREDO:
7451 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7456 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7464 /* Remove UDP tunneling port */
7466 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7467 struct rte_eth_udp_tunnel *udp_tunnel)
7470 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7472 if (udp_tunnel == NULL)
7475 switch (udp_tunnel->prot_type) {
7476 case RTE_TUNNEL_TYPE_VXLAN:
7477 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7479 case RTE_TUNNEL_TYPE_GENEVE:
7480 case RTE_TUNNEL_TYPE_TEREDO:
7481 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7485 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7493 /* Calculate the maximum number of contiguous PF queues that are configured */
7495 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7497 struct rte_eth_dev_data *data = pf->dev_data;
7499 struct i40e_rx_queue *rxq;
7502 for (i = 0; i < pf->lan_nb_qps; i++) {
7503 rxq = data->rx_queues[i];
7504 if (rxq && rxq->q_set)
7515 i40e_pf_config_rss(struct i40e_pf *pf)
7517 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7518 struct rte_eth_rss_conf rss_conf;
7519 uint32_t i, lut = 0;
7523 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7524 * It's necessary to calculate the actual PF queues that are configured.
7526 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7527 num = i40e_pf_calc_configured_queues_num(pf);
7529 num = pf->dev_data->nb_rx_queues;
7531 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7532 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7536 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7540 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7543 lut = (lut << 8) | (j & ((0x1 <<
7544 hw->func_caps.rss_table_entry_width) - 1));
7546 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7549 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7550 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7551 i40e_pf_disable_rss(pf);
7554 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7555 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7556 /* Random default keys */
7557 static uint32_t rss_key_default[] = {0x6b793944,
7558 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7559 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7560 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7562 rss_conf.rss_key = (uint8_t *)rss_key_default;
7563 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7567 return i40e_hw_rss_hash_set(pf, &rss_conf);
7571 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7572 struct rte_eth_tunnel_filter_conf *filter)
7574 if (pf == NULL || filter == NULL) {
7575 PMD_DRV_LOG(ERR, "Invalid parameter");
7579 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7580 PMD_DRV_LOG(ERR, "Invalid queue ID");
7584 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7585 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7589 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7590 (is_zero_ether_addr(&filter->outer_mac))) {
7591 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7595 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7596 (is_zero_ether_addr(&filter->inner_mac))) {
7597 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7604 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7605 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7607 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7612 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7613 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7616 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7617 } else if (len == 4) {
7618 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7620 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7625 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7632 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7633 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7639 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7646 switch (cfg->cfg_type) {
7647 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7648 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7651 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7659 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7660 enum rte_filter_op filter_op,
7663 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7664 int ret = I40E_ERR_PARAM;
7666 switch (filter_op) {
7667 case RTE_ETH_FILTER_SET:
7668 ret = i40e_dev_global_config_set(hw,
7669 (struct rte_eth_global_cfg *)arg);
7672 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7680 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7681 enum rte_filter_op filter_op,
7684 struct rte_eth_tunnel_filter_conf *filter;
7685 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7686 int ret = I40E_SUCCESS;
7688 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7690 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7691 return I40E_ERR_PARAM;
7693 switch (filter_op) {
7694 case RTE_ETH_FILTER_NOP:
7695 if (!(pf->flags & I40E_FLAG_VXLAN))
7696 ret = I40E_NOT_SUPPORTED;
7698 case RTE_ETH_FILTER_ADD:
7699 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7701 case RTE_ETH_FILTER_DELETE:
7702 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7705 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7706 ret = I40E_ERR_PARAM;
7714 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7717 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7720 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7721 ret = i40e_pf_config_rss(pf);
7723 i40e_pf_disable_rss(pf);
7728 /* Get the symmetric hash enable configurations per port */
7730 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7732 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7734 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7737 /* Set the symmetric hash enable configurations per port */
7739 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7741 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7744 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7746 "Symmetric hash has already been enabled");
7749 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7751 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7753 "Symmetric hash has already been disabled");
7756 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7758 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7759 I40E_WRITE_FLUSH(hw);
7763 * Get global configurations of hash function type and symmetric hash enable
7764 * per flow type (pctype). Note that global configuration means it affects all
7765 * the ports on the same NIC.
7768 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7769 struct rte_eth_hash_global_conf *g_cfg)
7771 uint32_t reg, mask = I40E_FLOW_TYPES;
7773 enum i40e_filter_pctype pctype;
7775 memset(g_cfg, 0, sizeof(*g_cfg));
7776 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7777 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7778 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7780 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7781 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7782 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7784 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7785 if (!(mask & (1UL << i)))
7787 mask &= ~(1UL << i);
7788 /* Bit set indicats the coresponding flow type is supported */
7789 g_cfg->valid_bit_mask[0] |= (1UL << i);
7790 /* if flowtype is invalid, continue */
7791 if (!I40E_VALID_FLOW(i))
7793 pctype = i40e_flowtype_to_pctype(i);
7794 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7795 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7796 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7803 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7806 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7808 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7809 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7810 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7811 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7817 * As i40e supports less than 32 flow types, only first 32 bits need to
7820 mask0 = g_cfg->valid_bit_mask[0];
7821 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7823 /* Check if any unsupported flow type configured */
7824 if ((mask0 | i40e_mask) ^ i40e_mask)
7827 if (g_cfg->valid_bit_mask[i])
7835 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7841 * Set global configurations of hash function type and symmetric hash enable
7842 * per flow type (pctype). Note any modifying global configuration will affect
7843 * all the ports on the same NIC.
7846 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7847 struct rte_eth_hash_global_conf *g_cfg)
7852 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7853 enum i40e_filter_pctype pctype;
7855 /* Check the input parameters */
7856 ret = i40e_hash_global_config_check(g_cfg);
7860 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7861 if (!(mask0 & (1UL << i)))
7863 mask0 &= ~(1UL << i);
7864 /* if flowtype is invalid, continue */
7865 if (!I40E_VALID_FLOW(i))
7867 pctype = i40e_flowtype_to_pctype(i);
7868 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7869 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7870 if (hw->mac.type == I40E_MAC_X722) {
7871 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7872 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7873 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7874 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7875 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7877 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7878 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7880 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7881 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7882 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7883 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7884 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7886 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7887 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7888 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7889 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7890 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7892 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7893 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7895 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7896 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7897 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7898 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7899 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7902 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7906 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7910 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7911 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7913 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7915 "Hash function already set to Toeplitz");
7918 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7919 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7921 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7923 "Hash function already set to Simple XOR");
7926 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7928 /* Use the default, and keep it as it is */
7931 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7934 I40E_WRITE_FLUSH(hw);
7940 * Valid input sets for hash and flow director filters per PCTYPE
7943 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7944 enum rte_filter_type filter)
7948 static const uint64_t valid_hash_inset_table[] = {
7949 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7950 I40E_INSET_DMAC | I40E_INSET_SMAC |
7951 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7952 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7953 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7954 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7955 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7956 I40E_INSET_FLEX_PAYLOAD,
7957 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7958 I40E_INSET_DMAC | I40E_INSET_SMAC |
7959 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7960 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7961 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7962 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7963 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7964 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7965 I40E_INSET_FLEX_PAYLOAD,
7966 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7967 I40E_INSET_DMAC | I40E_INSET_SMAC |
7968 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7969 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7970 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7971 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7972 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7973 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7974 I40E_INSET_FLEX_PAYLOAD,
7975 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7976 I40E_INSET_DMAC | I40E_INSET_SMAC |
7977 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7978 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7979 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7980 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7981 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7982 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7983 I40E_INSET_FLEX_PAYLOAD,
7984 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7985 I40E_INSET_DMAC | I40E_INSET_SMAC |
7986 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7987 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7988 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7989 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7990 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7991 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7992 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7993 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7994 I40E_INSET_DMAC | I40E_INSET_SMAC |
7995 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7996 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7997 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7998 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7999 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8000 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8001 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8002 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8003 I40E_INSET_DMAC | I40E_INSET_SMAC |
8004 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8005 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8006 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8007 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8008 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8009 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8010 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8011 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8012 I40E_INSET_DMAC | I40E_INSET_SMAC |
8013 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8014 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8015 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8016 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8017 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8018 I40E_INSET_FLEX_PAYLOAD,
8019 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8020 I40E_INSET_DMAC | I40E_INSET_SMAC |
8021 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8022 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8023 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8024 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8025 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8026 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8027 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8028 I40E_INSET_DMAC | I40E_INSET_SMAC |
8029 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8030 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8031 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8032 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8033 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8034 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8035 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8036 I40E_INSET_DMAC | I40E_INSET_SMAC |
8037 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8038 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8039 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8040 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8041 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8042 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8043 I40E_INSET_FLEX_PAYLOAD,
8044 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8045 I40E_INSET_DMAC | I40E_INSET_SMAC |
8046 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8047 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8048 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8049 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8050 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8051 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8052 I40E_INSET_FLEX_PAYLOAD,
8053 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8054 I40E_INSET_DMAC | I40E_INSET_SMAC |
8055 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8056 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8057 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8058 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8059 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8060 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8061 I40E_INSET_FLEX_PAYLOAD,
8062 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8063 I40E_INSET_DMAC | I40E_INSET_SMAC |
8064 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8065 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8066 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8067 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8068 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8069 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8070 I40E_INSET_FLEX_PAYLOAD,
8071 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8072 I40E_INSET_DMAC | I40E_INSET_SMAC |
8073 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8074 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8075 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8076 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8077 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8078 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8079 I40E_INSET_FLEX_PAYLOAD,
8080 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8081 I40E_INSET_DMAC | I40E_INSET_SMAC |
8082 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8083 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8084 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8085 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8086 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8087 I40E_INSET_FLEX_PAYLOAD,
8088 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8089 I40E_INSET_DMAC | I40E_INSET_SMAC |
8090 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8091 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8092 I40E_INSET_FLEX_PAYLOAD,
8096 * Flow director supports only fields defined in
8097 * union rte_eth_fdir_flow.
8099 static const uint64_t valid_fdir_inset_table[] = {
8100 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8101 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8102 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8103 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8104 I40E_INSET_IPV4_TTL,
8105 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8106 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8107 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8108 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8109 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8110 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8111 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8112 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8113 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8114 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8115 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8116 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8117 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8118 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8119 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8120 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8121 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8122 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8123 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8124 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8125 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8126 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8127 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8128 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8129 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8130 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8131 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8132 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8133 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8134 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8136 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8137 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8138 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8139 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8140 I40E_INSET_IPV4_TTL,
8141 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8142 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8143 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8144 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8145 I40E_INSET_IPV6_HOP_LIMIT,
8146 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8147 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8148 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8149 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8150 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8151 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8152 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8153 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8154 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8155 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8156 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8157 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8158 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8159 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8160 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8161 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8162 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8163 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8164 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8165 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8166 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8167 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8168 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8169 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8170 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8171 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8172 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8173 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8174 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8175 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8177 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8178 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8179 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8180 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8181 I40E_INSET_IPV6_HOP_LIMIT,
8182 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8183 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8184 I40E_INSET_LAST_ETHER_TYPE,
8187 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8189 if (filter == RTE_ETH_FILTER_HASH)
8190 valid = valid_hash_inset_table[pctype];
8192 valid = valid_fdir_inset_table[pctype];
8198 * Validate if the input set is allowed for a specific PCTYPE
8201 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8202 enum rte_filter_type filter, uint64_t inset)
8206 valid = i40e_get_valid_input_set(pctype, filter);
8207 if (inset & (~valid))
8213 /* default input set fields combination per pctype */
8215 i40e_get_default_input_set(uint16_t pctype)
8217 static const uint64_t default_inset_table[] = {
8218 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8219 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8220 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8221 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8222 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8223 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8224 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8225 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8226 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8227 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8228 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8229 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8230 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8231 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8232 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8233 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8234 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8235 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8236 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8237 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8239 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8240 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8241 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8242 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8243 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8244 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8245 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8246 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8247 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8248 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8249 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8250 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8251 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8252 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8253 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8254 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8255 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8256 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8257 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8258 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8259 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8260 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8262 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8263 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8264 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8265 I40E_INSET_LAST_ETHER_TYPE,
8268 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8271 return default_inset_table[pctype];
8275 * Parse the input set from index to logical bit masks
8278 i40e_parse_input_set(uint64_t *inset,
8279 enum i40e_filter_pctype pctype,
8280 enum rte_eth_input_set_field *field,
8286 static const struct {
8287 enum rte_eth_input_set_field field;
8289 } inset_convert_table[] = {
8290 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8291 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8292 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8293 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8294 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8295 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8296 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8297 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8298 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8299 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8300 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8301 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8302 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8303 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8304 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8305 I40E_INSET_IPV6_NEXT_HDR},
8306 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8307 I40E_INSET_IPV6_HOP_LIMIT},
8308 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8309 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8310 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8311 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8312 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8313 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8314 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8315 I40E_INSET_SCTP_VT},
8316 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8317 I40E_INSET_TUNNEL_DMAC},
8318 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8319 I40E_INSET_VLAN_TUNNEL},
8320 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8321 I40E_INSET_TUNNEL_ID},
8322 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8323 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8324 I40E_INSET_FLEX_PAYLOAD_W1},
8325 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8326 I40E_INSET_FLEX_PAYLOAD_W2},
8327 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8328 I40E_INSET_FLEX_PAYLOAD_W3},
8329 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8330 I40E_INSET_FLEX_PAYLOAD_W4},
8331 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8332 I40E_INSET_FLEX_PAYLOAD_W5},
8333 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8334 I40E_INSET_FLEX_PAYLOAD_W6},
8335 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8336 I40E_INSET_FLEX_PAYLOAD_W7},
8337 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8338 I40E_INSET_FLEX_PAYLOAD_W8},
8341 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8344 /* Only one item allowed for default or all */
8346 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8347 *inset = i40e_get_default_input_set(pctype);
8349 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8350 *inset = I40E_INSET_NONE;
8355 for (i = 0, *inset = 0; i < size; i++) {
8356 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8357 if (field[i] == inset_convert_table[j].field) {
8358 *inset |= inset_convert_table[j].inset;
8363 /* It contains unsupported input set, return immediately */
8364 if (j == RTE_DIM(inset_convert_table))
8372 * Translate the input set from bit masks to register aware bit masks
8376 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8386 static const struct inset_map inset_map_common[] = {
8387 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8388 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8389 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8390 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8391 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8392 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8393 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8394 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8395 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8396 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8397 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8398 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8399 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8400 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8401 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8402 {I40E_INSET_TUNNEL_DMAC,
8403 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8404 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8405 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8406 {I40E_INSET_TUNNEL_SRC_PORT,
8407 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8408 {I40E_INSET_TUNNEL_DST_PORT,
8409 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8410 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8411 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8412 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8413 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8414 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8415 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8416 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8417 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8418 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8421 /* some different registers map in x722*/
8422 static const struct inset_map inset_map_diff_x722[] = {
8423 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8424 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8425 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8426 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8429 static const struct inset_map inset_map_diff_not_x722[] = {
8430 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8431 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8432 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8433 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8439 /* Translate input set to register aware inset */
8440 if (type == I40E_MAC_X722) {
8441 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8442 if (input & inset_map_diff_x722[i].inset)
8443 val |= inset_map_diff_x722[i].inset_reg;
8446 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8447 if (input & inset_map_diff_not_x722[i].inset)
8448 val |= inset_map_diff_not_x722[i].inset_reg;
8452 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8453 if (input & inset_map_common[i].inset)
8454 val |= inset_map_common[i].inset_reg;
8461 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8464 uint64_t inset_need_mask = inset;
8466 static const struct {
8469 } inset_mask_map[] = {
8470 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8471 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8472 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8473 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8474 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8475 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8476 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8477 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8480 if (!inset || !mask || !nb_elem)
8483 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8484 /* Clear the inset bit, if no MASK is required,
8485 * for example proto + ttl
8487 if ((inset & inset_mask_map[i].inset) ==
8488 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8489 inset_need_mask &= ~inset_mask_map[i].inset;
8490 if (!inset_need_mask)
8493 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8494 if ((inset_need_mask & inset_mask_map[i].inset) ==
8495 inset_mask_map[i].inset) {
8496 if (idx >= nb_elem) {
8497 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8500 mask[idx] = inset_mask_map[i].mask;
8509 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8511 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8513 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8515 i40e_write_rx_ctl(hw, addr, val);
8516 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8517 (uint32_t)i40e_read_rx_ctl(hw, addr));
8521 i40e_filter_input_set_init(struct i40e_pf *pf)
8523 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8524 enum i40e_filter_pctype pctype;
8525 uint64_t input_set, inset_reg;
8526 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8529 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8530 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8531 if (hw->mac.type == I40E_MAC_X722) {
8532 if (!I40E_VALID_PCTYPE_X722(pctype))
8535 if (!I40E_VALID_PCTYPE(pctype))
8539 input_set = i40e_get_default_input_set(pctype);
8541 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8542 I40E_INSET_MASK_NUM_REG);
8545 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8548 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8549 (uint32_t)(inset_reg & UINT32_MAX));
8550 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8551 (uint32_t)((inset_reg >>
8552 I40E_32_BIT_WIDTH) & UINT32_MAX));
8553 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8554 (uint32_t)(inset_reg & UINT32_MAX));
8555 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8556 (uint32_t)((inset_reg >>
8557 I40E_32_BIT_WIDTH) & UINT32_MAX));
8559 for (i = 0; i < num; i++) {
8560 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8562 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8565 /*clear unused mask registers of the pctype */
8566 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8567 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8569 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8572 I40E_WRITE_FLUSH(hw);
8574 /* store the default input set */
8575 pf->hash_input_set[pctype] = input_set;
8576 pf->fdir.input_set[pctype] = input_set;
8581 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8582 struct rte_eth_input_set_conf *conf)
8584 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8585 enum i40e_filter_pctype pctype;
8586 uint64_t input_set, inset_reg = 0;
8587 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8591 PMD_DRV_LOG(ERR, "Invalid pointer");
8594 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8595 conf->op != RTE_ETH_INPUT_SET_ADD) {
8596 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8600 if (!I40E_VALID_FLOW(conf->flow_type)) {
8601 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8605 if (hw->mac.type == I40E_MAC_X722) {
8606 /* get translated pctype value in fd pctype register */
8607 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8608 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8611 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8613 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8616 PMD_DRV_LOG(ERR, "Failed to parse input set");
8619 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8621 PMD_DRV_LOG(ERR, "Invalid input set");
8624 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8625 /* get inset value in register */
8626 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8627 inset_reg <<= I40E_32_BIT_WIDTH;
8628 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8629 input_set |= pf->hash_input_set[pctype];
8631 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8632 I40E_INSET_MASK_NUM_REG);
8636 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8638 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8639 (uint32_t)(inset_reg & UINT32_MAX));
8640 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8641 (uint32_t)((inset_reg >>
8642 I40E_32_BIT_WIDTH) & UINT32_MAX));
8644 for (i = 0; i < num; i++)
8645 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8647 /*clear unused mask registers of the pctype */
8648 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8649 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8651 I40E_WRITE_FLUSH(hw);
8653 pf->hash_input_set[pctype] = input_set;
8658 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8659 struct rte_eth_input_set_conf *conf)
8661 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8662 enum i40e_filter_pctype pctype;
8663 uint64_t input_set, inset_reg = 0;
8664 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8668 PMD_DRV_LOG(ERR, "Invalid pointer");
8671 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8672 conf->op != RTE_ETH_INPUT_SET_ADD) {
8673 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8677 if (!I40E_VALID_FLOW(conf->flow_type)) {
8678 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8682 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8684 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8687 PMD_DRV_LOG(ERR, "Failed to parse input set");
8690 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8692 PMD_DRV_LOG(ERR, "Invalid input set");
8696 /* get inset value in register */
8697 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8698 inset_reg <<= I40E_32_BIT_WIDTH;
8699 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8701 /* Can not change the inset reg for flex payload for fdir,
8702 * it is done by writing I40E_PRTQF_FD_FLXINSET
8703 * in i40e_set_flex_mask_on_pctype.
8705 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8706 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8708 input_set |= pf->fdir.input_set[pctype];
8709 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8710 I40E_INSET_MASK_NUM_REG);
8714 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8716 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8717 (uint32_t)(inset_reg & UINT32_MAX));
8718 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8719 (uint32_t)((inset_reg >>
8720 I40E_32_BIT_WIDTH) & UINT32_MAX));
8722 for (i = 0; i < num; i++)
8723 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8725 /*clear unused mask registers of the pctype */
8726 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8727 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8729 I40E_WRITE_FLUSH(hw);
8731 pf->fdir.input_set[pctype] = input_set;
8736 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8741 PMD_DRV_LOG(ERR, "Invalid pointer");
8745 switch (info->info_type) {
8746 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8747 i40e_get_symmetric_hash_enable_per_port(hw,
8748 &(info->info.enable));
8750 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8751 ret = i40e_get_hash_filter_global_config(hw,
8752 &(info->info.global_conf));
8755 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8765 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8770 PMD_DRV_LOG(ERR, "Invalid pointer");
8774 switch (info->info_type) {
8775 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8776 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8778 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8779 ret = i40e_set_hash_filter_global_config(hw,
8780 &(info->info.global_conf));
8782 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8783 ret = i40e_hash_filter_inset_select(hw,
8784 &(info->info.input_set_conf));
8788 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8797 /* Operations for hash function */
8799 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8800 enum rte_filter_op filter_op,
8803 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8806 switch (filter_op) {
8807 case RTE_ETH_FILTER_NOP:
8809 case RTE_ETH_FILTER_GET:
8810 ret = i40e_hash_filter_get(hw,
8811 (struct rte_eth_hash_filter_info *)arg);
8813 case RTE_ETH_FILTER_SET:
8814 ret = i40e_hash_filter_set(hw,
8815 (struct rte_eth_hash_filter_info *)arg);
8818 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8827 /* Convert ethertype filter structure */
8829 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8830 struct i40e_ethertype_filter *filter)
8832 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8833 filter->input.ether_type = input->ether_type;
8834 filter->flags = input->flags;
8835 filter->queue = input->queue;
8840 /* Check if there exists the ehtertype filter */
8841 struct i40e_ethertype_filter *
8842 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8843 const struct i40e_ethertype_filter_input *input)
8847 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8851 return ethertype_rule->hash_map[ret];
8854 /* Add ethertype filter in SW list */
8856 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8857 struct i40e_ethertype_filter *filter)
8859 struct i40e_ethertype_rule *rule = &pf->ethertype;
8862 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8865 "Failed to insert ethertype filter"
8866 " to hash table %d!",
8870 rule->hash_map[ret] = filter;
8872 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8877 /* Delete ethertype filter in SW list */
8879 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8880 struct i40e_ethertype_filter_input *input)
8882 struct i40e_ethertype_rule *rule = &pf->ethertype;
8883 struct i40e_ethertype_filter *filter;
8886 ret = rte_hash_del_key(rule->hash_table, input);
8889 "Failed to delete ethertype filter"
8890 " to hash table %d!",
8894 filter = rule->hash_map[ret];
8895 rule->hash_map[ret] = NULL;
8897 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8904 * Configure ethertype filter, which can director packet by filtering
8905 * with mac address and ether_type or only ether_type
8908 i40e_ethertype_filter_set(struct i40e_pf *pf,
8909 struct rte_eth_ethertype_filter *filter,
8912 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8913 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8914 struct i40e_ethertype_filter *ethertype_filter, *node;
8915 struct i40e_ethertype_filter check_filter;
8916 struct i40e_control_filter_stats stats;
8920 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8921 PMD_DRV_LOG(ERR, "Invalid queue ID");
8924 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8925 filter->ether_type == ETHER_TYPE_IPv6) {
8927 "unsupported ether_type(0x%04x) in control packet filter.",
8928 filter->ether_type);
8931 if (filter->ether_type == ETHER_TYPE_VLAN)
8932 PMD_DRV_LOG(WARNING,
8933 "filter vlan ether_type in first tag is not supported.");
8935 /* Check if there is the filter in SW list */
8936 memset(&check_filter, 0, sizeof(check_filter));
8937 i40e_ethertype_filter_convert(filter, &check_filter);
8938 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8939 &check_filter.input);
8941 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8945 if (!add && !node) {
8946 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8950 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8951 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8952 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8953 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8954 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8956 memset(&stats, 0, sizeof(stats));
8957 ret = i40e_aq_add_rem_control_packet_filter(hw,
8958 filter->mac_addr.addr_bytes,
8959 filter->ether_type, flags,
8961 filter->queue, add, &stats, NULL);
8964 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8965 ret, stats.mac_etype_used, stats.etype_used,
8966 stats.mac_etype_free, stats.etype_free);
8970 /* Add or delete a filter in SW list */
8972 ethertype_filter = rte_zmalloc("ethertype_filter",
8973 sizeof(*ethertype_filter), 0);
8974 rte_memcpy(ethertype_filter, &check_filter,
8975 sizeof(check_filter));
8976 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8978 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8985 * Handle operations for ethertype filter.
8988 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8989 enum rte_filter_op filter_op,
8992 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8995 if (filter_op == RTE_ETH_FILTER_NOP)
8999 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9004 switch (filter_op) {
9005 case RTE_ETH_FILTER_ADD:
9006 ret = i40e_ethertype_filter_set(pf,
9007 (struct rte_eth_ethertype_filter *)arg,
9010 case RTE_ETH_FILTER_DELETE:
9011 ret = i40e_ethertype_filter_set(pf,
9012 (struct rte_eth_ethertype_filter *)arg,
9016 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9024 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9025 enum rte_filter_type filter_type,
9026 enum rte_filter_op filter_op,
9034 switch (filter_type) {
9035 case RTE_ETH_FILTER_NONE:
9036 /* For global configuration */
9037 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9039 case RTE_ETH_FILTER_HASH:
9040 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9042 case RTE_ETH_FILTER_MACVLAN:
9043 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9045 case RTE_ETH_FILTER_ETHERTYPE:
9046 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9048 case RTE_ETH_FILTER_TUNNEL:
9049 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9051 case RTE_ETH_FILTER_FDIR:
9052 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9054 case RTE_ETH_FILTER_GENERIC:
9055 if (filter_op != RTE_ETH_FILTER_GET)
9057 *(const void **)arg = &i40e_flow_ops;
9060 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9070 * Check and enable Extended Tag.
9071 * Enabling Extended Tag is important for 40G performance.
9074 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9076 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9080 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9083 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9087 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9088 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9093 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9096 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9100 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9101 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9104 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9105 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9108 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9115 * As some registers wouldn't be reset unless a global hardware reset,
9116 * hardware initialization is needed to put those registers into an
9117 * expected initial state.
9120 i40e_hw_init(struct rte_eth_dev *dev)
9122 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9124 i40e_enable_extended_tag(dev);
9126 /* clear the PF Queue Filter control register */
9127 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9129 /* Disable symmetric hash per port */
9130 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9133 enum i40e_filter_pctype
9134 i40e_flowtype_to_pctype(uint16_t flow_type)
9136 static const enum i40e_filter_pctype pctype_table[] = {
9137 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9138 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9139 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9140 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9141 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9142 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9143 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9144 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9145 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9146 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9147 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9148 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9149 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9150 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9151 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9152 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9153 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9154 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9155 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9158 return pctype_table[flow_type];
9162 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9164 static const uint16_t flowtype_table[] = {
9165 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9166 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9167 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9168 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9169 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9170 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9171 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9172 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9173 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9174 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9175 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9176 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9177 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9178 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9179 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9180 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9181 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9182 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9183 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9184 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9185 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9186 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9187 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9188 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9189 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9190 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9191 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9192 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9193 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9194 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9195 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9198 return flowtype_table[pctype];
9202 * On X710, performance number is far from the expectation on recent firmware
9203 * versions; on XL710, performance number is also far from the expectation on
9204 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9205 * mode is enabled and port MAC address is equal to the packet destination MAC
9206 * address. The fix for this issue may not be integrated in the following
9207 * firmware version. So the workaround in software driver is needed. It needs
9208 * to modify the initial values of 3 internal only registers for both X710 and
9209 * XL710. Note that the values for X710 or XL710 could be different, and the
9210 * workaround can be removed when it is fixed in firmware in the future.
9213 /* For both X710 and XL710 */
9214 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9215 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9217 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9218 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9221 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9222 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9225 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9227 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9228 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9231 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9233 enum i40e_status_code status;
9234 struct i40e_aq_get_phy_abilities_resp phy_ab;
9237 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9241 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9250 i40e_configure_registers(struct i40e_hw *hw)
9256 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9257 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9258 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9264 for (i = 0; i < RTE_DIM(reg_table); i++) {
9265 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9266 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9268 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9269 else /* For X710/XL710/XXV710 */
9271 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9274 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9275 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9277 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9278 else /* For X710/XL710/XXV710 */
9280 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9283 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9284 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9285 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9287 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9290 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9293 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9296 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9300 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9301 reg_table[i].addr, reg);
9302 if (reg == reg_table[i].val)
9305 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9306 reg_table[i].val, NULL);
9309 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9310 reg_table[i].val, reg_table[i].addr);
9313 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9314 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9318 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9319 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9320 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9321 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9323 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9328 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9329 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9333 /* Configure for double VLAN RX stripping */
9334 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9335 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9336 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9337 ret = i40e_aq_debug_write_register(hw,
9338 I40E_VSI_TSR(vsi->vsi_id),
9341 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9343 return I40E_ERR_CONFIG;
9347 /* Configure for double VLAN TX insertion */
9348 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9349 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9350 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9351 ret = i40e_aq_debug_write_register(hw,
9352 I40E_VSI_L2TAGSTXVALID(
9353 vsi->vsi_id), reg, NULL);
9356 "Failed to update VSI_L2TAGSTXVALID[%d]",
9358 return I40E_ERR_CONFIG;
9366 * i40e_aq_add_mirror_rule
9367 * @hw: pointer to the hardware structure
9368 * @seid: VEB seid to add mirror rule to
9369 * @dst_id: destination vsi seid
9370 * @entries: Buffer which contains the entities to be mirrored
9371 * @count: number of entities contained in the buffer
9372 * @rule_id:the rule_id of the rule to be added
9374 * Add a mirror rule for a given veb.
9377 static enum i40e_status_code
9378 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9379 uint16_t seid, uint16_t dst_id,
9380 uint16_t rule_type, uint16_t *entries,
9381 uint16_t count, uint16_t *rule_id)
9383 struct i40e_aq_desc desc;
9384 struct i40e_aqc_add_delete_mirror_rule cmd;
9385 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9386 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9389 enum i40e_status_code status;
9391 i40e_fill_default_direct_cmd_desc(&desc,
9392 i40e_aqc_opc_add_mirror_rule);
9393 memset(&cmd, 0, sizeof(cmd));
9395 buff_len = sizeof(uint16_t) * count;
9396 desc.datalen = rte_cpu_to_le_16(buff_len);
9398 desc.flags |= rte_cpu_to_le_16(
9399 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9400 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9401 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9402 cmd.num_entries = rte_cpu_to_le_16(count);
9403 cmd.seid = rte_cpu_to_le_16(seid);
9404 cmd.destination = rte_cpu_to_le_16(dst_id);
9406 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9407 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9409 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9410 hw->aq.asq_last_status, resp->rule_id,
9411 resp->mirror_rules_used, resp->mirror_rules_free);
9412 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9418 * i40e_aq_del_mirror_rule
9419 * @hw: pointer to the hardware structure
9420 * @seid: VEB seid to add mirror rule to
9421 * @entries: Buffer which contains the entities to be mirrored
9422 * @count: number of entities contained in the buffer
9423 * @rule_id:the rule_id of the rule to be delete
9425 * Delete a mirror rule for a given veb.
9428 static enum i40e_status_code
9429 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9430 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9431 uint16_t count, uint16_t rule_id)
9433 struct i40e_aq_desc desc;
9434 struct i40e_aqc_add_delete_mirror_rule cmd;
9435 uint16_t buff_len = 0;
9436 enum i40e_status_code status;
9439 i40e_fill_default_direct_cmd_desc(&desc,
9440 i40e_aqc_opc_delete_mirror_rule);
9441 memset(&cmd, 0, sizeof(cmd));
9442 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9443 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9445 cmd.num_entries = count;
9446 buff_len = sizeof(uint16_t) * count;
9447 desc.datalen = rte_cpu_to_le_16(buff_len);
9448 buff = (void *)entries;
9450 /* rule id is filled in destination field for deleting mirror rule */
9451 cmd.destination = rte_cpu_to_le_16(rule_id);
9453 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9454 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9455 cmd.seid = rte_cpu_to_le_16(seid);
9457 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9458 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9464 * i40e_mirror_rule_set
9465 * @dev: pointer to the hardware structure
9466 * @mirror_conf: mirror rule info
9467 * @sw_id: mirror rule's sw_id
9468 * @on: enable/disable
9470 * set a mirror rule.
9474 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9475 struct rte_eth_mirror_conf *mirror_conf,
9476 uint8_t sw_id, uint8_t on)
9478 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9479 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9480 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9481 struct i40e_mirror_rule *parent = NULL;
9482 uint16_t seid, dst_seid, rule_id;
9486 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9488 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9490 "mirror rule can not be configured without veb or vfs.");
9493 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9494 PMD_DRV_LOG(ERR, "mirror table is full.");
9497 if (mirror_conf->dst_pool > pf->vf_num) {
9498 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9499 mirror_conf->dst_pool);
9503 seid = pf->main_vsi->veb->seid;
9505 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9506 if (sw_id <= it->index) {
9512 if (mirr_rule && sw_id == mirr_rule->index) {
9514 PMD_DRV_LOG(ERR, "mirror rule exists.");
9517 ret = i40e_aq_del_mirror_rule(hw, seid,
9518 mirr_rule->rule_type,
9520 mirr_rule->num_entries, mirr_rule->id);
9523 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9524 ret, hw->aq.asq_last_status);
9527 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9528 rte_free(mirr_rule);
9529 pf->nb_mirror_rule--;
9533 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9537 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9538 sizeof(struct i40e_mirror_rule) , 0);
9540 PMD_DRV_LOG(ERR, "failed to allocate memory");
9541 return I40E_ERR_NO_MEMORY;
9543 switch (mirror_conf->rule_type) {
9544 case ETH_MIRROR_VLAN:
9545 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9546 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9547 mirr_rule->entries[j] =
9548 mirror_conf->vlan.vlan_id[i];
9553 PMD_DRV_LOG(ERR, "vlan is not specified.");
9554 rte_free(mirr_rule);
9557 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9559 case ETH_MIRROR_VIRTUAL_POOL_UP:
9560 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9561 /* check if the specified pool bit is out of range */
9562 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9563 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9564 rte_free(mirr_rule);
9567 for (i = 0, j = 0; i < pf->vf_num; i++) {
9568 if (mirror_conf->pool_mask & (1ULL << i)) {
9569 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9573 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9574 /* add pf vsi to entries */
9575 mirr_rule->entries[j] = pf->main_vsi_seid;
9579 PMD_DRV_LOG(ERR, "pool is not specified.");
9580 rte_free(mirr_rule);
9583 /* egress and ingress in aq commands means from switch but not port */
9584 mirr_rule->rule_type =
9585 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9586 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9587 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9589 case ETH_MIRROR_UPLINK_PORT:
9590 /* egress and ingress in aq commands means from switch but not port*/
9591 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9593 case ETH_MIRROR_DOWNLINK_PORT:
9594 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9597 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9598 mirror_conf->rule_type);
9599 rte_free(mirr_rule);
9603 /* If the dst_pool is equal to vf_num, consider it as PF */
9604 if (mirror_conf->dst_pool == pf->vf_num)
9605 dst_seid = pf->main_vsi_seid;
9607 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9609 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9610 mirr_rule->rule_type, mirr_rule->entries,
9614 "failed to add mirror rule: ret = %d, aq_err = %d.",
9615 ret, hw->aq.asq_last_status);
9616 rte_free(mirr_rule);
9620 mirr_rule->index = sw_id;
9621 mirr_rule->num_entries = j;
9622 mirr_rule->id = rule_id;
9623 mirr_rule->dst_vsi_seid = dst_seid;
9626 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9628 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9630 pf->nb_mirror_rule++;
9635 * i40e_mirror_rule_reset
9636 * @dev: pointer to the device
9637 * @sw_id: mirror rule's sw_id
9639 * reset a mirror rule.
9643 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9645 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9646 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9647 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9651 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9653 seid = pf->main_vsi->veb->seid;
9655 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9656 if (sw_id == it->index) {
9662 ret = i40e_aq_del_mirror_rule(hw, seid,
9663 mirr_rule->rule_type,
9665 mirr_rule->num_entries, mirr_rule->id);
9668 "failed to remove mirror rule: status = %d, aq_err = %d.",
9669 ret, hw->aq.asq_last_status);
9672 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9673 rte_free(mirr_rule);
9674 pf->nb_mirror_rule--;
9676 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9683 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9685 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9686 uint64_t systim_cycles;
9688 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9689 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9692 return systim_cycles;
9696 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9698 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9701 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9702 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9709 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9711 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9714 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9715 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9722 i40e_start_timecounters(struct rte_eth_dev *dev)
9724 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9725 struct i40e_adapter *adapter =
9726 (struct i40e_adapter *)dev->data->dev_private;
9727 struct rte_eth_link link;
9728 uint32_t tsync_inc_l;
9729 uint32_t tsync_inc_h;
9731 /* Get current link speed. */
9732 memset(&link, 0, sizeof(link));
9733 i40e_dev_link_update(dev, 1);
9734 rte_i40e_dev_atomic_read_link_status(dev, &link);
9736 switch (link.link_speed) {
9737 case ETH_SPEED_NUM_40G:
9738 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9739 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9741 case ETH_SPEED_NUM_10G:
9742 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9743 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9745 case ETH_SPEED_NUM_1G:
9746 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9747 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9754 /* Set the timesync increment value. */
9755 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9756 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9758 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9759 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9760 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9762 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9763 adapter->systime_tc.cc_shift = 0;
9764 adapter->systime_tc.nsec_mask = 0;
9766 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9767 adapter->rx_tstamp_tc.cc_shift = 0;
9768 adapter->rx_tstamp_tc.nsec_mask = 0;
9770 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9771 adapter->tx_tstamp_tc.cc_shift = 0;
9772 adapter->tx_tstamp_tc.nsec_mask = 0;
9776 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9778 struct i40e_adapter *adapter =
9779 (struct i40e_adapter *)dev->data->dev_private;
9781 adapter->systime_tc.nsec += delta;
9782 adapter->rx_tstamp_tc.nsec += delta;
9783 adapter->tx_tstamp_tc.nsec += delta;
9789 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9792 struct i40e_adapter *adapter =
9793 (struct i40e_adapter *)dev->data->dev_private;
9795 ns = rte_timespec_to_ns(ts);
9797 /* Set the timecounters to a new value. */
9798 adapter->systime_tc.nsec = ns;
9799 adapter->rx_tstamp_tc.nsec = ns;
9800 adapter->tx_tstamp_tc.nsec = ns;
9806 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9808 uint64_t ns, systime_cycles;
9809 struct i40e_adapter *adapter =
9810 (struct i40e_adapter *)dev->data->dev_private;
9812 systime_cycles = i40e_read_systime_cyclecounter(dev);
9813 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9814 *ts = rte_ns_to_timespec(ns);
9820 i40e_timesync_enable(struct rte_eth_dev *dev)
9822 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9823 uint32_t tsync_ctl_l;
9824 uint32_t tsync_ctl_h;
9826 /* Stop the timesync system time. */
9827 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9828 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9829 /* Reset the timesync system time value. */
9830 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9831 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9833 i40e_start_timecounters(dev);
9835 /* Clear timesync registers. */
9836 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9837 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9838 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9839 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9840 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9841 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9843 /* Enable timestamping of PTP packets. */
9844 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9845 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9847 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9848 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9849 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9851 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9852 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9858 i40e_timesync_disable(struct rte_eth_dev *dev)
9860 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9861 uint32_t tsync_ctl_l;
9862 uint32_t tsync_ctl_h;
9864 /* Disable timestamping of transmitted PTP packets. */
9865 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9866 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9868 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9869 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9871 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9872 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9874 /* Reset the timesync increment value. */
9875 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9876 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9882 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9883 struct timespec *timestamp, uint32_t flags)
9885 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9886 struct i40e_adapter *adapter =
9887 (struct i40e_adapter *)dev->data->dev_private;
9889 uint32_t sync_status;
9890 uint32_t index = flags & 0x03;
9891 uint64_t rx_tstamp_cycles;
9894 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9895 if ((sync_status & (1 << index)) == 0)
9898 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9899 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9900 *timestamp = rte_ns_to_timespec(ns);
9906 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9907 struct timespec *timestamp)
9909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9910 struct i40e_adapter *adapter =
9911 (struct i40e_adapter *)dev->data->dev_private;
9913 uint32_t sync_status;
9914 uint64_t tx_tstamp_cycles;
9917 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9918 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9921 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9922 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9923 *timestamp = rte_ns_to_timespec(ns);
9929 * i40e_parse_dcb_configure - parse dcb configure from user
9930 * @dev: the device being configured
9931 * @dcb_cfg: pointer of the result of parse
9932 * @*tc_map: bit map of enabled traffic classes
9934 * Returns 0 on success, negative value on failure
9937 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9938 struct i40e_dcbx_config *dcb_cfg,
9941 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9942 uint8_t i, tc_bw, bw_lf;
9944 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9946 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9947 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9948 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9952 /* assume each tc has the same bw */
9953 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9954 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9955 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9956 /* to ensure the sum of tcbw is equal to 100 */
9957 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9958 for (i = 0; i < bw_lf; i++)
9959 dcb_cfg->etscfg.tcbwtable[i]++;
9961 /* assume each tc has the same Transmission Selection Algorithm */
9962 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9963 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9965 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9966 dcb_cfg->etscfg.prioritytable[i] =
9967 dcb_rx_conf->dcb_tc[i];
9969 /* FW needs one App to configure HW */
9970 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9971 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9972 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9973 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9975 if (dcb_rx_conf->nb_tcs == 0)
9976 *tc_map = 1; /* tc0 only */
9978 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9980 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9981 dcb_cfg->pfc.willing = 0;
9982 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9983 dcb_cfg->pfc.pfcenable = *tc_map;
9989 static enum i40e_status_code
9990 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9991 struct i40e_aqc_vsi_properties_data *info,
9992 uint8_t enabled_tcmap)
9994 enum i40e_status_code ret;
9995 int i, total_tc = 0;
9996 uint16_t qpnum_per_tc, bsf, qp_idx;
9997 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9998 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9999 uint16_t used_queues;
10001 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10002 if (ret != I40E_SUCCESS)
10005 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10006 if (enabled_tcmap & (1 << i))
10011 vsi->enabled_tc = enabled_tcmap;
10013 /* different VSI has different queues assigned */
10014 if (vsi->type == I40E_VSI_MAIN)
10015 used_queues = dev_data->nb_rx_queues -
10016 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10017 else if (vsi->type == I40E_VSI_VMDQ2)
10018 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10020 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10021 return I40E_ERR_NO_AVAILABLE_VSI;
10024 qpnum_per_tc = used_queues / total_tc;
10025 /* Number of queues per enabled TC */
10026 if (qpnum_per_tc == 0) {
10027 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10028 return I40E_ERR_INVALID_QP_ID;
10030 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10031 I40E_MAX_Q_PER_TC);
10032 bsf = rte_bsf32(qpnum_per_tc);
10035 * Configure TC and queue mapping parameters, for enabled TC,
10036 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10037 * default queue will serve it.
10040 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10041 if (vsi->enabled_tc & (1 << i)) {
10042 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10043 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10044 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10045 qp_idx += qpnum_per_tc;
10047 info->tc_mapping[i] = 0;
10050 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10051 if (vsi->type == I40E_VSI_SRIOV) {
10052 info->mapping_flags |=
10053 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10054 for (i = 0; i < vsi->nb_qps; i++)
10055 info->queue_mapping[i] =
10056 rte_cpu_to_le_16(vsi->base_queue + i);
10058 info->mapping_flags |=
10059 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10060 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10062 info->valid_sections |=
10063 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10065 return I40E_SUCCESS;
10069 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10070 * @veb: VEB to be configured
10071 * @tc_map: enabled TC bitmap
10073 * Returns 0 on success, negative value on failure
10075 static enum i40e_status_code
10076 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10078 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10079 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10080 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10081 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10082 enum i40e_status_code ret = I40E_SUCCESS;
10086 /* Check if enabled_tc is same as existing or new TCs */
10087 if (veb->enabled_tc == tc_map)
10090 /* configure tc bandwidth */
10091 memset(&veb_bw, 0, sizeof(veb_bw));
10092 veb_bw.tc_valid_bits = tc_map;
10093 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10094 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10095 if (tc_map & BIT_ULL(i))
10096 veb_bw.tc_bw_share_credits[i] = 1;
10098 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10102 "AQ command Config switch_comp BW allocation per TC failed = %d",
10103 hw->aq.asq_last_status);
10107 memset(&ets_query, 0, sizeof(ets_query));
10108 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10110 if (ret != I40E_SUCCESS) {
10112 "Failed to get switch_comp ETS configuration %u",
10113 hw->aq.asq_last_status);
10116 memset(&bw_query, 0, sizeof(bw_query));
10117 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10119 if (ret != I40E_SUCCESS) {
10121 "Failed to get switch_comp bandwidth configuration %u",
10122 hw->aq.asq_last_status);
10126 /* store and print out BW info */
10127 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10128 veb->bw_info.bw_max = ets_query.tc_bw_max;
10129 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10130 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10131 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10132 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10133 I40E_16_BIT_WIDTH);
10134 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10135 veb->bw_info.bw_ets_share_credits[i] =
10136 bw_query.tc_bw_share_credits[i];
10137 veb->bw_info.bw_ets_credits[i] =
10138 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10139 /* 4 bits per TC, 4th bit is reserved */
10140 veb->bw_info.bw_ets_max[i] =
10141 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10142 RTE_LEN2MASK(3, uint8_t));
10143 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10144 veb->bw_info.bw_ets_share_credits[i]);
10145 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10146 veb->bw_info.bw_ets_credits[i]);
10147 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10148 veb->bw_info.bw_ets_max[i]);
10151 veb->enabled_tc = tc_map;
10158 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10159 * @vsi: VSI to be configured
10160 * @tc_map: enabled TC bitmap
10162 * Returns 0 on success, negative value on failure
10164 static enum i40e_status_code
10165 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10167 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10168 struct i40e_vsi_context ctxt;
10169 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10170 enum i40e_status_code ret = I40E_SUCCESS;
10173 /* Check if enabled_tc is same as existing or new TCs */
10174 if (vsi->enabled_tc == tc_map)
10177 /* configure tc bandwidth */
10178 memset(&bw_data, 0, sizeof(bw_data));
10179 bw_data.tc_valid_bits = tc_map;
10180 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10181 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10182 if (tc_map & BIT_ULL(i))
10183 bw_data.tc_bw_credits[i] = 1;
10185 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10188 "AQ command Config VSI BW allocation per TC failed = %d",
10189 hw->aq.asq_last_status);
10192 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10193 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10195 /* Update Queue Pairs Mapping for currently enabled UPs */
10196 ctxt.seid = vsi->seid;
10197 ctxt.pf_num = hw->pf_id;
10199 ctxt.uplink_seid = vsi->uplink_seid;
10200 ctxt.info = vsi->info;
10202 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10206 /* Update the VSI after updating the VSI queue-mapping information */
10207 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10209 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10210 hw->aq.asq_last_status);
10213 /* update the local VSI info with updated queue map */
10214 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10215 sizeof(vsi->info.tc_mapping));
10216 (void)rte_memcpy(&vsi->info.queue_mapping,
10217 &ctxt.info.queue_mapping,
10218 sizeof(vsi->info.queue_mapping));
10219 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10220 vsi->info.valid_sections = 0;
10222 /* query and update current VSI BW information */
10223 ret = i40e_vsi_get_bw_config(vsi);
10226 "Failed updating vsi bw info, err %s aq_err %s",
10227 i40e_stat_str(hw, ret),
10228 i40e_aq_str(hw, hw->aq.asq_last_status));
10232 vsi->enabled_tc = tc_map;
10239 * i40e_dcb_hw_configure - program the dcb setting to hw
10240 * @pf: pf the configuration is taken on
10241 * @new_cfg: new configuration
10242 * @tc_map: enabled TC bitmap
10244 * Returns 0 on success, negative value on failure
10246 static enum i40e_status_code
10247 i40e_dcb_hw_configure(struct i40e_pf *pf,
10248 struct i40e_dcbx_config *new_cfg,
10251 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10252 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10253 struct i40e_vsi *main_vsi = pf->main_vsi;
10254 struct i40e_vsi_list *vsi_list;
10255 enum i40e_status_code ret;
10259 /* Use the FW API if FW > v4.4*/
10260 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10261 (hw->aq.fw_maj_ver >= 5))) {
10263 "FW < v4.4, can not use FW LLDP API to configure DCB");
10264 return I40E_ERR_FIRMWARE_API_VERSION;
10267 /* Check if need reconfiguration */
10268 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10269 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10270 return I40E_SUCCESS;
10273 /* Copy the new config to the current config */
10274 *old_cfg = *new_cfg;
10275 old_cfg->etsrec = old_cfg->etscfg;
10276 ret = i40e_set_dcb_config(hw);
10278 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10279 i40e_stat_str(hw, ret),
10280 i40e_aq_str(hw, hw->aq.asq_last_status));
10283 /* set receive Arbiter to RR mode and ETS scheme by default */
10284 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10285 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10286 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10287 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10288 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10289 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10290 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10291 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10292 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10293 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10294 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10295 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10296 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10298 /* get local mib to check whether it is configured correctly */
10300 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10301 /* Get Local DCB Config */
10302 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10303 &hw->local_dcbx_config);
10305 /* if Veb is created, need to update TC of it at first */
10306 if (main_vsi->veb) {
10307 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10309 PMD_INIT_LOG(WARNING,
10310 "Failed configuring TC for VEB seid=%d",
10311 main_vsi->veb->seid);
10313 /* Update each VSI */
10314 i40e_vsi_config_tc(main_vsi, tc_map);
10315 if (main_vsi->veb) {
10316 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10317 /* Beside main VSI and VMDQ VSIs, only enable default
10318 * TC for other VSIs
10320 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10321 ret = i40e_vsi_config_tc(vsi_list->vsi,
10324 ret = i40e_vsi_config_tc(vsi_list->vsi,
10325 I40E_DEFAULT_TCMAP);
10327 PMD_INIT_LOG(WARNING,
10328 "Failed configuring TC for VSI seid=%d",
10329 vsi_list->vsi->seid);
10333 return I40E_SUCCESS;
10337 * i40e_dcb_init_configure - initial dcb config
10338 * @dev: device being configured
10339 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10341 * Returns 0 on success, negative value on failure
10344 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10346 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10347 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10350 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10351 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10355 /* DCB initialization:
10356 * Update DCB configuration from the Firmware and configure
10357 * LLDP MIB change event.
10359 if (sw_dcb == TRUE) {
10360 ret = i40e_init_dcb(hw);
10361 /* If lldp agent is stopped, the return value from
10362 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10363 * adminq status. Otherwise, it should return success.
10365 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10366 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10367 memset(&hw->local_dcbx_config, 0,
10368 sizeof(struct i40e_dcbx_config));
10369 /* set dcb default configuration */
10370 hw->local_dcbx_config.etscfg.willing = 0;
10371 hw->local_dcbx_config.etscfg.maxtcs = 0;
10372 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10373 hw->local_dcbx_config.etscfg.tsatable[0] =
10375 /* all UPs mapping to TC0 */
10376 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10377 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10378 hw->local_dcbx_config.etsrec =
10379 hw->local_dcbx_config.etscfg;
10380 hw->local_dcbx_config.pfc.willing = 0;
10381 hw->local_dcbx_config.pfc.pfccap =
10382 I40E_MAX_TRAFFIC_CLASS;
10383 /* FW needs one App to configure HW */
10384 hw->local_dcbx_config.numapps = 1;
10385 hw->local_dcbx_config.app[0].selector =
10386 I40E_APP_SEL_ETHTYPE;
10387 hw->local_dcbx_config.app[0].priority = 3;
10388 hw->local_dcbx_config.app[0].protocolid =
10389 I40E_APP_PROTOID_FCOE;
10390 ret = i40e_set_dcb_config(hw);
10393 "default dcb config fails. err = %d, aq_err = %d.",
10394 ret, hw->aq.asq_last_status);
10399 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10400 ret, hw->aq.asq_last_status);
10404 ret = i40e_aq_start_lldp(hw, NULL);
10405 if (ret != I40E_SUCCESS)
10406 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10408 ret = i40e_init_dcb(hw);
10410 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10412 "HW doesn't support DCBX offload.");
10417 "DCBX configuration failed, err = %d, aq_err = %d.",
10418 ret, hw->aq.asq_last_status);
10426 * i40e_dcb_setup - setup dcb related config
10427 * @dev: device being configured
10429 * Returns 0 on success, negative value on failure
10432 i40e_dcb_setup(struct rte_eth_dev *dev)
10434 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10435 struct i40e_dcbx_config dcb_cfg;
10436 uint8_t tc_map = 0;
10439 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10440 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10444 if (pf->vf_num != 0)
10445 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10447 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10449 PMD_INIT_LOG(ERR, "invalid dcb config");
10452 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10454 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10462 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10463 struct rte_eth_dcb_info *dcb_info)
10465 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10466 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10467 struct i40e_vsi *vsi = pf->main_vsi;
10468 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10469 uint16_t bsf, tc_mapping;
10472 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10473 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10475 dcb_info->nb_tcs = 1;
10476 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10477 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10478 for (i = 0; i < dcb_info->nb_tcs; i++)
10479 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10481 /* get queue mapping if vmdq is disabled */
10482 if (!pf->nb_cfg_vmdq_vsi) {
10483 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10484 if (!(vsi->enabled_tc & (1 << i)))
10486 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10487 dcb_info->tc_queue.tc_rxq[j][i].base =
10488 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10489 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10490 dcb_info->tc_queue.tc_txq[j][i].base =
10491 dcb_info->tc_queue.tc_rxq[j][i].base;
10492 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10493 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10494 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10495 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10496 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10501 /* get queue mapping if vmdq is enabled */
10503 vsi = pf->vmdq[j].vsi;
10504 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10505 if (!(vsi->enabled_tc & (1 << i)))
10507 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10508 dcb_info->tc_queue.tc_rxq[j][i].base =
10509 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10510 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10511 dcb_info->tc_queue.tc_txq[j][i].base =
10512 dcb_info->tc_queue.tc_rxq[j][i].base;
10513 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10514 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10515 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10516 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10517 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10520 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10525 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10527 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10528 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10529 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10530 uint16_t interval =
10531 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10532 uint16_t msix_intr;
10534 msix_intr = intr_handle->intr_vec[queue_id];
10535 if (msix_intr == I40E_MISC_VEC_ID)
10536 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10537 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10538 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10539 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10541 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10544 I40E_PFINT_DYN_CTLN(msix_intr -
10545 I40E_RX_VEC_START),
10546 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10547 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10548 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10550 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10552 I40E_WRITE_FLUSH(hw);
10553 rte_intr_enable(&pci_dev->intr_handle);
10559 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10561 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10562 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10563 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10564 uint16_t msix_intr;
10566 msix_intr = intr_handle->intr_vec[queue_id];
10567 if (msix_intr == I40E_MISC_VEC_ID)
10568 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10571 I40E_PFINT_DYN_CTLN(msix_intr -
10572 I40E_RX_VEC_START),
10574 I40E_WRITE_FLUSH(hw);
10579 static int i40e_get_regs(struct rte_eth_dev *dev,
10580 struct rte_dev_reg_info *regs)
10582 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10583 uint32_t *ptr_data = regs->data;
10584 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10585 const struct i40e_reg_info *reg_info;
10587 if (ptr_data == NULL) {
10588 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10589 regs->width = sizeof(uint32_t);
10593 /* The first few registers have to be read using AQ operations */
10595 while (i40e_regs_adminq[reg_idx].name) {
10596 reg_info = &i40e_regs_adminq[reg_idx++];
10597 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10599 arr_idx2 <= reg_info->count2;
10601 reg_offset = arr_idx * reg_info->stride1 +
10602 arr_idx2 * reg_info->stride2;
10603 reg_offset += reg_info->base_addr;
10604 ptr_data[reg_offset >> 2] =
10605 i40e_read_rx_ctl(hw, reg_offset);
10609 /* The remaining registers can be read using primitives */
10611 while (i40e_regs_others[reg_idx].name) {
10612 reg_info = &i40e_regs_others[reg_idx++];
10613 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10615 arr_idx2 <= reg_info->count2;
10617 reg_offset = arr_idx * reg_info->stride1 +
10618 arr_idx2 * reg_info->stride2;
10619 reg_offset += reg_info->base_addr;
10620 ptr_data[reg_offset >> 2] =
10621 I40E_READ_REG(hw, reg_offset);
10628 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10630 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10632 /* Convert word count to byte count */
10633 return hw->nvm.sr_size << 1;
10636 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10637 struct rte_dev_eeprom_info *eeprom)
10639 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10640 uint16_t *data = eeprom->data;
10641 uint16_t offset, length, cnt_words;
10644 offset = eeprom->offset >> 1;
10645 length = eeprom->length >> 1;
10646 cnt_words = length;
10648 if (offset > hw->nvm.sr_size ||
10649 offset + length > hw->nvm.sr_size) {
10650 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10654 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10656 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10657 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10658 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10665 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10666 struct ether_addr *mac_addr)
10668 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10670 if (!is_valid_assigned_ether_addr(mac_addr)) {
10671 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10675 /* Flags: 0x3 updates port address */
10676 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10680 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10682 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10683 struct rte_eth_dev_data *dev_data = pf->dev_data;
10684 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10687 /* check if mtu is within the allowed range */
10688 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10691 /* mtu setting is forbidden if port is start */
10692 if (dev_data->dev_started) {
10693 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10694 dev_data->port_id);
10698 if (frame_size > ETHER_MAX_LEN)
10699 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10701 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10703 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10708 /* Restore ethertype filter */
10710 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10712 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10713 struct i40e_ethertype_filter_list
10714 *ethertype_list = &pf->ethertype.ethertype_list;
10715 struct i40e_ethertype_filter *f;
10716 struct i40e_control_filter_stats stats;
10719 TAILQ_FOREACH(f, ethertype_list, rules) {
10721 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10722 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10723 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10724 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10725 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10727 memset(&stats, 0, sizeof(stats));
10728 i40e_aq_add_rem_control_packet_filter(hw,
10729 f->input.mac_addr.addr_bytes,
10730 f->input.ether_type,
10731 flags, pf->main_vsi->seid,
10732 f->queue, 1, &stats, NULL);
10734 PMD_DRV_LOG(INFO, "Ethertype filter:"
10735 " mac_etype_used = %u, etype_used = %u,"
10736 " mac_etype_free = %u, etype_free = %u",
10737 stats.mac_etype_used, stats.etype_used,
10738 stats.mac_etype_free, stats.etype_free);
10741 /* Restore tunnel filter */
10743 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10745 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10746 struct i40e_vsi *vsi;
10747 struct i40e_pf_vf *vf;
10748 struct i40e_tunnel_filter_list
10749 *tunnel_list = &pf->tunnel.tunnel_list;
10750 struct i40e_tunnel_filter *f;
10751 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10752 bool big_buffer = 0;
10754 TAILQ_FOREACH(f, tunnel_list, rules) {
10756 vsi = pf->main_vsi;
10758 vf = &pf->vfs[f->vf_id];
10761 memset(&cld_filter, 0, sizeof(cld_filter));
10762 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10763 (struct ether_addr *)&cld_filter.element.outer_mac);
10764 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10765 (struct ether_addr *)&cld_filter.element.inner_mac);
10766 cld_filter.element.inner_vlan = f->input.inner_vlan;
10767 cld_filter.element.flags = f->input.flags;
10768 cld_filter.element.tenant_id = f->input.tenant_id;
10769 cld_filter.element.queue_number = f->queue;
10770 rte_memcpy(cld_filter.general_fields,
10771 f->input.general_fields,
10772 sizeof(f->input.general_fields));
10774 if (((f->input.flags &
10775 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10776 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10778 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10779 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10781 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10782 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10786 i40e_aq_add_cloud_filters_big_buffer(hw,
10787 vsi->seid, &cld_filter, 1);
10789 i40e_aq_add_cloud_filters(hw, vsi->seid,
10790 &cld_filter.element, 1);
10795 i40e_filter_restore(struct i40e_pf *pf)
10797 i40e_ethertype_filter_restore(pf);
10798 i40e_tunnel_filter_restore(pf);
10799 i40e_fdir_filter_restore(pf);
10803 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10805 if (strcmp(dev->device->driver->name, drv->driver.name))
10812 is_i40e_supported(struct rte_eth_dev *dev)
10814 return is_device_supported(dev, &rte_i40e_pmd);
10817 /* Create a QinQ cloud filter
10819 * The Fortville NIC has limited resources for tunnel filters,
10820 * so we can only reuse existing filters.
10822 * In step 1 we define which Field Vector fields can be used for
10824 * As we do not have the inner tag defined as a field,
10825 * we have to define it first, by reusing one of L1 entries.
10827 * In step 2 we are replacing one of existing filter types with
10828 * a new one for QinQ.
10829 * As we reusing L1 and replacing L2, some of the default filter
10830 * types will disappear,which depends on L1 and L2 entries we reuse.
10832 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10834 * 1. Create L1 filter of outer vlan (12b) which will be in use
10835 * later when we define the cloud filter.
10836 * a. Valid_flags.replace_cloud = 0
10837 * b. Old_filter = 10 (Stag_Inner_Vlan)
10838 * c. New_filter = 0x10
10839 * d. TR bit = 0xff (optional, not used here)
10840 * e. Buffer – 2 entries:
10841 * i. Byte 0 = 8 (outer vlan FV index).
10843 * Byte 2-3 = 0x0fff
10844 * ii. Byte 0 = 37 (inner vlan FV index).
10846 * Byte 2-3 = 0x0fff
10849 * 2. Create cloud filter using two L1 filters entries: stag and
10850 * new filter(outer vlan+ inner vlan)
10851 * a. Valid_flags.replace_cloud = 1
10852 * b. Old_filter = 1 (instead of outer IP)
10853 * c. New_filter = 0x10
10854 * d. Buffer – 2 entries:
10855 * i. Byte 0 = 0x80 | 7 (valid | Stag).
10856 * Byte 1-3 = 0 (rsv)
10857 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10858 * Byte 9-11 = 0 (rsv)
10861 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10863 int ret = -ENOTSUP;
10864 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
10865 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
10866 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10869 memset(&filter_replace, 0,
10870 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10871 memset(&filter_replace_buf, 0,
10872 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10874 /* create L1 filter */
10875 filter_replace.old_filter_type =
10876 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10877 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10878 filter_replace.tr_bit = 0;
10880 /* Prepare the buffer, 2 entries */
10881 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10882 filter_replace_buf.data[0] |=
10883 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10884 /* Field Vector 12b mask */
10885 filter_replace_buf.data[2] = 0xff;
10886 filter_replace_buf.data[3] = 0x0f;
10887 filter_replace_buf.data[4] =
10888 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10889 filter_replace_buf.data[4] |=
10890 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10891 /* Field Vector 12b mask */
10892 filter_replace_buf.data[6] = 0xff;
10893 filter_replace_buf.data[7] = 0x0f;
10894 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10895 &filter_replace_buf);
10896 if (ret != I40E_SUCCESS)
10899 /* Apply the second L2 cloud filter */
10900 memset(&filter_replace, 0,
10901 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10902 memset(&filter_replace_buf, 0,
10903 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10905 /* create L2 filter, input for L2 filter will be L1 filter */
10906 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10907 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10908 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10910 /* Prepare the buffer, 2 entries */
10911 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10912 filter_replace_buf.data[0] |=
10913 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10914 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10915 filter_replace_buf.data[4] |=
10916 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10917 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10918 &filter_replace_buf);
10922 RTE_INIT(i40e_init_log);
10924 i40e_init_log(void)
10926 i40e_logtype_init = rte_log_register("pmd.i40e.init");
10927 if (i40e_logtype_init >= 0)
10928 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10929 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10930 if (i40e_logtype_driver >= 0)
10931 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);