4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and interval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Flow control default high water */
99 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
101 /* Flow control default low water */
102 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int i40e_dev_configure(struct rte_eth_dev *dev);
250 static int i40e_dev_start(struct rte_eth_dev *dev);
251 static void i40e_dev_stop(struct rte_eth_dev *dev);
252 static void i40e_dev_close(struct rte_eth_dev *dev);
253 static int i40e_dev_reset(struct rte_eth_dev *dev);
254 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
256 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
257 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
258 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
259 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
260 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
261 struct rte_eth_stats *stats);
262 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
263 struct rte_eth_xstat *xstats, unsigned n);
264 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
265 struct rte_eth_xstat_name *xstats_names,
267 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
268 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
272 static int i40e_fw_version_get(struct rte_eth_dev *dev,
273 char *fw_version, size_t fw_size);
274 static void i40e_dev_info_get(struct rte_eth_dev *dev,
275 struct rte_eth_dev_info *dev_info);
276 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
279 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
280 enum rte_vlan_type vlan_type,
282 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
283 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
286 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
287 static int i40e_dev_led_on(struct rte_eth_dev *dev);
288 static int i40e_dev_led_off(struct rte_eth_dev *dev);
289 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_fc_conf *fc_conf);
293 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
294 struct rte_eth_pfc_conf *pfc_conf);
295 static int i40e_macaddr_add(struct rte_eth_dev *dev,
296 struct ether_addr *mac_addr,
299 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
300 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
301 struct rte_eth_rss_reta_entry64 *reta_conf,
303 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
304 struct rte_eth_rss_reta_entry64 *reta_conf,
307 static int i40e_get_cap(struct i40e_hw *hw);
308 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
309 static int i40e_pf_setup(struct i40e_pf *pf);
310 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
311 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
312 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
313 static int i40e_dcb_setup(struct rte_eth_dev *dev);
314 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
315 bool offset_loaded, uint64_t *offset, uint64_t *stat);
316 static void i40e_stat_update_48(struct i40e_hw *hw,
322 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
323 static void i40e_dev_interrupt_handler(void *param);
324 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
325 uint32_t base, uint32_t num);
326 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
327 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
329 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
331 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
332 static int i40e_veb_release(struct i40e_veb *veb);
333 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
334 struct i40e_vsi *vsi);
335 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
336 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
337 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
338 struct i40e_macvlan_filter *mv_f,
341 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
342 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
343 struct rte_eth_rss_conf *rss_conf);
344 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
345 struct rte_eth_rss_conf *rss_conf);
346 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
347 struct rte_eth_udp_tunnel *udp_tunnel);
348 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
349 struct rte_eth_udp_tunnel *udp_tunnel);
350 static void i40e_filter_input_set_init(struct i40e_pf *pf);
351 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
352 enum rte_filter_op filter_op,
354 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
355 enum rte_filter_type filter_type,
356 enum rte_filter_op filter_op,
358 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
359 struct rte_eth_dcb_info *dcb_info);
360 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
361 static void i40e_configure_registers(struct i40e_hw *hw);
362 static void i40e_hw_init(struct rte_eth_dev *dev);
363 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
364 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
365 struct rte_eth_mirror_conf *mirror_conf,
366 uint8_t sw_id, uint8_t on);
367 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
369 static int i40e_timesync_enable(struct rte_eth_dev *dev);
370 static int i40e_timesync_disable(struct rte_eth_dev *dev);
371 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
372 struct timespec *timestamp,
374 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
375 struct timespec *timestamp);
376 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
378 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
380 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
381 struct timespec *timestamp);
382 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
383 const struct timespec *timestamp);
385 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
387 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
390 static int i40e_get_regs(struct rte_eth_dev *dev,
391 struct rte_dev_reg_info *regs);
393 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
395 static int i40e_get_eeprom(struct rte_eth_dev *dev,
396 struct rte_dev_eeprom_info *eeprom);
398 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
399 struct ether_addr *mac_addr);
401 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
403 static int i40e_ethertype_filter_convert(
404 const struct rte_eth_ethertype_filter *input,
405 struct i40e_ethertype_filter *filter);
406 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
407 struct i40e_ethertype_filter *filter);
409 static int i40e_tunnel_filter_convert(
410 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
411 struct i40e_tunnel_filter *tunnel_filter);
412 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
413 struct i40e_tunnel_filter *tunnel_filter);
414 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
416 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
417 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
418 static void i40e_filter_restore(struct i40e_pf *pf);
419 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
421 int i40e_logtype_init;
422 int i40e_logtype_driver;
424 static const struct rte_pci_id pci_id_i40e_map[] = {
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
445 { .vendor_id = 0, /* sentinel */ },
448 static const struct eth_dev_ops i40e_eth_dev_ops = {
449 .dev_configure = i40e_dev_configure,
450 .dev_start = i40e_dev_start,
451 .dev_stop = i40e_dev_stop,
452 .dev_close = i40e_dev_close,
453 .dev_reset = i40e_dev_reset,
454 .promiscuous_enable = i40e_dev_promiscuous_enable,
455 .promiscuous_disable = i40e_dev_promiscuous_disable,
456 .allmulticast_enable = i40e_dev_allmulticast_enable,
457 .allmulticast_disable = i40e_dev_allmulticast_disable,
458 .dev_set_link_up = i40e_dev_set_link_up,
459 .dev_set_link_down = i40e_dev_set_link_down,
460 .link_update = i40e_dev_link_update,
461 .stats_get = i40e_dev_stats_get,
462 .xstats_get = i40e_dev_xstats_get,
463 .xstats_get_names = i40e_dev_xstats_get_names,
464 .stats_reset = i40e_dev_stats_reset,
465 .xstats_reset = i40e_dev_stats_reset,
466 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
467 .fw_version_get = i40e_fw_version_get,
468 .dev_infos_get = i40e_dev_info_get,
469 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
470 .vlan_filter_set = i40e_vlan_filter_set,
471 .vlan_tpid_set = i40e_vlan_tpid_set,
472 .vlan_offload_set = i40e_vlan_offload_set,
473 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
474 .vlan_pvid_set = i40e_vlan_pvid_set,
475 .rx_queue_start = i40e_dev_rx_queue_start,
476 .rx_queue_stop = i40e_dev_rx_queue_stop,
477 .tx_queue_start = i40e_dev_tx_queue_start,
478 .tx_queue_stop = i40e_dev_tx_queue_stop,
479 .rx_queue_setup = i40e_dev_rx_queue_setup,
480 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
481 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
482 .rx_queue_release = i40e_dev_rx_queue_release,
483 .rx_queue_count = i40e_dev_rx_queue_count,
484 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
485 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
486 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
487 .tx_queue_setup = i40e_dev_tx_queue_setup,
488 .tx_queue_release = i40e_dev_tx_queue_release,
489 .dev_led_on = i40e_dev_led_on,
490 .dev_led_off = i40e_dev_led_off,
491 .flow_ctrl_get = i40e_flow_ctrl_get,
492 .flow_ctrl_set = i40e_flow_ctrl_set,
493 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
494 .mac_addr_add = i40e_macaddr_add,
495 .mac_addr_remove = i40e_macaddr_remove,
496 .reta_update = i40e_dev_rss_reta_update,
497 .reta_query = i40e_dev_rss_reta_query,
498 .rss_hash_update = i40e_dev_rss_hash_update,
499 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
500 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
501 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
502 .filter_ctrl = i40e_dev_filter_ctrl,
503 .rxq_info_get = i40e_rxq_info_get,
504 .txq_info_get = i40e_txq_info_get,
505 .mirror_rule_set = i40e_mirror_rule_set,
506 .mirror_rule_reset = i40e_mirror_rule_reset,
507 .timesync_enable = i40e_timesync_enable,
508 .timesync_disable = i40e_timesync_disable,
509 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
510 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
511 .get_dcb_info = i40e_dev_get_dcb_info,
512 .timesync_adjust_time = i40e_timesync_adjust_time,
513 .timesync_read_time = i40e_timesync_read_time,
514 .timesync_write_time = i40e_timesync_write_time,
515 .get_reg = i40e_get_regs,
516 .get_eeprom_length = i40e_get_eeprom_length,
517 .get_eeprom = i40e_get_eeprom,
518 .mac_addr_set = i40e_set_default_mac_addr,
519 .mtu_set = i40e_dev_mtu_set,
520 .tm_ops_get = i40e_tm_ops_get,
523 /* store statistics names and its offset in stats structure */
524 struct rte_i40e_xstats_name_off {
525 char name[RTE_ETH_XSTATS_NAME_SIZE];
529 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
530 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
531 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
532 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
533 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
534 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
535 rx_unknown_protocol)},
536 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
537 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
538 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
539 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
542 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
543 sizeof(rte_i40e_stats_strings[0]))
545 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
546 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
547 tx_dropped_link_down)},
548 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
549 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
551 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
552 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
554 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
556 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
558 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
559 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
560 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
561 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
562 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
563 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
580 mac_short_packet_dropped)},
581 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
583 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
584 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
585 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
597 {"rx_flow_director_atr_match_packets",
598 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
599 {"rx_flow_director_sb_match_packets",
600 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
601 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
603 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
605 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
607 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
611 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
612 sizeof(rte_i40e_hw_port_strings[0]))
614 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
615 {"xon_packets", offsetof(struct i40e_hw_port_stats,
617 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
621 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
622 sizeof(rte_i40e_rxq_prio_strings[0]))
624 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
625 {"xon_packets", offsetof(struct i40e_hw_port_stats,
627 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
629 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
630 priority_xon_2_xoff)},
633 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
634 sizeof(rte_i40e_txq_prio_strings[0]))
636 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
637 struct rte_pci_device *pci_dev)
639 return rte_eth_dev_pci_generic_probe(pci_dev,
640 sizeof(struct i40e_adapter), eth_i40e_dev_init);
643 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
645 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
648 static struct rte_pci_driver rte_i40e_pmd = {
649 .id_table = pci_id_i40e_map,
650 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
651 .probe = eth_i40e_pci_probe,
652 .remove = eth_i40e_pci_remove,
656 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
657 struct rte_eth_link *link)
659 struct rte_eth_link *dst = link;
660 struct rte_eth_link *src = &(dev->data->dev_link);
662 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
663 *(uint64_t *)src) == 0)
670 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
671 struct rte_eth_link *link)
673 struct rte_eth_link *dst = &(dev->data->dev_link);
674 struct rte_eth_link *src = link;
676 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
677 *(uint64_t *)src) == 0)
683 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
684 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
685 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
687 #ifndef I40E_GLQF_ORT
688 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
690 #ifndef I40E_GLQF_PIT
691 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
693 #ifndef I40E_GLQF_L3_MAP
694 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
697 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
700 * Initialize registers for flexible payload, which should be set by NVM.
701 * This should be removed from code once it is fixed in NVM.
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
712 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
713 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
714 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
716 /* Initialize registers for parsing packet type of QinQ */
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
718 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
721 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
724 * Add a ethertype filter to drop all flow control frames transmitted
728 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
730 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
731 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
732 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
733 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
736 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
737 I40E_FLOW_CONTROL_ETHERTYPE, flags,
738 pf->main_vsi_seid, 0,
742 "Failed to add filter to drop flow control frames from VSIs.");
746 floating_veb_list_handler(__rte_unused const char *key,
747 const char *floating_veb_value,
751 unsigned int count = 0;
754 bool *vf_floating_veb = opaque;
756 while (isblank(*floating_veb_value))
757 floating_veb_value++;
759 /* Reset floating VEB configuration for VFs */
760 for (idx = 0; idx < I40E_MAX_VF; idx++)
761 vf_floating_veb[idx] = false;
765 while (isblank(*floating_veb_value))
766 floating_veb_value++;
767 if (*floating_veb_value == '\0')
770 idx = strtoul(floating_veb_value, &end, 10);
771 if (errno || end == NULL)
773 while (isblank(*end))
777 } else if ((*end == ';') || (*end == '\0')) {
779 if (min == I40E_MAX_VF)
781 if (max >= I40E_MAX_VF)
782 max = I40E_MAX_VF - 1;
783 for (idx = min; idx <= max; idx++) {
784 vf_floating_veb[idx] = true;
791 floating_veb_value = end + 1;
792 } while (*end != '\0');
801 config_vf_floating_veb(struct rte_devargs *devargs,
802 uint16_t floating_veb,
803 bool *vf_floating_veb)
805 struct rte_kvargs *kvlist;
807 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
811 /* All the VFs attach to the floating VEB by default
812 * when the floating VEB is enabled.
814 for (i = 0; i < I40E_MAX_VF; i++)
815 vf_floating_veb[i] = true;
820 kvlist = rte_kvargs_parse(devargs->args, NULL);
824 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
825 rte_kvargs_free(kvlist);
828 /* When the floating_veb_list parameter exists, all the VFs
829 * will attach to the legacy VEB firstly, then configure VFs
830 * to the floating VEB according to the floating_veb_list.
832 if (rte_kvargs_process(kvlist, floating_veb_list,
833 floating_veb_list_handler,
834 vf_floating_veb) < 0) {
835 rte_kvargs_free(kvlist);
838 rte_kvargs_free(kvlist);
842 i40e_check_floating_handler(__rte_unused const char *key,
844 __rte_unused void *opaque)
846 if (strcmp(value, "1"))
853 is_floating_veb_supported(struct rte_devargs *devargs)
855 struct rte_kvargs *kvlist;
856 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
861 kvlist = rte_kvargs_parse(devargs->args, NULL);
865 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
866 rte_kvargs_free(kvlist);
869 /* Floating VEB is enabled when there's key-value:
870 * enable_floating_veb=1
872 if (rte_kvargs_process(kvlist, floating_veb_key,
873 i40e_check_floating_handler, NULL) < 0) {
874 rte_kvargs_free(kvlist);
877 rte_kvargs_free(kvlist);
883 config_floating_veb(struct rte_eth_dev *dev)
885 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
886 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
887 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
889 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
891 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
893 is_floating_veb_supported(pci_dev->device.devargs);
894 config_vf_floating_veb(pci_dev->device.devargs,
896 pf->floating_veb_list);
898 pf->floating_veb = false;
902 #define I40E_L2_TAGS_S_TAG_SHIFT 1
903 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
906 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
909 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
910 char ethertype_hash_name[RTE_HASH_NAMESIZE];
913 struct rte_hash_parameters ethertype_hash_params = {
914 .name = ethertype_hash_name,
915 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
916 .key_len = sizeof(struct i40e_ethertype_filter_input),
917 .hash_func = rte_hash_crc,
918 .hash_func_init_val = 0,
919 .socket_id = rte_socket_id(),
922 /* Initialize ethertype filter rule list and hash */
923 TAILQ_INIT(ðertype_rule->ethertype_list);
924 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
925 "ethertype_%s", dev->device->name);
926 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
927 if (!ethertype_rule->hash_table) {
928 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
931 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
932 sizeof(struct i40e_ethertype_filter *) *
933 I40E_MAX_ETHERTYPE_FILTER_NUM,
935 if (!ethertype_rule->hash_map) {
937 "Failed to allocate memory for ethertype hash map!");
939 goto err_ethertype_hash_map_alloc;
944 err_ethertype_hash_map_alloc:
945 rte_hash_free(ethertype_rule->hash_table);
951 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
953 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
954 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
955 char tunnel_hash_name[RTE_HASH_NAMESIZE];
958 struct rte_hash_parameters tunnel_hash_params = {
959 .name = tunnel_hash_name,
960 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
961 .key_len = sizeof(struct i40e_tunnel_filter_input),
962 .hash_func = rte_hash_crc,
963 .hash_func_init_val = 0,
964 .socket_id = rte_socket_id(),
967 /* Initialize tunnel filter rule list and hash */
968 TAILQ_INIT(&tunnel_rule->tunnel_list);
969 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
970 "tunnel_%s", dev->device->name);
971 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
972 if (!tunnel_rule->hash_table) {
973 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
976 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
977 sizeof(struct i40e_tunnel_filter *) *
978 I40E_MAX_TUNNEL_FILTER_NUM,
980 if (!tunnel_rule->hash_map) {
982 "Failed to allocate memory for tunnel hash map!");
984 goto err_tunnel_hash_map_alloc;
989 err_tunnel_hash_map_alloc:
990 rte_hash_free(tunnel_rule->hash_table);
996 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
998 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
999 struct i40e_fdir_info *fdir_info = &pf->fdir;
1000 char fdir_hash_name[RTE_HASH_NAMESIZE];
1003 struct rte_hash_parameters fdir_hash_params = {
1004 .name = fdir_hash_name,
1005 .entries = I40E_MAX_FDIR_FILTER_NUM,
1006 .key_len = sizeof(struct rte_eth_fdir_input),
1007 .hash_func = rte_hash_crc,
1008 .hash_func_init_val = 0,
1009 .socket_id = rte_socket_id(),
1012 /* Initialize flow director filter rule list and hash */
1013 TAILQ_INIT(&fdir_info->fdir_list);
1014 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1015 "fdir_%s", dev->device->name);
1016 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1017 if (!fdir_info->hash_table) {
1018 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1021 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1022 sizeof(struct i40e_fdir_filter *) *
1023 I40E_MAX_FDIR_FILTER_NUM,
1025 if (!fdir_info->hash_map) {
1027 "Failed to allocate memory for fdir hash map!");
1029 goto err_fdir_hash_map_alloc;
1033 err_fdir_hash_map_alloc:
1034 rte_hash_free(fdir_info->hash_table);
1040 eth_i40e_dev_init(struct rte_eth_dev *dev)
1042 struct rte_pci_device *pci_dev;
1043 struct rte_intr_handle *intr_handle;
1044 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1045 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1046 struct i40e_vsi *vsi;
1049 uint8_t aq_fail = 0;
1051 PMD_INIT_FUNC_TRACE();
1053 dev->dev_ops = &i40e_eth_dev_ops;
1054 dev->rx_pkt_burst = i40e_recv_pkts;
1055 dev->tx_pkt_burst = i40e_xmit_pkts;
1056 dev->tx_pkt_prepare = i40e_prep_pkts;
1058 /* for secondary processes, we don't initialise any further as primary
1059 * has already done this work. Only check we don't need a different
1061 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1062 i40e_set_rx_function(dev);
1063 i40e_set_tx_function(dev);
1066 i40e_set_default_ptype_table(dev);
1067 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1068 intr_handle = &pci_dev->intr_handle;
1070 rte_eth_copy_pci_info(dev, pci_dev);
1071 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1073 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1074 pf->adapter->eth_dev = dev;
1075 pf->dev_data = dev->data;
1077 hw->back = I40E_PF_TO_ADAPTER(pf);
1078 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1081 "Hardware is not available, as address is NULL");
1085 hw->vendor_id = pci_dev->id.vendor_id;
1086 hw->device_id = pci_dev->id.device_id;
1087 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1088 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1089 hw->bus.device = pci_dev->addr.devid;
1090 hw->bus.func = pci_dev->addr.function;
1091 hw->adapter_stopped = 0;
1093 /* Make sure all is clean before doing PF reset */
1096 /* Initialize the hardware */
1099 /* Reset here to make sure all is clean for each PF */
1100 ret = i40e_pf_reset(hw);
1102 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1106 /* Initialize the shared code (base driver) */
1107 ret = i40e_init_shared_code(hw);
1109 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1114 * To work around the NVM issue, initialize registers
1115 * for flexible payload and packet type of QinQ by
1116 * software. It should be removed once issues are fixed
1119 i40e_GLQF_reg_init(hw);
1121 /* Initialize the input set for filters (hash and fd) to default value */
1122 i40e_filter_input_set_init(pf);
1124 /* Initialize the parameters for adminq */
1125 i40e_init_adminq_parameter(hw);
1126 ret = i40e_init_adminq(hw);
1127 if (ret != I40E_SUCCESS) {
1128 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1131 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1132 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1133 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1134 ((hw->nvm.version >> 12) & 0xf),
1135 ((hw->nvm.version >> 4) & 0xff),
1136 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1138 /* initialise the L3_MAP register */
1139 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1142 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1144 /* Need the special FW version to support floating VEB */
1145 config_floating_veb(dev);
1146 /* Clear PXE mode */
1147 i40e_clear_pxe_mode(hw);
1148 i40e_dev_sync_phy_type(hw);
1151 * On X710, performance number is far from the expectation on recent
1152 * firmware versions. The fix for this issue may not be integrated in
1153 * the following firmware version. So the workaround in software driver
1154 * is needed. It needs to modify the initial values of 3 internal only
1155 * registers. Note that the workaround can be removed when it is fixed
1156 * in firmware in the future.
1158 i40e_configure_registers(hw);
1160 /* Get hw capabilities */
1161 ret = i40e_get_cap(hw);
1162 if (ret != I40E_SUCCESS) {
1163 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164 goto err_get_capabilities;
1167 /* Initialize parameters for PF */
1168 ret = i40e_pf_parameter_init(dev);
1170 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171 goto err_parameter_init;
1174 /* Initialize the queue management */
1175 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1177 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178 goto err_qp_pool_init;
1180 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181 hw->func_caps.num_msix_vectors - 1);
1183 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184 goto err_msix_pool_init;
1187 /* Initialize lan hmc */
1188 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189 hw->func_caps.num_rx_qp, 0, 0);
1190 if (ret != I40E_SUCCESS) {
1191 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192 goto err_init_lan_hmc;
1195 /* Configure lan hmc */
1196 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197 if (ret != I40E_SUCCESS) {
1198 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199 goto err_configure_lan_hmc;
1202 /* Get and check the mac address */
1203 i40e_get_mac_addr(hw, hw->mac.addr);
1204 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205 PMD_INIT_LOG(ERR, "mac address is not valid");
1207 goto err_get_mac_addr;
1209 /* Copy the permanent MAC address */
1210 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211 (struct ether_addr *) hw->mac.perm_addr);
1213 /* Disable flow control */
1214 hw->fc.requested_mode = I40E_FC_NONE;
1215 i40e_set_fc(hw, &aq_fail, TRUE);
1217 /* Set the global registers with default ether type value */
1218 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219 if (ret != I40E_SUCCESS) {
1221 "Failed to set the default outer VLAN ether type");
1222 goto err_setup_pf_switch;
1225 /* PF setup, which includes VSI setup */
1226 ret = i40e_pf_setup(pf);
1228 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229 goto err_setup_pf_switch;
1232 /* reset all stats of the device, including pf and main vsi */
1233 i40e_dev_stats_reset(dev);
1237 /* Disable double vlan by default */
1238 i40e_vsi_config_double_vlan(vsi, FALSE);
1240 /* Disable S-TAG identification when floating_veb is disabled */
1241 if (!pf->floating_veb) {
1242 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1249 if (!vsi->max_macaddrs)
1250 len = ETHER_ADDR_LEN;
1252 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1254 /* Should be after VSI initialized */
1255 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256 if (!dev->data->mac_addrs) {
1258 "Failed to allocated memory for storing mac address");
1261 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262 &dev->data->mac_addrs[0]);
1264 /* Init dcb to sw mode by default */
1265 ret = i40e_dcb_init_configure(dev, TRUE);
1266 if (ret != I40E_SUCCESS) {
1267 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268 pf->flags &= ~I40E_FLAG_DCB;
1270 /* Update HW struct after DCB configuration */
1273 /* initialize pf host driver to setup SRIOV resource if applicable */
1274 i40e_pf_host_init(dev);
1276 /* register callback func to eal lib */
1277 rte_intr_callback_register(intr_handle,
1278 i40e_dev_interrupt_handler, dev);
1280 /* configure and enable device interrupt */
1281 i40e_pf_config_irq0(hw, TRUE);
1282 i40e_pf_enable_irq0(hw);
1284 /* enable uio intr after callback register */
1285 rte_intr_enable(intr_handle);
1287 * Add an ethertype filter to drop all flow control frames transmitted
1288 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1291 i40e_add_tx_flow_control_drop_filter(pf);
1293 /* Set the max frame size to 0x2600 by default,
1294 * in case other drivers changed the default value.
1296 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1298 /* initialize mirror rule list */
1299 TAILQ_INIT(&pf->mirror_list);
1301 /* initialize Traffic Manager configuration */
1302 i40e_tm_conf_init(dev);
1304 ret = i40e_init_ethtype_filter_list(dev);
1306 goto err_init_ethtype_filter_list;
1307 ret = i40e_init_tunnel_filter_list(dev);
1309 goto err_init_tunnel_filter_list;
1310 ret = i40e_init_fdir_filter_list(dev);
1312 goto err_init_fdir_filter_list;
1316 err_init_fdir_filter_list:
1317 rte_free(pf->tunnel.hash_table);
1318 rte_free(pf->tunnel.hash_map);
1319 err_init_tunnel_filter_list:
1320 rte_free(pf->ethertype.hash_table);
1321 rte_free(pf->ethertype.hash_map);
1322 err_init_ethtype_filter_list:
1323 rte_free(dev->data->mac_addrs);
1325 i40e_vsi_release(pf->main_vsi);
1326 err_setup_pf_switch:
1328 err_configure_lan_hmc:
1329 (void)i40e_shutdown_lan_hmc(hw);
1331 i40e_res_pool_destroy(&pf->msix_pool);
1333 i40e_res_pool_destroy(&pf->qp_pool);
1336 err_get_capabilities:
1337 (void)i40e_shutdown_adminq(hw);
1343 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1345 struct i40e_ethertype_filter *p_ethertype;
1346 struct i40e_ethertype_rule *ethertype_rule;
1348 ethertype_rule = &pf->ethertype;
1349 /* Remove all ethertype filter rules and hash */
1350 if (ethertype_rule->hash_map)
1351 rte_free(ethertype_rule->hash_map);
1352 if (ethertype_rule->hash_table)
1353 rte_hash_free(ethertype_rule->hash_table);
1355 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1356 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1357 p_ethertype, rules);
1358 rte_free(p_ethertype);
1363 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1365 struct i40e_tunnel_filter *p_tunnel;
1366 struct i40e_tunnel_rule *tunnel_rule;
1368 tunnel_rule = &pf->tunnel;
1369 /* Remove all tunnel director rules and hash */
1370 if (tunnel_rule->hash_map)
1371 rte_free(tunnel_rule->hash_map);
1372 if (tunnel_rule->hash_table)
1373 rte_hash_free(tunnel_rule->hash_table);
1375 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1376 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1382 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1384 struct i40e_fdir_filter *p_fdir;
1385 struct i40e_fdir_info *fdir_info;
1387 fdir_info = &pf->fdir;
1388 /* Remove all flow director rules and hash */
1389 if (fdir_info->hash_map)
1390 rte_free(fdir_info->hash_map);
1391 if (fdir_info->hash_table)
1392 rte_hash_free(fdir_info->hash_table);
1394 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1395 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1401 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1404 struct rte_pci_device *pci_dev;
1405 struct rte_intr_handle *intr_handle;
1407 struct i40e_filter_control_settings settings;
1408 struct rte_flow *p_flow;
1410 uint8_t aq_fail = 0;
1412 PMD_INIT_FUNC_TRACE();
1414 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1417 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1418 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1420 intr_handle = &pci_dev->intr_handle;
1422 if (hw->adapter_stopped == 0)
1423 i40e_dev_close(dev);
1425 dev->dev_ops = NULL;
1426 dev->rx_pkt_burst = NULL;
1427 dev->tx_pkt_burst = NULL;
1429 /* Clear PXE mode */
1430 i40e_clear_pxe_mode(hw);
1432 /* Unconfigure filter control */
1433 memset(&settings, 0, sizeof(settings));
1434 ret = i40e_set_filter_control(hw, &settings);
1436 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1439 /* Disable flow control */
1440 hw->fc.requested_mode = I40E_FC_NONE;
1441 i40e_set_fc(hw, &aq_fail, TRUE);
1443 /* uninitialize pf host driver */
1444 i40e_pf_host_uninit(dev);
1446 rte_free(dev->data->mac_addrs);
1447 dev->data->mac_addrs = NULL;
1449 /* disable uio intr before callback unregister */
1450 rte_intr_disable(intr_handle);
1452 /* register callback func to eal lib */
1453 rte_intr_callback_unregister(intr_handle,
1454 i40e_dev_interrupt_handler, dev);
1456 i40e_rm_ethtype_filter_list(pf);
1457 i40e_rm_tunnel_filter_list(pf);
1458 i40e_rm_fdir_filter_list(pf);
1460 /* Remove all flows */
1461 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1462 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1466 /* Remove all Traffic Manager configuration */
1467 i40e_tm_conf_uninit(dev);
1473 i40e_dev_configure(struct rte_eth_dev *dev)
1475 struct i40e_adapter *ad =
1476 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1477 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1478 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1479 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1482 ret = i40e_dev_sync_phy_type(hw);
1486 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1487 * bulk allocation or vector Rx preconditions we will reset it.
1489 ad->rx_bulk_alloc_allowed = true;
1490 ad->rx_vec_allowed = true;
1491 ad->tx_simple_allowed = true;
1492 ad->tx_vec_allowed = true;
1494 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1495 ret = i40e_fdir_setup(pf);
1496 if (ret != I40E_SUCCESS) {
1497 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1500 ret = i40e_fdir_configure(dev);
1502 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1506 i40e_fdir_teardown(pf);
1508 ret = i40e_dev_init_vlan(dev);
1513 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1514 * RSS setting have different requirements.
1515 * General PMD driver call sequence are NIC init, configure,
1516 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1517 * will try to lookup the VSI that specific queue belongs to if VMDQ
1518 * applicable. So, VMDQ setting has to be done before
1519 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1520 * For RSS setting, it will try to calculate actual configured RX queue
1521 * number, which will be available after rx_queue_setup(). dev_start()
1522 * function is good to place RSS setup.
1524 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1525 ret = i40e_vmdq_setup(dev);
1530 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1531 ret = i40e_dcb_setup(dev);
1533 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1538 TAILQ_INIT(&pf->flow_list);
1543 /* need to release vmdq resource if exists */
1544 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1545 i40e_vsi_release(pf->vmdq[i].vsi);
1546 pf->vmdq[i].vsi = NULL;
1551 /* need to release fdir resource if exists */
1552 i40e_fdir_teardown(pf);
1557 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1559 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1560 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1561 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1562 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1563 uint16_t msix_vect = vsi->msix_intr;
1566 for (i = 0; i < vsi->nb_qps; i++) {
1567 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1568 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1572 if (vsi->type != I40E_VSI_SRIOV) {
1573 if (!rte_intr_allow_others(intr_handle)) {
1574 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1575 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1577 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1580 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1581 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1583 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1588 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1589 vsi->user_param + (msix_vect - 1);
1591 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1592 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1594 I40E_WRITE_FLUSH(hw);
1598 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1599 int base_queue, int nb_queue,
1604 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1606 /* Bind all RX queues to allocated MSIX interrupt */
1607 for (i = 0; i < nb_queue; i++) {
1608 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1609 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1610 ((base_queue + i + 1) <<
1611 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1612 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1613 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1615 if (i == nb_queue - 1)
1616 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1617 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1620 /* Write first RX queue to Link list register as the head element */
1621 if (vsi->type != I40E_VSI_SRIOV) {
1623 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1625 if (msix_vect == I40E_MISC_VEC_ID) {
1626 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1628 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1630 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1632 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1635 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1637 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1639 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1641 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1648 if (msix_vect == I40E_MISC_VEC_ID) {
1650 I40E_VPINT_LNKLST0(vsi->user_param),
1652 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1654 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1656 /* num_msix_vectors_vf needs to minus irq0 */
1657 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1658 vsi->user_param + (msix_vect - 1);
1660 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1662 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1664 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1668 I40E_WRITE_FLUSH(hw);
1672 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1674 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1675 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1676 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1677 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1678 uint16_t msix_vect = vsi->msix_intr;
1679 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1680 uint16_t queue_idx = 0;
1685 for (i = 0; i < vsi->nb_qps; i++) {
1686 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1687 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1690 /* INTENA flag is not auto-cleared for interrupt */
1691 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1692 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1693 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1694 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1695 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1697 /* VF bind interrupt */
1698 if (vsi->type == I40E_VSI_SRIOV) {
1699 __vsi_queues_bind_intr(vsi, msix_vect,
1700 vsi->base_queue, vsi->nb_qps,
1705 /* PF & VMDq bind interrupt */
1706 if (rte_intr_dp_is_en(intr_handle)) {
1707 if (vsi->type == I40E_VSI_MAIN) {
1710 } else if (vsi->type == I40E_VSI_VMDQ2) {
1711 struct i40e_vsi *main_vsi =
1712 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1713 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1718 for (i = 0; i < vsi->nb_used_qps; i++) {
1720 if (!rte_intr_allow_others(intr_handle))
1721 /* allow to share MISC_VEC_ID */
1722 msix_vect = I40E_MISC_VEC_ID;
1724 /* no enough msix_vect, map all to one */
1725 __vsi_queues_bind_intr(vsi, msix_vect,
1726 vsi->base_queue + i,
1727 vsi->nb_used_qps - i,
1729 for (; !!record && i < vsi->nb_used_qps; i++)
1730 intr_handle->intr_vec[queue_idx + i] =
1734 /* 1:1 queue/msix_vect mapping */
1735 __vsi_queues_bind_intr(vsi, msix_vect,
1736 vsi->base_queue + i, 1,
1739 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1747 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1749 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1750 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1751 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1752 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1753 uint16_t interval = i40e_calc_itr_interval(\
1754 RTE_LIBRTE_I40E_ITR_INTERVAL);
1755 uint16_t msix_intr, i;
1757 if (rte_intr_allow_others(intr_handle))
1758 for (i = 0; i < vsi->nb_msix; i++) {
1759 msix_intr = vsi->msix_intr + i;
1760 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1761 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1762 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1763 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1765 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1768 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1769 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1770 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1771 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1773 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1775 I40E_WRITE_FLUSH(hw);
1779 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1781 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1782 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1783 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1784 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1785 uint16_t msix_intr, i;
1787 if (rte_intr_allow_others(intr_handle))
1788 for (i = 0; i < vsi->nb_msix; i++) {
1789 msix_intr = vsi->msix_intr + i;
1790 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1794 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1796 I40E_WRITE_FLUSH(hw);
1799 static inline uint8_t
1800 i40e_parse_link_speeds(uint16_t link_speeds)
1802 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1804 if (link_speeds & ETH_LINK_SPEED_40G)
1805 link_speed |= I40E_LINK_SPEED_40GB;
1806 if (link_speeds & ETH_LINK_SPEED_25G)
1807 link_speed |= I40E_LINK_SPEED_25GB;
1808 if (link_speeds & ETH_LINK_SPEED_20G)
1809 link_speed |= I40E_LINK_SPEED_20GB;
1810 if (link_speeds & ETH_LINK_SPEED_10G)
1811 link_speed |= I40E_LINK_SPEED_10GB;
1812 if (link_speeds & ETH_LINK_SPEED_1G)
1813 link_speed |= I40E_LINK_SPEED_1GB;
1814 if (link_speeds & ETH_LINK_SPEED_100M)
1815 link_speed |= I40E_LINK_SPEED_100MB;
1821 i40e_phy_conf_link(struct i40e_hw *hw,
1823 uint8_t force_speed,
1826 enum i40e_status_code status;
1827 struct i40e_aq_get_phy_abilities_resp phy_ab;
1828 struct i40e_aq_set_phy_config phy_conf;
1829 enum i40e_aq_phy_type cnt;
1830 uint32_t phy_type_mask = 0;
1832 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1833 I40E_AQ_PHY_FLAG_PAUSE_RX |
1834 I40E_AQ_PHY_FLAG_PAUSE_RX |
1835 I40E_AQ_PHY_FLAG_LOW_POWER;
1836 const uint8_t advt = I40E_LINK_SPEED_40GB |
1837 I40E_LINK_SPEED_25GB |
1838 I40E_LINK_SPEED_10GB |
1839 I40E_LINK_SPEED_1GB |
1840 I40E_LINK_SPEED_100MB;
1844 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1849 /* If link already up, no need to set up again */
1850 if (is_up && phy_ab.phy_type != 0)
1851 return I40E_SUCCESS;
1853 memset(&phy_conf, 0, sizeof(phy_conf));
1855 /* bits 0-2 use the values from get_phy_abilities_resp */
1857 abilities |= phy_ab.abilities & mask;
1859 /* update ablities and speed */
1860 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1861 phy_conf.link_speed = advt;
1863 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1865 phy_conf.abilities = abilities;
1869 /* To enable link, phy_type mask needs to include each type */
1870 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1871 phy_type_mask |= 1 << cnt;
1873 /* use get_phy_abilities_resp value for the rest */
1874 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1875 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1876 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1877 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1878 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1879 phy_conf.eee_capability = phy_ab.eee_capability;
1880 phy_conf.eeer = phy_ab.eeer_val;
1881 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1883 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1884 phy_ab.abilities, phy_ab.link_speed);
1885 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1886 phy_conf.abilities, phy_conf.link_speed);
1888 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1892 return I40E_SUCCESS;
1896 i40e_apply_link_speed(struct rte_eth_dev *dev)
1899 uint8_t abilities = 0;
1900 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901 struct rte_eth_conf *conf = &dev->data->dev_conf;
1903 speed = i40e_parse_link_speeds(conf->link_speeds);
1904 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1905 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1906 abilities |= I40E_AQ_PHY_AN_ENABLED;
1907 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1909 return i40e_phy_conf_link(hw, abilities, speed, true);
1913 i40e_dev_start(struct rte_eth_dev *dev)
1915 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1916 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917 struct i40e_vsi *main_vsi = pf->main_vsi;
1919 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1920 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1921 uint32_t intr_vector = 0;
1922 struct i40e_vsi *vsi;
1924 hw->adapter_stopped = 0;
1926 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1927 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1928 dev->data->port_id);
1932 rte_intr_disable(intr_handle);
1934 if ((rte_intr_cap_multiple(intr_handle) ||
1935 !RTE_ETH_DEV_SRIOV(dev).active) &&
1936 dev->data->dev_conf.intr_conf.rxq != 0) {
1937 intr_vector = dev->data->nb_rx_queues;
1938 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1943 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1944 intr_handle->intr_vec =
1945 rte_zmalloc("intr_vec",
1946 dev->data->nb_rx_queues * sizeof(int),
1948 if (!intr_handle->intr_vec) {
1950 "Failed to allocate %d rx_queues intr_vec",
1951 dev->data->nb_rx_queues);
1956 /* Initialize VSI */
1957 ret = i40e_dev_rxtx_init(pf);
1958 if (ret != I40E_SUCCESS) {
1959 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1963 /* Map queues with MSIX interrupt */
1964 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1965 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1966 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1967 i40e_vsi_enable_queues_intr(main_vsi);
1969 /* Map VMDQ VSI queues with MSIX interrupt */
1970 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1971 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1972 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1973 I40E_ITR_INDEX_DEFAULT);
1974 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1977 /* enable FDIR MSIX interrupt */
1978 if (pf->fdir.fdir_vsi) {
1979 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1980 I40E_ITR_INDEX_NONE);
1981 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1984 /* Enable all queues which have been configured */
1985 ret = i40e_dev_switch_queues(pf, TRUE);
1986 if (ret != I40E_SUCCESS) {
1987 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1991 /* Enable receiving broadcast packets */
1992 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1993 if (ret != I40E_SUCCESS)
1994 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1996 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1997 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1999 if (ret != I40E_SUCCESS)
2000 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2003 /* Enable the VLAN promiscuous mode. */
2005 for (i = 0; i < pf->vf_num; i++) {
2006 vsi = pf->vfs[i].vsi;
2007 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2012 /* Apply link configure */
2013 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2014 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2015 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2016 ETH_LINK_SPEED_40G)) {
2017 PMD_DRV_LOG(ERR, "Invalid link setting");
2020 ret = i40e_apply_link_speed(dev);
2021 if (I40E_SUCCESS != ret) {
2022 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2026 if (!rte_intr_allow_others(intr_handle)) {
2027 rte_intr_callback_unregister(intr_handle,
2028 i40e_dev_interrupt_handler,
2030 /* configure and enable device interrupt */
2031 i40e_pf_config_irq0(hw, FALSE);
2032 i40e_pf_enable_irq0(hw);
2034 if (dev->data->dev_conf.intr_conf.lsc != 0)
2036 "lsc won't enable because of no intr multiplex");
2038 ret = i40e_aq_set_phy_int_mask(hw,
2039 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2040 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2041 I40E_AQ_EVENT_MEDIA_NA), NULL);
2042 if (ret != I40E_SUCCESS)
2043 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2045 /* Call get_link_info aq commond to enable/disable LSE */
2046 i40e_dev_link_update(dev, 0);
2049 /* enable uio intr after callback register */
2050 rte_intr_enable(intr_handle);
2052 i40e_filter_restore(pf);
2054 if (pf->tm_conf.root && !pf->tm_conf.committed)
2055 PMD_DRV_LOG(WARNING,
2056 "please call hierarchy_commit() "
2057 "before starting the port");
2059 return I40E_SUCCESS;
2062 i40e_dev_switch_queues(pf, FALSE);
2063 i40e_dev_clear_queues(dev);
2069 i40e_dev_stop(struct rte_eth_dev *dev)
2071 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2072 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073 struct i40e_vsi *main_vsi = pf->main_vsi;
2074 struct i40e_mirror_rule *p_mirror;
2075 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2076 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2079 if (hw->adapter_stopped == 1)
2081 /* Disable all queues */
2082 i40e_dev_switch_queues(pf, FALSE);
2084 /* un-map queues with interrupt registers */
2085 i40e_vsi_disable_queues_intr(main_vsi);
2086 i40e_vsi_queues_unbind_intr(main_vsi);
2088 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2089 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2090 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2093 if (pf->fdir.fdir_vsi) {
2094 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2095 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2097 /* Clear all queues and release memory */
2098 i40e_dev_clear_queues(dev);
2101 i40e_dev_set_link_down(dev);
2103 /* Remove all mirror rules */
2104 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2105 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2108 pf->nb_mirror_rule = 0;
2110 if (!rte_intr_allow_others(intr_handle))
2111 /* resume to the default handler */
2112 rte_intr_callback_register(intr_handle,
2113 i40e_dev_interrupt_handler,
2116 /* Clean datapath event and queue/vec mapping */
2117 rte_intr_efd_disable(intr_handle);
2118 if (intr_handle->intr_vec) {
2119 rte_free(intr_handle->intr_vec);
2120 intr_handle->intr_vec = NULL;
2123 /* reset hierarchy commit */
2124 pf->tm_conf.committed = false;
2126 hw->adapter_stopped = 1;
2130 i40e_dev_close(struct rte_eth_dev *dev)
2132 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2133 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2135 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2139 PMD_INIT_FUNC_TRACE();
2142 i40e_dev_free_queues(dev);
2144 /* Disable interrupt */
2145 i40e_pf_disable_irq0(hw);
2146 rte_intr_disable(intr_handle);
2148 /* shutdown and destroy the HMC */
2149 i40e_shutdown_lan_hmc(hw);
2151 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2152 i40e_vsi_release(pf->vmdq[i].vsi);
2153 pf->vmdq[i].vsi = NULL;
2158 /* release all the existing VSIs and VEBs */
2159 i40e_fdir_teardown(pf);
2160 i40e_vsi_release(pf->main_vsi);
2162 /* shutdown the adminq */
2163 i40e_aq_queue_shutdown(hw, true);
2164 i40e_shutdown_adminq(hw);
2166 i40e_res_pool_destroy(&pf->qp_pool);
2167 i40e_res_pool_destroy(&pf->msix_pool);
2169 /* force a PF reset to clean anything leftover */
2170 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2171 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2172 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2173 I40E_WRITE_FLUSH(hw);
2177 * Reset PF device only to re-initialize resources in PMD layer
2180 i40e_dev_reset(struct rte_eth_dev *dev)
2184 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2185 * its VF to make them align with it. The detailed notification
2186 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2187 * To avoid unexpected behavior in VF, currently reset of PF with
2188 * SR-IOV activation is not supported. It might be supported later.
2190 if (dev->data->sriov.active)
2193 ret = eth_i40e_dev_uninit(dev);
2197 ret = eth_i40e_dev_init(dev);
2203 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2205 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2206 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207 struct i40e_vsi *vsi = pf->main_vsi;
2210 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2212 if (status != I40E_SUCCESS)
2213 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2215 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2217 if (status != I40E_SUCCESS)
2218 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2223 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2225 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2226 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227 struct i40e_vsi *vsi = pf->main_vsi;
2230 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2232 if (status != I40E_SUCCESS)
2233 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2235 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2237 if (status != I40E_SUCCESS)
2238 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2242 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2244 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2245 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246 struct i40e_vsi *vsi = pf->main_vsi;
2249 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2250 if (ret != I40E_SUCCESS)
2251 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2255 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2257 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2258 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2259 struct i40e_vsi *vsi = pf->main_vsi;
2262 if (dev->data->promiscuous == 1)
2263 return; /* must remain in all_multicast mode */
2265 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2266 vsi->seid, FALSE, NULL);
2267 if (ret != I40E_SUCCESS)
2268 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2272 * Set device link up.
2275 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2277 /* re-apply link speed setting */
2278 return i40e_apply_link_speed(dev);
2282 * Set device link down.
2285 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2287 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2288 uint8_t abilities = 0;
2289 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2292 return i40e_phy_conf_link(hw, abilities, speed, false);
2296 i40e_dev_link_update(struct rte_eth_dev *dev,
2297 int wait_to_complete)
2299 #define CHECK_INTERVAL 100 /* 100ms */
2300 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2301 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302 struct i40e_link_status link_status;
2303 struct rte_eth_link link, old;
2305 unsigned rep_cnt = MAX_REPEAT_TIME;
2306 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2308 memset(&link, 0, sizeof(link));
2309 memset(&old, 0, sizeof(old));
2310 memset(&link_status, 0, sizeof(link_status));
2311 rte_i40e_dev_atomic_read_link_status(dev, &old);
2314 /* Get link status information from hardware */
2315 status = i40e_aq_get_link_info(hw, enable_lse,
2316 &link_status, NULL);
2317 if (status != I40E_SUCCESS) {
2318 link.link_speed = ETH_SPEED_NUM_100M;
2319 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2320 PMD_DRV_LOG(ERR, "Failed to get link info");
2324 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2325 if (!wait_to_complete || link.link_status)
2328 rte_delay_ms(CHECK_INTERVAL);
2329 } while (--rep_cnt);
2331 if (!link.link_status)
2334 /* i40e uses full duplex only */
2335 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2337 /* Parse the link status */
2338 switch (link_status.link_speed) {
2339 case I40E_LINK_SPEED_100MB:
2340 link.link_speed = ETH_SPEED_NUM_100M;
2342 case I40E_LINK_SPEED_1GB:
2343 link.link_speed = ETH_SPEED_NUM_1G;
2345 case I40E_LINK_SPEED_10GB:
2346 link.link_speed = ETH_SPEED_NUM_10G;
2348 case I40E_LINK_SPEED_20GB:
2349 link.link_speed = ETH_SPEED_NUM_20G;
2351 case I40E_LINK_SPEED_25GB:
2352 link.link_speed = ETH_SPEED_NUM_25G;
2354 case I40E_LINK_SPEED_40GB:
2355 link.link_speed = ETH_SPEED_NUM_40G;
2358 link.link_speed = ETH_SPEED_NUM_100M;
2362 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2363 ETH_LINK_SPEED_FIXED);
2366 rte_i40e_dev_atomic_write_link_status(dev, &link);
2367 if (link.link_status == old.link_status)
2370 i40e_notify_all_vfs_link_status(dev);
2375 /* Get all the statistics of a VSI */
2377 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2379 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2380 struct i40e_eth_stats *nes = &vsi->eth_stats;
2381 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2382 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2384 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2385 vsi->offset_loaded, &oes->rx_bytes,
2387 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2388 vsi->offset_loaded, &oes->rx_unicast,
2390 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2391 vsi->offset_loaded, &oes->rx_multicast,
2392 &nes->rx_multicast);
2393 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2394 vsi->offset_loaded, &oes->rx_broadcast,
2395 &nes->rx_broadcast);
2396 /* exclude CRC bytes */
2397 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2398 nes->rx_broadcast) * ETHER_CRC_LEN;
2400 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2401 &oes->rx_discards, &nes->rx_discards);
2402 /* GLV_REPC not supported */
2403 /* GLV_RMPC not supported */
2404 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2405 &oes->rx_unknown_protocol,
2406 &nes->rx_unknown_protocol);
2407 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2408 vsi->offset_loaded, &oes->tx_bytes,
2410 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2411 vsi->offset_loaded, &oes->tx_unicast,
2413 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2414 vsi->offset_loaded, &oes->tx_multicast,
2415 &nes->tx_multicast);
2416 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2417 vsi->offset_loaded, &oes->tx_broadcast,
2418 &nes->tx_broadcast);
2419 /* GLV_TDPC not supported */
2420 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2421 &oes->tx_errors, &nes->tx_errors);
2422 vsi->offset_loaded = true;
2424 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2426 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2427 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2428 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2429 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2430 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2431 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2432 nes->rx_unknown_protocol);
2433 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2434 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2435 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2436 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2437 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2438 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2439 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2444 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2447 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2448 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2450 /* Get rx/tx bytes of internal transfer packets */
2451 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2452 I40E_GLV_GORCL(hw->port),
2454 &pf->internal_stats_offset.rx_bytes,
2455 &pf->internal_stats.rx_bytes);
2457 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2458 I40E_GLV_GOTCL(hw->port),
2460 &pf->internal_stats_offset.tx_bytes,
2461 &pf->internal_stats.tx_bytes);
2462 /* Get total internal rx packet count */
2463 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2464 I40E_GLV_UPRCL(hw->port),
2466 &pf->internal_stats_offset.rx_unicast,
2467 &pf->internal_stats.rx_unicast);
2468 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2469 I40E_GLV_MPRCL(hw->port),
2471 &pf->internal_stats_offset.rx_multicast,
2472 &pf->internal_stats.rx_multicast);
2473 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2474 I40E_GLV_BPRCL(hw->port),
2476 &pf->internal_stats_offset.rx_broadcast,
2477 &pf->internal_stats.rx_broadcast);
2479 /* exclude CRC size */
2480 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2481 pf->internal_stats.rx_multicast +
2482 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2484 /* Get statistics of struct i40e_eth_stats */
2485 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2486 I40E_GLPRT_GORCL(hw->port),
2487 pf->offset_loaded, &os->eth.rx_bytes,
2489 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2490 I40E_GLPRT_UPRCL(hw->port),
2491 pf->offset_loaded, &os->eth.rx_unicast,
2492 &ns->eth.rx_unicast);
2493 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2494 I40E_GLPRT_MPRCL(hw->port),
2495 pf->offset_loaded, &os->eth.rx_multicast,
2496 &ns->eth.rx_multicast);
2497 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2498 I40E_GLPRT_BPRCL(hw->port),
2499 pf->offset_loaded, &os->eth.rx_broadcast,
2500 &ns->eth.rx_broadcast);
2501 /* Workaround: CRC size should not be included in byte statistics,
2502 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2504 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2505 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2507 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2508 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2511 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2512 ns->eth.rx_bytes = 0;
2513 /* exlude internal rx bytes */
2515 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2517 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2518 pf->offset_loaded, &os->eth.rx_discards,
2519 &ns->eth.rx_discards);
2520 /* GLPRT_REPC not supported */
2521 /* GLPRT_RMPC not supported */
2522 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2524 &os->eth.rx_unknown_protocol,
2525 &ns->eth.rx_unknown_protocol);
2526 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2527 I40E_GLPRT_GOTCL(hw->port),
2528 pf->offset_loaded, &os->eth.tx_bytes,
2530 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2531 I40E_GLPRT_UPTCL(hw->port),
2532 pf->offset_loaded, &os->eth.tx_unicast,
2533 &ns->eth.tx_unicast);
2534 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2535 I40E_GLPRT_MPTCL(hw->port),
2536 pf->offset_loaded, &os->eth.tx_multicast,
2537 &ns->eth.tx_multicast);
2538 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2539 I40E_GLPRT_BPTCL(hw->port),
2540 pf->offset_loaded, &os->eth.tx_broadcast,
2541 &ns->eth.tx_broadcast);
2542 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2543 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2545 /* exclude internal tx bytes */
2546 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2547 ns->eth.tx_bytes = 0;
2549 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2551 /* GLPRT_TEPC not supported */
2553 /* additional port specific stats */
2554 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2555 pf->offset_loaded, &os->tx_dropped_link_down,
2556 &ns->tx_dropped_link_down);
2557 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2558 pf->offset_loaded, &os->crc_errors,
2560 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2561 pf->offset_loaded, &os->illegal_bytes,
2562 &ns->illegal_bytes);
2563 /* GLPRT_ERRBC not supported */
2564 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2565 pf->offset_loaded, &os->mac_local_faults,
2566 &ns->mac_local_faults);
2567 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2568 pf->offset_loaded, &os->mac_remote_faults,
2569 &ns->mac_remote_faults);
2570 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2571 pf->offset_loaded, &os->rx_length_errors,
2572 &ns->rx_length_errors);
2573 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2574 pf->offset_loaded, &os->link_xon_rx,
2576 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2577 pf->offset_loaded, &os->link_xoff_rx,
2579 for (i = 0; i < 8; i++) {
2580 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2582 &os->priority_xon_rx[i],
2583 &ns->priority_xon_rx[i]);
2584 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2586 &os->priority_xoff_rx[i],
2587 &ns->priority_xoff_rx[i]);
2589 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2590 pf->offset_loaded, &os->link_xon_tx,
2592 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2593 pf->offset_loaded, &os->link_xoff_tx,
2595 for (i = 0; i < 8; i++) {
2596 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2598 &os->priority_xon_tx[i],
2599 &ns->priority_xon_tx[i]);
2600 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2602 &os->priority_xoff_tx[i],
2603 &ns->priority_xoff_tx[i]);
2604 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2606 &os->priority_xon_2_xoff[i],
2607 &ns->priority_xon_2_xoff[i]);
2609 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2610 I40E_GLPRT_PRC64L(hw->port),
2611 pf->offset_loaded, &os->rx_size_64,
2613 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2614 I40E_GLPRT_PRC127L(hw->port),
2615 pf->offset_loaded, &os->rx_size_127,
2617 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2618 I40E_GLPRT_PRC255L(hw->port),
2619 pf->offset_loaded, &os->rx_size_255,
2621 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2622 I40E_GLPRT_PRC511L(hw->port),
2623 pf->offset_loaded, &os->rx_size_511,
2625 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2626 I40E_GLPRT_PRC1023L(hw->port),
2627 pf->offset_loaded, &os->rx_size_1023,
2629 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2630 I40E_GLPRT_PRC1522L(hw->port),
2631 pf->offset_loaded, &os->rx_size_1522,
2633 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2634 I40E_GLPRT_PRC9522L(hw->port),
2635 pf->offset_loaded, &os->rx_size_big,
2637 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2638 pf->offset_loaded, &os->rx_undersize,
2640 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2641 pf->offset_loaded, &os->rx_fragments,
2643 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2644 pf->offset_loaded, &os->rx_oversize,
2646 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2647 pf->offset_loaded, &os->rx_jabber,
2649 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2650 I40E_GLPRT_PTC64L(hw->port),
2651 pf->offset_loaded, &os->tx_size_64,
2653 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2654 I40E_GLPRT_PTC127L(hw->port),
2655 pf->offset_loaded, &os->tx_size_127,
2657 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2658 I40E_GLPRT_PTC255L(hw->port),
2659 pf->offset_loaded, &os->tx_size_255,
2661 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2662 I40E_GLPRT_PTC511L(hw->port),
2663 pf->offset_loaded, &os->tx_size_511,
2665 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2666 I40E_GLPRT_PTC1023L(hw->port),
2667 pf->offset_loaded, &os->tx_size_1023,
2669 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2670 I40E_GLPRT_PTC1522L(hw->port),
2671 pf->offset_loaded, &os->tx_size_1522,
2673 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2674 I40E_GLPRT_PTC9522L(hw->port),
2675 pf->offset_loaded, &os->tx_size_big,
2677 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2679 &os->fd_sb_match, &ns->fd_sb_match);
2680 /* GLPRT_MSPDC not supported */
2681 /* GLPRT_XEC not supported */
2683 pf->offset_loaded = true;
2686 i40e_update_vsi_stats(pf->main_vsi);
2689 /* Get all statistics of a port */
2691 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2693 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2694 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2695 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2698 /* call read registers - updates values, now write them to struct */
2699 i40e_read_stats_registers(pf, hw);
2701 stats->ipackets = ns->eth.rx_unicast +
2702 ns->eth.rx_multicast +
2703 ns->eth.rx_broadcast -
2704 ns->eth.rx_discards -
2705 pf->main_vsi->eth_stats.rx_discards;
2706 stats->opackets = ns->eth.tx_unicast +
2707 ns->eth.tx_multicast +
2708 ns->eth.tx_broadcast;
2709 stats->ibytes = ns->eth.rx_bytes;
2710 stats->obytes = ns->eth.tx_bytes;
2711 stats->oerrors = ns->eth.tx_errors +
2712 pf->main_vsi->eth_stats.tx_errors;
2715 stats->imissed = ns->eth.rx_discards +
2716 pf->main_vsi->eth_stats.rx_discards;
2717 stats->ierrors = ns->crc_errors +
2718 ns->rx_length_errors + ns->rx_undersize +
2719 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2721 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2722 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2723 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2724 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2725 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2726 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2727 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2728 ns->eth.rx_unknown_protocol);
2729 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2730 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2731 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2732 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2733 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2734 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2736 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2737 ns->tx_dropped_link_down);
2738 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2739 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2741 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2742 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2743 ns->mac_local_faults);
2744 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2745 ns->mac_remote_faults);
2746 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2747 ns->rx_length_errors);
2748 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2749 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2750 for (i = 0; i < 8; i++) {
2751 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2752 i, ns->priority_xon_rx[i]);
2753 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2754 i, ns->priority_xoff_rx[i]);
2756 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2757 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2758 for (i = 0; i < 8; i++) {
2759 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2760 i, ns->priority_xon_tx[i]);
2761 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2762 i, ns->priority_xoff_tx[i]);
2763 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2764 i, ns->priority_xon_2_xoff[i]);
2766 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2767 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2768 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2769 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2770 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2771 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2772 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2773 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2774 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2775 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2776 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2777 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2778 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2779 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2780 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2781 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2782 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2783 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2784 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2785 ns->mac_short_packet_dropped);
2786 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2787 ns->checksum_error);
2788 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2789 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2792 /* Reset the statistics */
2794 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2796 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2799 /* Mark PF and VSI stats to update the offset, aka "reset" */
2800 pf->offset_loaded = false;
2802 pf->main_vsi->offset_loaded = false;
2804 /* read the stats, reading current register values into offset */
2805 i40e_read_stats_registers(pf, hw);
2809 i40e_xstats_calc_num(void)
2811 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2812 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2813 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2816 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2817 struct rte_eth_xstat_name *xstats_names,
2818 __rte_unused unsigned limit)
2823 if (xstats_names == NULL)
2824 return i40e_xstats_calc_num();
2826 /* Note: limit checked in rte_eth_xstats_names() */
2828 /* Get stats from i40e_eth_stats struct */
2829 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2830 snprintf(xstats_names[count].name,
2831 sizeof(xstats_names[count].name),
2832 "%s", rte_i40e_stats_strings[i].name);
2836 /* Get individiual stats from i40e_hw_port struct */
2837 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2838 snprintf(xstats_names[count].name,
2839 sizeof(xstats_names[count].name),
2840 "%s", rte_i40e_hw_port_strings[i].name);
2844 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2845 for (prio = 0; prio < 8; prio++) {
2846 snprintf(xstats_names[count].name,
2847 sizeof(xstats_names[count].name),
2848 "rx_priority%u_%s", prio,
2849 rte_i40e_rxq_prio_strings[i].name);
2854 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2855 for (prio = 0; prio < 8; prio++) {
2856 snprintf(xstats_names[count].name,
2857 sizeof(xstats_names[count].name),
2858 "tx_priority%u_%s", prio,
2859 rte_i40e_txq_prio_strings[i].name);
2867 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2870 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2872 unsigned i, count, prio;
2873 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2875 count = i40e_xstats_calc_num();
2879 i40e_read_stats_registers(pf, hw);
2886 /* Get stats from i40e_eth_stats struct */
2887 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2888 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2889 rte_i40e_stats_strings[i].offset);
2890 xstats[count].id = count;
2894 /* Get individiual stats from i40e_hw_port struct */
2895 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2896 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2897 rte_i40e_hw_port_strings[i].offset);
2898 xstats[count].id = count;
2902 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2903 for (prio = 0; prio < 8; prio++) {
2904 xstats[count].value =
2905 *(uint64_t *)(((char *)hw_stats) +
2906 rte_i40e_rxq_prio_strings[i].offset +
2907 (sizeof(uint64_t) * prio));
2908 xstats[count].id = count;
2913 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2914 for (prio = 0; prio < 8; prio++) {
2915 xstats[count].value =
2916 *(uint64_t *)(((char *)hw_stats) +
2917 rte_i40e_txq_prio_strings[i].offset +
2918 (sizeof(uint64_t) * prio));
2919 xstats[count].id = count;
2928 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2929 __rte_unused uint16_t queue_id,
2930 __rte_unused uint8_t stat_idx,
2931 __rte_unused uint8_t is_rx)
2933 PMD_INIT_FUNC_TRACE();
2939 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2941 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947 full_ver = hw->nvm.oem_ver;
2948 ver = (u8)(full_ver >> 24);
2949 build = (u16)((full_ver >> 8) & 0xffff);
2950 patch = (u8)(full_ver & 0xff);
2952 ret = snprintf(fw_version, fw_size,
2953 "%d.%d%d 0x%08x %d.%d.%d",
2954 ((hw->nvm.version >> 12) & 0xf),
2955 ((hw->nvm.version >> 4) & 0xff),
2956 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2959 ret += 1; /* add the size of '\0' */
2960 if (fw_size < (u32)ret)
2967 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2969 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2970 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971 struct i40e_vsi *vsi = pf->main_vsi;
2972 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2974 dev_info->pci_dev = pci_dev;
2975 dev_info->max_rx_queues = vsi->nb_qps;
2976 dev_info->max_tx_queues = vsi->nb_qps;
2977 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2978 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2979 dev_info->max_mac_addrs = vsi->max_macaddrs;
2980 dev_info->max_vfs = pci_dev->max_vfs;
2981 dev_info->rx_offload_capa =
2982 DEV_RX_OFFLOAD_VLAN_STRIP |
2983 DEV_RX_OFFLOAD_QINQ_STRIP |
2984 DEV_RX_OFFLOAD_IPV4_CKSUM |
2985 DEV_RX_OFFLOAD_UDP_CKSUM |
2986 DEV_RX_OFFLOAD_TCP_CKSUM;
2987 dev_info->tx_offload_capa =
2988 DEV_TX_OFFLOAD_VLAN_INSERT |
2989 DEV_TX_OFFLOAD_QINQ_INSERT |
2990 DEV_TX_OFFLOAD_IPV4_CKSUM |
2991 DEV_TX_OFFLOAD_UDP_CKSUM |
2992 DEV_TX_OFFLOAD_TCP_CKSUM |
2993 DEV_TX_OFFLOAD_SCTP_CKSUM |
2994 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2995 DEV_TX_OFFLOAD_TCP_TSO |
2996 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2997 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2998 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2999 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3000 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3002 dev_info->reta_size = pf->hash_lut_size;
3003 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
3005 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3007 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3008 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3009 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3011 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3015 dev_info->default_txconf = (struct rte_eth_txconf) {
3017 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3018 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3019 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3021 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3022 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3023 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3024 ETH_TXQ_FLAGS_NOOFFLOADS,
3027 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3028 .nb_max = I40E_MAX_RING_DESC,
3029 .nb_min = I40E_MIN_RING_DESC,
3030 .nb_align = I40E_ALIGN_RING_DESC,
3033 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3034 .nb_max = I40E_MAX_RING_DESC,
3035 .nb_min = I40E_MIN_RING_DESC,
3036 .nb_align = I40E_ALIGN_RING_DESC,
3037 .nb_seg_max = I40E_TX_MAX_SEG,
3038 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3041 if (pf->flags & I40E_FLAG_VMDQ) {
3042 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3043 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3044 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3045 pf->max_nb_vmdq_vsi;
3046 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3047 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3048 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3051 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3053 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3054 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3056 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3059 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3063 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3065 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3066 struct i40e_vsi *vsi = pf->main_vsi;
3067 PMD_INIT_FUNC_TRACE();
3070 return i40e_vsi_add_vlan(vsi, vlan_id);
3072 return i40e_vsi_delete_vlan(vsi, vlan_id);
3076 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3077 enum rte_vlan_type vlan_type,
3078 uint16_t tpid, int qinq)
3080 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3083 uint16_t reg_id = 3;
3087 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3091 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3093 if (ret != I40E_SUCCESS) {
3095 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3100 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3103 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3104 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3105 if (reg_r == reg_w) {
3106 PMD_DRV_LOG(DEBUG, "No need to write");
3110 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3112 if (ret != I40E_SUCCESS) {
3114 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3119 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3126 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3127 enum rte_vlan_type vlan_type,
3130 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3134 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3135 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3136 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3138 "Unsupported vlan type.");
3141 /* 802.1ad frames ability is added in NVM API 1.7*/
3142 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3144 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3145 hw->first_tag = rte_cpu_to_le_16(tpid);
3146 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3147 hw->second_tag = rte_cpu_to_le_16(tpid);
3149 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3150 hw->second_tag = rte_cpu_to_le_16(tpid);
3152 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3153 if (ret != I40E_SUCCESS) {
3155 "Set switch config failed aq_err: %d",
3156 hw->aq.asq_last_status);
3160 /* If NVM API < 1.7, keep the register setting */
3161 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3168 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3170 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3171 struct i40e_vsi *vsi = pf->main_vsi;
3173 if (mask & ETH_VLAN_FILTER_MASK) {
3174 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3175 i40e_vsi_config_vlan_filter(vsi, TRUE);
3177 i40e_vsi_config_vlan_filter(vsi, FALSE);
3180 if (mask & ETH_VLAN_STRIP_MASK) {
3181 /* Enable or disable VLAN stripping */
3182 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3183 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3185 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3188 if (mask & ETH_VLAN_EXTEND_MASK) {
3189 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3190 i40e_vsi_config_double_vlan(vsi, TRUE);
3191 /* Set global registers with default ethertype. */
3192 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3194 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3198 i40e_vsi_config_double_vlan(vsi, FALSE);
3203 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3204 __rte_unused uint16_t queue,
3205 __rte_unused int on)
3207 PMD_INIT_FUNC_TRACE();
3211 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3213 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3214 struct i40e_vsi *vsi = pf->main_vsi;
3215 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3216 struct i40e_vsi_vlan_pvid_info info;
3218 memset(&info, 0, sizeof(info));
3221 info.config.pvid = pvid;
3223 info.config.reject.tagged =
3224 data->dev_conf.txmode.hw_vlan_reject_tagged;
3225 info.config.reject.untagged =
3226 data->dev_conf.txmode.hw_vlan_reject_untagged;
3229 return i40e_vsi_vlan_pvid_set(vsi, &info);
3233 i40e_dev_led_on(struct rte_eth_dev *dev)
3235 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3236 uint32_t mode = i40e_led_get(hw);
3239 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3245 i40e_dev_led_off(struct rte_eth_dev *dev)
3247 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3248 uint32_t mode = i40e_led_get(hw);
3251 i40e_led_set(hw, 0, false);
3257 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3259 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3260 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3262 fc_conf->pause_time = pf->fc_conf.pause_time;
3264 /* read out from register, in case they are modified by other port */
3265 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3266 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3267 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3268 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3270 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3271 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3273 /* Return current mode according to actual setting*/
3274 switch (hw->fc.current_mode) {
3276 fc_conf->mode = RTE_FC_FULL;
3278 case I40E_FC_TX_PAUSE:
3279 fc_conf->mode = RTE_FC_TX_PAUSE;
3281 case I40E_FC_RX_PAUSE:
3282 fc_conf->mode = RTE_FC_RX_PAUSE;
3286 fc_conf->mode = RTE_FC_NONE;
3293 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3295 uint32_t mflcn_reg, fctrl_reg, reg;
3296 uint32_t max_high_water;
3297 uint8_t i, aq_failure;
3301 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3302 [RTE_FC_NONE] = I40E_FC_NONE,
3303 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3304 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3305 [RTE_FC_FULL] = I40E_FC_FULL
3308 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3310 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3311 if ((fc_conf->high_water > max_high_water) ||
3312 (fc_conf->high_water < fc_conf->low_water)) {
3314 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3319 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3320 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3321 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3323 pf->fc_conf.pause_time = fc_conf->pause_time;
3324 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3325 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3327 PMD_INIT_FUNC_TRACE();
3329 /* All the link flow control related enable/disable register
3330 * configuration is handle by the F/W
3332 err = i40e_set_fc(hw, &aq_failure, true);
3336 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3337 /* Configure flow control refresh threshold,
3338 * the value for stat_tx_pause_refresh_timer[8]
3339 * is used for global pause operation.
3343 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3344 pf->fc_conf.pause_time);
3346 /* configure the timer value included in transmitted pause
3348 * the value for stat_tx_pause_quanta[8] is used for global
3351 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3352 pf->fc_conf.pause_time);
3354 fctrl_reg = I40E_READ_REG(hw,
3355 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3357 if (fc_conf->mac_ctrl_frame_fwd != 0)
3358 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3360 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3362 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3365 /* Configure pause time (2 TCs per register) */
3366 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3367 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3368 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3370 /* Configure flow control refresh threshold value */
3371 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3372 pf->fc_conf.pause_time / 2);
3374 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3376 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3377 *depending on configuration
3379 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3380 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3381 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3383 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3384 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3387 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3390 /* config the water marker both based on the packets and bytes */
3391 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3392 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3393 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3394 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3395 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3396 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3397 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3398 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3400 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3401 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3404 I40E_WRITE_FLUSH(hw);
3410 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3411 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3413 PMD_INIT_FUNC_TRACE();
3418 /* Add a MAC address, and update filters */
3420 i40e_macaddr_add(struct rte_eth_dev *dev,
3421 struct ether_addr *mac_addr,
3422 __rte_unused uint32_t index,
3425 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3426 struct i40e_mac_filter_info mac_filter;
3427 struct i40e_vsi *vsi;
3430 /* If VMDQ not enabled or configured, return */
3431 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3432 !pf->nb_cfg_vmdq_vsi)) {
3433 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3434 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3439 if (pool > pf->nb_cfg_vmdq_vsi) {
3440 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3441 pool, pf->nb_cfg_vmdq_vsi);
3445 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3446 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3447 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3449 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3454 vsi = pf->vmdq[pool - 1].vsi;
3456 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3457 if (ret != I40E_SUCCESS) {
3458 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3464 /* Remove a MAC address, and update filters */
3466 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3468 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3469 struct i40e_vsi *vsi;
3470 struct rte_eth_dev_data *data = dev->data;
3471 struct ether_addr *macaddr;
3476 macaddr = &(data->mac_addrs[index]);
3478 pool_sel = dev->data->mac_pool_sel[index];
3480 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3481 if (pool_sel & (1ULL << i)) {
3485 /* No VMDQ pool enabled or configured */
3486 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3487 (i > pf->nb_cfg_vmdq_vsi)) {
3489 "No VMDQ pool enabled/configured");
3492 vsi = pf->vmdq[i - 1].vsi;
3494 ret = i40e_vsi_delete_mac(vsi, macaddr);
3497 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3504 /* Set perfect match or hash match of MAC and VLAN for a VF */
3506 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3507 struct rte_eth_mac_filter *filter,
3511 struct i40e_mac_filter_info mac_filter;
3512 struct ether_addr old_mac;
3513 struct ether_addr *new_mac;
3514 struct i40e_pf_vf *vf = NULL;
3519 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3522 hw = I40E_PF_TO_HW(pf);
3524 if (filter == NULL) {
3525 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3529 new_mac = &filter->mac_addr;
3531 if (is_zero_ether_addr(new_mac)) {
3532 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3536 vf_id = filter->dst_id;
3538 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3539 PMD_DRV_LOG(ERR, "Invalid argument.");
3542 vf = &pf->vfs[vf_id];
3544 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3545 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3550 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3551 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3553 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3556 mac_filter.filter_type = filter->filter_type;
3557 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3558 if (ret != I40E_SUCCESS) {
3559 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3562 ether_addr_copy(new_mac, &pf->dev_addr);
3564 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3566 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3567 if (ret != I40E_SUCCESS) {
3568 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3572 /* Clear device address as it has been removed */
3573 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3574 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3580 /* MAC filter handle */
3582 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3585 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3586 struct rte_eth_mac_filter *filter;
3587 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3588 int ret = I40E_NOT_SUPPORTED;
3590 filter = (struct rte_eth_mac_filter *)(arg);
3592 switch (filter_op) {
3593 case RTE_ETH_FILTER_NOP:
3596 case RTE_ETH_FILTER_ADD:
3597 i40e_pf_disable_irq0(hw);
3599 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3600 i40e_pf_enable_irq0(hw);
3602 case RTE_ETH_FILTER_DELETE:
3603 i40e_pf_disable_irq0(hw);
3605 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3606 i40e_pf_enable_irq0(hw);
3609 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3610 ret = I40E_ERR_PARAM;
3618 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3620 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3621 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3627 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3628 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3631 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3635 uint32_t *lut_dw = (uint32_t *)lut;
3636 uint16_t i, lut_size_dw = lut_size / 4;
3638 for (i = 0; i < lut_size_dw; i++)
3639 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3646 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3655 pf = I40E_VSI_TO_PF(vsi);
3656 hw = I40E_VSI_TO_HW(vsi);
3658 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3659 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3662 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3666 uint32_t *lut_dw = (uint32_t *)lut;
3667 uint16_t i, lut_size_dw = lut_size / 4;
3669 for (i = 0; i < lut_size_dw; i++)
3670 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3671 I40E_WRITE_FLUSH(hw);
3678 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3679 struct rte_eth_rss_reta_entry64 *reta_conf,
3682 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3683 uint16_t i, lut_size = pf->hash_lut_size;
3684 uint16_t idx, shift;
3688 if (reta_size != lut_size ||
3689 reta_size > ETH_RSS_RETA_SIZE_512) {
3691 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3692 reta_size, lut_size);
3696 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3698 PMD_DRV_LOG(ERR, "No memory can be allocated");
3701 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3704 for (i = 0; i < reta_size; i++) {
3705 idx = i / RTE_RETA_GROUP_SIZE;
3706 shift = i % RTE_RETA_GROUP_SIZE;
3707 if (reta_conf[idx].mask & (1ULL << shift))
3708 lut[i] = reta_conf[idx].reta[shift];
3710 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3719 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3720 struct rte_eth_rss_reta_entry64 *reta_conf,
3723 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3724 uint16_t i, lut_size = pf->hash_lut_size;
3725 uint16_t idx, shift;
3729 if (reta_size != lut_size ||
3730 reta_size > ETH_RSS_RETA_SIZE_512) {
3732 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3733 reta_size, lut_size);
3737 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3739 PMD_DRV_LOG(ERR, "No memory can be allocated");
3743 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3746 for (i = 0; i < reta_size; i++) {
3747 idx = i / RTE_RETA_GROUP_SIZE;
3748 shift = i % RTE_RETA_GROUP_SIZE;
3749 if (reta_conf[idx].mask & (1ULL << shift))
3750 reta_conf[idx].reta[shift] = lut[i];
3760 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3761 * @hw: pointer to the HW structure
3762 * @mem: pointer to mem struct to fill out
3763 * @size: size of memory requested
3764 * @alignment: what to align the allocation to
3766 enum i40e_status_code
3767 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3768 struct i40e_dma_mem *mem,
3772 const struct rte_memzone *mz = NULL;
3773 char z_name[RTE_MEMZONE_NAMESIZE];
3776 return I40E_ERR_PARAM;
3778 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3779 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3780 alignment, RTE_PGSIZE_2M);
3782 return I40E_ERR_NO_MEMORY;
3786 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3787 mem->zone = (const void *)mz;
3789 "memzone %s allocated with physical address: %"PRIu64,
3792 return I40E_SUCCESS;
3796 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3797 * @hw: pointer to the HW structure
3798 * @mem: ptr to mem struct to free
3800 enum i40e_status_code
3801 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3802 struct i40e_dma_mem *mem)
3805 return I40E_ERR_PARAM;
3808 "memzone %s to be freed with physical address: %"PRIu64,
3809 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3810 rte_memzone_free((const struct rte_memzone *)mem->zone);
3815 return I40E_SUCCESS;
3819 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3820 * @hw: pointer to the HW structure
3821 * @mem: pointer to mem struct to fill out
3822 * @size: size of memory requested
3824 enum i40e_status_code
3825 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3826 struct i40e_virt_mem *mem,
3830 return I40E_ERR_PARAM;
3833 mem->va = rte_zmalloc("i40e", size, 0);
3836 return I40E_SUCCESS;
3838 return I40E_ERR_NO_MEMORY;
3842 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3843 * @hw: pointer to the HW structure
3844 * @mem: pointer to mem struct to free
3846 enum i40e_status_code
3847 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3848 struct i40e_virt_mem *mem)
3851 return I40E_ERR_PARAM;
3856 return I40E_SUCCESS;
3860 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3862 rte_spinlock_init(&sp->spinlock);
3866 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3868 rte_spinlock_lock(&sp->spinlock);
3872 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3874 rte_spinlock_unlock(&sp->spinlock);
3878 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3884 * Get the hardware capabilities, which will be parsed
3885 * and saved into struct i40e_hw.
3888 i40e_get_cap(struct i40e_hw *hw)
3890 struct i40e_aqc_list_capabilities_element_resp *buf;
3891 uint16_t len, size = 0;
3894 /* Calculate a huge enough buff for saving response data temporarily */
3895 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3896 I40E_MAX_CAP_ELE_NUM;
3897 buf = rte_zmalloc("i40e", len, 0);
3899 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3900 return I40E_ERR_NO_MEMORY;
3903 /* Get, parse the capabilities and save it to hw */
3904 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3905 i40e_aqc_opc_list_func_capabilities, NULL);
3906 if (ret != I40E_SUCCESS)
3907 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3909 /* Free the temporary buffer after being used */
3916 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3918 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3919 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3920 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3921 uint16_t qp_count = 0, vsi_count = 0;
3923 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3924 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3927 /* Add the parameter init for LFC */
3928 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3929 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3930 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3932 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3933 pf->max_num_vsi = hw->func_caps.num_vsis;
3934 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3935 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3936 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3938 /* FDir queue/VSI allocation */
3939 pf->fdir_qp_offset = 0;
3940 if (hw->func_caps.fd) {
3941 pf->flags |= I40E_FLAG_FDIR;
3942 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3944 pf->fdir_nb_qps = 0;
3946 qp_count += pf->fdir_nb_qps;
3949 /* LAN queue/VSI allocation */
3950 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3951 if (!hw->func_caps.rss) {
3954 pf->flags |= I40E_FLAG_RSS;
3955 if (hw->mac.type == I40E_MAC_X722)
3956 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3957 pf->lan_nb_qps = pf->lan_nb_qp_max;
3959 qp_count += pf->lan_nb_qps;
3962 /* VF queue/VSI allocation */
3963 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3964 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3965 pf->flags |= I40E_FLAG_SRIOV;
3966 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3967 pf->vf_num = pci_dev->max_vfs;
3969 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3970 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3975 qp_count += pf->vf_nb_qps * pf->vf_num;
3976 vsi_count += pf->vf_num;
3978 /* VMDq queue/VSI allocation */
3979 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3980 pf->vmdq_nb_qps = 0;
3981 pf->max_nb_vmdq_vsi = 0;
3982 if (hw->func_caps.vmdq) {
3983 if (qp_count < hw->func_caps.num_tx_qp &&
3984 vsi_count < hw->func_caps.num_vsis) {
3985 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3986 qp_count) / pf->vmdq_nb_qp_max;
3988 /* Limit the maximum number of VMDq vsi to the maximum
3989 * ethdev can support
3991 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3992 hw->func_caps.num_vsis - vsi_count);
3993 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3995 if (pf->max_nb_vmdq_vsi) {
3996 pf->flags |= I40E_FLAG_VMDQ;
3997 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3999 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4000 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4001 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4004 "No enough queues left for VMDq");
4007 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4010 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4011 vsi_count += pf->max_nb_vmdq_vsi;
4013 if (hw->func_caps.dcb)
4014 pf->flags |= I40E_FLAG_DCB;
4016 if (qp_count > hw->func_caps.num_tx_qp) {
4018 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4019 qp_count, hw->func_caps.num_tx_qp);
4022 if (vsi_count > hw->func_caps.num_vsis) {
4024 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4025 vsi_count, hw->func_caps.num_vsis);
4033 i40e_pf_get_switch_config(struct i40e_pf *pf)
4035 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4036 struct i40e_aqc_get_switch_config_resp *switch_config;
4037 struct i40e_aqc_switch_config_element_resp *element;
4038 uint16_t start_seid = 0, num_reported;
4041 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4042 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4043 if (!switch_config) {
4044 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4048 /* Get the switch configurations */
4049 ret = i40e_aq_get_switch_config(hw, switch_config,
4050 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4051 if (ret != I40E_SUCCESS) {
4052 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4055 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4056 if (num_reported != 1) { /* The number should be 1 */
4057 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4061 /* Parse the switch configuration elements */
4062 element = &(switch_config->element[0]);
4063 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4064 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4065 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4067 PMD_DRV_LOG(INFO, "Unknown element type");
4070 rte_free(switch_config);
4076 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4079 struct pool_entry *entry;
4081 if (pool == NULL || num == 0)
4084 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4085 if (entry == NULL) {
4086 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4090 /* queue heap initialize */
4091 pool->num_free = num;
4092 pool->num_alloc = 0;
4094 LIST_INIT(&pool->alloc_list);
4095 LIST_INIT(&pool->free_list);
4097 /* Initialize element */
4101 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4106 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4108 struct pool_entry *entry, *next_entry;
4113 for (entry = LIST_FIRST(&pool->alloc_list);
4114 entry && (next_entry = LIST_NEXT(entry, next), 1);
4115 entry = next_entry) {
4116 LIST_REMOVE(entry, next);
4120 for (entry = LIST_FIRST(&pool->free_list);
4121 entry && (next_entry = LIST_NEXT(entry, next), 1);
4122 entry = next_entry) {
4123 LIST_REMOVE(entry, next);
4128 pool->num_alloc = 0;
4130 LIST_INIT(&pool->alloc_list);
4131 LIST_INIT(&pool->free_list);
4135 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4138 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4139 uint32_t pool_offset;
4143 PMD_DRV_LOG(ERR, "Invalid parameter");
4147 pool_offset = base - pool->base;
4148 /* Lookup in alloc list */
4149 LIST_FOREACH(entry, &pool->alloc_list, next) {
4150 if (entry->base == pool_offset) {
4151 valid_entry = entry;
4152 LIST_REMOVE(entry, next);
4157 /* Not find, return */
4158 if (valid_entry == NULL) {
4159 PMD_DRV_LOG(ERR, "Failed to find entry");
4164 * Found it, move it to free list and try to merge.
4165 * In order to make merge easier, always sort it by qbase.
4166 * Find adjacent prev and last entries.
4169 LIST_FOREACH(entry, &pool->free_list, next) {
4170 if (entry->base > valid_entry->base) {
4178 /* Try to merge with next one*/
4180 /* Merge with next one */
4181 if (valid_entry->base + valid_entry->len == next->base) {
4182 next->base = valid_entry->base;
4183 next->len += valid_entry->len;
4184 rte_free(valid_entry);
4191 /* Merge with previous one */
4192 if (prev->base + prev->len == valid_entry->base) {
4193 prev->len += valid_entry->len;
4194 /* If it merge with next one, remove next node */
4196 LIST_REMOVE(valid_entry, next);
4197 rte_free(valid_entry);
4199 rte_free(valid_entry);
4205 /* Not find any entry to merge, insert */
4208 LIST_INSERT_AFTER(prev, valid_entry, next);
4209 else if (next != NULL)
4210 LIST_INSERT_BEFORE(next, valid_entry, next);
4211 else /* It's empty list, insert to head */
4212 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4215 pool->num_free += valid_entry->len;
4216 pool->num_alloc -= valid_entry->len;
4222 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4225 struct pool_entry *entry, *valid_entry;
4227 if (pool == NULL || num == 0) {
4228 PMD_DRV_LOG(ERR, "Invalid parameter");
4232 if (pool->num_free < num) {
4233 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4234 num, pool->num_free);
4239 /* Lookup in free list and find most fit one */
4240 LIST_FOREACH(entry, &pool->free_list, next) {
4241 if (entry->len >= num) {
4243 if (entry->len == num) {
4244 valid_entry = entry;
4247 if (valid_entry == NULL || valid_entry->len > entry->len)
4248 valid_entry = entry;
4252 /* Not find one to satisfy the request, return */
4253 if (valid_entry == NULL) {
4254 PMD_DRV_LOG(ERR, "No valid entry found");
4258 * The entry have equal queue number as requested,
4259 * remove it from alloc_list.
4261 if (valid_entry->len == num) {
4262 LIST_REMOVE(valid_entry, next);
4265 * The entry have more numbers than requested,
4266 * create a new entry for alloc_list and minus its
4267 * queue base and number in free_list.
4269 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4270 if (entry == NULL) {
4272 "Failed to allocate memory for resource pool");
4275 entry->base = valid_entry->base;
4277 valid_entry->base += num;
4278 valid_entry->len -= num;
4279 valid_entry = entry;
4282 /* Insert it into alloc list, not sorted */
4283 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4285 pool->num_free -= valid_entry->len;
4286 pool->num_alloc += valid_entry->len;
4288 return valid_entry->base + pool->base;
4292 * bitmap_is_subset - Check whether src2 is subset of src1
4295 bitmap_is_subset(uint8_t src1, uint8_t src2)
4297 return !((src1 ^ src2) & src2);
4300 static enum i40e_status_code
4301 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4303 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4305 /* If DCB is not supported, only default TC is supported */
4306 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4307 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4308 return I40E_NOT_SUPPORTED;
4311 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4313 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4314 hw->func_caps.enabled_tcmap, enabled_tcmap);
4315 return I40E_NOT_SUPPORTED;
4317 return I40E_SUCCESS;
4321 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4322 struct i40e_vsi_vlan_pvid_info *info)
4325 struct i40e_vsi_context ctxt;
4326 uint8_t vlan_flags = 0;
4329 if (vsi == NULL || info == NULL) {
4330 PMD_DRV_LOG(ERR, "invalid parameters");
4331 return I40E_ERR_PARAM;
4335 vsi->info.pvid = info->config.pvid;
4337 * If insert pvid is enabled, only tagged pkts are
4338 * allowed to be sent out.
4340 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4341 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4344 if (info->config.reject.tagged == 0)
4345 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4347 if (info->config.reject.untagged == 0)
4348 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4350 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4351 I40E_AQ_VSI_PVLAN_MODE_MASK);
4352 vsi->info.port_vlan_flags |= vlan_flags;
4353 vsi->info.valid_sections =
4354 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4355 memset(&ctxt, 0, sizeof(ctxt));
4356 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4357 ctxt.seid = vsi->seid;
4359 hw = I40E_VSI_TO_HW(vsi);
4360 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4361 if (ret != I40E_SUCCESS)
4362 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4368 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4370 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4372 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4374 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4375 if (ret != I40E_SUCCESS)
4379 PMD_DRV_LOG(ERR, "seid not valid");
4383 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4384 tc_bw_data.tc_valid_bits = enabled_tcmap;
4385 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4386 tc_bw_data.tc_bw_credits[i] =
4387 (enabled_tcmap & (1 << i)) ? 1 : 0;
4389 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4390 if (ret != I40E_SUCCESS) {
4391 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4395 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4396 sizeof(vsi->info.qs_handle));
4397 return I40E_SUCCESS;
4400 static enum i40e_status_code
4401 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4402 struct i40e_aqc_vsi_properties_data *info,
4403 uint8_t enabled_tcmap)
4405 enum i40e_status_code ret;
4406 int i, total_tc = 0;
4407 uint16_t qpnum_per_tc, bsf, qp_idx;
4409 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4410 if (ret != I40E_SUCCESS)
4413 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4414 if (enabled_tcmap & (1 << i))
4418 vsi->enabled_tc = enabled_tcmap;
4420 /* Number of queues per enabled TC */
4421 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4422 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4423 bsf = rte_bsf32(qpnum_per_tc);
4425 /* Adjust the queue number to actual queues that can be applied */
4426 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4427 vsi->nb_qps = qpnum_per_tc * total_tc;
4430 * Configure TC and queue mapping parameters, for enabled TC,
4431 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4432 * default queue will serve it.
4435 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4436 if (vsi->enabled_tc & (1 << i)) {
4437 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4438 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4439 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4440 qp_idx += qpnum_per_tc;
4442 info->tc_mapping[i] = 0;
4445 /* Associate queue number with VSI */
4446 if (vsi->type == I40E_VSI_SRIOV) {
4447 info->mapping_flags |=
4448 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4449 for (i = 0; i < vsi->nb_qps; i++)
4450 info->queue_mapping[i] =
4451 rte_cpu_to_le_16(vsi->base_queue + i);
4453 info->mapping_flags |=
4454 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4455 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4457 info->valid_sections |=
4458 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4460 return I40E_SUCCESS;
4464 i40e_veb_release(struct i40e_veb *veb)
4466 struct i40e_vsi *vsi;
4472 if (!TAILQ_EMPTY(&veb->head)) {
4473 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4476 /* associate_vsi field is NULL for floating VEB */
4477 if (veb->associate_vsi != NULL) {
4478 vsi = veb->associate_vsi;
4479 hw = I40E_VSI_TO_HW(vsi);
4481 vsi->uplink_seid = veb->uplink_seid;
4484 veb->associate_pf->main_vsi->floating_veb = NULL;
4485 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4488 i40e_aq_delete_element(hw, veb->seid, NULL);
4490 return I40E_SUCCESS;
4494 static struct i40e_veb *
4495 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4497 struct i40e_veb *veb;
4503 "veb setup failed, associated PF shouldn't null");
4506 hw = I40E_PF_TO_HW(pf);
4508 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4510 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4514 veb->associate_vsi = vsi;
4515 veb->associate_pf = pf;
4516 TAILQ_INIT(&veb->head);
4517 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4519 /* create floating veb if vsi is NULL */
4521 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4522 I40E_DEFAULT_TCMAP, false,
4523 &veb->seid, false, NULL);
4525 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4526 true, &veb->seid, false, NULL);
4529 if (ret != I40E_SUCCESS) {
4530 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4531 hw->aq.asq_last_status);
4534 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4536 /* get statistics index */
4537 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4538 &veb->stats_idx, NULL, NULL, NULL);
4539 if (ret != I40E_SUCCESS) {
4540 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4541 hw->aq.asq_last_status);
4544 /* Get VEB bandwidth, to be implemented */
4545 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4547 vsi->uplink_seid = veb->seid;
4556 i40e_vsi_release(struct i40e_vsi *vsi)
4560 struct i40e_vsi_list *vsi_list;
4563 struct i40e_mac_filter *f;
4564 uint16_t user_param;
4567 return I40E_SUCCESS;
4572 user_param = vsi->user_param;
4574 pf = I40E_VSI_TO_PF(vsi);
4575 hw = I40E_VSI_TO_HW(vsi);
4577 /* VSI has child to attach, release child first */
4579 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4580 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4583 i40e_veb_release(vsi->veb);
4586 if (vsi->floating_veb) {
4587 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4588 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4593 /* Remove all macvlan filters of the VSI */
4594 i40e_vsi_remove_all_macvlan_filter(vsi);
4595 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4598 if (vsi->type != I40E_VSI_MAIN &&
4599 ((vsi->type != I40E_VSI_SRIOV) ||
4600 !pf->floating_veb_list[user_param])) {
4601 /* Remove vsi from parent's sibling list */
4602 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4603 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4604 return I40E_ERR_PARAM;
4606 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4607 &vsi->sib_vsi_list, list);
4609 /* Remove all switch element of the VSI */
4610 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4611 if (ret != I40E_SUCCESS)
4612 PMD_DRV_LOG(ERR, "Failed to delete element");
4615 if ((vsi->type == I40E_VSI_SRIOV) &&
4616 pf->floating_veb_list[user_param]) {
4617 /* Remove vsi from parent's sibling list */
4618 if (vsi->parent_vsi == NULL ||
4619 vsi->parent_vsi->floating_veb == NULL) {
4620 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4621 return I40E_ERR_PARAM;
4623 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4624 &vsi->sib_vsi_list, list);
4626 /* Remove all switch element of the VSI */
4627 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4628 if (ret != I40E_SUCCESS)
4629 PMD_DRV_LOG(ERR, "Failed to delete element");
4632 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4634 if (vsi->type != I40E_VSI_SRIOV)
4635 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4638 return I40E_SUCCESS;
4642 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4644 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4645 struct i40e_aqc_remove_macvlan_element_data def_filter;
4646 struct i40e_mac_filter_info filter;
4649 if (vsi->type != I40E_VSI_MAIN)
4650 return I40E_ERR_CONFIG;
4651 memset(&def_filter, 0, sizeof(def_filter));
4652 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4654 def_filter.vlan_tag = 0;
4655 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4656 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4657 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4658 if (ret != I40E_SUCCESS) {
4659 struct i40e_mac_filter *f;
4660 struct ether_addr *mac;
4663 "Cannot remove the default macvlan filter");
4664 /* It needs to add the permanent mac into mac list */
4665 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4667 PMD_DRV_LOG(ERR, "failed to allocate memory");
4668 return I40E_ERR_NO_MEMORY;
4670 mac = &f->mac_info.mac_addr;
4671 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4673 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4674 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4679 rte_memcpy(&filter.mac_addr,
4680 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4681 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4682 return i40e_vsi_add_mac(vsi, &filter);
4686 * i40e_vsi_get_bw_config - Query VSI BW Information
4687 * @vsi: the VSI to be queried
4689 * Returns 0 on success, negative value on failure
4691 static enum i40e_status_code
4692 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4694 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4695 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4696 struct i40e_hw *hw = &vsi->adapter->hw;
4701 memset(&bw_config, 0, sizeof(bw_config));
4702 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4703 if (ret != I40E_SUCCESS) {
4704 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4705 hw->aq.asq_last_status);
4709 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4710 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4711 &ets_sla_config, NULL);
4712 if (ret != I40E_SUCCESS) {
4714 "VSI failed to get TC bandwdith configuration %u",
4715 hw->aq.asq_last_status);
4719 /* store and print out BW info */
4720 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4721 vsi->bw_info.bw_max = bw_config.max_bw;
4722 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4723 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4724 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4725 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4727 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4728 vsi->bw_info.bw_ets_share_credits[i] =
4729 ets_sla_config.share_credits[i];
4730 vsi->bw_info.bw_ets_credits[i] =
4731 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4732 /* 4 bits per TC, 4th bit is reserved */
4733 vsi->bw_info.bw_ets_max[i] =
4734 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4735 RTE_LEN2MASK(3, uint8_t));
4736 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4737 vsi->bw_info.bw_ets_share_credits[i]);
4738 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4739 vsi->bw_info.bw_ets_credits[i]);
4740 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4741 vsi->bw_info.bw_ets_max[i]);
4744 return I40E_SUCCESS;
4747 /* i40e_enable_pf_lb
4748 * @pf: pointer to the pf structure
4750 * allow loopback on pf
4753 i40e_enable_pf_lb(struct i40e_pf *pf)
4755 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4756 struct i40e_vsi_context ctxt;
4759 /* Use the FW API if FW >= v5.0 */
4760 if (hw->aq.fw_maj_ver < 5) {
4761 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4765 memset(&ctxt, 0, sizeof(ctxt));
4766 ctxt.seid = pf->main_vsi_seid;
4767 ctxt.pf_num = hw->pf_id;
4768 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4770 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4771 ret, hw->aq.asq_last_status);
4774 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4775 ctxt.info.valid_sections =
4776 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4777 ctxt.info.switch_id |=
4778 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4780 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4782 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4783 hw->aq.asq_last_status);
4788 i40e_vsi_setup(struct i40e_pf *pf,
4789 enum i40e_vsi_type type,
4790 struct i40e_vsi *uplink_vsi,
4791 uint16_t user_param)
4793 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4794 struct i40e_vsi *vsi;
4795 struct i40e_mac_filter_info filter;
4797 struct i40e_vsi_context ctxt;
4798 struct ether_addr broadcast =
4799 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4801 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4802 uplink_vsi == NULL) {
4804 "VSI setup failed, VSI link shouldn't be NULL");
4808 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4810 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4815 * 1.type is not MAIN and uplink vsi is not NULL
4816 * If uplink vsi didn't setup VEB, create one first under veb field
4817 * 2.type is SRIOV and the uplink is NULL
4818 * If floating VEB is NULL, create one veb under floating veb field
4821 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4822 uplink_vsi->veb == NULL) {
4823 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4825 if (uplink_vsi->veb == NULL) {
4826 PMD_DRV_LOG(ERR, "VEB setup failed");
4829 /* set ALLOWLOOPBACk on pf, when veb is created */
4830 i40e_enable_pf_lb(pf);
4833 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4834 pf->main_vsi->floating_veb == NULL) {
4835 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4837 if (pf->main_vsi->floating_veb == NULL) {
4838 PMD_DRV_LOG(ERR, "VEB setup failed");
4843 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4845 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4848 TAILQ_INIT(&vsi->mac_list);
4850 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4851 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4852 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4853 vsi->user_param = user_param;
4854 vsi->vlan_anti_spoof_on = 0;
4855 vsi->vlan_filter_on = 0;
4856 /* Allocate queues */
4857 switch (vsi->type) {
4858 case I40E_VSI_MAIN :
4859 vsi->nb_qps = pf->lan_nb_qps;
4861 case I40E_VSI_SRIOV :
4862 vsi->nb_qps = pf->vf_nb_qps;
4864 case I40E_VSI_VMDQ2:
4865 vsi->nb_qps = pf->vmdq_nb_qps;
4868 vsi->nb_qps = pf->fdir_nb_qps;
4874 * The filter status descriptor is reported in rx queue 0,
4875 * while the tx queue for fdir filter programming has no
4876 * such constraints, can be non-zero queues.
4877 * To simplify it, choose FDIR vsi use queue 0 pair.
4878 * To make sure it will use queue 0 pair, queue allocation
4879 * need be done before this function is called
4881 if (type != I40E_VSI_FDIR) {
4882 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4884 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4888 vsi->base_queue = ret;
4890 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4892 /* VF has MSIX interrupt in VF range, don't allocate here */
4893 if (type == I40E_VSI_MAIN) {
4894 ret = i40e_res_pool_alloc(&pf->msix_pool,
4895 RTE_MIN(vsi->nb_qps,
4896 RTE_MAX_RXTX_INTR_VEC_ID));
4898 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4900 goto fail_queue_alloc;
4902 vsi->msix_intr = ret;
4903 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4904 } else if (type != I40E_VSI_SRIOV) {
4905 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4907 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4908 goto fail_queue_alloc;
4910 vsi->msix_intr = ret;
4918 if (type == I40E_VSI_MAIN) {
4919 /* For main VSI, no need to add since it's default one */
4920 vsi->uplink_seid = pf->mac_seid;
4921 vsi->seid = pf->main_vsi_seid;
4922 /* Bind queues with specific MSIX interrupt */
4924 * Needs 2 interrupt at least, one for misc cause which will
4925 * enabled from OS side, Another for queues binding the
4926 * interrupt from device side only.
4929 /* Get default VSI parameters from hardware */
4930 memset(&ctxt, 0, sizeof(ctxt));
4931 ctxt.seid = vsi->seid;
4932 ctxt.pf_num = hw->pf_id;
4933 ctxt.uplink_seid = vsi->uplink_seid;
4935 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4936 if (ret != I40E_SUCCESS) {
4937 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4938 goto fail_msix_alloc;
4940 rte_memcpy(&vsi->info, &ctxt.info,
4941 sizeof(struct i40e_aqc_vsi_properties_data));
4942 vsi->vsi_id = ctxt.vsi_number;
4943 vsi->info.valid_sections = 0;
4945 /* Configure tc, enabled TC0 only */
4946 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4948 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4949 goto fail_msix_alloc;
4952 /* TC, queue mapping */
4953 memset(&ctxt, 0, sizeof(ctxt));
4954 vsi->info.valid_sections |=
4955 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4956 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4957 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4958 rte_memcpy(&ctxt.info, &vsi->info,
4959 sizeof(struct i40e_aqc_vsi_properties_data));
4960 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4961 I40E_DEFAULT_TCMAP);
4962 if (ret != I40E_SUCCESS) {
4964 "Failed to configure TC queue mapping");
4965 goto fail_msix_alloc;
4967 ctxt.seid = vsi->seid;
4968 ctxt.pf_num = hw->pf_id;
4969 ctxt.uplink_seid = vsi->uplink_seid;
4972 /* Update VSI parameters */
4973 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4974 if (ret != I40E_SUCCESS) {
4975 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4976 goto fail_msix_alloc;
4979 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4980 sizeof(vsi->info.tc_mapping));
4981 rte_memcpy(&vsi->info.queue_mapping,
4982 &ctxt.info.queue_mapping,
4983 sizeof(vsi->info.queue_mapping));
4984 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4985 vsi->info.valid_sections = 0;
4987 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4991 * Updating default filter settings are necessary to prevent
4992 * reception of tagged packets.
4993 * Some old firmware configurations load a default macvlan
4994 * filter which accepts both tagged and untagged packets.
4995 * The updating is to use a normal filter instead if needed.
4996 * For NVM 4.2.2 or after, the updating is not needed anymore.
4997 * The firmware with correct configurations load the default
4998 * macvlan filter which is expected and cannot be removed.
5000 i40e_update_default_filter_setting(vsi);
5001 i40e_config_qinq(hw, vsi);
5002 } else if (type == I40E_VSI_SRIOV) {
5003 memset(&ctxt, 0, sizeof(ctxt));
5005 * For other VSI, the uplink_seid equals to uplink VSI's
5006 * uplink_seid since they share same VEB
5008 if (uplink_vsi == NULL)
5009 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5011 vsi->uplink_seid = uplink_vsi->uplink_seid;
5012 ctxt.pf_num = hw->pf_id;
5013 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5014 ctxt.uplink_seid = vsi->uplink_seid;
5015 ctxt.connection_type = 0x1;
5016 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5018 /* Use the VEB configuration if FW >= v5.0 */
5019 if (hw->aq.fw_maj_ver >= 5) {
5020 /* Configure switch ID */
5021 ctxt.info.valid_sections |=
5022 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5023 ctxt.info.switch_id =
5024 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5027 /* Configure port/vlan */
5028 ctxt.info.valid_sections |=
5029 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5030 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5031 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5032 hw->func_caps.enabled_tcmap);
5033 if (ret != I40E_SUCCESS) {
5035 "Failed to configure TC queue mapping");
5036 goto fail_msix_alloc;
5039 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5040 ctxt.info.valid_sections |=
5041 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5043 * Since VSI is not created yet, only configure parameter,
5044 * will add vsi below.
5047 i40e_config_qinq(hw, vsi);
5048 } else if (type == I40E_VSI_VMDQ2) {
5049 memset(&ctxt, 0, sizeof(ctxt));
5051 * For other VSI, the uplink_seid equals to uplink VSI's
5052 * uplink_seid since they share same VEB
5054 vsi->uplink_seid = uplink_vsi->uplink_seid;
5055 ctxt.pf_num = hw->pf_id;
5057 ctxt.uplink_seid = vsi->uplink_seid;
5058 ctxt.connection_type = 0x1;
5059 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5061 ctxt.info.valid_sections |=
5062 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5063 /* user_param carries flag to enable loop back */
5065 ctxt.info.switch_id =
5066 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5067 ctxt.info.switch_id |=
5068 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5071 /* Configure port/vlan */
5072 ctxt.info.valid_sections |=
5073 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5074 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5075 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5076 I40E_DEFAULT_TCMAP);
5077 if (ret != I40E_SUCCESS) {
5079 "Failed to configure TC queue mapping");
5080 goto fail_msix_alloc;
5082 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5083 ctxt.info.valid_sections |=
5084 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5085 } else if (type == I40E_VSI_FDIR) {
5086 memset(&ctxt, 0, sizeof(ctxt));
5087 vsi->uplink_seid = uplink_vsi->uplink_seid;
5088 ctxt.pf_num = hw->pf_id;
5090 ctxt.uplink_seid = vsi->uplink_seid;
5091 ctxt.connection_type = 0x1; /* regular data port */
5092 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5093 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5094 I40E_DEFAULT_TCMAP);
5095 if (ret != I40E_SUCCESS) {
5097 "Failed to configure TC queue mapping.");
5098 goto fail_msix_alloc;
5100 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5101 ctxt.info.valid_sections |=
5102 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5104 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5105 goto fail_msix_alloc;
5108 if (vsi->type != I40E_VSI_MAIN) {
5109 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5110 if (ret != I40E_SUCCESS) {
5111 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5112 hw->aq.asq_last_status);
5113 goto fail_msix_alloc;
5115 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5116 vsi->info.valid_sections = 0;
5117 vsi->seid = ctxt.seid;
5118 vsi->vsi_id = ctxt.vsi_number;
5119 vsi->sib_vsi_list.vsi = vsi;
5120 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5121 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5122 &vsi->sib_vsi_list, list);
5124 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5125 &vsi->sib_vsi_list, list);
5129 /* MAC/VLAN configuration */
5130 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5131 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5133 ret = i40e_vsi_add_mac(vsi, &filter);
5134 if (ret != I40E_SUCCESS) {
5135 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5136 goto fail_msix_alloc;
5139 /* Get VSI BW information */
5140 i40e_vsi_get_bw_config(vsi);
5143 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5145 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5151 /* Configure vlan filter on or off */
5153 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5156 struct i40e_mac_filter *f;
5158 struct i40e_mac_filter_info *mac_filter;
5159 enum rte_mac_filter_type desired_filter;
5160 int ret = I40E_SUCCESS;
5163 /* Filter to match MAC and VLAN */
5164 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5166 /* Filter to match only MAC */
5167 desired_filter = RTE_MAC_PERFECT_MATCH;
5172 mac_filter = rte_zmalloc("mac_filter_info_data",
5173 num * sizeof(*mac_filter), 0);
5174 if (mac_filter == NULL) {
5175 PMD_DRV_LOG(ERR, "failed to allocate memory");
5176 return I40E_ERR_NO_MEMORY;
5181 /* Remove all existing mac */
5182 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5183 mac_filter[i] = f->mac_info;
5184 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5186 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5187 on ? "enable" : "disable");
5193 /* Override with new filter */
5194 for (i = 0; i < num; i++) {
5195 mac_filter[i].filter_type = desired_filter;
5196 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5198 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5199 on ? "enable" : "disable");
5205 rte_free(mac_filter);
5209 /* Configure vlan stripping on or off */
5211 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5213 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5214 struct i40e_vsi_context ctxt;
5216 int ret = I40E_SUCCESS;
5218 /* Check if it has been already on or off */
5219 if (vsi->info.valid_sections &
5220 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5222 if ((vsi->info.port_vlan_flags &
5223 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5224 return 0; /* already on */
5226 if ((vsi->info.port_vlan_flags &
5227 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5228 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5229 return 0; /* already off */
5234 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5236 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5237 vsi->info.valid_sections =
5238 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5239 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5240 vsi->info.port_vlan_flags |= vlan_flags;
5241 ctxt.seid = vsi->seid;
5242 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5243 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5245 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5246 on ? "enable" : "disable");
5252 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5254 struct rte_eth_dev_data *data = dev->data;
5258 /* Apply vlan offload setting */
5259 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5260 i40e_vlan_offload_set(dev, mask);
5262 /* Apply double-vlan setting, not implemented yet */
5264 /* Apply pvid setting */
5265 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5266 data->dev_conf.txmode.hw_vlan_insert_pvid);
5268 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5274 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5276 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5278 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5282 i40e_update_flow_control(struct i40e_hw *hw)
5284 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5285 struct i40e_link_status link_status;
5286 uint32_t rxfc = 0, txfc = 0, reg;
5290 memset(&link_status, 0, sizeof(link_status));
5291 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5292 if (ret != I40E_SUCCESS) {
5293 PMD_DRV_LOG(ERR, "Failed to get link status information");
5294 goto write_reg; /* Disable flow control */
5297 an_info = hw->phy.link_info.an_info;
5298 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5299 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5300 ret = I40E_ERR_NOT_READY;
5301 goto write_reg; /* Disable flow control */
5304 * If link auto negotiation is enabled, flow control needs to
5305 * be configured according to it
5307 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5308 case I40E_LINK_PAUSE_RXTX:
5311 hw->fc.current_mode = I40E_FC_FULL;
5313 case I40E_AQ_LINK_PAUSE_RX:
5315 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5317 case I40E_AQ_LINK_PAUSE_TX:
5319 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5322 hw->fc.current_mode = I40E_FC_NONE;
5327 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5328 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5329 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5330 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5331 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5332 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5339 i40e_pf_setup(struct i40e_pf *pf)
5341 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5342 struct i40e_filter_control_settings settings;
5343 struct i40e_vsi *vsi;
5346 /* Clear all stats counters */
5347 pf->offset_loaded = FALSE;
5348 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5349 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5350 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5351 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5353 ret = i40e_pf_get_switch_config(pf);
5354 if (ret != I40E_SUCCESS) {
5355 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5358 if (pf->flags & I40E_FLAG_FDIR) {
5359 /* make queue allocated first, let FDIR use queue pair 0*/
5360 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5361 if (ret != I40E_FDIR_QUEUE_ID) {
5363 "queue allocation fails for FDIR: ret =%d",
5365 pf->flags &= ~I40E_FLAG_FDIR;
5368 /* main VSI setup */
5369 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5371 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5372 return I40E_ERR_NOT_READY;
5376 /* Configure filter control */
5377 memset(&settings, 0, sizeof(settings));
5378 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5379 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5380 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5381 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5383 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5384 hw->func_caps.rss_table_size);
5385 return I40E_ERR_PARAM;
5387 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5388 hw->func_caps.rss_table_size);
5389 pf->hash_lut_size = hw->func_caps.rss_table_size;
5391 /* Enable ethtype and macvlan filters */
5392 settings.enable_ethtype = TRUE;
5393 settings.enable_macvlan = TRUE;
5394 ret = i40e_set_filter_control(hw, &settings);
5396 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5399 /* Update flow control according to the auto negotiation */
5400 i40e_update_flow_control(hw);
5402 return I40E_SUCCESS;
5406 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5412 * Set or clear TX Queue Disable flags,
5413 * which is required by hardware.
5415 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5416 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5418 /* Wait until the request is finished */
5419 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5420 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5421 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5422 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5423 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5429 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5430 return I40E_SUCCESS; /* already on, skip next steps */
5432 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5433 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5435 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5436 return I40E_SUCCESS; /* already off, skip next steps */
5437 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5439 /* Write the register */
5440 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5441 /* Check the result */
5442 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5443 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5444 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5446 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5447 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5450 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5451 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5455 /* Check if it is timeout */
5456 if (j >= I40E_CHK_Q_ENA_COUNT) {
5457 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5458 (on ? "enable" : "disable"), q_idx);
5459 return I40E_ERR_TIMEOUT;
5462 return I40E_SUCCESS;
5465 /* Swith on or off the tx queues */
5467 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5469 struct rte_eth_dev_data *dev_data = pf->dev_data;
5470 struct i40e_tx_queue *txq;
5471 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5475 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5476 txq = dev_data->tx_queues[i];
5477 /* Don't operate the queue if not configured or
5478 * if starting only per queue */
5479 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5482 ret = i40e_dev_tx_queue_start(dev, i);
5484 ret = i40e_dev_tx_queue_stop(dev, i);
5485 if ( ret != I40E_SUCCESS)
5489 return I40E_SUCCESS;
5493 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5498 /* Wait until the request is finished */
5499 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5500 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5501 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5502 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5503 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5508 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5509 return I40E_SUCCESS; /* Already on, skip next steps */
5510 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5512 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5513 return I40E_SUCCESS; /* Already off, skip next steps */
5514 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5517 /* Write the register */
5518 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5519 /* Check the result */
5520 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5521 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5522 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5524 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5525 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5528 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5529 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5534 /* Check if it is timeout */
5535 if (j >= I40E_CHK_Q_ENA_COUNT) {
5536 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5537 (on ? "enable" : "disable"), q_idx);
5538 return I40E_ERR_TIMEOUT;
5541 return I40E_SUCCESS;
5543 /* Switch on or off the rx queues */
5545 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5547 struct rte_eth_dev_data *dev_data = pf->dev_data;
5548 struct i40e_rx_queue *rxq;
5549 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5553 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5554 rxq = dev_data->rx_queues[i];
5555 /* Don't operate the queue if not configured or
5556 * if starting only per queue */
5557 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5560 ret = i40e_dev_rx_queue_start(dev, i);
5562 ret = i40e_dev_rx_queue_stop(dev, i);
5563 if (ret != I40E_SUCCESS)
5567 return I40E_SUCCESS;
5570 /* Switch on or off all the rx/tx queues */
5572 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5577 /* enable rx queues before enabling tx queues */
5578 ret = i40e_dev_switch_rx_queues(pf, on);
5580 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5583 ret = i40e_dev_switch_tx_queues(pf, on);
5585 /* Stop tx queues before stopping rx queues */
5586 ret = i40e_dev_switch_tx_queues(pf, on);
5588 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5591 ret = i40e_dev_switch_rx_queues(pf, on);
5597 /* Initialize VSI for TX */
5599 i40e_dev_tx_init(struct i40e_pf *pf)
5601 struct rte_eth_dev_data *data = pf->dev_data;
5603 uint32_t ret = I40E_SUCCESS;
5604 struct i40e_tx_queue *txq;
5606 for (i = 0; i < data->nb_tx_queues; i++) {
5607 txq = data->tx_queues[i];
5608 if (!txq || !txq->q_set)
5610 ret = i40e_tx_queue_init(txq);
5611 if (ret != I40E_SUCCESS)
5614 if (ret == I40E_SUCCESS)
5615 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5621 /* Initialize VSI for RX */
5623 i40e_dev_rx_init(struct i40e_pf *pf)
5625 struct rte_eth_dev_data *data = pf->dev_data;
5626 int ret = I40E_SUCCESS;
5628 struct i40e_rx_queue *rxq;
5630 i40e_pf_config_mq_rx(pf);
5631 for (i = 0; i < data->nb_rx_queues; i++) {
5632 rxq = data->rx_queues[i];
5633 if (!rxq || !rxq->q_set)
5636 ret = i40e_rx_queue_init(rxq);
5637 if (ret != I40E_SUCCESS) {
5639 "Failed to do RX queue initialization");
5643 if (ret == I40E_SUCCESS)
5644 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5651 i40e_dev_rxtx_init(struct i40e_pf *pf)
5655 err = i40e_dev_tx_init(pf);
5657 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5660 err = i40e_dev_rx_init(pf);
5662 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5670 i40e_vmdq_setup(struct rte_eth_dev *dev)
5672 struct rte_eth_conf *conf = &dev->data->dev_conf;
5673 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5674 int i, err, conf_vsis, j, loop;
5675 struct i40e_vsi *vsi;
5676 struct i40e_vmdq_info *vmdq_info;
5677 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5678 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5681 * Disable interrupt to avoid message from VF. Furthermore, it will
5682 * avoid race condition in VSI creation/destroy.
5684 i40e_pf_disable_irq0(hw);
5686 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5687 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5691 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5692 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5693 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5694 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5695 pf->max_nb_vmdq_vsi);
5699 if (pf->vmdq != NULL) {
5700 PMD_INIT_LOG(INFO, "VMDQ already configured");
5704 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5705 sizeof(*vmdq_info) * conf_vsis, 0);
5707 if (pf->vmdq == NULL) {
5708 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5712 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5714 /* Create VMDQ VSI */
5715 for (i = 0; i < conf_vsis; i++) {
5716 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5717 vmdq_conf->enable_loop_back);
5719 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5723 vmdq_info = &pf->vmdq[i];
5725 vmdq_info->vsi = vsi;
5727 pf->nb_cfg_vmdq_vsi = conf_vsis;
5729 /* Configure Vlan */
5730 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5731 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5732 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5733 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5734 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5735 vmdq_conf->pool_map[i].vlan_id, j);
5737 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5738 vmdq_conf->pool_map[i].vlan_id);
5740 PMD_INIT_LOG(ERR, "Failed to add vlan");
5748 i40e_pf_enable_irq0(hw);
5753 for (i = 0; i < conf_vsis; i++)
5754 if (pf->vmdq[i].vsi == NULL)
5757 i40e_vsi_release(pf->vmdq[i].vsi);
5761 i40e_pf_enable_irq0(hw);
5766 i40e_stat_update_32(struct i40e_hw *hw,
5774 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5778 if (new_data >= *offset)
5779 *stat = (uint64_t)(new_data - *offset);
5781 *stat = (uint64_t)((new_data +
5782 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5786 i40e_stat_update_48(struct i40e_hw *hw,
5795 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5796 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5797 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5802 if (new_data >= *offset)
5803 *stat = new_data - *offset;
5805 *stat = (uint64_t)((new_data +
5806 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5808 *stat &= I40E_48_BIT_MASK;
5813 i40e_pf_disable_irq0(struct i40e_hw *hw)
5815 /* Disable all interrupt types */
5816 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5817 I40E_WRITE_FLUSH(hw);
5822 i40e_pf_enable_irq0(struct i40e_hw *hw)
5824 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5825 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5826 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5827 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5828 I40E_WRITE_FLUSH(hw);
5832 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5834 /* read pending request and disable first */
5835 i40e_pf_disable_irq0(hw);
5836 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5837 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5838 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5841 /* Link no queues with irq0 */
5842 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5843 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5847 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5849 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5850 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5853 uint32_t index, offset, val;
5858 * Try to find which VF trigger a reset, use absolute VF id to access
5859 * since the reg is global register.
5861 for (i = 0; i < pf->vf_num; i++) {
5862 abs_vf_id = hw->func_caps.vf_base_id + i;
5863 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5864 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5865 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5866 /* VFR event occurred */
5867 if (val & (0x1 << offset)) {
5870 /* Clear the event first */
5871 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5873 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5875 * Only notify a VF reset event occurred,
5876 * don't trigger another SW reset
5878 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5879 if (ret != I40E_SUCCESS)
5880 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5886 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5888 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5891 for (i = 0; i < pf->vf_num; i++)
5892 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5896 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5898 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5899 struct i40e_arq_event_info info;
5900 uint16_t pending, opcode;
5903 info.buf_len = I40E_AQ_BUF_SZ;
5904 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5905 if (!info.msg_buf) {
5906 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5912 ret = i40e_clean_arq_element(hw, &info, &pending);
5914 if (ret != I40E_SUCCESS) {
5916 "Failed to read msg from AdminQ, aq_err: %u",
5917 hw->aq.asq_last_status);
5920 opcode = rte_le_to_cpu_16(info.desc.opcode);
5923 case i40e_aqc_opc_send_msg_to_pf:
5924 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5925 i40e_pf_host_handle_vf_msg(dev,
5926 rte_le_to_cpu_16(info.desc.retval),
5927 rte_le_to_cpu_32(info.desc.cookie_high),
5928 rte_le_to_cpu_32(info.desc.cookie_low),
5932 case i40e_aqc_opc_get_link_status:
5933 ret = i40e_dev_link_update(dev, 0);
5935 _rte_eth_dev_callback_process(dev,
5936 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5939 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5944 rte_free(info.msg_buf);
5948 * Interrupt handler triggered by NIC for handling
5949 * specific interrupt.
5952 * Pointer to interrupt handle.
5954 * The address of parameter (struct rte_eth_dev *) regsitered before.
5960 i40e_dev_interrupt_handler(void *param)
5962 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5963 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5966 /* Disable interrupt */
5967 i40e_pf_disable_irq0(hw);
5969 /* read out interrupt causes */
5970 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5972 /* No interrupt event indicated */
5973 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5974 PMD_DRV_LOG(INFO, "No interrupt event");
5977 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5978 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5979 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5980 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5981 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5982 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5983 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5984 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5985 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5986 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5987 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5988 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5989 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5990 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5992 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5993 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5994 i40e_dev_handle_vfr_event(dev);
5996 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5997 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5998 i40e_dev_handle_aq_msg(dev);
6002 /* Enable interrupt */
6003 i40e_pf_enable_irq0(hw);
6004 rte_intr_enable(dev->intr_handle);
6008 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6009 struct i40e_macvlan_filter *filter,
6012 int ele_num, ele_buff_size;
6013 int num, actual_num, i;
6015 int ret = I40E_SUCCESS;
6016 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6017 struct i40e_aqc_add_macvlan_element_data *req_list;
6019 if (filter == NULL || total == 0)
6020 return I40E_ERR_PARAM;
6021 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6022 ele_buff_size = hw->aq.asq_buf_size;
6024 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6025 if (req_list == NULL) {
6026 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6027 return I40E_ERR_NO_MEMORY;
6032 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6033 memset(req_list, 0, ele_buff_size);
6035 for (i = 0; i < actual_num; i++) {
6036 rte_memcpy(req_list[i].mac_addr,
6037 &filter[num + i].macaddr, ETH_ADDR_LEN);
6038 req_list[i].vlan_tag =
6039 rte_cpu_to_le_16(filter[num + i].vlan_id);
6041 switch (filter[num + i].filter_type) {
6042 case RTE_MAC_PERFECT_MATCH:
6043 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6044 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6046 case RTE_MACVLAN_PERFECT_MATCH:
6047 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6049 case RTE_MAC_HASH_MATCH:
6050 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6051 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6053 case RTE_MACVLAN_HASH_MATCH:
6054 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6057 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6058 ret = I40E_ERR_PARAM;
6062 req_list[i].queue_number = 0;
6064 req_list[i].flags = rte_cpu_to_le_16(flags);
6067 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6069 if (ret != I40E_SUCCESS) {
6070 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6074 } while (num < total);
6082 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6083 struct i40e_macvlan_filter *filter,
6086 int ele_num, ele_buff_size;
6087 int num, actual_num, i;
6089 int ret = I40E_SUCCESS;
6090 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6091 struct i40e_aqc_remove_macvlan_element_data *req_list;
6093 if (filter == NULL || total == 0)
6094 return I40E_ERR_PARAM;
6096 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6097 ele_buff_size = hw->aq.asq_buf_size;
6099 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6100 if (req_list == NULL) {
6101 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6102 return I40E_ERR_NO_MEMORY;
6107 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6108 memset(req_list, 0, ele_buff_size);
6110 for (i = 0; i < actual_num; i++) {
6111 rte_memcpy(req_list[i].mac_addr,
6112 &filter[num + i].macaddr, ETH_ADDR_LEN);
6113 req_list[i].vlan_tag =
6114 rte_cpu_to_le_16(filter[num + i].vlan_id);
6116 switch (filter[num + i].filter_type) {
6117 case RTE_MAC_PERFECT_MATCH:
6118 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6119 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6121 case RTE_MACVLAN_PERFECT_MATCH:
6122 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6124 case RTE_MAC_HASH_MATCH:
6125 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6126 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6128 case RTE_MACVLAN_HASH_MATCH:
6129 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6132 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6133 ret = I40E_ERR_PARAM;
6136 req_list[i].flags = rte_cpu_to_le_16(flags);
6139 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6141 if (ret != I40E_SUCCESS) {
6142 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6146 } while (num < total);
6153 /* Find out specific MAC filter */
6154 static struct i40e_mac_filter *
6155 i40e_find_mac_filter(struct i40e_vsi *vsi,
6156 struct ether_addr *macaddr)
6158 struct i40e_mac_filter *f;
6160 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6161 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6169 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6172 uint32_t vid_idx, vid_bit;
6174 if (vlan_id > ETH_VLAN_ID_MAX)
6177 vid_idx = I40E_VFTA_IDX(vlan_id);
6178 vid_bit = I40E_VFTA_BIT(vlan_id);
6180 if (vsi->vfta[vid_idx] & vid_bit)
6187 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6188 uint16_t vlan_id, bool on)
6190 uint32_t vid_idx, vid_bit;
6192 vid_idx = I40E_VFTA_IDX(vlan_id);
6193 vid_bit = I40E_VFTA_BIT(vlan_id);
6196 vsi->vfta[vid_idx] |= vid_bit;
6198 vsi->vfta[vid_idx] &= ~vid_bit;
6202 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6203 uint16_t vlan_id, bool on)
6205 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6206 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6209 if (vlan_id > ETH_VLAN_ID_MAX)
6212 i40e_store_vlan_filter(vsi, vlan_id, on);
6214 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6217 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6220 ret = i40e_aq_add_vlan(hw, vsi->seid,
6221 &vlan_data, 1, NULL);
6222 if (ret != I40E_SUCCESS)
6223 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6225 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6226 &vlan_data, 1, NULL);
6227 if (ret != I40E_SUCCESS)
6229 "Failed to remove vlan filter");
6234 * Find all vlan options for specific mac addr,
6235 * return with actual vlan found.
6238 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6239 struct i40e_macvlan_filter *mv_f,
6240 int num, struct ether_addr *addr)
6246 * Not to use i40e_find_vlan_filter to decrease the loop time,
6247 * although the code looks complex.
6249 if (num < vsi->vlan_num)
6250 return I40E_ERR_PARAM;
6253 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6255 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6256 if (vsi->vfta[j] & (1 << k)) {
6259 "vlan number doesn't match");
6260 return I40E_ERR_PARAM;
6262 rte_memcpy(&mv_f[i].macaddr,
6263 addr, ETH_ADDR_LEN);
6265 j * I40E_UINT32_BIT_SIZE + k;
6271 return I40E_SUCCESS;
6275 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6276 struct i40e_macvlan_filter *mv_f,
6281 struct i40e_mac_filter *f;
6283 if (num < vsi->mac_num)
6284 return I40E_ERR_PARAM;
6286 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6288 PMD_DRV_LOG(ERR, "buffer number not match");
6289 return I40E_ERR_PARAM;
6291 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6293 mv_f[i].vlan_id = vlan;
6294 mv_f[i].filter_type = f->mac_info.filter_type;
6298 return I40E_SUCCESS;
6302 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6305 struct i40e_mac_filter *f;
6306 struct i40e_macvlan_filter *mv_f;
6307 int ret = I40E_SUCCESS;
6309 if (vsi == NULL || vsi->mac_num == 0)
6310 return I40E_ERR_PARAM;
6312 /* Case that no vlan is set */
6313 if (vsi->vlan_num == 0)
6316 num = vsi->mac_num * vsi->vlan_num;
6318 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6320 PMD_DRV_LOG(ERR, "failed to allocate memory");
6321 return I40E_ERR_NO_MEMORY;
6325 if (vsi->vlan_num == 0) {
6326 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6327 rte_memcpy(&mv_f[i].macaddr,
6328 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6329 mv_f[i].filter_type = f->mac_info.filter_type;
6330 mv_f[i].vlan_id = 0;
6334 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6335 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6336 vsi->vlan_num, &f->mac_info.mac_addr);
6337 if (ret != I40E_SUCCESS)
6339 for (j = i; j < i + vsi->vlan_num; j++)
6340 mv_f[j].filter_type = f->mac_info.filter_type;
6345 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6353 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6355 struct i40e_macvlan_filter *mv_f;
6357 int ret = I40E_SUCCESS;
6359 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6360 return I40E_ERR_PARAM;
6362 /* If it's already set, just return */
6363 if (i40e_find_vlan_filter(vsi,vlan))
6364 return I40E_SUCCESS;
6366 mac_num = vsi->mac_num;
6369 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6370 return I40E_ERR_PARAM;
6373 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6376 PMD_DRV_LOG(ERR, "failed to allocate memory");
6377 return I40E_ERR_NO_MEMORY;
6380 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6382 if (ret != I40E_SUCCESS)
6385 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6387 if (ret != I40E_SUCCESS)
6390 i40e_set_vlan_filter(vsi, vlan, 1);
6400 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6402 struct i40e_macvlan_filter *mv_f;
6404 int ret = I40E_SUCCESS;
6407 * Vlan 0 is the generic filter for untagged packets
6408 * and can't be removed.
6410 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6411 return I40E_ERR_PARAM;
6413 /* If can't find it, just return */
6414 if (!i40e_find_vlan_filter(vsi, vlan))
6415 return I40E_ERR_PARAM;
6417 mac_num = vsi->mac_num;
6420 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6421 return I40E_ERR_PARAM;
6424 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6427 PMD_DRV_LOG(ERR, "failed to allocate memory");
6428 return I40E_ERR_NO_MEMORY;
6431 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6433 if (ret != I40E_SUCCESS)
6436 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6438 if (ret != I40E_SUCCESS)
6441 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6442 if (vsi->vlan_num == 1) {
6443 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6444 if (ret != I40E_SUCCESS)
6447 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6448 if (ret != I40E_SUCCESS)
6452 i40e_set_vlan_filter(vsi, vlan, 0);
6462 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6464 struct i40e_mac_filter *f;
6465 struct i40e_macvlan_filter *mv_f;
6466 int i, vlan_num = 0;
6467 int ret = I40E_SUCCESS;
6469 /* If it's add and we've config it, return */
6470 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6472 return I40E_SUCCESS;
6473 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6474 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6477 * If vlan_num is 0, that's the first time to add mac,
6478 * set mask for vlan_id 0.
6480 if (vsi->vlan_num == 0) {
6481 i40e_set_vlan_filter(vsi, 0, 1);
6484 vlan_num = vsi->vlan_num;
6485 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6486 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6489 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6491 PMD_DRV_LOG(ERR, "failed to allocate memory");
6492 return I40E_ERR_NO_MEMORY;
6495 for (i = 0; i < vlan_num; i++) {
6496 mv_f[i].filter_type = mac_filter->filter_type;
6497 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6501 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6502 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6503 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6504 &mac_filter->mac_addr);
6505 if (ret != I40E_SUCCESS)
6509 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6510 if (ret != I40E_SUCCESS)
6513 /* Add the mac addr into mac list */
6514 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6516 PMD_DRV_LOG(ERR, "failed to allocate memory");
6517 ret = I40E_ERR_NO_MEMORY;
6520 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6522 f->mac_info.filter_type = mac_filter->filter_type;
6523 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6534 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6536 struct i40e_mac_filter *f;
6537 struct i40e_macvlan_filter *mv_f;
6539 enum rte_mac_filter_type filter_type;
6540 int ret = I40E_SUCCESS;
6542 /* Can't find it, return an error */
6543 f = i40e_find_mac_filter(vsi, addr);
6545 return I40E_ERR_PARAM;
6547 vlan_num = vsi->vlan_num;
6548 filter_type = f->mac_info.filter_type;
6549 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6550 filter_type == RTE_MACVLAN_HASH_MATCH) {
6551 if (vlan_num == 0) {
6552 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6553 return I40E_ERR_PARAM;
6555 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6556 filter_type == RTE_MAC_HASH_MATCH)
6559 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6561 PMD_DRV_LOG(ERR, "failed to allocate memory");
6562 return I40E_ERR_NO_MEMORY;
6565 for (i = 0; i < vlan_num; i++) {
6566 mv_f[i].filter_type = filter_type;
6567 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6570 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6571 filter_type == RTE_MACVLAN_HASH_MATCH) {
6572 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6573 if (ret != I40E_SUCCESS)
6577 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6578 if (ret != I40E_SUCCESS)
6581 /* Remove the mac addr into mac list */
6582 TAILQ_REMOVE(&vsi->mac_list, f, next);
6592 /* Configure hash enable flags for RSS */
6594 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6601 if (flags & ETH_RSS_FRAG_IPV4)
6602 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6603 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6604 if (type == I40E_MAC_X722) {
6605 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6606 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6608 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6610 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6611 if (type == I40E_MAC_X722) {
6612 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6613 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6614 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6616 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6618 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6619 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6620 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6621 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6622 if (flags & ETH_RSS_FRAG_IPV6)
6623 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6624 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6625 if (type == I40E_MAC_X722) {
6626 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6627 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6629 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6631 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6632 if (type == I40E_MAC_X722) {
6633 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6634 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6635 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6637 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6639 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6640 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6641 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6642 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6643 if (flags & ETH_RSS_L2_PAYLOAD)
6644 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6649 /* Parse the hash enable flags */
6651 i40e_parse_hena(uint64_t flags)
6653 uint64_t rss_hf = 0;
6657 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6658 rss_hf |= ETH_RSS_FRAG_IPV4;
6659 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6660 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6661 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6662 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6663 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6664 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6665 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6666 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6667 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6668 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6669 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6670 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6671 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6672 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6673 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6674 rss_hf |= ETH_RSS_FRAG_IPV6;
6675 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6676 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6677 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6678 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6679 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6680 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6681 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6682 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6683 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6684 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6685 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6686 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6687 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6688 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6689 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6690 rss_hf |= ETH_RSS_L2_PAYLOAD;
6697 i40e_pf_disable_rss(struct i40e_pf *pf)
6699 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6702 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6703 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6704 if (hw->mac.type == I40E_MAC_X722)
6705 hena &= ~I40E_RSS_HENA_ALL_X722;
6707 hena &= ~I40E_RSS_HENA_ALL;
6708 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6709 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6710 I40E_WRITE_FLUSH(hw);
6714 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6716 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6717 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6720 if (!key || key_len == 0) {
6721 PMD_DRV_LOG(DEBUG, "No key to be configured");
6723 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6725 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6729 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6730 struct i40e_aqc_get_set_rss_key_data *key_dw =
6731 (struct i40e_aqc_get_set_rss_key_data *)key;
6733 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6735 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6737 uint32_t *hash_key = (uint32_t *)key;
6740 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6741 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6742 I40E_WRITE_FLUSH(hw);
6749 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6751 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6752 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6755 if (!key || !key_len)
6758 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6759 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6760 (struct i40e_aqc_get_set_rss_key_data *)key);
6762 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6766 uint32_t *key_dw = (uint32_t *)key;
6769 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6770 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6772 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6778 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6780 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6785 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6786 rss_conf->rss_key_len);
6790 rss_hf = rss_conf->rss_hf;
6791 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6792 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6793 if (hw->mac.type == I40E_MAC_X722)
6794 hena &= ~I40E_RSS_HENA_ALL_X722;
6796 hena &= ~I40E_RSS_HENA_ALL;
6797 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6798 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6799 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6800 I40E_WRITE_FLUSH(hw);
6806 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6807 struct rte_eth_rss_conf *rss_conf)
6809 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6810 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6811 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6814 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6815 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6816 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6817 ? I40E_RSS_HENA_ALL_X722
6818 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6819 if (rss_hf != 0) /* Enable RSS */
6821 return 0; /* Nothing to do */
6824 if (rss_hf == 0) /* Disable RSS */
6827 return i40e_hw_rss_hash_set(pf, rss_conf);
6831 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6832 struct rte_eth_rss_conf *rss_conf)
6834 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6835 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6838 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6839 &rss_conf->rss_key_len);
6841 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6842 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6843 rss_conf->rss_hf = i40e_parse_hena(hena);
6849 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6851 switch (filter_type) {
6852 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6853 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6855 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6856 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6858 case RTE_TUNNEL_FILTER_IMAC_TENID:
6859 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6861 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6862 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6864 case ETH_TUNNEL_FILTER_IMAC:
6865 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6867 case ETH_TUNNEL_FILTER_OIP:
6868 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6870 case ETH_TUNNEL_FILTER_IIP:
6871 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6874 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6881 /* Convert tunnel filter structure */
6883 i40e_tunnel_filter_convert(
6884 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6885 struct i40e_tunnel_filter *tunnel_filter)
6887 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6888 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6889 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6890 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6891 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6892 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6893 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6894 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6895 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6897 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6898 tunnel_filter->input.flags = cld_filter->element.flags;
6899 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6900 tunnel_filter->queue = cld_filter->element.queue_number;
6901 rte_memcpy(tunnel_filter->input.general_fields,
6902 cld_filter->general_fields,
6903 sizeof(cld_filter->general_fields));
6908 /* Check if there exists the tunnel filter */
6909 struct i40e_tunnel_filter *
6910 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6911 const struct i40e_tunnel_filter_input *input)
6915 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6919 return tunnel_rule->hash_map[ret];
6922 /* Add a tunnel filter into the SW list */
6924 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6925 struct i40e_tunnel_filter *tunnel_filter)
6927 struct i40e_tunnel_rule *rule = &pf->tunnel;
6930 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6933 "Failed to insert tunnel filter to hash table %d!",
6937 rule->hash_map[ret] = tunnel_filter;
6939 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6944 /* Delete a tunnel filter from the SW list */
6946 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6947 struct i40e_tunnel_filter_input *input)
6949 struct i40e_tunnel_rule *rule = &pf->tunnel;
6950 struct i40e_tunnel_filter *tunnel_filter;
6953 ret = rte_hash_del_key(rule->hash_table, input);
6956 "Failed to delete tunnel filter to hash table %d!",
6960 tunnel_filter = rule->hash_map[ret];
6961 rule->hash_map[ret] = NULL;
6963 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6964 rte_free(tunnel_filter);
6970 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6971 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6976 uint8_t i, tun_type = 0;
6977 /* internal varialbe to convert ipv6 byte order */
6978 uint32_t convert_ipv6[4];
6980 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6981 struct i40e_vsi *vsi = pf->main_vsi;
6982 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6983 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6984 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6985 struct i40e_tunnel_filter *tunnel, *node;
6986 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6988 cld_filter = rte_zmalloc("tunnel_filter",
6989 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6992 if (NULL == cld_filter) {
6993 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6996 pfilter = cld_filter;
6998 ether_addr_copy(&tunnel_filter->outer_mac,
6999 (struct ether_addr *)&pfilter->element.outer_mac);
7000 ether_addr_copy(&tunnel_filter->inner_mac,
7001 (struct ether_addr *)&pfilter->element.inner_mac);
7003 pfilter->element.inner_vlan =
7004 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7005 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7006 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7007 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7008 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7009 &rte_cpu_to_le_32(ipv4_addr),
7010 sizeof(pfilter->element.ipaddr.v4.data));
7012 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7013 for (i = 0; i < 4; i++) {
7015 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7017 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7019 sizeof(pfilter->element.ipaddr.v6.data));
7022 /* check tunneled type */
7023 switch (tunnel_filter->tunnel_type) {
7024 case RTE_TUNNEL_TYPE_VXLAN:
7025 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7027 case RTE_TUNNEL_TYPE_NVGRE:
7028 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7030 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7031 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7034 /* Other tunnel types is not supported. */
7035 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7036 rte_free(cld_filter);
7040 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7041 &pfilter->element.flags);
7043 rte_free(cld_filter);
7047 pfilter->element.flags |= rte_cpu_to_le_16(
7048 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7049 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7050 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7051 pfilter->element.queue_number =
7052 rte_cpu_to_le_16(tunnel_filter->queue_id);
7054 /* Check if there is the filter in SW list */
7055 memset(&check_filter, 0, sizeof(check_filter));
7056 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7057 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7059 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7063 if (!add && !node) {
7064 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7069 ret = i40e_aq_add_cloud_filters(hw,
7070 vsi->seid, &cld_filter->element, 1);
7072 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7075 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7076 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7077 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7079 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7080 &cld_filter->element, 1);
7082 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7085 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7088 rte_free(cld_filter);
7092 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7093 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7094 #define I40E_TR_GENEVE_KEY_MASK 0x8
7095 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7096 #define I40E_TR_GRE_KEY_MASK 0x400
7097 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7098 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7101 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7103 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7104 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7105 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7106 enum i40e_status_code status = I40E_SUCCESS;
7108 memset(&filter_replace, 0,
7109 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7110 memset(&filter_replace_buf, 0,
7111 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7113 /* create L1 filter */
7114 filter_replace.old_filter_type =
7115 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7116 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7117 filter_replace.tr_bit = 0;
7119 /* Prepare the buffer, 3 entries */
7120 filter_replace_buf.data[0] =
7121 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7122 filter_replace_buf.data[0] |=
7123 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7124 filter_replace_buf.data[2] = 0xFF;
7125 filter_replace_buf.data[3] = 0xFF;
7126 filter_replace_buf.data[4] =
7127 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7128 filter_replace_buf.data[4] |=
7129 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7130 filter_replace_buf.data[7] = 0xF0;
7131 filter_replace_buf.data[8]
7132 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7133 filter_replace_buf.data[8] |=
7134 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7135 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7136 I40E_TR_GENEVE_KEY_MASK |
7137 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7138 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7139 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7140 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7142 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7143 &filter_replace_buf);
7148 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7150 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7151 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7152 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7153 enum i40e_status_code status = I40E_SUCCESS;
7156 memset(&filter_replace, 0,
7157 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7158 memset(&filter_replace_buf, 0,
7159 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7160 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7161 I40E_AQC_MIRROR_CLOUD_FILTER;
7162 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7163 filter_replace.new_filter_type =
7164 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7165 /* Prepare the buffer, 2 entries */
7166 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7167 filter_replace_buf.data[0] |=
7168 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7169 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7170 filter_replace_buf.data[4] |=
7171 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7172 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7173 &filter_replace_buf);
7178 memset(&filter_replace, 0,
7179 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7180 memset(&filter_replace_buf, 0,
7181 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7183 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7184 I40E_AQC_MIRROR_CLOUD_FILTER;
7185 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7186 filter_replace.new_filter_type =
7187 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7188 /* Prepare the buffer, 2 entries */
7189 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7190 filter_replace_buf.data[0] |=
7191 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7192 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7193 filter_replace_buf.data[4] |=
7194 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7196 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7197 &filter_replace_buf);
7202 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7203 struct i40e_tunnel_filter_conf *tunnel_filter,
7208 uint8_t i, tun_type = 0;
7209 /* internal variable to convert ipv6 byte order */
7210 uint32_t convert_ipv6[4];
7212 struct i40e_pf_vf *vf = NULL;
7213 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7214 struct i40e_vsi *vsi;
7215 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7216 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7217 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7218 struct i40e_tunnel_filter *tunnel, *node;
7219 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7221 bool big_buffer = 0;
7223 cld_filter = rte_zmalloc("tunnel_filter",
7224 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7227 if (cld_filter == NULL) {
7228 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7231 pfilter = cld_filter;
7233 ether_addr_copy(&tunnel_filter->outer_mac,
7234 (struct ether_addr *)&pfilter->element.outer_mac);
7235 ether_addr_copy(&tunnel_filter->inner_mac,
7236 (struct ether_addr *)&pfilter->element.inner_mac);
7238 pfilter->element.inner_vlan =
7239 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7240 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7241 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7242 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7243 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7244 &rte_cpu_to_le_32(ipv4_addr),
7245 sizeof(pfilter->element.ipaddr.v4.data));
7247 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7248 for (i = 0; i < 4; i++) {
7250 rte_cpu_to_le_32(rte_be_to_cpu_32(
7251 tunnel_filter->ip_addr.ipv6_addr[i]));
7253 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7255 sizeof(pfilter->element.ipaddr.v6.data));
7258 /* check tunneled type */
7259 switch (tunnel_filter->tunnel_type) {
7260 case I40E_TUNNEL_TYPE_VXLAN:
7261 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7263 case I40E_TUNNEL_TYPE_NVGRE:
7264 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7266 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7267 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7269 case I40E_TUNNEL_TYPE_MPLSoUDP:
7270 if (!pf->mpls_replace_flag) {
7271 i40e_replace_mpls_l1_filter(pf);
7272 i40e_replace_mpls_cloud_filter(pf);
7273 pf->mpls_replace_flag = 1;
7275 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7276 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7278 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7279 (teid_le & 0xF) << 12;
7280 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7283 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7285 case I40E_TUNNEL_TYPE_MPLSoGRE:
7286 if (!pf->mpls_replace_flag) {
7287 i40e_replace_mpls_l1_filter(pf);
7288 i40e_replace_mpls_cloud_filter(pf);
7289 pf->mpls_replace_flag = 1;
7291 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7292 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7294 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7295 (teid_le & 0xF) << 12;
7296 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7299 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7301 case I40E_TUNNEL_TYPE_QINQ:
7302 if (!pf->qinq_replace_flag) {
7303 ret = i40e_cloud_filter_qinq_create(pf);
7306 "QinQ tunnel filter already created.");
7307 pf->qinq_replace_flag = 1;
7309 /* Add in the General fields the values of
7310 * the Outer and Inner VLAN
7311 * Big Buffer should be set, see changes in
7312 * i40e_aq_add_cloud_filters
7314 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7315 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7319 /* Other tunnel types is not supported. */
7320 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7321 rte_free(cld_filter);
7325 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7326 pfilter->element.flags =
7327 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7328 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7329 pfilter->element.flags =
7330 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7331 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7332 pfilter->element.flags |=
7333 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7335 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7336 &pfilter->element.flags);
7338 rte_free(cld_filter);
7343 pfilter->element.flags |= rte_cpu_to_le_16(
7344 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7345 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7346 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7347 pfilter->element.queue_number =
7348 rte_cpu_to_le_16(tunnel_filter->queue_id);
7350 if (!tunnel_filter->is_to_vf)
7353 if (tunnel_filter->vf_id >= pf->vf_num) {
7354 PMD_DRV_LOG(ERR, "Invalid argument.");
7357 vf = &pf->vfs[tunnel_filter->vf_id];
7361 /* Check if there is the filter in SW list */
7362 memset(&check_filter, 0, sizeof(check_filter));
7363 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7364 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7365 check_filter.vf_id = tunnel_filter->vf_id;
7366 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7368 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7372 if (!add && !node) {
7373 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7379 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7380 vsi->seid, cld_filter, 1);
7382 ret = i40e_aq_add_cloud_filters(hw,
7383 vsi->seid, &cld_filter->element, 1);
7385 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7388 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7389 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7390 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7393 ret = i40e_aq_remove_cloud_filters_big_buffer(
7394 hw, vsi->seid, cld_filter, 1);
7396 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7397 &cld_filter->element, 1);
7399 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7402 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7405 rte_free(cld_filter);
7410 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7414 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7415 if (pf->vxlan_ports[i] == port)
7423 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7427 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7429 idx = i40e_get_vxlan_port_idx(pf, port);
7431 /* Check if port already exists */
7433 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7437 /* Now check if there is space to add the new port */
7438 idx = i40e_get_vxlan_port_idx(pf, 0);
7441 "Maximum number of UDP ports reached, not adding port %d",
7446 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7449 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7453 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7456 /* New port: add it and mark its index in the bitmap */
7457 pf->vxlan_ports[idx] = port;
7458 pf->vxlan_bitmap |= (1 << idx);
7460 if (!(pf->flags & I40E_FLAG_VXLAN))
7461 pf->flags |= I40E_FLAG_VXLAN;
7467 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7470 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7472 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7473 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7477 idx = i40e_get_vxlan_port_idx(pf, port);
7480 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7484 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7485 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7489 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7492 pf->vxlan_ports[idx] = 0;
7493 pf->vxlan_bitmap &= ~(1 << idx);
7495 if (!pf->vxlan_bitmap)
7496 pf->flags &= ~I40E_FLAG_VXLAN;
7501 /* Add UDP tunneling port */
7503 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7504 struct rte_eth_udp_tunnel *udp_tunnel)
7507 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7509 if (udp_tunnel == NULL)
7512 switch (udp_tunnel->prot_type) {
7513 case RTE_TUNNEL_TYPE_VXLAN:
7514 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7517 case RTE_TUNNEL_TYPE_GENEVE:
7518 case RTE_TUNNEL_TYPE_TEREDO:
7519 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7524 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7532 /* Remove UDP tunneling port */
7534 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7535 struct rte_eth_udp_tunnel *udp_tunnel)
7538 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7540 if (udp_tunnel == NULL)
7543 switch (udp_tunnel->prot_type) {
7544 case RTE_TUNNEL_TYPE_VXLAN:
7545 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7547 case RTE_TUNNEL_TYPE_GENEVE:
7548 case RTE_TUNNEL_TYPE_TEREDO:
7549 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7553 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7561 /* Calculate the maximum number of contiguous PF queues that are configured */
7563 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7565 struct rte_eth_dev_data *data = pf->dev_data;
7567 struct i40e_rx_queue *rxq;
7570 for (i = 0; i < pf->lan_nb_qps; i++) {
7571 rxq = data->rx_queues[i];
7572 if (rxq && rxq->q_set)
7583 i40e_pf_config_rss(struct i40e_pf *pf)
7585 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7586 struct rte_eth_rss_conf rss_conf;
7587 uint32_t i, lut = 0;
7591 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7592 * It's necessary to calculate the actual PF queues that are configured.
7594 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7595 num = i40e_pf_calc_configured_queues_num(pf);
7597 num = pf->dev_data->nb_rx_queues;
7599 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7600 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7604 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7608 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7611 lut = (lut << 8) | (j & ((0x1 <<
7612 hw->func_caps.rss_table_entry_width) - 1));
7614 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7617 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7618 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7619 i40e_pf_disable_rss(pf);
7622 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7623 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7624 /* Random default keys */
7625 static uint32_t rss_key_default[] = {0x6b793944,
7626 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7627 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7628 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7630 rss_conf.rss_key = (uint8_t *)rss_key_default;
7631 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7635 return i40e_hw_rss_hash_set(pf, &rss_conf);
7639 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7640 struct rte_eth_tunnel_filter_conf *filter)
7642 if (pf == NULL || filter == NULL) {
7643 PMD_DRV_LOG(ERR, "Invalid parameter");
7647 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7648 PMD_DRV_LOG(ERR, "Invalid queue ID");
7652 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7653 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7657 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7658 (is_zero_ether_addr(&filter->outer_mac))) {
7659 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7663 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7664 (is_zero_ether_addr(&filter->inner_mac))) {
7665 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7672 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7673 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7675 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7680 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7681 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7684 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7685 } else if (len == 4) {
7686 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7688 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7693 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7700 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7701 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7707 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7714 switch (cfg->cfg_type) {
7715 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7716 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7719 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7727 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7728 enum rte_filter_op filter_op,
7731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7732 int ret = I40E_ERR_PARAM;
7734 switch (filter_op) {
7735 case RTE_ETH_FILTER_SET:
7736 ret = i40e_dev_global_config_set(hw,
7737 (struct rte_eth_global_cfg *)arg);
7740 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7748 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7749 enum rte_filter_op filter_op,
7752 struct rte_eth_tunnel_filter_conf *filter;
7753 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7754 int ret = I40E_SUCCESS;
7756 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7758 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7759 return I40E_ERR_PARAM;
7761 switch (filter_op) {
7762 case RTE_ETH_FILTER_NOP:
7763 if (!(pf->flags & I40E_FLAG_VXLAN))
7764 ret = I40E_NOT_SUPPORTED;
7766 case RTE_ETH_FILTER_ADD:
7767 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7769 case RTE_ETH_FILTER_DELETE:
7770 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7773 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7774 ret = I40E_ERR_PARAM;
7782 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7785 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7788 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7789 ret = i40e_pf_config_rss(pf);
7791 i40e_pf_disable_rss(pf);
7796 /* Get the symmetric hash enable configurations per port */
7798 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7800 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7802 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7805 /* Set the symmetric hash enable configurations per port */
7807 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7809 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7812 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7814 "Symmetric hash has already been enabled");
7817 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7819 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7821 "Symmetric hash has already been disabled");
7824 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7826 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7827 I40E_WRITE_FLUSH(hw);
7831 * Get global configurations of hash function type and symmetric hash enable
7832 * per flow type (pctype). Note that global configuration means it affects all
7833 * the ports on the same NIC.
7836 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7837 struct rte_eth_hash_global_conf *g_cfg)
7839 uint32_t reg, mask = I40E_FLOW_TYPES;
7841 enum i40e_filter_pctype pctype;
7843 memset(g_cfg, 0, sizeof(*g_cfg));
7844 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7845 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7846 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7848 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7849 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7850 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7852 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7853 if (!(mask & (1UL << i)))
7855 mask &= ~(1UL << i);
7856 /* Bit set indicats the coresponding flow type is supported */
7857 g_cfg->valid_bit_mask[0] |= (1UL << i);
7858 /* if flowtype is invalid, continue */
7859 if (!I40E_VALID_FLOW(i))
7861 pctype = i40e_flowtype_to_pctype(i);
7862 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7863 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7864 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7871 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7874 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7876 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7877 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7878 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7879 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7885 * As i40e supports less than 32 flow types, only first 32 bits need to
7888 mask0 = g_cfg->valid_bit_mask[0];
7889 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7891 /* Check if any unsupported flow type configured */
7892 if ((mask0 | i40e_mask) ^ i40e_mask)
7895 if (g_cfg->valid_bit_mask[i])
7903 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7909 * Set global configurations of hash function type and symmetric hash enable
7910 * per flow type (pctype). Note any modifying global configuration will affect
7911 * all the ports on the same NIC.
7914 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7915 struct rte_eth_hash_global_conf *g_cfg)
7920 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7921 enum i40e_filter_pctype pctype;
7923 /* Check the input parameters */
7924 ret = i40e_hash_global_config_check(g_cfg);
7928 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7929 if (!(mask0 & (1UL << i)))
7931 mask0 &= ~(1UL << i);
7932 /* if flowtype is invalid, continue */
7933 if (!I40E_VALID_FLOW(i))
7935 pctype = i40e_flowtype_to_pctype(i);
7936 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7937 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7938 if (hw->mac.type == I40E_MAC_X722) {
7939 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7940 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7941 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7942 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7943 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7945 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7946 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7948 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7949 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7950 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7951 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7952 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7954 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7955 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7956 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7957 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7958 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7960 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7961 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7963 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7964 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7965 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7966 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7967 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7970 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7974 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7978 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7979 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7981 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7983 "Hash function already set to Toeplitz");
7986 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7987 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7989 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7991 "Hash function already set to Simple XOR");
7994 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7996 /* Use the default, and keep it as it is */
7999 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8002 I40E_WRITE_FLUSH(hw);
8008 * Valid input sets for hash and flow director filters per PCTYPE
8011 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8012 enum rte_filter_type filter)
8016 static const uint64_t valid_hash_inset_table[] = {
8017 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8018 I40E_INSET_DMAC | I40E_INSET_SMAC |
8019 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8020 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8021 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8022 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8023 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8024 I40E_INSET_FLEX_PAYLOAD,
8025 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8026 I40E_INSET_DMAC | I40E_INSET_SMAC |
8027 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8028 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8029 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8030 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8031 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8032 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8033 I40E_INSET_FLEX_PAYLOAD,
8034 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8035 I40E_INSET_DMAC | I40E_INSET_SMAC |
8036 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8037 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8038 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8039 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8040 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8041 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8042 I40E_INSET_FLEX_PAYLOAD,
8043 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8044 I40E_INSET_DMAC | I40E_INSET_SMAC |
8045 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8046 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8047 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8048 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8049 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8050 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8051 I40E_INSET_FLEX_PAYLOAD,
8052 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8053 I40E_INSET_DMAC | I40E_INSET_SMAC |
8054 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8055 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8056 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8057 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8058 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8059 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8060 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8061 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8062 I40E_INSET_DMAC | I40E_INSET_SMAC |
8063 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8064 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8065 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8066 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8067 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8068 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8069 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8070 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8071 I40E_INSET_DMAC | I40E_INSET_SMAC |
8072 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8073 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8074 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8075 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8076 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8077 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8078 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8079 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8080 I40E_INSET_DMAC | I40E_INSET_SMAC |
8081 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8082 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8083 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8084 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8085 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8086 I40E_INSET_FLEX_PAYLOAD,
8087 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8088 I40E_INSET_DMAC | I40E_INSET_SMAC |
8089 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8090 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8091 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8092 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8093 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8094 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8095 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8096 I40E_INSET_DMAC | I40E_INSET_SMAC |
8097 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8098 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8099 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8100 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8101 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8102 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8103 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8104 I40E_INSET_DMAC | I40E_INSET_SMAC |
8105 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8106 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8107 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8108 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8109 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8110 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8111 I40E_INSET_FLEX_PAYLOAD,
8112 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8113 I40E_INSET_DMAC | I40E_INSET_SMAC |
8114 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8115 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8116 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8117 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8118 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8119 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8120 I40E_INSET_FLEX_PAYLOAD,
8121 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8122 I40E_INSET_DMAC | I40E_INSET_SMAC |
8123 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8124 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8125 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8126 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8127 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8128 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8129 I40E_INSET_FLEX_PAYLOAD,
8130 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8131 I40E_INSET_DMAC | I40E_INSET_SMAC |
8132 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8133 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8134 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8135 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8136 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8137 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8138 I40E_INSET_FLEX_PAYLOAD,
8139 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8140 I40E_INSET_DMAC | I40E_INSET_SMAC |
8141 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8142 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8143 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8144 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8145 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8146 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8147 I40E_INSET_FLEX_PAYLOAD,
8148 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8149 I40E_INSET_DMAC | I40E_INSET_SMAC |
8150 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8151 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8152 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8153 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8154 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8155 I40E_INSET_FLEX_PAYLOAD,
8156 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8157 I40E_INSET_DMAC | I40E_INSET_SMAC |
8158 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8159 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8160 I40E_INSET_FLEX_PAYLOAD,
8164 * Flow director supports only fields defined in
8165 * union rte_eth_fdir_flow.
8167 static const uint64_t valid_fdir_inset_table[] = {
8168 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8169 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8170 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8171 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8172 I40E_INSET_IPV4_TTL,
8173 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8174 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8175 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8176 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8177 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8178 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8179 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8180 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8181 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8182 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8183 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8184 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8185 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8186 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8187 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8188 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8189 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8190 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8191 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8192 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8193 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8194 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8195 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8196 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8197 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8198 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8199 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8200 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8201 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8202 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8204 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8205 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8206 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8207 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8208 I40E_INSET_IPV4_TTL,
8209 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8210 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8211 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8212 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8213 I40E_INSET_IPV6_HOP_LIMIT,
8214 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8215 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8216 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8217 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8218 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8219 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8220 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8221 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8222 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8223 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8224 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8225 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8226 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8227 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8228 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8229 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8230 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8231 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8232 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8233 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8234 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8235 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8236 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8237 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8238 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8239 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8240 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8241 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8242 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8243 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8245 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8246 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8247 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8248 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8249 I40E_INSET_IPV6_HOP_LIMIT,
8250 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8251 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8252 I40E_INSET_LAST_ETHER_TYPE,
8255 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8257 if (filter == RTE_ETH_FILTER_HASH)
8258 valid = valid_hash_inset_table[pctype];
8260 valid = valid_fdir_inset_table[pctype];
8266 * Validate if the input set is allowed for a specific PCTYPE
8269 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8270 enum rte_filter_type filter, uint64_t inset)
8274 valid = i40e_get_valid_input_set(pctype, filter);
8275 if (inset & (~valid))
8281 /* default input set fields combination per pctype */
8283 i40e_get_default_input_set(uint16_t pctype)
8285 static const uint64_t default_inset_table[] = {
8286 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8287 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8288 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8289 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8290 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8291 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8292 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8293 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8294 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8295 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8296 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8297 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8298 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8299 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8300 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8301 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8302 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8303 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8304 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8305 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8307 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8308 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8309 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8310 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8311 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8312 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8313 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8314 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8315 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8316 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8317 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8318 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8319 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8320 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8321 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8322 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8323 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8324 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8325 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8326 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8327 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8328 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8330 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8331 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8332 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8333 I40E_INSET_LAST_ETHER_TYPE,
8336 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8339 return default_inset_table[pctype];
8343 * Parse the input set from index to logical bit masks
8346 i40e_parse_input_set(uint64_t *inset,
8347 enum i40e_filter_pctype pctype,
8348 enum rte_eth_input_set_field *field,
8354 static const struct {
8355 enum rte_eth_input_set_field field;
8357 } inset_convert_table[] = {
8358 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8359 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8360 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8361 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8362 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8363 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8364 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8365 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8366 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8367 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8368 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8369 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8370 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8371 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8372 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8373 I40E_INSET_IPV6_NEXT_HDR},
8374 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8375 I40E_INSET_IPV6_HOP_LIMIT},
8376 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8377 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8378 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8379 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8380 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8381 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8382 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8383 I40E_INSET_SCTP_VT},
8384 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8385 I40E_INSET_TUNNEL_DMAC},
8386 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8387 I40E_INSET_VLAN_TUNNEL},
8388 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8389 I40E_INSET_TUNNEL_ID},
8390 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8391 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8392 I40E_INSET_FLEX_PAYLOAD_W1},
8393 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8394 I40E_INSET_FLEX_PAYLOAD_W2},
8395 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8396 I40E_INSET_FLEX_PAYLOAD_W3},
8397 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8398 I40E_INSET_FLEX_PAYLOAD_W4},
8399 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8400 I40E_INSET_FLEX_PAYLOAD_W5},
8401 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8402 I40E_INSET_FLEX_PAYLOAD_W6},
8403 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8404 I40E_INSET_FLEX_PAYLOAD_W7},
8405 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8406 I40E_INSET_FLEX_PAYLOAD_W8},
8409 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8412 /* Only one item allowed for default or all */
8414 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8415 *inset = i40e_get_default_input_set(pctype);
8417 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8418 *inset = I40E_INSET_NONE;
8423 for (i = 0, *inset = 0; i < size; i++) {
8424 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8425 if (field[i] == inset_convert_table[j].field) {
8426 *inset |= inset_convert_table[j].inset;
8431 /* It contains unsupported input set, return immediately */
8432 if (j == RTE_DIM(inset_convert_table))
8440 * Translate the input set from bit masks to register aware bit masks
8444 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8454 static const struct inset_map inset_map_common[] = {
8455 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8456 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8457 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8458 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8459 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8460 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8461 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8462 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8463 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8464 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8465 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8466 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8467 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8468 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8469 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8470 {I40E_INSET_TUNNEL_DMAC,
8471 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8472 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8473 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8474 {I40E_INSET_TUNNEL_SRC_PORT,
8475 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8476 {I40E_INSET_TUNNEL_DST_PORT,
8477 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8478 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8479 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8480 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8481 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8482 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8483 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8484 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8485 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8486 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8489 /* some different registers map in x722*/
8490 static const struct inset_map inset_map_diff_x722[] = {
8491 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8492 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8493 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8494 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8497 static const struct inset_map inset_map_diff_not_x722[] = {
8498 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8499 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8500 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8501 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8507 /* Translate input set to register aware inset */
8508 if (type == I40E_MAC_X722) {
8509 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8510 if (input & inset_map_diff_x722[i].inset)
8511 val |= inset_map_diff_x722[i].inset_reg;
8514 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8515 if (input & inset_map_diff_not_x722[i].inset)
8516 val |= inset_map_diff_not_x722[i].inset_reg;
8520 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8521 if (input & inset_map_common[i].inset)
8522 val |= inset_map_common[i].inset_reg;
8529 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8532 uint64_t inset_need_mask = inset;
8534 static const struct {
8537 } inset_mask_map[] = {
8538 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8539 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8540 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8541 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8542 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8543 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8544 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8545 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8548 if (!inset || !mask || !nb_elem)
8551 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8552 /* Clear the inset bit, if no MASK is required,
8553 * for example proto + ttl
8555 if ((inset & inset_mask_map[i].inset) ==
8556 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8557 inset_need_mask &= ~inset_mask_map[i].inset;
8558 if (!inset_need_mask)
8561 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8562 if ((inset_need_mask & inset_mask_map[i].inset) ==
8563 inset_mask_map[i].inset) {
8564 if (idx >= nb_elem) {
8565 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8568 mask[idx] = inset_mask_map[i].mask;
8577 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8579 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8581 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8583 i40e_write_rx_ctl(hw, addr, val);
8584 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8585 (uint32_t)i40e_read_rx_ctl(hw, addr));
8589 i40e_filter_input_set_init(struct i40e_pf *pf)
8591 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8592 enum i40e_filter_pctype pctype;
8593 uint64_t input_set, inset_reg;
8594 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8597 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8598 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8599 if (hw->mac.type == I40E_MAC_X722) {
8600 if (!I40E_VALID_PCTYPE_X722(pctype))
8603 if (!I40E_VALID_PCTYPE(pctype))
8607 input_set = i40e_get_default_input_set(pctype);
8609 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8610 I40E_INSET_MASK_NUM_REG);
8613 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8616 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8617 (uint32_t)(inset_reg & UINT32_MAX));
8618 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8619 (uint32_t)((inset_reg >>
8620 I40E_32_BIT_WIDTH) & UINT32_MAX));
8621 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8622 (uint32_t)(inset_reg & UINT32_MAX));
8623 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8624 (uint32_t)((inset_reg >>
8625 I40E_32_BIT_WIDTH) & UINT32_MAX));
8627 for (i = 0; i < num; i++) {
8628 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8630 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8633 /*clear unused mask registers of the pctype */
8634 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8635 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8637 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8640 I40E_WRITE_FLUSH(hw);
8642 /* store the default input set */
8643 pf->hash_input_set[pctype] = input_set;
8644 pf->fdir.input_set[pctype] = input_set;
8649 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8650 struct rte_eth_input_set_conf *conf)
8652 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8653 enum i40e_filter_pctype pctype;
8654 uint64_t input_set, inset_reg = 0;
8655 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8659 PMD_DRV_LOG(ERR, "Invalid pointer");
8662 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8663 conf->op != RTE_ETH_INPUT_SET_ADD) {
8664 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8668 if (!I40E_VALID_FLOW(conf->flow_type)) {
8669 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8673 if (hw->mac.type == I40E_MAC_X722) {
8674 /* get translated pctype value in fd pctype register */
8675 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8676 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8679 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8681 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8684 PMD_DRV_LOG(ERR, "Failed to parse input set");
8687 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8689 PMD_DRV_LOG(ERR, "Invalid input set");
8692 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8693 /* get inset value in register */
8694 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8695 inset_reg <<= I40E_32_BIT_WIDTH;
8696 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8697 input_set |= pf->hash_input_set[pctype];
8699 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8700 I40E_INSET_MASK_NUM_REG);
8704 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8706 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8707 (uint32_t)(inset_reg & UINT32_MAX));
8708 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8709 (uint32_t)((inset_reg >>
8710 I40E_32_BIT_WIDTH) & UINT32_MAX));
8712 for (i = 0; i < num; i++)
8713 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8715 /*clear unused mask registers of the pctype */
8716 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8717 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8719 I40E_WRITE_FLUSH(hw);
8721 pf->hash_input_set[pctype] = input_set;
8726 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8727 struct rte_eth_input_set_conf *conf)
8729 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8730 enum i40e_filter_pctype pctype;
8731 uint64_t input_set, inset_reg = 0;
8732 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8736 PMD_DRV_LOG(ERR, "Invalid pointer");
8739 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8740 conf->op != RTE_ETH_INPUT_SET_ADD) {
8741 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8745 if (!I40E_VALID_FLOW(conf->flow_type)) {
8746 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8750 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8752 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8755 PMD_DRV_LOG(ERR, "Failed to parse input set");
8758 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8760 PMD_DRV_LOG(ERR, "Invalid input set");
8764 /* get inset value in register */
8765 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8766 inset_reg <<= I40E_32_BIT_WIDTH;
8767 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8769 /* Can not change the inset reg for flex payload for fdir,
8770 * it is done by writing I40E_PRTQF_FD_FLXINSET
8771 * in i40e_set_flex_mask_on_pctype.
8773 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8774 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8776 input_set |= pf->fdir.input_set[pctype];
8777 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8778 I40E_INSET_MASK_NUM_REG);
8782 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8784 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8785 (uint32_t)(inset_reg & UINT32_MAX));
8786 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8787 (uint32_t)((inset_reg >>
8788 I40E_32_BIT_WIDTH) & UINT32_MAX));
8790 for (i = 0; i < num; i++)
8791 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8793 /*clear unused mask registers of the pctype */
8794 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8795 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8797 I40E_WRITE_FLUSH(hw);
8799 pf->fdir.input_set[pctype] = input_set;
8804 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8809 PMD_DRV_LOG(ERR, "Invalid pointer");
8813 switch (info->info_type) {
8814 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8815 i40e_get_symmetric_hash_enable_per_port(hw,
8816 &(info->info.enable));
8818 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8819 ret = i40e_get_hash_filter_global_config(hw,
8820 &(info->info.global_conf));
8823 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8833 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8838 PMD_DRV_LOG(ERR, "Invalid pointer");
8842 switch (info->info_type) {
8843 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8844 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8846 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8847 ret = i40e_set_hash_filter_global_config(hw,
8848 &(info->info.global_conf));
8850 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8851 ret = i40e_hash_filter_inset_select(hw,
8852 &(info->info.input_set_conf));
8856 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8865 /* Operations for hash function */
8867 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8868 enum rte_filter_op filter_op,
8871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8874 switch (filter_op) {
8875 case RTE_ETH_FILTER_NOP:
8877 case RTE_ETH_FILTER_GET:
8878 ret = i40e_hash_filter_get(hw,
8879 (struct rte_eth_hash_filter_info *)arg);
8881 case RTE_ETH_FILTER_SET:
8882 ret = i40e_hash_filter_set(hw,
8883 (struct rte_eth_hash_filter_info *)arg);
8886 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8895 /* Convert ethertype filter structure */
8897 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8898 struct i40e_ethertype_filter *filter)
8900 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8901 filter->input.ether_type = input->ether_type;
8902 filter->flags = input->flags;
8903 filter->queue = input->queue;
8908 /* Check if there exists the ehtertype filter */
8909 struct i40e_ethertype_filter *
8910 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8911 const struct i40e_ethertype_filter_input *input)
8915 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8919 return ethertype_rule->hash_map[ret];
8922 /* Add ethertype filter in SW list */
8924 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8925 struct i40e_ethertype_filter *filter)
8927 struct i40e_ethertype_rule *rule = &pf->ethertype;
8930 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8933 "Failed to insert ethertype filter"
8934 " to hash table %d!",
8938 rule->hash_map[ret] = filter;
8940 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8945 /* Delete ethertype filter in SW list */
8947 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8948 struct i40e_ethertype_filter_input *input)
8950 struct i40e_ethertype_rule *rule = &pf->ethertype;
8951 struct i40e_ethertype_filter *filter;
8954 ret = rte_hash_del_key(rule->hash_table, input);
8957 "Failed to delete ethertype filter"
8958 " to hash table %d!",
8962 filter = rule->hash_map[ret];
8963 rule->hash_map[ret] = NULL;
8965 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8972 * Configure ethertype filter, which can director packet by filtering
8973 * with mac address and ether_type or only ether_type
8976 i40e_ethertype_filter_set(struct i40e_pf *pf,
8977 struct rte_eth_ethertype_filter *filter,
8980 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8981 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8982 struct i40e_ethertype_filter *ethertype_filter, *node;
8983 struct i40e_ethertype_filter check_filter;
8984 struct i40e_control_filter_stats stats;
8988 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8989 PMD_DRV_LOG(ERR, "Invalid queue ID");
8992 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8993 filter->ether_type == ETHER_TYPE_IPv6) {
8995 "unsupported ether_type(0x%04x) in control packet filter.",
8996 filter->ether_type);
8999 if (filter->ether_type == ETHER_TYPE_VLAN)
9000 PMD_DRV_LOG(WARNING,
9001 "filter vlan ether_type in first tag is not supported.");
9003 /* Check if there is the filter in SW list */
9004 memset(&check_filter, 0, sizeof(check_filter));
9005 i40e_ethertype_filter_convert(filter, &check_filter);
9006 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9007 &check_filter.input);
9009 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9013 if (!add && !node) {
9014 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9018 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9019 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9020 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9021 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9022 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9024 memset(&stats, 0, sizeof(stats));
9025 ret = i40e_aq_add_rem_control_packet_filter(hw,
9026 filter->mac_addr.addr_bytes,
9027 filter->ether_type, flags,
9029 filter->queue, add, &stats, NULL);
9032 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9033 ret, stats.mac_etype_used, stats.etype_used,
9034 stats.mac_etype_free, stats.etype_free);
9038 /* Add or delete a filter in SW list */
9040 ethertype_filter = rte_zmalloc("ethertype_filter",
9041 sizeof(*ethertype_filter), 0);
9042 rte_memcpy(ethertype_filter, &check_filter,
9043 sizeof(check_filter));
9044 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9046 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9053 * Handle operations for ethertype filter.
9056 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9057 enum rte_filter_op filter_op,
9060 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9063 if (filter_op == RTE_ETH_FILTER_NOP)
9067 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9072 switch (filter_op) {
9073 case RTE_ETH_FILTER_ADD:
9074 ret = i40e_ethertype_filter_set(pf,
9075 (struct rte_eth_ethertype_filter *)arg,
9078 case RTE_ETH_FILTER_DELETE:
9079 ret = i40e_ethertype_filter_set(pf,
9080 (struct rte_eth_ethertype_filter *)arg,
9084 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9092 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9093 enum rte_filter_type filter_type,
9094 enum rte_filter_op filter_op,
9102 switch (filter_type) {
9103 case RTE_ETH_FILTER_NONE:
9104 /* For global configuration */
9105 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9107 case RTE_ETH_FILTER_HASH:
9108 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9110 case RTE_ETH_FILTER_MACVLAN:
9111 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9113 case RTE_ETH_FILTER_ETHERTYPE:
9114 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9116 case RTE_ETH_FILTER_TUNNEL:
9117 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9119 case RTE_ETH_FILTER_FDIR:
9120 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9122 case RTE_ETH_FILTER_GENERIC:
9123 if (filter_op != RTE_ETH_FILTER_GET)
9125 *(const void **)arg = &i40e_flow_ops;
9128 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9138 * Check and enable Extended Tag.
9139 * Enabling Extended Tag is important for 40G performance.
9142 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9144 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9148 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9151 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9155 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9156 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9161 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9164 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9168 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9169 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9172 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9173 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9176 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9183 * As some registers wouldn't be reset unless a global hardware reset,
9184 * hardware initialization is needed to put those registers into an
9185 * expected initial state.
9188 i40e_hw_init(struct rte_eth_dev *dev)
9190 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9192 i40e_enable_extended_tag(dev);
9194 /* clear the PF Queue Filter control register */
9195 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9197 /* Disable symmetric hash per port */
9198 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9201 enum i40e_filter_pctype
9202 i40e_flowtype_to_pctype(uint16_t flow_type)
9204 static const enum i40e_filter_pctype pctype_table[] = {
9205 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9206 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9207 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9208 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9209 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9210 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9211 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9212 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9213 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9214 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9215 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9216 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9217 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9218 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9219 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9220 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9221 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9222 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9223 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9226 return pctype_table[flow_type];
9230 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9232 static const uint16_t flowtype_table[] = {
9233 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9234 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9235 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9236 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9237 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9238 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9239 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9240 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9241 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9242 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9243 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9244 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9245 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9246 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9247 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9248 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9249 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9250 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9251 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9252 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9253 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9254 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9255 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9256 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9257 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9258 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9259 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9260 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9261 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9262 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9263 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9266 return flowtype_table[pctype];
9270 * On X710, performance number is far from the expectation on recent firmware
9271 * versions; on XL710, performance number is also far from the expectation on
9272 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9273 * mode is enabled and port MAC address is equal to the packet destination MAC
9274 * address. The fix for this issue may not be integrated in the following
9275 * firmware version. So the workaround in software driver is needed. It needs
9276 * to modify the initial values of 3 internal only registers for both X710 and
9277 * XL710. Note that the values for X710 or XL710 could be different, and the
9278 * workaround can be removed when it is fixed in firmware in the future.
9281 /* For both X710 and XL710 */
9282 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9283 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
9284 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9286 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9287 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9290 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9291 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9294 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9296 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9297 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9300 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9302 enum i40e_status_code status;
9303 struct i40e_aq_get_phy_abilities_resp phy_ab;
9307 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9311 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9314 rte_delay_us(100000);
9316 status = i40e_aq_get_phy_capabilities(hw, false,
9317 true, &phy_ab, NULL);
9325 i40e_configure_registers(struct i40e_hw *hw)
9331 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9332 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9333 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9339 for (i = 0; i < RTE_DIM(reg_table); i++) {
9340 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9341 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9343 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9344 else /* For X710/XL710/XXV710 */
9345 if (hw->aq.fw_maj_ver < 6)
9347 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9350 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9353 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9354 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9356 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9357 else /* For X710/XL710/XXV710 */
9359 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9362 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9363 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9364 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9366 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9369 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9372 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9375 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9379 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9380 reg_table[i].addr, reg);
9381 if (reg == reg_table[i].val)
9384 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9385 reg_table[i].val, NULL);
9388 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9389 reg_table[i].val, reg_table[i].addr);
9392 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9393 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9397 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9398 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9399 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9400 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9402 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9407 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9408 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9412 /* Configure for double VLAN RX stripping */
9413 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9414 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9415 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9416 ret = i40e_aq_debug_write_register(hw,
9417 I40E_VSI_TSR(vsi->vsi_id),
9420 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9422 return I40E_ERR_CONFIG;
9426 /* Configure for double VLAN TX insertion */
9427 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9428 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9429 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9430 ret = i40e_aq_debug_write_register(hw,
9431 I40E_VSI_L2TAGSTXVALID(
9432 vsi->vsi_id), reg, NULL);
9435 "Failed to update VSI_L2TAGSTXVALID[%d]",
9437 return I40E_ERR_CONFIG;
9445 * i40e_aq_add_mirror_rule
9446 * @hw: pointer to the hardware structure
9447 * @seid: VEB seid to add mirror rule to
9448 * @dst_id: destination vsi seid
9449 * @entries: Buffer which contains the entities to be mirrored
9450 * @count: number of entities contained in the buffer
9451 * @rule_id:the rule_id of the rule to be added
9453 * Add a mirror rule for a given veb.
9456 static enum i40e_status_code
9457 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9458 uint16_t seid, uint16_t dst_id,
9459 uint16_t rule_type, uint16_t *entries,
9460 uint16_t count, uint16_t *rule_id)
9462 struct i40e_aq_desc desc;
9463 struct i40e_aqc_add_delete_mirror_rule cmd;
9464 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9465 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9468 enum i40e_status_code status;
9470 i40e_fill_default_direct_cmd_desc(&desc,
9471 i40e_aqc_opc_add_mirror_rule);
9472 memset(&cmd, 0, sizeof(cmd));
9474 buff_len = sizeof(uint16_t) * count;
9475 desc.datalen = rte_cpu_to_le_16(buff_len);
9477 desc.flags |= rte_cpu_to_le_16(
9478 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9479 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9480 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9481 cmd.num_entries = rte_cpu_to_le_16(count);
9482 cmd.seid = rte_cpu_to_le_16(seid);
9483 cmd.destination = rte_cpu_to_le_16(dst_id);
9485 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9486 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9488 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9489 hw->aq.asq_last_status, resp->rule_id,
9490 resp->mirror_rules_used, resp->mirror_rules_free);
9491 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9497 * i40e_aq_del_mirror_rule
9498 * @hw: pointer to the hardware structure
9499 * @seid: VEB seid to add mirror rule to
9500 * @entries: Buffer which contains the entities to be mirrored
9501 * @count: number of entities contained in the buffer
9502 * @rule_id:the rule_id of the rule to be delete
9504 * Delete a mirror rule for a given veb.
9507 static enum i40e_status_code
9508 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9509 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9510 uint16_t count, uint16_t rule_id)
9512 struct i40e_aq_desc desc;
9513 struct i40e_aqc_add_delete_mirror_rule cmd;
9514 uint16_t buff_len = 0;
9515 enum i40e_status_code status;
9518 i40e_fill_default_direct_cmd_desc(&desc,
9519 i40e_aqc_opc_delete_mirror_rule);
9520 memset(&cmd, 0, sizeof(cmd));
9521 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9522 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9524 cmd.num_entries = count;
9525 buff_len = sizeof(uint16_t) * count;
9526 desc.datalen = rte_cpu_to_le_16(buff_len);
9527 buff = (void *)entries;
9529 /* rule id is filled in destination field for deleting mirror rule */
9530 cmd.destination = rte_cpu_to_le_16(rule_id);
9532 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9533 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9534 cmd.seid = rte_cpu_to_le_16(seid);
9536 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9537 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9543 * i40e_mirror_rule_set
9544 * @dev: pointer to the hardware structure
9545 * @mirror_conf: mirror rule info
9546 * @sw_id: mirror rule's sw_id
9547 * @on: enable/disable
9549 * set a mirror rule.
9553 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9554 struct rte_eth_mirror_conf *mirror_conf,
9555 uint8_t sw_id, uint8_t on)
9557 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9558 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9559 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9560 struct i40e_mirror_rule *parent = NULL;
9561 uint16_t seid, dst_seid, rule_id;
9565 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9567 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9569 "mirror rule can not be configured without veb or vfs.");
9572 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9573 PMD_DRV_LOG(ERR, "mirror table is full.");
9576 if (mirror_conf->dst_pool > pf->vf_num) {
9577 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9578 mirror_conf->dst_pool);
9582 seid = pf->main_vsi->veb->seid;
9584 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9585 if (sw_id <= it->index) {
9591 if (mirr_rule && sw_id == mirr_rule->index) {
9593 PMD_DRV_LOG(ERR, "mirror rule exists.");
9596 ret = i40e_aq_del_mirror_rule(hw, seid,
9597 mirr_rule->rule_type,
9599 mirr_rule->num_entries, mirr_rule->id);
9602 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9603 ret, hw->aq.asq_last_status);
9606 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9607 rte_free(mirr_rule);
9608 pf->nb_mirror_rule--;
9612 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9616 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9617 sizeof(struct i40e_mirror_rule) , 0);
9619 PMD_DRV_LOG(ERR, "failed to allocate memory");
9620 return I40E_ERR_NO_MEMORY;
9622 switch (mirror_conf->rule_type) {
9623 case ETH_MIRROR_VLAN:
9624 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9625 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9626 mirr_rule->entries[j] =
9627 mirror_conf->vlan.vlan_id[i];
9632 PMD_DRV_LOG(ERR, "vlan is not specified.");
9633 rte_free(mirr_rule);
9636 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9638 case ETH_MIRROR_VIRTUAL_POOL_UP:
9639 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9640 /* check if the specified pool bit is out of range */
9641 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9642 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9643 rte_free(mirr_rule);
9646 for (i = 0, j = 0; i < pf->vf_num; i++) {
9647 if (mirror_conf->pool_mask & (1ULL << i)) {
9648 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9652 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9653 /* add pf vsi to entries */
9654 mirr_rule->entries[j] = pf->main_vsi_seid;
9658 PMD_DRV_LOG(ERR, "pool is not specified.");
9659 rte_free(mirr_rule);
9662 /* egress and ingress in aq commands means from switch but not port */
9663 mirr_rule->rule_type =
9664 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9665 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9666 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9668 case ETH_MIRROR_UPLINK_PORT:
9669 /* egress and ingress in aq commands means from switch but not port*/
9670 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9672 case ETH_MIRROR_DOWNLINK_PORT:
9673 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9676 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9677 mirror_conf->rule_type);
9678 rte_free(mirr_rule);
9682 /* If the dst_pool is equal to vf_num, consider it as PF */
9683 if (mirror_conf->dst_pool == pf->vf_num)
9684 dst_seid = pf->main_vsi_seid;
9686 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9688 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9689 mirr_rule->rule_type, mirr_rule->entries,
9693 "failed to add mirror rule: ret = %d, aq_err = %d.",
9694 ret, hw->aq.asq_last_status);
9695 rte_free(mirr_rule);
9699 mirr_rule->index = sw_id;
9700 mirr_rule->num_entries = j;
9701 mirr_rule->id = rule_id;
9702 mirr_rule->dst_vsi_seid = dst_seid;
9705 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9707 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9709 pf->nb_mirror_rule++;
9714 * i40e_mirror_rule_reset
9715 * @dev: pointer to the device
9716 * @sw_id: mirror rule's sw_id
9718 * reset a mirror rule.
9722 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9724 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9725 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9726 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9730 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9732 seid = pf->main_vsi->veb->seid;
9734 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9735 if (sw_id == it->index) {
9741 ret = i40e_aq_del_mirror_rule(hw, seid,
9742 mirr_rule->rule_type,
9744 mirr_rule->num_entries, mirr_rule->id);
9747 "failed to remove mirror rule: status = %d, aq_err = %d.",
9748 ret, hw->aq.asq_last_status);
9751 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9752 rte_free(mirr_rule);
9753 pf->nb_mirror_rule--;
9755 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9762 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9764 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9765 uint64_t systim_cycles;
9767 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9768 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9771 return systim_cycles;
9775 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9777 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9780 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9781 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9788 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9790 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9793 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9794 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9801 i40e_start_timecounters(struct rte_eth_dev *dev)
9803 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9804 struct i40e_adapter *adapter =
9805 (struct i40e_adapter *)dev->data->dev_private;
9806 struct rte_eth_link link;
9807 uint32_t tsync_inc_l;
9808 uint32_t tsync_inc_h;
9810 /* Get current link speed. */
9811 memset(&link, 0, sizeof(link));
9812 i40e_dev_link_update(dev, 1);
9813 rte_i40e_dev_atomic_read_link_status(dev, &link);
9815 switch (link.link_speed) {
9816 case ETH_SPEED_NUM_40G:
9817 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9818 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9820 case ETH_SPEED_NUM_10G:
9821 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9822 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9824 case ETH_SPEED_NUM_1G:
9825 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9826 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9833 /* Set the timesync increment value. */
9834 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9835 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9837 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9838 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9839 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9841 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9842 adapter->systime_tc.cc_shift = 0;
9843 adapter->systime_tc.nsec_mask = 0;
9845 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9846 adapter->rx_tstamp_tc.cc_shift = 0;
9847 adapter->rx_tstamp_tc.nsec_mask = 0;
9849 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9850 adapter->tx_tstamp_tc.cc_shift = 0;
9851 adapter->tx_tstamp_tc.nsec_mask = 0;
9855 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9857 struct i40e_adapter *adapter =
9858 (struct i40e_adapter *)dev->data->dev_private;
9860 adapter->systime_tc.nsec += delta;
9861 adapter->rx_tstamp_tc.nsec += delta;
9862 adapter->tx_tstamp_tc.nsec += delta;
9868 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9871 struct i40e_adapter *adapter =
9872 (struct i40e_adapter *)dev->data->dev_private;
9874 ns = rte_timespec_to_ns(ts);
9876 /* Set the timecounters to a new value. */
9877 adapter->systime_tc.nsec = ns;
9878 adapter->rx_tstamp_tc.nsec = ns;
9879 adapter->tx_tstamp_tc.nsec = ns;
9885 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9887 uint64_t ns, systime_cycles;
9888 struct i40e_adapter *adapter =
9889 (struct i40e_adapter *)dev->data->dev_private;
9891 systime_cycles = i40e_read_systime_cyclecounter(dev);
9892 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9893 *ts = rte_ns_to_timespec(ns);
9899 i40e_timesync_enable(struct rte_eth_dev *dev)
9901 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9902 uint32_t tsync_ctl_l;
9903 uint32_t tsync_ctl_h;
9905 /* Stop the timesync system time. */
9906 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9907 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9908 /* Reset the timesync system time value. */
9909 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9910 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9912 i40e_start_timecounters(dev);
9914 /* Clear timesync registers. */
9915 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9916 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9917 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9918 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9919 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9920 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9922 /* Enable timestamping of PTP packets. */
9923 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9924 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9926 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9927 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9928 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9930 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9931 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9937 i40e_timesync_disable(struct rte_eth_dev *dev)
9939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9940 uint32_t tsync_ctl_l;
9941 uint32_t tsync_ctl_h;
9943 /* Disable timestamping of transmitted PTP packets. */
9944 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9945 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9947 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9948 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9950 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9951 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9953 /* Reset the timesync increment value. */
9954 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9955 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9961 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9962 struct timespec *timestamp, uint32_t flags)
9964 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9965 struct i40e_adapter *adapter =
9966 (struct i40e_adapter *)dev->data->dev_private;
9968 uint32_t sync_status;
9969 uint32_t index = flags & 0x03;
9970 uint64_t rx_tstamp_cycles;
9973 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9974 if ((sync_status & (1 << index)) == 0)
9977 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9978 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9979 *timestamp = rte_ns_to_timespec(ns);
9985 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9986 struct timespec *timestamp)
9988 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9989 struct i40e_adapter *adapter =
9990 (struct i40e_adapter *)dev->data->dev_private;
9992 uint32_t sync_status;
9993 uint64_t tx_tstamp_cycles;
9996 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9997 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10000 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10001 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10002 *timestamp = rte_ns_to_timespec(ns);
10008 * i40e_parse_dcb_configure - parse dcb configure from user
10009 * @dev: the device being configured
10010 * @dcb_cfg: pointer of the result of parse
10011 * @*tc_map: bit map of enabled traffic classes
10013 * Returns 0 on success, negative value on failure
10016 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10017 struct i40e_dcbx_config *dcb_cfg,
10020 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10021 uint8_t i, tc_bw, bw_lf;
10023 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10025 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10026 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10027 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10031 /* assume each tc has the same bw */
10032 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10033 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10034 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10035 /* to ensure the sum of tcbw is equal to 100 */
10036 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10037 for (i = 0; i < bw_lf; i++)
10038 dcb_cfg->etscfg.tcbwtable[i]++;
10040 /* assume each tc has the same Transmission Selection Algorithm */
10041 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10042 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10044 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10045 dcb_cfg->etscfg.prioritytable[i] =
10046 dcb_rx_conf->dcb_tc[i];
10048 /* FW needs one App to configure HW */
10049 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10050 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10051 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10052 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10054 if (dcb_rx_conf->nb_tcs == 0)
10055 *tc_map = 1; /* tc0 only */
10057 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10059 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10060 dcb_cfg->pfc.willing = 0;
10061 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10062 dcb_cfg->pfc.pfcenable = *tc_map;
10068 static enum i40e_status_code
10069 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10070 struct i40e_aqc_vsi_properties_data *info,
10071 uint8_t enabled_tcmap)
10073 enum i40e_status_code ret;
10074 int i, total_tc = 0;
10075 uint16_t qpnum_per_tc, bsf, qp_idx;
10076 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10077 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10078 uint16_t used_queues;
10080 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10081 if (ret != I40E_SUCCESS)
10084 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10085 if (enabled_tcmap & (1 << i))
10090 vsi->enabled_tc = enabled_tcmap;
10092 /* different VSI has different queues assigned */
10093 if (vsi->type == I40E_VSI_MAIN)
10094 used_queues = dev_data->nb_rx_queues -
10095 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10096 else if (vsi->type == I40E_VSI_VMDQ2)
10097 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10099 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10100 return I40E_ERR_NO_AVAILABLE_VSI;
10103 qpnum_per_tc = used_queues / total_tc;
10104 /* Number of queues per enabled TC */
10105 if (qpnum_per_tc == 0) {
10106 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10107 return I40E_ERR_INVALID_QP_ID;
10109 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10110 I40E_MAX_Q_PER_TC);
10111 bsf = rte_bsf32(qpnum_per_tc);
10114 * Configure TC and queue mapping parameters, for enabled TC,
10115 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10116 * default queue will serve it.
10119 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10120 if (vsi->enabled_tc & (1 << i)) {
10121 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10122 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10123 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10124 qp_idx += qpnum_per_tc;
10126 info->tc_mapping[i] = 0;
10129 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10130 if (vsi->type == I40E_VSI_SRIOV) {
10131 info->mapping_flags |=
10132 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10133 for (i = 0; i < vsi->nb_qps; i++)
10134 info->queue_mapping[i] =
10135 rte_cpu_to_le_16(vsi->base_queue + i);
10137 info->mapping_flags |=
10138 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10139 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10141 info->valid_sections |=
10142 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10144 return I40E_SUCCESS;
10148 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10149 * @veb: VEB to be configured
10150 * @tc_map: enabled TC bitmap
10152 * Returns 0 on success, negative value on failure
10154 static enum i40e_status_code
10155 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10157 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10158 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10159 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10160 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10161 enum i40e_status_code ret = I40E_SUCCESS;
10165 /* Check if enabled_tc is same as existing or new TCs */
10166 if (veb->enabled_tc == tc_map)
10169 /* configure tc bandwidth */
10170 memset(&veb_bw, 0, sizeof(veb_bw));
10171 veb_bw.tc_valid_bits = tc_map;
10172 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10173 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10174 if (tc_map & BIT_ULL(i))
10175 veb_bw.tc_bw_share_credits[i] = 1;
10177 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10181 "AQ command Config switch_comp BW allocation per TC failed = %d",
10182 hw->aq.asq_last_status);
10186 memset(&ets_query, 0, sizeof(ets_query));
10187 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10189 if (ret != I40E_SUCCESS) {
10191 "Failed to get switch_comp ETS configuration %u",
10192 hw->aq.asq_last_status);
10195 memset(&bw_query, 0, sizeof(bw_query));
10196 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10198 if (ret != I40E_SUCCESS) {
10200 "Failed to get switch_comp bandwidth configuration %u",
10201 hw->aq.asq_last_status);
10205 /* store and print out BW info */
10206 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10207 veb->bw_info.bw_max = ets_query.tc_bw_max;
10208 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10209 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10210 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10211 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10212 I40E_16_BIT_WIDTH);
10213 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10214 veb->bw_info.bw_ets_share_credits[i] =
10215 bw_query.tc_bw_share_credits[i];
10216 veb->bw_info.bw_ets_credits[i] =
10217 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10218 /* 4 bits per TC, 4th bit is reserved */
10219 veb->bw_info.bw_ets_max[i] =
10220 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10221 RTE_LEN2MASK(3, uint8_t));
10222 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10223 veb->bw_info.bw_ets_share_credits[i]);
10224 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10225 veb->bw_info.bw_ets_credits[i]);
10226 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10227 veb->bw_info.bw_ets_max[i]);
10230 veb->enabled_tc = tc_map;
10237 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10238 * @vsi: VSI to be configured
10239 * @tc_map: enabled TC bitmap
10241 * Returns 0 on success, negative value on failure
10243 static enum i40e_status_code
10244 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10246 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10247 struct i40e_vsi_context ctxt;
10248 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10249 enum i40e_status_code ret = I40E_SUCCESS;
10252 /* Check if enabled_tc is same as existing or new TCs */
10253 if (vsi->enabled_tc == tc_map)
10256 /* configure tc bandwidth */
10257 memset(&bw_data, 0, sizeof(bw_data));
10258 bw_data.tc_valid_bits = tc_map;
10259 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10260 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10261 if (tc_map & BIT_ULL(i))
10262 bw_data.tc_bw_credits[i] = 1;
10264 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10267 "AQ command Config VSI BW allocation per TC failed = %d",
10268 hw->aq.asq_last_status);
10271 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10272 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10274 /* Update Queue Pairs Mapping for currently enabled UPs */
10275 ctxt.seid = vsi->seid;
10276 ctxt.pf_num = hw->pf_id;
10278 ctxt.uplink_seid = vsi->uplink_seid;
10279 ctxt.info = vsi->info;
10281 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10285 /* Update the VSI after updating the VSI queue-mapping information */
10286 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10288 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10289 hw->aq.asq_last_status);
10292 /* update the local VSI info with updated queue map */
10293 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10294 sizeof(vsi->info.tc_mapping));
10295 rte_memcpy(&vsi->info.queue_mapping,
10296 &ctxt.info.queue_mapping,
10297 sizeof(vsi->info.queue_mapping));
10298 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10299 vsi->info.valid_sections = 0;
10301 /* query and update current VSI BW information */
10302 ret = i40e_vsi_get_bw_config(vsi);
10305 "Failed updating vsi bw info, err %s aq_err %s",
10306 i40e_stat_str(hw, ret),
10307 i40e_aq_str(hw, hw->aq.asq_last_status));
10311 vsi->enabled_tc = tc_map;
10318 * i40e_dcb_hw_configure - program the dcb setting to hw
10319 * @pf: pf the configuration is taken on
10320 * @new_cfg: new configuration
10321 * @tc_map: enabled TC bitmap
10323 * Returns 0 on success, negative value on failure
10325 static enum i40e_status_code
10326 i40e_dcb_hw_configure(struct i40e_pf *pf,
10327 struct i40e_dcbx_config *new_cfg,
10330 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10331 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10332 struct i40e_vsi *main_vsi = pf->main_vsi;
10333 struct i40e_vsi_list *vsi_list;
10334 enum i40e_status_code ret;
10338 /* Use the FW API if FW > v4.4*/
10339 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10340 (hw->aq.fw_maj_ver >= 5))) {
10342 "FW < v4.4, can not use FW LLDP API to configure DCB");
10343 return I40E_ERR_FIRMWARE_API_VERSION;
10346 /* Check if need reconfiguration */
10347 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10348 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10349 return I40E_SUCCESS;
10352 /* Copy the new config to the current config */
10353 *old_cfg = *new_cfg;
10354 old_cfg->etsrec = old_cfg->etscfg;
10355 ret = i40e_set_dcb_config(hw);
10357 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10358 i40e_stat_str(hw, ret),
10359 i40e_aq_str(hw, hw->aq.asq_last_status));
10362 /* set receive Arbiter to RR mode and ETS scheme by default */
10363 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10364 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10365 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10366 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10367 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10368 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10369 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10370 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10371 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10372 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10373 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10374 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10375 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10377 /* get local mib to check whether it is configured correctly */
10379 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10380 /* Get Local DCB Config */
10381 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10382 &hw->local_dcbx_config);
10384 /* if Veb is created, need to update TC of it at first */
10385 if (main_vsi->veb) {
10386 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10388 PMD_INIT_LOG(WARNING,
10389 "Failed configuring TC for VEB seid=%d",
10390 main_vsi->veb->seid);
10392 /* Update each VSI */
10393 i40e_vsi_config_tc(main_vsi, tc_map);
10394 if (main_vsi->veb) {
10395 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10396 /* Beside main VSI and VMDQ VSIs, only enable default
10397 * TC for other VSIs
10399 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10400 ret = i40e_vsi_config_tc(vsi_list->vsi,
10403 ret = i40e_vsi_config_tc(vsi_list->vsi,
10404 I40E_DEFAULT_TCMAP);
10406 PMD_INIT_LOG(WARNING,
10407 "Failed configuring TC for VSI seid=%d",
10408 vsi_list->vsi->seid);
10412 return I40E_SUCCESS;
10416 * i40e_dcb_init_configure - initial dcb config
10417 * @dev: device being configured
10418 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10420 * Returns 0 on success, negative value on failure
10423 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10425 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10426 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10429 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10430 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10434 /* DCB initialization:
10435 * Update DCB configuration from the Firmware and configure
10436 * LLDP MIB change event.
10438 if (sw_dcb == TRUE) {
10439 ret = i40e_init_dcb(hw);
10440 /* If lldp agent is stopped, the return value from
10441 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10442 * adminq status. Otherwise, it should return success.
10444 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10445 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10446 memset(&hw->local_dcbx_config, 0,
10447 sizeof(struct i40e_dcbx_config));
10448 /* set dcb default configuration */
10449 hw->local_dcbx_config.etscfg.willing = 0;
10450 hw->local_dcbx_config.etscfg.maxtcs = 0;
10451 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10452 hw->local_dcbx_config.etscfg.tsatable[0] =
10454 /* all UPs mapping to TC0 */
10455 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10456 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10457 hw->local_dcbx_config.etsrec =
10458 hw->local_dcbx_config.etscfg;
10459 hw->local_dcbx_config.pfc.willing = 0;
10460 hw->local_dcbx_config.pfc.pfccap =
10461 I40E_MAX_TRAFFIC_CLASS;
10462 /* FW needs one App to configure HW */
10463 hw->local_dcbx_config.numapps = 1;
10464 hw->local_dcbx_config.app[0].selector =
10465 I40E_APP_SEL_ETHTYPE;
10466 hw->local_dcbx_config.app[0].priority = 3;
10467 hw->local_dcbx_config.app[0].protocolid =
10468 I40E_APP_PROTOID_FCOE;
10469 ret = i40e_set_dcb_config(hw);
10472 "default dcb config fails. err = %d, aq_err = %d.",
10473 ret, hw->aq.asq_last_status);
10478 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10479 ret, hw->aq.asq_last_status);
10483 ret = i40e_aq_start_lldp(hw, NULL);
10484 if (ret != I40E_SUCCESS)
10485 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10487 ret = i40e_init_dcb(hw);
10489 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10491 "HW doesn't support DCBX offload.");
10496 "DCBX configuration failed, err = %d, aq_err = %d.",
10497 ret, hw->aq.asq_last_status);
10505 * i40e_dcb_setup - setup dcb related config
10506 * @dev: device being configured
10508 * Returns 0 on success, negative value on failure
10511 i40e_dcb_setup(struct rte_eth_dev *dev)
10513 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10514 struct i40e_dcbx_config dcb_cfg;
10515 uint8_t tc_map = 0;
10518 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10519 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10523 if (pf->vf_num != 0)
10524 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10526 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10528 PMD_INIT_LOG(ERR, "invalid dcb config");
10531 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10533 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10541 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10542 struct rte_eth_dcb_info *dcb_info)
10544 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10545 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10546 struct i40e_vsi *vsi = pf->main_vsi;
10547 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10548 uint16_t bsf, tc_mapping;
10551 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10552 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10554 dcb_info->nb_tcs = 1;
10555 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10556 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10557 for (i = 0; i < dcb_info->nb_tcs; i++)
10558 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10560 /* get queue mapping if vmdq is disabled */
10561 if (!pf->nb_cfg_vmdq_vsi) {
10562 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10563 if (!(vsi->enabled_tc & (1 << i)))
10565 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10566 dcb_info->tc_queue.tc_rxq[j][i].base =
10567 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10568 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10569 dcb_info->tc_queue.tc_txq[j][i].base =
10570 dcb_info->tc_queue.tc_rxq[j][i].base;
10571 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10572 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10573 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10574 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10575 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10580 /* get queue mapping if vmdq is enabled */
10582 vsi = pf->vmdq[j].vsi;
10583 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10584 if (!(vsi->enabled_tc & (1 << i)))
10586 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10587 dcb_info->tc_queue.tc_rxq[j][i].base =
10588 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10589 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10590 dcb_info->tc_queue.tc_txq[j][i].base =
10591 dcb_info->tc_queue.tc_rxq[j][i].base;
10592 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10593 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10594 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10595 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10596 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10599 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10604 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10606 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10607 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10608 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10609 uint16_t interval =
10610 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10611 uint16_t msix_intr;
10613 msix_intr = intr_handle->intr_vec[queue_id];
10614 if (msix_intr == I40E_MISC_VEC_ID)
10615 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10616 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10617 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10618 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10620 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10623 I40E_PFINT_DYN_CTLN(msix_intr -
10624 I40E_RX_VEC_START),
10625 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10626 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10627 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10629 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10631 I40E_WRITE_FLUSH(hw);
10632 rte_intr_enable(&pci_dev->intr_handle);
10638 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10640 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10641 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10642 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10643 uint16_t msix_intr;
10645 msix_intr = intr_handle->intr_vec[queue_id];
10646 if (msix_intr == I40E_MISC_VEC_ID)
10647 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10650 I40E_PFINT_DYN_CTLN(msix_intr -
10651 I40E_RX_VEC_START),
10653 I40E_WRITE_FLUSH(hw);
10658 static int i40e_get_regs(struct rte_eth_dev *dev,
10659 struct rte_dev_reg_info *regs)
10661 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10662 uint32_t *ptr_data = regs->data;
10663 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10664 const struct i40e_reg_info *reg_info;
10666 if (ptr_data == NULL) {
10667 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10668 regs->width = sizeof(uint32_t);
10672 /* The first few registers have to be read using AQ operations */
10674 while (i40e_regs_adminq[reg_idx].name) {
10675 reg_info = &i40e_regs_adminq[reg_idx++];
10676 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10678 arr_idx2 <= reg_info->count2;
10680 reg_offset = arr_idx * reg_info->stride1 +
10681 arr_idx2 * reg_info->stride2;
10682 reg_offset += reg_info->base_addr;
10683 ptr_data[reg_offset >> 2] =
10684 i40e_read_rx_ctl(hw, reg_offset);
10688 /* The remaining registers can be read using primitives */
10690 while (i40e_regs_others[reg_idx].name) {
10691 reg_info = &i40e_regs_others[reg_idx++];
10692 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10694 arr_idx2 <= reg_info->count2;
10696 reg_offset = arr_idx * reg_info->stride1 +
10697 arr_idx2 * reg_info->stride2;
10698 reg_offset += reg_info->base_addr;
10699 ptr_data[reg_offset >> 2] =
10700 I40E_READ_REG(hw, reg_offset);
10707 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10709 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10711 /* Convert word count to byte count */
10712 return hw->nvm.sr_size << 1;
10715 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10716 struct rte_dev_eeprom_info *eeprom)
10718 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10719 uint16_t *data = eeprom->data;
10720 uint16_t offset, length, cnt_words;
10723 offset = eeprom->offset >> 1;
10724 length = eeprom->length >> 1;
10725 cnt_words = length;
10727 if (offset > hw->nvm.sr_size ||
10728 offset + length > hw->nvm.sr_size) {
10729 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10733 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10735 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10736 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10737 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10744 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10745 struct ether_addr *mac_addr)
10747 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10749 if (!is_valid_assigned_ether_addr(mac_addr)) {
10750 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10754 /* Flags: 0x3 updates port address */
10755 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10759 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10761 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10762 struct rte_eth_dev_data *dev_data = pf->dev_data;
10763 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10766 /* check if mtu is within the allowed range */
10767 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10770 /* mtu setting is forbidden if port is start */
10771 if (dev_data->dev_started) {
10772 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10773 dev_data->port_id);
10777 if (frame_size > ETHER_MAX_LEN)
10778 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10780 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10782 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10787 /* Restore ethertype filter */
10789 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10791 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10792 struct i40e_ethertype_filter_list
10793 *ethertype_list = &pf->ethertype.ethertype_list;
10794 struct i40e_ethertype_filter *f;
10795 struct i40e_control_filter_stats stats;
10798 TAILQ_FOREACH(f, ethertype_list, rules) {
10800 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10801 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10802 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10803 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10804 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10806 memset(&stats, 0, sizeof(stats));
10807 i40e_aq_add_rem_control_packet_filter(hw,
10808 f->input.mac_addr.addr_bytes,
10809 f->input.ether_type,
10810 flags, pf->main_vsi->seid,
10811 f->queue, 1, &stats, NULL);
10813 PMD_DRV_LOG(INFO, "Ethertype filter:"
10814 " mac_etype_used = %u, etype_used = %u,"
10815 " mac_etype_free = %u, etype_free = %u",
10816 stats.mac_etype_used, stats.etype_used,
10817 stats.mac_etype_free, stats.etype_free);
10820 /* Restore tunnel filter */
10822 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10824 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10825 struct i40e_vsi *vsi;
10826 struct i40e_pf_vf *vf;
10827 struct i40e_tunnel_filter_list
10828 *tunnel_list = &pf->tunnel.tunnel_list;
10829 struct i40e_tunnel_filter *f;
10830 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10831 bool big_buffer = 0;
10833 TAILQ_FOREACH(f, tunnel_list, rules) {
10835 vsi = pf->main_vsi;
10837 vf = &pf->vfs[f->vf_id];
10840 memset(&cld_filter, 0, sizeof(cld_filter));
10841 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10842 (struct ether_addr *)&cld_filter.element.outer_mac);
10843 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10844 (struct ether_addr *)&cld_filter.element.inner_mac);
10845 cld_filter.element.inner_vlan = f->input.inner_vlan;
10846 cld_filter.element.flags = f->input.flags;
10847 cld_filter.element.tenant_id = f->input.tenant_id;
10848 cld_filter.element.queue_number = f->queue;
10849 rte_memcpy(cld_filter.general_fields,
10850 f->input.general_fields,
10851 sizeof(f->input.general_fields));
10853 if (((f->input.flags &
10854 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10855 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10857 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10858 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10860 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10861 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10865 i40e_aq_add_cloud_filters_big_buffer(hw,
10866 vsi->seid, &cld_filter, 1);
10868 i40e_aq_add_cloud_filters(hw, vsi->seid,
10869 &cld_filter.element, 1);
10874 i40e_filter_restore(struct i40e_pf *pf)
10876 i40e_ethertype_filter_restore(pf);
10877 i40e_tunnel_filter_restore(pf);
10878 i40e_fdir_filter_restore(pf);
10882 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10884 if (strcmp(dev->device->driver->name, drv->driver.name))
10891 is_i40e_supported(struct rte_eth_dev *dev)
10893 return is_device_supported(dev, &rte_i40e_pmd);
10896 /* Create a QinQ cloud filter
10898 * The Fortville NIC has limited resources for tunnel filters,
10899 * so we can only reuse existing filters.
10901 * In step 1 we define which Field Vector fields can be used for
10903 * As we do not have the inner tag defined as a field,
10904 * we have to define it first, by reusing one of L1 entries.
10906 * In step 2 we are replacing one of existing filter types with
10907 * a new one for QinQ.
10908 * As we reusing L1 and replacing L2, some of the default filter
10909 * types will disappear,which depends on L1 and L2 entries we reuse.
10911 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10913 * 1. Create L1 filter of outer vlan (12b) which will be in use
10914 * later when we define the cloud filter.
10915 * a. Valid_flags.replace_cloud = 0
10916 * b. Old_filter = 10 (Stag_Inner_Vlan)
10917 * c. New_filter = 0x10
10918 * d. TR bit = 0xff (optional, not used here)
10919 * e. Buffer – 2 entries:
10920 * i. Byte 0 = 8 (outer vlan FV index).
10922 * Byte 2-3 = 0x0fff
10923 * ii. Byte 0 = 37 (inner vlan FV index).
10925 * Byte 2-3 = 0x0fff
10928 * 2. Create cloud filter using two L1 filters entries: stag and
10929 * new filter(outer vlan+ inner vlan)
10930 * a. Valid_flags.replace_cloud = 1
10931 * b. Old_filter = 1 (instead of outer IP)
10932 * c. New_filter = 0x10
10933 * d. Buffer – 2 entries:
10934 * i. Byte 0 = 0x80 | 7 (valid | Stag).
10935 * Byte 1-3 = 0 (rsv)
10936 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10937 * Byte 9-11 = 0 (rsv)
10940 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10942 int ret = -ENOTSUP;
10943 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
10944 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
10945 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10948 memset(&filter_replace, 0,
10949 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10950 memset(&filter_replace_buf, 0,
10951 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10953 /* create L1 filter */
10954 filter_replace.old_filter_type =
10955 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10956 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10957 filter_replace.tr_bit = 0;
10959 /* Prepare the buffer, 2 entries */
10960 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10961 filter_replace_buf.data[0] |=
10962 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10963 /* Field Vector 12b mask */
10964 filter_replace_buf.data[2] = 0xff;
10965 filter_replace_buf.data[3] = 0x0f;
10966 filter_replace_buf.data[4] =
10967 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10968 filter_replace_buf.data[4] |=
10969 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10970 /* Field Vector 12b mask */
10971 filter_replace_buf.data[6] = 0xff;
10972 filter_replace_buf.data[7] = 0x0f;
10973 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10974 &filter_replace_buf);
10975 if (ret != I40E_SUCCESS)
10978 /* Apply the second L2 cloud filter */
10979 memset(&filter_replace, 0,
10980 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10981 memset(&filter_replace_buf, 0,
10982 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10984 /* create L2 filter, input for L2 filter will be L1 filter */
10985 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10986 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10987 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10989 /* Prepare the buffer, 2 entries */
10990 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10991 filter_replace_buf.data[0] |=
10992 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10993 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10994 filter_replace_buf.data[4] |=
10995 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10996 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10997 &filter_replace_buf);
11001 RTE_INIT(i40e_init_log);
11003 i40e_init_log(void)
11005 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11006 if (i40e_logtype_init >= 0)
11007 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11008 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11009 if (i40e_logtype_driver >= 0)
11010 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);