4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_adminq_cmd.h"
57 #include "base/i40e_type.h"
58 #include "base/i40e_register.h"
59 #include "base/i40e_dcb.h"
60 #include "i40e_ethdev.h"
61 #include "i40e_rxtx.h"
64 /* Maximun number of MAC addresses */
65 #define I40E_NUM_MACADDR_MAX 64
66 #define I40E_CLEAR_PXE_WAIT_MS 200
68 /* Maximun number of capability elements */
69 #define I40E_MAX_CAP_ELE_NUM 128
71 /* Wait count and inteval */
72 #define I40E_CHK_Q_ENA_COUNT 1000
73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
75 /* Maximun number of VSI */
76 #define I40E_MAX_NUM_VSIS (384UL)
78 /* Default queue interrupt throttling time in microseconds */
79 #define I40E_ITR_INDEX_DEFAULT 0
80 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
81 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_MAX_PERCENT 100
139 #define I40E_DEFAULT_DCB_APP_NUM 1
140 #define I40E_DEFAULT_DCB_APP_PRIO 3
142 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
143 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
144 static int i40e_dev_configure(struct rte_eth_dev *dev);
145 static int i40e_dev_start(struct rte_eth_dev *dev);
146 static void i40e_dev_stop(struct rte_eth_dev *dev);
147 static void i40e_dev_close(struct rte_eth_dev *dev);
148 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
149 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
150 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
151 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
152 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
153 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
154 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
155 struct rte_eth_stats *stats);
156 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
157 struct rte_eth_xstats *xstats, unsigned n);
158 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
159 static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
160 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
164 static void i40e_dev_info_get(struct rte_eth_dev *dev,
165 struct rte_eth_dev_info *dev_info);
166 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
169 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
170 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
171 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
174 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
175 static int i40e_dev_led_on(struct rte_eth_dev *dev);
176 static int i40e_dev_led_off(struct rte_eth_dev *dev);
177 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
178 struct rte_eth_fc_conf *fc_conf);
179 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
180 struct rte_eth_fc_conf *fc_conf);
181 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
182 struct rte_eth_pfc_conf *pfc_conf);
183 static void i40e_macaddr_add(struct rte_eth_dev *dev,
184 struct ether_addr *mac_addr,
187 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
188 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
189 struct rte_eth_rss_reta_entry64 *reta_conf,
191 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
192 struct rte_eth_rss_reta_entry64 *reta_conf,
195 static int i40e_get_cap(struct i40e_hw *hw);
196 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
197 static int i40e_pf_setup(struct i40e_pf *pf);
198 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
199 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
200 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
201 static int i40e_dcb_setup(struct rte_eth_dev *dev);
202 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
203 bool offset_loaded, uint64_t *offset, uint64_t *stat);
204 static void i40e_stat_update_48(struct i40e_hw *hw,
210 static void i40e_pf_config_irq0(struct i40e_hw *hw);
211 static void i40e_dev_interrupt_handler(
212 __rte_unused struct rte_intr_handle *handle, void *param);
213 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
214 uint32_t base, uint32_t num);
215 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
216 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
218 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
220 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
221 static int i40e_veb_release(struct i40e_veb *veb);
222 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
223 struct i40e_vsi *vsi);
224 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
225 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
226 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
227 struct i40e_macvlan_filter *mv_f,
229 struct ether_addr *addr);
230 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
231 struct i40e_macvlan_filter *mv_f,
234 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
235 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
236 struct rte_eth_rss_conf *rss_conf);
237 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
238 struct rte_eth_rss_conf *rss_conf);
239 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
240 struct rte_eth_udp_tunnel *udp_tunnel);
241 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
242 struct rte_eth_udp_tunnel *udp_tunnel);
243 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
244 struct rte_eth_ethertype_filter *filter,
246 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
247 enum rte_filter_op filter_op,
249 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
250 enum rte_filter_type filter_type,
251 enum rte_filter_op filter_op,
253 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
254 struct rte_eth_dcb_info *dcb_info);
255 static void i40e_configure_registers(struct i40e_hw *hw);
256 static void i40e_hw_init(struct i40e_hw *hw);
257 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
258 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
259 struct rte_eth_mirror_conf *mirror_conf,
260 uint8_t sw_id, uint8_t on);
261 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
263 static int i40e_timesync_enable(struct rte_eth_dev *dev);
264 static int i40e_timesync_disable(struct rte_eth_dev *dev);
265 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
266 struct timespec *timestamp,
268 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
269 struct timespec *timestamp);
270 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
273 static const struct rte_pci_id pci_id_i40e_map[] = {
274 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
275 #include "rte_pci_dev_ids.h"
276 { .vendor_id = 0, /* sentinel */ },
279 static const struct eth_dev_ops i40e_eth_dev_ops = {
280 .dev_configure = i40e_dev_configure,
281 .dev_start = i40e_dev_start,
282 .dev_stop = i40e_dev_stop,
283 .dev_close = i40e_dev_close,
284 .promiscuous_enable = i40e_dev_promiscuous_enable,
285 .promiscuous_disable = i40e_dev_promiscuous_disable,
286 .allmulticast_enable = i40e_dev_allmulticast_enable,
287 .allmulticast_disable = i40e_dev_allmulticast_disable,
288 .dev_set_link_up = i40e_dev_set_link_up,
289 .dev_set_link_down = i40e_dev_set_link_down,
290 .link_update = i40e_dev_link_update,
291 .stats_get = i40e_dev_stats_get,
292 .xstats_get = i40e_dev_xstats_get,
293 .stats_reset = i40e_dev_stats_reset,
294 .xstats_reset = i40e_dev_xstats_reset,
295 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
296 .dev_infos_get = i40e_dev_info_get,
297 .vlan_filter_set = i40e_vlan_filter_set,
298 .vlan_tpid_set = i40e_vlan_tpid_set,
299 .vlan_offload_set = i40e_vlan_offload_set,
300 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
301 .vlan_pvid_set = i40e_vlan_pvid_set,
302 .rx_queue_start = i40e_dev_rx_queue_start,
303 .rx_queue_stop = i40e_dev_rx_queue_stop,
304 .tx_queue_start = i40e_dev_tx_queue_start,
305 .tx_queue_stop = i40e_dev_tx_queue_stop,
306 .rx_queue_setup = i40e_dev_rx_queue_setup,
307 .rx_queue_release = i40e_dev_rx_queue_release,
308 .rx_queue_count = i40e_dev_rx_queue_count,
309 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
310 .tx_queue_setup = i40e_dev_tx_queue_setup,
311 .tx_queue_release = i40e_dev_tx_queue_release,
312 .dev_led_on = i40e_dev_led_on,
313 .dev_led_off = i40e_dev_led_off,
314 .flow_ctrl_get = i40e_flow_ctrl_get,
315 .flow_ctrl_set = i40e_flow_ctrl_set,
316 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
317 .mac_addr_add = i40e_macaddr_add,
318 .mac_addr_remove = i40e_macaddr_remove,
319 .reta_update = i40e_dev_rss_reta_update,
320 .reta_query = i40e_dev_rss_reta_query,
321 .rss_hash_update = i40e_dev_rss_hash_update,
322 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
323 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
324 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
325 .filter_ctrl = i40e_dev_filter_ctrl,
326 .rxq_info_get = i40e_rxq_info_get,
327 .txq_info_get = i40e_txq_info_get,
328 .mirror_rule_set = i40e_mirror_rule_set,
329 .mirror_rule_reset = i40e_mirror_rule_reset,
330 .timesync_enable = i40e_timesync_enable,
331 .timesync_disable = i40e_timesync_disable,
332 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
333 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
334 .get_dcb_info = i40e_dev_get_dcb_info,
337 /* store statistics names and its offset in stats structure */
338 struct rte_i40e_xstats_name_off {
339 char name[RTE_ETH_XSTATS_NAME_SIZE];
343 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
344 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
345 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
346 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
347 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
348 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
349 rx_unknown_protocol)},
350 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
351 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
352 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
353 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
356 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
357 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
358 tx_dropped_link_down)},
359 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
360 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
362 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
363 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
365 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
367 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
369 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
370 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
371 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
372 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
373 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
374 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
376 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
378 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
380 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
382 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
384 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
386 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
388 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
390 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
391 mac_short_packet_dropped)},
392 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
394 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
395 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
396 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
398 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
400 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
402 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
404 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
406 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
408 {"rx_flow_director_atr_match_packets",
409 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
410 {"rx_flow_director_sb_match_packets",
411 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
412 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
414 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
416 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
418 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
422 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
423 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
425 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
426 sizeof(rte_i40e_stats_strings[0]))
427 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
428 sizeof(rte_i40e_hw_port_strings[0]))
429 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
430 I40E_NB_HW_PORT_Q_STATS)
432 static struct eth_driver rte_i40e_pmd = {
434 .name = "rte_i40e_pmd",
435 .id_table = pci_id_i40e_map,
436 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
437 RTE_PCI_DRV_DETACHABLE,
439 .eth_dev_init = eth_i40e_dev_init,
440 .eth_dev_uninit = eth_i40e_dev_uninit,
441 .dev_private_size = sizeof(struct i40e_adapter),
445 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
446 struct rte_eth_link *link)
448 struct rte_eth_link *dst = link;
449 struct rte_eth_link *src = &(dev->data->dev_link);
451 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
452 *(uint64_t *)src) == 0)
459 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
460 struct rte_eth_link *link)
462 struct rte_eth_link *dst = &(dev->data->dev_link);
463 struct rte_eth_link *src = link;
465 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
466 *(uint64_t *)src) == 0)
473 * Driver initialization routine.
474 * Invoked once at EAL init time.
475 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
478 rte_i40e_pmd_init(const char *name __rte_unused,
479 const char *params __rte_unused)
481 PMD_INIT_FUNC_TRACE();
482 rte_eth_driver_register(&rte_i40e_pmd);
487 static struct rte_driver rte_i40e_driver = {
489 .init = rte_i40e_pmd_init,
492 PMD_REGISTER_DRIVER(rte_i40e_driver);
495 * Initialize registers for flexible payload, which should be set by NVM.
496 * This should be removed from code once it is fixed in NVM.
498 #ifndef I40E_GLQF_ORT
499 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
501 #ifndef I40E_GLQF_PIT
502 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
505 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
507 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
508 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
509 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
510 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
511 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
512 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
513 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
514 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
515 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
516 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
518 /* GLQF_PIT Registers */
519 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
520 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
523 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
526 * Add a ethertype filter to drop all flow control frames transmitted
530 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
532 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
533 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
534 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
535 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
538 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
539 I40E_FLOW_CONTROL_ETHERTYPE, flags,
540 pf->main_vsi_seid, 0,
543 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
544 " frames from VSIs.");
548 eth_i40e_dev_init(struct rte_eth_dev *dev)
550 struct rte_pci_device *pci_dev;
551 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
552 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
553 struct i40e_vsi *vsi;
558 PMD_INIT_FUNC_TRACE();
560 dev->dev_ops = &i40e_eth_dev_ops;
561 dev->rx_pkt_burst = i40e_recv_pkts;
562 dev->tx_pkt_burst = i40e_xmit_pkts;
564 /* for secondary processes, we don't initialise any further as primary
565 * has already done this work. Only check we don't need a different
567 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
568 i40e_set_rx_function(dev);
569 i40e_set_tx_function(dev);
572 pci_dev = dev->pci_dev;
573 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
574 pf->adapter->eth_dev = dev;
575 pf->dev_data = dev->data;
577 hw->back = I40E_PF_TO_ADAPTER(pf);
578 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
580 PMD_INIT_LOG(ERR, "Hardware is not available, "
581 "as address is NULL");
585 hw->vendor_id = pci_dev->id.vendor_id;
586 hw->device_id = pci_dev->id.device_id;
587 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
588 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
589 hw->bus.device = pci_dev->addr.devid;
590 hw->bus.func = pci_dev->addr.function;
591 hw->adapter_stopped = 0;
593 /* Make sure all is clean before doing PF reset */
596 /* Initialize the hardware */
599 /* Reset here to make sure all is clean for each PF */
600 ret = i40e_pf_reset(hw);
602 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
606 /* Initialize the shared code (base driver) */
607 ret = i40e_init_shared_code(hw);
609 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
614 * To work around the NVM issue,initialize registers
615 * for flexible payload by software.
616 * It should be removed once issues are fixed in NVM.
618 i40e_flex_payload_reg_init(hw);
620 /* Initialize the parameters for adminq */
621 i40e_init_adminq_parameter(hw);
622 ret = i40e_init_adminq(hw);
623 if (ret != I40E_SUCCESS) {
624 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
627 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
628 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
629 hw->aq.api_maj_ver, hw->aq.api_min_ver,
630 ((hw->nvm.version >> 12) & 0xf),
631 ((hw->nvm.version >> 4) & 0xff),
632 (hw->nvm.version & 0xf), hw->nvm.eetrack);
635 i40e_clear_pxe_mode(hw);
638 * On X710, performance number is far from the expectation on recent
639 * firmware versions. The fix for this issue may not be integrated in
640 * the following firmware version. So the workaround in software driver
641 * is needed. It needs to modify the initial values of 3 internal only
642 * registers. Note that the workaround can be removed when it is fixed
643 * in firmware in the future.
645 i40e_configure_registers(hw);
647 /* Get hw capabilities */
648 ret = i40e_get_cap(hw);
649 if (ret != I40E_SUCCESS) {
650 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
651 goto err_get_capabilities;
654 /* Initialize parameters for PF */
655 ret = i40e_pf_parameter_init(dev);
657 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
658 goto err_parameter_init;
661 /* Initialize the queue management */
662 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
664 PMD_INIT_LOG(ERR, "Failed to init queue pool");
665 goto err_qp_pool_init;
667 ret = i40e_res_pool_init(&pf->msix_pool, 1,
668 hw->func_caps.num_msix_vectors - 1);
670 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
671 goto err_msix_pool_init;
674 /* Initialize lan hmc */
675 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
676 hw->func_caps.num_rx_qp, 0, 0);
677 if (ret != I40E_SUCCESS) {
678 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
679 goto err_init_lan_hmc;
682 /* Configure lan hmc */
683 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
684 if (ret != I40E_SUCCESS) {
685 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
686 goto err_configure_lan_hmc;
689 /* Get and check the mac address */
690 i40e_get_mac_addr(hw, hw->mac.addr);
691 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
692 PMD_INIT_LOG(ERR, "mac address is not valid");
694 goto err_get_mac_addr;
696 /* Copy the permanent MAC address */
697 ether_addr_copy((struct ether_addr *) hw->mac.addr,
698 (struct ether_addr *) hw->mac.perm_addr);
700 /* Disable flow control */
701 hw->fc.requested_mode = I40E_FC_NONE;
702 i40e_set_fc(hw, &aq_fail, TRUE);
704 /* PF setup, which includes VSI setup */
705 ret = i40e_pf_setup(pf);
707 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
708 goto err_setup_pf_switch;
713 /* Disable double vlan by default */
714 i40e_vsi_config_double_vlan(vsi, FALSE);
716 if (!vsi->max_macaddrs)
717 len = ETHER_ADDR_LEN;
719 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
721 /* Should be after VSI initialized */
722 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
723 if (!dev->data->mac_addrs) {
724 PMD_INIT_LOG(ERR, "Failed to allocated memory "
725 "for storing mac address");
728 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
729 &dev->data->mac_addrs[0]);
731 /* initialize pf host driver to setup SRIOV resource if applicable */
732 i40e_pf_host_init(dev);
734 /* register callback func to eal lib */
735 rte_intr_callback_register(&(pci_dev->intr_handle),
736 i40e_dev_interrupt_handler, (void *)dev);
738 /* configure and enable device interrupt */
739 i40e_pf_config_irq0(hw);
740 i40e_pf_enable_irq0(hw);
742 /* enable uio intr after callback register */
743 rte_intr_enable(&(pci_dev->intr_handle));
745 * Add an ethertype filter to drop all flow control frames transmitted
746 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
749 i40e_add_tx_flow_control_drop_filter(pf);
751 /* initialize mirror rule list */
752 TAILQ_INIT(&pf->mirror_list);
754 /* Init dcb to sw mode by default */
755 ret = i40e_dcb_init_configure(dev, TRUE);
756 if (ret != I40E_SUCCESS) {
757 PMD_INIT_LOG(INFO, "Failed to init dcb.");
758 pf->flags &= ~I40E_FLAG_DCB;
764 i40e_vsi_release(pf->main_vsi);
767 err_configure_lan_hmc:
768 (void)i40e_shutdown_lan_hmc(hw);
770 i40e_res_pool_destroy(&pf->msix_pool);
772 i40e_res_pool_destroy(&pf->qp_pool);
775 err_get_capabilities:
776 (void)i40e_shutdown_adminq(hw);
782 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
784 struct rte_pci_device *pci_dev;
786 struct i40e_filter_control_settings settings;
790 PMD_INIT_FUNC_TRACE();
792 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
795 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
796 pci_dev = dev->pci_dev;
798 if (hw->adapter_stopped == 0)
802 dev->rx_pkt_burst = NULL;
803 dev->tx_pkt_burst = NULL;
806 ret = i40e_aq_stop_lldp(hw, true, NULL);
807 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
808 PMD_INIT_LOG(INFO, "Failed to stop lldp");
811 i40e_clear_pxe_mode(hw);
813 /* Unconfigure filter control */
814 memset(&settings, 0, sizeof(settings));
815 ret = i40e_set_filter_control(hw, &settings);
817 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
820 /* Disable flow control */
821 hw->fc.requested_mode = I40E_FC_NONE;
822 i40e_set_fc(hw, &aq_fail, TRUE);
824 /* uninitialize pf host driver */
825 i40e_pf_host_uninit(dev);
827 rte_free(dev->data->mac_addrs);
828 dev->data->mac_addrs = NULL;
830 /* disable uio intr before callback unregister */
831 rte_intr_disable(&(pci_dev->intr_handle));
833 /* register callback func to eal lib */
834 rte_intr_callback_unregister(&(pci_dev->intr_handle),
835 i40e_dev_interrupt_handler, (void *)dev);
841 i40e_dev_configure(struct rte_eth_dev *dev)
843 struct i40e_adapter *ad =
844 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
845 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
846 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
849 /* Initialize to TRUE. If any of Rx queues doesn't meet the
850 * bulk allocation or vector Rx preconditions we will reset it.
852 ad->rx_bulk_alloc_allowed = true;
853 ad->rx_vec_allowed = true;
854 ad->tx_simple_allowed = true;
855 ad->tx_vec_allowed = true;
857 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
858 ret = i40e_fdir_setup(pf);
859 if (ret != I40E_SUCCESS) {
860 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
863 ret = i40e_fdir_configure(dev);
865 PMD_DRV_LOG(ERR, "failed to configure fdir.");
869 i40e_fdir_teardown(pf);
871 ret = i40e_dev_init_vlan(dev);
876 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
877 * RSS setting have different requirements.
878 * General PMD driver call sequence are NIC init, configure,
879 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
880 * will try to lookup the VSI that specific queue belongs to if VMDQ
881 * applicable. So, VMDQ setting has to be done before
882 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
883 * For RSS setting, it will try to calculate actual configured RX queue
884 * number, which will be available after rx_queue_setup(). dev_start()
885 * function is good to place RSS setup.
887 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
888 ret = i40e_vmdq_setup(dev);
893 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
894 ret = i40e_dcb_setup(dev);
896 PMD_DRV_LOG(ERR, "failed to configure DCB.");
904 /* need to release vmdq resource if exists */
905 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
906 i40e_vsi_release(pf->vmdq[i].vsi);
907 pf->vmdq[i].vsi = NULL;
912 /* need to release fdir resource if exists */
913 i40e_fdir_teardown(pf);
918 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
920 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
921 uint16_t msix_vect = vsi->msix_intr;
924 for (i = 0; i < vsi->nb_qps; i++) {
925 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
926 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
930 if (vsi->type != I40E_VSI_SRIOV) {
931 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
932 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
936 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
937 vsi->user_param + (msix_vect - 1);
939 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
941 I40E_WRITE_FLUSH(hw);
944 static inline uint16_t
945 i40e_calc_itr_interval(int16_t interval)
947 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
948 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
950 /* Convert to hardware count, as writing each 1 represents 2 us */
955 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
958 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
959 uint16_t msix_vect = vsi->msix_intr;
962 for (i = 0; i < vsi->nb_qps; i++)
963 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
965 /* Bind all RX queues to allocated MSIX interrupt */
966 for (i = 0; i < vsi->nb_qps; i++) {
967 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
968 I40E_QINT_RQCTL_ITR_INDX_MASK |
969 ((vsi->base_queue + i + 1) <<
970 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
971 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
972 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
974 if (i == vsi->nb_qps - 1)
975 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
976 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
979 /* Write first RX queue to Link list register as the head element */
980 if (vsi->type != I40E_VSI_SRIOV) {
982 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
984 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
986 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
987 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
989 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
990 msix_vect - 1), interval);
992 #ifndef I40E_GLINT_CTL
993 #define I40E_GLINT_CTL 0x0003F800
994 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
996 /* Disable auto-mask on enabling of all none-zero interrupt */
997 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
998 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
1002 /* num_msix_vectors_vf needs to minus irq0 */
1003 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1004 vsi->user_param + (msix_vect - 1);
1006 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
1007 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1008 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1011 I40E_WRITE_FLUSH(hw);
1015 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1017 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1018 uint16_t interval = i40e_calc_itr_interval(\
1019 RTE_LIBRTE_I40E_ITR_INTERVAL);
1021 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
1022 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1023 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1024 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1025 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1029 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1031 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1033 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
1036 static inline uint8_t
1037 i40e_parse_link_speed(uint16_t eth_link_speed)
1039 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1041 switch (eth_link_speed) {
1042 case ETH_LINK_SPEED_40G:
1043 link_speed = I40E_LINK_SPEED_40GB;
1045 case ETH_LINK_SPEED_20G:
1046 link_speed = I40E_LINK_SPEED_20GB;
1048 case ETH_LINK_SPEED_10G:
1049 link_speed = I40E_LINK_SPEED_10GB;
1051 case ETH_LINK_SPEED_1000:
1052 link_speed = I40E_LINK_SPEED_1GB;
1054 case ETH_LINK_SPEED_100:
1055 link_speed = I40E_LINK_SPEED_100MB;
1063 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1065 enum i40e_status_code status;
1066 struct i40e_aq_get_phy_abilities_resp phy_ab;
1067 struct i40e_aq_set_phy_config phy_conf;
1068 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1069 I40E_AQ_PHY_FLAG_PAUSE_RX |
1070 I40E_AQ_PHY_FLAG_LOW_POWER;
1071 const uint8_t advt = I40E_LINK_SPEED_40GB |
1072 I40E_LINK_SPEED_10GB |
1073 I40E_LINK_SPEED_1GB |
1074 I40E_LINK_SPEED_100MB;
1077 /* Skip it on 40G interfaces, as a workaround for the link issue */
1078 if (i40e_is_40G_device(hw->device_id))
1079 return I40E_SUCCESS;
1081 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1086 memset(&phy_conf, 0, sizeof(phy_conf));
1088 /* bits 0-2 use the values from get_phy_abilities_resp */
1090 abilities |= phy_ab.abilities & mask;
1092 /* update ablities and speed */
1093 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1094 phy_conf.link_speed = advt;
1096 phy_conf.link_speed = force_speed;
1098 phy_conf.abilities = abilities;
1100 /* use get_phy_abilities_resp value for the rest */
1101 phy_conf.phy_type = phy_ab.phy_type;
1102 phy_conf.eee_capability = phy_ab.eee_capability;
1103 phy_conf.eeer = phy_ab.eeer_val;
1104 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1106 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1107 phy_ab.abilities, phy_ab.link_speed);
1108 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1109 phy_conf.abilities, phy_conf.link_speed);
1111 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1115 return I40E_SUCCESS;
1119 i40e_apply_link_speed(struct rte_eth_dev *dev)
1122 uint8_t abilities = 0;
1123 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1124 struct rte_eth_conf *conf = &dev->data->dev_conf;
1126 speed = i40e_parse_link_speed(conf->link_speed);
1127 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1128 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1129 abilities |= I40E_AQ_PHY_AN_ENABLED;
1131 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1133 return i40e_phy_conf_link(hw, abilities, speed);
1137 i40e_dev_start(struct rte_eth_dev *dev)
1139 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1140 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1141 struct i40e_vsi *main_vsi = pf->main_vsi;
1144 hw->adapter_stopped = 0;
1146 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1147 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1148 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1149 dev->data->dev_conf.link_duplex,
1150 dev->data->port_id);
1154 /* Initialize VSI */
1155 ret = i40e_dev_rxtx_init(pf);
1156 if (ret != I40E_SUCCESS) {
1157 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1161 /* Map queues with MSIX interrupt */
1162 i40e_vsi_queues_bind_intr(main_vsi);
1163 i40e_vsi_enable_queues_intr(main_vsi);
1165 /* Map VMDQ VSI queues with MSIX interrupt */
1166 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1167 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1168 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1171 /* enable FDIR MSIX interrupt */
1172 if (pf->fdir.fdir_vsi) {
1173 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1174 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1177 /* Enable all queues which have been configured */
1178 ret = i40e_dev_switch_queues(pf, TRUE);
1179 if (ret != I40E_SUCCESS) {
1180 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1184 /* Enable receiving broadcast packets */
1185 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1186 if (ret != I40E_SUCCESS)
1187 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1189 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1190 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1192 if (ret != I40E_SUCCESS)
1193 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1196 /* Apply link configure */
1197 ret = i40e_apply_link_speed(dev);
1198 if (I40E_SUCCESS != ret) {
1199 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1203 return I40E_SUCCESS;
1206 i40e_dev_switch_queues(pf, FALSE);
1207 i40e_dev_clear_queues(dev);
1213 i40e_dev_stop(struct rte_eth_dev *dev)
1215 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1216 struct i40e_vsi *main_vsi = pf->main_vsi;
1217 struct i40e_mirror_rule *p_mirror;
1220 /* Disable all queues */
1221 i40e_dev_switch_queues(pf, FALSE);
1223 /* un-map queues with interrupt registers */
1224 i40e_vsi_disable_queues_intr(main_vsi);
1225 i40e_vsi_queues_unbind_intr(main_vsi);
1227 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1228 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1229 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1232 if (pf->fdir.fdir_vsi) {
1233 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1234 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1236 /* Clear all queues and release memory */
1237 i40e_dev_clear_queues(dev);
1240 i40e_dev_set_link_down(dev);
1242 /* Remove all mirror rules */
1243 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1244 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1247 pf->nb_mirror_rule = 0;
1252 i40e_dev_close(struct rte_eth_dev *dev)
1254 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1255 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1259 PMD_INIT_FUNC_TRACE();
1262 hw->adapter_stopped = 1;
1263 i40e_dev_free_queues(dev);
1265 /* Disable interrupt */
1266 i40e_pf_disable_irq0(hw);
1267 rte_intr_disable(&(dev->pci_dev->intr_handle));
1269 /* shutdown and destroy the HMC */
1270 i40e_shutdown_lan_hmc(hw);
1272 /* release all the existing VSIs and VEBs */
1273 i40e_fdir_teardown(pf);
1274 i40e_vsi_release(pf->main_vsi);
1276 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1277 i40e_vsi_release(pf->vmdq[i].vsi);
1278 pf->vmdq[i].vsi = NULL;
1284 /* shutdown the adminq */
1285 i40e_aq_queue_shutdown(hw, true);
1286 i40e_shutdown_adminq(hw);
1288 i40e_res_pool_destroy(&pf->qp_pool);
1289 i40e_res_pool_destroy(&pf->msix_pool);
1291 /* force a PF reset to clean anything leftover */
1292 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1293 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1294 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1295 I40E_WRITE_FLUSH(hw);
1299 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1301 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1302 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1303 struct i40e_vsi *vsi = pf->main_vsi;
1306 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1308 if (status != I40E_SUCCESS)
1309 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1311 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1313 if (status != I40E_SUCCESS)
1314 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1319 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1321 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1322 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1323 struct i40e_vsi *vsi = pf->main_vsi;
1326 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1328 if (status != I40E_SUCCESS)
1329 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1331 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1333 if (status != I40E_SUCCESS)
1334 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1338 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1340 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1341 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1342 struct i40e_vsi *vsi = pf->main_vsi;
1345 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1346 if (ret != I40E_SUCCESS)
1347 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1351 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1353 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1354 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1355 struct i40e_vsi *vsi = pf->main_vsi;
1358 if (dev->data->promiscuous == 1)
1359 return; /* must remain in all_multicast mode */
1361 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1362 vsi->seid, FALSE, NULL);
1363 if (ret != I40E_SUCCESS)
1364 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1368 * Set device link up.
1371 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1373 /* re-apply link speed setting */
1374 return i40e_apply_link_speed(dev);
1378 * Set device link down.
1381 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1383 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1384 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1385 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1387 return i40e_phy_conf_link(hw, abilities, speed);
1391 i40e_dev_link_update(struct rte_eth_dev *dev,
1392 int wait_to_complete)
1394 #define CHECK_INTERVAL 100 /* 100ms */
1395 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1396 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397 struct i40e_link_status link_status;
1398 struct rte_eth_link link, old;
1400 unsigned rep_cnt = MAX_REPEAT_TIME;
1402 memset(&link, 0, sizeof(link));
1403 memset(&old, 0, sizeof(old));
1404 memset(&link_status, 0, sizeof(link_status));
1405 rte_i40e_dev_atomic_read_link_status(dev, &old);
1408 /* Get link status information from hardware */
1409 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1410 if (status != I40E_SUCCESS) {
1411 link.link_speed = ETH_LINK_SPEED_100;
1412 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1413 PMD_DRV_LOG(ERR, "Failed to get link info");
1417 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1418 if (!wait_to_complete)
1421 rte_delay_ms(CHECK_INTERVAL);
1422 } while (!link.link_status && rep_cnt--);
1424 if (!link.link_status)
1427 /* i40e uses full duplex only */
1428 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1430 /* Parse the link status */
1431 switch (link_status.link_speed) {
1432 case I40E_LINK_SPEED_100MB:
1433 link.link_speed = ETH_LINK_SPEED_100;
1435 case I40E_LINK_SPEED_1GB:
1436 link.link_speed = ETH_LINK_SPEED_1000;
1438 case I40E_LINK_SPEED_10GB:
1439 link.link_speed = ETH_LINK_SPEED_10G;
1441 case I40E_LINK_SPEED_20GB:
1442 link.link_speed = ETH_LINK_SPEED_20G;
1444 case I40E_LINK_SPEED_40GB:
1445 link.link_speed = ETH_LINK_SPEED_40G;
1448 link.link_speed = ETH_LINK_SPEED_100;
1453 rte_i40e_dev_atomic_write_link_status(dev, &link);
1454 if (link.link_status == old.link_status)
1460 /* Get all the statistics of a VSI */
1462 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1464 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1465 struct i40e_eth_stats *nes = &vsi->eth_stats;
1466 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1467 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1469 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1470 vsi->offset_loaded, &oes->rx_bytes,
1472 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1473 vsi->offset_loaded, &oes->rx_unicast,
1475 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1476 vsi->offset_loaded, &oes->rx_multicast,
1477 &nes->rx_multicast);
1478 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1479 vsi->offset_loaded, &oes->rx_broadcast,
1480 &nes->rx_broadcast);
1481 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1482 &oes->rx_discards, &nes->rx_discards);
1483 /* GLV_REPC not supported */
1484 /* GLV_RMPC not supported */
1485 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1486 &oes->rx_unknown_protocol,
1487 &nes->rx_unknown_protocol);
1488 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1489 vsi->offset_loaded, &oes->tx_bytes,
1491 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1492 vsi->offset_loaded, &oes->tx_unicast,
1494 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1495 vsi->offset_loaded, &oes->tx_multicast,
1496 &nes->tx_multicast);
1497 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1498 vsi->offset_loaded, &oes->tx_broadcast,
1499 &nes->tx_broadcast);
1500 /* GLV_TDPC not supported */
1501 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1502 &oes->tx_errors, &nes->tx_errors);
1503 vsi->offset_loaded = true;
1505 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1507 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1508 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1509 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1510 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1511 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1512 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1513 nes->rx_unknown_protocol);
1514 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1515 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1516 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1517 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1518 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1519 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1520 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1525 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1528 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1529 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1530 /* Get statistics of struct i40e_eth_stats */
1531 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1532 I40E_GLPRT_GORCL(hw->port),
1533 pf->offset_loaded, &os->eth.rx_bytes,
1535 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1536 I40E_GLPRT_UPRCL(hw->port),
1537 pf->offset_loaded, &os->eth.rx_unicast,
1538 &ns->eth.rx_unicast);
1539 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1540 I40E_GLPRT_MPRCL(hw->port),
1541 pf->offset_loaded, &os->eth.rx_multicast,
1542 &ns->eth.rx_multicast);
1543 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1544 I40E_GLPRT_BPRCL(hw->port),
1545 pf->offset_loaded, &os->eth.rx_broadcast,
1546 &ns->eth.rx_broadcast);
1547 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1548 pf->offset_loaded, &os->eth.rx_discards,
1549 &ns->eth.rx_discards);
1550 /* GLPRT_REPC not supported */
1551 /* GLPRT_RMPC not supported */
1552 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1554 &os->eth.rx_unknown_protocol,
1555 &ns->eth.rx_unknown_protocol);
1556 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1557 I40E_GLPRT_GOTCL(hw->port),
1558 pf->offset_loaded, &os->eth.tx_bytes,
1560 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1561 I40E_GLPRT_UPTCL(hw->port),
1562 pf->offset_loaded, &os->eth.tx_unicast,
1563 &ns->eth.tx_unicast);
1564 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1565 I40E_GLPRT_MPTCL(hw->port),
1566 pf->offset_loaded, &os->eth.tx_multicast,
1567 &ns->eth.tx_multicast);
1568 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1569 I40E_GLPRT_BPTCL(hw->port),
1570 pf->offset_loaded, &os->eth.tx_broadcast,
1571 &ns->eth.tx_broadcast);
1572 /* GLPRT_TEPC not supported */
1574 /* additional port specific stats */
1575 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1576 pf->offset_loaded, &os->tx_dropped_link_down,
1577 &ns->tx_dropped_link_down);
1578 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1579 pf->offset_loaded, &os->crc_errors,
1581 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1582 pf->offset_loaded, &os->illegal_bytes,
1583 &ns->illegal_bytes);
1584 /* GLPRT_ERRBC not supported */
1585 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1586 pf->offset_loaded, &os->mac_local_faults,
1587 &ns->mac_local_faults);
1588 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1589 pf->offset_loaded, &os->mac_remote_faults,
1590 &ns->mac_remote_faults);
1591 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1592 pf->offset_loaded, &os->rx_length_errors,
1593 &ns->rx_length_errors);
1594 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1595 pf->offset_loaded, &os->link_xon_rx,
1597 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1598 pf->offset_loaded, &os->link_xoff_rx,
1600 for (i = 0; i < 8; i++) {
1601 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1603 &os->priority_xon_rx[i],
1604 &ns->priority_xon_rx[i]);
1605 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1607 &os->priority_xoff_rx[i],
1608 &ns->priority_xoff_rx[i]);
1610 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1611 pf->offset_loaded, &os->link_xon_tx,
1613 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1614 pf->offset_loaded, &os->link_xoff_tx,
1616 for (i = 0; i < 8; i++) {
1617 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1619 &os->priority_xon_tx[i],
1620 &ns->priority_xon_tx[i]);
1621 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1623 &os->priority_xoff_tx[i],
1624 &ns->priority_xoff_tx[i]);
1625 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1627 &os->priority_xon_2_xoff[i],
1628 &ns->priority_xon_2_xoff[i]);
1630 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1631 I40E_GLPRT_PRC64L(hw->port),
1632 pf->offset_loaded, &os->rx_size_64,
1634 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1635 I40E_GLPRT_PRC127L(hw->port),
1636 pf->offset_loaded, &os->rx_size_127,
1638 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1639 I40E_GLPRT_PRC255L(hw->port),
1640 pf->offset_loaded, &os->rx_size_255,
1642 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1643 I40E_GLPRT_PRC511L(hw->port),
1644 pf->offset_loaded, &os->rx_size_511,
1646 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1647 I40E_GLPRT_PRC1023L(hw->port),
1648 pf->offset_loaded, &os->rx_size_1023,
1650 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1651 I40E_GLPRT_PRC1522L(hw->port),
1652 pf->offset_loaded, &os->rx_size_1522,
1654 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1655 I40E_GLPRT_PRC9522L(hw->port),
1656 pf->offset_loaded, &os->rx_size_big,
1658 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1659 pf->offset_loaded, &os->rx_undersize,
1661 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1662 pf->offset_loaded, &os->rx_fragments,
1664 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1665 pf->offset_loaded, &os->rx_oversize,
1667 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1668 pf->offset_loaded, &os->rx_jabber,
1670 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1671 I40E_GLPRT_PTC64L(hw->port),
1672 pf->offset_loaded, &os->tx_size_64,
1674 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1675 I40E_GLPRT_PTC127L(hw->port),
1676 pf->offset_loaded, &os->tx_size_127,
1678 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1679 I40E_GLPRT_PTC255L(hw->port),
1680 pf->offset_loaded, &os->tx_size_255,
1682 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1683 I40E_GLPRT_PTC511L(hw->port),
1684 pf->offset_loaded, &os->tx_size_511,
1686 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1687 I40E_GLPRT_PTC1023L(hw->port),
1688 pf->offset_loaded, &os->tx_size_1023,
1690 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1691 I40E_GLPRT_PTC1522L(hw->port),
1692 pf->offset_loaded, &os->tx_size_1522,
1694 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1695 I40E_GLPRT_PTC9522L(hw->port),
1696 pf->offset_loaded, &os->tx_size_big,
1698 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1700 &os->fd_sb_match, &ns->fd_sb_match);
1701 /* GLPRT_MSPDC not supported */
1702 /* GLPRT_XEC not supported */
1704 pf->offset_loaded = true;
1707 i40e_update_vsi_stats(pf->main_vsi);
1710 /* Get all statistics of a port */
1712 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1714 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1715 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1716 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1719 /* call read registers - updates values, now write them to struct */
1720 i40e_read_stats_registers(pf, hw);
1722 stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1723 ns->eth.rx_broadcast;
1724 stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1725 ns->eth.tx_broadcast;
1726 stats->ibytes = ns->eth.rx_bytes;
1727 stats->obytes = ns->eth.tx_bytes;
1728 stats->oerrors = ns->eth.tx_errors;
1729 stats->imcasts = ns->eth.rx_multicast;
1730 stats->fdirmatch = ns->fd_sb_match;
1733 stats->ibadcrc = ns->crc_errors;
1734 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1735 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1736 stats->imissed = ns->eth.rx_discards;
1737 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1739 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1740 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
1741 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
1742 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
1743 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
1744 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
1745 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1746 ns->eth.rx_unknown_protocol);
1747 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
1748 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
1749 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
1750 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
1751 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
1752 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
1754 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
1755 ns->tx_dropped_link_down);
1756 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
1757 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
1759 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
1760 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
1761 ns->mac_local_faults);
1762 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
1763 ns->mac_remote_faults);
1764 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
1765 ns->rx_length_errors);
1766 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
1767 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
1768 for (i = 0; i < 8; i++) {
1769 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
1770 i, ns->priority_xon_rx[i]);
1771 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
1772 i, ns->priority_xoff_rx[i]);
1774 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
1775 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
1776 for (i = 0; i < 8; i++) {
1777 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
1778 i, ns->priority_xon_tx[i]);
1779 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
1780 i, ns->priority_xoff_tx[i]);
1781 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
1782 i, ns->priority_xon_2_xoff[i]);
1784 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
1785 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
1786 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
1787 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
1788 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
1789 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
1790 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
1791 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
1792 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
1793 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
1794 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
1795 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
1796 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
1797 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
1798 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
1799 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
1800 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
1801 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
1802 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1803 ns->mac_short_packet_dropped);
1804 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
1805 ns->checksum_error);
1806 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
1807 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1811 i40e_dev_xstats_reset(struct rte_eth_dev *dev)
1813 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1814 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1815 struct i40e_hw_port_stats *hw_stats = &pf->stats;
1817 /* The hw registers are cleared on read */
1818 pf->offset_loaded = false;
1819 i40e_read_stats_registers(pf, hw);
1821 /* reset software counters */
1822 memset(hw_stats, 0, sizeof(*hw_stats));
1826 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1829 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1830 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1831 unsigned i, count = 0;
1832 struct i40e_hw_port_stats *hw_stats = &pf->stats;
1834 if (n < I40E_NB_XSTATS)
1835 return I40E_NB_XSTATS;
1837 i40e_read_stats_registers(pf, hw);
1843 /* Get stats from i40e_eth_stats struct */
1844 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
1845 snprintf(xstats[count].name, sizeof(xstats[count].name),
1846 "%s", rte_i40e_stats_strings[i].name);
1847 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
1848 rte_i40e_stats_strings[i].offset);
1852 /* Get individiual stats from i40e_hw_port struct */
1853 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
1854 snprintf(xstats[count].name, sizeof(xstats[count].name),
1855 "%s", rte_i40e_hw_port_strings[i].name);
1856 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1857 rte_i40e_hw_port_strings[i].offset);
1861 /* Get per-queue stats from i40e_hw_port struct */
1862 for (i = 0; i < 8; i++) {
1863 snprintf(xstats[count].name, sizeof(xstats[count].name),
1864 "rx_q%u_xon_priority_packets", i);
1865 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1866 offsetof(struct i40e_hw_port_stats,
1867 priority_xon_rx[i]));
1870 snprintf(xstats[count].name, sizeof(xstats[count].name),
1871 "rx_q%u_xoff_priority_packets", i);
1872 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1873 offsetof(struct i40e_hw_port_stats,
1874 priority_xoff_rx[i]));
1877 snprintf(xstats[count].name, sizeof(xstats[count].name),
1878 "tx_q%u_xon_priority_packets", i);
1879 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1880 offsetof(struct i40e_hw_port_stats,
1881 priority_xon_tx[i]));
1884 snprintf(xstats[count].name, sizeof(xstats[count].name),
1885 "tx_q%u_xoff_priority_packets", i);
1886 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1887 offsetof(struct i40e_hw_port_stats,
1888 priority_xoff_tx[i]));
1891 snprintf(xstats[count].name, sizeof(xstats[count].name),
1892 "xx_q%u_xon_to_xoff_priority_packets", i);
1893 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1894 offsetof(struct i40e_hw_port_stats,
1895 priority_xon_2_xoff[i]));
1899 return I40E_NB_XSTATS;
1902 /* Reset the statistics */
1904 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1906 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908 /* It results in reloading the start point of each counter */
1909 pf->offset_loaded = false;
1913 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1914 __rte_unused uint16_t queue_id,
1915 __rte_unused uint8_t stat_idx,
1916 __rte_unused uint8_t is_rx)
1918 PMD_INIT_FUNC_TRACE();
1924 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1926 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1927 struct i40e_vsi *vsi = pf->main_vsi;
1929 dev_info->max_rx_queues = vsi->nb_qps;
1930 dev_info->max_tx_queues = vsi->nb_qps;
1931 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1932 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1933 dev_info->max_mac_addrs = vsi->max_macaddrs;
1934 dev_info->max_vfs = dev->pci_dev->max_vfs;
1935 dev_info->rx_offload_capa =
1936 DEV_RX_OFFLOAD_VLAN_STRIP |
1937 DEV_RX_OFFLOAD_QINQ_STRIP |
1938 DEV_RX_OFFLOAD_IPV4_CKSUM |
1939 DEV_RX_OFFLOAD_UDP_CKSUM |
1940 DEV_RX_OFFLOAD_TCP_CKSUM;
1941 dev_info->tx_offload_capa =
1942 DEV_TX_OFFLOAD_VLAN_INSERT |
1943 DEV_TX_OFFLOAD_QINQ_INSERT |
1944 DEV_TX_OFFLOAD_IPV4_CKSUM |
1945 DEV_TX_OFFLOAD_UDP_CKSUM |
1946 DEV_TX_OFFLOAD_TCP_CKSUM |
1947 DEV_TX_OFFLOAD_SCTP_CKSUM |
1948 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1949 DEV_TX_OFFLOAD_TCP_TSO;
1950 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1952 dev_info->reta_size = pf->hash_lut_size;
1953 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1955 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1957 .pthresh = I40E_DEFAULT_RX_PTHRESH,
1958 .hthresh = I40E_DEFAULT_RX_HTHRESH,
1959 .wthresh = I40E_DEFAULT_RX_WTHRESH,
1961 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1965 dev_info->default_txconf = (struct rte_eth_txconf) {
1967 .pthresh = I40E_DEFAULT_TX_PTHRESH,
1968 .hthresh = I40E_DEFAULT_TX_HTHRESH,
1969 .wthresh = I40E_DEFAULT_TX_WTHRESH,
1971 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1972 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1973 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1974 ETH_TXQ_FLAGS_NOOFFLOADS,
1977 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1978 .nb_max = I40E_MAX_RING_DESC,
1979 .nb_min = I40E_MIN_RING_DESC,
1980 .nb_align = I40E_ALIGN_RING_DESC,
1983 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1984 .nb_max = I40E_MAX_RING_DESC,
1985 .nb_min = I40E_MIN_RING_DESC,
1986 .nb_align = I40E_ALIGN_RING_DESC,
1989 if (pf->flags & I40E_FLAG_VMDQ) {
1990 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1991 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1992 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1993 pf->max_nb_vmdq_vsi;
1994 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1995 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1996 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2001 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2003 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2004 struct i40e_vsi *vsi = pf->main_vsi;
2005 PMD_INIT_FUNC_TRACE();
2008 return i40e_vsi_add_vlan(vsi, vlan_id);
2010 return i40e_vsi_delete_vlan(vsi, vlan_id);
2014 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2015 __rte_unused uint16_t tpid)
2017 PMD_INIT_FUNC_TRACE();
2021 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2023 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2024 struct i40e_vsi *vsi = pf->main_vsi;
2026 if (mask & ETH_VLAN_STRIP_MASK) {
2027 /* Enable or disable VLAN stripping */
2028 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2029 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2031 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2034 if (mask & ETH_VLAN_EXTEND_MASK) {
2035 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2036 i40e_vsi_config_double_vlan(vsi, TRUE);
2038 i40e_vsi_config_double_vlan(vsi, FALSE);
2043 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2044 __rte_unused uint16_t queue,
2045 __rte_unused int on)
2047 PMD_INIT_FUNC_TRACE();
2051 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2053 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054 struct i40e_vsi *vsi = pf->main_vsi;
2055 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2056 struct i40e_vsi_vlan_pvid_info info;
2058 memset(&info, 0, sizeof(info));
2061 info.config.pvid = pvid;
2063 info.config.reject.tagged =
2064 data->dev_conf.txmode.hw_vlan_reject_tagged;
2065 info.config.reject.untagged =
2066 data->dev_conf.txmode.hw_vlan_reject_untagged;
2069 return i40e_vsi_vlan_pvid_set(vsi, &info);
2073 i40e_dev_led_on(struct rte_eth_dev *dev)
2075 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2076 uint32_t mode = i40e_led_get(hw);
2079 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2085 i40e_dev_led_off(struct rte_eth_dev *dev)
2087 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2088 uint32_t mode = i40e_led_get(hw);
2091 i40e_led_set(hw, 0, false);
2097 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2099 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2102 fc_conf->pause_time = pf->fc_conf.pause_time;
2103 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2104 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2106 /* Return current mode according to actual setting*/
2107 switch (hw->fc.current_mode) {
2109 fc_conf->mode = RTE_FC_FULL;
2111 case I40E_FC_TX_PAUSE:
2112 fc_conf->mode = RTE_FC_TX_PAUSE;
2114 case I40E_FC_RX_PAUSE:
2115 fc_conf->mode = RTE_FC_RX_PAUSE;
2119 fc_conf->mode = RTE_FC_NONE;
2126 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2128 uint32_t mflcn_reg, fctrl_reg, reg;
2129 uint32_t max_high_water;
2130 uint8_t i, aq_failure;
2134 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2135 [RTE_FC_NONE] = I40E_FC_NONE,
2136 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2137 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2138 [RTE_FC_FULL] = I40E_FC_FULL
2141 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2143 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2144 if ((fc_conf->high_water > max_high_water) ||
2145 (fc_conf->high_water < fc_conf->low_water)) {
2146 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2147 "High_water must <= %d.", max_high_water);
2151 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2152 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2153 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2155 pf->fc_conf.pause_time = fc_conf->pause_time;
2156 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2157 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2159 PMD_INIT_FUNC_TRACE();
2161 /* All the link flow control related enable/disable register
2162 * configuration is handle by the F/W
2164 err = i40e_set_fc(hw, &aq_failure, true);
2168 if (i40e_is_40G_device(hw->device_id)) {
2169 /* Configure flow control refresh threshold,
2170 * the value for stat_tx_pause_refresh_timer[8]
2171 * is used for global pause operation.
2175 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2176 pf->fc_conf.pause_time);
2178 /* configure the timer value included in transmitted pause
2180 * the value for stat_tx_pause_quanta[8] is used for global
2183 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2184 pf->fc_conf.pause_time);
2186 fctrl_reg = I40E_READ_REG(hw,
2187 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2189 if (fc_conf->mac_ctrl_frame_fwd != 0)
2190 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2192 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2194 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2197 /* Configure pause time (2 TCs per register) */
2198 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2199 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2200 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2202 /* Configure flow control refresh threshold value */
2203 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2204 pf->fc_conf.pause_time / 2);
2206 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2208 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2209 *depending on configuration
2211 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2212 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2213 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2215 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2216 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2219 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2222 /* config the water marker both based on the packets and bytes */
2223 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2224 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2225 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2226 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2227 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2228 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2229 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2230 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2232 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2233 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2236 I40E_WRITE_FLUSH(hw);
2242 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2243 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2245 PMD_INIT_FUNC_TRACE();
2250 /* Add a MAC address, and update filters */
2252 i40e_macaddr_add(struct rte_eth_dev *dev,
2253 struct ether_addr *mac_addr,
2254 __rte_unused uint32_t index,
2257 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2258 struct i40e_mac_filter_info mac_filter;
2259 struct i40e_vsi *vsi;
2262 /* If VMDQ not enabled or configured, return */
2263 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2264 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2265 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2270 if (pool > pf->nb_cfg_vmdq_vsi) {
2271 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2272 pool, pf->nb_cfg_vmdq_vsi);
2276 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2277 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2282 vsi = pf->vmdq[pool - 1].vsi;
2284 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2285 if (ret != I40E_SUCCESS) {
2286 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2291 /* Remove a MAC address, and update filters */
2293 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2295 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2296 struct i40e_vsi *vsi;
2297 struct rte_eth_dev_data *data = dev->data;
2298 struct ether_addr *macaddr;
2303 macaddr = &(data->mac_addrs[index]);
2305 pool_sel = dev->data->mac_pool_sel[index];
2307 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2308 if (pool_sel & (1ULL << i)) {
2312 /* No VMDQ pool enabled or configured */
2313 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2314 (i > pf->nb_cfg_vmdq_vsi)) {
2315 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2319 vsi = pf->vmdq[i - 1].vsi;
2321 ret = i40e_vsi_delete_mac(vsi, macaddr);
2324 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2331 /* Set perfect match or hash match of MAC and VLAN for a VF */
2333 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2334 struct rte_eth_mac_filter *filter,
2338 struct i40e_mac_filter_info mac_filter;
2339 struct ether_addr old_mac;
2340 struct ether_addr *new_mac;
2341 struct i40e_pf_vf *vf = NULL;
2346 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2349 hw = I40E_PF_TO_HW(pf);
2351 if (filter == NULL) {
2352 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2356 new_mac = &filter->mac_addr;
2358 if (is_zero_ether_addr(new_mac)) {
2359 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2363 vf_id = filter->dst_id;
2365 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2366 PMD_DRV_LOG(ERR, "Invalid argument.");
2369 vf = &pf->vfs[vf_id];
2371 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2372 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2377 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2378 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2380 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2383 mac_filter.filter_type = filter->filter_type;
2384 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2385 if (ret != I40E_SUCCESS) {
2386 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2389 ether_addr_copy(new_mac, &pf->dev_addr);
2391 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2393 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2394 if (ret != I40E_SUCCESS) {
2395 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2399 /* Clear device address as it has been removed */
2400 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2401 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2407 /* MAC filter handle */
2409 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2412 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2413 struct rte_eth_mac_filter *filter;
2414 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2415 int ret = I40E_NOT_SUPPORTED;
2417 filter = (struct rte_eth_mac_filter *)(arg);
2419 switch (filter_op) {
2420 case RTE_ETH_FILTER_NOP:
2423 case RTE_ETH_FILTER_ADD:
2424 i40e_pf_disable_irq0(hw);
2426 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2427 i40e_pf_enable_irq0(hw);
2429 case RTE_ETH_FILTER_DELETE:
2430 i40e_pf_disable_irq0(hw);
2432 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2433 i40e_pf_enable_irq0(hw);
2436 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2437 ret = I40E_ERR_PARAM;
2445 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2446 struct rte_eth_rss_reta_entry64 *reta_conf,
2449 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2450 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2452 uint16_t i, j, lut_size = pf->hash_lut_size;
2453 uint16_t idx, shift;
2456 if (reta_size != lut_size ||
2457 reta_size > ETH_RSS_RETA_SIZE_512) {
2458 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2459 "(%d) doesn't match the number hardware can supported "
2460 "(%d)\n", reta_size, lut_size);
2464 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2465 idx = i / RTE_RETA_GROUP_SIZE;
2466 shift = i % RTE_RETA_GROUP_SIZE;
2467 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2471 if (mask == I40E_4_BIT_MASK)
2474 l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2475 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2476 if (mask & (0x1 << j))
2477 lut |= reta_conf[idx].reta[shift + j] <<
2480 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2482 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2489 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2490 struct rte_eth_rss_reta_entry64 *reta_conf,
2493 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2494 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496 uint16_t i, j, lut_size = pf->hash_lut_size;
2497 uint16_t idx, shift;
2500 if (reta_size != lut_size ||
2501 reta_size > ETH_RSS_RETA_SIZE_512) {
2502 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2503 "(%d) doesn't match the number hardware can supported "
2504 "(%d)\n", reta_size, lut_size);
2508 for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2509 idx = i / RTE_RETA_GROUP_SIZE;
2510 shift = i % RTE_RETA_GROUP_SIZE;
2511 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2516 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2517 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2518 if (mask & (0x1 << j))
2519 reta_conf[idx].reta[shift + j] = ((lut >>
2520 (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2528 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2529 * @hw: pointer to the HW structure
2530 * @mem: pointer to mem struct to fill out
2531 * @size: size of memory requested
2532 * @alignment: what to align the allocation to
2534 enum i40e_status_code
2535 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2536 struct i40e_dma_mem *mem,
2540 static uint64_t id = 0;
2541 const struct rte_memzone *mz = NULL;
2542 char z_name[RTE_MEMZONE_NAMESIZE];
2545 return I40E_ERR_PARAM;
2548 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2549 #ifdef RTE_LIBRTE_XEN_DOM0
2550 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2551 alignment, RTE_PGSIZE_2M);
2553 mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2557 return I40E_ERR_NO_MEMORY;
2562 #ifdef RTE_LIBRTE_XEN_DOM0
2563 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2565 mem->pa = mz->phys_addr;
2568 return I40E_SUCCESS;
2572 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2573 * @hw: pointer to the HW structure
2574 * @mem: ptr to mem struct to free
2576 enum i40e_status_code
2577 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2578 struct i40e_dma_mem *mem)
2580 if (!mem || !mem->va)
2581 return I40E_ERR_PARAM;
2586 return I40E_SUCCESS;
2590 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2591 * @hw: pointer to the HW structure
2592 * @mem: pointer to mem struct to fill out
2593 * @size: size of memory requested
2595 enum i40e_status_code
2596 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2597 struct i40e_virt_mem *mem,
2601 return I40E_ERR_PARAM;
2604 mem->va = rte_zmalloc("i40e", size, 0);
2607 return I40E_SUCCESS;
2609 return I40E_ERR_NO_MEMORY;
2613 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2614 * @hw: pointer to the HW structure
2615 * @mem: pointer to mem struct to free
2617 enum i40e_status_code
2618 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2619 struct i40e_virt_mem *mem)
2622 return I40E_ERR_PARAM;
2627 return I40E_SUCCESS;
2631 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2633 rte_spinlock_init(&sp->spinlock);
2637 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2639 rte_spinlock_lock(&sp->spinlock);
2643 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2645 rte_spinlock_unlock(&sp->spinlock);
2649 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2655 * Get the hardware capabilities, which will be parsed
2656 * and saved into struct i40e_hw.
2659 i40e_get_cap(struct i40e_hw *hw)
2661 struct i40e_aqc_list_capabilities_element_resp *buf;
2662 uint16_t len, size = 0;
2665 /* Calculate a huge enough buff for saving response data temporarily */
2666 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2667 I40E_MAX_CAP_ELE_NUM;
2668 buf = rte_zmalloc("i40e", len, 0);
2670 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2671 return I40E_ERR_NO_MEMORY;
2674 /* Get, parse the capabilities and save it to hw */
2675 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2676 i40e_aqc_opc_list_func_capabilities, NULL);
2677 if (ret != I40E_SUCCESS)
2678 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2680 /* Free the temporary buffer after being used */
2687 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2689 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2690 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2691 uint16_t sum_queues = 0, sum_vsis, left_queues;
2693 /* First check if FW support SRIOV */
2694 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2695 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2698 /* Add the parameter init for LFC */
2699 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2700 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2701 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2703 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2704 pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2705 PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2706 /* Allocate queues for pf */
2707 if (hw->func_caps.rss) {
2708 pf->flags |= I40E_FLAG_RSS;
2709 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2710 (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2711 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2714 sum_queues = pf->lan_nb_qps;
2715 /* Default VSI is not counted in */
2717 PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2719 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2720 pf->flags |= I40E_FLAG_SRIOV;
2721 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2722 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2723 PMD_INIT_LOG(ERR, "Config VF number %u, "
2724 "max supported %u.",
2725 dev->pci_dev->max_vfs,
2726 hw->func_caps.num_vfs);
2729 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2730 PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2731 "max support %u queues.",
2732 pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2735 pf->vf_num = dev->pci_dev->max_vfs;
2736 sum_queues += pf->vf_nb_qps * pf->vf_num;
2737 sum_vsis += pf->vf_num;
2738 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2739 pf->vf_num, pf->vf_nb_qps);
2743 if (hw->func_caps.vmdq) {
2744 pf->flags |= I40E_FLAG_VMDQ;
2745 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2746 pf->max_nb_vmdq_vsi = 1;
2748 * If VMDQ available, assume a single VSI can be created. Will adjust
2751 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2752 sum_vsis += pf->max_nb_vmdq_vsi;
2754 pf->vmdq_nb_qps = 0;
2755 pf->max_nb_vmdq_vsi = 0;
2757 pf->nb_cfg_vmdq_vsi = 0;
2759 if (hw->func_caps.fd) {
2760 pf->flags |= I40E_FLAG_FDIR;
2761 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2763 * Each flow director consumes one VSI and one queue,
2764 * but can't calculate out predictably here.
2768 if (hw->func_caps.dcb)
2769 pf->flags |= I40E_FLAG_DCB;
2771 if (sum_vsis > pf->max_num_vsi ||
2772 sum_queues > hw->func_caps.num_rx_qp) {
2773 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2774 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2775 pf->max_num_vsi, sum_vsis);
2776 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2777 hw->func_caps.num_rx_qp, sum_queues);
2781 /* Adjust VMDQ setting to support as many VMs as possible */
2782 if (pf->flags & I40E_FLAG_VMDQ) {
2783 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2785 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2786 pf->max_num_vsi - sum_vsis);
2788 /* Limit the max VMDQ number that rte_ether that can support */
2789 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2792 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2793 pf->max_nb_vmdq_vsi);
2794 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2797 /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2799 if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2800 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2801 sum_vsis, hw->func_caps.num_msix_vectors);
2804 return I40E_SUCCESS;
2808 i40e_pf_get_switch_config(struct i40e_pf *pf)
2810 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2811 struct i40e_aqc_get_switch_config_resp *switch_config;
2812 struct i40e_aqc_switch_config_element_resp *element;
2813 uint16_t start_seid = 0, num_reported;
2816 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2817 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2818 if (!switch_config) {
2819 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2823 /* Get the switch configurations */
2824 ret = i40e_aq_get_switch_config(hw, switch_config,
2825 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2826 if (ret != I40E_SUCCESS) {
2827 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2830 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2831 if (num_reported != 1) { /* The number should be 1 */
2832 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2836 /* Parse the switch configuration elements */
2837 element = &(switch_config->element[0]);
2838 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2839 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2840 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2842 PMD_DRV_LOG(INFO, "Unknown element type");
2845 rte_free(switch_config);
2851 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2854 struct pool_entry *entry;
2856 if (pool == NULL || num == 0)
2859 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2860 if (entry == NULL) {
2861 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2865 /* queue heap initialize */
2866 pool->num_free = num;
2867 pool->num_alloc = 0;
2869 LIST_INIT(&pool->alloc_list);
2870 LIST_INIT(&pool->free_list);
2872 /* Initialize element */
2876 LIST_INSERT_HEAD(&pool->free_list, entry, next);
2881 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2883 struct pool_entry *entry;
2888 LIST_FOREACH(entry, &pool->alloc_list, next) {
2889 LIST_REMOVE(entry, next);
2893 LIST_FOREACH(entry, &pool->free_list, next) {
2894 LIST_REMOVE(entry, next);
2899 pool->num_alloc = 0;
2901 LIST_INIT(&pool->alloc_list);
2902 LIST_INIT(&pool->free_list);
2906 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2909 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2910 uint32_t pool_offset;
2914 PMD_DRV_LOG(ERR, "Invalid parameter");
2918 pool_offset = base - pool->base;
2919 /* Lookup in alloc list */
2920 LIST_FOREACH(entry, &pool->alloc_list, next) {
2921 if (entry->base == pool_offset) {
2922 valid_entry = entry;
2923 LIST_REMOVE(entry, next);
2928 /* Not find, return */
2929 if (valid_entry == NULL) {
2930 PMD_DRV_LOG(ERR, "Failed to find entry");
2935 * Found it, move it to free list and try to merge.
2936 * In order to make merge easier, always sort it by qbase.
2937 * Find adjacent prev and last entries.
2940 LIST_FOREACH(entry, &pool->free_list, next) {
2941 if (entry->base > valid_entry->base) {
2949 /* Try to merge with next one*/
2951 /* Merge with next one */
2952 if (valid_entry->base + valid_entry->len == next->base) {
2953 next->base = valid_entry->base;
2954 next->len += valid_entry->len;
2955 rte_free(valid_entry);
2962 /* Merge with previous one */
2963 if (prev->base + prev->len == valid_entry->base) {
2964 prev->len += valid_entry->len;
2965 /* If it merge with next one, remove next node */
2967 LIST_REMOVE(valid_entry, next);
2968 rte_free(valid_entry);
2970 rte_free(valid_entry);
2976 /* Not find any entry to merge, insert */
2979 LIST_INSERT_AFTER(prev, valid_entry, next);
2980 else if (next != NULL)
2981 LIST_INSERT_BEFORE(next, valid_entry, next);
2982 else /* It's empty list, insert to head */
2983 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2986 pool->num_free += valid_entry->len;
2987 pool->num_alloc -= valid_entry->len;
2993 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2996 struct pool_entry *entry, *valid_entry;
2998 if (pool == NULL || num == 0) {
2999 PMD_DRV_LOG(ERR, "Invalid parameter");
3003 if (pool->num_free < num) {
3004 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3005 num, pool->num_free);
3010 /* Lookup in free list and find most fit one */
3011 LIST_FOREACH(entry, &pool->free_list, next) {
3012 if (entry->len >= num) {
3014 if (entry->len == num) {
3015 valid_entry = entry;
3018 if (valid_entry == NULL || valid_entry->len > entry->len)
3019 valid_entry = entry;
3023 /* Not find one to satisfy the request, return */
3024 if (valid_entry == NULL) {
3025 PMD_DRV_LOG(ERR, "No valid entry found");
3029 * The entry have equal queue number as requested,
3030 * remove it from alloc_list.
3032 if (valid_entry->len == num) {
3033 LIST_REMOVE(valid_entry, next);
3036 * The entry have more numbers than requested,
3037 * create a new entry for alloc_list and minus its
3038 * queue base and number in free_list.
3040 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3041 if (entry == NULL) {
3042 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3046 entry->base = valid_entry->base;
3048 valid_entry->base += num;
3049 valid_entry->len -= num;
3050 valid_entry = entry;
3053 /* Insert it into alloc list, not sorted */
3054 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3056 pool->num_free -= valid_entry->len;
3057 pool->num_alloc += valid_entry->len;
3059 return (valid_entry->base + pool->base);
3063 * bitmap_is_subset - Check whether src2 is subset of src1
3066 bitmap_is_subset(uint8_t src1, uint8_t src2)
3068 return !((src1 ^ src2) & src2);
3072 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3074 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3076 /* If DCB is not supported, only default TC is supported */
3077 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3078 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3082 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3083 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3084 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3088 return I40E_SUCCESS;
3092 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3093 struct i40e_vsi_vlan_pvid_info *info)
3096 struct i40e_vsi_context ctxt;
3097 uint8_t vlan_flags = 0;
3100 if (vsi == NULL || info == NULL) {
3101 PMD_DRV_LOG(ERR, "invalid parameters");
3102 return I40E_ERR_PARAM;
3106 vsi->info.pvid = info->config.pvid;
3108 * If insert pvid is enabled, only tagged pkts are
3109 * allowed to be sent out.
3111 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3112 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3115 if (info->config.reject.tagged == 0)
3116 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3118 if (info->config.reject.untagged == 0)
3119 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3121 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3122 I40E_AQ_VSI_PVLAN_MODE_MASK);
3123 vsi->info.port_vlan_flags |= vlan_flags;
3124 vsi->info.valid_sections =
3125 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3126 memset(&ctxt, 0, sizeof(ctxt));
3127 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3128 ctxt.seid = vsi->seid;
3130 hw = I40E_VSI_TO_HW(vsi);
3131 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3132 if (ret != I40E_SUCCESS)
3133 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3139 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3141 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3143 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3145 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3146 if (ret != I40E_SUCCESS)
3150 PMD_DRV_LOG(ERR, "seid not valid");
3154 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3155 tc_bw_data.tc_valid_bits = enabled_tcmap;
3156 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3157 tc_bw_data.tc_bw_credits[i] =
3158 (enabled_tcmap & (1 << i)) ? 1 : 0;
3160 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3161 if (ret != I40E_SUCCESS) {
3162 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3166 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3167 sizeof(vsi->info.qs_handle));
3168 return I40E_SUCCESS;
3172 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3173 struct i40e_aqc_vsi_properties_data *info,
3174 uint8_t enabled_tcmap)
3176 int ret, i, total_tc = 0;
3177 uint16_t qpnum_per_tc, bsf, qp_idx;
3179 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3180 if (ret != I40E_SUCCESS)
3183 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3184 if (enabled_tcmap & (1 << i))
3186 vsi->enabled_tc = enabled_tcmap;
3188 /* Number of queues per enabled TC */
3189 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3190 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3191 bsf = rte_bsf32(qpnum_per_tc);
3193 /* Adjust the queue number to actual queues that can be applied */
3194 vsi->nb_qps = qpnum_per_tc * total_tc;
3197 * Configure TC and queue mapping parameters, for enabled TC,
3198 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3199 * default queue will serve it.
3202 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3203 if (vsi->enabled_tc & (1 << i)) {
3204 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3205 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3206 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3207 qp_idx += qpnum_per_tc;
3209 info->tc_mapping[i] = 0;
3212 /* Associate queue number with VSI */
3213 if (vsi->type == I40E_VSI_SRIOV) {
3214 info->mapping_flags |=
3215 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3216 for (i = 0; i < vsi->nb_qps; i++)
3217 info->queue_mapping[i] =
3218 rte_cpu_to_le_16(vsi->base_queue + i);
3220 info->mapping_flags |=
3221 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3222 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3224 info->valid_sections |=
3225 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3227 return I40E_SUCCESS;
3231 i40e_veb_release(struct i40e_veb *veb)
3233 struct i40e_vsi *vsi;
3236 if (veb == NULL || veb->associate_vsi == NULL)
3239 if (!TAILQ_EMPTY(&veb->head)) {
3240 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3244 vsi = veb->associate_vsi;
3245 hw = I40E_VSI_TO_HW(vsi);
3247 vsi->uplink_seid = veb->uplink_seid;
3248 i40e_aq_delete_element(hw, veb->seid, NULL);
3251 return I40E_SUCCESS;
3255 static struct i40e_veb *
3256 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3258 struct i40e_veb *veb;
3262 if (NULL == pf || vsi == NULL) {
3263 PMD_DRV_LOG(ERR, "veb setup failed, "
3264 "associated VSI shouldn't null");
3267 hw = I40E_PF_TO_HW(pf);
3269 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3271 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3275 veb->associate_vsi = vsi;
3276 TAILQ_INIT(&veb->head);
3277 veb->uplink_seid = vsi->uplink_seid;
3279 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3280 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3282 if (ret != I40E_SUCCESS) {
3283 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3284 hw->aq.asq_last_status);
3288 /* get statistics index */
3289 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3290 &veb->stats_idx, NULL, NULL, NULL);
3291 if (ret != I40E_SUCCESS) {
3292 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3293 hw->aq.asq_last_status);
3297 /* Get VEB bandwidth, to be implemented */
3298 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3299 vsi->uplink_seid = veb->seid;
3308 i40e_vsi_release(struct i40e_vsi *vsi)
3312 struct i40e_vsi_list *vsi_list;
3314 struct i40e_mac_filter *f;
3317 return I40E_SUCCESS;
3319 pf = I40E_VSI_TO_PF(vsi);
3320 hw = I40E_VSI_TO_HW(vsi);
3322 /* VSI has child to attach, release child first */
3324 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3325 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3327 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3329 i40e_veb_release(vsi->veb);
3332 /* Remove all macvlan filters of the VSI */
3333 i40e_vsi_remove_all_macvlan_filter(vsi);
3334 TAILQ_FOREACH(f, &vsi->mac_list, next)
3337 if (vsi->type != I40E_VSI_MAIN) {
3338 /* Remove vsi from parent's sibling list */
3339 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3340 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3341 return I40E_ERR_PARAM;
3343 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3344 &vsi->sib_vsi_list, list);
3346 /* Remove all switch element of the VSI */
3347 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3348 if (ret != I40E_SUCCESS)
3349 PMD_DRV_LOG(ERR, "Failed to delete element");
3351 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3353 if (vsi->type != I40E_VSI_SRIOV)
3354 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3357 return I40E_SUCCESS;
3361 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3363 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3364 struct i40e_aqc_remove_macvlan_element_data def_filter;
3365 struct i40e_mac_filter_info filter;
3368 if (vsi->type != I40E_VSI_MAIN)
3369 return I40E_ERR_CONFIG;
3370 memset(&def_filter, 0, sizeof(def_filter));
3371 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3373 def_filter.vlan_tag = 0;
3374 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3375 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3376 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3377 if (ret != I40E_SUCCESS) {
3378 struct i40e_mac_filter *f;
3379 struct ether_addr *mac;
3381 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3383 /* It needs to add the permanent mac into mac list */
3384 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3386 PMD_DRV_LOG(ERR, "failed to allocate memory");
3387 return I40E_ERR_NO_MEMORY;
3389 mac = &f->mac_info.mac_addr;
3390 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3392 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3393 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3398 (void)rte_memcpy(&filter.mac_addr,
3399 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3400 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3401 return i40e_vsi_add_mac(vsi, &filter);
3405 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3407 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3408 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3409 struct i40e_hw *hw = &vsi->adapter->hw;
3413 memset(&bw_config, 0, sizeof(bw_config));
3414 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3415 if (ret != I40E_SUCCESS) {
3416 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3417 hw->aq.asq_last_status);
3421 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3422 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3423 &ets_sla_config, NULL);
3424 if (ret != I40E_SUCCESS) {
3425 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3426 "configuration %u", hw->aq.asq_last_status);
3430 /* Not store the info yet, just print out */
3431 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3432 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3433 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3434 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3435 ets_sla_config.share_credits[i]);
3436 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3437 rte_le_to_cpu_16(ets_sla_config.credits[i]));
3438 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3439 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3448 i40e_vsi_setup(struct i40e_pf *pf,
3449 enum i40e_vsi_type type,
3450 struct i40e_vsi *uplink_vsi,
3451 uint16_t user_param)
3453 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3454 struct i40e_vsi *vsi;
3455 struct i40e_mac_filter_info filter;
3457 struct i40e_vsi_context ctxt;
3458 struct ether_addr broadcast =
3459 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3461 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3462 PMD_DRV_LOG(ERR, "VSI setup failed, "
3463 "VSI link shouldn't be NULL");
3467 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3468 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3469 "uplink VSI should be NULL");
3473 /* If uplink vsi didn't setup VEB, create one first */
3474 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3475 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3477 if (NULL == uplink_vsi->veb) {
3478 PMD_DRV_LOG(ERR, "VEB setup failed");
3483 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3485 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3488 TAILQ_INIT(&vsi->mac_list);
3490 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3491 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3492 vsi->parent_vsi = uplink_vsi;
3493 vsi->user_param = user_param;
3494 /* Allocate queues */
3495 switch (vsi->type) {
3496 case I40E_VSI_MAIN :
3497 vsi->nb_qps = pf->lan_nb_qps;
3499 case I40E_VSI_SRIOV :
3500 vsi->nb_qps = pf->vf_nb_qps;
3502 case I40E_VSI_VMDQ2:
3503 vsi->nb_qps = pf->vmdq_nb_qps;
3506 vsi->nb_qps = pf->fdir_nb_qps;
3512 * The filter status descriptor is reported in rx queue 0,
3513 * while the tx queue for fdir filter programming has no
3514 * such constraints, can be non-zero queues.
3515 * To simplify it, choose FDIR vsi use queue 0 pair.
3516 * To make sure it will use queue 0 pair, queue allocation
3517 * need be done before this function is called
3519 if (type != I40E_VSI_FDIR) {
3520 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3522 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3526 vsi->base_queue = ret;
3528 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3530 /* VF has MSIX interrupt in VF range, don't allocate here */
3531 if (type != I40E_VSI_SRIOV) {
3532 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3534 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3535 goto fail_queue_alloc;
3537 vsi->msix_intr = ret;
3541 if (type == I40E_VSI_MAIN) {
3542 /* For main VSI, no need to add since it's default one */
3543 vsi->uplink_seid = pf->mac_seid;
3544 vsi->seid = pf->main_vsi_seid;
3545 /* Bind queues with specific MSIX interrupt */
3547 * Needs 2 interrupt at least, one for misc cause which will
3548 * enabled from OS side, Another for queues binding the
3549 * interrupt from device side only.
3552 /* Get default VSI parameters from hardware */
3553 memset(&ctxt, 0, sizeof(ctxt));
3554 ctxt.seid = vsi->seid;
3555 ctxt.pf_num = hw->pf_id;
3556 ctxt.uplink_seid = vsi->uplink_seid;
3558 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3559 if (ret != I40E_SUCCESS) {
3560 PMD_DRV_LOG(ERR, "Failed to get VSI params");
3561 goto fail_msix_alloc;
3563 (void)rte_memcpy(&vsi->info, &ctxt.info,
3564 sizeof(struct i40e_aqc_vsi_properties_data));
3565 vsi->vsi_id = ctxt.vsi_number;
3566 vsi->info.valid_sections = 0;
3568 /* Configure tc, enabled TC0 only */
3569 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3571 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3572 goto fail_msix_alloc;
3575 /* TC, queue mapping */
3576 memset(&ctxt, 0, sizeof(ctxt));
3577 vsi->info.valid_sections |=
3578 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3579 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3580 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3581 (void)rte_memcpy(&ctxt.info, &vsi->info,
3582 sizeof(struct i40e_aqc_vsi_properties_data));
3583 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3584 I40E_DEFAULT_TCMAP);
3585 if (ret != I40E_SUCCESS) {
3586 PMD_DRV_LOG(ERR, "Failed to configure "
3587 "TC queue mapping");
3588 goto fail_msix_alloc;
3590 ctxt.seid = vsi->seid;
3591 ctxt.pf_num = hw->pf_id;
3592 ctxt.uplink_seid = vsi->uplink_seid;
3595 /* Update VSI parameters */
3596 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3597 if (ret != I40E_SUCCESS) {
3598 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3599 goto fail_msix_alloc;
3602 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3603 sizeof(vsi->info.tc_mapping));
3604 (void)rte_memcpy(&vsi->info.queue_mapping,
3605 &ctxt.info.queue_mapping,
3606 sizeof(vsi->info.queue_mapping));
3607 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3608 vsi->info.valid_sections = 0;
3610 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3614 * Updating default filter settings are necessary to prevent
3615 * reception of tagged packets.
3616 * Some old firmware configurations load a default macvlan
3617 * filter which accepts both tagged and untagged packets.
3618 * The updating is to use a normal filter instead if needed.
3619 * For NVM 4.2.2 or after, the updating is not needed anymore.
3620 * The firmware with correct configurations load the default
3621 * macvlan filter which is expected and cannot be removed.
3623 i40e_update_default_filter_setting(vsi);
3624 i40e_config_qinq(hw, vsi);
3625 } else if (type == I40E_VSI_SRIOV) {
3626 memset(&ctxt, 0, sizeof(ctxt));
3628 * For other VSI, the uplink_seid equals to uplink VSI's
3629 * uplink_seid since they share same VEB
3631 vsi->uplink_seid = uplink_vsi->uplink_seid;
3632 ctxt.pf_num = hw->pf_id;
3633 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3634 ctxt.uplink_seid = vsi->uplink_seid;
3635 ctxt.connection_type = 0x1;
3636 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3639 * Do not configure switch ID to enable VEB switch by
3640 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3641 * if the source mac address of packet sent from VF is not
3642 * listed in the VEB's mac table, the VEB will switch the
3643 * packet back to the VF. Need to enable it when HW issue
3647 /* Configure port/vlan */
3648 ctxt.info.valid_sections |=
3649 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3650 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3651 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3652 I40E_DEFAULT_TCMAP);
3653 if (ret != I40E_SUCCESS) {
3654 PMD_DRV_LOG(ERR, "Failed to configure "
3655 "TC queue mapping");
3656 goto fail_msix_alloc;
3658 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3659 ctxt.info.valid_sections |=
3660 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3662 * Since VSI is not created yet, only configure parameter,
3663 * will add vsi below.
3666 i40e_config_qinq(hw, vsi);
3667 } else if (type == I40E_VSI_VMDQ2) {
3668 memset(&ctxt, 0, sizeof(ctxt));
3670 * For other VSI, the uplink_seid equals to uplink VSI's
3671 * uplink_seid since they share same VEB
3673 vsi->uplink_seid = uplink_vsi->uplink_seid;
3674 ctxt.pf_num = hw->pf_id;
3676 ctxt.uplink_seid = vsi->uplink_seid;
3677 ctxt.connection_type = 0x1;
3678 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3680 ctxt.info.valid_sections |=
3681 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3682 /* user_param carries flag to enable loop back */
3684 ctxt.info.switch_id =
3685 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3686 ctxt.info.switch_id |=
3687 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3690 /* Configure port/vlan */
3691 ctxt.info.valid_sections |=
3692 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3693 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3694 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3695 I40E_DEFAULT_TCMAP);
3696 if (ret != I40E_SUCCESS) {
3697 PMD_DRV_LOG(ERR, "Failed to configure "
3698 "TC queue mapping");
3699 goto fail_msix_alloc;
3701 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3702 ctxt.info.valid_sections |=
3703 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3704 } else if (type == I40E_VSI_FDIR) {
3705 memset(&ctxt, 0, sizeof(ctxt));
3706 vsi->uplink_seid = uplink_vsi->uplink_seid;
3707 ctxt.pf_num = hw->pf_id;
3709 ctxt.uplink_seid = vsi->uplink_seid;
3710 ctxt.connection_type = 0x1; /* regular data port */
3711 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3712 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3713 I40E_DEFAULT_TCMAP);
3714 if (ret != I40E_SUCCESS) {
3715 PMD_DRV_LOG(ERR, "Failed to configure "
3716 "TC queue mapping.");
3717 goto fail_msix_alloc;
3719 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3720 ctxt.info.valid_sections |=
3721 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3723 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3724 goto fail_msix_alloc;
3727 if (vsi->type != I40E_VSI_MAIN) {
3728 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3729 if (ret != I40E_SUCCESS) {
3730 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3731 hw->aq.asq_last_status);
3732 goto fail_msix_alloc;
3734 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3735 vsi->info.valid_sections = 0;
3736 vsi->seid = ctxt.seid;
3737 vsi->vsi_id = ctxt.vsi_number;
3738 vsi->sib_vsi_list.vsi = vsi;
3739 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3740 &vsi->sib_vsi_list, list);
3743 /* MAC/VLAN configuration */
3744 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3745 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3747 ret = i40e_vsi_add_mac(vsi, &filter);
3748 if (ret != I40E_SUCCESS) {
3749 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3750 goto fail_msix_alloc;
3753 /* Get VSI BW information */
3754 i40e_vsi_dump_bw_config(vsi);
3757 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3759 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3765 /* Configure vlan stripping on or off */
3767 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3769 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3770 struct i40e_vsi_context ctxt;
3772 int ret = I40E_SUCCESS;
3774 /* Check if it has been already on or off */
3775 if (vsi->info.valid_sections &
3776 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3778 if ((vsi->info.port_vlan_flags &
3779 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3780 return 0; /* already on */
3782 if ((vsi->info.port_vlan_flags &
3783 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3784 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3785 return 0; /* already off */
3790 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3792 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3793 vsi->info.valid_sections =
3794 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3795 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3796 vsi->info.port_vlan_flags |= vlan_flags;
3797 ctxt.seid = vsi->seid;
3798 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3799 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3801 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3802 on ? "enable" : "disable");
3808 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3810 struct rte_eth_dev_data *data = dev->data;
3813 /* Apply vlan offload setting */
3814 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3816 /* Apply double-vlan setting, not implemented yet */
3818 /* Apply pvid setting */
3819 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3820 data->dev_conf.txmode.hw_vlan_insert_pvid);
3822 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3828 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3830 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3832 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3836 i40e_update_flow_control(struct i40e_hw *hw)
3838 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3839 struct i40e_link_status link_status;
3840 uint32_t rxfc = 0, txfc = 0, reg;
3844 memset(&link_status, 0, sizeof(link_status));
3845 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3846 if (ret != I40E_SUCCESS) {
3847 PMD_DRV_LOG(ERR, "Failed to get link status information");
3848 goto write_reg; /* Disable flow control */
3851 an_info = hw->phy.link_info.an_info;
3852 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3853 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3854 ret = I40E_ERR_NOT_READY;
3855 goto write_reg; /* Disable flow control */
3858 * If link auto negotiation is enabled, flow control needs to
3859 * be configured according to it
3861 switch (an_info & I40E_LINK_PAUSE_RXTX) {
3862 case I40E_LINK_PAUSE_RXTX:
3865 hw->fc.current_mode = I40E_FC_FULL;
3867 case I40E_AQ_LINK_PAUSE_RX:
3869 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3871 case I40E_AQ_LINK_PAUSE_TX:
3873 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3876 hw->fc.current_mode = I40E_FC_NONE;
3881 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3882 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3883 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3884 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3885 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3886 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3893 i40e_pf_setup(struct i40e_pf *pf)
3895 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3896 struct i40e_filter_control_settings settings;
3897 struct i40e_vsi *vsi;
3900 /* Clear all stats counters */
3901 pf->offset_loaded = FALSE;
3902 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3903 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3905 ret = i40e_pf_get_switch_config(pf);
3906 if (ret != I40E_SUCCESS) {
3907 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3910 if (pf->flags & I40E_FLAG_FDIR) {
3911 /* make queue allocated first, let FDIR use queue pair 0*/
3912 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3913 if (ret != I40E_FDIR_QUEUE_ID) {
3914 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3916 pf->flags &= ~I40E_FLAG_FDIR;
3919 /* main VSI setup */
3920 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3922 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3923 return I40E_ERR_NOT_READY;
3927 /* Configure filter control */
3928 memset(&settings, 0, sizeof(settings));
3929 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3930 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3931 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3932 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3934 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3935 hw->func_caps.rss_table_size);
3936 return I40E_ERR_PARAM;
3938 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3939 "size: %u\n", hw->func_caps.rss_table_size);
3940 pf->hash_lut_size = hw->func_caps.rss_table_size;
3942 /* Enable ethtype and macvlan filters */
3943 settings.enable_ethtype = TRUE;
3944 settings.enable_macvlan = TRUE;
3945 ret = i40e_set_filter_control(hw, &settings);
3947 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3950 /* Update flow control according to the auto negotiation */
3951 i40e_update_flow_control(hw);
3953 return I40E_SUCCESS;
3957 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3963 * Set or clear TX Queue Disable flags,
3964 * which is required by hardware.
3966 i40e_pre_tx_queue_cfg(hw, q_idx, on);
3967 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3969 /* Wait until the request is finished */
3970 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3971 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3972 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3973 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3974 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3980 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3981 return I40E_SUCCESS; /* already on, skip next steps */
3983 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3984 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3986 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3987 return I40E_SUCCESS; /* already off, skip next steps */
3988 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3990 /* Write the register */
3991 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3992 /* Check the result */
3993 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3994 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3995 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3997 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3998 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4001 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4002 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4006 /* Check if it is timeout */
4007 if (j >= I40E_CHK_Q_ENA_COUNT) {
4008 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4009 (on ? "enable" : "disable"), q_idx);
4010 return I40E_ERR_TIMEOUT;
4013 return I40E_SUCCESS;
4016 /* Swith on or off the tx queues */
4018 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4020 struct rte_eth_dev_data *dev_data = pf->dev_data;
4021 struct i40e_tx_queue *txq;
4022 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4026 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4027 txq = dev_data->tx_queues[i];
4028 /* Don't operate the queue if not configured or
4029 * if starting only per queue */
4030 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4033 ret = i40e_dev_tx_queue_start(dev, i);
4035 ret = i40e_dev_tx_queue_stop(dev, i);
4036 if ( ret != I40E_SUCCESS)
4040 return I40E_SUCCESS;
4044 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4049 /* Wait until the request is finished */
4050 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4051 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4052 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4053 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4054 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4059 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4060 return I40E_SUCCESS; /* Already on, skip next steps */
4061 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4063 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4064 return I40E_SUCCESS; /* Already off, skip next steps */
4065 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4068 /* Write the register */
4069 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4070 /* Check the result */
4071 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4072 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4073 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4075 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4076 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4079 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4080 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4085 /* Check if it is timeout */
4086 if (j >= I40E_CHK_Q_ENA_COUNT) {
4087 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4088 (on ? "enable" : "disable"), q_idx);
4089 return I40E_ERR_TIMEOUT;
4092 return I40E_SUCCESS;
4094 /* Switch on or off the rx queues */
4096 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4098 struct rte_eth_dev_data *dev_data = pf->dev_data;
4099 struct i40e_rx_queue *rxq;
4100 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4104 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4105 rxq = dev_data->rx_queues[i];
4106 /* Don't operate the queue if not configured or
4107 * if starting only per queue */
4108 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4111 ret = i40e_dev_rx_queue_start(dev, i);
4113 ret = i40e_dev_rx_queue_stop(dev, i);
4114 if (ret != I40E_SUCCESS)
4118 return I40E_SUCCESS;
4121 /* Switch on or off all the rx/tx queues */
4123 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4128 /* enable rx queues before enabling tx queues */
4129 ret = i40e_dev_switch_rx_queues(pf, on);
4131 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4134 ret = i40e_dev_switch_tx_queues(pf, on);
4136 /* Stop tx queues before stopping rx queues */
4137 ret = i40e_dev_switch_tx_queues(pf, on);
4139 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4142 ret = i40e_dev_switch_rx_queues(pf, on);
4148 /* Initialize VSI for TX */
4150 i40e_dev_tx_init(struct i40e_pf *pf)
4152 struct rte_eth_dev_data *data = pf->dev_data;
4154 uint32_t ret = I40E_SUCCESS;
4155 struct i40e_tx_queue *txq;
4157 for (i = 0; i < data->nb_tx_queues; i++) {
4158 txq = data->tx_queues[i];
4159 if (!txq || !txq->q_set)
4161 ret = i40e_tx_queue_init(txq);
4162 if (ret != I40E_SUCCESS)
4165 if (ret == I40E_SUCCESS)
4166 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4172 /* Initialize VSI for RX */
4174 i40e_dev_rx_init(struct i40e_pf *pf)
4176 struct rte_eth_dev_data *data = pf->dev_data;
4177 int ret = I40E_SUCCESS;
4179 struct i40e_rx_queue *rxq;
4181 i40e_pf_config_mq_rx(pf);
4182 for (i = 0; i < data->nb_rx_queues; i++) {
4183 rxq = data->rx_queues[i];
4184 if (!rxq || !rxq->q_set)
4187 ret = i40e_rx_queue_init(rxq);
4188 if (ret != I40E_SUCCESS) {
4189 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4194 if (ret == I40E_SUCCESS)
4195 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4202 i40e_dev_rxtx_init(struct i40e_pf *pf)
4206 err = i40e_dev_tx_init(pf);
4208 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4211 err = i40e_dev_rx_init(pf);
4213 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4221 i40e_vmdq_setup(struct rte_eth_dev *dev)
4223 struct rte_eth_conf *conf = &dev->data->dev_conf;
4224 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4225 int i, err, conf_vsis, j, loop;
4226 struct i40e_vsi *vsi;
4227 struct i40e_vmdq_info *vmdq_info;
4228 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4229 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4232 * Disable interrupt to avoid message from VF. Furthermore, it will
4233 * avoid race condition in VSI creation/destroy.
4235 i40e_pf_disable_irq0(hw);
4237 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4238 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4242 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4243 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4244 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4245 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4246 pf->max_nb_vmdq_vsi);
4250 if (pf->vmdq != NULL) {
4251 PMD_INIT_LOG(INFO, "VMDQ already configured");
4255 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4256 sizeof(*vmdq_info) * conf_vsis, 0);
4258 if (pf->vmdq == NULL) {
4259 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4263 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4265 /* Create VMDQ VSI */
4266 for (i = 0; i < conf_vsis; i++) {
4267 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4268 vmdq_conf->enable_loop_back);
4270 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4274 vmdq_info = &pf->vmdq[i];
4276 vmdq_info->vsi = vsi;
4278 pf->nb_cfg_vmdq_vsi = conf_vsis;
4280 /* Configure Vlan */
4281 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4282 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4283 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4284 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4285 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4286 vmdq_conf->pool_map[i].vlan_id, j);
4288 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4289 vmdq_conf->pool_map[i].vlan_id);
4291 PMD_INIT_LOG(ERR, "Failed to add vlan");
4299 i40e_pf_enable_irq0(hw);
4304 for (i = 0; i < conf_vsis; i++)
4305 if (pf->vmdq[i].vsi == NULL)
4308 i40e_vsi_release(pf->vmdq[i].vsi);
4312 i40e_pf_enable_irq0(hw);
4317 i40e_stat_update_32(struct i40e_hw *hw,
4325 new_data = (uint64_t)I40E_READ_REG(hw, reg);
4329 if (new_data >= *offset)
4330 *stat = (uint64_t)(new_data - *offset);
4332 *stat = (uint64_t)((new_data +
4333 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4337 i40e_stat_update_48(struct i40e_hw *hw,
4346 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4347 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4348 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4353 if (new_data >= *offset)
4354 *stat = new_data - *offset;
4356 *stat = (uint64_t)((new_data +
4357 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4359 *stat &= I40E_48_BIT_MASK;
4364 i40e_pf_disable_irq0(struct i40e_hw *hw)
4366 /* Disable all interrupt types */
4367 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4368 I40E_WRITE_FLUSH(hw);
4373 i40e_pf_enable_irq0(struct i40e_hw *hw)
4375 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4376 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4377 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4378 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4379 I40E_WRITE_FLUSH(hw);
4383 i40e_pf_config_irq0(struct i40e_hw *hw)
4385 /* read pending request and disable first */
4386 i40e_pf_disable_irq0(hw);
4387 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4388 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4389 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4391 /* Link no queues with irq0 */
4392 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4393 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4397 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4399 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4403 uint32_t index, offset, val;
4408 * Try to find which VF trigger a reset, use absolute VF id to access
4409 * since the reg is global register.
4411 for (i = 0; i < pf->vf_num; i++) {
4412 abs_vf_id = hw->func_caps.vf_base_id + i;
4413 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4414 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4415 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4416 /* VFR event occured */
4417 if (val & (0x1 << offset)) {
4420 /* Clear the event first */
4421 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4423 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4425 * Only notify a VF reset event occured,
4426 * don't trigger another SW reset
4428 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4429 if (ret != I40E_SUCCESS)
4430 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4436 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4439 struct i40e_arq_event_info info;
4440 uint16_t pending, opcode;
4443 info.buf_len = I40E_AQ_BUF_SZ;
4444 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4445 if (!info.msg_buf) {
4446 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4452 ret = i40e_clean_arq_element(hw, &info, &pending);
4454 if (ret != I40E_SUCCESS) {
4455 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4456 "aq_err: %u", hw->aq.asq_last_status);
4459 opcode = rte_le_to_cpu_16(info.desc.opcode);
4462 case i40e_aqc_opc_send_msg_to_pf:
4463 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4464 i40e_pf_host_handle_vf_msg(dev,
4465 rte_le_to_cpu_16(info.desc.retval),
4466 rte_le_to_cpu_32(info.desc.cookie_high),
4467 rte_le_to_cpu_32(info.desc.cookie_low),
4472 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4477 rte_free(info.msg_buf);
4481 * Interrupt handler is registered as the alarm callback for handling LSC
4482 * interrupt in a definite of time, in order to wait the NIC into a stable
4483 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4484 * no need for link down interrupt.
4487 i40e_dev_interrupt_delayed_handler(void *param)
4489 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4490 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4493 /* read interrupt causes again */
4494 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4496 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4497 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4498 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4499 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4500 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4501 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4502 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4503 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4504 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4505 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4506 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4508 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4509 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4510 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4511 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4512 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4514 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4515 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4516 i40e_dev_handle_vfr_event(dev);
4518 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4519 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4520 i40e_dev_handle_aq_msg(dev);
4523 /* handle the link up interrupt in an alarm callback */
4524 i40e_dev_link_update(dev, 0);
4525 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4527 i40e_pf_enable_irq0(hw);
4528 rte_intr_enable(&(dev->pci_dev->intr_handle));
4532 * Interrupt handler triggered by NIC for handling
4533 * specific interrupt.
4536 * Pointer to interrupt handle.
4538 * The address of parameter (struct rte_eth_dev *) regsitered before.
4544 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4547 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4548 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4551 /* Disable interrupt */
4552 i40e_pf_disable_irq0(hw);
4554 /* read out interrupt causes */
4555 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4557 /* No interrupt event indicated */
4558 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4559 PMD_DRV_LOG(INFO, "No interrupt event");
4562 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4563 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4564 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4565 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4566 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4567 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4568 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4569 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4570 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4571 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4572 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4573 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4574 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4575 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4576 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4577 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4579 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4580 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4581 i40e_dev_handle_vfr_event(dev);
4583 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4584 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4585 i40e_dev_handle_aq_msg(dev);
4588 /* Link Status Change interrupt */
4589 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4590 #define I40E_US_PER_SECOND 1000000
4591 struct rte_eth_link link;
4593 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4594 memset(&link, 0, sizeof(link));
4595 rte_i40e_dev_atomic_read_link_status(dev, &link);
4596 i40e_dev_link_update(dev, 0);
4599 * For link up interrupt, it needs to wait 1 second to let the
4600 * hardware be a stable state. Otherwise several consecutive
4601 * interrupts can be observed.
4602 * For link down interrupt, no need to wait.
4604 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4605 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4608 _rte_eth_dev_callback_process(dev,
4609 RTE_ETH_EVENT_INTR_LSC);
4613 /* Enable interrupt */
4614 i40e_pf_enable_irq0(hw);
4615 rte_intr_enable(&(dev->pci_dev->intr_handle));
4619 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4620 struct i40e_macvlan_filter *filter,
4623 int ele_num, ele_buff_size;
4624 int num, actual_num, i;
4626 int ret = I40E_SUCCESS;
4627 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4628 struct i40e_aqc_add_macvlan_element_data *req_list;
4630 if (filter == NULL || total == 0)
4631 return I40E_ERR_PARAM;
4632 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4633 ele_buff_size = hw->aq.asq_buf_size;
4635 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4636 if (req_list == NULL) {
4637 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4638 return I40E_ERR_NO_MEMORY;
4643 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4644 memset(req_list, 0, ele_buff_size);
4646 for (i = 0; i < actual_num; i++) {
4647 (void)rte_memcpy(req_list[i].mac_addr,
4648 &filter[num + i].macaddr, ETH_ADDR_LEN);
4649 req_list[i].vlan_tag =
4650 rte_cpu_to_le_16(filter[num + i].vlan_id);
4652 switch (filter[num + i].filter_type) {
4653 case RTE_MAC_PERFECT_MATCH:
4654 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4655 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4657 case RTE_MACVLAN_PERFECT_MATCH:
4658 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4660 case RTE_MAC_HASH_MATCH:
4661 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4662 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4664 case RTE_MACVLAN_HASH_MATCH:
4665 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4668 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4669 ret = I40E_ERR_PARAM;
4673 req_list[i].queue_number = 0;
4675 req_list[i].flags = rte_cpu_to_le_16(flags);
4678 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4680 if (ret != I40E_SUCCESS) {
4681 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4685 } while (num < total);
4693 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4694 struct i40e_macvlan_filter *filter,
4697 int ele_num, ele_buff_size;
4698 int num, actual_num, i;
4700 int ret = I40E_SUCCESS;
4701 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4702 struct i40e_aqc_remove_macvlan_element_data *req_list;
4704 if (filter == NULL || total == 0)
4705 return I40E_ERR_PARAM;
4707 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4708 ele_buff_size = hw->aq.asq_buf_size;
4710 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4711 if (req_list == NULL) {
4712 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4713 return I40E_ERR_NO_MEMORY;
4718 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4719 memset(req_list, 0, ele_buff_size);
4721 for (i = 0; i < actual_num; i++) {
4722 (void)rte_memcpy(req_list[i].mac_addr,
4723 &filter[num + i].macaddr, ETH_ADDR_LEN);
4724 req_list[i].vlan_tag =
4725 rte_cpu_to_le_16(filter[num + i].vlan_id);
4727 switch (filter[num + i].filter_type) {
4728 case RTE_MAC_PERFECT_MATCH:
4729 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4730 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4732 case RTE_MACVLAN_PERFECT_MATCH:
4733 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4735 case RTE_MAC_HASH_MATCH:
4736 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4737 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4739 case RTE_MACVLAN_HASH_MATCH:
4740 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4743 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4744 ret = I40E_ERR_PARAM;
4747 req_list[i].flags = rte_cpu_to_le_16(flags);
4750 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4752 if (ret != I40E_SUCCESS) {
4753 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4757 } while (num < total);
4764 /* Find out specific MAC filter */
4765 static struct i40e_mac_filter *
4766 i40e_find_mac_filter(struct i40e_vsi *vsi,
4767 struct ether_addr *macaddr)
4769 struct i40e_mac_filter *f;
4771 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4772 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4780 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4783 uint32_t vid_idx, vid_bit;
4785 if (vlan_id > ETH_VLAN_ID_MAX)
4788 vid_idx = I40E_VFTA_IDX(vlan_id);
4789 vid_bit = I40E_VFTA_BIT(vlan_id);
4791 if (vsi->vfta[vid_idx] & vid_bit)
4798 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4799 uint16_t vlan_id, bool on)
4801 uint32_t vid_idx, vid_bit;
4803 if (vlan_id > ETH_VLAN_ID_MAX)
4806 vid_idx = I40E_VFTA_IDX(vlan_id);
4807 vid_bit = I40E_VFTA_BIT(vlan_id);
4810 vsi->vfta[vid_idx] |= vid_bit;
4812 vsi->vfta[vid_idx] &= ~vid_bit;
4816 * Find all vlan options for specific mac addr,
4817 * return with actual vlan found.
4820 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4821 struct i40e_macvlan_filter *mv_f,
4822 int num, struct ether_addr *addr)
4828 * Not to use i40e_find_vlan_filter to decrease the loop time,
4829 * although the code looks complex.
4831 if (num < vsi->vlan_num)
4832 return I40E_ERR_PARAM;
4835 for (j = 0; j < I40E_VFTA_SIZE; j++) {
4837 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4838 if (vsi->vfta[j] & (1 << k)) {
4840 PMD_DRV_LOG(ERR, "vlan number "
4842 return I40E_ERR_PARAM;
4844 (void)rte_memcpy(&mv_f[i].macaddr,
4845 addr, ETH_ADDR_LEN);
4847 j * I40E_UINT32_BIT_SIZE + k;
4853 return I40E_SUCCESS;
4857 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4858 struct i40e_macvlan_filter *mv_f,
4863 struct i40e_mac_filter *f;
4865 if (num < vsi->mac_num)
4866 return I40E_ERR_PARAM;
4868 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4870 PMD_DRV_LOG(ERR, "buffer number not match");
4871 return I40E_ERR_PARAM;
4873 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4875 mv_f[i].vlan_id = vlan;
4876 mv_f[i].filter_type = f->mac_info.filter_type;
4880 return I40E_SUCCESS;
4884 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4887 struct i40e_mac_filter *f;
4888 struct i40e_macvlan_filter *mv_f;
4889 int ret = I40E_SUCCESS;
4891 if (vsi == NULL || vsi->mac_num == 0)
4892 return I40E_ERR_PARAM;
4894 /* Case that no vlan is set */
4895 if (vsi->vlan_num == 0)
4898 num = vsi->mac_num * vsi->vlan_num;
4900 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4902 PMD_DRV_LOG(ERR, "failed to allocate memory");
4903 return I40E_ERR_NO_MEMORY;
4907 if (vsi->vlan_num == 0) {
4908 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4909 (void)rte_memcpy(&mv_f[i].macaddr,
4910 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4911 mv_f[i].vlan_id = 0;
4915 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4916 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4917 vsi->vlan_num, &f->mac_info.mac_addr);
4918 if (ret != I40E_SUCCESS)
4924 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4932 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4934 struct i40e_macvlan_filter *mv_f;
4936 int ret = I40E_SUCCESS;
4938 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4939 return I40E_ERR_PARAM;
4941 /* If it's already set, just return */
4942 if (i40e_find_vlan_filter(vsi,vlan))
4943 return I40E_SUCCESS;
4945 mac_num = vsi->mac_num;
4948 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4949 return I40E_ERR_PARAM;
4952 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4955 PMD_DRV_LOG(ERR, "failed to allocate memory");
4956 return I40E_ERR_NO_MEMORY;
4959 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4961 if (ret != I40E_SUCCESS)
4964 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4966 if (ret != I40E_SUCCESS)
4969 i40e_set_vlan_filter(vsi, vlan, 1);
4979 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4981 struct i40e_macvlan_filter *mv_f;
4983 int ret = I40E_SUCCESS;
4986 * Vlan 0 is the generic filter for untagged packets
4987 * and can't be removed.
4989 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4990 return I40E_ERR_PARAM;
4992 /* If can't find it, just return */
4993 if (!i40e_find_vlan_filter(vsi, vlan))
4994 return I40E_ERR_PARAM;
4996 mac_num = vsi->mac_num;
4999 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5000 return I40E_ERR_PARAM;
5003 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5006 PMD_DRV_LOG(ERR, "failed to allocate memory");
5007 return I40E_ERR_NO_MEMORY;
5010 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5012 if (ret != I40E_SUCCESS)
5015 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5017 if (ret != I40E_SUCCESS)
5020 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5021 if (vsi->vlan_num == 1) {
5022 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5023 if (ret != I40E_SUCCESS)
5026 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5027 if (ret != I40E_SUCCESS)
5031 i40e_set_vlan_filter(vsi, vlan, 0);
5041 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5043 struct i40e_mac_filter *f;
5044 struct i40e_macvlan_filter *mv_f;
5045 int i, vlan_num = 0;
5046 int ret = I40E_SUCCESS;
5048 /* If it's add and we've config it, return */
5049 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5051 return I40E_SUCCESS;
5052 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5053 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5056 * If vlan_num is 0, that's the first time to add mac,
5057 * set mask for vlan_id 0.
5059 if (vsi->vlan_num == 0) {
5060 i40e_set_vlan_filter(vsi, 0, 1);
5063 vlan_num = vsi->vlan_num;
5064 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5065 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5068 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5070 PMD_DRV_LOG(ERR, "failed to allocate memory");
5071 return I40E_ERR_NO_MEMORY;
5074 for (i = 0; i < vlan_num; i++) {
5075 mv_f[i].filter_type = mac_filter->filter_type;
5076 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5080 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5081 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5082 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5083 &mac_filter->mac_addr);
5084 if (ret != I40E_SUCCESS)
5088 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5089 if (ret != I40E_SUCCESS)
5092 /* Add the mac addr into mac list */
5093 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5095 PMD_DRV_LOG(ERR, "failed to allocate memory");
5096 ret = I40E_ERR_NO_MEMORY;
5099 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5101 f->mac_info.filter_type = mac_filter->filter_type;
5102 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5113 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5115 struct i40e_mac_filter *f;
5116 struct i40e_macvlan_filter *mv_f;
5118 enum rte_mac_filter_type filter_type;
5119 int ret = I40E_SUCCESS;
5121 /* Can't find it, return an error */
5122 f = i40e_find_mac_filter(vsi, addr);
5124 return I40E_ERR_PARAM;
5126 vlan_num = vsi->vlan_num;
5127 filter_type = f->mac_info.filter_type;
5128 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5129 filter_type == RTE_MACVLAN_HASH_MATCH) {
5130 if (vlan_num == 0) {
5131 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5132 return I40E_ERR_PARAM;
5134 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5135 filter_type == RTE_MAC_HASH_MATCH)
5138 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5140 PMD_DRV_LOG(ERR, "failed to allocate memory");
5141 return I40E_ERR_NO_MEMORY;
5144 for (i = 0; i < vlan_num; i++) {
5145 mv_f[i].filter_type = filter_type;
5146 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5149 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5150 filter_type == RTE_MACVLAN_HASH_MATCH) {
5151 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5152 if (ret != I40E_SUCCESS)
5156 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5157 if (ret != I40E_SUCCESS)
5160 /* Remove the mac addr into mac list */
5161 TAILQ_REMOVE(&vsi->mac_list, f, next);
5171 /* Configure hash enable flags for RSS */
5173 i40e_config_hena(uint64_t flags)
5180 if (flags & ETH_RSS_FRAG_IPV4)
5181 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5182 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5183 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5184 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5185 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5186 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5187 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5188 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5189 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5190 if (flags & ETH_RSS_FRAG_IPV6)
5191 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5192 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5193 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5194 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5195 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5196 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5197 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5198 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5199 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5200 if (flags & ETH_RSS_L2_PAYLOAD)
5201 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5206 /* Parse the hash enable flags */
5208 i40e_parse_hena(uint64_t flags)
5210 uint64_t rss_hf = 0;
5214 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5215 rss_hf |= ETH_RSS_FRAG_IPV4;
5216 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5217 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5218 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5219 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5220 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5221 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5222 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5223 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5224 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5225 rss_hf |= ETH_RSS_FRAG_IPV6;
5226 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5227 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5228 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5229 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5230 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5231 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5232 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5233 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5234 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5235 rss_hf |= ETH_RSS_L2_PAYLOAD;
5242 i40e_pf_disable_rss(struct i40e_pf *pf)
5244 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5247 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5248 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5249 hena &= ~I40E_RSS_HENA_ALL;
5250 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5251 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5252 I40E_WRITE_FLUSH(hw);
5256 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
5259 uint8_t hash_key_len;
5264 hash_key = (uint32_t *)(rss_conf->rss_key);
5265 hash_key_len = rss_conf->rss_key_len;
5266 if (hash_key != NULL && hash_key_len >=
5267 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5268 /* Fill in RSS hash key */
5269 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5270 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5273 rss_hf = rss_conf->rss_hf;
5274 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5275 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5276 hena &= ~I40E_RSS_HENA_ALL;
5277 hena |= i40e_config_hena(rss_hf);
5278 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5279 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5280 I40E_WRITE_FLUSH(hw);
5286 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5287 struct rte_eth_rss_conf *rss_conf)
5289 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5290 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5293 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5294 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5295 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5296 if (rss_hf != 0) /* Enable RSS */
5298 return 0; /* Nothing to do */
5301 if (rss_hf == 0) /* Disable RSS */
5304 return i40e_hw_rss_hash_set(hw, rss_conf);
5308 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5309 struct rte_eth_rss_conf *rss_conf)
5311 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312 uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
5316 if (hash_key != NULL) {
5317 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5318 hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5319 rss_conf->rss_key_len = i * sizeof(uint32_t);
5321 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5322 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5323 rss_conf->rss_hf = i40e_parse_hena(hena);
5329 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5331 switch (filter_type) {
5332 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5333 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5335 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5336 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5338 case RTE_TUNNEL_FILTER_IMAC_TENID:
5339 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5341 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5342 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5344 case ETH_TUNNEL_FILTER_IMAC:
5345 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5348 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5356 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5357 struct rte_eth_tunnel_filter_conf *tunnel_filter,
5361 uint8_t tun_type = 0;
5363 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5364 struct i40e_vsi *vsi = pf->main_vsi;
5365 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
5366 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
5368 cld_filter = rte_zmalloc("tunnel_filter",
5369 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5372 if (NULL == cld_filter) {
5373 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5376 pfilter = cld_filter;
5378 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5379 sizeof(struct ether_addr));
5380 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5381 sizeof(struct ether_addr));
5383 pfilter->inner_vlan = tunnel_filter->inner_vlan;
5384 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5385 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5386 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5387 &tunnel_filter->ip_addr,
5388 sizeof(pfilter->ipaddr.v4.data));
5390 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5391 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5392 &tunnel_filter->ip_addr,
5393 sizeof(pfilter->ipaddr.v6.data));
5396 /* check tunneled type */
5397 switch (tunnel_filter->tunnel_type) {
5398 case RTE_TUNNEL_TYPE_VXLAN:
5399 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5401 case RTE_TUNNEL_TYPE_NVGRE:
5402 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5405 /* Other tunnel types is not supported. */
5406 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5407 rte_free(cld_filter);
5411 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5414 rte_free(cld_filter);
5418 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5419 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5420 pfilter->tenant_id = tunnel_filter->tenant_id;
5421 pfilter->queue_number = tunnel_filter->queue_id;
5424 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5426 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5429 rte_free(cld_filter);
5434 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5438 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5439 if (pf->vxlan_ports[i] == port)
5447 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5451 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5453 idx = i40e_get_vxlan_port_idx(pf, port);
5455 /* Check if port already exists */
5457 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5461 /* Now check if there is space to add the new port */
5462 idx = i40e_get_vxlan_port_idx(pf, 0);
5464 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5465 "not adding port %d", port);
5469 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5472 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5476 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5479 /* New port: add it and mark its index in the bitmap */
5480 pf->vxlan_ports[idx] = port;
5481 pf->vxlan_bitmap |= (1 << idx);
5483 if (!(pf->flags & I40E_FLAG_VXLAN))
5484 pf->flags |= I40E_FLAG_VXLAN;
5490 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5493 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5495 if (!(pf->flags & I40E_FLAG_VXLAN)) {
5496 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5500 idx = i40e_get_vxlan_port_idx(pf, port);
5503 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5507 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5508 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5512 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5515 pf->vxlan_ports[idx] = 0;
5516 pf->vxlan_bitmap &= ~(1 << idx);
5518 if (!pf->vxlan_bitmap)
5519 pf->flags &= ~I40E_FLAG_VXLAN;
5524 /* Add UDP tunneling port */
5526 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5527 struct rte_eth_udp_tunnel *udp_tunnel)
5530 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5532 if (udp_tunnel == NULL)
5535 switch (udp_tunnel->prot_type) {
5536 case RTE_TUNNEL_TYPE_VXLAN:
5537 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5540 case RTE_TUNNEL_TYPE_GENEVE:
5541 case RTE_TUNNEL_TYPE_TEREDO:
5542 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5547 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5555 /* Remove UDP tunneling port */
5557 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5558 struct rte_eth_udp_tunnel *udp_tunnel)
5561 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5563 if (udp_tunnel == NULL)
5566 switch (udp_tunnel->prot_type) {
5567 case RTE_TUNNEL_TYPE_VXLAN:
5568 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5570 case RTE_TUNNEL_TYPE_GENEVE:
5571 case RTE_TUNNEL_TYPE_TEREDO:
5572 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5576 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5584 /* Calculate the maximum number of contiguous PF queues that are configured */
5586 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5588 struct rte_eth_dev_data *data = pf->dev_data;
5590 struct i40e_rx_queue *rxq;
5593 for (i = 0; i < pf->lan_nb_qps; i++) {
5594 rxq = data->rx_queues[i];
5595 if (rxq && rxq->q_set)
5606 i40e_pf_config_rss(struct i40e_pf *pf)
5608 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5609 struct rte_eth_rss_conf rss_conf;
5610 uint32_t i, lut = 0;
5614 * If both VMDQ and RSS enabled, not all of PF queues are configured.
5615 * It's necessary to calulate the actual PF queues that are configured.
5617 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5618 num = i40e_pf_calc_configured_queues_num(pf);
5619 num = i40e_align_floor(num);
5621 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5623 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5627 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5631 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5634 lut = (lut << 8) | (j & ((0x1 <<
5635 hw->func_caps.rss_table_entry_width) - 1));
5637 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5640 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5641 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5642 i40e_pf_disable_rss(pf);
5645 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5646 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5647 /* Random default keys */
5648 static uint32_t rss_key_default[] = {0x6b793944,
5649 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5650 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5651 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5653 rss_conf.rss_key = (uint8_t *)rss_key_default;
5654 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5658 return i40e_hw_rss_hash_set(hw, &rss_conf);
5662 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5663 struct rte_eth_tunnel_filter_conf *filter)
5665 if (pf == NULL || filter == NULL) {
5666 PMD_DRV_LOG(ERR, "Invalid parameter");
5670 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5671 PMD_DRV_LOG(ERR, "Invalid queue ID");
5675 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5676 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5680 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5681 (is_zero_ether_addr(filter->outer_mac))) {
5682 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5686 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5687 (is_zero_ether_addr(filter->inner_mac))) {
5688 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5696 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5699 struct rte_eth_tunnel_filter_conf *filter;
5700 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5701 int ret = I40E_SUCCESS;
5703 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5705 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5706 return I40E_ERR_PARAM;
5708 switch (filter_op) {
5709 case RTE_ETH_FILTER_NOP:
5710 if (!(pf->flags & I40E_FLAG_VXLAN))
5711 ret = I40E_NOT_SUPPORTED;
5712 case RTE_ETH_FILTER_ADD:
5713 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5715 case RTE_ETH_FILTER_DELETE:
5716 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5719 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5720 ret = I40E_ERR_PARAM;
5728 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5731 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5734 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5735 ret = i40e_pf_config_rss(pf);
5737 i40e_pf_disable_rss(pf);
5742 /* Get the symmetric hash enable configurations per port */
5744 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5746 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5748 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5751 /* Set the symmetric hash enable configurations per port */
5753 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5755 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5758 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5759 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5763 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5765 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5766 PMD_DRV_LOG(INFO, "Symmetric hash has already "
5770 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5772 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5773 I40E_WRITE_FLUSH(hw);
5777 * Get global configurations of hash function type and symmetric hash enable
5778 * per flow type (pctype). Note that global configuration means it affects all
5779 * the ports on the same NIC.
5782 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5783 struct rte_eth_hash_global_conf *g_cfg)
5785 uint32_t reg, mask = I40E_FLOW_TYPES;
5787 enum i40e_filter_pctype pctype;
5789 memset(g_cfg, 0, sizeof(*g_cfg));
5790 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5791 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5792 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5794 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5795 PMD_DRV_LOG(DEBUG, "Hash function is %s",
5796 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5798 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5799 if (!(mask & (1UL << i)))
5801 mask &= ~(1UL << i);
5802 /* Bit set indicats the coresponding flow type is supported */
5803 g_cfg->valid_bit_mask[0] |= (1UL << i);
5804 pctype = i40e_flowtype_to_pctype(i);
5805 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5806 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5807 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5814 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5817 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5819 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5820 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5821 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5822 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5828 * As i40e supports less than 32 flow types, only first 32 bits need to
5831 mask0 = g_cfg->valid_bit_mask[0];
5832 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5834 /* Check if any unsupported flow type configured */
5835 if ((mask0 | i40e_mask) ^ i40e_mask)
5838 if (g_cfg->valid_bit_mask[i])
5846 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5852 * Set global configurations of hash function type and symmetric hash enable
5853 * per flow type (pctype). Note any modifying global configuration will affect
5854 * all the ports on the same NIC.
5857 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5858 struct rte_eth_hash_global_conf *g_cfg)
5863 uint32_t mask0 = g_cfg->valid_bit_mask[0];
5864 enum i40e_filter_pctype pctype;
5866 /* Check the input parameters */
5867 ret = i40e_hash_global_config_check(g_cfg);
5871 for (i = 0; mask0 && i < UINT32_BIT; i++) {
5872 if (!(mask0 & (1UL << i)))
5874 mask0 &= ~(1UL << i);
5875 pctype = i40e_flowtype_to_pctype(i);
5876 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5877 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5878 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5881 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5882 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5884 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5885 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5889 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5890 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5892 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5893 PMD_DRV_LOG(DEBUG, "Hash function already set to "
5897 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5899 /* Use the default, and keep it as it is */
5902 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5905 I40E_WRITE_FLUSH(hw);
5911 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5916 PMD_DRV_LOG(ERR, "Invalid pointer");
5920 switch (info->info_type) {
5921 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5922 i40e_get_symmetric_hash_enable_per_port(hw,
5923 &(info->info.enable));
5925 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5926 ret = i40e_get_hash_filter_global_config(hw,
5927 &(info->info.global_conf));
5930 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5940 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5945 PMD_DRV_LOG(ERR, "Invalid pointer");
5949 switch (info->info_type) {
5950 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5951 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5953 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5954 ret = i40e_set_hash_filter_global_config(hw,
5955 &(info->info.global_conf));
5958 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5967 /* Operations for hash function */
5969 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5970 enum rte_filter_op filter_op,
5973 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5976 switch (filter_op) {
5977 case RTE_ETH_FILTER_NOP:
5979 case RTE_ETH_FILTER_GET:
5980 ret = i40e_hash_filter_get(hw,
5981 (struct rte_eth_hash_filter_info *)arg);
5983 case RTE_ETH_FILTER_SET:
5984 ret = i40e_hash_filter_set(hw,
5985 (struct rte_eth_hash_filter_info *)arg);
5988 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5998 * Configure ethertype filter, which can director packet by filtering
5999 * with mac address and ether_type or only ether_type
6002 i40e_ethertype_filter_set(struct i40e_pf *pf,
6003 struct rte_eth_ethertype_filter *filter,
6006 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6007 struct i40e_control_filter_stats stats;
6011 if (filter->queue >= pf->dev_data->nb_rx_queues) {
6012 PMD_DRV_LOG(ERR, "Invalid queue ID");
6015 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6016 filter->ether_type == ETHER_TYPE_IPv6) {
6017 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6018 " control packet filter.", filter->ether_type);
6021 if (filter->ether_type == ETHER_TYPE_VLAN)
6022 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
6025 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
6026 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
6027 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
6028 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
6029 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
6031 memset(&stats, 0, sizeof(stats));
6032 ret = i40e_aq_add_rem_control_packet_filter(hw,
6033 filter->mac_addr.addr_bytes,
6034 filter->ether_type, flags,
6036 filter->queue, add, &stats, NULL);
6038 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
6039 " mac_etype_used = %u, etype_used = %u,"
6040 " mac_etype_free = %u, etype_free = %u\n",
6041 ret, stats.mac_etype_used, stats.etype_used,
6042 stats.mac_etype_free, stats.etype_free);
6049 * Handle operations for ethertype filter.
6052 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
6053 enum rte_filter_op filter_op,
6056 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6059 if (filter_op == RTE_ETH_FILTER_NOP)
6063 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6068 switch (filter_op) {
6069 case RTE_ETH_FILTER_ADD:
6070 ret = i40e_ethertype_filter_set(pf,
6071 (struct rte_eth_ethertype_filter *)arg,
6074 case RTE_ETH_FILTER_DELETE:
6075 ret = i40e_ethertype_filter_set(pf,
6076 (struct rte_eth_ethertype_filter *)arg,
6080 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6088 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
6089 enum rte_filter_type filter_type,
6090 enum rte_filter_op filter_op,
6098 switch (filter_type) {
6099 case RTE_ETH_FILTER_HASH:
6100 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
6102 case RTE_ETH_FILTER_MACVLAN:
6103 ret = i40e_mac_filter_handle(dev, filter_op, arg);
6105 case RTE_ETH_FILTER_ETHERTYPE:
6106 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
6108 case RTE_ETH_FILTER_TUNNEL:
6109 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
6111 case RTE_ETH_FILTER_FDIR:
6112 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
6115 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6125 * As some registers wouldn't be reset unless a global hardware reset,
6126 * hardware initialization is needed to put those registers into an
6127 * expected initial state.
6130 i40e_hw_init(struct i40e_hw *hw)
6132 /* clear the PF Queue Filter control register */
6133 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
6135 /* Disable symmetric hash per port */
6136 i40e_set_symmetric_hash_enable_per_port(hw, 0);
6139 enum i40e_filter_pctype
6140 i40e_flowtype_to_pctype(uint16_t flow_type)
6142 static const enum i40e_filter_pctype pctype_table[] = {
6143 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
6144 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
6145 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
6146 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
6147 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
6148 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
6149 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
6150 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
6151 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
6152 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
6153 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
6154 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
6155 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
6156 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
6157 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
6158 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
6159 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
6160 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
6161 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
6164 return pctype_table[flow_type];
6168 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
6170 static const uint16_t flowtype_table[] = {
6171 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
6172 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6173 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
6174 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6175 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
6176 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6177 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
6178 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6179 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
6180 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
6181 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6182 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
6183 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6184 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
6185 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6186 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
6187 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6188 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
6189 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
6192 return flowtype_table[pctype];
6196 * On X710, performance number is far from the expectation on recent firmware
6197 * versions; on XL710, performance number is also far from the expectation on
6198 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
6199 * mode is enabled and port MAC address is equal to the packet destination MAC
6200 * address. The fix for this issue may not be integrated in the following
6201 * firmware version. So the workaround in software driver is needed. It needs
6202 * to modify the initial values of 3 internal only registers for both X710 and
6203 * XL710. Note that the values for X710 or XL710 could be different, and the
6204 * workaround can be removed when it is fixed in firmware in the future.
6207 /* For both X710 and XL710 */
6208 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
6209 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
6211 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
6212 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
6215 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
6217 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
6218 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
6221 i40e_configure_registers(struct i40e_hw *hw)
6227 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
6228 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
6229 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
6235 for (i = 0; i < RTE_DIM(reg_table); i++) {
6236 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
6237 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
6239 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
6242 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
6245 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
6248 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
6252 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
6253 reg_table[i].addr, reg);
6254 if (reg == reg_table[i].val)
6257 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
6258 reg_table[i].val, NULL);
6260 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
6261 "address of 0x%"PRIx32, reg_table[i].val,
6265 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
6266 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
6270 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
6271 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
6272 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
6273 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
6275 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
6280 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
6281 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
6285 /* Configure for double VLAN RX stripping */
6286 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
6287 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
6288 reg |= I40E_VSI_TSR_QINQ_CONFIG;
6289 ret = i40e_aq_debug_write_register(hw,
6290 I40E_VSI_TSR(vsi->vsi_id),
6293 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
6295 return I40E_ERR_CONFIG;
6299 /* Configure for double VLAN TX insertion */
6300 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
6301 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
6302 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
6303 ret = i40e_aq_debug_write_register(hw,
6304 I40E_VSI_L2TAGSTXVALID(
6305 vsi->vsi_id), reg, NULL);
6307 PMD_DRV_LOG(ERR, "Failed to update "
6308 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
6309 return I40E_ERR_CONFIG;
6317 * i40e_aq_add_mirror_rule
6318 * @hw: pointer to the hardware structure
6319 * @seid: VEB seid to add mirror rule to
6320 * @dst_id: destination vsi seid
6321 * @entries: Buffer which contains the entities to be mirrored
6322 * @count: number of entities contained in the buffer
6323 * @rule_id:the rule_id of the rule to be added
6325 * Add a mirror rule for a given veb.
6328 static enum i40e_status_code
6329 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
6330 uint16_t seid, uint16_t dst_id,
6331 uint16_t rule_type, uint16_t *entries,
6332 uint16_t count, uint16_t *rule_id)
6334 struct i40e_aq_desc desc;
6335 struct i40e_aqc_add_delete_mirror_rule cmd;
6336 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
6337 (struct i40e_aqc_add_delete_mirror_rule_completion *)
6340 enum i40e_status_code status;
6342 i40e_fill_default_direct_cmd_desc(&desc,
6343 i40e_aqc_opc_add_mirror_rule);
6344 memset(&cmd, 0, sizeof(cmd));
6346 buff_len = sizeof(uint16_t) * count;
6347 desc.datalen = rte_cpu_to_le_16(buff_len);
6349 desc.flags |= rte_cpu_to_le_16(
6350 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6351 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6352 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6353 cmd.num_entries = rte_cpu_to_le_16(count);
6354 cmd.seid = rte_cpu_to_le_16(seid);
6355 cmd.destination = rte_cpu_to_le_16(dst_id);
6357 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6358 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
6359 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
6361 " mirror_rules_used = %u, mirror_rules_free = %u,",
6362 hw->aq.asq_last_status, resp->rule_id,
6363 resp->mirror_rules_used, resp->mirror_rules_free);
6364 *rule_id = rte_le_to_cpu_16(resp->rule_id);
6370 * i40e_aq_del_mirror_rule
6371 * @hw: pointer to the hardware structure
6372 * @seid: VEB seid to add mirror rule to
6373 * @entries: Buffer which contains the entities to be mirrored
6374 * @count: number of entities contained in the buffer
6375 * @rule_id:the rule_id of the rule to be delete
6377 * Delete a mirror rule for a given veb.
6380 static enum i40e_status_code
6381 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
6382 uint16_t seid, uint16_t rule_type, uint16_t *entries,
6383 uint16_t count, uint16_t rule_id)
6385 struct i40e_aq_desc desc;
6386 struct i40e_aqc_add_delete_mirror_rule cmd;
6387 uint16_t buff_len = 0;
6388 enum i40e_status_code status;
6391 i40e_fill_default_direct_cmd_desc(&desc,
6392 i40e_aqc_opc_delete_mirror_rule);
6393 memset(&cmd, 0, sizeof(cmd));
6394 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
6395 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
6397 cmd.num_entries = count;
6398 buff_len = sizeof(uint16_t) * count;
6399 desc.datalen = rte_cpu_to_le_16(buff_len);
6400 buff = (void *)entries;
6402 /* rule id is filled in destination field for deleting mirror rule */
6403 cmd.destination = rte_cpu_to_le_16(rule_id);
6405 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6406 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6407 cmd.seid = rte_cpu_to_le_16(seid);
6409 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6410 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
6416 * i40e_mirror_rule_set
6417 * @dev: pointer to the hardware structure
6418 * @mirror_conf: mirror rule info
6419 * @sw_id: mirror rule's sw_id
6420 * @on: enable/disable
6422 * set a mirror rule.
6426 i40e_mirror_rule_set(struct rte_eth_dev *dev,
6427 struct rte_eth_mirror_conf *mirror_conf,
6428 uint8_t sw_id, uint8_t on)
6430 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6431 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6432 struct i40e_mirror_rule *it, *mirr_rule = NULL;
6433 struct i40e_mirror_rule *parent = NULL;
6434 uint16_t seid, dst_seid, rule_id;
6438 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
6440 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
6441 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
6442 " without veb or vfs.");
6445 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
6446 PMD_DRV_LOG(ERR, "mirror table is full.");
6449 if (mirror_conf->dst_pool > pf->vf_num) {
6450 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6451 mirror_conf->dst_pool);
6455 seid = pf->main_vsi->veb->seid;
6457 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6458 if (sw_id <= it->index) {
6464 if (mirr_rule && sw_id == mirr_rule->index) {
6466 PMD_DRV_LOG(ERR, "mirror rule exists.");
6469 ret = i40e_aq_del_mirror_rule(hw, seid,
6470 mirr_rule->rule_type,
6472 mirr_rule->num_entries, mirr_rule->id);
6474 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6475 " ret = %d, aq_err = %d.",
6476 ret, hw->aq.asq_last_status);
6479 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6480 rte_free(mirr_rule);
6481 pf->nb_mirror_rule--;
6485 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6489 mirr_rule = rte_zmalloc("i40e_mirror_rule",
6490 sizeof(struct i40e_mirror_rule) , 0);
6492 PMD_DRV_LOG(ERR, "failed to allocate memory");
6493 return I40E_ERR_NO_MEMORY;
6495 switch (mirror_conf->rule_type) {
6496 case ETH_MIRROR_VLAN:
6497 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6498 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6499 mirr_rule->entries[j] =
6500 mirror_conf->vlan.vlan_id[i];
6505 PMD_DRV_LOG(ERR, "vlan is not specified.");
6506 rte_free(mirr_rule);
6509 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6511 case ETH_MIRROR_VIRTUAL_POOL_UP:
6512 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6513 /* check if the specified pool bit is out of range */
6514 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6515 PMD_DRV_LOG(ERR, "pool mask is out of range.");
6516 rte_free(mirr_rule);
6519 for (i = 0, j = 0; i < pf->vf_num; i++) {
6520 if (mirror_conf->pool_mask & (1ULL << i)) {
6521 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6525 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6526 /* add pf vsi to entries */
6527 mirr_rule->entries[j] = pf->main_vsi_seid;
6531 PMD_DRV_LOG(ERR, "pool is not specified.");
6532 rte_free(mirr_rule);
6535 /* egress and ingress in aq commands means from switch but not port */
6536 mirr_rule->rule_type =
6537 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6538 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6539 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6541 case ETH_MIRROR_UPLINK_PORT:
6542 /* egress and ingress in aq commands means from switch but not port*/
6543 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6545 case ETH_MIRROR_DOWNLINK_PORT:
6546 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6549 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6550 mirror_conf->rule_type);
6551 rte_free(mirr_rule);
6555 /* If the dst_pool is equal to vf_num, consider it as PF */
6556 if (mirror_conf->dst_pool == pf->vf_num)
6557 dst_seid = pf->main_vsi_seid;
6559 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6561 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6562 mirr_rule->rule_type, mirr_rule->entries,
6565 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6566 " ret = %d, aq_err = %d.",
6567 ret, hw->aq.asq_last_status);
6568 rte_free(mirr_rule);
6572 mirr_rule->index = sw_id;
6573 mirr_rule->num_entries = j;
6574 mirr_rule->id = rule_id;
6575 mirr_rule->dst_vsi_seid = dst_seid;
6578 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6580 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6582 pf->nb_mirror_rule++;
6587 * i40e_mirror_rule_reset
6588 * @dev: pointer to the device
6589 * @sw_id: mirror rule's sw_id
6591 * reset a mirror rule.
6595 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6597 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6598 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6599 struct i40e_mirror_rule *it, *mirr_rule = NULL;
6603 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6605 seid = pf->main_vsi->veb->seid;
6607 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6608 if (sw_id == it->index) {
6614 ret = i40e_aq_del_mirror_rule(hw, seid,
6615 mirr_rule->rule_type,
6617 mirr_rule->num_entries, mirr_rule->id);
6619 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6620 " status = %d, aq_err = %d.",
6621 ret, hw->aq.asq_last_status);
6624 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6625 rte_free(mirr_rule);
6626 pf->nb_mirror_rule--;
6628 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6635 i40e_timesync_enable(struct rte_eth_dev *dev)
6637 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6638 struct rte_eth_link *link = &dev->data->dev_link;
6639 uint32_t tsync_ctl_l;
6640 uint32_t tsync_ctl_h;
6641 uint32_t tsync_inc_l;
6642 uint32_t tsync_inc_h;
6644 switch (link->link_speed) {
6645 case ETH_LINK_SPEED_40G:
6646 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6647 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6649 case ETH_LINK_SPEED_10G:
6650 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6651 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6653 case ETH_LINK_SPEED_1000:
6654 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6655 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6662 /* Clear timesync registers. */
6663 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6664 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6665 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6666 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6667 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6668 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6669 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6671 /* Set the timesync increment value. */
6672 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6673 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6675 /* Enable timestamping of PTP packets. */
6676 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6677 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6679 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6680 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6681 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6683 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6684 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6690 i40e_timesync_disable(struct rte_eth_dev *dev)
6692 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6693 uint32_t tsync_ctl_l;
6694 uint32_t tsync_ctl_h;
6696 /* Disable timestamping of transmitted PTP packets. */
6697 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6698 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6700 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6701 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6703 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6704 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6706 /* Set the timesync increment value. */
6707 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6708 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6714 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6715 struct timespec *timestamp, uint32_t flags)
6717 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6718 uint32_t sync_status;
6721 uint32_t index = flags & 0x03;
6723 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6724 if ((sync_status & (1 << index)) == 0)
6727 rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6728 rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6730 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6731 timestamp->tv_nsec = 0;
6737 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6738 struct timespec *timestamp)
6740 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6741 uint32_t sync_status;
6745 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6746 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6749 tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6750 tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6752 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6753 timestamp->tv_nsec = 0;
6759 * i40e_parse_dcb_configure - parse dcb configure from user
6760 * @dev: the device being configured
6761 * @dcb_cfg: pointer of the result of parse
6762 * @*tc_map: bit map of enabled traffic classes
6764 * Returns 0 on success, negative value on failure
6767 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
6768 struct i40e_dcbx_config *dcb_cfg,
6771 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
6772 uint8_t i, tc_bw, bw_lf;
6774 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
6776 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6777 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
6778 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
6782 /* assume each tc has the same bw */
6783 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
6784 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6785 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
6786 /* to ensure the sum of tcbw is equal to 100 */
6787 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
6788 for (i = 0; i < bw_lf; i++)
6789 dcb_cfg->etscfg.tcbwtable[i]++;
6791 /* assume each tc has the same Transmission Selection Algorithm */
6792 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6793 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
6795 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
6796 dcb_cfg->etscfg.prioritytable[i] =
6797 dcb_rx_conf->dcb_tc[i];
6799 /* FW needs one App to configure HW */
6800 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
6801 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
6802 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
6803 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
6805 if (dcb_rx_conf->nb_tcs == 0)
6806 *tc_map = 1; /* tc0 only */
6808 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
6810 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
6811 dcb_cfg->pfc.willing = 0;
6812 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
6813 dcb_cfg->pfc.pfcenable = *tc_map;
6819 * i40e_vsi_get_bw_info - Query VSI BW Information
6820 * @vsi: the VSI being queried
6822 * Returns 0 on success, negative value on failure
6825 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
6827 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
6828 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
6829 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6833 /* Get the VSI level BW configuration */
6834 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
6837 "couldn't get PF vsi bw config, err %s aq_err %s\n",
6838 i40e_stat_str(hw, ret),
6839 i40e_aq_str(hw, hw->aq.asq_last_status));
6843 /* Get the VSI level BW configuration per TC */
6844 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6848 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
6849 i40e_stat_str(hw, ret),
6850 i40e_aq_str(hw, hw->aq.asq_last_status));
6854 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
6855 PMD_INIT_LOG(WARNING,
6856 "Enabled TCs mismatch from querying VSI BW info"
6857 " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
6858 bw_ets_config.tc_valid_bits);
6859 /* Still continuing */
6862 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
6863 vsi->bw_info.bw_max_quanta = bw_config.max_bw;
6864 tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
6865 (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
6866 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6867 vsi->bw_info.bw_ets_share_credits[i] =
6868 bw_ets_config.share_credits[i];
6869 vsi->bw_info.bw_ets_limit_credits[i] =
6870 rte_le_to_cpu_16(bw_ets_config.credits[i]);
6871 /* 3 bits out of 4 for each TC */
6872 vsi->bw_info.bw_ets_max_quanta[i] =
6873 (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
6875 "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
6876 __func__, vsi->seid, i, bw_config.qs_handles[i]);
6883 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
6884 struct i40e_aqc_vsi_properties_data *info,
6885 uint8_t enabled_tcmap)
6887 int ret, i, total_tc = 0;
6888 uint16_t qpnum_per_tc, bsf, qp_idx;
6889 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
6891 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
6892 if (ret != I40E_SUCCESS)
6895 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6896 if (enabled_tcmap & (1 << i))
6901 vsi->enabled_tc = enabled_tcmap;
6903 qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
6904 /* Number of queues per enabled TC */
6905 if (qpnum_per_tc == 0) {
6906 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
6907 return I40E_ERR_INVALID_QP_ID;
6909 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
6911 bsf = rte_bsf32(qpnum_per_tc);
6914 * Configure TC and queue mapping parameters, for enabled TC,
6915 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
6916 * default queue will serve it.
6919 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6920 if (vsi->enabled_tc & (1 << i)) {
6921 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
6922 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
6923 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
6924 qp_idx += qpnum_per_tc;
6926 info->tc_mapping[i] = 0;
6929 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
6930 if (vsi->type == I40E_VSI_SRIOV) {
6931 info->mapping_flags |=
6932 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
6933 for (i = 0; i < vsi->nb_qps; i++)
6934 info->queue_mapping[i] =
6935 rte_cpu_to_le_16(vsi->base_queue + i);
6937 info->mapping_flags |=
6938 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
6939 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
6941 info->valid_sections |=
6942 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
6944 return I40E_SUCCESS;
6948 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
6949 * @vsi: VSI to be configured
6950 * @tc_map: enabled TC bitmap
6952 * Returns 0 on success, negative value on failure
6955 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
6957 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
6958 struct i40e_vsi_context ctxt;
6959 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6963 /* Check if enabled_tc is same as existing or new TCs */
6964 if (vsi->enabled_tc == tc_map)
6967 /* configure tc bandwidth */
6968 memset(&bw_data, 0, sizeof(bw_data));
6969 bw_data.tc_valid_bits = tc_map;
6970 /* Enable ETS TCs with equal BW Share for now across all VSIs */
6971 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6972 if (tc_map & BIT_ULL(i))
6973 bw_data.tc_bw_credits[i] = 1;
6975 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
6977 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
6978 " per TC failed = %d",
6979 hw->aq.asq_last_status);
6982 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
6983 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
6985 /* Update Queue Pairs Mapping for currently enabled UPs */
6986 ctxt.seid = vsi->seid;
6987 ctxt.pf_num = hw->pf_id;
6989 ctxt.uplink_seid = vsi->uplink_seid;
6990 ctxt.info = vsi->info;
6992 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
6996 /* Update the VSI after updating the VSI queue-mapping information */
6997 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6999 PMD_INIT_LOG(ERR, "Failed to configure "
7000 "TC queue mapping = %d",
7001 hw->aq.asq_last_status);
7004 /* update the local VSI info with updated queue map */
7005 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
7006 sizeof(vsi->info.tc_mapping));
7007 (void)rte_memcpy(&vsi->info.queue_mapping,
7008 &ctxt.info.queue_mapping,
7009 sizeof(vsi->info.queue_mapping));
7010 vsi->info.mapping_flags = ctxt.info.mapping_flags;
7011 vsi->info.valid_sections = 0;
7013 /* Update current VSI BW information */
7014 ret = i40e_vsi_get_bw_info(vsi);
7017 "Failed updating vsi bw info, err %s aq_err %s",
7018 i40e_stat_str(hw, ret),
7019 i40e_aq_str(hw, hw->aq.asq_last_status));
7023 vsi->enabled_tc = tc_map;
7030 * i40e_dcb_hw_configure - program the dcb setting to hw
7031 * @pf: pf the configuration is taken on
7032 * @new_cfg: new configuration
7033 * @tc_map: enabled TC bitmap
7035 * Returns 0 on success, negative value on failure
7037 static enum i40e_status_code
7038 i40e_dcb_hw_configure(struct i40e_pf *pf,
7039 struct i40e_dcbx_config *new_cfg,
7042 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7043 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
7044 struct i40e_vsi *main_vsi = pf->main_vsi;
7045 struct i40e_vsi_list *vsi_list;
7049 /* Use the FW API if FW > v4.4*/
7050 if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
7051 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
7052 " to configure DCB");
7053 return I40E_ERR_FIRMWARE_API_VERSION;
7056 /* Check if need reconfiguration */
7057 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
7058 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
7059 return I40E_SUCCESS;
7062 /* Copy the new config to the current config */
7063 *old_cfg = *new_cfg;
7064 old_cfg->etsrec = old_cfg->etscfg;
7065 ret = i40e_set_dcb_config(hw);
7068 "Set DCB Config failed, err %s aq_err %s\n",
7069 i40e_stat_str(hw, ret),
7070 i40e_aq_str(hw, hw->aq.asq_last_status));
7073 /* set receive Arbiter to RR mode and ETS scheme by default */
7074 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
7075 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
7076 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
7077 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
7078 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
7079 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
7080 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
7081 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
7082 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
7083 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
7084 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
7085 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
7086 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
7088 /* get local mib to check whether it is configured correctly */
7090 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
7091 /* Get Local DCB Config */
7092 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
7093 &hw->local_dcbx_config);
7095 /* Update each VSI */
7096 i40e_vsi_config_tc(main_vsi, tc_map);
7097 if (main_vsi->veb) {
7098 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
7099 /* Beside main VSI, only enable default
7102 ret = i40e_vsi_config_tc(vsi_list->vsi,
7103 I40E_DEFAULT_TCMAP);
7105 PMD_INIT_LOG(WARNING,
7106 "Failed configuring TC for VSI seid=%d\n",
7107 vsi_list->vsi->seid);
7111 return I40E_SUCCESS;
7115 * i40e_dcb_init_configure - initial dcb config
7116 * @dev: device being configured
7117 * @sw_dcb: indicate whether dcb is sw configured or hw offload
7119 * Returns 0 on success, negative value on failure
7122 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
7124 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7125 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7128 if ((pf->flags & I40E_FLAG_DCB) == 0) {
7129 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7133 /* DCB initialization:
7134 * Update DCB configuration from the Firmware and configure
7135 * LLDP MIB change event.
7137 if (sw_dcb == TRUE) {
7138 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
7139 if (ret != I40E_SUCCESS)
7140 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
7142 ret = i40e_init_dcb(hw);
7143 /* if sw_dcb, lldp agent is stopped, the return from
7144 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
7147 if (ret != I40E_SUCCESS &&
7148 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
7149 memset(&hw->local_dcbx_config, 0,
7150 sizeof(struct i40e_dcbx_config));
7151 /* set dcb default configuration */
7152 hw->local_dcbx_config.etscfg.willing = 0;
7153 hw->local_dcbx_config.etscfg.maxtcs = 0;
7154 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
7155 hw->local_dcbx_config.etscfg.tsatable[0] =
7157 hw->local_dcbx_config.etsrec =
7158 hw->local_dcbx_config.etscfg;
7159 hw->local_dcbx_config.pfc.willing = 0;
7160 hw->local_dcbx_config.pfc.pfccap =
7161 I40E_MAX_TRAFFIC_CLASS;
7162 /* FW needs one App to configure HW */
7163 hw->local_dcbx_config.numapps = 1;
7164 hw->local_dcbx_config.app[0].selector =
7165 I40E_APP_SEL_ETHTYPE;
7166 hw->local_dcbx_config.app[0].priority = 3;
7167 hw->local_dcbx_config.app[0].protocolid =
7168 I40E_APP_PROTOID_FCOE;
7169 ret = i40e_set_dcb_config(hw);
7171 PMD_INIT_LOG(ERR, "default dcb config fails."
7172 " err = %d, aq_err = %d.", ret,
7173 hw->aq.asq_last_status);
7177 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
7178 " aq_err = %d.", ret,
7179 hw->aq.asq_last_status);
7183 ret = i40e_aq_start_lldp(hw, NULL);
7184 if (ret != I40E_SUCCESS)
7185 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
7187 ret = i40e_init_dcb(hw);
7189 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
7190 PMD_INIT_LOG(ERR, "HW doesn't support"
7195 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
7196 " aq_err = %d.", ret,
7197 hw->aq.asq_last_status);
7205 * i40e_dcb_setup - setup dcb related config
7206 * @dev: device being configured
7208 * Returns 0 on success, negative value on failure
7211 i40e_dcb_setup(struct rte_eth_dev *dev)
7213 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7214 struct i40e_dcbx_config dcb_cfg;
7218 if ((pf->flags & I40E_FLAG_DCB) == 0) {
7219 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7223 if (pf->vf_num != 0 ||
7224 (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
7225 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
7227 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
7229 PMD_INIT_LOG(ERR, "invalid dcb config");
7232 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
7234 PMD_INIT_LOG(ERR, "dcb sw configure fails");
7241 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
7242 struct rte_eth_dcb_info *dcb_info)
7244 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7245 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7246 struct i40e_vsi *vsi = pf->main_vsi;
7247 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
7248 uint16_t bsf, tc_mapping;
7251 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7252 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
7254 dcb_info->nb_tcs = 1;
7255 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7256 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
7257 for (i = 0; i < dcb_info->nb_tcs; i++)
7258 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
7260 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7261 if (vsi->enabled_tc & (1 << i)) {
7262 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
7263 /* only main vsi support multi TCs */
7264 dcb_info->tc_queue.tc_rxq[0][i].base =
7265 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
7266 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
7267 dcb_info->tc_queue.tc_txq[0][i].base =
7268 dcb_info->tc_queue.tc_rxq[0][i].base;
7269 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
7270 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
7271 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
7272 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
7273 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;