drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 244                              struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct rte_ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static void i40e_dev_alarm_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct rte_ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
 404 int i40e_logtype_rx;
 405 #endif
 406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
 407 int i40e_logtype_tx;
 408 #endif
 409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
 410 int i40e_logtype_tx_free;
 411 #endif
 412
 413 static const char *const valid_keys[] = {
 414         ETH_I40E_FLOATING_VEB_ARG,
 415         ETH_I40E_FLOATING_VEB_LIST_ARG,
 416         ETH_I40E_SUPPORT_MULTI_DRIVER,
 417         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 418         ETH_I40E_USE_LATEST_VEC,
 419         ETH_I40E_VF_MSG_CFG,
 420         NULL};
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 448         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 449         { .vendor_id = 0, /* sentinel */ },
 450 };
 451
 452 static const struct eth_dev_ops i40e_eth_dev_ops = {
 453         .dev_configure                = i40e_dev_configure,
 454         .dev_start                    = i40e_dev_start,
 455         .dev_stop                     = i40e_dev_stop,
 456         .dev_close                    = i40e_dev_close,
 457         .dev_reset                    = i40e_dev_reset,
 458         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 459         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 460         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 461         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 462         .dev_set_link_up              = i40e_dev_set_link_up,
 463         .dev_set_link_down            = i40e_dev_set_link_down,
 464         .link_update                  = i40e_dev_link_update,
 465         .stats_get                    = i40e_dev_stats_get,
 466         .xstats_get                   = i40e_dev_xstats_get,
 467         .xstats_get_names             = i40e_dev_xstats_get_names,
 468         .stats_reset                  = i40e_dev_stats_reset,
 469         .xstats_reset                 = i40e_dev_stats_reset,
 470         .fw_version_get               = i40e_fw_version_get,
 471         .dev_infos_get                = i40e_dev_info_get,
 472         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 473         .vlan_filter_set              = i40e_vlan_filter_set,
 474         .vlan_tpid_set                = i40e_vlan_tpid_set,
 475         .vlan_offload_set             = i40e_vlan_offload_set,
 476         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 477         .vlan_pvid_set                = i40e_vlan_pvid_set,
 478         .rx_queue_start               = i40e_dev_rx_queue_start,
 479         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 480         .tx_queue_start               = i40e_dev_tx_queue_start,
 481         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 482         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 483         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 484         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 485         .rx_queue_release             = i40e_dev_rx_queue_release,
 486         .rx_queue_count               = i40e_dev_rx_queue_count,
 487         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 488         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 489         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 490         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 491         .tx_queue_release             = i40e_dev_tx_queue_release,
 492         .dev_led_on                   = i40e_dev_led_on,
 493         .dev_led_off                  = i40e_dev_led_off,
 494         .flow_ctrl_get                = i40e_flow_ctrl_get,
 495         .flow_ctrl_set                = i40e_flow_ctrl_set,
 496         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 497         .mac_addr_add                 = i40e_macaddr_add,
 498         .mac_addr_remove              = i40e_macaddr_remove,
 499         .reta_update                  = i40e_dev_rss_reta_update,
 500         .reta_query                   = i40e_dev_rss_reta_query,
 501         .rss_hash_update              = i40e_dev_rss_hash_update,
 502         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 503         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 504         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 505         .filter_ctrl                  = i40e_dev_filter_ctrl,
 506         .rxq_info_get                 = i40e_rxq_info_get,
 507         .txq_info_get                 = i40e_txq_info_get,
 508         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 509         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 510         .mirror_rule_set              = i40e_mirror_rule_set,
 511         .mirror_rule_reset            = i40e_mirror_rule_reset,
 512         .timesync_enable              = i40e_timesync_enable,
 513         .timesync_disable             = i40e_timesync_disable,
 514         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 515         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 516         .get_dcb_info                 = i40e_dev_get_dcb_info,
 517         .timesync_adjust_time         = i40e_timesync_adjust_time,
 518         .timesync_read_time           = i40e_timesync_read_time,
 519         .timesync_write_time          = i40e_timesync_write_time,
 520         .get_reg                      = i40e_get_regs,
 521         .get_eeprom_length            = i40e_get_eeprom_length,
 522         .get_eeprom                   = i40e_get_eeprom,
 523         .get_module_info              = i40e_get_module_info,
 524         .get_module_eeprom            = i40e_get_module_eeprom,
 525         .mac_addr_set                 = i40e_set_default_mac_addr,
 526         .mtu_set                      = i40e_dev_mtu_set,
 527         .tm_ops_get                   = i40e_tm_ops_get,
 528         .tx_done_cleanup              = i40e_tx_done_cleanup,
 529 };
 530
 531 /* store statistics names and its offset in stats structure */
 532 struct rte_i40e_xstats_name_off {
 533         char name[RTE_ETH_XSTATS_NAME_SIZE];
 534         unsigned offset;
 535 };
 536
 537 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 538         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 539         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 540         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 541         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 542         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 543                 rx_unknown_protocol)},
 544         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 545         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 546         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 547         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 548 };
 549
 550 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 551                 sizeof(rte_i40e_stats_strings[0]))
 552
 553 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 554         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 555                 tx_dropped_link_down)},
 556         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 557         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 558                 illegal_bytes)},
 559         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 560         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 561                 mac_local_faults)},
 562         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 563                 mac_remote_faults)},
 564         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 565                 rx_length_errors)},
 566         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 567         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 568         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 569         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 570         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 571         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_127)},
 573         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_255)},
 575         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_511)},
 577         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 578                 rx_size_1023)},
 579         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 580                 rx_size_1522)},
 581         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 582                 rx_size_big)},
 583         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 584                 rx_undersize)},
 585         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 586                 rx_oversize)},
 587         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 588                 mac_short_packet_dropped)},
 589         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 590                 rx_fragments)},
 591         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 592         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 593         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_127)},
 595         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_255)},
 597         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_511)},
 599         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 600                 tx_size_1023)},
 601         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 602                 tx_size_1522)},
 603         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 604                 tx_size_big)},
 605         {"rx_flow_director_atr_match_packets",
 606                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 607         {"rx_flow_director_sb_match_packets",
 608                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 609         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 610                 tx_lpi_status)},
 611         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 612                 rx_lpi_status)},
 613         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 614                 tx_lpi_count)},
 615         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 616                 rx_lpi_count)},
 617 };
 618
 619 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 620                 sizeof(rte_i40e_hw_port_strings[0]))
 621
 622 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 623         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_rx)},
 625         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xoff_rx)},
 627 };
 628
 629 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 630                 sizeof(rte_i40e_rxq_prio_strings[0]))
 631
 632 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 633         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 634                 priority_xon_tx)},
 635         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 636                 priority_xoff_tx)},
 637         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 638                 priority_xon_2_xoff)},
 639 };
 640
 641 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 642                 sizeof(rte_i40e_txq_prio_strings[0]))
 643
 644 static int
 645 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 646         struct rte_pci_device *pci_dev)
 647 {
 648         char name[RTE_ETH_NAME_MAX_LEN];
 649         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 650         int i, retval;
 651
 652         if (pci_dev->device.devargs) {
 653                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 654                                 &eth_da);
 655                 if (retval)
 656                         return retval;
 657         }
 658
 659         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 660                 sizeof(struct i40e_adapter),
 661                 eth_dev_pci_specific_init, pci_dev,
 662                 eth_i40e_dev_init, NULL);
 663
 664         if (retval || eth_da.nb_representor_ports < 1)
 665                 return retval;
 666
 667         /* probe VF representor ports */
 668         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 669                 pci_dev->device.name);
 670
 671         if (pf_ethdev == NULL)
 672                 return -ENODEV;
 673
 674         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 675                 struct i40e_vf_representor representor = {
 676                         .vf_id = eth_da.representor_ports[i],
 677                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 678                                 pf_ethdev->data->dev_private)->switch_domain_id,
 679                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 680                                 pf_ethdev->data->dev_private)
 681                 };
 682
 683                 /* representor port net_bdf_port */
 684                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 685                         pci_dev->device.name, eth_da.representor_ports[i]);
 686
 687                 retval = rte_eth_dev_create(&pci_dev->device, name,
 688                         sizeof(struct i40e_vf_representor), NULL, NULL,
 689                         i40e_vf_representor_init, &representor);
 690
 691                 if (retval)
 692                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 693                                 "representor %s.", name);
 694         }
 695
 696         return 0;
 697 }
 698
 699 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 700 {
 701         struct rte_eth_dev *ethdev;
 702
 703         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 704         if (!ethdev)
 705                 return 0;
 706
 707         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 708                 return rte_eth_dev_pci_generic_remove(pci_dev,
 709                                         i40e_vf_representor_uninit);
 710         else
 711                 return rte_eth_dev_pci_generic_remove(pci_dev,
 712                                                 eth_i40e_dev_uninit);
 713 }
 714
 715 static struct rte_pci_driver rte_i40e_pmd = {
 716         .id_table = pci_id_i40e_map,
 717         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 718         .probe = eth_i40e_pci_probe,
 719         .remove = eth_i40e_pci_remove,
 720 };
 721
 722 static inline void
 723 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 724                          uint32_t reg_val)
 725 {
 726         uint32_t ori_reg_val;
 727         struct rte_eth_dev *dev;
 728
 729         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 730         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 731         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 732         if (ori_reg_val != reg_val)
 733                 PMD_DRV_LOG(WARNING,
 734                             "i40e device %s changed global register [0x%08x]."
 735                             " original: 0x%08x, new: 0x%08x",
 736                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 737 }
 738
 739 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 740 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 741 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 742
 743 #ifndef I40E_GLQF_ORT
 744 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 745 #endif
 746 #ifndef I40E_GLQF_PIT
 747 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 748 #endif
 749 #ifndef I40E_GLQF_L3_MAP
 750 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 751 #endif
 752
 753 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 754 {
 755         /*
 756          * Initialize registers for parsing packet type of QinQ
 757          * This should be removed from code once proper
 758          * configuration API is added to avoid configuration conflicts
 759          * between ports of the same device.
 760          */
 761         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 762         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 763 }
 764
 765 static inline void i40e_config_automask(struct i40e_pf *pf)
 766 {
 767         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 768         uint32_t val;
 769
 770         /* INTENA flag is not auto-cleared for interrupt */
 771         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 772         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 773                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 774
 775         /* If support multi-driver, PF will use INT0. */
 776         if (!pf->support_multi_driver)
 777                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 778
 779         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 780 }
 781
 782 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 783
 784 /*
 785  * Add a ethertype filter to drop all flow control frames transmitted
 786  * from VSIs.
 787 */
 788 static void
 789 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 790 {
 791         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 792         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 793                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 794                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 795         int ret;
 796
 797         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 798                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 799                                 pf->main_vsi_seid, 0,
 800                                 TRUE, NULL, NULL);
 801         if (ret)
 802                 PMD_INIT_LOG(ERR,
 803                         "Failed to add filter to drop flow control frames from VSIs.");
 804 }
 805
 806 static int
 807 floating_veb_list_handler(__rte_unused const char *key,
 808                           const char *floating_veb_value,
 809                           void *opaque)
 810 {
 811         int idx = 0;
 812         unsigned int count = 0;
 813         char *end = NULL;
 814         int min, max;
 815         bool *vf_floating_veb = opaque;
 816
 817         while (isblank(*floating_veb_value))
 818                 floating_veb_value++;
 819
 820         /* Reset floating VEB configuration for VFs */
 821         for (idx = 0; idx < I40E_MAX_VF; idx++)
 822                 vf_floating_veb[idx] = false;
 823
 824         min = I40E_MAX_VF;
 825         do {
 826                 while (isblank(*floating_veb_value))
 827                         floating_veb_value++;
 828                 if (*floating_veb_value == '\0')
 829                         return -1;
 830                 errno = 0;
 831                 idx = strtoul(floating_veb_value, &end, 10);
 832                 if (errno || end == NULL)
 833                         return -1;
 834                 while (isblank(*end))
 835                         end++;
 836                 if (*end == '-') {
 837                         min = idx;
 838                 } else if ((*end == ';') || (*end == '\0')) {
 839                         max = idx;
 840                         if (min == I40E_MAX_VF)
 841                                 min = idx;
 842                         if (max >= I40E_MAX_VF)
 843                                 max = I40E_MAX_VF - 1;
 844                         for (idx = min; idx <= max; idx++) {
 845                                 vf_floating_veb[idx] = true;
 846                                 count++;
 847                         }
 848                         min = I40E_MAX_VF;
 849                 } else {
 850                         return -1;
 851                 }
 852                 floating_veb_value = end + 1;
 853         } while (*end != '\0');
 854
 855         if (count == 0)
 856                 return -1;
 857
 858         return 0;
 859 }
 860
 861 static void
 862 config_vf_floating_veb(struct rte_devargs *devargs,
 863                        uint16_t floating_veb,
 864                        bool *vf_floating_veb)
 865 {
 866         struct rte_kvargs *kvlist;
 867         int i;
 868         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 869
 870         if (!floating_veb)
 871                 return;
 872         /* All the VFs attach to the floating VEB by default
 873          * when the floating VEB is enabled.
 874          */
 875         for (i = 0; i < I40E_MAX_VF; i++)
 876                 vf_floating_veb[i] = true;
 877
 878         if (devargs == NULL)
 879                 return;
 880
 881         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 882         if (kvlist == NULL)
 883                 return;
 884
 885         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 886                 rte_kvargs_free(kvlist);
 887                 return;
 888         }
 889         /* When the floating_veb_list parameter exists, all the VFs
 890          * will attach to the legacy VEB firstly, then configure VFs
 891          * to the floating VEB according to the floating_veb_list.
 892          */
 893         if (rte_kvargs_process(kvlist, floating_veb_list,
 894                                floating_veb_list_handler,
 895                                vf_floating_veb) < 0) {
 896                 rte_kvargs_free(kvlist);
 897                 return;
 898         }
 899         rte_kvargs_free(kvlist);
 900 }
 901
 902 static int
 903 i40e_check_floating_handler(__rte_unused const char *key,
 904                             const char *value,
 905                             __rte_unused void *opaque)
 906 {
 907         if (strcmp(value, "1"))
 908                 return -1;
 909
 910         return 0;
 911 }
 912
 913 static int
 914 is_floating_veb_supported(struct rte_devargs *devargs)
 915 {
 916         struct rte_kvargs *kvlist;
 917         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 918
 919         if (devargs == NULL)
 920                 return 0;
 921
 922         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 923         if (kvlist == NULL)
 924                 return 0;
 925
 926         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 927                 rte_kvargs_free(kvlist);
 928                 return 0;
 929         }
 930         /* Floating VEB is enabled when there's key-value:
 931          * enable_floating_veb=1
 932          */
 933         if (rte_kvargs_process(kvlist, floating_veb_key,
 934                                i40e_check_floating_handler, NULL) < 0) {
 935                 rte_kvargs_free(kvlist);
 936                 return 0;
 937         }
 938         rte_kvargs_free(kvlist);
 939
 940         return 1;
 941 }
 942
 943 static void
 944 config_floating_veb(struct rte_eth_dev *dev)
 945 {
 946         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 947         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 949
 950         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 951
 952         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 953                 pf->floating_veb =
 954                         is_floating_veb_supported(pci_dev->device.devargs);
 955                 config_vf_floating_veb(pci_dev->device.devargs,
 956                                        pf->floating_veb,
 957                                        pf->floating_veb_list);
 958         } else {
 959                 pf->floating_veb = false;
 960         }
 961 }
 962
 963 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 964 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 965
 966 static int
 967 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 968 {
 969         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 970         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 971         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 972         int ret;
 973
 974         struct rte_hash_parameters ethertype_hash_params = {
 975                 .name = ethertype_hash_name,
 976                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 977                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 978                 .hash_func = rte_hash_crc,
 979                 .hash_func_init_val = 0,
 980                 .socket_id = rte_socket_id(),
 981         };
 982
 983         /* Initialize ethertype filter rule list and hash */
 984         TAILQ_INIT(&ethertype_rule->ethertype_list);
 985         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 986                  "ethertype_%s", dev->device->name);
 987         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 988         if (!ethertype_rule->hash_table) {
 989                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 990                 return -EINVAL;
 991         }
 992         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 993                                        sizeof(struct i40e_ethertype_filter *) *
 994                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 995                                        0);
 996         if (!ethertype_rule->hash_map) {
 997                 PMD_INIT_LOG(ERR,
 998                              "Failed to allocate memory for ethertype hash map!");
 999                 ret = -ENOMEM;
1000                 goto err_ethertype_hash_map_alloc;
1001         }
1002
1003         return 0;
1004
1005 err_ethertype_hash_map_alloc:
1006         rte_hash_free(ethertype_rule->hash_table);
1007
1008         return ret;
1009 }
1010
1011 static int
1012 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1013 {
1014         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1015         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1016         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1017         int ret;
1018
1019         struct rte_hash_parameters tunnel_hash_params = {
1020                 .name = tunnel_hash_name,
1021                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1022                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1023                 .hash_func = rte_hash_crc,
1024                 .hash_func_init_val = 0,
1025                 .socket_id = rte_socket_id(),
1026         };
1027
1028         /* Initialize tunnel filter rule list and hash */
1029         TAILQ_INIT(&tunnel_rule->tunnel_list);
1030         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1031                  "tunnel_%s", dev->device->name);
1032         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1033         if (!tunnel_rule->hash_table) {
1034                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1035                 return -EINVAL;
1036         }
1037         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1038                                     sizeof(struct i40e_tunnel_filter *) *
1039                                     I40E_MAX_TUNNEL_FILTER_NUM,
1040                                     0);
1041         if (!tunnel_rule->hash_map) {
1042                 PMD_INIT_LOG(ERR,
1043                              "Failed to allocate memory for tunnel hash map!");
1044                 ret = -ENOMEM;
1045                 goto err_tunnel_hash_map_alloc;
1046         }
1047
1048         return 0;
1049
1050 err_tunnel_hash_map_alloc:
1051         rte_hash_free(tunnel_rule->hash_table);
1052
1053         return ret;
1054 }
1055
1056 static int
1057 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1058 {
1059         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1060         struct i40e_fdir_info *fdir_info = &pf->fdir;
1061         char fdir_hash_name[RTE_HASH_NAMESIZE];
1062         int ret;
1063
1064         struct rte_hash_parameters fdir_hash_params = {
1065                 .name = fdir_hash_name,
1066                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1067                 .key_len = sizeof(struct i40e_fdir_input),
1068                 .hash_func = rte_hash_crc,
1069                 .hash_func_init_val = 0,
1070                 .socket_id = rte_socket_id(),
1071         };
1072
1073         /* Initialize flow director filter rule list and hash */
1074         TAILQ_INIT(&fdir_info->fdir_list);
1075         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1076                  "fdir_%s", dev->device->name);
1077         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1078         if (!fdir_info->hash_table) {
1079                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1080                 return -EINVAL;
1081         }
1082         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1083                                           sizeof(struct i40e_fdir_filter *) *
1084                                           I40E_MAX_FDIR_FILTER_NUM,
1085                                           0);
1086         if (!fdir_info->hash_map) {
1087                 PMD_INIT_LOG(ERR,
1088                              "Failed to allocate memory for fdir hash map!");
1089                 ret = -ENOMEM;
1090                 goto err_fdir_hash_map_alloc;
1091         }
1092         return 0;
1093
1094 err_fdir_hash_map_alloc:
1095         rte_hash_free(fdir_info->hash_table);
1096
1097         return ret;
1098 }
1099
1100 static void
1101 i40e_init_customized_info(struct i40e_pf *pf)
1102 {
1103         int i;
1104
1105         /* Initialize customized pctype */
1106         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1107                 pf->customized_pctype[i].index = i;
1108                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1109                 pf->customized_pctype[i].valid = false;
1110         }
1111
1112         pf->gtp_support = false;
1113         pf->esp_support = false;
1114 }
1115
1116 void
1117 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1118 {
1119         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1120         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1121         struct i40e_queue_regions *info = &pf->queue_region;
1122         uint16_t i;
1123
1124         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1125                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1126
1127         memset(info, 0, sizeof(struct i40e_queue_regions));
1128 }
1129
1130 static int
1131 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1132                                const char *value,
1133                                void *opaque)
1134 {
1135         struct i40e_pf *pf;
1136         unsigned long support_multi_driver;
1137         char *end;
1138
1139         pf = (struct i40e_pf *)opaque;
1140
1141         errno = 0;
1142         support_multi_driver = strtoul(value, &end, 10);
1143         if (errno != 0 || end == value || *end != 0) {
1144                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1145                 return -(EINVAL);
1146         }
1147
1148         if (support_multi_driver == 1 || support_multi_driver == 0)
1149                 pf->support_multi_driver = (bool)support_multi_driver;
1150         else
1151                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1152                             "enable global configuration by default."
1153                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1154         return 0;
1155 }
1156
1157 static int
1158 i40e_support_multi_driver(struct rte_eth_dev *dev)
1159 {
1160         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1161         struct rte_kvargs *kvlist;
1162         int kvargs_count;
1163
1164         /* Enable global configuration by default */
1165         pf->support_multi_driver = false;
1166
1167         if (!dev->device->devargs)
1168                 return 0;
1169
1170         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1171         if (!kvlist)
1172                 return -EINVAL;
1173
1174         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1175         if (!kvargs_count) {
1176                 rte_kvargs_free(kvlist);
1177                 return 0;
1178         }
1179
1180         if (kvargs_count > 1)
1181                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1182                             "the first invalid or last valid one is used !",
1183                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1184
1185         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1186                                i40e_parse_multi_drv_handler, pf) < 0) {
1187                 rte_kvargs_free(kvlist);
1188                 return -EINVAL;
1189         }
1190
1191         rte_kvargs_free(kvlist);
1192         return 0;
1193 }
1194
1195 static int
1196 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1197                                     uint32_t reg_addr, uint64_t reg_val,
1198                                     struct i40e_asq_cmd_details *cmd_details)
1199 {
1200         uint64_t ori_reg_val;
1201         struct rte_eth_dev *dev;
1202         int ret;
1203
1204         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1205         if (ret != I40E_SUCCESS) {
1206                 PMD_DRV_LOG(ERR,
1207                             "Fail to debug read from 0x%08x",
1208                             reg_addr);
1209                 return -EIO;
1210         }
1211         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1212
1213         if (ori_reg_val != reg_val)
1214                 PMD_DRV_LOG(WARNING,
1215                             "i40e device %s changed global register [0x%08x]."
1216                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1217                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1218
1219         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1220 }
1221
1222 static int
1223 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1224                                 const char *value,
1225                                 void *opaque)
1226 {
1227         struct i40e_adapter *ad = opaque;
1228         int use_latest_vec;
1229
1230         use_latest_vec = atoi(value);
1231
1232         if (use_latest_vec != 0 && use_latest_vec != 1)
1233                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1234
1235         ad->use_latest_vec = (uint8_t)use_latest_vec;
1236
1237         return 0;
1238 }
1239
1240 static int
1241 i40e_use_latest_vec(struct rte_eth_dev *dev)
1242 {
1243         struct i40e_adapter *ad =
1244                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1245         struct rte_kvargs *kvlist;
1246         int kvargs_count;
1247
1248         ad->use_latest_vec = false;
1249
1250         if (!dev->device->devargs)
1251                 return 0;
1252
1253         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1254         if (!kvlist)
1255                 return -EINVAL;
1256
1257         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1258         if (!kvargs_count) {
1259                 rte_kvargs_free(kvlist);
1260                 return 0;
1261         }
1262
1263         if (kvargs_count > 1)
1264                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1265                             "the first invalid or last valid one is used !",
1266                             ETH_I40E_USE_LATEST_VEC);
1267
1268         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1269                                 i40e_parse_latest_vec_handler, ad) < 0) {
1270                 rte_kvargs_free(kvlist);
1271                 return -EINVAL;
1272         }
1273
1274         rte_kvargs_free(kvlist);
1275         return 0;
1276 }
1277
1278 static int
1279 read_vf_msg_config(__rte_unused const char *key,
1280                                const char *value,
1281                                void *opaque)
1282 {
1283         struct i40e_vf_msg_cfg *cfg = opaque;
1284
1285         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1286                         &cfg->ignore_second) != 3) {
1287                 memset(cfg, 0, sizeof(*cfg));
1288                 PMD_DRV_LOG(ERR, "format error! example: "
1289                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1290                 return -EINVAL;
1291         }
1292
1293         /*
1294          * If the message validation function been enabled, the 'period'
1295          * and 'ignore_second' must greater than 0.
1296          */
1297         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1298                 memset(cfg, 0, sizeof(*cfg));
1299                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1300                                 " number must be greater than 0!",
1301                                 ETH_I40E_VF_MSG_CFG);
1302                 return -EINVAL;
1303         }
1304
1305         return 0;
1306 }
1307
1308 static int
1309 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1310                 struct i40e_vf_msg_cfg *msg_cfg)
1311 {
1312         struct rte_kvargs *kvlist;
1313         int kvargs_count;
1314         int ret = 0;
1315
1316         memset(msg_cfg, 0, sizeof(*msg_cfg));
1317
1318         if (!dev->device->devargs)
1319                 return ret;
1320
1321         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1322         if (!kvlist)
1323                 return -EINVAL;
1324
1325         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1326         if (!kvargs_count)
1327                 goto free_end;
1328
1329         if (kvargs_count > 1) {
1330                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1331                                 ETH_I40E_VF_MSG_CFG);
1332                 ret = -EINVAL;
1333                 goto free_end;
1334         }
1335
1336         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1337                         read_vf_msg_config, msg_cfg) < 0)
1338                 ret = -EINVAL;
1339
1340 free_end:
1341         rte_kvargs_free(kvlist);
1342         return ret;
1343 }
1344
1345 #define I40E_ALARM_INTERVAL 50000 /* us */
1346
1347 static int
1348 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1349 {
1350         struct rte_pci_device *pci_dev;
1351         struct rte_intr_handle *intr_handle;
1352         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1353         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354         struct i40e_vsi *vsi;
1355         int ret;
1356         uint32_t len, val;
1357         uint8_t aq_fail = 0;
1358
1359         PMD_INIT_FUNC_TRACE();
1360
1361         dev->dev_ops = &i40e_eth_dev_ops;
1362         dev->rx_pkt_burst = i40e_recv_pkts;
1363         dev->tx_pkt_burst = i40e_xmit_pkts;
1364         dev->tx_pkt_prepare = i40e_prep_pkts;
1365
1366         /* for secondary processes, we don't initialise any further as primary
1367          * has already done this work. Only check we don't need a different
1368          * RX function */
1369         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1370                 i40e_set_rx_function(dev);
1371                 i40e_set_tx_function(dev);
1372                 return 0;
1373         }
1374         i40e_set_default_ptype_table(dev);
1375         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1376         intr_handle = &pci_dev->intr_handle;
1377
1378         rte_eth_copy_pci_info(dev, pci_dev);
1379
1380         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1381         pf->adapter->eth_dev = dev;
1382         pf->dev_data = dev->data;
1383
1384         hw->back = I40E_PF_TO_ADAPTER(pf);
1385         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1386         if (!hw->hw_addr) {
1387                 PMD_INIT_LOG(ERR,
1388                         "Hardware is not available, as address is NULL");
1389                 return -ENODEV;
1390         }
1391
1392         hw->vendor_id = pci_dev->id.vendor_id;
1393         hw->device_id = pci_dev->id.device_id;
1394         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1395         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1396         hw->bus.device = pci_dev->addr.devid;
1397         hw->bus.func = pci_dev->addr.function;
1398         hw->adapter_stopped = 0;
1399         hw->adapter_closed = 0;
1400
1401         /* Init switch device pointer */
1402         hw->switch_dev = NULL;
1403
1404         /*
1405          * Switch Tag value should not be identical to either the First Tag
1406          * or Second Tag values. So set something other than common Ethertype
1407          * for internal switching.
1408          */
1409         hw->switch_tag = 0xffff;
1410
1411         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1412         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1413                 PMD_INIT_LOG(ERR, "\nERROR: "
1414                         "Firmware recovery mode detected. Limiting functionality.\n"
1415                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1416                         "User Guide for details on firmware recovery mode.");
1417                 return -EIO;
1418         }
1419
1420         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1421         /* Check if need to support multi-driver */
1422         i40e_support_multi_driver(dev);
1423         /* Check if users want the latest supported vec path */
1424         i40e_use_latest_vec(dev);
1425
1426         /* Make sure all is clean before doing PF reset */
1427         i40e_clear_hw(hw);
1428
1429         /* Reset here to make sure all is clean for each PF */
1430         ret = i40e_pf_reset(hw);
1431         if (ret) {
1432                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1433                 return ret;
1434         }
1435
1436         /* Initialize the shared code (base driver) */
1437         ret = i40e_init_shared_code(hw);
1438         if (ret) {
1439                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1440                 return ret;
1441         }
1442
1443         /* Initialize the parameters for adminq */
1444         i40e_init_adminq_parameter(hw);
1445         ret = i40e_init_adminq(hw);
1446         if (ret != I40E_SUCCESS) {
1447                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1448                 return -EIO;
1449         }
1450         /* Firmware of SFP x722 does not support adminq option */
1451         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1452                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1453
1454         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1455                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1456                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1457                      ((hw->nvm.version >> 12) & 0xf),
1458                      ((hw->nvm.version >> 4) & 0xff),
1459                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1460
1461         /* Initialize the hardware */
1462         i40e_hw_init(dev);
1463
1464         i40e_config_automask(pf);
1465
1466         i40e_set_default_pctype_table(dev);
1467
1468         /*
1469          * To work around the NVM issue, initialize registers
1470          * for packet type of QinQ by software.
1471          * It should be removed once issues are fixed in NVM.
1472          */
1473         if (!pf->support_multi_driver)
1474                 i40e_GLQF_reg_init(hw);
1475
1476         /* Initialize the input set for filters (hash and fd) to default value */
1477         i40e_filter_input_set_init(pf);
1478
1479         /* initialise the L3_MAP register */
1480         if (!pf->support_multi_driver) {
1481                 ret = i40e_aq_debug_write_global_register(hw,
1482                                                    I40E_GLQF_L3_MAP(40),
1483                                                    0x00000028,  NULL);
1484                 if (ret)
1485                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1486                                      ret);
1487                 PMD_INIT_LOG(DEBUG,
1488                              "Global register 0x%08x is changed with 0x28",
1489                              I40E_GLQF_L3_MAP(40));
1490         }
1491
1492         /* Need the special FW version to support floating VEB */
1493         config_floating_veb(dev);
1494         /* Clear PXE mode */
1495         i40e_clear_pxe_mode(hw);
1496         i40e_dev_sync_phy_type(hw);
1497
1498         /*
1499          * On X710, performance number is far from the expectation on recent
1500          * firmware versions. The fix for this issue may not be integrated in
1501          * the following firmware version. So the workaround in software driver
1502          * is needed. It needs to modify the initial values of 3 internal only
1503          * registers. Note that the workaround can be removed when it is fixed
1504          * in firmware in the future.
1505          */
1506         i40e_configure_registers(hw);
1507
1508         /* Get hw capabilities */
1509         ret = i40e_get_cap(hw);
1510         if (ret != I40E_SUCCESS) {
1511                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1512                 goto err_get_capabilities;
1513         }
1514
1515         /* Initialize parameters for PF */
1516         ret = i40e_pf_parameter_init(dev);
1517         if (ret != 0) {
1518                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1519                 goto err_parameter_init;
1520         }
1521
1522         /* Initialize the queue management */
1523         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1524         if (ret < 0) {
1525                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1526                 goto err_qp_pool_init;
1527         }
1528         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1529                                 hw->func_caps.num_msix_vectors - 1);
1530         if (ret < 0) {
1531                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1532                 goto err_msix_pool_init;
1533         }
1534
1535         /* Initialize lan hmc */
1536         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1537                                 hw->func_caps.num_rx_qp, 0, 0);
1538         if (ret != I40E_SUCCESS) {
1539                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1540                 goto err_init_lan_hmc;
1541         }
1542
1543         /* Configure lan hmc */
1544         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1545         if (ret != I40E_SUCCESS) {
1546                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1547                 goto err_configure_lan_hmc;
1548         }
1549
1550         /* Get and check the mac address */
1551         i40e_get_mac_addr(hw, hw->mac.addr);
1552         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1553                 PMD_INIT_LOG(ERR, "mac address is not valid");
1554                 ret = -EIO;
1555                 goto err_get_mac_addr;
1556         }
1557         /* Copy the permanent MAC address */
1558         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1559                         (struct rte_ether_addr *)hw->mac.perm_addr);
1560
1561         /* Disable flow control */
1562         hw->fc.requested_mode = I40E_FC_NONE;
1563         i40e_set_fc(hw, &aq_fail, TRUE);
1564
1565         /* Set the global registers with default ether type value */
1566         if (!pf->support_multi_driver) {
1567                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1568                                          RTE_ETHER_TYPE_VLAN);
1569                 if (ret != I40E_SUCCESS) {
1570                         PMD_INIT_LOG(ERR,
1571                                      "Failed to set the default outer "
1572                                      "VLAN ether type");
1573                         goto err_setup_pf_switch;
1574                 }
1575         }
1576
1577         /* PF setup, which includes VSI setup */
1578         ret = i40e_pf_setup(pf);
1579         if (ret) {
1580                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1581                 goto err_setup_pf_switch;
1582         }
1583
1584         vsi = pf->main_vsi;
1585
1586         /* Disable double vlan by default */
1587         i40e_vsi_config_double_vlan(vsi, FALSE);
1588
1589         /* Disable S-TAG identification when floating_veb is disabled */
1590         if (!pf->floating_veb) {
1591                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1592                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1593                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1594                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1595                 }
1596         }
1597
1598         if (!vsi->max_macaddrs)
1599                 len = RTE_ETHER_ADDR_LEN;
1600         else
1601                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1602
1603         /* Should be after VSI initialized */
1604         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1605         if (!dev->data->mac_addrs) {
1606                 PMD_INIT_LOG(ERR,
1607                         "Failed to allocated memory for storing mac address");
1608                 goto err_mac_alloc;
1609         }
1610         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1611                                         &dev->data->mac_addrs[0]);
1612
1613         /* Pass the information to the rte_eth_dev_close() that it should also
1614          * release the private port resources.
1615          */
1616         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1617
1618         /* Init dcb to sw mode by default */
1619         ret = i40e_dcb_init_configure(dev, TRUE);
1620         if (ret != I40E_SUCCESS) {
1621                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1622                 pf->flags &= ~I40E_FLAG_DCB;
1623         }
1624         /* Update HW struct after DCB configuration */
1625         i40e_get_cap(hw);
1626
1627         /* initialize pf host driver to setup SRIOV resource if applicable */
1628         i40e_pf_host_init(dev);
1629
1630         /* register callback func to eal lib */
1631         rte_intr_callback_register(intr_handle,
1632                                    i40e_dev_interrupt_handler, dev);
1633
1634         /* configure and enable device interrupt */
1635         i40e_pf_config_irq0(hw, TRUE);
1636         i40e_pf_enable_irq0(hw);
1637
1638         /* enable uio intr after callback register */
1639         rte_intr_enable(intr_handle);
1640
1641         /* By default disable flexible payload in global configuration */
1642         if (!pf->support_multi_driver)
1643                 i40e_flex_payload_reg_set_default(hw);
1644
1645         /*
1646          * Add an ethertype filter to drop all flow control frames transmitted
1647          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1648          * frames to wire.
1649          */
1650         i40e_add_tx_flow_control_drop_filter(pf);
1651
1652         /* Set the max frame size to 0x2600 by default,
1653          * in case other drivers changed the default value.
1654          */
1655         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1656
1657         /* initialize mirror rule list */
1658         TAILQ_INIT(&pf->mirror_list);
1659
1660         /* initialize RSS rule list */
1661         TAILQ_INIT(&pf->rss_config_list);
1662
1663         /* initialize Traffic Manager configuration */
1664         i40e_tm_conf_init(dev);
1665
1666         /* Initialize customized information */
1667         i40e_init_customized_info(pf);
1668
1669         ret = i40e_init_ethtype_filter_list(dev);
1670         if (ret < 0)
1671                 goto err_init_ethtype_filter_list;
1672         ret = i40e_init_tunnel_filter_list(dev);
1673         if (ret < 0)
1674                 goto err_init_tunnel_filter_list;
1675         ret = i40e_init_fdir_filter_list(dev);
1676         if (ret < 0)
1677                 goto err_init_fdir_filter_list;
1678
1679         /* initialize queue region configuration */
1680         i40e_init_queue_region_conf(dev);
1681
1682         /* initialize RSS configuration from rte_flow */
1683         memset(&pf->rss_info, 0,
1684                 sizeof(struct i40e_rte_flow_rss_conf));
1685
1686         /* reset all stats of the device, including pf and main vsi */
1687         i40e_dev_stats_reset(dev);
1688
1689         return 0;
1690
1691 err_init_fdir_filter_list:
1692         rte_free(pf->tunnel.hash_table);
1693         rte_free(pf->tunnel.hash_map);
1694 err_init_tunnel_filter_list:
1695         rte_free(pf->ethertype.hash_table);
1696         rte_free(pf->ethertype.hash_map);
1697 err_init_ethtype_filter_list:
1698         rte_free(dev->data->mac_addrs);
1699         dev->data->mac_addrs = NULL;
1700 err_mac_alloc:
1701         i40e_vsi_release(pf->main_vsi);
1702 err_setup_pf_switch:
1703 err_get_mac_addr:
1704 err_configure_lan_hmc:
1705         (void)i40e_shutdown_lan_hmc(hw);
1706 err_init_lan_hmc:
1707         i40e_res_pool_destroy(&pf->msix_pool);
1708 err_msix_pool_init:
1709         i40e_res_pool_destroy(&pf->qp_pool);
1710 err_qp_pool_init:
1711 err_parameter_init:
1712 err_get_capabilities:
1713         (void)i40e_shutdown_adminq(hw);
1714
1715         return ret;
1716 }
1717
1718 static void
1719 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1720 {
1721         struct i40e_ethertype_filter *p_ethertype;
1722         struct i40e_ethertype_rule *ethertype_rule;
1723
1724         ethertype_rule = &pf->ethertype;
1725         /* Remove all ethertype filter rules and hash */
1726         if (ethertype_rule->hash_map)
1727                 rte_free(ethertype_rule->hash_map);
1728         if (ethertype_rule->hash_table)
1729                 rte_hash_free(ethertype_rule->hash_table);
1730
1731         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1732                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1733                              p_ethertype, rules);
1734                 rte_free(p_ethertype);
1735         }
1736 }
1737
1738 static void
1739 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1740 {
1741         struct i40e_tunnel_filter *p_tunnel;
1742         struct i40e_tunnel_rule *tunnel_rule;
1743
1744         tunnel_rule = &pf->tunnel;
1745         /* Remove all tunnel director rules and hash */
1746         if (tunnel_rule->hash_map)
1747                 rte_free(tunnel_rule->hash_map);
1748         if (tunnel_rule->hash_table)
1749                 rte_hash_free(tunnel_rule->hash_table);
1750
1751         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1752                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1753                 rte_free(p_tunnel);
1754         }
1755 }
1756
1757 static void
1758 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1759 {
1760         struct i40e_fdir_filter *p_fdir;
1761         struct i40e_fdir_info *fdir_info;
1762
1763         fdir_info = &pf->fdir;
1764         /* Remove all flow director rules and hash */
1765         if (fdir_info->hash_map)
1766                 rte_free(fdir_info->hash_map);
1767         if (fdir_info->hash_table)
1768                 rte_hash_free(fdir_info->hash_table);
1769
1770         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1771                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1772                 rte_free(p_fdir);
1773         }
1774 }
1775
1776 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1777 {
1778         /*
1779          * Disable by default flexible payload
1780          * for corresponding L2/L3/L4 layers.
1781          */
1782         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1783         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1784         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1785 }
1786
1787 static int
1788 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1789 {
1790         struct i40e_hw *hw;
1791
1792         PMD_INIT_FUNC_TRACE();
1793
1794         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1795                 return 0;
1796
1797         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798
1799         if (hw->adapter_closed == 0)
1800                 i40e_dev_close(dev);
1801
1802         return 0;
1803 }
1804
1805 static int
1806 i40e_dev_configure(struct rte_eth_dev *dev)
1807 {
1808         struct i40e_adapter *ad =
1809                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1813         int i, ret;
1814
1815         ret = i40e_dev_sync_phy_type(hw);
1816         if (ret)
1817                 return ret;
1818
1819         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1820          * bulk allocation or vector Rx preconditions we will reset it.
1821          */
1822         ad->rx_bulk_alloc_allowed = true;
1823         ad->rx_vec_allowed = true;
1824         ad->tx_simple_allowed = true;
1825         ad->tx_vec_allowed = true;
1826
1827         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1828                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1829
1830         /* Only legacy filter API needs the following fdir config. So when the
1831          * legacy filter API is deprecated, the following codes should also be
1832          * removed.
1833          */
1834         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1835                 ret = i40e_fdir_setup(pf);
1836                 if (ret != I40E_SUCCESS) {
1837                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1838                         return -ENOTSUP;
1839                 }
1840                 ret = i40e_fdir_configure(dev);
1841                 if (ret < 0) {
1842                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1843                         goto err;
1844                 }
1845         } else
1846                 i40e_fdir_teardown(pf);
1847
1848         ret = i40e_dev_init_vlan(dev);
1849         if (ret < 0)
1850                 goto err;
1851
1852         /* VMDQ setup.
1853          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1854          *  RSS setting have different requirements.
1855          *  General PMD driver call sequence are NIC init, configure,
1856          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1857          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1858          *  applicable. So, VMDQ setting has to be done before
1859          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1860          *  For RSS setting, it will try to calculate actual configured RX queue
1861          *  number, which will be available after rx_queue_setup(). dev_start()
1862          *  function is good to place RSS setup.
1863          */
1864         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1865                 ret = i40e_vmdq_setup(dev);
1866                 if (ret)
1867                         goto err;
1868         }
1869
1870         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1871                 ret = i40e_dcb_setup(dev);
1872                 if (ret) {
1873                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1874                         goto err_dcb;
1875                 }
1876         }
1877
1878         TAILQ_INIT(&pf->flow_list);
1879
1880         return 0;
1881
1882 err_dcb:
1883         /* need to release vmdq resource if exists */
1884         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1885                 i40e_vsi_release(pf->vmdq[i].vsi);
1886                 pf->vmdq[i].vsi = NULL;
1887         }
1888         rte_free(pf->vmdq);
1889         pf->vmdq = NULL;
1890 err:
1891         /* Need to release fdir resource if exists.
1892          * Only legacy filter API needs the following fdir config. So when the
1893          * legacy filter API is deprecated, the following code should also be
1894          * removed.
1895          */
1896         i40e_fdir_teardown(pf);
1897         return ret;
1898 }
1899
1900 void
1901 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1902 {
1903         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1904         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1905         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1906         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1907         uint16_t msix_vect = vsi->msix_intr;
1908         uint16_t i;
1909
1910         for (i = 0; i < vsi->nb_qps; i++) {
1911                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1912                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1913                 rte_wmb();
1914         }
1915
1916         if (vsi->type != I40E_VSI_SRIOV) {
1917                 if (!rte_intr_allow_others(intr_handle)) {
1918                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1919                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1920                         I40E_WRITE_REG(hw,
1921                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1922                                        0);
1923                 } else {
1924                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1925                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1926                         I40E_WRITE_REG(hw,
1927                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1928                                                        msix_vect - 1), 0);
1929                 }
1930         } else {
1931                 uint32_t reg;
1932                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1933                         vsi->user_param + (msix_vect - 1);
1934
1935                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1936                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1937         }
1938         I40E_WRITE_FLUSH(hw);
1939 }
1940
1941 static void
1942 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1943                        int base_queue, int nb_queue,
1944                        uint16_t itr_idx)
1945 {
1946         int i;
1947         uint32_t val;
1948         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1949         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1950
1951         /* Bind all RX queues to allocated MSIX interrupt */
1952         for (i = 0; i < nb_queue; i++) {
1953                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1954                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1955                         ((base_queue + i + 1) <<
1956                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1957                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1958                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1959
1960                 if (i == nb_queue - 1)
1961                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1962                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1963         }
1964
1965         /* Write first RX queue to Link list register as the head element */
1966         if (vsi->type != I40E_VSI_SRIOV) {
1967                 uint16_t interval =
1968                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1969
1970                 if (msix_vect == I40E_MISC_VEC_ID) {
1971                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1972                                        (base_queue <<
1973                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1974                                        (0x0 <<
1975                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1976                         I40E_WRITE_REG(hw,
1977                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1978                                        interval);
1979                 } else {
1980                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1981                                        (base_queue <<
1982                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1983                                        (0x0 <<
1984                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1985                         I40E_WRITE_REG(hw,
1986                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1987                                                        msix_vect - 1),
1988                                        interval);
1989                 }
1990         } else {
1991                 uint32_t reg;
1992
1993                 if (msix_vect == I40E_MISC_VEC_ID) {
1994                         I40E_WRITE_REG(hw,
1995                                        I40E_VPINT_LNKLST0(vsi->user_param),
1996                                        (base_queue <<
1997                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1998                                        (0x0 <<
1999                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2000                 } else {
2001                         /* num_msix_vectors_vf needs to minus irq0 */
2002                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2003                                 vsi->user_param + (msix_vect - 1);
2004
2005                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2006                                        (base_queue <<
2007                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2008                                        (0x0 <<
2009                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2010                 }
2011         }
2012
2013         I40E_WRITE_FLUSH(hw);
2014 }
2015
2016 void
2017 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2018 {
2019         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2020         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2021         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2022         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2023         uint16_t msix_vect = vsi->msix_intr;
2024         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2025         uint16_t queue_idx = 0;
2026         int record = 0;
2027         int i;
2028
2029         for (i = 0; i < vsi->nb_qps; i++) {
2030                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2031                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2032         }
2033
2034         /* VF bind interrupt */
2035         if (vsi->type == I40E_VSI_SRIOV) {
2036                 __vsi_queues_bind_intr(vsi, msix_vect,
2037                                        vsi->base_queue, vsi->nb_qps,
2038                                        itr_idx);
2039                 return;
2040         }
2041
2042         /* PF & VMDq bind interrupt */
2043         if (rte_intr_dp_is_en(intr_handle)) {
2044                 if (vsi->type == I40E_VSI_MAIN) {
2045                         queue_idx = 0;
2046                         record = 1;
2047                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2048                         struct i40e_vsi *main_vsi =
2049                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2050                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2051                         record = 1;
2052                 }
2053         }
2054
2055         for (i = 0; i < vsi->nb_used_qps; i++) {
2056                 if (nb_msix <= 1) {
2057                         if (!rte_intr_allow_others(intr_handle))
2058                                 /* allow to share MISC_VEC_ID */
2059                                 msix_vect = I40E_MISC_VEC_ID;
2060
2061                         /* no enough msix_vect, map all to one */
2062                         __vsi_queues_bind_intr(vsi, msix_vect,
2063                                                vsi->base_queue + i,
2064                                                vsi->nb_used_qps - i,
2065                                                itr_idx);
2066                         for (; !!record && i < vsi->nb_used_qps; i++)
2067                                 intr_handle->intr_vec[queue_idx + i] =
2068                                         msix_vect;
2069                         break;
2070                 }
2071                 /* 1:1 queue/msix_vect mapping */
2072                 __vsi_queues_bind_intr(vsi, msix_vect,
2073                                        vsi->base_queue + i, 1,
2074                                        itr_idx);
2075                 if (!!record)
2076                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2077
2078                 msix_vect++;
2079                 nb_msix--;
2080         }
2081 }
2082
2083 static void
2084 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2085 {
2086         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2087         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2088         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2089         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2090         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2091         uint16_t msix_intr, i;
2092
2093         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2094                 for (i = 0; i < vsi->nb_msix; i++) {
2095                         msix_intr = vsi->msix_intr + i;
2096                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2097                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2098                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2099                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2100                 }
2101         else
2102                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2103                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2104                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2105                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2106
2107         I40E_WRITE_FLUSH(hw);
2108 }
2109
2110 static void
2111 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2112 {
2113         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2114         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2115         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2116         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2117         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2118         uint16_t msix_intr, i;
2119
2120         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2121                 for (i = 0; i < vsi->nb_msix; i++) {
2122                         msix_intr = vsi->msix_intr + i;
2123                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2124                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2125                 }
2126         else
2127                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2128                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2129
2130         I40E_WRITE_FLUSH(hw);
2131 }
2132
2133 static inline uint8_t
2134 i40e_parse_link_speeds(uint16_t link_speeds)
2135 {
2136         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2137
2138         if (link_speeds & ETH_LINK_SPEED_40G)
2139                 link_speed |= I40E_LINK_SPEED_40GB;
2140         if (link_speeds & ETH_LINK_SPEED_25G)
2141                 link_speed |= I40E_LINK_SPEED_25GB;
2142         if (link_speeds & ETH_LINK_SPEED_20G)
2143                 link_speed |= I40E_LINK_SPEED_20GB;
2144         if (link_speeds & ETH_LINK_SPEED_10G)
2145                 link_speed |= I40E_LINK_SPEED_10GB;
2146         if (link_speeds & ETH_LINK_SPEED_1G)
2147                 link_speed |= I40E_LINK_SPEED_1GB;
2148         if (link_speeds & ETH_LINK_SPEED_100M)
2149                 link_speed |= I40E_LINK_SPEED_100MB;
2150
2151         return link_speed;
2152 }
2153
2154 static int
2155 i40e_phy_conf_link(struct i40e_hw *hw,
2156                    uint8_t abilities,
2157                    uint8_t force_speed,
2158                    bool is_up)
2159 {
2160         enum i40e_status_code status;
2161         struct i40e_aq_get_phy_abilities_resp phy_ab;
2162         struct i40e_aq_set_phy_config phy_conf;
2163         enum i40e_aq_phy_type cnt;
2164         uint8_t avail_speed;
2165         uint32_t phy_type_mask = 0;
2166
2167         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2168                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2169                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2170                         I40E_AQ_PHY_FLAG_LOW_POWER;
2171         int ret = -ENOTSUP;
2172
2173         /* To get phy capabilities of available speeds. */
2174         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2175                                               NULL);
2176         if (status) {
2177                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2178                                 status);
2179                 return ret;
2180         }
2181         avail_speed = phy_ab.link_speed;
2182
2183         /* To get the current phy config. */
2184         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2185                                               NULL);
2186         if (status) {
2187                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2188                                 status);
2189                 return ret;
2190         }
2191
2192         /* If link needs to go up and it is in autoneg mode the speed is OK,
2193          * no need to set up again.
2194          */
2195         if (is_up && phy_ab.phy_type != 0 &&
2196                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2197                      phy_ab.link_speed != 0)
2198                 return I40E_SUCCESS;
2199
2200         memset(&phy_conf, 0, sizeof(phy_conf));
2201
2202         /* bits 0-2 use the values from get_phy_abilities_resp */
2203         abilities &= ~mask;
2204         abilities |= phy_ab.abilities & mask;
2205
2206         phy_conf.abilities = abilities;
2207
2208         /* If link needs to go up, but the force speed is not supported,
2209          * Warn users and config the default available speeds.
2210          */
2211         if (is_up && !(force_speed & avail_speed)) {
2212                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2213                 phy_conf.link_speed = avail_speed;
2214         } else {
2215                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2216         }
2217
2218         /* PHY type mask needs to include each type except PHY type extension */
2219         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2220                 phy_type_mask |= 1 << cnt;
2221
2222         /* use get_phy_abilities_resp value for the rest */
2223         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2224         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2225                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2226                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2227         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2228         phy_conf.eee_capability = phy_ab.eee_capability;
2229         phy_conf.eeer = phy_ab.eeer_val;
2230         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2231
2232         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2233                     phy_ab.abilities, phy_ab.link_speed);
2234         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2235                     phy_conf.abilities, phy_conf.link_speed);
2236
2237         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2238         if (status)
2239                 return ret;
2240
2241         return I40E_SUCCESS;
2242 }
2243
2244 static int
2245 i40e_apply_link_speed(struct rte_eth_dev *dev)
2246 {
2247         uint8_t speed;
2248         uint8_t abilities = 0;
2249         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250         struct rte_eth_conf *conf = &dev->data->dev_conf;
2251
2252         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2253                      I40E_AQ_PHY_LINK_ENABLED;
2254
2255         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2256                 conf->link_speeds = ETH_LINK_SPEED_40G |
2257                                     ETH_LINK_SPEED_25G |
2258                                     ETH_LINK_SPEED_20G |
2259                                     ETH_LINK_SPEED_10G |
2260                                     ETH_LINK_SPEED_1G |
2261                                     ETH_LINK_SPEED_100M;
2262
2263                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2264         } else {
2265                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2266         }
2267         speed = i40e_parse_link_speeds(conf->link_speeds);
2268
2269         return i40e_phy_conf_link(hw, abilities, speed, true);
2270 }
2271
2272 static int
2273 i40e_dev_start(struct rte_eth_dev *dev)
2274 {
2275         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277         struct i40e_vsi *main_vsi = pf->main_vsi;
2278         int ret, i;
2279         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2280         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2281         uint32_t intr_vector = 0;
2282         struct i40e_vsi *vsi;
2283
2284         hw->adapter_stopped = 0;
2285
2286         rte_intr_disable(intr_handle);
2287
2288         if ((rte_intr_cap_multiple(intr_handle) ||
2289              !RTE_ETH_DEV_SRIOV(dev).active) &&
2290             dev->data->dev_conf.intr_conf.rxq != 0) {
2291                 intr_vector = dev->data->nb_rx_queues;
2292                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2293                 if (ret)
2294                         return ret;
2295         }
2296
2297         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2298                 intr_handle->intr_vec =
2299                         rte_zmalloc("intr_vec",
2300                                     dev->data->nb_rx_queues * sizeof(int),
2301                                     0);
2302                 if (!intr_handle->intr_vec) {
2303                         PMD_INIT_LOG(ERR,
2304                                 "Failed to allocate %d rx_queues intr_vec",
2305                                 dev->data->nb_rx_queues);
2306                         return -ENOMEM;
2307                 }
2308         }
2309
2310         /* Initialize VSI */
2311         ret = i40e_dev_rxtx_init(pf);
2312         if (ret != I40E_SUCCESS) {
2313                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2314                 goto err_up;
2315         }
2316
2317         /* Map queues with MSIX interrupt */
2318         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2319                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2320         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2321         i40e_vsi_enable_queues_intr(main_vsi);
2322
2323         /* Map VMDQ VSI queues with MSIX interrupt */
2324         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2325                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2326                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2327                                           I40E_ITR_INDEX_DEFAULT);
2328                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2329         }
2330
2331         /* enable FDIR MSIX interrupt */
2332         if (pf->fdir.fdir_vsi) {
2333                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2334                                           I40E_ITR_INDEX_NONE);
2335                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2336         }
2337
2338         /* Enable all queues which have been configured */
2339         ret = i40e_dev_switch_queues(pf, TRUE);
2340         if (ret != I40E_SUCCESS) {
2341                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2342                 goto err_up;
2343         }
2344
2345         /* Enable receiving broadcast packets */
2346         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2347         if (ret != I40E_SUCCESS)
2348                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2349
2350         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2351                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2352                                                 true, NULL);
2353                 if (ret != I40E_SUCCESS)
2354                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2355         }
2356
2357         /* Enable the VLAN promiscuous mode. */
2358         if (pf->vfs) {
2359                 for (i = 0; i < pf->vf_num; i++) {
2360                         vsi = pf->vfs[i].vsi;
2361                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2362                                                      true, NULL);
2363                 }
2364         }
2365
2366         /* Enable mac loopback mode */
2367         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2368             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2369                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2370                 if (ret != I40E_SUCCESS) {
2371                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2372                         goto err_up;
2373                 }
2374         }
2375
2376         /* Apply link configure */
2377         ret = i40e_apply_link_speed(dev);
2378         if (I40E_SUCCESS != ret) {
2379                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2380                 goto err_up;
2381         }
2382
2383         if (!rte_intr_allow_others(intr_handle)) {
2384                 rte_intr_callback_unregister(intr_handle,
2385                                              i40e_dev_interrupt_handler,
2386                                              (void *)dev);
2387                 /* configure and enable device interrupt */
2388                 i40e_pf_config_irq0(hw, FALSE);
2389                 i40e_pf_enable_irq0(hw);
2390
2391                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2392                         PMD_INIT_LOG(INFO,
2393                                 "lsc won't enable because of no intr multiplex");
2394         } else {
2395                 ret = i40e_aq_set_phy_int_mask(hw,
2396                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2397                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2398                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2399                 if (ret != I40E_SUCCESS)
2400                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2401
2402                 /* Call get_link_info aq commond to enable/disable LSE */
2403                 i40e_dev_link_update(dev, 0);
2404         }
2405
2406         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2407                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2408                                   i40e_dev_alarm_handler, dev);
2409         } else {
2410                 /* enable uio intr after callback register */
2411                 rte_intr_enable(intr_handle);
2412         }
2413
2414         i40e_filter_restore(pf);
2415
2416         if (pf->tm_conf.root && !pf->tm_conf.committed)
2417                 PMD_DRV_LOG(WARNING,
2418                             "please call hierarchy_commit() "
2419                             "before starting the port");
2420
2421         return I40E_SUCCESS;
2422
2423 err_up:
2424         i40e_dev_switch_queues(pf, FALSE);
2425         i40e_dev_clear_queues(dev);
2426
2427         return ret;
2428 }
2429
2430 static void
2431 i40e_dev_stop(struct rte_eth_dev *dev)
2432 {
2433         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         struct i40e_vsi *main_vsi = pf->main_vsi;
2436         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2437         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2438         int i;
2439
2440         if (hw->adapter_stopped == 1)
2441                 return;
2442
2443         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2444                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2445                 rte_intr_enable(intr_handle);
2446         }
2447
2448         /* Disable all queues */
2449         i40e_dev_switch_queues(pf, FALSE);
2450
2451         /* un-map queues with interrupt registers */
2452         i40e_vsi_disable_queues_intr(main_vsi);
2453         i40e_vsi_queues_unbind_intr(main_vsi);
2454
2455         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2456                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2457                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2458         }
2459
2460         if (pf->fdir.fdir_vsi) {
2461                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2462                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2463         }
2464         /* Clear all queues and release memory */
2465         i40e_dev_clear_queues(dev);
2466
2467         /* Set link down */
2468         i40e_dev_set_link_down(dev);
2469
2470         if (!rte_intr_allow_others(intr_handle))
2471                 /* resume to the default handler */
2472                 rte_intr_callback_register(intr_handle,
2473                                            i40e_dev_interrupt_handler,
2474                                            (void *)dev);
2475
2476         /* Clean datapath event and queue/vec mapping */
2477         rte_intr_efd_disable(intr_handle);
2478         if (intr_handle->intr_vec) {
2479                 rte_free(intr_handle->intr_vec);
2480                 intr_handle->intr_vec = NULL;
2481         }
2482
2483         /* reset hierarchy commit */
2484         pf->tm_conf.committed = false;
2485
2486         hw->adapter_stopped = 1;
2487
2488         pf->adapter->rss_reta_updated = 0;
2489 }
2490
2491 static void
2492 i40e_dev_close(struct rte_eth_dev *dev)
2493 {
2494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2495         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2497         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2498         struct i40e_mirror_rule *p_mirror;
2499         struct i40e_filter_control_settings settings;
2500         struct rte_flow *p_flow;
2501         uint32_t reg;
2502         int i;
2503         int ret;
2504         uint8_t aq_fail = 0;
2505         int retries = 0;
2506
2507         PMD_INIT_FUNC_TRACE();
2508
2509         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2510         if (ret)
2511                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2512
2513
2514         i40e_dev_stop(dev);
2515
2516         /* Remove all mirror rules */
2517         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2518                 ret = i40e_aq_del_mirror_rule(hw,
2519                                               pf->main_vsi->veb->seid,
2520                                               p_mirror->rule_type,
2521                                               p_mirror->entries,
2522                                               p_mirror->num_entries,
2523                                               p_mirror->id);
2524                 if (ret < 0)
2525                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2526                                     "status = %d, aq_err = %d.", ret,
2527                                     hw->aq.asq_last_status);
2528
2529                 /* remove mirror software resource anyway */
2530                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2531                 rte_free(p_mirror);
2532                 pf->nb_mirror_rule--;
2533         }
2534
2535         i40e_dev_free_queues(dev);
2536
2537         /* Disable interrupt */
2538         i40e_pf_disable_irq0(hw);
2539         rte_intr_disable(intr_handle);
2540
2541         /*
2542          * Only legacy filter API needs the following fdir config. So when the
2543          * legacy filter API is deprecated, the following code should also be
2544          * removed.
2545          */
2546         i40e_fdir_teardown(pf);
2547
2548         /* shutdown and destroy the HMC */
2549         i40e_shutdown_lan_hmc(hw);
2550
2551         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2552                 i40e_vsi_release(pf->vmdq[i].vsi);
2553                 pf->vmdq[i].vsi = NULL;
2554         }
2555         rte_free(pf->vmdq);
2556         pf->vmdq = NULL;
2557
2558         /* release all the existing VSIs and VEBs */
2559         i40e_vsi_release(pf->main_vsi);
2560
2561         /* shutdown the adminq */
2562         i40e_aq_queue_shutdown(hw, true);
2563         i40e_shutdown_adminq(hw);
2564
2565         i40e_res_pool_destroy(&pf->qp_pool);
2566         i40e_res_pool_destroy(&pf->msix_pool);
2567
2568         /* Disable flexible payload in global configuration */
2569         if (!pf->support_multi_driver)
2570                 i40e_flex_payload_reg_set_default(hw);
2571
2572         /* force a PF reset to clean anything leftover */
2573         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2574         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2575                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2576         I40E_WRITE_FLUSH(hw);
2577
2578         dev->dev_ops = NULL;
2579         dev->rx_pkt_burst = NULL;
2580         dev->tx_pkt_burst = NULL;
2581
2582         /* Clear PXE mode */
2583         i40e_clear_pxe_mode(hw);
2584
2585         /* Unconfigure filter control */
2586         memset(&settings, 0, sizeof(settings));
2587         ret = i40e_set_filter_control(hw, &settings);
2588         if (ret)
2589                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2590                                         ret);
2591
2592         /* Disable flow control */
2593         hw->fc.requested_mode = I40E_FC_NONE;
2594         i40e_set_fc(hw, &aq_fail, TRUE);
2595
2596         /* uninitialize pf host driver */
2597         i40e_pf_host_uninit(dev);
2598
2599         do {
2600                 ret = rte_intr_callback_unregister(intr_handle,
2601                                 i40e_dev_interrupt_handler, dev);
2602                 if (ret >= 0 || ret == -ENOENT) {
2603                         break;
2604                 } else if (ret != -EAGAIN) {
2605                         PMD_INIT_LOG(ERR,
2606                                  "intr callback unregister failed: %d",
2607                                  ret);
2608                 }
2609                 i40e_msec_delay(500);
2610         } while (retries++ < 5);
2611
2612         i40e_rm_ethtype_filter_list(pf);
2613         i40e_rm_tunnel_filter_list(pf);
2614         i40e_rm_fdir_filter_list(pf);
2615
2616         /* Remove all flows */
2617         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2618                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2619                 rte_free(p_flow);
2620         }
2621
2622         /* Remove all Traffic Manager configuration */
2623         i40e_tm_conf_uninit(dev);
2624
2625         hw->adapter_closed = 1;
2626 }
2627
2628 /*
2629  * Reset PF device only to re-initialize resources in PMD layer
2630  */
2631 static int
2632 i40e_dev_reset(struct rte_eth_dev *dev)
2633 {
2634         int ret;
2635
2636         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2637          * its VF to make them align with it. The detailed notification
2638          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2639          * To avoid unexpected behavior in VF, currently reset of PF with
2640          * SR-IOV activation is not supported. It might be supported later.
2641          */
2642         if (dev->data->sriov.active)
2643                 return -ENOTSUP;
2644
2645         ret = eth_i40e_dev_uninit(dev);
2646         if (ret)
2647                 return ret;
2648
2649         ret = eth_i40e_dev_init(dev, NULL);
2650
2651         return ret;
2652 }
2653
2654 static int
2655 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2656 {
2657         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2659         struct i40e_vsi *vsi = pf->main_vsi;
2660         int status;
2661
2662         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2663                                                      true, NULL, true);
2664         if (status != I40E_SUCCESS) {
2665                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2666                 return -EAGAIN;
2667         }
2668
2669         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2670                                                         TRUE, NULL);
2671         if (status != I40E_SUCCESS) {
2672                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2673                 /* Rollback unicast promiscuous mode */
2674                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2675                                                     false, NULL, true);
2676                 return -EAGAIN;
2677         }
2678
2679         return 0;
2680 }
2681
2682 static int
2683 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2684 {
2685         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2686         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2687         struct i40e_vsi *vsi = pf->main_vsi;
2688         int status;
2689
2690         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2691                                                      false, NULL, true);
2692         if (status != I40E_SUCCESS) {
2693                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2694                 return -EAGAIN;
2695         }
2696
2697         /* must remain in all_multicast mode */
2698         if (dev->data->all_multicast == 1)
2699                 return 0;
2700
2701         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2702                                                         false, NULL);
2703         if (status != I40E_SUCCESS) {
2704                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2705                 /* Rollback unicast promiscuous mode */
2706                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2707                                                     true, NULL, true);
2708                 return -EAGAIN;
2709         }
2710
2711         return 0;
2712 }
2713
2714 static int
2715 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2716 {
2717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2719         struct i40e_vsi *vsi = pf->main_vsi;
2720         int ret;
2721
2722         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2723         if (ret != I40E_SUCCESS) {
2724                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2725                 return -EAGAIN;
2726         }
2727
2728         return 0;
2729 }
2730
2731 static int
2732 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2733 {
2734         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736         struct i40e_vsi *vsi = pf->main_vsi;
2737         int ret;
2738
2739         if (dev->data->promiscuous == 1)
2740                 return 0; /* must remain in all_multicast mode */
2741
2742         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2743                                 vsi->seid, FALSE, NULL);
2744         if (ret != I40E_SUCCESS) {
2745                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2746                 return -EAGAIN;
2747         }
2748
2749         return 0;
2750 }
2751
2752 /*
2753  * Set device link up.
2754  */
2755 static int
2756 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2757 {
2758         /* re-apply link speed setting */
2759         return i40e_apply_link_speed(dev);
2760 }
2761
2762 /*
2763  * Set device link down.
2764  */
2765 static int
2766 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2767 {
2768         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2769         uint8_t abilities = 0;
2770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2771
2772         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2773         return i40e_phy_conf_link(hw, abilities, speed, false);
2774 }
2775
2776 static __rte_always_inline void
2777 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2778 {
2779 /* Link status registers and values*/
2780 #define I40E_PRTMAC_LINKSTA             0x001E2420
2781 #define I40E_REG_LINK_UP                0x40000080
2782 #define I40E_PRTMAC_MACC                0x001E24E0
2783 #define I40E_REG_MACC_25GB              0x00020000
2784 #define I40E_REG_SPEED_MASK             0x38000000
2785 #define I40E_REG_SPEED_0                0x00000000
2786 #define I40E_REG_SPEED_1                0x08000000
2787 #define I40E_REG_SPEED_2                0x10000000
2788 #define I40E_REG_SPEED_3                0x18000000
2789 #define I40E_REG_SPEED_4                0x20000000
2790         uint32_t link_speed;
2791         uint32_t reg_val;
2792
2793         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2794         link_speed = reg_val & I40E_REG_SPEED_MASK;
2795         reg_val &= I40E_REG_LINK_UP;
2796         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2797
2798         if (unlikely(link->link_status == 0))
2799                 return;
2800
2801         /* Parse the link status */
2802         switch (link_speed) {
2803         case I40E_REG_SPEED_0:
2804                 link->link_speed = ETH_SPEED_NUM_100M;
2805                 break;
2806         case I40E_REG_SPEED_1:
2807                 link->link_speed = ETH_SPEED_NUM_1G;
2808                 break;
2809         case I40E_REG_SPEED_2:
2810                 if (hw->mac.type == I40E_MAC_X722)
2811                         link->link_speed = ETH_SPEED_NUM_2_5G;
2812                 else
2813                         link->link_speed = ETH_SPEED_NUM_10G;
2814                 break;
2815         case I40E_REG_SPEED_3:
2816                 if (hw->mac.type == I40E_MAC_X722) {
2817                         link->link_speed = ETH_SPEED_NUM_5G;
2818                 } else {
2819                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2820
2821                         if (reg_val & I40E_REG_MACC_25GB)
2822                                 link->link_speed = ETH_SPEED_NUM_25G;
2823                         else
2824                                 link->link_speed = ETH_SPEED_NUM_40G;
2825                 }
2826                 break;
2827         case I40E_REG_SPEED_4:
2828                 if (hw->mac.type == I40E_MAC_X722)
2829                         link->link_speed = ETH_SPEED_NUM_10G;
2830                 else
2831                         link->link_speed = ETH_SPEED_NUM_20G;
2832                 break;
2833         default:
2834                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2835                 break;
2836         }
2837 }
2838
2839 static __rte_always_inline void
2840 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2841         bool enable_lse, int wait_to_complete)
2842 {
2843 #define CHECK_INTERVAL             100  /* 100ms */
2844 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2845         uint32_t rep_cnt = MAX_REPEAT_TIME;
2846         struct i40e_link_status link_status;
2847         int status;
2848
2849         memset(&link_status, 0, sizeof(link_status));
2850
2851         do {
2852                 memset(&link_status, 0, sizeof(link_status));
2853
2854                 /* Get link status information from hardware */
2855                 status = i40e_aq_get_link_info(hw, enable_lse,
2856                                                 &link_status, NULL);
2857                 if (unlikely(status != I40E_SUCCESS)) {
2858                         link->link_speed = ETH_SPEED_NUM_NONE;
2859                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2860                         PMD_DRV_LOG(ERR, "Failed to get link info");
2861                         return;
2862                 }
2863
2864                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2865                 if (!wait_to_complete || link->link_status)
2866                         break;
2867
2868                 rte_delay_ms(CHECK_INTERVAL);
2869         } while (--rep_cnt);
2870
2871         /* Parse the link status */
2872         switch (link_status.link_speed) {
2873         case I40E_LINK_SPEED_100MB:
2874                 link->link_speed = ETH_SPEED_NUM_100M;
2875                 break;
2876         case I40E_LINK_SPEED_1GB:
2877                 link->link_speed = ETH_SPEED_NUM_1G;
2878                 break;
2879         case I40E_LINK_SPEED_10GB:
2880                 link->link_speed = ETH_SPEED_NUM_10G;
2881                 break;
2882         case I40E_LINK_SPEED_20GB:
2883                 link->link_speed = ETH_SPEED_NUM_20G;
2884                 break;
2885         case I40E_LINK_SPEED_25GB:
2886                 link->link_speed = ETH_SPEED_NUM_25G;
2887                 break;
2888         case I40E_LINK_SPEED_40GB:
2889                 link->link_speed = ETH_SPEED_NUM_40G;
2890                 break;
2891         default:
2892                 link->link_speed = ETH_SPEED_NUM_NONE;
2893                 break;
2894         }
2895 }
2896
2897 int
2898 i40e_dev_link_update(struct rte_eth_dev *dev,
2899                      int wait_to_complete)
2900 {
2901         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2902         struct rte_eth_link link;
2903         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2904         int ret;
2905
2906         memset(&link, 0, sizeof(link));
2907
2908         /* i40e uses full duplex only */
2909         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2910         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2911                         ETH_LINK_SPEED_FIXED);
2912
2913         if (!wait_to_complete && !enable_lse)
2914                 update_link_reg(hw, &link);
2915         else
2916                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2917
2918         if (hw->switch_dev)
2919                 rte_eth_linkstatus_get(hw->switch_dev, &link);
2920
2921         ret = rte_eth_linkstatus_set(dev, &link);
2922         i40e_notify_all_vfs_link_status(dev);
2923
2924         return ret;
2925 }
2926
2927 /* Get all the statistics of a VSI */
2928 void
2929 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2930 {
2931         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2932         struct i40e_eth_stats *nes = &vsi->eth_stats;
2933         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2934         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2935
2936         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2937                             vsi->offset_loaded, &oes->rx_bytes,
2938                             &nes->rx_bytes);
2939         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2940                             vsi->offset_loaded, &oes->rx_unicast,
2941                             &nes->rx_unicast);
2942         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2943                             vsi->offset_loaded, &oes->rx_multicast,
2944                             &nes->rx_multicast);
2945         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2946                             vsi->offset_loaded, &oes->rx_broadcast,
2947                             &nes->rx_broadcast);
2948         /* exclude CRC bytes */
2949         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2950                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2951
2952         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2953                             &oes->rx_discards, &nes->rx_discards);
2954         /* GLV_REPC not supported */
2955         /* GLV_RMPC not supported */
2956         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2957                             &oes->rx_unknown_protocol,
2958                             &nes->rx_unknown_protocol);
2959         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2960                             vsi->offset_loaded, &oes->tx_bytes,
2961                             &nes->tx_bytes);
2962         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2963                             vsi->offset_loaded, &oes->tx_unicast,
2964                             &nes->tx_unicast);
2965         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2966                             vsi->offset_loaded, &oes->tx_multicast,
2967                             &nes->tx_multicast);
2968         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2969                             vsi->offset_loaded,  &oes->tx_broadcast,
2970                             &nes->tx_broadcast);
2971         /* GLV_TDPC not supported */
2972         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2973                             &oes->tx_errors, &nes->tx_errors);
2974         vsi->offset_loaded = true;
2975
2976         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2977                     vsi->vsi_id);
2978         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2979         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2980         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2981         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2982         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2983         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2984                     nes->rx_unknown_protocol);
2985         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2986         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2987         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2988         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2989         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2990         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2991         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2992                     vsi->vsi_id);
2993 }
2994
2995 static void
2996 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2997 {
2998         unsigned int i;
2999         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3000         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3001
3002         /* Get rx/tx bytes of internal transfer packets */
3003         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3004                         I40E_GLV_GORCL(hw->port),
3005                         pf->offset_loaded,
3006                         &pf->internal_stats_offset.rx_bytes,
3007                         &pf->internal_stats.rx_bytes);
3008
3009         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3010                         I40E_GLV_GOTCL(hw->port),
3011                         pf->offset_loaded,
3012                         &pf->internal_stats_offset.tx_bytes,
3013                         &pf->internal_stats.tx_bytes);
3014         /* Get total internal rx packet count */
3015         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3016                             I40E_GLV_UPRCL(hw->port),
3017                             pf->offset_loaded,
3018                             &pf->internal_stats_offset.rx_unicast,
3019                             &pf->internal_stats.rx_unicast);
3020         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3021                             I40E_GLV_MPRCL(hw->port),
3022                             pf->offset_loaded,
3023                             &pf->internal_stats_offset.rx_multicast,
3024                             &pf->internal_stats.rx_multicast);
3025         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3026                             I40E_GLV_BPRCL(hw->port),
3027                             pf->offset_loaded,
3028                             &pf->internal_stats_offset.rx_broadcast,
3029                             &pf->internal_stats.rx_broadcast);
3030         /* Get total internal tx packet count */
3031         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3032                             I40E_GLV_UPTCL(hw->port),
3033                             pf->offset_loaded,
3034                             &pf->internal_stats_offset.tx_unicast,
3035                             &pf->internal_stats.tx_unicast);
3036         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3037                             I40E_GLV_MPTCL(hw->port),
3038                             pf->offset_loaded,
3039                             &pf->internal_stats_offset.tx_multicast,
3040                             &pf->internal_stats.tx_multicast);
3041         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3042                             I40E_GLV_BPTCL(hw->port),
3043                             pf->offset_loaded,
3044                             &pf->internal_stats_offset.tx_broadcast,
3045                             &pf->internal_stats.tx_broadcast);
3046
3047         /* exclude CRC size */
3048         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3049                 pf->internal_stats.rx_multicast +
3050                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3051
3052         /* Get statistics of struct i40e_eth_stats */
3053         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3054                             I40E_GLPRT_GORCL(hw->port),
3055                             pf->offset_loaded, &os->eth.rx_bytes,
3056                             &ns->eth.rx_bytes);
3057         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3058                             I40E_GLPRT_UPRCL(hw->port),
3059                             pf->offset_loaded, &os->eth.rx_unicast,
3060                             &ns->eth.rx_unicast);
3061         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3062                             I40E_GLPRT_MPRCL(hw->port),
3063                             pf->offset_loaded, &os->eth.rx_multicast,
3064                             &ns->eth.rx_multicast);
3065         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3066                             I40E_GLPRT_BPRCL(hw->port),
3067                             pf->offset_loaded, &os->eth.rx_broadcast,
3068                             &ns->eth.rx_broadcast);
3069         /* Workaround: CRC size should not be included in byte statistics,
3070          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3071          * packet.
3072          */
3073         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3074                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3075
3076         /* exclude internal rx bytes
3077          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3078          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3079          * value.
3080          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3081          */
3082         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3083                 ns->eth.rx_bytes = 0;
3084         else
3085                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3086
3087         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3088                 ns->eth.rx_unicast = 0;
3089         else
3090                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3091
3092         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3093                 ns->eth.rx_multicast = 0;
3094         else
3095                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3096
3097         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3098                 ns->eth.rx_broadcast = 0;
3099         else
3100                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3101
3102         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3103                             pf->offset_loaded, &os->eth.rx_discards,
3104                             &ns->eth.rx_discards);
3105         /* GLPRT_REPC not supported */
3106         /* GLPRT_RMPC not supported */
3107         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3108                             pf->offset_loaded,
3109                             &os->eth.rx_unknown_protocol,
3110                             &ns->eth.rx_unknown_protocol);
3111         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3112                             I40E_GLPRT_GOTCL(hw->port),
3113                             pf->offset_loaded, &os->eth.tx_bytes,
3114                             &ns->eth.tx_bytes);
3115         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3116                             I40E_GLPRT_UPTCL(hw->port),
3117                             pf->offset_loaded, &os->eth.tx_unicast,
3118                             &ns->eth.tx_unicast);
3119         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3120                             I40E_GLPRT_MPTCL(hw->port),
3121                             pf->offset_loaded, &os->eth.tx_multicast,
3122                             &ns->eth.tx_multicast);
3123         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3124                             I40E_GLPRT_BPTCL(hw->port),
3125                             pf->offset_loaded, &os->eth.tx_broadcast,
3126                             &ns->eth.tx_broadcast);
3127         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3128                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3129
3130         /* exclude internal tx bytes
3131          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3132          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3133          * value.
3134          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3135          */
3136         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3137                 ns->eth.tx_bytes = 0;
3138         else
3139                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3140
3141         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3142                 ns->eth.tx_unicast = 0;
3143         else
3144                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3145
3146         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3147                 ns->eth.tx_multicast = 0;
3148         else
3149                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3150
3151         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3152                 ns->eth.tx_broadcast = 0;
3153         else
3154                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3155
3156         /* GLPRT_TEPC not supported */
3157
3158         /* additional port specific stats */
3159         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3160                             pf->offset_loaded, &os->tx_dropped_link_down,
3161                             &ns->tx_dropped_link_down);
3162         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3163                             pf->offset_loaded, &os->crc_errors,
3164                             &ns->crc_errors);
3165         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3166                             pf->offset_loaded, &os->illegal_bytes,
3167                             &ns->illegal_bytes);
3168         /* GLPRT_ERRBC not supported */
3169         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3170                             pf->offset_loaded, &os->mac_local_faults,
3171                             &ns->mac_local_faults);
3172         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3173                             pf->offset_loaded, &os->mac_remote_faults,
3174                             &ns->mac_remote_faults);
3175         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3176                             pf->offset_loaded, &os->rx_length_errors,
3177                             &ns->rx_length_errors);
3178         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3179                             pf->offset_loaded, &os->link_xon_rx,
3180                             &ns->link_xon_rx);
3181         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3182                             pf->offset_loaded, &os->link_xoff_rx,
3183                             &ns->link_xoff_rx);
3184         for (i = 0; i < 8; i++) {
3185                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3186                                     pf->offset_loaded,
3187                                     &os->priority_xon_rx[i],
3188                                     &ns->priority_xon_rx[i]);
3189                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3190                                     pf->offset_loaded,
3191                                     &os->priority_xoff_rx[i],
3192                                     &ns->priority_xoff_rx[i]);
3193         }
3194         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3195                             pf->offset_loaded, &os->link_xon_tx,
3196                             &ns->link_xon_tx);
3197         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3198                             pf->offset_loaded, &os->link_xoff_tx,
3199                             &ns->link_xoff_tx);
3200         for (i = 0; i < 8; i++) {
3201                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3202                                     pf->offset_loaded,
3203                                     &os->priority_xon_tx[i],
3204                                     &ns->priority_xon_tx[i]);
3205                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3206                                     pf->offset_loaded,
3207                                     &os->priority_xoff_tx[i],
3208                                     &ns->priority_xoff_tx[i]);
3209                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3210                                     pf->offset_loaded,
3211                                     &os->priority_xon_2_xoff[i],
3212                                     &ns->priority_xon_2_xoff[i]);
3213         }
3214         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3215                             I40E_GLPRT_PRC64L(hw->port),
3216                             pf->offset_loaded, &os->rx_size_64,
3217                             &ns->rx_size_64);
3218         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3219                             I40E_GLPRT_PRC127L(hw->port),
3220                             pf->offset_loaded, &os->rx_size_127,
3221                             &ns->rx_size_127);
3222         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3223                             I40E_GLPRT_PRC255L(hw->port),
3224                             pf->offset_loaded, &os->rx_size_255,
3225                             &ns->rx_size_255);
3226         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3227                             I40E_GLPRT_PRC511L(hw->port),
3228                             pf->offset_loaded, &os->rx_size_511,
3229                             &ns->rx_size_511);
3230         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3231                             I40E_GLPRT_PRC1023L(hw->port),
3232                             pf->offset_loaded, &os->rx_size_1023,
3233                             &ns->rx_size_1023);
3234         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3235                             I40E_GLPRT_PRC1522L(hw->port),
3236                             pf->offset_loaded, &os->rx_size_1522,
3237                             &ns->rx_size_1522);
3238         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3239                             I40E_GLPRT_PRC9522L(hw->port),
3240                             pf->offset_loaded, &os->rx_size_big,
3241                             &ns->rx_size_big);
3242         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3243                             pf->offset_loaded, &os->rx_undersize,
3244                             &ns->rx_undersize);
3245         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3246                             pf->offset_loaded, &os->rx_fragments,
3247                             &ns->rx_fragments);
3248         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3249                             pf->offset_loaded, &os->rx_oversize,
3250                             &ns->rx_oversize);
3251         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3252                             pf->offset_loaded, &os->rx_jabber,
3253                             &ns->rx_jabber);
3254         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3255                             I40E_GLPRT_PTC64L(hw->port),
3256                             pf->offset_loaded, &os->tx_size_64,
3257                             &ns->tx_size_64);
3258         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3259                             I40E_GLPRT_PTC127L(hw->port),
3260                             pf->offset_loaded, &os->tx_size_127,
3261                             &ns->tx_size_127);
3262         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3263                             I40E_GLPRT_PTC255L(hw->port),
3264                             pf->offset_loaded, &os->tx_size_255,
3265                             &ns->tx_size_255);
3266         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3267                             I40E_GLPRT_PTC511L(hw->port),
3268                             pf->offset_loaded, &os->tx_size_511,
3269                             &ns->tx_size_511);
3270         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3271                             I40E_GLPRT_PTC1023L(hw->port),
3272                             pf->offset_loaded, &os->tx_size_1023,
3273                             &ns->tx_size_1023);
3274         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3275                             I40E_GLPRT_PTC1522L(hw->port),
3276                             pf->offset_loaded, &os->tx_size_1522,
3277                             &ns->tx_size_1522);
3278         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3279                             I40E_GLPRT_PTC9522L(hw->port),
3280                             pf->offset_loaded, &os->tx_size_big,
3281                             &ns->tx_size_big);
3282         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3283                            pf->offset_loaded,
3284                            &os->fd_sb_match, &ns->fd_sb_match);
3285         /* GLPRT_MSPDC not supported */
3286         /* GLPRT_XEC not supported */
3287
3288         pf->offset_loaded = true;
3289
3290         if (pf->main_vsi)
3291                 i40e_update_vsi_stats(pf->main_vsi);
3292 }
3293
3294 /* Get all statistics of a port */
3295 static int
3296 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3297 {
3298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3301         struct i40e_vsi *vsi;
3302         unsigned i;
3303
3304         /* call read registers - updates values, now write them to struct */
3305         i40e_read_stats_registers(pf, hw);
3306
3307         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3308                         pf->main_vsi->eth_stats.rx_multicast +
3309                         pf->main_vsi->eth_stats.rx_broadcast -
3310                         pf->main_vsi->eth_stats.rx_discards;
3311         stats->opackets = ns->eth.tx_unicast +
3312                         ns->eth.tx_multicast +
3313                         ns->eth.tx_broadcast;
3314         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3315         stats->obytes   = ns->eth.tx_bytes;
3316         stats->oerrors  = ns->eth.tx_errors +
3317                         pf->main_vsi->eth_stats.tx_errors;
3318
3319         /* Rx Errors */
3320         stats->imissed  = ns->eth.rx_discards +
3321                         pf->main_vsi->eth_stats.rx_discards;
3322         stats->ierrors  = ns->crc_errors +
3323                         ns->rx_length_errors + ns->rx_undersize +
3324                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3325
3326         if (pf->vfs) {
3327                 for (i = 0; i < pf->vf_num; i++) {
3328                         vsi = pf->vfs[i].vsi;
3329                         i40e_update_vsi_stats(vsi);
3330
3331                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3332                                         vsi->eth_stats.rx_multicast +
3333                                         vsi->eth_stats.rx_broadcast -
3334                                         vsi->eth_stats.rx_discards);
3335                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3336                         stats->oerrors  += vsi->eth_stats.tx_errors;
3337                         stats->imissed  += vsi->eth_stats.rx_discards;
3338                 }
3339         }
3340
3341         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3342         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3343         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3344         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3345         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3346         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3347         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3348                     ns->eth.rx_unknown_protocol);
3349         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3350         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3351         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3352         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3353         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3354         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3355
3356         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3357                     ns->tx_dropped_link_down);
3358         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3359         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3360                     ns->illegal_bytes);
3361         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3362         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3363                     ns->mac_local_faults);
3364         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3365                     ns->mac_remote_faults);
3366         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3367                     ns->rx_length_errors);
3368         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3369         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3370         for (i = 0; i < 8; i++) {
3371                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3372                                 i, ns->priority_xon_rx[i]);
3373                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3374                                 i, ns->priority_xoff_rx[i]);
3375         }
3376         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3377         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3378         for (i = 0; i < 8; i++) {
3379                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3380                                 i, ns->priority_xon_tx[i]);
3381                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3382                                 i, ns->priority_xoff_tx[i]);
3383                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3384                                 i, ns->priority_xon_2_xoff[i]);
3385         }
3386         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3387         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3388         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3389         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3390         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3391         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3392         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3393         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3394         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3395         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3396         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3397         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3398         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3399         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3400         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3401         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3402         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3403         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3404         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3405                         ns->mac_short_packet_dropped);
3406         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3407                     ns->checksum_error);
3408         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3409         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3410         return 0;
3411 }
3412
3413 /* Reset the statistics */
3414 static int
3415 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3416 {
3417         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419
3420         /* Mark PF and VSI stats to update the offset, aka "reset" */
3421         pf->offset_loaded = false;
3422         if (pf->main_vsi)
3423                 pf->main_vsi->offset_loaded = false;
3424
3425         /* read the stats, reading current register values into offset */
3426         i40e_read_stats_registers(pf, hw);
3427
3428         return 0;
3429 }
3430
3431 static uint32_t
3432 i40e_xstats_calc_num(void)
3433 {
3434         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3435                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3436                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3437 }
3438
3439 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3440                                      struct rte_eth_xstat_name *xstats_names,
3441                                      __rte_unused unsigned limit)
3442 {
3443         unsigned count = 0;
3444         unsigned i, prio;
3445
3446         if (xstats_names == NULL)
3447                 return i40e_xstats_calc_num();
3448
3449         /* Note: limit checked in rte_eth_xstats_names() */
3450
3451         /* Get stats from i40e_eth_stats struct */
3452         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3453                 strlcpy(xstats_names[count].name,
3454                         rte_i40e_stats_strings[i].name,
3455                         sizeof(xstats_names[count].name));
3456                 count++;
3457         }
3458
3459         /* Get individiual stats from i40e_hw_port struct */
3460         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3461                 strlcpy(xstats_names[count].name,
3462                         rte_i40e_hw_port_strings[i].name,
3463                         sizeof(xstats_names[count].name));
3464                 count++;
3465         }
3466
3467         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3468                 for (prio = 0; prio < 8; prio++) {
3469                         snprintf(xstats_names[count].name,
3470                                  sizeof(xstats_names[count].name),
3471                                  "rx_priority%u_%s", prio,
3472                                  rte_i40e_rxq_prio_strings[i].name);
3473                         count++;
3474                 }
3475         }
3476
3477         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3478                 for (prio = 0; prio < 8; prio++) {
3479                         snprintf(xstats_names[count].name,
3480                                  sizeof(xstats_names[count].name),
3481                                  "tx_priority%u_%s", prio,
3482                                  rte_i40e_txq_prio_strings[i].name);
3483                         count++;
3484                 }
3485         }
3486         return count;
3487 }
3488
3489 static int
3490 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3491                     unsigned n)
3492 {
3493         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3495         unsigned i, count, prio;
3496         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3497
3498         count = i40e_xstats_calc_num();
3499         if (n < count)
3500                 return count;
3501
3502         i40e_read_stats_registers(pf, hw);
3503
3504         if (xstats == NULL)
3505                 return 0;
3506
3507         count = 0;
3508
3509         /* Get stats from i40e_eth_stats struct */
3510         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3511                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3512                         rte_i40e_stats_strings[i].offset);
3513                 xstats[count].id = count;
3514                 count++;
3515         }
3516
3517         /* Get individiual stats from i40e_hw_port struct */
3518         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3519                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3520                         rte_i40e_hw_port_strings[i].offset);
3521                 xstats[count].id = count;
3522                 count++;
3523         }
3524
3525         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3526                 for (prio = 0; prio < 8; prio++) {
3527                         xstats[count].value =
3528                                 *(uint64_t *)(((char *)hw_stats) +
3529                                 rte_i40e_rxq_prio_strings[i].offset +
3530                                 (sizeof(uint64_t) * prio));
3531                         xstats[count].id = count;
3532                         count++;
3533                 }
3534         }
3535
3536         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3537                 for (prio = 0; prio < 8; prio++) {
3538                         xstats[count].value =
3539                                 *(uint64_t *)(((char *)hw_stats) +
3540                                 rte_i40e_txq_prio_strings[i].offset +
3541                                 (sizeof(uint64_t) * prio));
3542                         xstats[count].id = count;
3543                         count++;
3544                 }
3545         }
3546
3547         return count;
3548 }
3549
3550 static int
3551 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3552 {
3553         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3554         u32 full_ver;
3555         u8 ver, patch;
3556         u16 build;
3557         int ret;
3558
3559         full_ver = hw->nvm.oem_ver;
3560         ver = (u8)(full_ver >> 24);
3561         build = (u16)((full_ver >> 8) & 0xffff);
3562         patch = (u8)(full_ver & 0xff);
3563
3564         ret = snprintf(fw_version, fw_size,
3565                  "%d.%d%d 0x%08x %d.%d.%d",
3566                  ((hw->nvm.version >> 12) & 0xf),
3567                  ((hw->nvm.version >> 4) & 0xff),
3568                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3569                  ver, build, patch);
3570
3571         ret += 1; /* add the size of '\0' */
3572         if (fw_size < (u32)ret)
3573                 return ret;
3574         else
3575                 return 0;
3576 }
3577
3578 /*
3579  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3580  * the Rx data path does not hang if the FW LLDP is stopped.
3581  * return true if lldp need to stop
3582  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3583  */
3584 static bool
3585 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3586 {
3587         double nvm_ver;
3588         char ver_str[64] = {0};
3589         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3590
3591         i40e_fw_version_get(dev, ver_str, 64);
3592         nvm_ver = atof(ver_str);
3593         if ((hw->mac.type == I40E_MAC_X722 ||
3594              hw->mac.type == I40E_MAC_X722_VF) &&
3595              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3596                 return true;
3597         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3598                 return true;
3599
3600         return false;
3601 }
3602
3603 static int
3604 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3605 {
3606         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3607         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608         struct i40e_vsi *vsi = pf->main_vsi;
3609         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3610
3611         dev_info->max_rx_queues = vsi->nb_qps;
3612         dev_info->max_tx_queues = vsi->nb_qps;
3613         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3614         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3615         dev_info->max_mac_addrs = vsi->max_macaddrs;
3616         dev_info->max_vfs = pci_dev->max_vfs;
3617         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3618         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3619         dev_info->rx_queue_offload_capa = 0;
3620         dev_info->rx_offload_capa =
3621                 DEV_RX_OFFLOAD_VLAN_STRIP |
3622                 DEV_RX_OFFLOAD_QINQ_STRIP |
3623                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3624                 DEV_RX_OFFLOAD_UDP_CKSUM |
3625                 DEV_RX_OFFLOAD_TCP_CKSUM |
3626                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3627                 DEV_RX_OFFLOAD_KEEP_CRC |
3628                 DEV_RX_OFFLOAD_SCATTER |
3629                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3630                 DEV_RX_OFFLOAD_VLAN_FILTER |
3631                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3632                 DEV_RX_OFFLOAD_RSS_HASH;
3633
3634         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3635         dev_info->tx_offload_capa =
3636                 DEV_TX_OFFLOAD_VLAN_INSERT |
3637                 DEV_TX_OFFLOAD_QINQ_INSERT |
3638                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3639                 DEV_TX_OFFLOAD_UDP_CKSUM |
3640                 DEV_TX_OFFLOAD_TCP_CKSUM |
3641                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3642                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3643                 DEV_TX_OFFLOAD_TCP_TSO |
3644                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3645                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3646                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3647                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3648                 DEV_TX_OFFLOAD_MULTI_SEGS |
3649                 dev_info->tx_queue_offload_capa;
3650         dev_info->dev_capa =
3651                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3652                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3653
3654         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3655                                                 sizeof(uint32_t);
3656         dev_info->reta_size = pf->hash_lut_size;
3657         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3658
3659         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3660                 .rx_thresh = {
3661                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3662                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3663                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3664                 },
3665                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3666                 .rx_drop_en = 0,
3667                 .offloads = 0,
3668         };
3669
3670         dev_info->default_txconf = (struct rte_eth_txconf) {
3671                 .tx_thresh = {
3672                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3673                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3674                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3675                 },
3676                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3677                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3678                 .offloads = 0,
3679         };
3680
3681         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3682                 .nb_max = I40E_MAX_RING_DESC,
3683                 .nb_min = I40E_MIN_RING_DESC,
3684                 .nb_align = I40E_ALIGN_RING_DESC,
3685         };
3686
3687         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3688                 .nb_max = I40E_MAX_RING_DESC,
3689                 .nb_min = I40E_MIN_RING_DESC,
3690                 .nb_align = I40E_ALIGN_RING_DESC,
3691                 .nb_seg_max = I40E_TX_MAX_SEG,
3692                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3693         };
3694
3695         if (pf->flags & I40E_FLAG_VMDQ) {
3696                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3697                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3698                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3699                                                 pf->max_nb_vmdq_vsi;
3700                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3701                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3702                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3703         }
3704
3705         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3706                 /* For XL710 */
3707                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3708                 dev_info->default_rxportconf.nb_queues = 2;
3709                 dev_info->default_txportconf.nb_queues = 2;
3710                 if (dev->data->nb_rx_queues == 1)
3711                         dev_info->default_rxportconf.ring_size = 2048;
3712                 else
3713                         dev_info->default_rxportconf.ring_size = 1024;
3714                 if (dev->data->nb_tx_queues == 1)
3715                         dev_info->default_txportconf.ring_size = 1024;
3716                 else
3717                         dev_info->default_txportconf.ring_size = 512;
3718
3719         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3720                 /* For XXV710 */
3721                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3722                 dev_info->default_rxportconf.nb_queues = 1;
3723                 dev_info->default_txportconf.nb_queues = 1;
3724                 dev_info->default_rxportconf.ring_size = 256;
3725                 dev_info->default_txportconf.ring_size = 256;
3726         } else {
3727                 /* For X710 */
3728                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3729                 dev_info->default_rxportconf.nb_queues = 1;
3730                 dev_info->default_txportconf.nb_queues = 1;
3731                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3732                         dev_info->default_rxportconf.ring_size = 512;
3733                         dev_info->default_txportconf.ring_size = 256;
3734                 } else {
3735                         dev_info->default_rxportconf.ring_size = 256;
3736                         dev_info->default_txportconf.ring_size = 256;
3737                 }
3738         }
3739         dev_info->default_rxportconf.burst_size = 32;
3740         dev_info->default_txportconf.burst_size = 32;
3741
3742         return 0;
3743 }
3744
3745 static int
3746 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3747 {
3748         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3749         struct i40e_vsi *vsi = pf->main_vsi;
3750         PMD_INIT_FUNC_TRACE();
3751
3752         if (on)
3753                 return i40e_vsi_add_vlan(vsi, vlan_id);
3754         else
3755                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3756 }
3757
3758 static int
3759 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3760                                 enum rte_vlan_type vlan_type,
3761                                 uint16_t tpid, int qinq)
3762 {
3763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764         uint64_t reg_r = 0;
3765         uint64_t reg_w = 0;
3766         uint16_t reg_id = 3;
3767         int ret;
3768
3769         if (qinq) {
3770                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3771                         reg_id = 2;
3772         }
3773
3774         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3775                                           &reg_r, NULL);
3776         if (ret != I40E_SUCCESS) {
3777                 PMD_DRV_LOG(ERR,
3778                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3779                            reg_id);
3780                 return -EIO;
3781         }
3782         PMD_DRV_LOG(DEBUG,
3783                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3784                     reg_id, reg_r);
3785
3786         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3787         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3788         if (reg_r == reg_w) {
3789                 PMD_DRV_LOG(DEBUG, "No need to write");
3790                 return 0;
3791         }
3792
3793         ret = i40e_aq_debug_write_global_register(hw,
3794                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3795                                            reg_w, NULL);
3796         if (ret != I40E_SUCCESS) {
3797                 PMD_DRV_LOG(ERR,
3798                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3799                             reg_id);
3800                 return -EIO;
3801         }
3802         PMD_DRV_LOG(DEBUG,
3803                     "Global register 0x%08x is changed with value 0x%08x",
3804                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3805
3806         return 0;
3807 }
3808
3809 static int
3810 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3811                    enum rte_vlan_type vlan_type,
3812                    uint16_t tpid)
3813 {
3814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3815         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3816         int qinq = dev->data->dev_conf.rxmode.offloads &
3817                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3818         int ret = 0;
3819
3820         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3821              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3822             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3823                 PMD_DRV_LOG(ERR,
3824                             "Unsupported vlan type.");
3825                 return -EINVAL;
3826         }
3827
3828         if (pf->support_multi_driver) {
3829                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3830                 return -ENOTSUP;
3831         }
3832
3833         /* 802.1ad frames ability is added in NVM API 1.7*/
3834         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3835                 if (qinq) {
3836                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3837                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3838                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3839                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3840                 } else {
3841                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3842                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3843                 }
3844                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3845                 if (ret != I40E_SUCCESS) {
3846                         PMD_DRV_LOG(ERR,
3847                                     "Set switch config failed aq_err: %d",
3848                                     hw->aq.asq_last_status);
3849                         ret = -EIO;
3850                 }
3851         } else
3852                 /* If NVM API < 1.7, keep the register setting */
3853                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3854                                                       tpid, qinq);
3855
3856         return ret;
3857 }
3858
3859 static int
3860 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3861 {
3862         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3863         struct i40e_vsi *vsi = pf->main_vsi;
3864         struct rte_eth_rxmode *rxmode;
3865
3866         if (mask & ETH_QINQ_STRIP_MASK) {
3867                 PMD_DRV_LOG(ERR, "Strip qinq is not supported.");
3868                 return -ENOTSUP;
3869         }
3870
3871         rxmode = &dev->data->dev_conf.rxmode;
3872         if (mask & ETH_VLAN_FILTER_MASK) {
3873                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3874                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3875                 else
3876                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3877         }
3878
3879         if (mask & ETH_VLAN_STRIP_MASK) {
3880                 /* Enable or disable VLAN stripping */
3881                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3882                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3883                 else
3884                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3885         }
3886
3887         if (mask & ETH_VLAN_EXTEND_MASK) {
3888                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3889                         i40e_vsi_config_double_vlan(vsi, TRUE);
3890                         /* Set global registers with default ethertype. */
3891                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3892                                            RTE_ETHER_TYPE_VLAN);
3893                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3894                                            RTE_ETHER_TYPE_VLAN);
3895                 }
3896                 else
3897                         i40e_vsi_config_double_vlan(vsi, FALSE);
3898         }
3899
3900         return 0;
3901 }
3902
3903 static void
3904 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3905                           __rte_unused uint16_t queue,
3906                           __rte_unused int on)
3907 {
3908         PMD_INIT_FUNC_TRACE();
3909 }
3910
3911 static int
3912 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3913 {
3914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3915         struct i40e_vsi *vsi = pf->main_vsi;
3916         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3917         struct i40e_vsi_vlan_pvid_info info;
3918
3919         memset(&info, 0, sizeof(info));
3920         info.on = on;
3921         if (info.on)
3922                 info.config.pvid = pvid;
3923         else {
3924                 info.config.reject.tagged =
3925                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3926                 info.config.reject.untagged =
3927                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3928         }
3929
3930         return i40e_vsi_vlan_pvid_set(vsi, &info);
3931 }
3932
3933 static int
3934 i40e_dev_led_on(struct rte_eth_dev *dev)
3935 {
3936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937         uint32_t mode = i40e_led_get(hw);
3938
3939         if (mode == 0)
3940                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3941
3942         return 0;
3943 }
3944
3945 static int
3946 i40e_dev_led_off(struct rte_eth_dev *dev)
3947 {
3948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3949         uint32_t mode = i40e_led_get(hw);
3950
3951         if (mode != 0)
3952                 i40e_led_set(hw, 0, false);
3953
3954         return 0;
3955 }
3956
3957 static int
3958 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3959 {
3960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3962
3963         fc_conf->pause_time = pf->fc_conf.pause_time;
3964
3965         /* read out from register, in case they are modified by other port */
3966         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3967                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3968         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3969                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3970
3971         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3972         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3973
3974          /* Return current mode according to actual setting*/
3975         switch (hw->fc.current_mode) {
3976         case I40E_FC_FULL:
3977                 fc_conf->mode = RTE_FC_FULL;
3978                 break;
3979         case I40E_FC_TX_PAUSE:
3980                 fc_conf->mode = RTE_FC_TX_PAUSE;
3981                 break;
3982         case I40E_FC_RX_PAUSE:
3983                 fc_conf->mode = RTE_FC_RX_PAUSE;
3984                 break;
3985         case I40E_FC_NONE:
3986         default:
3987                 fc_conf->mode = RTE_FC_NONE;
3988         };
3989
3990         return 0;
3991 }
3992
3993 static int
3994 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3995 {
3996         uint32_t mflcn_reg, fctrl_reg, reg;
3997         uint32_t max_high_water;
3998         uint8_t i, aq_failure;
3999         int err;
4000         struct i40e_hw *hw;
4001         struct i40e_pf *pf;
4002         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4003                 [RTE_FC_NONE] = I40E_FC_NONE,
4004                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4005                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4006                 [RTE_FC_FULL] = I40E_FC_FULL
4007         };
4008
4009         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4010
4011         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4012         if ((fc_conf->high_water > max_high_water) ||
4013                         (fc_conf->high_water < fc_conf->low_water)) {
4014                 PMD_INIT_LOG(ERR,
4015                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4016                         max_high_water);
4017                 return -EINVAL;
4018         }
4019
4020         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4021         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4022         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4023
4024         pf->fc_conf.pause_time = fc_conf->pause_time;
4025         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4026         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4027
4028         PMD_INIT_FUNC_TRACE();
4029
4030         /* All the link flow control related enable/disable register
4031          * configuration is handle by the F/W
4032          */
4033         err = i40e_set_fc(hw, &aq_failure, true);
4034         if (err < 0)
4035                 return -ENOSYS;
4036
4037         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4038                 /* Configure flow control refresh threshold,
4039                  * the value for stat_tx_pause_refresh_timer[8]
4040                  * is used for global pause operation.
4041                  */
4042
4043                 I40E_WRITE_REG(hw,
4044                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4045                                pf->fc_conf.pause_time);
4046
4047                 /* configure the timer value included in transmitted pause
4048                  * frame,
4049                  * the value for stat_tx_pause_quanta[8] is used for global
4050                  * pause operation
4051                  */
4052                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4053                                pf->fc_conf.pause_time);
4054
4055                 fctrl_reg = I40E_READ_REG(hw,
4056                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4057
4058                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4059                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4060                 else
4061                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4062
4063                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4064                                fctrl_reg);
4065         } else {
4066                 /* Configure pause time (2 TCs per register) */
4067                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4068                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4069                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4070
4071                 /* Configure flow control refresh threshold value */
4072                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4073                                pf->fc_conf.pause_time / 2);
4074
4075                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4076
4077                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4078                  *depending on configuration
4079                  */
4080                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4081                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4082                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4083                 } else {
4084                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4085                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4086                 }
4087
4088                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4089         }
4090
4091         if (!pf->support_multi_driver) {
4092                 /* config water marker both based on the packets and bytes */
4093                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4094                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4095                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4096                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4097                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4098                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4099                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4100                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4101                                   << I40E_KILOSHIFT);
4102                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4103                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4104                                    << I40E_KILOSHIFT);
4105         } else {
4106                 PMD_DRV_LOG(ERR,
4107                             "Water marker configuration is not supported.");
4108         }
4109
4110         I40E_WRITE_FLUSH(hw);
4111
4112         return 0;
4113 }
4114
4115 static int
4116 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4117                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4118 {
4119         PMD_INIT_FUNC_TRACE();
4120
4121         return -ENOSYS;
4122 }
4123
4124 /* Add a MAC address, and update filters */
4125 static int
4126 i40e_macaddr_add(struct rte_eth_dev *dev,
4127                  struct rte_ether_addr *mac_addr,
4128                  __rte_unused uint32_t index,
4129                  uint32_t pool)
4130 {
4131         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4132         struct i40e_mac_filter_info mac_filter;
4133         struct i40e_vsi *vsi;
4134         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4135         int ret;
4136
4137         /* If VMDQ not enabled or configured, return */
4138         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4139                           !pf->nb_cfg_vmdq_vsi)) {
4140                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4141                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4142                         pool);
4143                 return -ENOTSUP;
4144         }
4145
4146         if (pool > pf->nb_cfg_vmdq_vsi) {
4147                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4148                                 pool, pf->nb_cfg_vmdq_vsi);
4149                 return -EINVAL;
4150         }
4151
4152         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4153         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4154                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4155         else
4156                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4157
4158         if (pool == 0)
4159                 vsi = pf->main_vsi;
4160         else
4161                 vsi = pf->vmdq[pool - 1].vsi;
4162
4163         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4164         if (ret != I40E_SUCCESS) {
4165                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4166                 return -ENODEV;
4167         }
4168         return 0;
4169 }
4170
4171 /* Remove a MAC address, and update filters */
4172 static void
4173 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4174 {
4175         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4176         struct i40e_vsi *vsi;
4177         struct rte_eth_dev_data *data = dev->data;
4178         struct rte_ether_addr *macaddr;
4179         int ret;
4180         uint32_t i;
4181         uint64_t pool_sel;
4182
4183         macaddr = &(data->mac_addrs[index]);
4184
4185         pool_sel = dev->data->mac_pool_sel[index];
4186
4187         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4188                 if (pool_sel & (1ULL << i)) {
4189                         if (i == 0)
4190                                 vsi = pf->main_vsi;
4191                         else {
4192                                 /* No VMDQ pool enabled or configured */
4193                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4194                                         (i > pf->nb_cfg_vmdq_vsi)) {
4195                                         PMD_DRV_LOG(ERR,
4196                                                 "No VMDQ pool enabled/configured");
4197                                         return;
4198                                 }
4199                                 vsi = pf->vmdq[i - 1].vsi;
4200                         }
4201                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4202
4203                         if (ret) {
4204                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4205                                 return;
4206                         }
4207                 }
4208         }
4209 }
4210
4211 /* Set perfect match or hash match of MAC and VLAN for a VF */
4212 static int
4213 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4214                  struct rte_eth_mac_filter *filter,
4215                  bool add)
4216 {
4217         struct i40e_hw *hw;
4218         struct i40e_mac_filter_info mac_filter;
4219         struct rte_ether_addr old_mac;
4220         struct rte_ether_addr *new_mac;
4221         struct i40e_pf_vf *vf = NULL;
4222         uint16_t vf_id;
4223         int ret;
4224
4225         if (pf == NULL) {
4226                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4227                 return -EINVAL;
4228         }
4229         hw = I40E_PF_TO_HW(pf);
4230
4231         if (filter == NULL) {
4232                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4233                 return -EINVAL;
4234         }
4235
4236         new_mac = &filter->mac_addr;
4237
4238         if (rte_is_zero_ether_addr(new_mac)) {
4239                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4240                 return -EINVAL;
4241         }
4242
4243         vf_id = filter->dst_id;
4244
4245         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4246                 PMD_DRV_LOG(ERR, "Invalid argument.");
4247                 return -EINVAL;
4248         }
4249         vf = &pf->vfs[vf_id];
4250
4251         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4252                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4253                 return -EINVAL;
4254         }
4255
4256         if (add) {
4257                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4258                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4259                                 RTE_ETHER_ADDR_LEN);
4260                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4261                                  RTE_ETHER_ADDR_LEN);
4262
4263                 mac_filter.filter_type = filter->filter_type;
4264                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4265                 if (ret != I40E_SUCCESS) {
4266                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4267                         return -1;
4268                 }
4269                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4270         } else {
4271                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4272                                 RTE_ETHER_ADDR_LEN);
4273                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4274                 if (ret != I40E_SUCCESS) {
4275                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4276                         return -1;
4277                 }
4278
4279                 /* Clear device address as it has been removed */
4280                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4281                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4282         }
4283
4284         return 0;
4285 }
4286
4287 /* MAC filter handle */
4288 static int
4289 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4290                 void *arg)
4291 {
4292         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4293         struct rte_eth_mac_filter *filter;
4294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4295         int ret = I40E_NOT_SUPPORTED;
4296
4297         filter = (struct rte_eth_mac_filter *)(arg);
4298
4299         switch (filter_op) {
4300         case RTE_ETH_FILTER_NOP:
4301                 ret = I40E_SUCCESS;
4302                 break;
4303         case RTE_ETH_FILTER_ADD:
4304                 i40e_pf_disable_irq0(hw);
4305                 if (filter->is_vf)
4306                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4307                 i40e_pf_enable_irq0(hw);
4308                 break;
4309         case RTE_ETH_FILTER_DELETE:
4310                 i40e_pf_disable_irq0(hw);
4311                 if (filter->is_vf)
4312                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4313                 i40e_pf_enable_irq0(hw);
4314                 break;
4315         default:
4316                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4317                 ret = I40E_ERR_PARAM;
4318                 break;
4319         }
4320
4321         return ret;
4322 }
4323
4324 static int
4325 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4326 {
4327         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4328         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4329         uint32_t reg;
4330         int ret;
4331
4332         if (!lut)
4333                 return -EINVAL;
4334
4335         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4336                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4337                                           vsi->type != I40E_VSI_SRIOV,
4338                                           lut, lut_size);
4339                 if (ret) {
4340                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4341                         return ret;
4342                 }
4343         } else {
4344                 uint32_t *lut_dw = (uint32_t *)lut;
4345                 uint16_t i, lut_size_dw = lut_size / 4;
4346
4347                 if (vsi->type == I40E_VSI_SRIOV) {
4348                         for (i = 0; i <= lut_size_dw; i++) {
4349                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4350                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4351                         }
4352                 } else {
4353                         for (i = 0; i < lut_size_dw; i++)
4354                                 lut_dw[i] = I40E_READ_REG(hw,
4355                                                           I40E_PFQF_HLUT(i));
4356                 }
4357         }
4358
4359         return 0;
4360 }
4361
4362 int
4363 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4364 {
4365         struct i40e_pf *pf;
4366         struct i40e_hw *hw;
4367         int ret;
4368
4369         if (!vsi || !lut)
4370                 return -EINVAL;
4371
4372         pf = I40E_VSI_TO_PF(vsi);
4373         hw = I40E_VSI_TO_HW(vsi);
4374
4375         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4376                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4377                                           vsi->type != I40E_VSI_SRIOV,
4378                                           lut, lut_size);
4379                 if (ret) {
4380                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4381                         return ret;
4382                 }
4383         } else {
4384                 uint32_t *lut_dw = (uint32_t *)lut;
4385                 uint16_t i, lut_size_dw = lut_size / 4;
4386
4387                 if (vsi->type == I40E_VSI_SRIOV) {
4388                         for (i = 0; i < lut_size_dw; i++)
4389                                 I40E_WRITE_REG(
4390                                         hw,
4391                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4392                                         lut_dw[i]);
4393                 } else {
4394                         for (i = 0; i < lut_size_dw; i++)
4395                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4396                                                lut_dw[i]);
4397                 }
4398                 I40E_WRITE_FLUSH(hw);
4399         }
4400
4401         return 0;
4402 }
4403
4404 static int
4405 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4406                          struct rte_eth_rss_reta_entry64 *reta_conf,
4407                          uint16_t reta_size)
4408 {
4409         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4410         uint16_t i, lut_size = pf->hash_lut_size;
4411         uint16_t idx, shift;
4412         uint8_t *lut;
4413         int ret;
4414
4415         if (reta_size != lut_size ||
4416                 reta_size > ETH_RSS_RETA_SIZE_512) {
4417                 PMD_DRV_LOG(ERR,
4418                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4419                         reta_size, lut_size);
4420                 return -EINVAL;
4421         }
4422
4423         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4424         if (!lut) {
4425                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4426                 return -ENOMEM;
4427         }
4428         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4429         if (ret)
4430                 goto out;
4431         for (i = 0; i < reta_size; i++) {
4432                 idx = i / RTE_RETA_GROUP_SIZE;
4433                 shift = i % RTE_RETA_GROUP_SIZE;
4434                 if (reta_conf[idx].mask & (1ULL << shift))
4435                         lut[i] = reta_conf[idx].reta[shift];
4436         }
4437         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4438
4439         pf->adapter->rss_reta_updated = 1;
4440
4441 out:
4442         rte_free(lut);
4443
4444         return ret;
4445 }
4446
4447 static int
4448 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4449                         struct rte_eth_rss_reta_entry64 *reta_conf,
4450                         uint16_t reta_size)
4451 {
4452         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4453         uint16_t i, lut_size = pf->hash_lut_size;
4454         uint16_t idx, shift;
4455         uint8_t *lut;
4456         int ret;
4457
4458         if (reta_size != lut_size ||
4459                 reta_size > ETH_RSS_RETA_SIZE_512) {
4460                 PMD_DRV_LOG(ERR,
4461                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4462                         reta_size, lut_size);
4463                 return -EINVAL;
4464         }
4465
4466         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4467         if (!lut) {
4468                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4469                 return -ENOMEM;
4470         }
4471
4472         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4473         if (ret)
4474                 goto out;
4475         for (i = 0; i < reta_size; i++) {
4476                 idx = i / RTE_RETA_GROUP_SIZE;
4477                 shift = i % RTE_RETA_GROUP_SIZE;
4478                 if (reta_conf[idx].mask & (1ULL << shift))
4479                         reta_conf[idx].reta[shift] = lut[i];
4480         }
4481
4482 out:
4483         rte_free(lut);
4484
4485         return ret;
4486 }
4487
4488 /**
4489  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4490  * @hw:   pointer to the HW structure
4491  * @mem:  pointer to mem struct to fill out
4492  * @size: size of memory requested
4493  * @alignment: what to align the allocation to
4494  **/
4495 enum i40e_status_code
4496 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4497                         struct i40e_dma_mem *mem,
4498                         u64 size,
4499                         u32 alignment)
4500 {
4501         const struct rte_memzone *mz = NULL;
4502         char z_name[RTE_MEMZONE_NAMESIZE];
4503
4504         if (!mem)
4505                 return I40E_ERR_PARAM;
4506
4507         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4508         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4509                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4510         if (!mz)
4511                 return I40E_ERR_NO_MEMORY;
4512
4513         mem->size = size;
4514         mem->va = mz->addr;
4515         mem->pa = mz->iova;
4516         mem->zone = (const void *)mz;
4517         PMD_DRV_LOG(DEBUG,
4518                 "memzone %s allocated with physical address: %"PRIu64,
4519                 mz->name, mem->pa);
4520
4521         return I40E_SUCCESS;
4522 }
4523
4524 /**
4525  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4526  * @hw:   pointer to the HW structure
4527  * @mem:  ptr to mem struct to free
4528  **/
4529 enum i40e_status_code
4530 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4531                     struct i40e_dma_mem *mem)
4532 {
4533         if (!mem)
4534                 return I40E_ERR_PARAM;
4535
4536         PMD_DRV_LOG(DEBUG,
4537                 "memzone %s to be freed with physical address: %"PRIu64,
4538                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4539         rte_memzone_free((const struct rte_memzone *)mem->zone);
4540         mem->zone = NULL;
4541         mem->va = NULL;
4542         mem->pa = (u64)0;
4543
4544         return I40E_SUCCESS;
4545 }
4546
4547 /**
4548  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4549  * @hw:   pointer to the HW structure
4550  * @mem:  pointer to mem struct to fill out
4551  * @size: size of memory requested
4552  **/
4553 enum i40e_status_code
4554 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4555                          struct i40e_virt_mem *mem,
4556                          u32 size)
4557 {
4558         if (!mem)
4559                 return I40E_ERR_PARAM;
4560
4561         mem->size = size;
4562         mem->va = rte_zmalloc("i40e", size, 0);
4563
4564         if (mem->va)
4565                 return I40E_SUCCESS;
4566         else
4567                 return I40E_ERR_NO_MEMORY;
4568 }
4569
4570 /**
4571  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4572  * @hw:   pointer to the HW structure
4573  * @mem:  pointer to mem struct to free
4574  **/
4575 enum i40e_status_code
4576 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4577                      struct i40e_virt_mem *mem)
4578 {
4579         if (!mem)
4580                 return I40E_ERR_PARAM;
4581
4582         rte_free(mem->va);
4583         mem->va = NULL;
4584
4585         return I40E_SUCCESS;
4586 }
4587
4588 void
4589 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4590 {
4591         rte_spinlock_init(&sp->spinlock);
4592 }
4593
4594 void
4595 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4596 {
4597         rte_spinlock_lock(&sp->spinlock);
4598 }
4599
4600 void
4601 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4602 {
4603         rte_spinlock_unlock(&sp->spinlock);
4604 }
4605
4606 void
4607 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4608 {
4609         return;
4610 }
4611
4612 /**
4613  * Get the hardware capabilities, which will be parsed
4614  * and saved into struct i40e_hw.
4615  */
4616 static int
4617 i40e_get_cap(struct i40e_hw *hw)
4618 {
4619         struct i40e_aqc_list_capabilities_element_resp *buf;
4620         uint16_t len, size = 0;
4621         int ret;
4622
4623         /* Calculate a huge enough buff for saving response data temporarily */
4624         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4625                                                 I40E_MAX_CAP_ELE_NUM;
4626         buf = rte_zmalloc("i40e", len, 0);
4627         if (!buf) {
4628                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4629                 return I40E_ERR_NO_MEMORY;
4630         }
4631
4632         /* Get, parse the capabilities and save it to hw */
4633         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4634                         i40e_aqc_opc_list_func_capabilities, NULL);
4635         if (ret != I40E_SUCCESS)
4636                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4637
4638         /* Free the temporary buffer after being used */
4639         rte_free(buf);
4640
4641         return ret;
4642 }
4643
4644 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4645
4646 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4647                 const char *value,
4648                 void *opaque)
4649 {
4650         struct i40e_pf *pf;
4651         unsigned long num;
4652         char *end;
4653
4654         pf = (struct i40e_pf *)opaque;
4655         RTE_SET_USED(key);
4656
4657         errno = 0;
4658         num = strtoul(value, &end, 0);
4659         if (errno != 0 || end == value || *end != 0) {
4660                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4661                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4662                 return -(EINVAL);
4663         }
4664
4665         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4666                 pf->vf_nb_qp_max = (uint16_t)num;
4667         else
4668                 /* here return 0 to make next valid same argument work */
4669                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4670                             "power of 2 and equal or less than 16 !, Now it is "
4671                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4672
4673         return 0;
4674 }
4675
4676 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4677 {
4678         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4679         struct rte_kvargs *kvlist;
4680         int kvargs_count;
4681
4682         /* set default queue number per VF as 4 */
4683         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4684
4685         if (dev->device->devargs == NULL)
4686                 return 0;
4687
4688         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4689         if (kvlist == NULL)
4690                 return -(EINVAL);
4691
4692         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4693         if (!kvargs_count) {
4694                 rte_kvargs_free(kvlist);
4695                 return 0;
4696         }
4697
4698         if (kvargs_count > 1)
4699                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4700                             "the first invalid or last valid one is used !",
4701                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4702
4703         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4704                            i40e_pf_parse_vf_queue_number_handler, pf);
4705
4706         rte_kvargs_free(kvlist);
4707
4708         return 0;
4709 }
4710
4711 static int
4712 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4713 {
4714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4715         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4716         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4717         uint16_t qp_count = 0, vsi_count = 0;
4718
4719         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4720                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4721                 return -EINVAL;
4722         }
4723
4724         i40e_pf_config_vf_rxq_number(dev);
4725
4726         /* Add the parameter init for LFC */
4727         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4728         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4729         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4730
4731         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4732         pf->max_num_vsi = hw->func_caps.num_vsis;
4733         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4734         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4735
4736         /* FDir queue/VSI allocation */
4737         pf->fdir_qp_offset = 0;
4738         if (hw->func_caps.fd) {
4739                 pf->flags |= I40E_FLAG_FDIR;
4740                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4741         } else {
4742                 pf->fdir_nb_qps = 0;
4743         }
4744         qp_count += pf->fdir_nb_qps;
4745         vsi_count += 1;
4746
4747         /* LAN queue/VSI allocation */
4748         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4749         if (!hw->func_caps.rss) {
4750                 pf->lan_nb_qps = 1;
4751         } else {
4752                 pf->flags |= I40E_FLAG_RSS;
4753                 if (hw->mac.type == I40E_MAC_X722)
4754                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4755                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4756         }
4757         qp_count += pf->lan_nb_qps;
4758         vsi_count += 1;
4759
4760         /* VF queue/VSI allocation */
4761         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4762         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4763                 pf->flags |= I40E_FLAG_SRIOV;
4764                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4765                 pf->vf_num = pci_dev->max_vfs;
4766                 PMD_DRV_LOG(DEBUG,
4767                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4768                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4769         } else {
4770                 pf->vf_nb_qps = 0;
4771                 pf->vf_num = 0;
4772         }
4773         qp_count += pf->vf_nb_qps * pf->vf_num;
4774         vsi_count += pf->vf_num;
4775
4776         /* VMDq queue/VSI allocation */
4777         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4778         pf->vmdq_nb_qps = 0;
4779         pf->max_nb_vmdq_vsi = 0;
4780         if (hw->func_caps.vmdq) {
4781                 if (qp_count < hw->func_caps.num_tx_qp &&
4782                         vsi_count < hw->func_caps.num_vsis) {
4783                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4784                                 qp_count) / pf->vmdq_nb_qp_max;
4785
4786                         /* Limit the maximum number of VMDq vsi to the maximum
4787                          * ethdev can support
4788                          */
4789                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4790                                 hw->func_caps.num_vsis - vsi_count);
4791                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4792                                 ETH_64_POOLS);
4793                         if (pf->max_nb_vmdq_vsi) {
4794                                 pf->flags |= I40E_FLAG_VMDQ;
4795                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4796                                 PMD_DRV_LOG(DEBUG,
4797                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4798                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4799                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4800                         } else {
4801                                 PMD_DRV_LOG(INFO,
4802                                         "No enough queues left for VMDq");
4803                         }
4804                 } else {
4805                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4806                 }
4807         }
4808         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4809         vsi_count += pf->max_nb_vmdq_vsi;
4810
4811         if (hw->func_caps.dcb)
4812                 pf->flags |= I40E_FLAG_DCB;
4813
4814         if (qp_count > hw->func_caps.num_tx_qp) {
4815                 PMD_DRV_LOG(ERR,
4816                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4817                         qp_count, hw->func_caps.num_tx_qp);
4818                 return -EINVAL;
4819         }
4820         if (vsi_count > hw->func_caps.num_vsis) {
4821                 PMD_DRV_LOG(ERR,
4822                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4823                         vsi_count, hw->func_caps.num_vsis);
4824                 return -EINVAL;
4825         }
4826
4827         return 0;
4828 }
4829
4830 static int
4831 i40e_pf_get_switch_config(struct i40e_pf *pf)
4832 {
4833         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4834         struct i40e_aqc_get_switch_config_resp *switch_config;
4835         struct i40e_aqc_switch_config_element_resp *element;
4836         uint16_t start_seid = 0, num_reported;
4837         int ret;
4838
4839         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4840                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4841         if (!switch_config) {
4842                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4843                 return -ENOMEM;
4844         }
4845
4846         /* Get the switch configurations */
4847         ret = i40e_aq_get_switch_config(hw, switch_config,
4848                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4849         if (ret != I40E_SUCCESS) {
4850                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4851                 goto fail;
4852         }
4853         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4854         if (num_reported != 1) { /* The number should be 1 */
4855                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4856                 goto fail;
4857         }
4858
4859         /* Parse the switch configuration elements */
4860         element = &(switch_config->element[0]);
4861         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4862                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4863                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4864         } else
4865                 PMD_DRV_LOG(INFO, "Unknown element type");
4866
4867 fail:
4868         rte_free(switch_config);
4869
4870         return ret;
4871 }
4872
4873 static int
4874 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4875                         uint32_t num)
4876 {
4877         struct pool_entry *entry;
4878
4879         if (pool == NULL || num == 0)
4880                 return -EINVAL;
4881
4882         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4883         if (entry == NULL) {
4884                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4885                 return -ENOMEM;
4886         }
4887
4888         /* queue heap initialize */
4889         pool->num_free = num;
4890         pool->num_alloc = 0;
4891         pool->base = base;
4892         LIST_INIT(&pool->alloc_list);
4893         LIST_INIT(&pool->free_list);
4894
4895         /* Initialize element  */
4896         entry->base = 0;
4897         entry->len = num;
4898
4899         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4900         return 0;
4901 }
4902
4903 static void
4904 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4905 {
4906         struct pool_entry *entry, *next_entry;
4907
4908         if (pool == NULL)
4909                 return;
4910
4911         for (entry = LIST_FIRST(&pool->alloc_list);
4912                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4913                         entry = next_entry) {
4914                 LIST_REMOVE(entry, next);
4915                 rte_free(entry);
4916         }
4917
4918         for (entry = LIST_FIRST(&pool->free_list);
4919                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4920                         entry = next_entry) {
4921                 LIST_REMOVE(entry, next);
4922                 rte_free(entry);
4923         }
4924
4925         pool->num_free = 0;
4926         pool->num_alloc = 0;
4927         pool->base = 0;
4928         LIST_INIT(&pool->alloc_list);
4929         LIST_INIT(&pool->free_list);
4930 }
4931
4932 static int
4933 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4934                        uint32_t base)
4935 {
4936         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4937         uint32_t pool_offset;
4938         int insert;
4939
4940         if (pool == NULL) {
4941                 PMD_DRV_LOG(ERR, "Invalid parameter");
4942                 return -EINVAL;
4943         }
4944
4945         pool_offset = base - pool->base;
4946         /* Lookup in alloc list */
4947         LIST_FOREACH(entry, &pool->alloc_list, next) {
4948                 if (entry->base == pool_offset) {
4949                         valid_entry = entry;
4950                         LIST_REMOVE(entry, next);
4951                         break;
4952                 }
4953         }
4954
4955         /* Not find, return */
4956         if (valid_entry == NULL) {
4957                 PMD_DRV_LOG(ERR, "Failed to find entry");
4958                 return -EINVAL;
4959         }
4960
4961         /**
4962          * Found it, move it to free list  and try to merge.
4963          * In order to make merge easier, always sort it by qbase.
4964          * Find adjacent prev and last entries.
4965          */
4966         prev = next = NULL;
4967         LIST_FOREACH(entry, &pool->free_list, next) {
4968                 if (entry->base > valid_entry->base) {
4969                         next = entry;
4970                         break;
4971                 }
4972                 prev = entry;
4973         }
4974
4975         insert = 0;
4976         /* Try to merge with next one*/
4977         if (next != NULL) {
4978                 /* Merge with next one */
4979                 if (valid_entry->base + valid_entry->len == next->base) {
4980                         next->base = valid_entry->base;
4981                         next->len += valid_entry->len;
4982                         rte_free(valid_entry);
4983                         valid_entry = next;
4984                         insert = 1;
4985                 }
4986         }
4987
4988         if (prev != NULL) {
4989                 /* Merge with previous one */
4990                 if (prev->base + prev->len == valid_entry->base) {
4991                         prev->len += valid_entry->len;
4992                         /* If it merge with next one, remove next node */
4993                         if (insert == 1) {
4994                                 LIST_REMOVE(valid_entry, next);
4995                                 rte_free(valid_entry);
4996                         } else {
4997                                 rte_free(valid_entry);
4998                                 insert = 1;
4999                         }
5000                 }
5001         }
5002
5003         /* Not find any entry to merge, insert */
5004         if (insert == 0) {
5005                 if (prev != NULL)
5006                         LIST_INSERT_AFTER(prev, valid_entry, next);
5007                 else if (next != NULL)
5008                         LIST_INSERT_BEFORE(next, valid_entry, next);
5009                 else /* It's empty list, insert to head */
5010                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5011         }
5012
5013         pool->num_free += valid_entry->len;
5014         pool->num_alloc -= valid_entry->len;
5015
5016         return 0;
5017 }
5018
5019 static int
5020 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5021                        uint16_t num)
5022 {
5023         struct pool_entry *entry, *valid_entry;
5024
5025         if (pool == NULL || num == 0) {
5026                 PMD_DRV_LOG(ERR, "Invalid parameter");
5027                 return -EINVAL;
5028         }
5029
5030         if (pool->num_free < num) {
5031                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5032                             num, pool->num_free);
5033                 return -ENOMEM;
5034         }
5035
5036         valid_entry = NULL;
5037         /* Lookup  in free list and find most fit one */
5038         LIST_FOREACH(entry, &pool->free_list, next) {
5039                 if (entry->len >= num) {
5040                         /* Find best one */
5041                         if (entry->len == num) {
5042                                 valid_entry = entry;
5043                                 break;
5044                         }
5045                         if (valid_entry == NULL || valid_entry->len > entry->len)
5046                                 valid_entry = entry;
5047                 }
5048         }
5049
5050         /* Not find one to satisfy the request, return */
5051         if (valid_entry == NULL) {
5052                 PMD_DRV_LOG(ERR, "No valid entry found");
5053                 return -ENOMEM;
5054         }
5055         /**
5056          * The entry have equal queue number as requested,
5057          * remove it from alloc_list.
5058          */
5059         if (valid_entry->len == num) {
5060                 LIST_REMOVE(valid_entry, next);
5061         } else {
5062                 /**
5063                  * The entry have more numbers than requested,
5064                  * create a new entry for alloc_list and minus its
5065                  * queue base and number in free_list.
5066                  */
5067                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5068                 if (entry == NULL) {
5069                         PMD_DRV_LOG(ERR,
5070                                 "Failed to allocate memory for resource pool");
5071                         return -ENOMEM;
5072                 }
5073                 entry->base = valid_entry->base;
5074                 entry->len = num;
5075                 valid_entry->base += num;
5076                 valid_entry->len -= num;
5077                 valid_entry = entry;
5078         }
5079
5080         /* Insert it into alloc list, not sorted */
5081         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5082
5083         pool->num_free -= valid_entry->len;
5084         pool->num_alloc += valid_entry->len;
5085
5086         return valid_entry->base + pool->base;
5087 }
5088
5089 /**
5090  * bitmap_is_subset - Check whether src2 is subset of src1
5091  **/
5092 static inline int
5093 bitmap_is_subset(uint8_t src1, uint8_t src2)
5094 {
5095         return !((src1 ^ src2) & src2);
5096 }
5097
5098 static enum i40e_status_code
5099 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5100 {
5101         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5102
5103         /* If DCB is not supported, only default TC is supported */
5104         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5105                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5106                 return I40E_NOT_SUPPORTED;
5107         }
5108
5109         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5110                 PMD_DRV_LOG(ERR,
5111                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5112                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5113                 return I40E_NOT_SUPPORTED;
5114         }
5115         return I40E_SUCCESS;
5116 }
5117
5118 int
5119 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5120                                 struct i40e_vsi_vlan_pvid_info *info)
5121 {
5122         struct i40e_hw *hw;
5123         struct i40e_vsi_context ctxt;
5124         uint8_t vlan_flags = 0;
5125         int ret;
5126
5127         if (vsi == NULL || info == NULL) {
5128                 PMD_DRV_LOG(ERR, "invalid parameters");
5129                 return I40E_ERR_PARAM;
5130         }
5131
5132         if (info->on) {
5133                 vsi->info.pvid = info->config.pvid;
5134                 /**
5135                  * If insert pvid is enabled, only tagged pkts are
5136                  * allowed to be sent out.
5137                  */
5138                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5139                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5140         } else {
5141                 vsi->info.pvid = 0;
5142                 if (info->config.reject.tagged == 0)
5143                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5144
5145                 if (info->config.reject.untagged == 0)
5146                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5147         }
5148         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5149                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5150         vsi->info.port_vlan_flags |= vlan_flags;
5151         vsi->info.valid_sections =
5152                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5153         memset(&ctxt, 0, sizeof(ctxt));
5154         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5155         ctxt.seid = vsi->seid;
5156
5157         hw = I40E_VSI_TO_HW(vsi);
5158         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5159         if (ret != I40E_SUCCESS)
5160                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5161
5162         return ret;
5163 }
5164
5165 static int
5166 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5167 {
5168         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5169         int i, ret;
5170         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5171
5172         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5173         if (ret != I40E_SUCCESS)
5174                 return ret;
5175
5176         if (!vsi->seid) {
5177                 PMD_DRV_LOG(ERR, "seid not valid");
5178                 return -EINVAL;
5179         }
5180
5181         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5182         tc_bw_data.tc_valid_bits = enabled_tcmap;
5183         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5184                 tc_bw_data.tc_bw_credits[i] =
5185                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5186
5187         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5188         if (ret != I40E_SUCCESS) {
5189                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5190                 return ret;
5191         }
5192
5193         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5194                                         sizeof(vsi->info.qs_handle));
5195         return I40E_SUCCESS;
5196 }
5197
5198 static enum i40e_status_code
5199 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5200                                  struct i40e_aqc_vsi_properties_data *info,
5201                                  uint8_t enabled_tcmap)
5202 {
5203         enum i40e_status_code ret;
5204         int i, total_tc = 0;
5205         uint16_t qpnum_per_tc, bsf, qp_idx;
5206
5207         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5208         if (ret != I40E_SUCCESS)
5209                 return ret;
5210
5211         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5212                 if (enabled_tcmap & (1 << i))
5213                         total_tc++;
5214         if (total_tc == 0)
5215                 total_tc = 1;
5216         vsi->enabled_tc = enabled_tcmap;
5217
5218         /* Number of queues per enabled TC */
5219         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5220         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5221         bsf = rte_bsf32(qpnum_per_tc);
5222
5223         /* Adjust the queue number to actual queues that can be applied */
5224         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5225                 vsi->nb_qps = qpnum_per_tc * total_tc;
5226
5227         /**
5228          * Configure TC and queue mapping parameters, for enabled TC,
5229          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5230          * default queue will serve it.
5231          */
5232         qp_idx = 0;
5233         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5234                 if (vsi->enabled_tc & (1 << i)) {
5235                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5236                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5237                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5238                         qp_idx += qpnum_per_tc;
5239                 } else
5240                         info->tc_mapping[i] = 0;
5241         }
5242
5243         /* Associate queue number with VSI */
5244         if (vsi->type == I40E_VSI_SRIOV) {
5245                 info->mapping_flags |=
5246                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5247                 for (i = 0; i < vsi->nb_qps; i++)
5248                         info->queue_mapping[i] =
5249                                 rte_cpu_to_le_16(vsi->base_queue + i);
5250         } else {
5251                 info->mapping_flags |=
5252                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5253                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5254         }
5255         info->valid_sections |=
5256                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5257
5258         return I40E_SUCCESS;
5259 }
5260
5261 static int
5262 i40e_veb_release(struct i40e_veb *veb)
5263 {
5264         struct i40e_vsi *vsi;
5265         struct i40e_hw *hw;
5266
5267         if (veb == NULL)
5268                 return -EINVAL;
5269
5270         if (!TAILQ_EMPTY(&veb->head)) {
5271                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5272                 return -EACCES;
5273         }
5274         /* associate_vsi field is NULL for floating VEB */
5275         if (veb->associate_vsi != NULL) {
5276                 vsi = veb->associate_vsi;
5277                 hw = I40E_VSI_TO_HW(vsi);
5278
5279                 vsi->uplink_seid = veb->uplink_seid;
5280                 vsi->veb = NULL;
5281         } else {
5282                 veb->associate_pf->main_vsi->floating_veb = NULL;
5283                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5284         }
5285
5286         i40e_aq_delete_element(hw, veb->seid, NULL);
5287         rte_free(veb);
5288         return I40E_SUCCESS;
5289 }
5290
5291 /* Setup a veb */
5292 static struct i40e_veb *
5293 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5294 {
5295         struct i40e_veb *veb;
5296         int ret;
5297         struct i40e_hw *hw;
5298
5299         if (pf == NULL) {
5300                 PMD_DRV_LOG(ERR,
5301                             "veb setup failed, associated PF shouldn't null");
5302                 return NULL;
5303         }
5304         hw = I40E_PF_TO_HW(pf);
5305
5306         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5307         if (!veb) {
5308                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5309                 goto fail;
5310         }
5311
5312         veb->associate_vsi = vsi;
5313         veb->associate_pf = pf;
5314         TAILQ_INIT(&veb->head);
5315         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5316
5317         /* create floating veb if vsi is NULL */
5318         if (vsi != NULL) {
5319                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5320                                       I40E_DEFAULT_TCMAP, false,
5321                                       &veb->seid, false, NULL);
5322         } else {
5323                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5324                                       true, &veb->seid, false, NULL);
5325         }
5326
5327         if (ret != I40E_SUCCESS) {
5328                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5329                             hw->aq.asq_last_status);
5330                 goto fail;
5331         }
5332         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5333
5334         /* get statistics index */
5335         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5336                                 &veb->stats_idx, NULL, NULL, NULL);
5337         if (ret != I40E_SUCCESS) {
5338                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5339                             hw->aq.asq_last_status);
5340                 goto fail;
5341         }
5342         /* Get VEB bandwidth, to be implemented */
5343         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5344         if (vsi)
5345                 vsi->uplink_seid = veb->seid;
5346
5347         return veb;
5348 fail:
5349         rte_free(veb);
5350         return NULL;
5351 }
5352
5353 int
5354 i40e_vsi_release(struct i40e_vsi *vsi)
5355 {
5356         struct i40e_pf *pf;
5357         struct i40e_hw *hw;
5358         struct i40e_vsi_list *vsi_list;
5359         void *temp;
5360         int ret;
5361         struct i40e_mac_filter *f;
5362         uint16_t user_param;
5363
5364         if (!vsi)
5365                 return I40E_SUCCESS;
5366
5367         if (!vsi->adapter)
5368                 return -EFAULT;
5369
5370         user_param = vsi->user_param;
5371
5372         pf = I40E_VSI_TO_PF(vsi);
5373         hw = I40E_VSI_TO_HW(vsi);
5374
5375         /* VSI has child to attach, release child first */
5376         if (vsi->veb) {
5377                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5378                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5379                                 return -1;
5380                 }
5381                 i40e_veb_release(vsi->veb);
5382         }
5383
5384         if (vsi->floating_veb) {
5385                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5386                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5387                                 return -1;
5388                 }
5389         }
5390
5391         /* Remove all macvlan filters of the VSI */
5392         i40e_vsi_remove_all_macvlan_filter(vsi);
5393         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5394                 rte_free(f);
5395
5396         if (vsi->type != I40E_VSI_MAIN &&
5397             ((vsi->type != I40E_VSI_SRIOV) ||
5398             !pf->floating_veb_list[user_param])) {
5399                 /* Remove vsi from parent's sibling list */
5400                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5401                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5402                         return I40E_ERR_PARAM;
5403                 }
5404                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5405                                 &vsi->sib_vsi_list, list);
5406
5407                 /* Remove all switch element of the VSI */
5408                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5409                 if (ret != I40E_SUCCESS)
5410                         PMD_DRV_LOG(ERR, "Failed to delete element");
5411         }
5412
5413         if ((vsi->type == I40E_VSI_SRIOV) &&
5414             pf->floating_veb_list[user_param]) {
5415                 /* Remove vsi from parent's sibling list */
5416                 if (vsi->parent_vsi == NULL ||
5417                     vsi->parent_vsi->floating_veb == NULL) {
5418                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5419                         return I40E_ERR_PARAM;
5420                 }
5421                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5422                              &vsi->sib_vsi_list, list);
5423
5424                 /* Remove all switch element of the VSI */
5425                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5426                 if (ret != I40E_SUCCESS)
5427                         PMD_DRV_LOG(ERR, "Failed to delete element");
5428         }
5429
5430         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5431
5432         if (vsi->type != I40E_VSI_SRIOV)
5433                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5434         rte_free(vsi);
5435
5436         return I40E_SUCCESS;
5437 }
5438
5439 static int
5440 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5441 {
5442         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5443         struct i40e_aqc_remove_macvlan_element_data def_filter;
5444         struct i40e_mac_filter_info filter;
5445         int ret;
5446
5447         if (vsi->type != I40E_VSI_MAIN)
5448                 return I40E_ERR_CONFIG;
5449         memset(&def_filter, 0, sizeof(def_filter));
5450         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5451                                         ETH_ADDR_LEN);
5452         def_filter.vlan_tag = 0;
5453         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5454                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5455         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5456         if (ret != I40E_SUCCESS) {
5457                 struct i40e_mac_filter *f;
5458                 struct rte_ether_addr *mac;
5459
5460                 PMD_DRV_LOG(DEBUG,
5461                             "Cannot remove the default macvlan filter");
5462                 /* It needs to add the permanent mac into mac list */
5463                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5464                 if (f == NULL) {
5465                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5466                         return I40E_ERR_NO_MEMORY;
5467                 }
5468                 mac = &f->mac_info.mac_addr;
5469                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5470                                 ETH_ADDR_LEN);
5471                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5472                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5473                 vsi->mac_num++;
5474
5475                 return ret;
5476         }
5477         rte_memcpy(&filter.mac_addr,
5478                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5479         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5480         return i40e_vsi_add_mac(vsi, &filter);
5481 }
5482
5483 /*
5484  * i40e_vsi_get_bw_config - Query VSI BW Information
5485  * @vsi: the VSI to be queried
5486  *
5487  * Returns 0 on success, negative value on failure
5488  */
5489 static enum i40e_status_code
5490 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5491 {
5492         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5493         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5494         struct i40e_hw *hw = &vsi->adapter->hw;
5495         i40e_status ret;
5496         int i;
5497         uint32_t bw_max;
5498
5499         memset(&bw_config, 0, sizeof(bw_config));
5500         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5501         if (ret != I40E_SUCCESS) {
5502                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5503                             hw->aq.asq_last_status);
5504                 return ret;
5505         }
5506
5507         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5508         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5509                                         &ets_sla_config, NULL);
5510         if (ret != I40E_SUCCESS) {
5511                 PMD_DRV_LOG(ERR,
5512                         "VSI failed to get TC bandwdith configuration %u",
5513                         hw->aq.asq_last_status);
5514                 return ret;
5515         }
5516
5517         /* store and print out BW info */
5518         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5519         vsi->bw_info.bw_max = bw_config.max_bw;
5520         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5521         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5522         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5523                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5524                      I40E_16_BIT_WIDTH);
5525         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5526                 vsi->bw_info.bw_ets_share_credits[i] =
5527                                 ets_sla_config.share_credits[i];
5528                 vsi->bw_info.bw_ets_credits[i] =
5529                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5530                 /* 4 bits per TC, 4th bit is reserved */
5531                 vsi->bw_info.bw_ets_max[i] =
5532                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5533                                   RTE_LEN2MASK(3, uint8_t));
5534                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5535                             vsi->bw_info.bw_ets_share_credits[i]);
5536                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5537                             vsi->bw_info.bw_ets_credits[i]);
5538                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5539                             vsi->bw_info.bw_ets_max[i]);
5540         }
5541
5542         return I40E_SUCCESS;
5543 }
5544
5545 /* i40e_enable_pf_lb
5546  * @pf: pointer to the pf structure
5547  *
5548  * allow loopback on pf
5549  */
5550 static inline void
5551 i40e_enable_pf_lb(struct i40e_pf *pf)
5552 {
5553         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5554         struct i40e_vsi_context ctxt;
5555         int ret;
5556
5557         /* Use the FW API if FW >= v5.0 */
5558         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5559                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5560                 return;
5561         }
5562
5563         memset(&ctxt, 0, sizeof(ctxt));
5564         ctxt.seid = pf->main_vsi_seid;
5565         ctxt.pf_num = hw->pf_id;
5566         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5567         if (ret) {
5568                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5569                             ret, hw->aq.asq_last_status);
5570                 return;
5571         }
5572         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5573         ctxt.info.valid_sections =
5574                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5575         ctxt.info.switch_id |=
5576                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5577
5578         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5579         if (ret)
5580                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5581                             hw->aq.asq_last_status);
5582 }
5583
5584 /* Setup a VSI */
5585 struct i40e_vsi *
5586 i40e_vsi_setup(struct i40e_pf *pf,
5587                enum i40e_vsi_type type,
5588                struct i40e_vsi *uplink_vsi,
5589                uint16_t user_param)
5590 {
5591         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5592         struct i40e_vsi *vsi;
5593         struct i40e_mac_filter_info filter;
5594         int ret;
5595         struct i40e_vsi_context ctxt;
5596         struct rte_ether_addr broadcast =
5597                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5598
5599         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5600             uplink_vsi == NULL) {
5601                 PMD_DRV_LOG(ERR,
5602                         "VSI setup failed, VSI link shouldn't be NULL");
5603                 return NULL;
5604         }
5605
5606         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5607                 PMD_DRV_LOG(ERR,
5608                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5609                 return NULL;
5610         }
5611
5612         /* two situations
5613          * 1.type is not MAIN and uplink vsi is not NULL
5614          * If uplink vsi didn't setup VEB, create one first under veb field
5615          * 2.type is SRIOV and the uplink is NULL
5616          * If floating VEB is NULL, create one veb under floating veb field
5617          */
5618
5619         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5620             uplink_vsi->veb == NULL) {
5621                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5622
5623                 if (uplink_vsi->veb == NULL) {
5624                         PMD_DRV_LOG(ERR, "VEB setup failed");
5625                         return NULL;
5626                 }
5627                 /* set ALLOWLOOPBACk on pf, when veb is created */
5628                 i40e_enable_pf_lb(pf);
5629         }
5630
5631         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5632             pf->main_vsi->floating_veb == NULL) {
5633                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5634
5635                 if (pf->main_vsi->floating_veb == NULL) {
5636                         PMD_DRV_LOG(ERR, "VEB setup failed");
5637                         return NULL;
5638                 }
5639         }
5640
5641         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5642         if (!vsi) {
5643                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5644                 return NULL;
5645         }
5646         TAILQ_INIT(&vsi->mac_list);
5647         vsi->type = type;
5648         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5649         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5650         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5651         vsi->user_param = user_param;
5652         vsi->vlan_anti_spoof_on = 0;
5653         vsi->vlan_filter_on = 0;
5654         /* Allocate queues */
5655         switch (vsi->type) {
5656         case I40E_VSI_MAIN  :
5657                 vsi->nb_qps = pf->lan_nb_qps;
5658                 break;
5659         case I40E_VSI_SRIOV :
5660                 vsi->nb_qps = pf->vf_nb_qps;
5661                 break;
5662         case I40E_VSI_VMDQ2:
5663                 vsi->nb_qps = pf->vmdq_nb_qps;
5664                 break;
5665         case I40E_VSI_FDIR:
5666                 vsi->nb_qps = pf->fdir_nb_qps;
5667                 break;
5668         default:
5669                 goto fail_mem;
5670         }
5671         /*
5672          * The filter status descriptor is reported in rx queue 0,
5673          * while the tx queue for fdir filter programming has no
5674          * such constraints, can be non-zero queues.
5675          * To simplify it, choose FDIR vsi use queue 0 pair.
5676          * To make sure it will use queue 0 pair, queue allocation
5677          * need be done before this function is called
5678          */
5679         if (type != I40E_VSI_FDIR) {
5680                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5681                         if (ret < 0) {
5682                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5683                                                 vsi->seid, ret);
5684                                 goto fail_mem;
5685                         }
5686                         vsi->base_queue = ret;
5687         } else
5688                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5689
5690         /* VF has MSIX interrupt in VF range, don't allocate here */
5691         if (type == I40E_VSI_MAIN) {
5692                 if (pf->support_multi_driver) {
5693                         /* If support multi-driver, need to use INT0 instead of
5694                          * allocating from msix pool. The Msix pool is init from
5695                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5696                          * to 1 without calling i40e_res_pool_alloc.
5697                          */
5698                         vsi->msix_intr = 0;
5699                         vsi->nb_msix = 1;
5700                 } else {
5701                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5702                                                   RTE_MIN(vsi->nb_qps,
5703                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5704                         if (ret < 0) {
5705                                 PMD_DRV_LOG(ERR,
5706                                             "VSI MAIN %d get heap failed %d",
5707                                             vsi->seid, ret);
5708                                 goto fail_queue_alloc;
5709                         }
5710                         vsi->msix_intr = ret;
5711                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5712                                                RTE_MAX_RXTX_INTR_VEC_ID);
5713                 }
5714         } else if (type != I40E_VSI_SRIOV) {
5715                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5716                 if (ret < 0) {
5717                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5718                         goto fail_queue_alloc;
5719                 }
5720                 vsi->msix_intr = ret;
5721                 vsi->nb_msix = 1;
5722         } else {
5723                 vsi->msix_intr = 0;
5724                 vsi->nb_msix = 0;
5725         }
5726
5727         /* Add VSI */
5728         if (type == I40E_VSI_MAIN) {
5729                 /* For main VSI, no need to add since it's default one */
5730                 vsi->uplink_seid = pf->mac_seid;
5731                 vsi->seid = pf->main_vsi_seid;
5732                 /* Bind queues with specific MSIX interrupt */
5733                 /**
5734                  * Needs 2 interrupt at least, one for misc cause which will
5735                  * enabled from OS side, Another for queues binding the
5736                  * interrupt from device side only.
5737                  */
5738
5739                 /* Get default VSI parameters from hardware */
5740                 memset(&ctxt, 0, sizeof(ctxt));
5741                 ctxt.seid = vsi->seid;
5742                 ctxt.pf_num = hw->pf_id;
5743                 ctxt.uplink_seid = vsi->uplink_seid;
5744                 ctxt.vf_num = 0;
5745                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5746                 if (ret != I40E_SUCCESS) {
5747                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5748                         goto fail_msix_alloc;
5749                 }
5750                 rte_memcpy(&vsi->info, &ctxt.info,
5751                         sizeof(struct i40e_aqc_vsi_properties_data));
5752                 vsi->vsi_id = ctxt.vsi_number;
5753                 vsi->info.valid_sections = 0;
5754
5755                 /* Configure tc, enabled TC0 only */
5756                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5757                         I40E_SUCCESS) {
5758                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5759                         goto fail_msix_alloc;
5760                 }
5761
5762                 /* TC, queue mapping */
5763                 memset(&ctxt, 0, sizeof(ctxt));
5764                 vsi->info.valid_sections |=
5765                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5766                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5767                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5768                 rte_memcpy(&ctxt.info, &vsi->info,
5769                         sizeof(struct i40e_aqc_vsi_properties_data));
5770                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5771                                                 I40E_DEFAULT_TCMAP);
5772                 if (ret != I40E_SUCCESS) {
5773                         PMD_DRV_LOG(ERR,
5774                                 "Failed to configure TC queue mapping");
5775                         goto fail_msix_alloc;
5776                 }
5777                 ctxt.seid = vsi->seid;
5778                 ctxt.pf_num = hw->pf_id;
5779                 ctxt.uplink_seid = vsi->uplink_seid;
5780                 ctxt.vf_num = 0;
5781
5782                 /* Update VSI parameters */
5783                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5784                 if (ret != I40E_SUCCESS) {
5785                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5786                         goto fail_msix_alloc;
5787                 }
5788
5789                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5790                                                 sizeof(vsi->info.tc_mapping));
5791                 rte_memcpy(&vsi->info.queue_mapping,
5792                                 &ctxt.info.queue_mapping,
5793                         sizeof(vsi->info.queue_mapping));
5794                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5795                 vsi->info.valid_sections = 0;
5796
5797                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5798                                 ETH_ADDR_LEN);
5799
5800                 /**
5801                  * Updating default filter settings are necessary to prevent
5802                  * reception of tagged packets.
5803                  * Some old firmware configurations load a default macvlan
5804                  * filter which accepts both tagged and untagged packets.
5805                  * The updating is to use a normal filter instead if needed.
5806                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5807                  * The firmware with correct configurations load the default
5808                  * macvlan filter which is expected and cannot be removed.
5809                  */
5810                 i40e_update_default_filter_setting(vsi);
5811                 i40e_config_qinq(hw, vsi);
5812         } else if (type == I40E_VSI_SRIOV) {
5813                 memset(&ctxt, 0, sizeof(ctxt));
5814                 /**
5815                  * For other VSI, the uplink_seid equals to uplink VSI's
5816                  * uplink_seid since they share same VEB
5817                  */
5818                 if (uplink_vsi == NULL)
5819                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5820                 else
5821                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5822                 ctxt.pf_num = hw->pf_id;
5823                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5824                 ctxt.uplink_seid = vsi->uplink_seid;
5825                 ctxt.connection_type = 0x1;
5826                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5827
5828                 /* Use the VEB configuration if FW >= v5.0 */
5829                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5830                         /* Configure switch ID */
5831                         ctxt.info.valid_sections |=
5832                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5833                         ctxt.info.switch_id =
5834                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5835                 }
5836
5837                 /* Configure port/vlan */
5838                 ctxt.info.valid_sections |=
5839                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5840                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5841                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5842                                                 hw->func_caps.enabled_tcmap);
5843                 if (ret != I40E_SUCCESS) {
5844                         PMD_DRV_LOG(ERR,
5845                                 "Failed to configure TC queue mapping");
5846                         goto fail_msix_alloc;
5847                 }
5848
5849                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5850                 ctxt.info.valid_sections |=
5851                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5852                 /**
5853                  * Since VSI is not created yet, only configure parameter,
5854                  * will add vsi below.
5855                  */
5856
5857                 i40e_config_qinq(hw, vsi);
5858         } else if (type == I40E_VSI_VMDQ2) {
5859                 memset(&ctxt, 0, sizeof(ctxt));
5860                 /*
5861                  * For other VSI, the uplink_seid equals to uplink VSI's
5862                  * uplink_seid since they share same VEB
5863                  */
5864                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5865                 ctxt.pf_num = hw->pf_id;
5866                 ctxt.vf_num = 0;
5867                 ctxt.uplink_seid = vsi->uplink_seid;
5868                 ctxt.connection_type = 0x1;
5869                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5870
5871                 ctxt.info.valid_sections |=
5872                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5873                 /* user_param carries flag to enable loop back */
5874                 if (user_param) {
5875                         ctxt.info.switch_id =
5876                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5877                         ctxt.info.switch_id |=
5878                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5879                 }
5880
5881                 /* Configure port/vlan */
5882                 ctxt.info.valid_sections |=
5883                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5884                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5885                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5886                                                 I40E_DEFAULT_TCMAP);
5887                 if (ret != I40E_SUCCESS) {
5888                         PMD_DRV_LOG(ERR,
5889                                 "Failed to configure TC queue mapping");
5890                         goto fail_msix_alloc;
5891                 }
5892                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5893                 ctxt.info.valid_sections |=
5894                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5895         } else if (type == I40E_VSI_FDIR) {
5896                 memset(&ctxt, 0, sizeof(ctxt));
5897                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5898                 ctxt.pf_num = hw->pf_id;
5899                 ctxt.vf_num = 0;
5900                 ctxt.uplink_seid = vsi->uplink_seid;
5901                 ctxt.connection_type = 0x1;     /* regular data port */
5902                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5903                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5904                                                 I40E_DEFAULT_TCMAP);
5905                 if (ret != I40E_SUCCESS) {
5906                         PMD_DRV_LOG(ERR,
5907                                 "Failed to configure TC queue mapping.");
5908                         goto fail_msix_alloc;
5909                 }
5910                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5911                 ctxt.info.valid_sections |=
5912                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5913         } else {
5914                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5915                 goto fail_msix_alloc;
5916         }
5917
5918         if (vsi->type != I40E_VSI_MAIN) {
5919                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5920                 if (ret != I40E_SUCCESS) {
5921                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5922                                     hw->aq.asq_last_status);
5923                         goto fail_msix_alloc;
5924                 }
5925                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5926                 vsi->info.valid_sections = 0;
5927                 vsi->seid = ctxt.seid;
5928                 vsi->vsi_id = ctxt.vsi_number;
5929                 vsi->sib_vsi_list.vsi = vsi;
5930                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5931                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5932                                           &vsi->sib_vsi_list, list);
5933                 } else {
5934                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5935                                           &vsi->sib_vsi_list, list);
5936                 }
5937         }
5938
5939         /* MAC/VLAN configuration */
5940         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5941         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5942
5943         ret = i40e_vsi_add_mac(vsi, &filter);
5944         if (ret != I40E_SUCCESS) {
5945                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5946                 goto fail_msix_alloc;
5947         }
5948
5949         /* Get VSI BW information */
5950         i40e_vsi_get_bw_config(vsi);
5951         return vsi;
5952 fail_msix_alloc:
5953         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5954 fail_queue_alloc:
5955         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5956 fail_mem:
5957         rte_free(vsi);
5958         return NULL;
5959 }
5960
5961 /* Configure vlan filter on or off */
5962 int
5963 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5964 {
5965         int i, num;
5966         struct i40e_mac_filter *f;
5967         void *temp;
5968         struct i40e_mac_filter_info *mac_filter;
5969         enum rte_mac_filter_type desired_filter;
5970         int ret = I40E_SUCCESS;
5971
5972         if (on) {
5973                 /* Filter to match MAC and VLAN */
5974                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5975         } else {
5976                 /* Filter to match only MAC */
5977                 desired_filter = RTE_MAC_PERFECT_MATCH;
5978         }
5979
5980         num = vsi->mac_num;
5981
5982         mac_filter = rte_zmalloc("mac_filter_info_data",
5983                                  num * sizeof(*mac_filter), 0);
5984         if (mac_filter == NULL) {
5985                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5986                 return I40E_ERR_NO_MEMORY;
5987         }
5988
5989         i = 0;
5990
5991         /* Remove all existing mac */
5992         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5993                 mac_filter[i] = f->mac_info;
5994                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5995                 if (ret) {
5996                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5997                                     on ? "enable" : "disable");
5998                         goto DONE;
5999                 }
6000                 i++;
6001         }
6002
6003         /* Override with new filter */
6004         for (i = 0; i < num; i++) {
6005                 mac_filter[i].filter_type = desired_filter;
6006                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6007                 if (ret) {
6008                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6009                                     on ? "enable" : "disable");
6010                         goto DONE;
6011                 }
6012         }
6013
6014 DONE:
6015         rte_free(mac_filter);
6016         return ret;
6017 }
6018
6019 /* Configure vlan stripping on or off */
6020 int
6021 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6022 {
6023         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6024         struct i40e_vsi_context ctxt;
6025         uint8_t vlan_flags;
6026         int ret = I40E_SUCCESS;
6027
6028         /* Check if it has been already on or off */
6029         if (vsi->info.valid_sections &
6030                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6031                 if (on) {
6032                         if ((vsi->info.port_vlan_flags &
6033                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6034                                 return 0; /* already on */
6035                 } else {
6036                         if ((vsi->info.port_vlan_flags &
6037                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6038                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6039                                 return 0; /* already off */
6040                 }
6041         }
6042
6043         if (on)
6044                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6045         else
6046                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6047         vsi->info.valid_sections =
6048                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6049         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6050         vsi->info.port_vlan_flags |= vlan_flags;
6051         ctxt.seid = vsi->seid;
6052         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6053         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6054         if (ret)
6055                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6056                             on ? "enable" : "disable");
6057
6058         return ret;
6059 }
6060
6061 static int
6062 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6063 {
6064         struct rte_eth_dev_data *data = dev->data;
6065         int ret;
6066         int mask = 0;
6067
6068         /* Apply vlan offload setting */
6069         mask = ETH_VLAN_STRIP_MASK |
6070                ETH_VLAN_FILTER_MASK |
6071                ETH_VLAN_EXTEND_MASK;
6072         ret = i40e_vlan_offload_set(dev, mask);
6073         if (ret) {
6074                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6075                 return ret;
6076         }
6077
6078         /* Apply pvid setting */
6079         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6080                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6081         if (ret)
6082                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6083
6084         return ret;
6085 }
6086
6087 static int
6088 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6089 {
6090         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6091
6092         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6093 }
6094
6095 static int
6096 i40e_update_flow_control(struct i40e_hw *hw)
6097 {
6098 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6099         struct i40e_link_status link_status;
6100         uint32_t rxfc = 0, txfc = 0, reg;
6101         uint8_t an_info;
6102         int ret;
6103
6104         memset(&link_status, 0, sizeof(link_status));
6105         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6106         if (ret != I40E_SUCCESS) {
6107                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6108                 goto write_reg; /* Disable flow control */
6109         }
6110
6111         an_info = hw->phy.link_info.an_info;
6112         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6113                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6114                 ret = I40E_ERR_NOT_READY;
6115                 goto write_reg; /* Disable flow control */
6116         }
6117         /**
6118          * If link auto negotiation is enabled, flow control needs to
6119          * be configured according to it
6120          */
6121         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6122         case I40E_LINK_PAUSE_RXTX:
6123                 rxfc = 1;
6124                 txfc = 1;
6125                 hw->fc.current_mode = I40E_FC_FULL;
6126                 break;
6127         case I40E_AQ_LINK_PAUSE_RX:
6128                 rxfc = 1;
6129                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6130                 break;
6131         case I40E_AQ_LINK_PAUSE_TX:
6132                 txfc = 1;
6133                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6134                 break;
6135         default:
6136                 hw->fc.current_mode = I40E_FC_NONE;
6137                 break;
6138         }
6139
6140 write_reg:
6141         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6142                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6143         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6144         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6145         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6146         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6147
6148         return ret;
6149 }
6150
6151 /* PF setup */
6152 static int
6153 i40e_pf_setup(struct i40e_pf *pf)
6154 {
6155         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6156         struct i40e_filter_control_settings settings;
6157         struct i40e_vsi *vsi;
6158         int ret;
6159
6160         /* Clear all stats counters */
6161         pf->offset_loaded = FALSE;
6162         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6163         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6164         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6165         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6166
6167         ret = i40e_pf_get_switch_config(pf);
6168         if (ret != I40E_SUCCESS) {
6169                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6170                 return ret;
6171         }
6172
6173         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6174         if (ret)
6175                 PMD_INIT_LOG(WARNING,
6176                         "failed to allocate switch domain for device %d", ret);
6177
6178         if (pf->flags & I40E_FLAG_FDIR) {
6179                 /* make queue allocated first, let FDIR use queue pair 0*/
6180                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6181                 if (ret != I40E_FDIR_QUEUE_ID) {
6182                         PMD_DRV_LOG(ERR,
6183                                 "queue allocation fails for FDIR: ret =%d",
6184                                 ret);
6185                         pf->flags &= ~I40E_FLAG_FDIR;
6186                 }
6187         }
6188         /*  main VSI setup */
6189         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6190         if (!vsi) {
6191                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6192                 return I40E_ERR_NOT_READY;
6193         }
6194         pf->main_vsi = vsi;
6195
6196         /* Configure filter control */
6197         memset(&settings, 0, sizeof(settings));
6198         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6199                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6200         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6201                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6202         else {
6203                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6204                         hw->func_caps.rss_table_size);
6205                 return I40E_ERR_PARAM;
6206         }
6207         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6208                 hw->func_caps.rss_table_size);
6209         pf->hash_lut_size = hw->func_caps.rss_table_size;
6210
6211         /* Enable ethtype and macvlan filters */
6212         settings.enable_ethtype = TRUE;
6213         settings.enable_macvlan = TRUE;
6214         ret = i40e_set_filter_control(hw, &settings);
6215         if (ret)
6216                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6217                                                                 ret);
6218
6219         /* Update flow control according to the auto negotiation */
6220         i40e_update_flow_control(hw);
6221
6222         return I40E_SUCCESS;
6223 }
6224
6225 int
6226 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6227 {
6228         uint32_t reg;
6229         uint16_t j;
6230
6231         /**
6232          * Set or clear TX Queue Disable flags,
6233          * which is required by hardware.
6234          */
6235         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6236         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6237
6238         /* Wait until the request is finished */
6239         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6240                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6241                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6242                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6243                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6244                                                         & 0x1))) {
6245                         break;
6246                 }
6247         }
6248         if (on) {
6249                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6250                         return I40E_SUCCESS; /* already on, skip next steps */
6251
6252                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6253                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6254         } else {
6255                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6256                         return I40E_SUCCESS; /* already off, skip next steps */
6257                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6258         }
6259         /* Write the register */
6260         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6261         /* Check the result */
6262         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6263                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6264                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6265                 if (on) {
6266                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6267                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6268                                 break;
6269                 } else {
6270                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6271                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6272                                 break;
6273                 }
6274         }
6275         /* Check if it is timeout */
6276         if (j >= I40E_CHK_Q_ENA_COUNT) {
6277                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6278                             (on ? "enable" : "disable"), q_idx);
6279                 return I40E_ERR_TIMEOUT;
6280         }
6281
6282         return I40E_SUCCESS;
6283 }
6284
6285 /* Swith on or off the tx queues */
6286 static int
6287 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6288 {
6289         struct rte_eth_dev_data *dev_data = pf->dev_data;
6290         struct i40e_tx_queue *txq;
6291         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6292         uint16_t i;
6293         int ret;
6294
6295         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6296                 txq = dev_data->tx_queues[i];
6297                 /* Don't operate the queue if not configured or
6298                  * if starting only per queue */
6299                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6300                         continue;
6301                 if (on)
6302                         ret = i40e_dev_tx_queue_start(dev, i);
6303                 else
6304                         ret = i40e_dev_tx_queue_stop(dev, i);
6305                 if ( ret != I40E_SUCCESS)
6306                         return ret;
6307         }
6308
6309         return I40E_SUCCESS;
6310 }
6311
6312 int
6313 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6314 {
6315         uint32_t reg;
6316         uint16_t j;
6317
6318         /* Wait until the request is finished */
6319         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6320                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6321                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6322                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6323                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6324                         break;
6325         }
6326
6327         if (on) {
6328                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6329                         return I40E_SUCCESS; /* Already on, skip next steps */
6330                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6331         } else {
6332                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6333                         return I40E_SUCCESS; /* Already off, skip next steps */
6334                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6335         }
6336
6337         /* Write the register */
6338         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6339         /* Check the result */
6340         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6341                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6342                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6343                 if (on) {
6344                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6345                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6346                                 break;
6347                 } else {
6348                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6349                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6350                                 break;
6351                 }
6352         }
6353
6354         /* Check if it is timeout */
6355         if (j >= I40E_CHK_Q_ENA_COUNT) {
6356                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6357                             (on ? "enable" : "disable"), q_idx);
6358                 return I40E_ERR_TIMEOUT;
6359         }
6360
6361         return I40E_SUCCESS;
6362 }
6363 /* Switch on or off the rx queues */
6364 static int
6365 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6366 {
6367         struct rte_eth_dev_data *dev_data = pf->dev_data;
6368         struct i40e_rx_queue *rxq;
6369         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6370         uint16_t i;
6371         int ret;
6372
6373         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6374                 rxq = dev_data->rx_queues[i];
6375                 /* Don't operate the queue if not configured or
6376                  * if starting only per queue */
6377                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6378                         continue;
6379                 if (on)
6380                         ret = i40e_dev_rx_queue_start(dev, i);
6381                 else
6382                         ret = i40e_dev_rx_queue_stop(dev, i);
6383                 if (ret != I40E_SUCCESS)
6384                         return ret;
6385         }
6386
6387         return I40E_SUCCESS;
6388 }
6389
6390 /* Switch on or off all the rx/tx queues */
6391 int
6392 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6393 {
6394         int ret;
6395
6396         if (on) {
6397                 /* enable rx queues before enabling tx queues */
6398                 ret = i40e_dev_switch_rx_queues(pf, on);
6399                 if (ret) {
6400                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6401                         return ret;
6402                 }
6403                 ret = i40e_dev_switch_tx_queues(pf, on);
6404         } else {
6405                 /* Stop tx queues before stopping rx queues */
6406                 ret = i40e_dev_switch_tx_queues(pf, on);
6407                 if (ret) {
6408                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6409                         return ret;
6410                 }
6411                 ret = i40e_dev_switch_rx_queues(pf, on);
6412         }
6413
6414         return ret;
6415 }
6416
6417 /* Initialize VSI for TX */
6418 static int
6419 i40e_dev_tx_init(struct i40e_pf *pf)
6420 {
6421         struct rte_eth_dev_data *data = pf->dev_data;
6422         uint16_t i;
6423         uint32_t ret = I40E_SUCCESS;
6424         struct i40e_tx_queue *txq;
6425
6426         for (i = 0; i < data->nb_tx_queues; i++) {
6427                 txq = data->tx_queues[i];
6428                 if (!txq || !txq->q_set)
6429                         continue;
6430                 ret = i40e_tx_queue_init(txq);
6431                 if (ret != I40E_SUCCESS)
6432                         break;
6433         }
6434         if (ret == I40E_SUCCESS)
6435                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6436                                      ->eth_dev);
6437
6438         return ret;
6439 }
6440
6441 /* Initialize VSI for RX */
6442 static int
6443 i40e_dev_rx_init(struct i40e_pf *pf)
6444 {
6445         struct rte_eth_dev_data *data = pf->dev_data;
6446         int ret = I40E_SUCCESS;
6447         uint16_t i;
6448         struct i40e_rx_queue *rxq;
6449
6450         i40e_pf_config_mq_rx(pf);
6451         for (i = 0; i < data->nb_rx_queues; i++) {
6452                 rxq = data->rx_queues[i];
6453                 if (!rxq || !rxq->q_set)
6454                         continue;
6455
6456                 ret = i40e_rx_queue_init(rxq);
6457                 if (ret != I40E_SUCCESS) {
6458                         PMD_DRV_LOG(ERR,
6459                                 "Failed to do RX queue initialization");
6460                         break;
6461                 }
6462         }
6463         if (ret == I40E_SUCCESS)
6464                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6465                                      ->eth_dev);
6466
6467         return ret;
6468 }
6469
6470 static int
6471 i40e_dev_rxtx_init(struct i40e_pf *pf)
6472 {
6473         int err;
6474
6475         err = i40e_dev_tx_init(pf);
6476         if (err) {
6477                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6478                 return err;
6479         }
6480         err = i40e_dev_rx_init(pf);
6481         if (err) {
6482                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6483                 return err;
6484         }
6485
6486         return err;
6487 }
6488
6489 static int
6490 i40e_vmdq_setup(struct rte_eth_dev *dev)
6491 {
6492         struct rte_eth_conf *conf = &dev->data->dev_conf;
6493         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6494         int i, err, conf_vsis, j, loop;
6495         struct i40e_vsi *vsi;
6496         struct i40e_vmdq_info *vmdq_info;
6497         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6498         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6499
6500         /*
6501          * Disable interrupt to avoid message from VF. Furthermore, it will
6502          * avoid race condition in VSI creation/destroy.
6503          */
6504         i40e_pf_disable_irq0(hw);
6505
6506         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6507                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6508                 return -ENOTSUP;
6509         }
6510
6511         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6512         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6513                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6514                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6515                         pf->max_nb_vmdq_vsi);
6516                 return -ENOTSUP;
6517         }
6518
6519         if (pf->vmdq != NULL) {
6520                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6521                 return 0;
6522         }
6523
6524         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6525                                 sizeof(*vmdq_info) * conf_vsis, 0);
6526
6527         if (pf->vmdq == NULL) {
6528                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6529                 return -ENOMEM;
6530         }
6531
6532         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6533
6534         /* Create VMDQ VSI */
6535         for (i = 0; i < conf_vsis; i++) {
6536                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6537                                 vmdq_conf->enable_loop_back);
6538                 if (vsi == NULL) {
6539                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6540                         err = -1;
6541                         goto err_vsi_setup;
6542                 }
6543                 vmdq_info = &pf->vmdq[i];
6544                 vmdq_info->pf = pf;
6545                 vmdq_info->vsi = vsi;
6546         }
6547         pf->nb_cfg_vmdq_vsi = conf_vsis;
6548
6549         /* Configure Vlan */
6550         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6551         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6552                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6553                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6554                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6555                                         vmdq_conf->pool_map[i].vlan_id, j);
6556
6557                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6558                                                 vmdq_conf->pool_map[i].vlan_id);
6559                                 if (err) {
6560                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6561                                         err = -1;
6562                                         goto err_vsi_setup;
6563                                 }
6564                         }
6565                 }
6566         }
6567
6568         i40e_pf_enable_irq0(hw);
6569
6570         return 0;
6571
6572 err_vsi_setup:
6573         for (i = 0; i < conf_vsis; i++)
6574                 if (pf->vmdq[i].vsi == NULL)
6575                         break;
6576                 else
6577                         i40e_vsi_release(pf->vmdq[i].vsi);
6578
6579         rte_free(pf->vmdq);
6580         pf->vmdq = NULL;
6581         i40e_pf_enable_irq0(hw);
6582         return err;
6583 }
6584
6585 static void
6586 i40e_stat_update_32(struct i40e_hw *hw,
6587                    uint32_t reg,
6588                    bool offset_loaded,
6589                    uint64_t *offset,
6590                    uint64_t *stat)
6591 {
6592         uint64_t new_data;
6593
6594         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6595         if (!offset_loaded)
6596                 *offset = new_data;
6597
6598         if (new_data >= *offset)
6599                 *stat = (uint64_t)(new_data - *offset);
6600         else
6601                 *stat = (uint64_t)((new_data +
6602                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6603 }
6604
6605 static void
6606 i40e_stat_update_48(struct i40e_hw *hw,
6607                    uint32_t hireg,
6608                    uint32_t loreg,
6609                    bool offset_loaded,
6610                    uint64_t *offset,
6611                    uint64_t *stat)
6612 {
6613         uint64_t new_data;
6614
6615         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6616         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6617                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6618
6619         if (!offset_loaded)
6620                 *offset = new_data;
6621
6622         if (new_data >= *offset)
6623                 *stat = new_data - *offset;
6624         else
6625                 *stat = (uint64_t)((new_data +
6626                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6627
6628         *stat &= I40E_48_BIT_MASK;
6629 }
6630
6631 /* Disable IRQ0 */
6632 void
6633 i40e_pf_disable_irq0(struct i40e_hw *hw)
6634 {
6635         /* Disable all interrupt types */
6636         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6637                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6638         I40E_WRITE_FLUSH(hw);
6639 }
6640
6641 /* Enable IRQ0 */
6642 void
6643 i40e_pf_enable_irq0(struct i40e_hw *hw)
6644 {
6645         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6646                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6647                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6648                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6649         I40E_WRITE_FLUSH(hw);
6650 }
6651
6652 static void
6653 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6654 {
6655         /* read pending request and disable first */
6656         i40e_pf_disable_irq0(hw);
6657         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6658         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6659                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6660
6661         if (no_queue)
6662                 /* Link no queues with irq0 */
6663                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6664                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6665 }
6666
6667 static void
6668 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6669 {
6670         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6671         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6672         int i;
6673         uint16_t abs_vf_id;
6674         uint32_t index, offset, val;
6675
6676         if (!pf->vfs)
6677                 return;
6678         /**
6679          * Try to find which VF trigger a reset, use absolute VF id to access
6680          * since the reg is global register.
6681          */
6682         for (i = 0; i < pf->vf_num; i++) {
6683                 abs_vf_id = hw->func_caps.vf_base_id + i;
6684                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6685                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6686                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6687                 /* VFR event occurred */
6688                 if (val & (0x1 << offset)) {
6689                         int ret;
6690
6691                         /* Clear the event first */
6692                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6693                                                         (0x1 << offset));
6694                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6695                         /**
6696                          * Only notify a VF reset event occurred,
6697                          * don't trigger another SW reset
6698                          */
6699                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6700                         if (ret != I40E_SUCCESS)
6701                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6702                 }
6703         }
6704 }
6705
6706 static void
6707 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6708 {
6709         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6710         int i;
6711
6712         for (i = 0; i < pf->vf_num; i++)
6713                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6714 }
6715
6716 static void
6717 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6718 {
6719         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6720         struct i40e_arq_event_info info;
6721         uint16_t pending, opcode;
6722         int ret;
6723
6724         info.buf_len = I40E_AQ_BUF_SZ;
6725         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6726         if (!info.msg_buf) {
6727                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6728                 return;
6729         }
6730
6731         pending = 1;
6732         while (pending) {
6733                 ret = i40e_clean_arq_element(hw, &info, &pending);
6734
6735                 if (ret != I40E_SUCCESS) {
6736                         PMD_DRV_LOG(INFO,
6737                                 "Failed to read msg from AdminQ, aq_err: %u",
6738                                 hw->aq.asq_last_status);
6739                         break;
6740                 }
6741                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6742
6743                 switch (opcode) {
6744                 case i40e_aqc_opc_send_msg_to_pf:
6745                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6746                         i40e_pf_host_handle_vf_msg(dev,
6747                                         rte_le_to_cpu_16(info.desc.retval),
6748                                         rte_le_to_cpu_32(info.desc.cookie_high),
6749                                         rte_le_to_cpu_32(info.desc.cookie_low),
6750                                         info.msg_buf,
6751                                         info.msg_len);
6752                         break;
6753                 case i40e_aqc_opc_get_link_status:
6754                         ret = i40e_dev_link_update(dev, 0);
6755                         if (!ret)
6756                                 _rte_eth_dev_callback_process(dev,
6757                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6758                         break;
6759                 default:
6760                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6761                                     opcode);
6762                         break;
6763                 }
6764         }
6765         rte_free(info.msg_buf);
6766 }
6767
6768 static void
6769 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6770 {
6771 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6772 #define I40E_MDD_CLEAR16 0xFFFF
6773         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6774         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6775         bool mdd_detected = false;
6776         struct i40e_pf_vf *vf;
6777         uint32_t reg;
6778         int i;
6779
6780         /* find what triggered the MDD event */
6781         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6782         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6783                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6784                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6785                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6786                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6787                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6788                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6789                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6790                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6791                                         hw->func_caps.base_queue;
6792                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6793                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6794                                 event, queue, pf_num, vf_num, dev->data->name);
6795                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6796                 mdd_detected = true;
6797         }
6798         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6799         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6800                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6801                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6802                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6803                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6804                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6805                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6806                                         hw->func_caps.base_queue;
6807
6808                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6809                                 "queue %d of function 0x%02x device %s\n",
6810                                         event, queue, func, dev->data->name);
6811                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6812                 mdd_detected = true;
6813         }
6814
6815         if (mdd_detected) {
6816                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6817                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6818                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6819                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6820                 }
6821                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6822                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6823                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6824                                         I40E_MDD_CLEAR16);
6825                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6826                 }
6827         }
6828
6829         /* see if one of the VFs needs its hand slapped */
6830         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6831                 vf = &pf->vfs[i];
6832                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6833                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6834                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6835                                         I40E_MDD_CLEAR16);
6836                         vf->num_mdd_events++;
6837                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6838                                         PRIu64 "times\n",
6839                                         i, vf->num_mdd_events);
6840                 }
6841
6842                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6843                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6844                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6845                                         I40E_MDD_CLEAR16);
6846                         vf->num_mdd_events++;
6847                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6848                                         PRIu64 "times\n",
6849                                         i, vf->num_mdd_events);
6850                 }
6851         }
6852 }
6853
6854 /**
6855  * Interrupt handler triggered by NIC  for handling
6856  * specific interrupt.
6857  *
6858  * @param handle
6859  *  Pointer to interrupt handle.
6860  * @param param
6861  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6862  *
6863  * @return
6864  *  void
6865  */
6866 static void
6867 i40e_dev_interrupt_handler(void *param)
6868 {
6869         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6871         uint32_t icr0;
6872
6873         /* Disable interrupt */
6874         i40e_pf_disable_irq0(hw);
6875
6876         /* read out interrupt causes */
6877         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6878
6879         /* No interrupt event indicated */
6880         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6881                 PMD_DRV_LOG(INFO, "No interrupt event");
6882                 goto done;
6883         }
6884         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6885                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6886         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6887                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6888                 i40e_handle_mdd_event(dev);
6889         }
6890         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6891                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6892         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6893                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6894         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6895                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6896         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6897                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6898         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6899                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6900
6901         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6902                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6903                 i40e_dev_handle_vfr_event(dev);
6904         }
6905         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6906                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6907                 i40e_dev_handle_aq_msg(dev);
6908         }
6909
6910 done:
6911         /* Enable interrupt */
6912         i40e_pf_enable_irq0(hw);
6913 }
6914
6915 static void
6916 i40e_dev_alarm_handler(void *param)
6917 {
6918         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6920         uint32_t icr0;
6921
6922         /* Disable interrupt */
6923         i40e_pf_disable_irq0(hw);
6924
6925         /* read out interrupt causes */
6926         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6927
6928         /* No interrupt event indicated */
6929         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6930                 goto done;
6931         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6932                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6933         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6934                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6935                 i40e_handle_mdd_event(dev);
6936         }
6937         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6938                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6939         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6940                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6941         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6942                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6943         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6944                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6945         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6946                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6947
6948         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6949                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6950                 i40e_dev_handle_vfr_event(dev);
6951         }
6952         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6953                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6954                 i40e_dev_handle_aq_msg(dev);
6955         }
6956
6957 done:
6958         /* Enable interrupt */
6959         i40e_pf_enable_irq0(hw);
6960         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6961                           i40e_dev_alarm_handler, dev);
6962 }
6963
6964 int
6965 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6966                          struct i40e_macvlan_filter *filter,
6967                          int total)
6968 {
6969         int ele_num, ele_buff_size;
6970         int num, actual_num, i;
6971         uint16_t flags;
6972         int ret = I40E_SUCCESS;
6973         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6974         struct i40e_aqc_add_macvlan_element_data *req_list;
6975
6976         if (filter == NULL  || total == 0)
6977                 return I40E_ERR_PARAM;
6978         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6979         ele_buff_size = hw->aq.asq_buf_size;
6980
6981         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6982         if (req_list == NULL) {
6983                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6984                 return I40E_ERR_NO_MEMORY;
6985         }
6986
6987         num = 0;
6988         do {
6989                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6990                 memset(req_list, 0, ele_buff_size);
6991
6992                 for (i = 0; i < actual_num; i++) {
6993                         rte_memcpy(req_list[i].mac_addr,
6994                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6995                         req_list[i].vlan_tag =
6996                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6997
6998                         switch (filter[num + i].filter_type) {
6999                         case RTE_MAC_PERFECT_MATCH:
7000                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7001                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7002                                 break;
7003                         case RTE_MACVLAN_PERFECT_MATCH:
7004                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7005                                 break;
7006                         case RTE_MAC_HASH_MATCH:
7007                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7008                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7009                                 break;
7010                         case RTE_MACVLAN_HASH_MATCH:
7011                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7012                                 break;
7013                         default:
7014                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7015                                 ret = I40E_ERR_PARAM;
7016                                 goto DONE;
7017                         }
7018
7019                         req_list[i].queue_number = 0;
7020
7021                         req_list[i].flags = rte_cpu_to_le_16(flags);
7022                 }
7023
7024                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7025                                                 actual_num, NULL);
7026                 if (ret != I40E_SUCCESS) {
7027                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7028                         goto DONE;
7029                 }
7030                 num += actual_num;
7031         } while (num < total);
7032
7033 DONE:
7034         rte_free(req_list);
7035         return ret;
7036 }
7037
7038 int
7039 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7040                             struct i40e_macvlan_filter *filter,
7041                             int total)
7042 {
7043         int ele_num, ele_buff_size;
7044         int num, actual_num, i;
7045         uint16_t flags;
7046         int ret = I40E_SUCCESS;
7047         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7048         struct i40e_aqc_remove_macvlan_element_data *req_list;
7049
7050         if (filter == NULL  || total == 0)
7051                 return I40E_ERR_PARAM;
7052
7053         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7054         ele_buff_size = hw->aq.asq_buf_size;
7055
7056         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7057         if (req_list == NULL) {
7058                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7059                 return I40E_ERR_NO_MEMORY;
7060         }
7061
7062         num = 0;
7063         do {
7064                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7065                 memset(req_list, 0, ele_buff_size);
7066
7067                 for (i = 0; i < actual_num; i++) {
7068                         rte_memcpy(req_list[i].mac_addr,
7069                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7070                         req_list[i].vlan_tag =
7071                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7072
7073                         switch (filter[num + i].filter_type) {
7074                         case RTE_MAC_PERFECT_MATCH:
7075                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7076                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7077                                 break;
7078                         case RTE_MACVLAN_PERFECT_MATCH:
7079                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7080                                 break;
7081                         case RTE_MAC_HASH_MATCH:
7082                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7083                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7084                                 break;
7085                         case RTE_MACVLAN_HASH_MATCH:
7086                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7087                                 break;
7088                         default:
7089                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7090                                 ret = I40E_ERR_PARAM;
7091                                 goto DONE;
7092                         }
7093                         req_list[i].flags = rte_cpu_to_le_16(flags);
7094                 }
7095
7096                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7097                                                 actual_num, NULL);
7098                 if (ret != I40E_SUCCESS) {
7099                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7100                         goto DONE;
7101                 }
7102                 num += actual_num;
7103         } while (num < total);
7104
7105 DONE:
7106         rte_free(req_list);
7107         return ret;
7108 }
7109
7110 /* Find out specific MAC filter */
7111 static struct i40e_mac_filter *
7112 i40e_find_mac_filter(struct i40e_vsi *vsi,
7113                          struct rte_ether_addr *macaddr)
7114 {
7115         struct i40e_mac_filter *f;
7116
7117         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7118                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7119                         return f;
7120         }
7121
7122         return NULL;
7123 }
7124
7125 static bool
7126 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7127                          uint16_t vlan_id)
7128 {
7129         uint32_t vid_idx, vid_bit;
7130
7131         if (vlan_id > ETH_VLAN_ID_MAX)
7132                 return 0;
7133
7134         vid_idx = I40E_VFTA_IDX(vlan_id);
7135         vid_bit = I40E_VFTA_BIT(vlan_id);
7136
7137         if (vsi->vfta[vid_idx] & vid_bit)
7138                 return 1;
7139         else
7140                 return 0;
7141 }
7142
7143 static void
7144 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7145                        uint16_t vlan_id, bool on)
7146 {
7147         uint32_t vid_idx, vid_bit;
7148
7149         vid_idx = I40E_VFTA_IDX(vlan_id);
7150         vid_bit = I40E_VFTA_BIT(vlan_id);
7151
7152         if (on)
7153                 vsi->vfta[vid_idx] |= vid_bit;
7154         else
7155                 vsi->vfta[vid_idx] &= ~vid_bit;
7156 }
7157
7158 void
7159 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7160                      uint16_t vlan_id, bool on)
7161 {
7162         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7163         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7164         int ret;
7165
7166         if (vlan_id > ETH_VLAN_ID_MAX)
7167                 return;
7168
7169         i40e_store_vlan_filter(vsi, vlan_id, on);
7170
7171         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7172                 return;
7173
7174         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7175
7176         if (on) {
7177                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7178                                        &vlan_data, 1, NULL);
7179                 if (ret != I40E_SUCCESS)
7180                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7181         } else {
7182                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7183                                           &vlan_data, 1, NULL);
7184                 if (ret != I40E_SUCCESS)
7185                         PMD_DRV_LOG(ERR,
7186                                     "Failed to remove vlan filter");
7187         }
7188 }
7189
7190 /**
7191  * Find all vlan options for specific mac addr,
7192  * return with actual vlan found.
7193  */
7194 int
7195 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7196                            struct i40e_macvlan_filter *mv_f,
7197                            int num, struct rte_ether_addr *addr)
7198 {
7199         int i;
7200         uint32_t j, k;
7201
7202         /**
7203          * Not to use i40e_find_vlan_filter to decrease the loop time,
7204          * although the code looks complex.
7205           */
7206         if (num < vsi->vlan_num)
7207                 return I40E_ERR_PARAM;
7208
7209         i = 0;
7210         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7211                 if (vsi->vfta[j]) {
7212                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7213                                 if (vsi->vfta[j] & (1 << k)) {
7214                                         if (i > num - 1) {
7215                                                 PMD_DRV_LOG(ERR,
7216                                                         "vlan number doesn't match");
7217                                                 return I40E_ERR_PARAM;
7218                                         }
7219                                         rte_memcpy(&mv_f[i].macaddr,
7220                                                         addr, ETH_ADDR_LEN);
7221                                         mv_f[i].vlan_id =
7222                                                 j * I40E_UINT32_BIT_SIZE + k;
7223                                         i++;
7224                                 }
7225                         }
7226                 }
7227         }
7228         return I40E_SUCCESS;
7229 }
7230
7231 static inline int
7232 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7233                            struct i40e_macvlan_filter *mv_f,
7234                            int num,
7235                            uint16_t vlan)
7236 {
7237         int i = 0;
7238         struct i40e_mac_filter *f;
7239
7240         if (num < vsi->mac_num)
7241                 return I40E_ERR_PARAM;
7242
7243         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7244                 if (i > num - 1) {
7245                         PMD_DRV_LOG(ERR, "buffer number not match");
7246                         return I40E_ERR_PARAM;
7247                 }
7248                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7249                                 ETH_ADDR_LEN);
7250                 mv_f[i].vlan_id = vlan;
7251                 mv_f[i].filter_type = f->mac_info.filter_type;
7252                 i++;
7253         }
7254
7255         return I40E_SUCCESS;
7256 }
7257
7258 static int
7259 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7260 {
7261         int i, j, num;
7262         struct i40e_mac_filter *f;
7263         struct i40e_macvlan_filter *mv_f;
7264         int ret = I40E_SUCCESS;
7265
7266         if (vsi == NULL || vsi->mac_num == 0)
7267                 return I40E_ERR_PARAM;
7268
7269         /* Case that no vlan is set */
7270         if (vsi->vlan_num == 0)
7271                 num = vsi->mac_num;
7272         else
7273                 num = vsi->mac_num * vsi->vlan_num;
7274
7275         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7276         if (mv_f == NULL) {
7277                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7278                 return I40E_ERR_NO_MEMORY;
7279         }
7280
7281         i = 0;
7282         if (vsi->vlan_num == 0) {
7283                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7284                         rte_memcpy(&mv_f[i].macaddr,
7285                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7286                         mv_f[i].filter_type = f->mac_info.filter_type;
7287                         mv_f[i].vlan_id = 0;
7288                         i++;
7289                 }
7290         } else {
7291                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7292                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7293                                         vsi->vlan_num, &f->mac_info.mac_addr);
7294                         if (ret != I40E_SUCCESS)
7295                                 goto DONE;
7296                         for (j = i; j < i + vsi->vlan_num; j++)
7297                                 mv_f[j].filter_type = f->mac_info.filter_type;
7298                         i += vsi->vlan_num;
7299                 }
7300         }
7301
7302         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7303 DONE:
7304         rte_free(mv_f);
7305
7306         return ret;
7307 }
7308
7309 int
7310 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7311 {
7312         struct i40e_macvlan_filter *mv_f;
7313         int mac_num;
7314         int ret = I40E_SUCCESS;
7315
7316         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7317                 return I40E_ERR_PARAM;
7318
7319         /* If it's already set, just return */
7320         if (i40e_find_vlan_filter(vsi,vlan))
7321                 return I40E_SUCCESS;
7322
7323         mac_num = vsi->mac_num;
7324
7325         if (mac_num == 0) {
7326                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7327                 return I40E_ERR_PARAM;
7328         }
7329
7330         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7331
7332         if (mv_f == NULL) {
7333                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7334                 return I40E_ERR_NO_MEMORY;
7335         }
7336
7337         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7338
7339         if (ret != I40E_SUCCESS)
7340                 goto DONE;
7341
7342         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7343
7344         if (ret != I40E_SUCCESS)
7345                 goto DONE;
7346
7347         i40e_set_vlan_filter(vsi, vlan, 1);
7348
7349         vsi->vlan_num++;
7350         ret = I40E_SUCCESS;
7351 DONE:
7352         rte_free(mv_f);
7353         return ret;
7354 }
7355
7356 int
7357 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7358 {
7359         struct i40e_macvlan_filter *mv_f;
7360         int mac_num;
7361         int ret = I40E_SUCCESS;
7362
7363         /**
7364          * Vlan 0 is the generic filter for untagged packets
7365          * and can't be removed.
7366          */
7367         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7368                 return I40E_ERR_PARAM;
7369
7370         /* If can't find it, just return */
7371         if (!i40e_find_vlan_filter(vsi, vlan))
7372                 return I40E_ERR_PARAM;
7373
7374         mac_num = vsi->mac_num;
7375
7376         if (mac_num == 0) {
7377                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7378                 return I40E_ERR_PARAM;
7379         }
7380
7381         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7382
7383         if (mv_f == NULL) {
7384                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7385                 return I40E_ERR_NO_MEMORY;
7386         }
7387
7388         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7389
7390         if (ret != I40E_SUCCESS)
7391                 goto DONE;
7392
7393         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7394
7395         if (ret != I40E_SUCCESS)
7396                 goto DONE;
7397
7398         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7399         if (vsi->vlan_num == 1) {
7400                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7401                 if (ret != I40E_SUCCESS)
7402                         goto DONE;
7403
7404                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7405                 if (ret != I40E_SUCCESS)
7406                         goto DONE;
7407         }
7408
7409         i40e_set_vlan_filter(vsi, vlan, 0);
7410
7411         vsi->vlan_num--;
7412         ret = I40E_SUCCESS;
7413 DONE:
7414         rte_free(mv_f);
7415         return ret;
7416 }
7417
7418 int
7419 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7420 {
7421         struct i40e_mac_filter *f;
7422         struct i40e_macvlan_filter *mv_f;
7423         int i, vlan_num = 0;
7424         int ret = I40E_SUCCESS;
7425
7426         /* If it's add and we've config it, return */
7427         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7428         if (f != NULL)
7429                 return I40E_SUCCESS;
7430         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7431                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7432
7433                 /**
7434                  * If vlan_num is 0, that's the first time to add mac,
7435                  * set mask for vlan_id 0.
7436                  */
7437                 if (vsi->vlan_num == 0) {
7438                         i40e_set_vlan_filter(vsi, 0, 1);
7439                         vsi->vlan_num = 1;
7440                 }
7441                 vlan_num = vsi->vlan_num;
7442         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7443                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7444                 vlan_num = 1;
7445
7446         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7447         if (mv_f == NULL) {
7448                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7449                 return I40E_ERR_NO_MEMORY;
7450         }
7451
7452         for (i = 0; i < vlan_num; i++) {
7453                 mv_f[i].filter_type = mac_filter->filter_type;
7454                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7455                                 ETH_ADDR_LEN);
7456         }
7457
7458         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7459                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7460                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7461                                         &mac_filter->mac_addr);
7462                 if (ret != I40E_SUCCESS)
7463                         goto DONE;
7464         }
7465
7466         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7467         if (ret != I40E_SUCCESS)
7468                 goto DONE;
7469
7470         /* Add the mac addr into mac list */
7471         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7472         if (f == NULL) {
7473                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7474                 ret = I40E_ERR_NO_MEMORY;
7475                 goto DONE;
7476         }
7477         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7478                         ETH_ADDR_LEN);
7479         f->mac_info.filter_type = mac_filter->filter_type;
7480         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7481         vsi->mac_num++;
7482
7483         ret = I40E_SUCCESS;
7484 DONE:
7485         rte_free(mv_f);
7486
7487         return ret;
7488 }
7489
7490 int
7491 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7492 {
7493         struct i40e_mac_filter *f;
7494         struct i40e_macvlan_filter *mv_f;
7495         int i, vlan_num;
7496         enum rte_mac_filter_type filter_type;
7497         int ret = I40E_SUCCESS;
7498
7499         /* Can't find it, return an error */
7500         f = i40e_find_mac_filter(vsi, addr);
7501         if (f == NULL)
7502                 return I40E_ERR_PARAM;
7503
7504         vlan_num = vsi->vlan_num;
7505         filter_type = f->mac_info.filter_type;
7506         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7507                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7508                 if (vlan_num == 0) {
7509                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7510                         return I40E_ERR_PARAM;
7511                 }
7512         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7513                         filter_type == RTE_MAC_HASH_MATCH)
7514                 vlan_num = 1;
7515
7516         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7517         if (mv_f == NULL) {
7518                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7519                 return I40E_ERR_NO_MEMORY;
7520         }
7521
7522         for (i = 0; i < vlan_num; i++) {
7523                 mv_f[i].filter_type = filter_type;
7524                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7525                                 ETH_ADDR_LEN);
7526         }
7527         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7528                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7529                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7530                 if (ret != I40E_SUCCESS)
7531                         goto DONE;
7532         }
7533
7534         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7535         if (ret != I40E_SUCCESS)
7536                 goto DONE;
7537
7538         /* Remove the mac addr into mac list */
7539         TAILQ_REMOVE(&vsi->mac_list, f, next);
7540         rte_free(f);
7541         vsi->mac_num--;
7542
7543         ret = I40E_SUCCESS;
7544 DONE:
7545         rte_free(mv_f);
7546         return ret;
7547 }
7548
7549 /* Configure hash enable flags for RSS */
7550 uint64_t
7551 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7552 {
7553         uint64_t hena = 0;
7554         int i;
7555
7556         if (!flags)
7557                 return hena;
7558
7559         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7560                 if (flags & (1ULL << i))
7561                         hena |= adapter->pctypes_tbl[i];
7562         }
7563
7564         return hena;
7565 }
7566
7567 /* Parse the hash enable flags */
7568 uint64_t
7569 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7570 {
7571         uint64_t rss_hf = 0;
7572
7573         if (!flags)
7574                 return rss_hf;
7575         int i;
7576
7577         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7578                 if (flags & adapter->pctypes_tbl[i])
7579                         rss_hf |= (1ULL << i);
7580         }
7581         return rss_hf;
7582 }
7583
7584 /* Disable RSS */
7585 static void
7586 i40e_pf_disable_rss(struct i40e_pf *pf)
7587 {
7588         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7589
7590         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7591         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7592         I40E_WRITE_FLUSH(hw);
7593 }
7594
7595 int
7596 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7597 {
7598         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7600         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7601                            I40E_VFQF_HKEY_MAX_INDEX :
7602                            I40E_PFQF_HKEY_MAX_INDEX;
7603         int ret = 0;
7604
7605         if (!key || key_len == 0) {
7606                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7607                 return 0;
7608         } else if (key_len != (key_idx + 1) *
7609                 sizeof(uint32_t)) {
7610                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7611                 return -EINVAL;
7612         }
7613
7614         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7615                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7616                         (struct i40e_aqc_get_set_rss_key_data *)key;
7617
7618                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7619                 if (ret)
7620                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7621         } else {
7622                 uint32_t *hash_key = (uint32_t *)key;
7623                 uint16_t i;
7624
7625                 if (vsi->type == I40E_VSI_SRIOV) {
7626                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7627                                 I40E_WRITE_REG(
7628                                         hw,
7629                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7630                                         hash_key[i]);
7631
7632                 } else {
7633                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7634                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7635                                                hash_key[i]);
7636                 }
7637                 I40E_WRITE_FLUSH(hw);
7638         }
7639
7640         return ret;
7641 }
7642
7643 static int
7644 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7645 {
7646         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7647         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7648         uint32_t reg;
7649         int ret;
7650
7651         if (!key || !key_len)
7652                 return 0;
7653
7654         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7655                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7656                         (struct i40e_aqc_get_set_rss_key_data *)key);
7657                 if (ret) {
7658                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7659                         return ret;
7660                 }
7661         } else {
7662                 uint32_t *key_dw = (uint32_t *)key;
7663                 uint16_t i;
7664
7665                 if (vsi->type == I40E_VSI_SRIOV) {
7666                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7667                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7668                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7669                         }
7670                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7671                                    sizeof(uint32_t);
7672                 } else {
7673                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7674                                 reg = I40E_PFQF_HKEY(i);
7675                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7676                         }
7677                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7678                                    sizeof(uint32_t);
7679                 }
7680         }
7681         return 0;
7682 }
7683
7684 static int
7685 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7686 {
7687         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7688         uint64_t hena;
7689         int ret;
7690
7691         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7692                                rss_conf->rss_key_len);
7693         if (ret)
7694                 return ret;
7695
7696         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7697         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7698         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7699         I40E_WRITE_FLUSH(hw);
7700
7701         return 0;
7702 }
7703
7704 static int
7705 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7706                          struct rte_eth_rss_conf *rss_conf)
7707 {
7708         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7709         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7710         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7711         uint64_t hena;
7712
7713         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7714         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7715
7716         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7717                 if (rss_hf != 0) /* Enable RSS */
7718                         return -EINVAL;
7719                 return 0; /* Nothing to do */
7720         }
7721         /* RSS enabled */
7722         if (rss_hf == 0) /* Disable RSS */
7723                 return -EINVAL;
7724
7725         return i40e_hw_rss_hash_set(pf, rss_conf);
7726 }
7727
7728 static int
7729 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7730                            struct rte_eth_rss_conf *rss_conf)
7731 {
7732         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7734         uint64_t hena;
7735         int ret;
7736
7737         if (!rss_conf)
7738                 return -EINVAL;
7739
7740         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7741                          &rss_conf->rss_key_len);
7742         if (ret)
7743                 return ret;
7744
7745         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7746         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7747         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7748
7749         return 0;
7750 }
7751
7752 static int
7753 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7754 {
7755         switch (filter_type) {
7756         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7757                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7758                 break;
7759         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7760                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7761                 break;
7762         case RTE_TUNNEL_FILTER_IMAC_TENID:
7763                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7764                 break;
7765         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7766                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7767                 break;
7768         case ETH_TUNNEL_FILTER_IMAC:
7769                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7770                 break;
7771         case ETH_TUNNEL_FILTER_OIP:
7772                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7773                 break;
7774         case ETH_TUNNEL_FILTER_IIP:
7775                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7776                 break;
7777         default:
7778                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7779                 return -EINVAL;
7780         }
7781
7782         return 0;
7783 }
7784
7785 /* Convert tunnel filter structure */
7786 static int
7787 i40e_tunnel_filter_convert(
7788         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7789         struct i40e_tunnel_filter *tunnel_filter)
7790 {
7791         rte_ether_addr_copy((struct rte_ether_addr *)
7792                         &cld_filter->element.outer_mac,
7793                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7794         rte_ether_addr_copy((struct rte_ether_addr *)
7795                         &cld_filter->element.inner_mac,
7796                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7797         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7798         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7799              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7800             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7801                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7802         else
7803                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7804         tunnel_filter->input.flags = cld_filter->element.flags;
7805         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7806         tunnel_filter->queue = cld_filter->element.queue_number;
7807         rte_memcpy(tunnel_filter->input.general_fields,
7808                    cld_filter->general_fields,
7809                    sizeof(cld_filter->general_fields));
7810
7811         return 0;
7812 }
7813
7814 /* Check if there exists the tunnel filter */
7815 struct i40e_tunnel_filter *
7816 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7817                              const struct i40e_tunnel_filter_input *input)
7818 {
7819         int ret;
7820
7821         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7822         if (ret < 0)
7823                 return NULL;
7824
7825         return tunnel_rule->hash_map[ret];
7826 }
7827
7828 /* Add a tunnel filter into the SW list */
7829 static int
7830 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7831                              struct i40e_tunnel_filter *tunnel_filter)
7832 {
7833         struct i40e_tunnel_rule *rule = &pf->tunnel;
7834         int ret;
7835
7836         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7837         if (ret < 0) {
7838                 PMD_DRV_LOG(ERR,
7839                             "Failed to insert tunnel filter to hash table %d!",
7840                             ret);
7841                 return ret;
7842         }
7843         rule->hash_map[ret] = tunnel_filter;
7844
7845         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7846
7847         return 0;
7848 }
7849
7850 /* Delete a tunnel filter from the SW list */
7851 int
7852 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7853                           struct i40e_tunnel_filter_input *input)
7854 {
7855         struct i40e_tunnel_rule *rule = &pf->tunnel;
7856         struct i40e_tunnel_filter *tunnel_filter;
7857         int ret;
7858
7859         ret = rte_hash_del_key(rule->hash_table, input);
7860         if (ret < 0) {
7861                 PMD_DRV_LOG(ERR,
7862                             "Failed to delete tunnel filter to hash table %d!",
7863                             ret);
7864                 return ret;
7865         }
7866         tunnel_filter = rule->hash_map[ret];
7867         rule->hash_map[ret] = NULL;
7868
7869         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7870         rte_free(tunnel_filter);
7871
7872         return 0;
7873 }
7874
7875 int
7876 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7877                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7878                         uint8_t add)
7879 {
7880         uint16_t ip_type;
7881         uint32_t ipv4_addr, ipv4_addr_le;
7882         uint8_t i, tun_type = 0;
7883         /* internal varialbe to convert ipv6 byte order */
7884         uint32_t convert_ipv6[4];
7885         int val, ret = 0;
7886         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7887         struct i40e_vsi *vsi = pf->main_vsi;
7888         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7889         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7890         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7891         struct i40e_tunnel_filter *tunnel, *node;
7892         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7893
7894         cld_filter = rte_zmalloc("tunnel_filter",
7895                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7896         0);
7897
7898         if (NULL == cld_filter) {
7899                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7900                 return -ENOMEM;
7901         }
7902         pfilter = cld_filter;
7903
7904         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7905                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7906         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7907                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7908
7909         pfilter->element.inner_vlan =
7910                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7911         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7912                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7913                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7914                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7915                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7916                                 &ipv4_addr_le,
7917                                 sizeof(pfilter->element.ipaddr.v4.data));
7918         } else {
7919                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7920                 for (i = 0; i < 4; i++) {
7921                         convert_ipv6[i] =
7922                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7923                 }
7924                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7925                            &convert_ipv6,
7926                            sizeof(pfilter->element.ipaddr.v6.data));
7927         }
7928
7929         /* check tunneled type */
7930         switch (tunnel_filter->tunnel_type) {
7931         case RTE_TUNNEL_TYPE_VXLAN:
7932                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7933                 break;
7934         case RTE_TUNNEL_TYPE_NVGRE:
7935                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7936                 break;
7937         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7938                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7939                 break;
7940         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7941                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7942                 break;
7943         default:
7944                 /* Other tunnel types is not supported. */
7945                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7946                 rte_free(cld_filter);
7947                 return -EINVAL;
7948         }
7949
7950         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7951                                        &pfilter->element.flags);
7952         if (val < 0) {
7953                 rte_free(cld_filter);
7954                 return -EINVAL;
7955         }
7956
7957         pfilter->element.flags |= rte_cpu_to_le_16(
7958                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7959                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7960         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7961         pfilter->element.queue_number =
7962                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7963
7964         /* Check if there is the filter in SW list */
7965         memset(&check_filter, 0, sizeof(check_filter));
7966         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7967         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7968         if (add && node) {
7969                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7970                 rte_free(cld_filter);
7971                 return -EINVAL;
7972         }
7973
7974         if (!add && !node) {
7975                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7976                 rte_free(cld_filter);
7977                 return -EINVAL;
7978         }
7979
7980         if (add) {
7981                 ret = i40e_aq_add_cloud_filters(hw,
7982                                         vsi->seid, &cld_filter->element, 1);
7983                 if (ret < 0) {
7984                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7985                         rte_free(cld_filter);
7986                         return -ENOTSUP;
7987                 }
7988                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7989                 if (tunnel == NULL) {
7990                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7991                         rte_free(cld_filter);
7992                         return -ENOMEM;
7993                 }
7994
7995                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7996                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7997                 if (ret < 0)
7998                         rte_free(tunnel);
7999         } else {
8000                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8001                                                    &cld_filter->element, 1);
8002                 if (ret < 0) {
8003                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8004                         rte_free(cld_filter);
8005                         return -ENOTSUP;
8006                 }
8007                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8008         }
8009
8010         rte_free(cld_filter);
8011         return ret;
8012 }
8013
8014 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8015 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
8016 #define I40E_TR_GENEVE_KEY_MASK                 0x8
8017 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
8018 #define I40E_TR_GRE_KEY_MASK                    0x400
8019 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
8020 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
8021
8022 static enum
8023 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8024 {
8025         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8026         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8027         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8028         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8029         enum i40e_status_code status = I40E_SUCCESS;
8030
8031         if (pf->support_multi_driver) {
8032                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8033                 return I40E_NOT_SUPPORTED;
8034         }
8035
8036         memset(&filter_replace, 0,
8037                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8038         memset(&filter_replace_buf, 0,
8039                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8040
8041         /* create L1 filter */
8042         filter_replace.old_filter_type =
8043                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8044         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8045         filter_replace.tr_bit = 0;
8046
8047         /* Prepare the buffer, 3 entries */
8048         filter_replace_buf.data[0] =
8049                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8050         filter_replace_buf.data[0] |=
8051                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8052         filter_replace_buf.data[2] = 0xFF;
8053         filter_replace_buf.data[3] = 0xFF;
8054         filter_replace_buf.data[4] =
8055                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8056         filter_replace_buf.data[4] |=
8057                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8058         filter_replace_buf.data[7] = 0xF0;
8059         filter_replace_buf.data[8]
8060                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8061         filter_replace_buf.data[8] |=
8062                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8063         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8064                 I40E_TR_GENEVE_KEY_MASK |
8065                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8066         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8067                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8068                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8069
8070         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8071                                                &filter_replace_buf);
8072         if (!status && (filter_replace.old_filter_type !=
8073                         filter_replace.new_filter_type))
8074                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8075                             " original: 0x%x, new: 0x%x",
8076                             dev->device->name,
8077                             filter_replace.old_filter_type,
8078                             filter_replace.new_filter_type);
8079
8080         return status;
8081 }
8082
8083 static enum
8084 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8085 {
8086         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8087         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8088         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8089         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8090         enum i40e_status_code status = I40E_SUCCESS;
8091
8092         if (pf->support_multi_driver) {
8093                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8094                 return I40E_NOT_SUPPORTED;
8095         }
8096
8097         /* For MPLSoUDP */
8098         memset(&filter_replace, 0,
8099                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8100         memset(&filter_replace_buf, 0,
8101                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8102         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8103                 I40E_AQC_MIRROR_CLOUD_FILTER;
8104         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8105         filter_replace.new_filter_type =
8106                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8107         /* Prepare the buffer, 2 entries */
8108         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8109         filter_replace_buf.data[0] |=
8110                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8111         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8112         filter_replace_buf.data[4] |=
8113                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8114         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8115                                                &filter_replace_buf);
8116         if (status < 0)
8117                 return status;
8118         if (filter_replace.old_filter_type !=
8119             filter_replace.new_filter_type)
8120                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8121                             " original: 0x%x, new: 0x%x",
8122                             dev->device->name,
8123                             filter_replace.old_filter_type,
8124                             filter_replace.new_filter_type);
8125
8126         /* For MPLSoGRE */
8127         memset(&filter_replace, 0,
8128                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8129         memset(&filter_replace_buf, 0,
8130                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8131
8132         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8133                 I40E_AQC_MIRROR_CLOUD_FILTER;
8134         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8135         filter_replace.new_filter_type =
8136                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8137         /* Prepare the buffer, 2 entries */
8138         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8139         filter_replace_buf.data[0] |=
8140                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8141         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8142         filter_replace_buf.data[4] |=
8143                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8144
8145         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8146                                                &filter_replace_buf);
8147         if (!status && (filter_replace.old_filter_type !=
8148                         filter_replace.new_filter_type))
8149                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8150                             " original: 0x%x, new: 0x%x",
8151                             dev->device->name,
8152                             filter_replace.old_filter_type,
8153                             filter_replace.new_filter_type);
8154
8155         return status;
8156 }
8157
8158 static enum i40e_status_code
8159 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8160 {
8161         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8162         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8163         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8164         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8165         enum i40e_status_code status = I40E_SUCCESS;
8166
8167         if (pf->support_multi_driver) {
8168                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8169                 return I40E_NOT_SUPPORTED;
8170         }
8171
8172         /* For GTP-C */
8173         memset(&filter_replace, 0,
8174                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8175         memset(&filter_replace_buf, 0,
8176                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8177         /* create L1 filter */
8178         filter_replace.old_filter_type =
8179                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8180         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8181         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8182                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8183         /* Prepare the buffer, 2 entries */
8184         filter_replace_buf.data[0] =
8185                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8186         filter_replace_buf.data[0] |=
8187                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8188         filter_replace_buf.data[2] = 0xFF;
8189         filter_replace_buf.data[3] = 0xFF;
8190         filter_replace_buf.data[4] =
8191                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8192         filter_replace_buf.data[4] |=
8193                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8194         filter_replace_buf.data[6] = 0xFF;
8195         filter_replace_buf.data[7] = 0xFF;
8196         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8197                                                &filter_replace_buf);
8198         if (status < 0)
8199                 return status;
8200         if (filter_replace.old_filter_type !=
8201             filter_replace.new_filter_type)
8202                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8203                             " original: 0x%x, new: 0x%x",
8204                             dev->device->name,
8205                             filter_replace.old_filter_type,
8206                             filter_replace.new_filter_type);
8207
8208         /* for GTP-U */
8209         memset(&filter_replace, 0,
8210                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8211         memset(&filter_replace_buf, 0,
8212                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8213         /* create L1 filter */
8214         filter_replace.old_filter_type =
8215                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8216         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8217         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8218                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8219         /* Prepare the buffer, 2 entries */
8220         filter_replace_buf.data[0] =
8221                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8222         filter_replace_buf.data[0] |=
8223                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8224         filter_replace_buf.data[2] = 0xFF;
8225         filter_replace_buf.data[3] = 0xFF;
8226         filter_replace_buf.data[4] =
8227                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8228         filter_replace_buf.data[4] |=
8229                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8230         filter_replace_buf.data[6] = 0xFF;
8231         filter_replace_buf.data[7] = 0xFF;
8232
8233         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8234                                                &filter_replace_buf);
8235         if (!status && (filter_replace.old_filter_type !=
8236                         filter_replace.new_filter_type))
8237                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8238                             " original: 0x%x, new: 0x%x",
8239                             dev->device->name,
8240                             filter_replace.old_filter_type,
8241                             filter_replace.new_filter_type);
8242
8243         return status;
8244 }
8245
8246 static enum
8247 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8248 {
8249         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8250         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8251         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8252         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8253         enum i40e_status_code status = I40E_SUCCESS;
8254
8255         if (pf->support_multi_driver) {
8256                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8257                 return I40E_NOT_SUPPORTED;
8258         }
8259
8260         /* for GTP-C */
8261         memset(&filter_replace, 0,
8262                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8263         memset(&filter_replace_buf, 0,
8264                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8265         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8266         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8267         filter_replace.new_filter_type =
8268                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8269         /* Prepare the buffer, 2 entries */
8270         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8271         filter_replace_buf.data[0] |=
8272                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8273         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8274         filter_replace_buf.data[4] |=
8275                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8276         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8277                                                &filter_replace_buf);
8278         if (status < 0)
8279                 return status;
8280         if (filter_replace.old_filter_type !=
8281             filter_replace.new_filter_type)
8282                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8283                             " original: 0x%x, new: 0x%x",
8284                             dev->device->name,
8285                             filter_replace.old_filter_type,
8286                             filter_replace.new_filter_type);
8287
8288         /* for GTP-U */
8289         memset(&filter_replace, 0,
8290                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8291         memset(&filter_replace_buf, 0,
8292                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8293         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8294         filter_replace.old_filter_type =
8295                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8296         filter_replace.new_filter_type =
8297                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8298         /* Prepare the buffer, 2 entries */
8299         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8300         filter_replace_buf.data[0] |=
8301                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8302         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8303         filter_replace_buf.data[4] |=
8304                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8305
8306         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8307                                                &filter_replace_buf);
8308         if (!status && (filter_replace.old_filter_type !=
8309                         filter_replace.new_filter_type))
8310                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8311                             " original: 0x%x, new: 0x%x",
8312                             dev->device->name,
8313                             filter_replace.old_filter_type,
8314                             filter_replace.new_filter_type);
8315
8316         return status;
8317 }
8318
8319 int
8320 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8321                       struct i40e_tunnel_filter_conf *tunnel_filter,
8322                       uint8_t add)
8323 {
8324         uint16_t ip_type;
8325         uint32_t ipv4_addr, ipv4_addr_le;
8326         uint8_t i, tun_type = 0;
8327         /* internal variable to convert ipv6 byte order */
8328         uint32_t convert_ipv6[4];
8329         int val, ret = 0;
8330         struct i40e_pf_vf *vf = NULL;
8331         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8332         struct i40e_vsi *vsi;
8333         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8334         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8335         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8336         struct i40e_tunnel_filter *tunnel, *node;
8337         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8338         uint32_t teid_le;
8339         bool big_buffer = 0;
8340
8341         cld_filter = rte_zmalloc("tunnel_filter",
8342                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8343                          0);
8344
8345         if (cld_filter == NULL) {
8346                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8347                 return -ENOMEM;
8348         }
8349         pfilter = cld_filter;
8350
8351         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8352                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8353         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8354                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8355
8356         pfilter->element.inner_vlan =
8357                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8358         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8359                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8360                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8361                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8362                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8363                                 &ipv4_addr_le,
8364                                 sizeof(pfilter->element.ipaddr.v4.data));
8365         } else {
8366                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8367                 for (i = 0; i < 4; i++) {
8368                         convert_ipv6[i] =
8369                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8370                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8371                 }
8372                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8373                            &convert_ipv6,
8374                            sizeof(pfilter->element.ipaddr.v6.data));
8375         }
8376
8377         /* check tunneled type */
8378         switch (tunnel_filter->tunnel_type) {
8379         case I40E_TUNNEL_TYPE_VXLAN:
8380                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8381                 break;
8382         case I40E_TUNNEL_TYPE_NVGRE:
8383                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8384                 break;
8385         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8386                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8387                 break;
8388         case I40E_TUNNEL_TYPE_MPLSoUDP:
8389                 if (!pf->mpls_replace_flag) {
8390                         i40e_replace_mpls_l1_filter(pf);
8391                         i40e_replace_mpls_cloud_filter(pf);
8392                         pf->mpls_replace_flag = 1;
8393                 }
8394                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8395                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8396                         teid_le >> 4;
8397                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8398                         (teid_le & 0xF) << 12;
8399                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8400                         0x40;
8401                 big_buffer = 1;
8402                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8403                 break;
8404         case I40E_TUNNEL_TYPE_MPLSoGRE:
8405                 if (!pf->mpls_replace_flag) {
8406                         i40e_replace_mpls_l1_filter(pf);
8407                         i40e_replace_mpls_cloud_filter(pf);
8408                         pf->mpls_replace_flag = 1;
8409                 }
8410                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8411                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8412                         teid_le >> 4;
8413                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8414                         (teid_le & 0xF) << 12;
8415                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8416                         0x0;
8417                 big_buffer = 1;
8418                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8419                 break;
8420         case I40E_TUNNEL_TYPE_GTPC:
8421                 if (!pf->gtp_replace_flag) {
8422                         i40e_replace_gtp_l1_filter(pf);
8423                         i40e_replace_gtp_cloud_filter(pf);
8424                         pf->gtp_replace_flag = 1;
8425                 }
8426                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8427                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8428                         (teid_le >> 16) & 0xFFFF;
8429                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8430                         teid_le & 0xFFFF;
8431                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8432                         0x0;
8433                 big_buffer = 1;
8434                 break;
8435         case I40E_TUNNEL_TYPE_GTPU:
8436                 if (!pf->gtp_replace_flag) {
8437                         i40e_replace_gtp_l1_filter(pf);
8438                         i40e_replace_gtp_cloud_filter(pf);
8439                         pf->gtp_replace_flag = 1;
8440                 }
8441                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8442                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8443                         (teid_le >> 16) & 0xFFFF;
8444                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8445                         teid_le & 0xFFFF;
8446                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8447                         0x0;
8448                 big_buffer = 1;
8449                 break;
8450         case I40E_TUNNEL_TYPE_QINQ:
8451                 if (!pf->qinq_replace_flag) {
8452                         ret = i40e_cloud_filter_qinq_create(pf);
8453                         if (ret < 0)
8454                                 PMD_DRV_LOG(DEBUG,
8455                                             "QinQ tunnel filter already created.");
8456                         pf->qinq_replace_flag = 1;
8457                 }
8458                 /*      Add in the General fields the values of
8459                  *      the Outer and Inner VLAN
8460                  *      Big Buffer should be set, see changes in
8461                  *      i40e_aq_add_cloud_filters
8462                  */
8463                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8464                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8465                 big_buffer = 1;
8466                 break;
8467         default:
8468                 /* Other tunnel types is not supported. */
8469                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8470                 rte_free(cld_filter);
8471                 return -EINVAL;
8472         }
8473
8474         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8475                 pfilter->element.flags =
8476                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8477         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8478                 pfilter->element.flags =
8479                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8480         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8481                 pfilter->element.flags =
8482                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8483         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8484                 pfilter->element.flags =
8485                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8486         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8487                 pfilter->element.flags |=
8488                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8489         else {
8490                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8491                                                 &pfilter->element.flags);
8492                 if (val < 0) {
8493                         rte_free(cld_filter);
8494                         return -EINVAL;
8495                 }
8496         }
8497
8498         pfilter->element.flags |= rte_cpu_to_le_16(
8499                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8500                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8501         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8502         pfilter->element.queue_number =
8503                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8504
8505         if (!tunnel_filter->is_to_vf)
8506                 vsi = pf->main_vsi;
8507         else {
8508                 if (tunnel_filter->vf_id >= pf->vf_num) {
8509                         PMD_DRV_LOG(ERR, "Invalid argument.");
8510                         rte_free(cld_filter);
8511                         return -EINVAL;
8512                 }
8513                 vf = &pf->vfs[tunnel_filter->vf_id];
8514                 vsi = vf->vsi;
8515         }
8516
8517         /* Check if there is the filter in SW list */
8518         memset(&check_filter, 0, sizeof(check_filter));
8519         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8520         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8521         check_filter.vf_id = tunnel_filter->vf_id;
8522         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8523         if (add && node) {
8524                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8525                 rte_free(cld_filter);
8526                 return -EINVAL;
8527         }
8528
8529         if (!add && !node) {
8530                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8531                 rte_free(cld_filter);
8532                 return -EINVAL;
8533         }
8534
8535         if (add) {
8536                 if (big_buffer)
8537                         ret = i40e_aq_add_cloud_filters_bb(hw,
8538                                                    vsi->seid, cld_filter, 1);
8539                 else
8540                         ret = i40e_aq_add_cloud_filters(hw,
8541                                         vsi->seid, &cld_filter->element, 1);
8542                 if (ret < 0) {
8543                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8544                         rte_free(cld_filter);
8545                         return -ENOTSUP;
8546                 }
8547                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8548                 if (tunnel == NULL) {
8549                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8550                         rte_free(cld_filter);
8551                         return -ENOMEM;
8552                 }
8553
8554                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8555                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8556                 if (ret < 0)
8557                         rte_free(tunnel);
8558         } else {
8559                 if (big_buffer)
8560                         ret = i40e_aq_rem_cloud_filters_bb(
8561                                 hw, vsi->seid, cld_filter, 1);
8562                 else
8563                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8564                                                 &cld_filter->element, 1);
8565                 if (ret < 0) {
8566                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8567                         rte_free(cld_filter);
8568                         return -ENOTSUP;
8569                 }
8570                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8571         }
8572
8573         rte_free(cld_filter);
8574         return ret;
8575 }
8576
8577 static int
8578 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8579 {
8580         uint8_t i;
8581
8582         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8583                 if (pf->vxlan_ports[i] == port)
8584                         return i;
8585         }
8586
8587         return -1;
8588 }
8589
8590 static int
8591 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8592 {
8593         int  idx, ret;
8594         uint8_t filter_idx = 0;
8595         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8596
8597         idx = i40e_get_vxlan_port_idx(pf, port);
8598
8599         /* Check if port already exists */
8600         if (idx >= 0) {
8601                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8602                 return -EINVAL;
8603         }
8604
8605         /* Now check if there is space to add the new port */
8606         idx = i40e_get_vxlan_port_idx(pf, 0);
8607         if (idx < 0) {
8608                 PMD_DRV_LOG(ERR,
8609                         "Maximum number of UDP ports reached, not adding port %d",
8610                         port);
8611                 return -ENOSPC;
8612         }
8613
8614         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8615                                         &filter_idx, NULL);
8616         if (ret < 0) {
8617                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8618                 return -1;
8619         }
8620
8621         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8622                          port,  filter_idx);
8623
8624         /* New port: add it and mark its index in the bitmap */
8625         pf->vxlan_ports[idx] = port;
8626         pf->vxlan_bitmap |= (1 << idx);
8627
8628         if (!(pf->flags & I40E_FLAG_VXLAN))
8629                 pf->flags |= I40E_FLAG_VXLAN;
8630
8631         return 0;
8632 }
8633
8634 static int
8635 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8636 {
8637         int idx;
8638         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8639
8640         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8641                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8642                 return -EINVAL;
8643         }
8644
8645         idx = i40e_get_vxlan_port_idx(pf, port);
8646
8647         if (idx < 0) {
8648                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8649                 return -EINVAL;
8650         }
8651
8652         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8653                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8654                 return -1;
8655         }
8656
8657         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8658                         port, idx);
8659
8660         pf->vxlan_ports[idx] = 0;
8661         pf->vxlan_bitmap &= ~(1 << idx);
8662
8663         if (!pf->vxlan_bitmap)
8664                 pf->flags &= ~I40E_FLAG_VXLAN;
8665
8666         return 0;
8667 }
8668
8669 /* Add UDP tunneling port */
8670 static int
8671 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8672                              struct rte_eth_udp_tunnel *udp_tunnel)
8673 {
8674         int ret = 0;
8675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8676
8677         if (udp_tunnel == NULL)
8678                 return -EINVAL;
8679
8680         switch (udp_tunnel->prot_type) {
8681         case RTE_TUNNEL_TYPE_VXLAN:
8682                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8683                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8684                 break;
8685         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8686                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8687                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8688                 break;
8689         case RTE_TUNNEL_TYPE_GENEVE:
8690         case RTE_TUNNEL_TYPE_TEREDO:
8691                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8692                 ret = -1;
8693                 break;
8694
8695         default:
8696                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8697                 ret = -1;
8698                 break;
8699         }
8700
8701         return ret;
8702 }
8703
8704 /* Remove UDP tunneling port */
8705 static int
8706 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8707                              struct rte_eth_udp_tunnel *udp_tunnel)
8708 {
8709         int ret = 0;
8710         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8711
8712         if (udp_tunnel == NULL)
8713                 return -EINVAL;
8714
8715         switch (udp_tunnel->prot_type) {
8716         case RTE_TUNNEL_TYPE_VXLAN:
8717         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8718                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8719                 break;
8720         case RTE_TUNNEL_TYPE_GENEVE:
8721         case RTE_TUNNEL_TYPE_TEREDO:
8722                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8723                 ret = -1;
8724                 break;
8725         default:
8726                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8727                 ret = -1;
8728                 break;
8729         }
8730
8731         return ret;
8732 }
8733
8734 /* Calculate the maximum number of contiguous PF queues that are configured */
8735 static int
8736 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8737 {
8738         struct rte_eth_dev_data *data = pf->dev_data;
8739         int i, num;
8740         struct i40e_rx_queue *rxq;
8741
8742         num = 0;
8743         for (i = 0; i < pf->lan_nb_qps; i++) {
8744                 rxq = data->rx_queues[i];
8745                 if (rxq && rxq->q_set)
8746                         num++;
8747                 else
8748                         break;
8749         }
8750
8751         return num;
8752 }
8753
8754 /* Configure RSS */
8755 static int
8756 i40e_pf_config_rss(struct i40e_pf *pf)
8757 {
8758         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8759         struct rte_eth_rss_conf rss_conf;
8760         uint32_t i, lut = 0;
8761         uint16_t j, num;
8762
8763         /*
8764          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8765          * It's necessary to calculate the actual PF queues that are configured.
8766          */
8767         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8768                 num = i40e_pf_calc_configured_queues_num(pf);
8769         else
8770                 num = pf->dev_data->nb_rx_queues;
8771
8772         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8773         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8774                         num);
8775
8776         if (num == 0) {
8777                 PMD_INIT_LOG(ERR,
8778                         "No PF queues are configured to enable RSS for port %u",
8779                         pf->dev_data->port_id);
8780                 return -ENOTSUP;
8781         }
8782
8783         if (pf->adapter->rss_reta_updated == 0) {
8784                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8785                         if (j == num)
8786                                 j = 0;
8787                         lut = (lut << 8) | (j & ((0x1 <<
8788                                 hw->func_caps.rss_table_entry_width) - 1));
8789                         if ((i & 3) == 3)
8790                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8791                                                rte_bswap32(lut));
8792                 }
8793         }
8794
8795         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8796         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8797                 i40e_pf_disable_rss(pf);
8798                 return 0;
8799         }
8800         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8801                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8802                 /* Random default keys */
8803                 static uint32_t rss_key_default[] = {0x6b793944,
8804                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8805                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8806                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8807
8808                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8809                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8810                                                         sizeof(uint32_t);
8811         }
8812
8813         return i40e_hw_rss_hash_set(pf, &rss_conf);
8814 }
8815
8816 static int
8817 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8818                                struct rte_eth_tunnel_filter_conf *filter)
8819 {
8820         if (pf == NULL || filter == NULL) {
8821                 PMD_DRV_LOG(ERR, "Invalid parameter");
8822                 return -EINVAL;
8823         }
8824
8825         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8826                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8827                 return -EINVAL;
8828         }
8829
8830         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8831                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8832                 return -EINVAL;
8833         }
8834
8835         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8836                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8837                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8838                 return -EINVAL;
8839         }
8840
8841         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8842                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8843                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8844                 return -EINVAL;
8845         }
8846
8847         return 0;
8848 }
8849
8850 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8851 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8852 static int
8853 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8854 {
8855         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8856         uint32_t val, reg;
8857         int ret = -EINVAL;
8858
8859         if (pf->support_multi_driver) {
8860                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8861                 return -ENOTSUP;
8862         }
8863
8864         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8865         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8866
8867         if (len == 3) {
8868                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8869         } else if (len == 4) {
8870                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8871         } else {
8872                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8873                 return ret;
8874         }
8875
8876         if (reg != val) {
8877                 ret = i40e_aq_debug_write_global_register(hw,
8878                                                    I40E_GL_PRS_FVBM(2),
8879                                                    reg, NULL);
8880                 if (ret != 0)
8881                         return ret;
8882                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8883                             "with value 0x%08x",
8884                             I40E_GL_PRS_FVBM(2), reg);
8885         } else {
8886                 ret = 0;
8887         }
8888         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8889                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8890
8891         return ret;
8892 }
8893
8894 static int
8895 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8896 {
8897         int ret = -EINVAL;
8898
8899         if (!hw || !cfg)
8900                 return -EINVAL;
8901
8902         switch (cfg->cfg_type) {
8903         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8904                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8905                 break;
8906         default:
8907                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8908                 break;
8909         }
8910
8911         return ret;
8912 }
8913
8914 static int
8915 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8916                                enum rte_filter_op filter_op,
8917                                void *arg)
8918 {
8919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8920         int ret = I40E_ERR_PARAM;
8921
8922         switch (filter_op) {
8923         case RTE_ETH_FILTER_SET:
8924                 ret = i40e_dev_global_config_set(hw,
8925                         (struct rte_eth_global_cfg *)arg);
8926                 break;
8927         default:
8928                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8929                 break;
8930         }
8931
8932         return ret;
8933 }
8934
8935 static int
8936 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8937                           enum rte_filter_op filter_op,
8938                           void *arg)
8939 {
8940         struct rte_eth_tunnel_filter_conf *filter;
8941         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8942         int ret = I40E_SUCCESS;
8943
8944         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8945
8946         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8947                 return I40E_ERR_PARAM;
8948
8949         switch (filter_op) {
8950         case RTE_ETH_FILTER_NOP:
8951                 if (!(pf->flags & I40E_FLAG_VXLAN))
8952                         ret = I40E_NOT_SUPPORTED;
8953                 break;
8954         case RTE_ETH_FILTER_ADD:
8955                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8956                 break;
8957         case RTE_ETH_FILTER_DELETE:
8958                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8959                 break;
8960         default:
8961                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8962                 ret = I40E_ERR_PARAM;
8963                 break;
8964         }
8965
8966         return ret;
8967 }
8968
8969 static int
8970 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8971 {
8972         int ret = 0;
8973         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8974
8975         /* RSS setup */
8976         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8977                 ret = i40e_pf_config_rss(pf);
8978         else
8979                 i40e_pf_disable_rss(pf);
8980
8981         return ret;
8982 }
8983
8984 /* Get the symmetric hash enable configurations per port */
8985 static void
8986 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8987 {
8988         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8989
8990         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8991 }
8992
8993 /* Set the symmetric hash enable configurations per port */
8994 static void
8995 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8996 {
8997         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8998
8999         if (enable > 0) {
9000                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9001                         PMD_DRV_LOG(INFO,
9002                                 "Symmetric hash has already been enabled");
9003                         return;
9004                 }
9005                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9006         } else {
9007                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9008                         PMD_DRV_LOG(INFO,
9009                                 "Symmetric hash has already been disabled");
9010                         return;
9011                 }
9012                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9013         }
9014         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9015         I40E_WRITE_FLUSH(hw);
9016 }
9017
9018 /*
9019  * Get global configurations of hash function type and symmetric hash enable
9020  * per flow type (pctype). Note that global configuration means it affects all
9021  * the ports on the same NIC.
9022  */
9023 static int
9024 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9025                                    struct rte_eth_hash_global_conf *g_cfg)
9026 {
9027         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9028         uint32_t reg;
9029         uint16_t i, j;
9030
9031         memset(g_cfg, 0, sizeof(*g_cfg));
9032         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9033         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9034                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9035         else
9036                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9037         PMD_DRV_LOG(DEBUG, "Hash function is %s",
9038                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9039
9040         /*
9041          * As i40e supports less than 64 flow types, only first 64 bits need to
9042          * be checked.
9043          */
9044         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9045                 g_cfg->valid_bit_mask[i] = 0ULL;
9046                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9047         }
9048
9049         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9050
9051         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9052                 if (!adapter->pctypes_tbl[i])
9053                         continue;
9054                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9055                      j < I40E_FILTER_PCTYPE_MAX; j++) {
9056                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9057                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9058                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9059                                         g_cfg->sym_hash_enable_mask[0] |=
9060                                                                 (1ULL << i);
9061                                 }
9062                         }
9063                 }
9064         }
9065
9066         return 0;
9067 }
9068
9069 static int
9070 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9071                               const struct rte_eth_hash_global_conf *g_cfg)
9072 {
9073         uint32_t i;
9074         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9075
9076         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9077                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9078                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9079                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9080                                                 g_cfg->hash_func);
9081                 return -EINVAL;
9082         }
9083
9084         /*
9085          * As i40e supports less than 64 flow types, only first 64 bits need to
9086          * be checked.
9087          */
9088         mask0 = g_cfg->valid_bit_mask[0];
9089         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9090                 if (i == 0) {
9091                         /* Check if any unsupported flow type configured */
9092                         if ((mask0 | i40e_mask) ^ i40e_mask)
9093                                 goto mask_err;
9094                 } else {
9095                         if (g_cfg->valid_bit_mask[i])
9096                                 goto mask_err;
9097                 }
9098         }
9099
9100         return 0;
9101
9102 mask_err:
9103         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9104
9105         return -EINVAL;
9106 }
9107
9108 /*
9109  * Set global configurations of hash function type and symmetric hash enable
9110  * per flow type (pctype). Note any modifying global configuration will affect
9111  * all the ports on the same NIC.
9112  */
9113 static int
9114 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9115                                    struct rte_eth_hash_global_conf *g_cfg)
9116 {
9117         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9118         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9119         int ret;
9120         uint16_t i, j;
9121         uint32_t reg;
9122         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9123
9124         if (pf->support_multi_driver) {
9125                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9126                 return -ENOTSUP;
9127         }
9128
9129         /* Check the input parameters */
9130         ret = i40e_hash_global_config_check(adapter, g_cfg);
9131         if (ret < 0)
9132                 return ret;
9133
9134         /*
9135          * As i40e supports less than 64 flow types, only first 64 bits need to
9136          * be configured.
9137          */
9138         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9139                 if (mask0 & (1UL << i)) {
9140                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9141                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9142
9143                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9144                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9145                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9146                                         i40e_write_global_rx_ctl(hw,
9147                                                           I40E_GLQF_HSYM(j),
9148                                                           reg);
9149                         }
9150                 }
9151         }
9152
9153         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9154         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9155                 /* Toeplitz */
9156                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9157                         PMD_DRV_LOG(DEBUG,
9158                                 "Hash function already set to Toeplitz");
9159                         goto out;
9160                 }
9161                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9162         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9163                 /* Simple XOR */
9164                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9165                         PMD_DRV_LOG(DEBUG,
9166                                 "Hash function already set to Simple XOR");
9167                         goto out;
9168                 }
9169                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9170         } else
9171                 /* Use the default, and keep it as it is */
9172                 goto out;
9173
9174         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9175
9176 out:
9177         I40E_WRITE_FLUSH(hw);
9178
9179         return 0;
9180 }
9181
9182 /**
9183  * Valid input sets for hash and flow director filters per PCTYPE
9184  */
9185 static uint64_t
9186 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9187                 enum rte_filter_type filter)
9188 {
9189         uint64_t valid;
9190
9191         static const uint64_t valid_hash_inset_table[] = {
9192                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9193                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9194                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9195                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9196                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9197                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9198                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9199                         I40E_INSET_FLEX_PAYLOAD,
9200                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9201                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9202                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9203                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9204                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9205                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9206                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9207                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9208                         I40E_INSET_FLEX_PAYLOAD,
9209                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9210                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9211                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9212                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9213                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9214                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9215                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9216                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9217                         I40E_INSET_FLEX_PAYLOAD,
9218                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9219                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9220                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9221                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9222                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9223                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9224                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9225                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9226                         I40E_INSET_FLEX_PAYLOAD,
9227                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9228                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9229                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9230                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9231                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9232                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9233                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9234                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9235                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9236                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9237                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9238                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9239                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9240                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9241                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9242                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9243                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9244                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9245                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9246                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9247                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9248                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9249                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9250                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9251                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9252                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9253                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9254                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9255                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9256                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9257                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9258                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9259                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9260                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9261                         I40E_INSET_FLEX_PAYLOAD,
9262                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9263                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9264                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9265                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9266                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9267                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9268                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9269                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9270                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9271                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9272                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9273                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9274                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9275                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9276                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9277                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9278                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9279                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9280                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9281                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9282                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9283                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9284                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9285                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9286                         I40E_INSET_FLEX_PAYLOAD,
9287                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9288                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9289                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9290                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9291                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9292                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9293                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9294                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9295                         I40E_INSET_FLEX_PAYLOAD,
9296                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9297                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9298                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9299                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9300                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9301                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9302                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9303                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9304                         I40E_INSET_FLEX_PAYLOAD,
9305                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9306                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9307                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9308                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9309                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9310                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9311                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9312                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9313                         I40E_INSET_FLEX_PAYLOAD,
9314                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9315                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9316                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9317                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9318                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9319                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9320                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9321                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9322                         I40E_INSET_FLEX_PAYLOAD,
9323                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9324                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9325                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9326                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9327                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9328                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9329                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9330                         I40E_INSET_FLEX_PAYLOAD,
9331                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9332                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9333                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9334                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9335                         I40E_INSET_FLEX_PAYLOAD,
9336         };
9337
9338         /**
9339          * Flow director supports only fields defined in
9340          * union rte_eth_fdir_flow.
9341          */
9342         static const uint64_t valid_fdir_inset_table[] = {
9343                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9344                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9345                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9346                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9347                 I40E_INSET_IPV4_TTL,
9348                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9349                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9350                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9351                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9352                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9353                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9354                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9355                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9356                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9357                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9358                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9359                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9360                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9361                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9362                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9363                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9364                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9365                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9366                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9367                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9368                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9369                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9370                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9371                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9372                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9373                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9374                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9375                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9376                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9377                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9378                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9379                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9380                 I40E_INSET_SCTP_VT,
9381                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9382                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9383                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9384                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9385                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9386                 I40E_INSET_IPV4_TTL,
9387                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9388                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9389                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9390                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9391                 I40E_INSET_IPV6_HOP_LIMIT,
9392                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9393                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9394                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9395                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9396                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9397                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9398                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9399                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9400                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9401                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9402                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9403                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9404                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9405                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9406                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9407                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9408                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9409                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9410                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9411                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9412                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9413                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9414                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9415                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9416                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9417                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9418                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9419                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9420                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9421                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9422                 I40E_INSET_SCTP_VT,
9423                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9424                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9425                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9426                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9427                 I40E_INSET_IPV6_HOP_LIMIT,
9428                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9429                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9430                 I40E_INSET_LAST_ETHER_TYPE,
9431         };
9432
9433         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9434                 return 0;
9435         if (filter == RTE_ETH_FILTER_HASH)
9436                 valid = valid_hash_inset_table[pctype];
9437         else
9438                 valid = valid_fdir_inset_table[pctype];
9439
9440         return valid;
9441 }
9442
9443 /**
9444  * Validate if the input set is allowed for a specific PCTYPE
9445  */
9446 int
9447 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9448                 enum rte_filter_type filter, uint64_t inset)
9449 {
9450         uint64_t valid;
9451
9452         valid = i40e_get_valid_input_set(pctype, filter);
9453         if (inset & (~valid))
9454                 return -EINVAL;
9455
9456         return 0;
9457 }
9458
9459 /* default input set fields combination per pctype */
9460 uint64_t
9461 i40e_get_default_input_set(uint16_t pctype)
9462 {
9463         static const uint64_t default_inset_table[] = {
9464                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9465                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9466                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9467                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9468                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9469                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9470                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9471                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9472                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9473                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9474                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9475                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9476                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9477                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9478                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9479                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9480                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9481                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9482                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9483                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9484                         I40E_INSET_SCTP_VT,
9485                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9486                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9487                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9488                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9489                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9490                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9491                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9492                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9493                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9494                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9495                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9496                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9497                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9498                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9499                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9500                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9501                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9502                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9503                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9504                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9505                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9506                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9507                         I40E_INSET_SCTP_VT,
9508                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9509                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9510                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9511                         I40E_INSET_LAST_ETHER_TYPE,
9512         };
9513
9514         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9515                 return 0;
9516
9517         return default_inset_table[pctype];
9518 }
9519
9520 /**
9521  * Parse the input set from index to logical bit masks
9522  */
9523 static int
9524 i40e_parse_input_set(uint64_t *inset,
9525                      enum i40e_filter_pctype pctype,
9526                      enum rte_eth_input_set_field *field,
9527                      uint16_t size)
9528 {
9529         uint16_t i, j;
9530         int ret = -EINVAL;
9531
9532         static const struct {
9533                 enum rte_eth_input_set_field field;
9534                 uint64_t inset;
9535         } inset_convert_table[] = {
9536                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9537                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9538                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9539                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9540                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9541                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9542                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9543                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9544                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9545                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9546                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9547                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9548                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9549                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9550                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9551                         I40E_INSET_IPV6_NEXT_HDR},
9552                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9553                         I40E_INSET_IPV6_HOP_LIMIT},
9554                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9555                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9556                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9557                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9558                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9559                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9560                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9561                         I40E_INSET_SCTP_VT},
9562                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9563                         I40E_INSET_TUNNEL_DMAC},
9564                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9565                         I40E_INSET_VLAN_TUNNEL},
9566                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9567                         I40E_INSET_TUNNEL_ID},
9568                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9569                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9570                         I40E_INSET_FLEX_PAYLOAD_W1},
9571                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9572                         I40E_INSET_FLEX_PAYLOAD_W2},
9573                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9574                         I40E_INSET_FLEX_PAYLOAD_W3},
9575                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9576                         I40E_INSET_FLEX_PAYLOAD_W4},
9577                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9578                         I40E_INSET_FLEX_PAYLOAD_W5},
9579                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9580                         I40E_INSET_FLEX_PAYLOAD_W6},
9581                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9582                         I40E_INSET_FLEX_PAYLOAD_W7},
9583                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9584                         I40E_INSET_FLEX_PAYLOAD_W8},
9585         };
9586
9587         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9588                 return ret;
9589
9590         /* Only one item allowed for default or all */
9591         if (size == 1) {
9592                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9593                         *inset = i40e_get_default_input_set(pctype);
9594                         return 0;
9595                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9596                         *inset = I40E_INSET_NONE;
9597                         return 0;
9598                 }
9599         }
9600
9601         for (i = 0, *inset = 0; i < size; i++) {
9602                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9603                         if (field[i] == inset_convert_table[j].field) {
9604                                 *inset |= inset_convert_table[j].inset;
9605                                 break;
9606                         }
9607                 }
9608
9609                 /* It contains unsupported input set, return immediately */
9610                 if (j == RTE_DIM(inset_convert_table))
9611                         return ret;
9612         }
9613
9614         return 0;
9615 }
9616
9617 /**
9618  * Translate the input set from bit masks to register aware bit masks
9619  * and vice versa
9620  */
9621 uint64_t
9622 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9623 {
9624         uint64_t val = 0;
9625         uint16_t i;
9626
9627         struct inset_map {
9628                 uint64_t inset;
9629                 uint64_t inset_reg;
9630         };
9631
9632         static const struct inset_map inset_map_common[] = {
9633                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9634                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9635                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9636                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9637                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9638                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9639                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9640                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9641                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9642                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9643                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9644                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9645                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9646                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9647                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9648                 {I40E_INSET_TUNNEL_DMAC,
9649                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9650                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9651                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9652                 {I40E_INSET_TUNNEL_SRC_PORT,
9653                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9654                 {I40E_INSET_TUNNEL_DST_PORT,
9655                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9656                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9657                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9658                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9659                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9660                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9661                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9662                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9663                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9664                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9665         };
9666
9667     /* some different registers map in x722*/
9668         static const struct inset_map inset_map_diff_x722[] = {
9669                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9670                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9671                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9672                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9673         };
9674
9675         static const struct inset_map inset_map_diff_not_x722[] = {
9676                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9677                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9678                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9679                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9680         };
9681
9682         if (input == 0)
9683                 return val;
9684
9685         /* Translate input set to register aware inset */
9686         if (type == I40E_MAC_X722) {
9687                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9688                         if (input & inset_map_diff_x722[i].inset)
9689                                 val |= inset_map_diff_x722[i].inset_reg;
9690                 }
9691         } else {
9692                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9693                         if (input & inset_map_diff_not_x722[i].inset)
9694                                 val |= inset_map_diff_not_x722[i].inset_reg;
9695                 }
9696         }
9697
9698         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9699                 if (input & inset_map_common[i].inset)
9700                         val |= inset_map_common[i].inset_reg;
9701         }
9702
9703         return val;
9704 }
9705
9706 int
9707 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9708 {
9709         uint8_t i, idx = 0;
9710         uint64_t inset_need_mask = inset;
9711
9712         static const struct {
9713                 uint64_t inset;
9714                 uint32_t mask;
9715         } inset_mask_map[] = {
9716                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9717                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9718                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9719                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9720                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9721                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9722                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9723                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9724         };
9725
9726         if (!inset || !mask || !nb_elem)
9727                 return 0;
9728
9729         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9730                 /* Clear the inset bit, if no MASK is required,
9731                  * for example proto + ttl
9732                  */
9733                 if ((inset & inset_mask_map[i].inset) ==
9734                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9735                         inset_need_mask &= ~inset_mask_map[i].inset;
9736                 if (!inset_need_mask)
9737                         return 0;
9738         }
9739         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9740                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9741                     inset_mask_map[i].inset) {
9742                         if (idx >= nb_elem) {
9743                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9744                                 return -EINVAL;
9745                         }
9746                         mask[idx] = inset_mask_map[i].mask;
9747                         idx++;
9748                 }
9749         }
9750
9751         return idx;
9752 }
9753
9754 void
9755 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9756 {
9757         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9758
9759         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9760         if (reg != val)
9761                 i40e_write_rx_ctl(hw, addr, val);
9762         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9763                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9764 }
9765
9766 void
9767 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9768 {
9769         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9770         struct rte_eth_dev *dev;
9771
9772         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9773         if (reg != val) {
9774                 i40e_write_rx_ctl(hw, addr, val);
9775                 PMD_DRV_LOG(WARNING,
9776                             "i40e device %s changed global register [0x%08x]."
9777                             " original: 0x%08x, new: 0x%08x",
9778                             dev->device->name, addr, reg,
9779                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9780         }
9781 }
9782
9783 static void
9784 i40e_filter_input_set_init(struct i40e_pf *pf)
9785 {
9786         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9787         enum i40e_filter_pctype pctype;
9788         uint64_t input_set, inset_reg;
9789         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9790         int num, i;
9791         uint16_t flow_type;
9792
9793         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9794              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9795                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9796
9797                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9798                         continue;
9799
9800                 input_set = i40e_get_default_input_set(pctype);
9801
9802                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9803                                                    I40E_INSET_MASK_NUM_REG);
9804                 if (num < 0)
9805                         return;
9806                 if (pf->support_multi_driver && num > 0) {
9807                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9808                         return;
9809                 }
9810                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9811                                         input_set);
9812
9813                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9814                                       (uint32_t)(inset_reg & UINT32_MAX));
9815                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9816                                      (uint32_t)((inset_reg >>
9817                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9818                 if (!pf->support_multi_driver) {
9819                         i40e_check_write_global_reg(hw,
9820                                             I40E_GLQF_HASH_INSET(0, pctype),
9821                                             (uint32_t)(inset_reg & UINT32_MAX));
9822                         i40e_check_write_global_reg(hw,
9823                                              I40E_GLQF_HASH_INSET(1, pctype),
9824                                              (uint32_t)((inset_reg >>
9825                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9826
9827                         for (i = 0; i < num; i++) {
9828                                 i40e_check_write_global_reg(hw,
9829                                                     I40E_GLQF_FD_MSK(i, pctype),
9830                                                     mask_reg[i]);
9831                                 i40e_check_write_global_reg(hw,
9832                                                   I40E_GLQF_HASH_MSK(i, pctype),
9833                                                   mask_reg[i]);
9834                         }
9835                         /*clear unused mask registers of the pctype */
9836                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9837                                 i40e_check_write_global_reg(hw,
9838                                                     I40E_GLQF_FD_MSK(i, pctype),
9839                                                     0);
9840                                 i40e_check_write_global_reg(hw,
9841                                                   I40E_GLQF_HASH_MSK(i, pctype),
9842                                                   0);
9843                         }
9844                 } else {
9845                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9846                 }
9847                 I40E_WRITE_FLUSH(hw);
9848
9849                 /* store the default input set */
9850                 if (!pf->support_multi_driver)
9851                         pf->hash_input_set[pctype] = input_set;
9852                 pf->fdir.input_set[pctype] = input_set;
9853         }
9854 }
9855
9856 int
9857 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9858                          struct rte_eth_input_set_conf *conf)
9859 {
9860         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9861         enum i40e_filter_pctype pctype;
9862         uint64_t input_set, inset_reg = 0;
9863         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9864         int ret, i, num;
9865
9866         if (!conf) {
9867                 PMD_DRV_LOG(ERR, "Invalid pointer");
9868                 return -EFAULT;
9869         }
9870         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9871             conf->op != RTE_ETH_INPUT_SET_ADD) {
9872                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9873                 return -EINVAL;
9874         }
9875
9876         if (pf->support_multi_driver) {
9877                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9878                 return -ENOTSUP;
9879         }
9880
9881         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9882         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9883                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9884                 return -EINVAL;
9885         }
9886
9887         if (hw->mac.type == I40E_MAC_X722) {
9888                 /* get translated pctype value in fd pctype register */
9889                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9890                         I40E_GLQF_FD_PCTYPES((int)pctype));
9891         }
9892
9893         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9894                                    conf->inset_size);
9895         if (ret) {
9896                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9897                 return -EINVAL;
9898         }
9899
9900         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9901                 /* get inset value in register */
9902                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9903                 inset_reg <<= I40E_32_BIT_WIDTH;
9904                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9905                 input_set |= pf->hash_input_set[pctype];
9906         }
9907         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9908                                            I40E_INSET_MASK_NUM_REG);
9909         if (num < 0)
9910                 return -EINVAL;
9911
9912         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9913
9914         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9915                                     (uint32_t)(inset_reg & UINT32_MAX));
9916         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9917                                     (uint32_t)((inset_reg >>
9918                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9919
9920         for (i = 0; i < num; i++)
9921                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9922                                             mask_reg[i]);
9923         /*clear unused mask registers of the pctype */
9924         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9925                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9926                                             0);
9927         I40E_WRITE_FLUSH(hw);
9928
9929         pf->hash_input_set[pctype] = input_set;
9930         return 0;
9931 }
9932
9933 int
9934 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9935                          struct rte_eth_input_set_conf *conf)
9936 {
9937         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9938         enum i40e_filter_pctype pctype;
9939         uint64_t input_set, inset_reg = 0;
9940         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9941         int ret, i, num;
9942
9943         if (!hw || !conf) {
9944                 PMD_DRV_LOG(ERR, "Invalid pointer");
9945                 return -EFAULT;
9946         }
9947         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9948             conf->op != RTE_ETH_INPUT_SET_ADD) {
9949                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9950                 return -EINVAL;
9951         }
9952
9953         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9954
9955         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9956                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9957                 return -EINVAL;
9958         }
9959
9960         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9961                                    conf->inset_size);
9962         if (ret) {
9963                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9964                 return -EINVAL;
9965         }
9966
9967         /* get inset value in register */
9968         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9969         inset_reg <<= I40E_32_BIT_WIDTH;
9970         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9971
9972         /* Can not change the inset reg for flex payload for fdir,
9973          * it is done by writing I40E_PRTQF_FD_FLXINSET
9974          * in i40e_set_flex_mask_on_pctype.
9975          */
9976         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9977                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9978         else
9979                 input_set |= pf->fdir.input_set[pctype];
9980         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9981                                            I40E_INSET_MASK_NUM_REG);
9982         if (num < 0)
9983                 return -EINVAL;
9984         if (pf->support_multi_driver && num > 0) {
9985                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9986                 return -ENOTSUP;
9987         }
9988
9989         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9990
9991         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9992                               (uint32_t)(inset_reg & UINT32_MAX));
9993         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9994                              (uint32_t)((inset_reg >>
9995                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9996
9997         if (!pf->support_multi_driver) {
9998                 for (i = 0; i < num; i++)
9999                         i40e_check_write_global_reg(hw,
10000                                                     I40E_GLQF_FD_MSK(i, pctype),
10001                                                     mask_reg[i]);
10002                 /*clear unused mask registers of the pctype */
10003                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10004                         i40e_check_write_global_reg(hw,
10005                                                     I40E_GLQF_FD_MSK(i, pctype),
10006                                                     0);
10007         } else {
10008                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10009         }
10010         I40E_WRITE_FLUSH(hw);
10011
10012         pf->fdir.input_set[pctype] = input_set;
10013         return 0;
10014 }
10015
10016 static int
10017 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10018 {
10019         int ret = 0;
10020
10021         if (!hw || !info) {
10022                 PMD_DRV_LOG(ERR, "Invalid pointer");
10023                 return -EFAULT;
10024         }
10025
10026         switch (info->info_type) {
10027         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10028                 i40e_get_symmetric_hash_enable_per_port(hw,
10029                                         &(info->info.enable));
10030                 break;
10031         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10032                 ret = i40e_get_hash_filter_global_config(hw,
10033                                 &(info->info.global_conf));
10034                 break;
10035         default:
10036                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10037                                                         info->info_type);
10038                 ret = -EINVAL;
10039                 break;
10040         }
10041
10042         return ret;
10043 }
10044
10045 static int
10046 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10047 {
10048         int ret = 0;
10049
10050         if (!hw || !info) {
10051                 PMD_DRV_LOG(ERR, "Invalid pointer");
10052                 return -EFAULT;
10053         }
10054
10055         switch (info->info_type) {
10056         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10057                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10058                 break;
10059         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10060                 ret = i40e_set_hash_filter_global_config(hw,
10061                                 &(info->info.global_conf));
10062                 break;
10063         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10064                 ret = i40e_hash_filter_inset_select(hw,
10065                                                &(info->info.input_set_conf));
10066                 break;
10067
10068         default:
10069                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10070                                                         info->info_type);
10071                 ret = -EINVAL;
10072                 break;
10073         }
10074
10075         return ret;
10076 }
10077
10078 /* Operations for hash function */
10079 static int
10080 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10081                       enum rte_filter_op filter_op,
10082                       void *arg)
10083 {
10084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10085         int ret = 0;
10086
10087         switch (filter_op) {
10088         case RTE_ETH_FILTER_NOP:
10089                 break;
10090         case RTE_ETH_FILTER_GET:
10091                 ret = i40e_hash_filter_get(hw,
10092                         (struct rte_eth_hash_filter_info *)arg);
10093                 break;
10094         case RTE_ETH_FILTER_SET:
10095                 ret = i40e_hash_filter_set(hw,
10096                         (struct rte_eth_hash_filter_info *)arg);
10097                 break;
10098         default:
10099                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10100                                                                 filter_op);
10101                 ret = -ENOTSUP;
10102                 break;
10103         }
10104
10105         return ret;
10106 }
10107
10108 /* Convert ethertype filter structure */
10109 static int
10110 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10111                               struct i40e_ethertype_filter *filter)
10112 {
10113         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10114                 RTE_ETHER_ADDR_LEN);
10115         filter->input.ether_type = input->ether_type;
10116         filter->flags = input->flags;
10117         filter->queue = input->queue;
10118
10119         return 0;
10120 }
10121
10122 /* Check if there exists the ehtertype filter */
10123 struct i40e_ethertype_filter *
10124 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10125                                 const struct i40e_ethertype_filter_input *input)
10126 {
10127         int ret;
10128
10129         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10130         if (ret < 0)
10131                 return NULL;
10132
10133         return ethertype_rule->hash_map[ret];
10134 }
10135
10136 /* Add ethertype filter in SW list */
10137 static int
10138 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10139                                 struct i40e_ethertype_filter *filter)
10140 {
10141         struct i40e_ethertype_rule *rule = &pf->ethertype;
10142         int ret;
10143
10144         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10145         if (ret < 0) {
10146                 PMD_DRV_LOG(ERR,
10147                             "Failed to insert ethertype filter"
10148                             " to hash table %d!",
10149                             ret);
10150                 return ret;
10151         }
10152         rule->hash_map[ret] = filter;
10153
10154         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10155
10156         return 0;
10157 }
10158
10159 /* Delete ethertype filter in SW list */
10160 int
10161 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10162                              struct i40e_ethertype_filter_input *input)
10163 {
10164         struct i40e_ethertype_rule *rule = &pf->ethertype;
10165         struct i40e_ethertype_filter *filter;
10166         int ret;
10167
10168         ret = rte_hash_del_key(rule->hash_table, input);
10169         if (ret < 0) {
10170                 PMD_DRV_LOG(ERR,
10171                             "Failed to delete ethertype filter"
10172                             " to hash table %d!",
10173                             ret);
10174                 return ret;
10175         }
10176         filter = rule->hash_map[ret];
10177         rule->hash_map[ret] = NULL;
10178
10179         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10180         rte_free(filter);
10181
10182         return 0;
10183 }
10184
10185 /*
10186  * Configure ethertype filter, which can director packet by filtering
10187  * with mac address and ether_type or only ether_type
10188  */
10189 int
10190 i40e_ethertype_filter_set(struct i40e_pf *pf,
10191                         struct rte_eth_ethertype_filter *filter,
10192                         bool add)
10193 {
10194         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10195         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10196         struct i40e_ethertype_filter *ethertype_filter, *node;
10197         struct i40e_ethertype_filter check_filter;
10198         struct i40e_control_filter_stats stats;
10199         uint16_t flags = 0;
10200         int ret;
10201
10202         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10203                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10204                 return -EINVAL;
10205         }
10206         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10207                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10208                 PMD_DRV_LOG(ERR,
10209                         "unsupported ether_type(0x%04x) in control packet filter.",
10210                         filter->ether_type);
10211                 return -EINVAL;
10212         }
10213         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10214                 PMD_DRV_LOG(WARNING,
10215                         "filter vlan ether_type in first tag is not supported.");
10216
10217         /* Check if there is the filter in SW list */
10218         memset(&check_filter, 0, sizeof(check_filter));
10219         i40e_ethertype_filter_convert(filter, &check_filter);
10220         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10221                                                &check_filter.input);
10222         if (add && node) {
10223                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10224                 return -EINVAL;
10225         }
10226
10227         if (!add && !node) {
10228                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10229                 return -EINVAL;
10230         }
10231
10232         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10233                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10234         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10235                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10236         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10237
10238         memset(&stats, 0, sizeof(stats));
10239         ret = i40e_aq_add_rem_control_packet_filter(hw,
10240                         filter->mac_addr.addr_bytes,
10241                         filter->ether_type, flags,
10242                         pf->main_vsi->seid,
10243                         filter->queue, add, &stats, NULL);
10244
10245         PMD_DRV_LOG(INFO,
10246                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10247                 ret, stats.mac_etype_used, stats.etype_used,
10248                 stats.mac_etype_free, stats.etype_free);
10249         if (ret < 0)
10250                 return -ENOSYS;
10251
10252         /* Add or delete a filter in SW list */
10253         if (add) {
10254                 ethertype_filter = rte_zmalloc("ethertype_filter",
10255                                        sizeof(*ethertype_filter), 0);
10256                 if (ethertype_filter == NULL) {
10257                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10258                         return -ENOMEM;
10259                 }
10260
10261                 rte_memcpy(ethertype_filter, &check_filter,
10262                            sizeof(check_filter));
10263                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10264                 if (ret < 0)
10265                         rte_free(ethertype_filter);
10266         } else {
10267                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10268         }
10269
10270         return ret;
10271 }
10272
10273 /*
10274  * Handle operations for ethertype filter.
10275  */
10276 static int
10277 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10278                                 enum rte_filter_op filter_op,
10279                                 void *arg)
10280 {
10281         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10282         int ret = 0;
10283
10284         if (filter_op == RTE_ETH_FILTER_NOP)
10285                 return ret;
10286
10287         if (arg == NULL) {
10288                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10289                             filter_op);
10290                 return -EINVAL;
10291         }
10292
10293         switch (filter_op) {
10294         case RTE_ETH_FILTER_ADD:
10295                 ret = i40e_ethertype_filter_set(pf,
10296                         (struct rte_eth_ethertype_filter *)arg,
10297                         TRUE);
10298                 break;
10299         case RTE_ETH_FILTER_DELETE:
10300                 ret = i40e_ethertype_filter_set(pf,
10301                         (struct rte_eth_ethertype_filter *)arg,
10302                         FALSE);
10303                 break;
10304         default:
10305                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10306                 ret = -ENOSYS;
10307                 break;
10308         }
10309         return ret;
10310 }
10311
10312 static int
10313 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10314                      enum rte_filter_type filter_type,
10315                      enum rte_filter_op filter_op,
10316                      void *arg)
10317 {
10318         int ret = 0;
10319
10320         if (dev == NULL)
10321                 return -EINVAL;
10322
10323         switch (filter_type) {
10324         case RTE_ETH_FILTER_NONE:
10325                 /* For global configuration */
10326                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10327                 break;
10328         case RTE_ETH_FILTER_HASH:
10329                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10330                 break;
10331         case RTE_ETH_FILTER_MACVLAN:
10332                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10333                 break;
10334         case RTE_ETH_FILTER_ETHERTYPE:
10335                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10336                 break;
10337         case RTE_ETH_FILTER_TUNNEL:
10338                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10339                 break;
10340         case RTE_ETH_FILTER_FDIR:
10341                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10342                 break;
10343         case RTE_ETH_FILTER_GENERIC:
10344                 if (filter_op != RTE_ETH_FILTER_GET)
10345                         return -EINVAL;
10346                 *(const void **)arg = &i40e_flow_ops;
10347                 break;
10348         default:
10349                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10350                                                         filter_type);
10351                 ret = -EINVAL;
10352                 break;
10353         }
10354
10355         return ret;
10356 }
10357
10358 /*
10359  * Check and enable Extended Tag.
10360  * Enabling Extended Tag is important for 40G performance.
10361  */
10362 static void
10363 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10364 {
10365         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10366         uint32_t buf = 0;
10367         int ret;
10368
10369         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10370                                       PCI_DEV_CAP_REG);
10371         if (ret < 0) {
10372                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10373                             PCI_DEV_CAP_REG);
10374                 return;
10375         }
10376         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10377                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10378                 return;
10379         }
10380
10381         buf = 0;
10382         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10383                                       PCI_DEV_CTRL_REG);
10384         if (ret < 0) {
10385                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10386                             PCI_DEV_CTRL_REG);
10387                 return;
10388         }
10389         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10390                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10391                 return;
10392         }
10393         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10394         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10395                                        PCI_DEV_CTRL_REG);
10396         if (ret < 0) {
10397                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10398                             PCI_DEV_CTRL_REG);
10399                 return;
10400         }
10401 }
10402
10403 /*
10404  * As some registers wouldn't be reset unless a global hardware reset,
10405  * hardware initialization is needed to put those registers into an
10406  * expected initial state.
10407  */
10408 static void
10409 i40e_hw_init(struct rte_eth_dev *dev)
10410 {
10411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10412
10413         i40e_enable_extended_tag(dev);
10414
10415         /* clear the PF Queue Filter control register */
10416         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10417
10418         /* Disable symmetric hash per port */
10419         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10420 }
10421
10422 /*
10423  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10424  * however this function will return only one highest pctype index,
10425  * which is not quite correct. This is known problem of i40e driver
10426  * and needs to be fixed later.
10427  */
10428 enum i40e_filter_pctype
10429 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10430 {
10431         int i;
10432         uint64_t pctype_mask;
10433
10434         if (flow_type < I40E_FLOW_TYPE_MAX) {
10435                 pctype_mask = adapter->pctypes_tbl[flow_type];
10436                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10437                         if (pctype_mask & (1ULL << i))
10438                                 return (enum i40e_filter_pctype)i;
10439                 }
10440         }
10441         return I40E_FILTER_PCTYPE_INVALID;
10442 }
10443
10444 uint16_t
10445 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10446                         enum i40e_filter_pctype pctype)
10447 {
10448         uint16_t flowtype;
10449         uint64_t pctype_mask = 1ULL << pctype;
10450
10451         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10452              flowtype++) {
10453                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10454                         return flowtype;
10455         }
10456
10457         return RTE_ETH_FLOW_UNKNOWN;
10458 }
10459
10460 /*
10461  * On X710, performance number is far from the expectation on recent firmware
10462  * versions; on XL710, performance number is also far from the expectation on
10463  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10464  * mode is enabled and port MAC address is equal to the packet destination MAC
10465  * address. The fix for this issue may not be integrated in the following
10466  * firmware version. So the workaround in software driver is needed. It needs
10467  * to modify the initial values of 3 internal only registers for both X710 and
10468  * XL710. Note that the values for X710 or XL710 could be different, and the
10469  * workaround can be removed when it is fixed in firmware in the future.
10470  */
10471
10472 /* For both X710 and XL710 */
10473 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10474 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10475 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10476
10477 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10478 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10479
10480 /* For X722 */
10481 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10482 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10483
10484 /* For X710 */
10485 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10486 /* For XL710 */
10487 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10488 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10489
10490 /*
10491  * GL_SWR_PM_UP_THR:
10492  * The value is not impacted from the link speed, its value is set according
10493  * to the total number of ports for a better pipe-monitor configuration.
10494  */
10495 static bool
10496 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10497 {
10498 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10499                 .device_id = (dev),   \
10500                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10501
10502 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10503                 .device_id = (dev),   \
10504                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10505
10506         static const struct {
10507                 uint16_t device_id;
10508                 uint32_t val;
10509         } swr_pm_table[] = {
10510                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10511                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10512                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10513                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10514                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10515
10516                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10517                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10518                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10519                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10520                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10521                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10522                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10523         };
10524         uint32_t i;
10525
10526         if (value == NULL) {
10527                 PMD_DRV_LOG(ERR, "value is NULL");
10528                 return false;
10529         }
10530
10531         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10532                 if (hw->device_id == swr_pm_table[i].device_id) {
10533                         *value = swr_pm_table[i].val;
10534
10535                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10536                                     "value - 0x%08x",
10537                                     hw->device_id, *value);
10538                         return true;
10539                 }
10540         }
10541
10542         return false;
10543 }
10544
10545 static int
10546 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10547 {
10548         enum i40e_status_code status;
10549         struct i40e_aq_get_phy_abilities_resp phy_ab;
10550         int ret = -ENOTSUP;
10551         int retries = 0;
10552
10553         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10554                                               NULL);
10555
10556         while (status) {
10557                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10558                         status);
10559                 retries++;
10560                 rte_delay_us(100000);
10561                 if  (retries < 5)
10562                         status = i40e_aq_get_phy_capabilities(hw, false,
10563                                         true, &phy_ab, NULL);
10564                 else
10565                         return ret;
10566         }
10567         return 0;
10568 }
10569
10570 static void
10571 i40e_configure_registers(struct i40e_hw *hw)
10572 {
10573         static struct {
10574                 uint32_t addr;
10575                 uint64_t val;
10576         } reg_table[] = {
10577                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10578                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10579                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10580         };
10581         uint64_t reg;
10582         uint32_t i;
10583         int ret;
10584
10585         for (i = 0; i < RTE_DIM(reg_table); i++) {
10586                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10587                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10588                                 reg_table[i].val =
10589                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10590                         else /* For X710/XL710/XXV710 */
10591                                 if (hw->aq.fw_maj_ver < 6)
10592                                         reg_table[i].val =
10593                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10594                                 else
10595                                         reg_table[i].val =
10596                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10597                 }
10598
10599                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10600                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10601                                 reg_table[i].val =
10602                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10603                         else /* For X710/XL710/XXV710 */
10604                                 reg_table[i].val =
10605                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10606                 }
10607
10608                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10609                         uint32_t cfg_val;
10610
10611                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10612                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10613                                             "GL_SWR_PM_UP_THR value fixup",
10614                                             hw->device_id);
10615                                 continue;
10616                         }
10617
10618                         reg_table[i].val = cfg_val;
10619                 }
10620
10621                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10622                                                         &reg, NULL);
10623                 if (ret < 0) {
10624                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10625                                                         reg_table[i].addr);
10626                         break;
10627                 }
10628                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10629                                                 reg_table[i].addr, reg);
10630                 if (reg == reg_table[i].val)
10631                         continue;
10632
10633                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10634                                                 reg_table[i].val, NULL);
10635                 if (ret < 0) {
10636                         PMD_DRV_LOG(ERR,
10637                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10638                                 reg_table[i].val, reg_table[i].addr);
10639                         break;
10640                 }
10641                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10642                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10643         }
10644 }
10645
10646 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10647 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10648 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10649 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10650 static int
10651 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10652 {
10653         uint32_t reg;
10654         int ret;
10655
10656         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10657                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10658                 return -EINVAL;
10659         }
10660
10661         /* Configure for double VLAN RX stripping */
10662         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10663         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10664                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10665                 ret = i40e_aq_debug_write_register(hw,
10666                                                    I40E_VSI_TSR(vsi->vsi_id),
10667                                                    reg, NULL);
10668                 if (ret < 0) {
10669                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10670                                     vsi->vsi_id);
10671                         return I40E_ERR_CONFIG;
10672                 }
10673         }
10674
10675         /* Configure for double VLAN TX insertion */
10676         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10677         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10678                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10679                 ret = i40e_aq_debug_write_register(hw,
10680                                                    I40E_VSI_L2TAGSTXVALID(
10681                                                    vsi->vsi_id), reg, NULL);
10682                 if (ret < 0) {
10683                         PMD_DRV_LOG(ERR,
10684                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10685                                 vsi->vsi_id);
10686                         return I40E_ERR_CONFIG;
10687                 }
10688         }
10689
10690         return 0;
10691 }
10692
10693 /**
10694  * i40e_aq_add_mirror_rule
10695  * @hw: pointer to the hardware structure
10696  * @seid: VEB seid to add mirror rule to
10697  * @dst_id: destination vsi seid
10698  * @entries: Buffer which contains the entities to be mirrored
10699  * @count: number of entities contained in the buffer
10700  * @rule_id:the rule_id of the rule to be added
10701  *
10702  * Add a mirror rule for a given veb.
10703  *
10704  **/
10705 static enum i40e_status_code
10706 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10707                         uint16_t seid, uint16_t dst_id,
10708                         uint16_t rule_type, uint16_t *entries,
10709                         uint16_t count, uint16_t *rule_id)
10710 {
10711         struct i40e_aq_desc desc;
10712         struct i40e_aqc_add_delete_mirror_rule cmd;
10713         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10714                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10715                 &desc.params.raw;
10716         uint16_t buff_len;
10717         enum i40e_status_code status;
10718
10719         i40e_fill_default_direct_cmd_desc(&desc,
10720                                           i40e_aqc_opc_add_mirror_rule);
10721         memset(&cmd, 0, sizeof(cmd));
10722
10723         buff_len = sizeof(uint16_t) * count;
10724         desc.datalen = rte_cpu_to_le_16(buff_len);
10725         if (buff_len > 0)
10726                 desc.flags |= rte_cpu_to_le_16(
10727                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10728         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10729                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10730         cmd.num_entries = rte_cpu_to_le_16(count);
10731         cmd.seid = rte_cpu_to_le_16(seid);
10732         cmd.destination = rte_cpu_to_le_16(dst_id);
10733
10734         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10735         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10736         PMD_DRV_LOG(INFO,
10737                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10738                 hw->aq.asq_last_status, resp->rule_id,
10739                 resp->mirror_rules_used, resp->mirror_rules_free);
10740         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10741
10742         return status;
10743 }
10744
10745 /**
10746  * i40e_aq_del_mirror_rule
10747  * @hw: pointer to the hardware structure
10748  * @seid: VEB seid to add mirror rule to
10749  * @entries: Buffer which contains the entities to be mirrored
10750  * @count: number of entities contained in the buffer
10751  * @rule_id:the rule_id of the rule to be delete
10752  *
10753  * Delete a mirror rule for a given veb.
10754  *
10755  **/
10756 static enum i40e_status_code
10757 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10758                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10759                 uint16_t count, uint16_t rule_id)
10760 {
10761         struct i40e_aq_desc desc;
10762         struct i40e_aqc_add_delete_mirror_rule cmd;
10763         uint16_t buff_len = 0;
10764         enum i40e_status_code status;
10765         void *buff = NULL;
10766
10767         i40e_fill_default_direct_cmd_desc(&desc,
10768                                           i40e_aqc_opc_delete_mirror_rule);
10769         memset(&cmd, 0, sizeof(cmd));
10770         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10771                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10772                                                           I40E_AQ_FLAG_RD));
10773                 cmd.num_entries = count;
10774                 buff_len = sizeof(uint16_t) * count;
10775                 desc.datalen = rte_cpu_to_le_16(buff_len);
10776                 buff = (void *)entries;
10777         } else
10778                 /* rule id is filled in destination field for deleting mirror rule */
10779                 cmd.destination = rte_cpu_to_le_16(rule_id);
10780
10781         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10782                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10783         cmd.seid = rte_cpu_to_le_16(seid);
10784
10785         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10786         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10787
10788         return status;
10789 }
10790
10791 /**
10792  * i40e_mirror_rule_set
10793  * @dev: pointer to the hardware structure
10794  * @mirror_conf: mirror rule info
10795  * @sw_id: mirror rule's sw_id
10796  * @on: enable/disable
10797  *
10798  * set a mirror rule.
10799  *
10800  **/
10801 static int
10802 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10803                         struct rte_eth_mirror_conf *mirror_conf,
10804                         uint8_t sw_id, uint8_t on)
10805 {
10806         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10807         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10808         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10809         struct i40e_mirror_rule *parent = NULL;
10810         uint16_t seid, dst_seid, rule_id;
10811         uint16_t i, j = 0;
10812         int ret;
10813
10814         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10815
10816         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10817                 PMD_DRV_LOG(ERR,
10818                         "mirror rule can not be configured without veb or vfs.");
10819                 return -ENOSYS;
10820         }
10821         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10822                 PMD_DRV_LOG(ERR, "mirror table is full.");
10823                 return -ENOSPC;
10824         }
10825         if (mirror_conf->dst_pool > pf->vf_num) {
10826                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10827                                  mirror_conf->dst_pool);
10828                 return -EINVAL;
10829         }
10830
10831         seid = pf->main_vsi->veb->seid;
10832
10833         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10834                 if (sw_id <= it->index) {
10835                         mirr_rule = it;
10836                         break;
10837                 }
10838                 parent = it;
10839         }
10840         if (mirr_rule && sw_id == mirr_rule->index) {
10841                 if (on) {
10842                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10843                         return -EEXIST;
10844                 } else {
10845                         ret = i40e_aq_del_mirror_rule(hw, seid,
10846                                         mirr_rule->rule_type,
10847                                         mirr_rule->entries,
10848                                         mirr_rule->num_entries, mirr_rule->id);
10849                         if (ret < 0) {
10850                                 PMD_DRV_LOG(ERR,
10851                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10852                                         ret, hw->aq.asq_last_status);
10853                                 return -ENOSYS;
10854                         }
10855                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10856                         rte_free(mirr_rule);
10857                         pf->nb_mirror_rule--;
10858                         return 0;
10859                 }
10860         } else if (!on) {
10861                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10862                 return -ENOENT;
10863         }
10864
10865         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10866                                 sizeof(struct i40e_mirror_rule) , 0);
10867         if (!mirr_rule) {
10868                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10869                 return I40E_ERR_NO_MEMORY;
10870         }
10871         switch (mirror_conf->rule_type) {
10872         case ETH_MIRROR_VLAN:
10873                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10874                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10875                                 mirr_rule->entries[j] =
10876                                         mirror_conf->vlan.vlan_id[i];
10877                                 j++;
10878                         }
10879                 }
10880                 if (j == 0) {
10881                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10882                         rte_free(mirr_rule);
10883                         return -EINVAL;
10884                 }
10885                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10886                 break;
10887         case ETH_MIRROR_VIRTUAL_POOL_UP:
10888         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10889                 /* check if the specified pool bit is out of range */
10890                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10891                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10892                         rte_free(mirr_rule);
10893                         return -EINVAL;
10894                 }
10895                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10896                         if (mirror_conf->pool_mask & (1ULL << i)) {
10897                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10898                                 j++;
10899                         }
10900                 }
10901                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10902                         /* add pf vsi to entries */
10903                         mirr_rule->entries[j] = pf->main_vsi_seid;
10904                         j++;
10905                 }
10906                 if (j == 0) {
10907                         PMD_DRV_LOG(ERR, "pool is not specified.");
10908                         rte_free(mirr_rule);
10909                         return -EINVAL;
10910                 }
10911                 /* egress and ingress in aq commands means from switch but not port */
10912                 mirr_rule->rule_type =
10913                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10914                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10915                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10916                 break;
10917         case ETH_MIRROR_UPLINK_PORT:
10918                 /* egress and ingress in aq commands means from switch but not port*/
10919                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10920                 break;
10921         case ETH_MIRROR_DOWNLINK_PORT:
10922                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10923                 break;
10924         default:
10925                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10926                         mirror_conf->rule_type);
10927                 rte_free(mirr_rule);
10928                 return -EINVAL;
10929         }
10930
10931         /* If the dst_pool is equal to vf_num, consider it as PF */
10932         if (mirror_conf->dst_pool == pf->vf_num)
10933                 dst_seid = pf->main_vsi_seid;
10934         else
10935                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10936
10937         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10938                                       mirr_rule->rule_type, mirr_rule->entries,
10939                                       j, &rule_id);
10940         if (ret < 0) {
10941                 PMD_DRV_LOG(ERR,
10942                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10943                         ret, hw->aq.asq_last_status);
10944                 rte_free(mirr_rule);
10945                 return -ENOSYS;
10946         }
10947
10948         mirr_rule->index = sw_id;
10949         mirr_rule->num_entries = j;
10950         mirr_rule->id = rule_id;
10951         mirr_rule->dst_vsi_seid = dst_seid;
10952
10953         if (parent)
10954                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10955         else
10956                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10957
10958         pf->nb_mirror_rule++;
10959         return 0;
10960 }
10961
10962 /**
10963  * i40e_mirror_rule_reset
10964  * @dev: pointer to the device
10965  * @sw_id: mirror rule's sw_id
10966  *
10967  * reset a mirror rule.
10968  *
10969  **/
10970 static int
10971 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10972 {
10973         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10975         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10976         uint16_t seid;
10977         int ret;
10978
10979         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10980
10981         seid = pf->main_vsi->veb->seid;
10982
10983         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10984                 if (sw_id == it->index) {
10985                         mirr_rule = it;
10986                         break;
10987                 }
10988         }
10989         if (mirr_rule) {
10990                 ret = i40e_aq_del_mirror_rule(hw, seid,
10991                                 mirr_rule->rule_type,
10992                                 mirr_rule->entries,
10993                                 mirr_rule->num_entries, mirr_rule->id);
10994                 if (ret < 0) {
10995                         PMD_DRV_LOG(ERR,
10996                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10997                                 ret, hw->aq.asq_last_status);
10998                         return -ENOSYS;
10999                 }
11000                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11001                 rte_free(mirr_rule);
11002                 pf->nb_mirror_rule--;
11003         } else {
11004                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11005                 return -ENOENT;
11006         }
11007         return 0;
11008 }
11009
11010 static uint64_t
11011 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11012 {
11013         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11014         uint64_t systim_cycles;
11015
11016         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11017         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11018                         << 32;
11019
11020         return systim_cycles;
11021 }
11022
11023 static uint64_t
11024 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11025 {
11026         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11027         uint64_t rx_tstamp;
11028
11029         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11030         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11031                         << 32;
11032
11033         return rx_tstamp;
11034 }
11035
11036 static uint64_t
11037 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11038 {
11039         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11040         uint64_t tx_tstamp;
11041
11042         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11043         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11044                         << 32;
11045
11046         return tx_tstamp;
11047 }
11048
11049 static void
11050 i40e_start_timecounters(struct rte_eth_dev *dev)
11051 {
11052         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11053         struct i40e_adapter *adapter = dev->data->dev_private;
11054         struct rte_eth_link link;
11055         uint32_t tsync_inc_l;
11056         uint32_t tsync_inc_h;
11057
11058         /* Get current link speed. */
11059         i40e_dev_link_update(dev, 1);
11060         rte_eth_linkstatus_get(dev, &link);
11061
11062         switch (link.link_speed) {
11063         case ETH_SPEED_NUM_40G:
11064         case ETH_SPEED_NUM_25G:
11065                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11066                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11067                 break;
11068         case ETH_SPEED_NUM_10G:
11069                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11070                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11071                 break;
11072         case ETH_SPEED_NUM_1G:
11073                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11074                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11075                 break;
11076         default:
11077                 tsync_inc_l = 0x0;
11078                 tsync_inc_h = 0x0;
11079         }
11080
11081         /* Set the timesync increment value. */
11082         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11083         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11084
11085         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11086         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11087         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11088
11089         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11090         adapter->systime_tc.cc_shift = 0;
11091         adapter->systime_tc.nsec_mask = 0;
11092
11093         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11094         adapter->rx_tstamp_tc.cc_shift = 0;
11095         adapter->rx_tstamp_tc.nsec_mask = 0;
11096
11097         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11098         adapter->tx_tstamp_tc.cc_shift = 0;
11099         adapter->tx_tstamp_tc.nsec_mask = 0;
11100 }
11101
11102 static int
11103 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11104 {
11105         struct i40e_adapter *adapter = dev->data->dev_private;
11106
11107         adapter->systime_tc.nsec += delta;
11108         adapter->rx_tstamp_tc.nsec += delta;
11109         adapter->tx_tstamp_tc.nsec += delta;
11110
11111         return 0;
11112 }
11113
11114 static int
11115 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11116 {
11117         uint64_t ns;
11118         struct i40e_adapter *adapter = dev->data->dev_private;
11119
11120         ns = rte_timespec_to_ns(ts);
11121
11122         /* Set the timecounters to a new value. */
11123         adapter->systime_tc.nsec = ns;
11124         adapter->rx_tstamp_tc.nsec = ns;
11125         adapter->tx_tstamp_tc.nsec = ns;
11126
11127         return 0;
11128 }
11129
11130 static int
11131 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11132 {
11133         uint64_t ns, systime_cycles;
11134         struct i40e_adapter *adapter = dev->data->dev_private;
11135
11136         systime_cycles = i40e_read_systime_cyclecounter(dev);
11137         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11138         *ts = rte_ns_to_timespec(ns);
11139
11140         return 0;
11141 }
11142
11143 static int
11144 i40e_timesync_enable(struct rte_eth_dev *dev)
11145 {
11146         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11147         uint32_t tsync_ctl_l;
11148         uint32_t tsync_ctl_h;
11149
11150         /* Stop the timesync system time. */
11151         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11152         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11153         /* Reset the timesync system time value. */
11154         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11155         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11156
11157         i40e_start_timecounters(dev);
11158
11159         /* Clear timesync registers. */
11160         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11161         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11162         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11163         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11164         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11165         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11166
11167         /* Enable timestamping of PTP packets. */
11168         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11169         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11170
11171         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11172         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11173         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11174
11175         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11176         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11177
11178         return 0;
11179 }
11180
11181 static int
11182 i40e_timesync_disable(struct rte_eth_dev *dev)
11183 {
11184         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11185         uint32_t tsync_ctl_l;
11186         uint32_t tsync_ctl_h;
11187
11188         /* Disable timestamping of transmitted PTP packets. */
11189         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11190         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11191
11192         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11193         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11194
11195         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11196         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11197
11198         /* Reset the timesync increment value. */
11199         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11200         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11201
11202         return 0;
11203 }
11204
11205 static int
11206 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11207                                 struct timespec *timestamp, uint32_t flags)
11208 {
11209         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11210         struct i40e_adapter *adapter = dev->data->dev_private;
11211         uint32_t sync_status;
11212         uint32_t index = flags & 0x03;
11213         uint64_t rx_tstamp_cycles;
11214         uint64_t ns;
11215
11216         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11217         if ((sync_status & (1 << index)) == 0)
11218                 return -EINVAL;
11219
11220         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11221         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11222         *timestamp = rte_ns_to_timespec(ns);
11223
11224         return 0;
11225 }
11226
11227 static int
11228 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11229                                 struct timespec *timestamp)
11230 {
11231         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11232         struct i40e_adapter *adapter = dev->data->dev_private;
11233         uint32_t sync_status;
11234         uint64_t tx_tstamp_cycles;
11235         uint64_t ns;
11236
11237         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11238         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11239                 return -EINVAL;
11240
11241         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11242         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11243         *timestamp = rte_ns_to_timespec(ns);
11244
11245         return 0;
11246 }
11247
11248 /*
11249  * i40e_parse_dcb_configure - parse dcb configure from user
11250  * @dev: the device being configured
11251  * @dcb_cfg: pointer of the result of parse
11252  * @*tc_map: bit map of enabled traffic classes
11253  *
11254  * Returns 0 on success, negative value on failure
11255  */
11256 static int
11257 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11258                          struct i40e_dcbx_config *dcb_cfg,
11259                          uint8_t *tc_map)
11260 {
11261         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11262         uint8_t i, tc_bw, bw_lf;
11263
11264         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11265
11266         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11267         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11268                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11269                 return -EINVAL;
11270         }
11271
11272         /* assume each tc has the same bw */
11273         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11274         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11275                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11276         /* to ensure the sum of tcbw is equal to 100 */
11277         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11278         for (i = 0; i < bw_lf; i++)
11279                 dcb_cfg->etscfg.tcbwtable[i]++;
11280
11281         /* assume each tc has the same Transmission Selection Algorithm */
11282         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11283                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11284
11285         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11286                 dcb_cfg->etscfg.prioritytable[i] =
11287                                 dcb_rx_conf->dcb_tc[i];
11288
11289         /* FW needs one App to configure HW */
11290         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11291         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11292         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11293         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11294
11295         if (dcb_rx_conf->nb_tcs == 0)
11296                 *tc_map = 1; /* tc0 only */
11297         else
11298                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11299
11300         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11301                 dcb_cfg->pfc.willing = 0;
11302                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11303                 dcb_cfg->pfc.pfcenable = *tc_map;
11304         }
11305         return 0;
11306 }
11307
11308
11309 static enum i40e_status_code
11310 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11311                               struct i40e_aqc_vsi_properties_data *info,
11312                               uint8_t enabled_tcmap)
11313 {
11314         enum i40e_status_code ret;
11315         int i, total_tc = 0;
11316         uint16_t qpnum_per_tc, bsf, qp_idx;
11317         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11318         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11319         uint16_t used_queues;
11320
11321         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11322         if (ret != I40E_SUCCESS)
11323                 return ret;
11324
11325         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11326                 if (enabled_tcmap & (1 << i))
11327                         total_tc++;
11328         }
11329         if (total_tc == 0)
11330                 total_tc = 1;
11331         vsi->enabled_tc = enabled_tcmap;
11332
11333         /* different VSI has different queues assigned */
11334         if (vsi->type == I40E_VSI_MAIN)
11335                 used_queues = dev_data->nb_rx_queues -
11336                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11337         else if (vsi->type == I40E_VSI_VMDQ2)
11338                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11339         else {
11340                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11341                 return I40E_ERR_NO_AVAILABLE_VSI;
11342         }
11343
11344         qpnum_per_tc = used_queues / total_tc;
11345         /* Number of queues per enabled TC */
11346         if (qpnum_per_tc == 0) {
11347                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11348                 return I40E_ERR_INVALID_QP_ID;
11349         }
11350         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11351                                 I40E_MAX_Q_PER_TC);
11352         bsf = rte_bsf32(qpnum_per_tc);
11353
11354         /**
11355          * Configure TC and queue mapping parameters, for enabled TC,
11356          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11357          * default queue will serve it.
11358          */
11359         qp_idx = 0;
11360         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11361                 if (vsi->enabled_tc & (1 << i)) {
11362                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11363                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11364                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11365                         qp_idx += qpnum_per_tc;
11366                 } else
11367                         info->tc_mapping[i] = 0;
11368         }
11369
11370         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11371         if (vsi->type == I40E_VSI_SRIOV) {
11372                 info->mapping_flags |=
11373                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11374                 for (i = 0; i < vsi->nb_qps; i++)
11375                         info->queue_mapping[i] =
11376                                 rte_cpu_to_le_16(vsi->base_queue + i);
11377         } else {
11378                 info->mapping_flags |=
11379                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11380                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11381         }
11382         info->valid_sections |=
11383                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11384
11385         return I40E_SUCCESS;
11386 }
11387
11388 /*
11389  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11390  * @veb: VEB to be configured
11391  * @tc_map: enabled TC bitmap
11392  *
11393  * Returns 0 on success, negative value on failure
11394  */
11395 static enum i40e_status_code
11396 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11397 {
11398         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11399         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11400         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11401         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11402         enum i40e_status_code ret = I40E_SUCCESS;
11403         int i;
11404         uint32_t bw_max;
11405
11406         /* Check if enabled_tc is same as existing or new TCs */
11407         if (veb->enabled_tc == tc_map)
11408                 return ret;
11409
11410         /* configure tc bandwidth */
11411         memset(&veb_bw, 0, sizeof(veb_bw));
11412         veb_bw.tc_valid_bits = tc_map;
11413         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11414         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11415                 if (tc_map & BIT_ULL(i))
11416                         veb_bw.tc_bw_share_credits[i] = 1;
11417         }
11418         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11419                                                    &veb_bw, NULL);
11420         if (ret) {
11421                 PMD_INIT_LOG(ERR,
11422                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11423                         hw->aq.asq_last_status);
11424                 return ret;
11425         }
11426
11427         memset(&ets_query, 0, sizeof(ets_query));
11428         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11429                                                    &ets_query, NULL);
11430         if (ret != I40E_SUCCESS) {
11431                 PMD_DRV_LOG(ERR,
11432                         "Failed to get switch_comp ETS configuration %u",
11433                         hw->aq.asq_last_status);
11434                 return ret;
11435         }
11436         memset(&bw_query, 0, sizeof(bw_query));
11437         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11438                                                   &bw_query, NULL);
11439         if (ret != I40E_SUCCESS) {
11440                 PMD_DRV_LOG(ERR,
11441                         "Failed to get switch_comp bandwidth configuration %u",
11442                         hw->aq.asq_last_status);
11443                 return ret;
11444         }
11445
11446         /* store and print out BW info */
11447         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11448         veb->bw_info.bw_max = ets_query.tc_bw_max;
11449         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11450         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11451         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11452                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11453                      I40E_16_BIT_WIDTH);
11454         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11455                 veb->bw_info.bw_ets_share_credits[i] =
11456                                 bw_query.tc_bw_share_credits[i];
11457                 veb->bw_info.bw_ets_credits[i] =
11458                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11459                 /* 4 bits per TC, 4th bit is reserved */
11460                 veb->bw_info.bw_ets_max[i] =
11461                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11462                                   RTE_LEN2MASK(3, uint8_t));
11463                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11464                             veb->bw_info.bw_ets_share_credits[i]);
11465                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11466                             veb->bw_info.bw_ets_credits[i]);
11467                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11468                             veb->bw_info.bw_ets_max[i]);
11469         }
11470
11471         veb->enabled_tc = tc_map;
11472
11473         return ret;
11474 }
11475
11476
11477 /*
11478  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11479  * @vsi: VSI to be configured
11480  * @tc_map: enabled TC bitmap
11481  *
11482  * Returns 0 on success, negative value on failure
11483  */
11484 static enum i40e_status_code
11485 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11486 {
11487         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11488         struct i40e_vsi_context ctxt;
11489         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11490         enum i40e_status_code ret = I40E_SUCCESS;
11491         int i;
11492
11493         /* Check if enabled_tc is same as existing or new TCs */
11494         if (vsi->enabled_tc == tc_map)
11495                 return ret;
11496
11497         /* configure tc bandwidth */
11498         memset(&bw_data, 0, sizeof(bw_data));
11499         bw_data.tc_valid_bits = tc_map;
11500         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11501         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11502                 if (tc_map & BIT_ULL(i))
11503                         bw_data.tc_bw_credits[i] = 1;
11504         }
11505         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11506         if (ret) {
11507                 PMD_INIT_LOG(ERR,
11508                         "AQ command Config VSI BW allocation per TC failed = %d",
11509                         hw->aq.asq_last_status);
11510                 goto out;
11511         }
11512         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11513                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11514
11515         /* Update Queue Pairs Mapping for currently enabled UPs */
11516         ctxt.seid = vsi->seid;
11517         ctxt.pf_num = hw->pf_id;
11518         ctxt.vf_num = 0;
11519         ctxt.uplink_seid = vsi->uplink_seid;
11520         ctxt.info = vsi->info;
11521         i40e_get_cap(hw);
11522         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11523         if (ret)
11524                 goto out;
11525
11526         /* Update the VSI after updating the VSI queue-mapping information */
11527         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11528         if (ret) {
11529                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11530                         hw->aq.asq_last_status);
11531                 goto out;
11532         }
11533         /* update the local VSI info with updated queue map */
11534         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11535                                         sizeof(vsi->info.tc_mapping));
11536         rte_memcpy(&vsi->info.queue_mapping,
11537                         &ctxt.info.queue_mapping,
11538                 sizeof(vsi->info.queue_mapping));
11539         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11540         vsi->info.valid_sections = 0;
11541
11542         /* query and update current VSI BW information */
11543         ret = i40e_vsi_get_bw_config(vsi);
11544         if (ret) {
11545                 PMD_INIT_LOG(ERR,
11546                          "Failed updating vsi bw info, err %s aq_err %s",
11547                          i40e_stat_str(hw, ret),
11548                          i40e_aq_str(hw, hw->aq.asq_last_status));
11549                 goto out;
11550         }
11551
11552         vsi->enabled_tc = tc_map;
11553
11554 out:
11555         return ret;
11556 }
11557
11558 /*
11559  * i40e_dcb_hw_configure - program the dcb setting to hw
11560  * @pf: pf the configuration is taken on
11561  * @new_cfg: new configuration
11562  * @tc_map: enabled TC bitmap
11563  *
11564  * Returns 0 on success, negative value on failure
11565  */
11566 static enum i40e_status_code
11567 i40e_dcb_hw_configure(struct i40e_pf *pf,
11568                       struct i40e_dcbx_config *new_cfg,
11569                       uint8_t tc_map)
11570 {
11571         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11572         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11573         struct i40e_vsi *main_vsi = pf->main_vsi;
11574         struct i40e_vsi_list *vsi_list;
11575         enum i40e_status_code ret;
11576         int i;
11577         uint32_t val;
11578
11579         /* Use the FW API if FW > v4.4*/
11580         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11581               (hw->aq.fw_maj_ver >= 5))) {
11582                 PMD_INIT_LOG(ERR,
11583                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11584                 return I40E_ERR_FIRMWARE_API_VERSION;
11585         }
11586
11587         /* Check if need reconfiguration */
11588         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11589                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11590                 return I40E_SUCCESS;
11591         }
11592
11593         /* Copy the new config to the current config */
11594         *old_cfg = *new_cfg;
11595         old_cfg->etsrec = old_cfg->etscfg;
11596         ret = i40e_set_dcb_config(hw);
11597         if (ret) {
11598                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11599                          i40e_stat_str(hw, ret),
11600                          i40e_aq_str(hw, hw->aq.asq_last_status));
11601                 return ret;
11602         }
11603         /* set receive Arbiter to RR mode and ETS scheme by default */
11604         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11605                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11606                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11607                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11608                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11609                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11610                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11611                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11612                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11613                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11614                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11615                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11616                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11617         }
11618         /* get local mib to check whether it is configured correctly */
11619         /* IEEE mode */
11620         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11621         /* Get Local DCB Config */
11622         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11623                                      &hw->local_dcbx_config);
11624
11625         /* if Veb is created, need to update TC of it at first */
11626         if (main_vsi->veb) {
11627                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11628                 if (ret)
11629                         PMD_INIT_LOG(WARNING,
11630                                  "Failed configuring TC for VEB seid=%d",
11631                                  main_vsi->veb->seid);
11632         }
11633         /* Update each VSI */
11634         i40e_vsi_config_tc(main_vsi, tc_map);
11635         if (main_vsi->veb) {
11636                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11637                         /* Beside main VSI and VMDQ VSIs, only enable default
11638                          * TC for other VSIs
11639                          */
11640                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11641                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11642                                                          tc_map);
11643                         else
11644                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11645                                                          I40E_DEFAULT_TCMAP);
11646                         if (ret)
11647                                 PMD_INIT_LOG(WARNING,
11648                                         "Failed configuring TC for VSI seid=%d",
11649                                         vsi_list->vsi->seid);
11650                         /* continue */
11651                 }
11652         }
11653         return I40E_SUCCESS;
11654 }
11655
11656 /*
11657  * i40e_dcb_init_configure - initial dcb config
11658  * @dev: device being configured
11659  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11660  *
11661  * Returns 0 on success, negative value on failure
11662  */
11663 int
11664 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11665 {
11666         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11667         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11668         int i, ret = 0;
11669
11670         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11671                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11672                 return -ENOTSUP;
11673         }
11674
11675         /* DCB initialization:
11676          * Update DCB configuration from the Firmware and configure
11677          * LLDP MIB change event.
11678          */
11679         if (sw_dcb == TRUE) {
11680                 /* Stopping lldp is necessary for DPDK, but it will cause
11681                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11682                  * for successful initialization of DCB is that LLDP is
11683                  * enabled. So it is needed to start lldp before DCB init
11684                  * and stop it after initialization.
11685                  */
11686                 ret = i40e_aq_start_lldp(hw, true, NULL);
11687                 if (ret != I40E_SUCCESS)
11688                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11689
11690                 ret = i40e_init_dcb(hw, true);
11691                 /* If lldp agent is stopped, the return value from
11692                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11693                  * adminq status. Otherwise, it should return success.
11694                  */
11695                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11696                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11697                         memset(&hw->local_dcbx_config, 0,
11698                                 sizeof(struct i40e_dcbx_config));
11699                         /* set dcb default configuration */
11700                         hw->local_dcbx_config.etscfg.willing = 0;
11701                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11702                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11703                         hw->local_dcbx_config.etscfg.tsatable[0] =
11704                                                 I40E_IEEE_TSA_ETS;
11705                         /* all UPs mapping to TC0 */
11706                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11707                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11708                         hw->local_dcbx_config.etsrec =
11709                                 hw->local_dcbx_config.etscfg;
11710                         hw->local_dcbx_config.pfc.willing = 0;
11711                         hw->local_dcbx_config.pfc.pfccap =
11712                                                 I40E_MAX_TRAFFIC_CLASS;
11713                         /* FW needs one App to configure HW */
11714                         hw->local_dcbx_config.numapps = 1;
11715                         hw->local_dcbx_config.app[0].selector =
11716                                                 I40E_APP_SEL_ETHTYPE;
11717                         hw->local_dcbx_config.app[0].priority = 3;
11718                         hw->local_dcbx_config.app[0].protocolid =
11719                                                 I40E_APP_PROTOID_FCOE;
11720                         ret = i40e_set_dcb_config(hw);
11721                         if (ret) {
11722                                 PMD_INIT_LOG(ERR,
11723                                         "default dcb config fails. err = %d, aq_err = %d.",
11724                                         ret, hw->aq.asq_last_status);
11725                                 return -ENOSYS;
11726                         }
11727                 } else {
11728                         PMD_INIT_LOG(ERR,
11729                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11730                                 ret, hw->aq.asq_last_status);
11731                         return -ENOTSUP;
11732                 }
11733
11734                 if (i40e_need_stop_lldp(dev)) {
11735                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11736                         if (ret != I40E_SUCCESS)
11737                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11738                 }
11739         } else {
11740                 ret = i40e_aq_start_lldp(hw, true, NULL);
11741                 if (ret != I40E_SUCCESS)
11742                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11743
11744                 ret = i40e_init_dcb(hw, true);
11745                 if (!ret) {
11746                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11747                                 PMD_INIT_LOG(ERR,
11748                                         "HW doesn't support DCBX offload.");
11749                                 return -ENOTSUP;
11750                         }
11751                 } else {
11752                         PMD_INIT_LOG(ERR,
11753                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11754                                 ret, hw->aq.asq_last_status);
11755                         return -ENOTSUP;
11756                 }
11757         }
11758         return 0;
11759 }
11760
11761 /*
11762  * i40e_dcb_setup - setup dcb related config
11763  * @dev: device being configured
11764  *
11765  * Returns 0 on success, negative value on failure
11766  */
11767 static int
11768 i40e_dcb_setup(struct rte_eth_dev *dev)
11769 {
11770         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11771         struct i40e_dcbx_config dcb_cfg;
11772         uint8_t tc_map = 0;
11773         int ret = 0;
11774
11775         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11776                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11777                 return -ENOTSUP;
11778         }
11779
11780         if (pf->vf_num != 0)
11781                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11782
11783         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11784         if (ret) {
11785                 PMD_INIT_LOG(ERR, "invalid dcb config");
11786                 return -EINVAL;
11787         }
11788         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11789         if (ret) {
11790                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11791                 return -ENOSYS;
11792         }
11793
11794         return 0;
11795 }
11796
11797 static int
11798 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11799                       struct rte_eth_dcb_info *dcb_info)
11800 {
11801         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11802         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11803         struct i40e_vsi *vsi = pf->main_vsi;
11804         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11805         uint16_t bsf, tc_mapping;
11806         int i, j = 0;
11807
11808         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11809                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11810         else
11811                 dcb_info->nb_tcs = 1;
11812         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11813                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11814         for (i = 0; i < dcb_info->nb_tcs; i++)
11815                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11816
11817         /* get queue mapping if vmdq is disabled */
11818         if (!pf->nb_cfg_vmdq_vsi) {
11819                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11820                         if (!(vsi->enabled_tc & (1 << i)))
11821                                 continue;
11822                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11823                         dcb_info->tc_queue.tc_rxq[j][i].base =
11824                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11825                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11826                         dcb_info->tc_queue.tc_txq[j][i].base =
11827                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11828                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11829                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11830                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11831                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11832                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11833                 }
11834                 return 0;
11835         }
11836
11837         /* get queue mapping if vmdq is enabled */
11838         do {
11839                 vsi = pf->vmdq[j].vsi;
11840                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11841                         if (!(vsi->enabled_tc & (1 << i)))
11842                                 continue;
11843                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11844                         dcb_info->tc_queue.tc_rxq[j][i].base =
11845                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11846                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11847                         dcb_info->tc_queue.tc_txq[j][i].base =
11848                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11849                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11850                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11851                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11852                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11853                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11854                 }
11855                 j++;
11856         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11857         return 0;
11858 }
11859
11860 static int
11861 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11862 {
11863         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11864         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11865         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11866         uint16_t msix_intr;
11867
11868         msix_intr = intr_handle->intr_vec[queue_id];
11869         if (msix_intr == I40E_MISC_VEC_ID)
11870                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11871                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11872                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11873                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11874         else
11875                 I40E_WRITE_REG(hw,
11876                                I40E_PFINT_DYN_CTLN(msix_intr -
11877                                                    I40E_RX_VEC_START),
11878                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11879                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11880                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11881
11882         I40E_WRITE_FLUSH(hw);
11883         rte_intr_ack(&pci_dev->intr_handle);
11884
11885         return 0;
11886 }
11887
11888 static int
11889 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11890 {
11891         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11892         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11893         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11894         uint16_t msix_intr;
11895
11896         msix_intr = intr_handle->intr_vec[queue_id];
11897         if (msix_intr == I40E_MISC_VEC_ID)
11898                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11899                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11900         else
11901                 I40E_WRITE_REG(hw,
11902                                I40E_PFINT_DYN_CTLN(msix_intr -
11903                                                    I40E_RX_VEC_START),
11904                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11905         I40E_WRITE_FLUSH(hw);
11906
11907         return 0;
11908 }
11909
11910 /**
11911  * This function is used to check if the register is valid.
11912  * Below is the valid registers list for X722 only:
11913  * 0x2b800--0x2bb00
11914  * 0x38700--0x38a00
11915  * 0x3d800--0x3db00
11916  * 0x208e00--0x209000
11917  * 0x20be00--0x20c000
11918  * 0x263c00--0x264000
11919  * 0x265c00--0x266000
11920  */
11921 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11922 {
11923         if ((type != I40E_MAC_X722) &&
11924             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11925              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11926              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11927              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11928              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11929              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11930              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11931                 return 0;
11932         else
11933                 return 1;
11934 }
11935
11936 static int i40e_get_regs(struct rte_eth_dev *dev,
11937                          struct rte_dev_reg_info *regs)
11938 {
11939         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11940         uint32_t *ptr_data = regs->data;
11941         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11942         const struct i40e_reg_info *reg_info;
11943
11944         if (ptr_data == NULL) {
11945                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11946                 regs->width = sizeof(uint32_t);
11947                 return 0;
11948         }
11949
11950         /* The first few registers have to be read using AQ operations */
11951         reg_idx = 0;
11952         while (i40e_regs_adminq[reg_idx].name) {
11953                 reg_info = &i40e_regs_adminq[reg_idx++];
11954                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11955                         for (arr_idx2 = 0;
11956                                         arr_idx2 <= reg_info->count2;
11957                                         arr_idx2++) {
11958                                 reg_offset = arr_idx * reg_info->stride1 +
11959                                         arr_idx2 * reg_info->stride2;
11960                                 reg_offset += reg_info->base_addr;
11961                                 ptr_data[reg_offset >> 2] =
11962                                         i40e_read_rx_ctl(hw, reg_offset);
11963                         }
11964         }
11965
11966         /* The remaining registers can be read using primitives */
11967         reg_idx = 0;
11968         while (i40e_regs_others[reg_idx].name) {
11969                 reg_info = &i40e_regs_others[reg_idx++];
11970                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11971                         for (arr_idx2 = 0;
11972                                         arr_idx2 <= reg_info->count2;
11973                                         arr_idx2++) {
11974                                 reg_offset = arr_idx * reg_info->stride1 +
11975                                         arr_idx2 * reg_info->stride2;
11976                                 reg_offset += reg_info->base_addr;
11977                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11978                                         ptr_data[reg_offset >> 2] = 0;
11979                                 else
11980                                         ptr_data[reg_offset >> 2] =
11981                                                 I40E_READ_REG(hw, reg_offset);
11982                         }
11983         }
11984
11985         return 0;
11986 }
11987
11988 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11989 {
11990         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11991
11992         /* Convert word count to byte count */
11993         return hw->nvm.sr_size << 1;
11994 }
11995
11996 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11997                            struct rte_dev_eeprom_info *eeprom)
11998 {
11999         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12000         uint16_t *data = eeprom->data;
12001         uint16_t offset, length, cnt_words;
12002         int ret_code;
12003
12004         offset = eeprom->offset >> 1;
12005         length = eeprom->length >> 1;
12006         cnt_words = length;
12007
12008         if (offset > hw->nvm.sr_size ||
12009                 offset + length > hw->nvm.sr_size) {
12010                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12011                 return -EINVAL;
12012         }
12013
12014         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12015
12016         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12017         if (ret_code != I40E_SUCCESS || cnt_words != length) {
12018                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12019                 return -EIO;
12020         }
12021
12022         return 0;
12023 }
12024
12025 static int i40e_get_module_info(struct rte_eth_dev *dev,
12026                                 struct rte_eth_dev_module_info *modinfo)
12027 {
12028         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12029         uint32_t sff8472_comp = 0;
12030         uint32_t sff8472_swap = 0;
12031         uint32_t sff8636_rev = 0;
12032         i40e_status status;
12033         uint32_t type = 0;
12034
12035         /* Check if firmware supports reading module EEPROM. */
12036         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12037                 PMD_DRV_LOG(ERR,
12038                             "Module EEPROM memory read not supported. "
12039                             "Please update the NVM image.\n");
12040                 return -EINVAL;
12041         }
12042
12043         status = i40e_update_link_info(hw);
12044         if (status)
12045                 return -EIO;
12046
12047         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12048                 PMD_DRV_LOG(ERR,
12049                             "Cannot read module EEPROM memory. "
12050                             "No module connected.\n");
12051                 return -EINVAL;
12052         }
12053
12054         type = hw->phy.link_info.module_type[0];
12055
12056         switch (type) {
12057         case I40E_MODULE_TYPE_SFP:
12058                 status = i40e_aq_get_phy_register(hw,
12059                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12060                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12061                                 I40E_MODULE_SFF_8472_COMP,
12062                                 &sff8472_comp, NULL);
12063                 if (status)
12064                         return -EIO;
12065
12066                 status = i40e_aq_get_phy_register(hw,
12067                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12068                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12069                                 I40E_MODULE_SFF_8472_SWAP,
12070                                 &sff8472_swap, NULL);
12071                 if (status)
12072                         return -EIO;
12073
12074                 /* Check if the module requires address swap to access
12075                  * the other EEPROM memory page.
12076                  */
12077                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12078                         PMD_DRV_LOG(WARNING,
12079                                     "Module address swap to access "
12080                                     "page 0xA2 is not supported.\n");
12081                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12082                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12083                 } else if (sff8472_comp == 0x00) {
12084                         /* Module is not SFF-8472 compliant */
12085                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12086                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12087                 } else {
12088                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
12089                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12090                 }
12091                 break;
12092         case I40E_MODULE_TYPE_QSFP_PLUS:
12093                 /* Read from memory page 0. */
12094                 status = i40e_aq_get_phy_register(hw,
12095                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12096                                 0, 1,
12097                                 I40E_MODULE_REVISION_ADDR,
12098                                 &sff8636_rev, NULL);
12099                 if (status)
12100                         return -EIO;
12101                 /* Determine revision compliance byte */
12102                 if (sff8636_rev > 0x02) {
12103                         /* Module is SFF-8636 compliant */
12104                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
12105                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12106                 } else {
12107                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
12108                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12109                 }
12110                 break;
12111         case I40E_MODULE_TYPE_QSFP28:
12112                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12113                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12114                 break;
12115         default:
12116                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12117                 return -EINVAL;
12118         }
12119         return 0;
12120 }
12121
12122 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12123                                   struct rte_dev_eeprom_info *info)
12124 {
12125         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12126         bool is_sfp = false;
12127         i40e_status status;
12128         uint8_t *data;
12129         uint32_t value = 0;
12130         uint32_t i;
12131
12132         if (!info || !info->length || !info->data)
12133                 return -EINVAL;
12134
12135         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12136                 is_sfp = true;
12137
12138         data = info->data;
12139         for (i = 0; i < info->length; i++) {
12140                 u32 offset = i + info->offset;
12141                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12142
12143                 /* Check if we need to access the other memory page */
12144                 if (is_sfp) {
12145                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12146                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12147                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12148                         }
12149                 } else {
12150                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12151                                 /* Compute memory page number and offset. */
12152                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12153                                 addr++;
12154                         }
12155                 }
12156                 status = i40e_aq_get_phy_register(hw,
12157                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12158                                 addr, offset, 1, &value, NULL);
12159                 if (status)
12160                         return -EIO;
12161                 data[i] = (uint8_t)value;
12162         }
12163         return 0;
12164 }
12165
12166 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12167                                      struct rte_ether_addr *mac_addr)
12168 {
12169         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12170         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12171         struct i40e_vsi *vsi = pf->main_vsi;
12172         struct i40e_mac_filter_info mac_filter;
12173         struct i40e_mac_filter *f;
12174         int ret;
12175
12176         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12177                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12178                 return -EINVAL;
12179         }
12180
12181         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12182                 if (rte_is_same_ether_addr(&pf->dev_addr,
12183                                                 &f->mac_info.mac_addr))
12184                         break;
12185         }
12186
12187         if (f == NULL) {
12188                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12189                 return -EIO;
12190         }
12191
12192         mac_filter = f->mac_info;
12193         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12194         if (ret != I40E_SUCCESS) {
12195                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12196                 return -EIO;
12197         }
12198         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12199         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12200         if (ret != I40E_SUCCESS) {
12201                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12202                 return -EIO;
12203         }
12204         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12205
12206         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12207                                         mac_addr->addr_bytes, NULL);
12208         if (ret != I40E_SUCCESS) {
12209                 PMD_DRV_LOG(ERR, "Failed to change mac");
12210                 return -EIO;
12211         }
12212
12213         return 0;
12214 }
12215
12216 static int
12217 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12218 {
12219         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12220         struct rte_eth_dev_data *dev_data = pf->dev_data;
12221         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12222         int ret = 0;
12223
12224         /* check if mtu is within the allowed range */
12225         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12226                 return -EINVAL;
12227
12228         /* mtu setting is forbidden if port is start */
12229         if (dev_data->dev_started) {
12230                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12231                             dev_data->port_id);
12232                 return -EBUSY;
12233         }
12234
12235         if (frame_size > RTE_ETHER_MAX_LEN)
12236                 dev_data->dev_conf.rxmode.offloads |=
12237                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12238         else
12239                 dev_data->dev_conf.rxmode.offloads &=
12240                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12241
12242         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12243
12244         return ret;
12245 }
12246
12247 /* Restore ethertype filter */
12248 static void
12249 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12250 {
12251         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12252         struct i40e_ethertype_filter_list
12253                 *ethertype_list = &pf->ethertype.ethertype_list;
12254         struct i40e_ethertype_filter *f;
12255         struct i40e_control_filter_stats stats;
12256         uint16_t flags;
12257
12258         TAILQ_FOREACH(f, ethertype_list, rules) {
12259                 flags = 0;
12260                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12261                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12262                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12263                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12264                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12265
12266                 memset(&stats, 0, sizeof(stats));
12267                 i40e_aq_add_rem_control_packet_filter(hw,
12268                                             f->input.mac_addr.addr_bytes,
12269                                             f->input.ether_type,
12270                                             flags, pf->main_vsi->seid,
12271                                             f->queue, 1, &stats, NULL);
12272         }
12273         PMD_DRV_LOG(INFO, "Ethertype filter:"
12274                     " mac_etype_used = %u, etype_used = %u,"
12275                     " mac_etype_free = %u, etype_free = %u",
12276                     stats.mac_etype_used, stats.etype_used,
12277                     stats.mac_etype_free, stats.etype_free);
12278 }
12279
12280 /* Restore tunnel filter */
12281 static void
12282 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12283 {
12284         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12285         struct i40e_vsi *vsi;
12286         struct i40e_pf_vf *vf;
12287         struct i40e_tunnel_filter_list
12288                 *tunnel_list = &pf->tunnel.tunnel_list;
12289         struct i40e_tunnel_filter *f;
12290         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12291         bool big_buffer = 0;
12292
12293         TAILQ_FOREACH(f, tunnel_list, rules) {
12294                 if (!f->is_to_vf)
12295                         vsi = pf->main_vsi;
12296                 else {
12297                         vf = &pf->vfs[f->vf_id];
12298                         vsi = vf->vsi;
12299                 }
12300                 memset(&cld_filter, 0, sizeof(cld_filter));
12301                 rte_ether_addr_copy((struct rte_ether_addr *)
12302                                 &f->input.outer_mac,
12303                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12304                 rte_ether_addr_copy((struct rte_ether_addr *)
12305                                 &f->input.inner_mac,
12306                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12307                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12308                 cld_filter.element.flags = f->input.flags;
12309                 cld_filter.element.tenant_id = f->input.tenant_id;
12310                 cld_filter.element.queue_number = f->queue;
12311                 rte_memcpy(cld_filter.general_fields,
12312                            f->input.general_fields,
12313                            sizeof(f->input.general_fields));
12314
12315                 if (((f->input.flags &
12316                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12317                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12318                     ((f->input.flags &
12319                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12320                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12321                     ((f->input.flags &
12322                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12323                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12324                         big_buffer = 1;
12325
12326                 if (big_buffer)
12327                         i40e_aq_add_cloud_filters_bb(hw,
12328                                         vsi->seid, &cld_filter, 1);
12329                 else
12330                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12331                                                   &cld_filter.element, 1);
12332         }
12333 }
12334
12335 /* Restore RSS filter */
12336 static inline void
12337 i40e_rss_filter_restore(struct i40e_pf *pf)
12338 {
12339         struct i40e_rss_conf_list *list = &pf->rss_config_list;
12340         struct i40e_rss_filter *filter;
12341
12342         TAILQ_FOREACH(filter, list, next) {
12343                 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12344         }
12345 }
12346
12347 static void
12348 i40e_filter_restore(struct i40e_pf *pf)
12349 {
12350         i40e_ethertype_filter_restore(pf);
12351         i40e_tunnel_filter_restore(pf);
12352         i40e_fdir_filter_restore(pf);
12353         i40e_rss_filter_restore(pf);
12354 }
12355
12356 bool
12357 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12358 {
12359         if (strcmp(dev->device->driver->name, drv->driver.name))
12360                 return false;
12361
12362         return true;
12363 }
12364
12365 bool
12366 is_i40e_supported(struct rte_eth_dev *dev)
12367 {
12368         return is_device_supported(dev, &rte_i40e_pmd);
12369 }
12370
12371 struct i40e_customized_pctype*
12372 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12373 {
12374         int i;
12375
12376         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12377                 if (pf->customized_pctype[i].index == index)
12378                         return &pf->customized_pctype[i];
12379         }
12380         return NULL;
12381 }
12382
12383 static int
12384 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12385                               uint32_t pkg_size, uint32_t proto_num,
12386                               struct rte_pmd_i40e_proto_info *proto,
12387                               enum rte_pmd_i40e_package_op op)
12388 {
12389         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12390         uint32_t pctype_num;
12391         struct rte_pmd_i40e_ptype_info *pctype;
12392         uint32_t buff_size;
12393         struct i40e_customized_pctype *new_pctype = NULL;
12394         uint8_t proto_id;
12395         uint8_t pctype_value;
12396         char name[64];
12397         uint32_t i, j, n;
12398         int ret;
12399
12400         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12401             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12402                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12403                 return -1;
12404         }
12405
12406         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12407                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12408                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12409         if (ret) {
12410                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12411                 return -1;
12412         }
12413         if (!pctype_num) {
12414                 PMD_DRV_LOG(INFO, "No new pctype added");
12415                 return -1;
12416         }
12417
12418         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12419         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12420         if (!pctype) {
12421                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12422                 return -1;
12423         }
12424         /* get information about new pctype list */
12425         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12426                                         (uint8_t *)pctype, buff_size,
12427                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12428         if (ret) {
12429                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12430                 rte_free(pctype);
12431                 return -1;
12432         }
12433
12434         /* Update customized pctype. */
12435         for (i = 0; i < pctype_num; i++) {
12436                 pctype_value = pctype[i].ptype_id;
12437                 memset(name, 0, sizeof(name));
12438                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12439                         proto_id = pctype[i].protocols[j];
12440                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12441                                 continue;
12442                         for (n = 0; n < proto_num; n++) {
12443                                 if (proto[n].proto_id != proto_id)
12444                                         continue;
12445                                 strlcat(name, proto[n].name, sizeof(name));
12446                                 strlcat(name, "_", sizeof(name));
12447                                 break;
12448                         }
12449                 }
12450                 name[strlen(name) - 1] = '\0';
12451                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12452                 if (!strcmp(name, "GTPC"))
12453                         new_pctype =
12454                                 i40e_find_customized_pctype(pf,
12455                                                       I40E_CUSTOMIZED_GTPC);
12456                 else if (!strcmp(name, "GTPU_IPV4"))
12457                         new_pctype =
12458                                 i40e_find_customized_pctype(pf,
12459                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12460                 else if (!strcmp(name, "GTPU_IPV6"))
12461                         new_pctype =
12462                                 i40e_find_customized_pctype(pf,
12463                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12464                 else if (!strcmp(name, "GTPU"))
12465                         new_pctype =
12466                                 i40e_find_customized_pctype(pf,
12467                                                       I40E_CUSTOMIZED_GTPU);
12468                 else if (!strcmp(name, "IPV4_L2TPV3"))
12469                         new_pctype =
12470                                 i40e_find_customized_pctype(pf,
12471                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12472                 else if (!strcmp(name, "IPV6_L2TPV3"))
12473                         new_pctype =
12474                                 i40e_find_customized_pctype(pf,
12475                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12476                 else if (!strcmp(name, "IPV4_ESP"))
12477                         new_pctype =
12478                                 i40e_find_customized_pctype(pf,
12479                                                 I40E_CUSTOMIZED_ESP_IPV4);
12480                 else if (!strcmp(name, "IPV6_ESP"))
12481                         new_pctype =
12482                                 i40e_find_customized_pctype(pf,
12483                                                 I40E_CUSTOMIZED_ESP_IPV6);
12484                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12485                         new_pctype =
12486                                 i40e_find_customized_pctype(pf,
12487                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12488                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12489                         new_pctype =
12490                                 i40e_find_customized_pctype(pf,
12491                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12492                 else if (!strcmp(name, "IPV4_AH"))
12493                         new_pctype =
12494                                 i40e_find_customized_pctype(pf,
12495                                                 I40E_CUSTOMIZED_AH_IPV4);
12496                 else if (!strcmp(name, "IPV6_AH"))
12497                         new_pctype =
12498                                 i40e_find_customized_pctype(pf,
12499                                                 I40E_CUSTOMIZED_AH_IPV6);
12500                 if (new_pctype) {
12501                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12502                                 new_pctype->pctype = pctype_value;
12503                                 new_pctype->valid = true;
12504                         } else {
12505                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12506                                 new_pctype->valid = false;
12507                         }
12508                 }
12509         }
12510
12511         rte_free(pctype);
12512         return 0;
12513 }
12514
12515 static int
12516 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12517                              uint32_t pkg_size, uint32_t proto_num,
12518                              struct rte_pmd_i40e_proto_info *proto,
12519                              enum rte_pmd_i40e_package_op op)
12520 {
12521         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12522         uint16_t port_id = dev->data->port_id;
12523         uint32_t ptype_num;
12524         struct rte_pmd_i40e_ptype_info *ptype;
12525         uint32_t buff_size;
12526         uint8_t proto_id;
12527         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12528         uint32_t i, j, n;
12529         bool in_tunnel;
12530         int ret;
12531
12532         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12533             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12534                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12535                 return -1;
12536         }
12537
12538         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12539                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12540                 return 0;
12541         }
12542
12543         /* get information about new ptype num */
12544         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12545                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12546                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12547         if (ret) {
12548                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12549                 return ret;
12550         }
12551         if (!ptype_num) {
12552                 PMD_DRV_LOG(INFO, "No new ptype added");
12553                 return -1;
12554         }
12555
12556         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12557         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12558         if (!ptype) {
12559                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12560                 return -1;
12561         }
12562
12563         /* get information about new ptype list */
12564         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12565                                         (uint8_t *)ptype, buff_size,
12566                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12567         if (ret) {
12568                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12569                 rte_free(ptype);
12570                 return ret;
12571         }
12572
12573         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12574         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12575         if (!ptype_mapping) {
12576                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12577                 rte_free(ptype);
12578                 return -1;
12579         }
12580
12581         /* Update ptype mapping table. */
12582         for (i = 0; i < ptype_num; i++) {
12583                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12584                 ptype_mapping[i].sw_ptype = 0;
12585                 in_tunnel = false;
12586                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12587                         proto_id = ptype[i].protocols[j];
12588                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12589                                 continue;
12590                         for (n = 0; n < proto_num; n++) {
12591                                 if (proto[n].proto_id != proto_id)
12592                                         continue;
12593                                 memset(name, 0, sizeof(name));
12594                                 strcpy(name, proto[n].name);
12595                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12596                                 if (!strncasecmp(name, "PPPOE", 5))
12597                                         ptype_mapping[i].sw_ptype |=
12598                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12599                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12600                                          !in_tunnel) {
12601                                         ptype_mapping[i].sw_ptype |=
12602                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12603                                         ptype_mapping[i].sw_ptype |=
12604                                                 RTE_PTYPE_L4_FRAG;
12605                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12606                                            in_tunnel) {
12607                                         ptype_mapping[i].sw_ptype |=
12608                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12609                                         ptype_mapping[i].sw_ptype |=
12610                                                 RTE_PTYPE_INNER_L4_FRAG;
12611                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12612                                         ptype_mapping[i].sw_ptype |=
12613                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12614                                         in_tunnel = true;
12615                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12616                                            !in_tunnel)
12617                                         ptype_mapping[i].sw_ptype |=
12618                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12619                                 else if (!strncasecmp(name, "IPV4", 4) &&
12620                                          in_tunnel)
12621                                         ptype_mapping[i].sw_ptype |=
12622                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12623                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12624                                          !in_tunnel) {
12625                                         ptype_mapping[i].sw_ptype |=
12626                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12627                                         ptype_mapping[i].sw_ptype |=
12628                                                 RTE_PTYPE_L4_FRAG;
12629                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12630                                            in_tunnel) {
12631                                         ptype_mapping[i].sw_ptype |=
12632                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12633                                         ptype_mapping[i].sw_ptype |=
12634                                                 RTE_PTYPE_INNER_L4_FRAG;
12635                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12636                                         ptype_mapping[i].sw_ptype |=
12637                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12638                                         in_tunnel = true;
12639                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12640                                            !in_tunnel)
12641                                         ptype_mapping[i].sw_ptype |=
12642                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12643                                 else if (!strncasecmp(name, "IPV6", 4) &&
12644                                          in_tunnel)
12645                                         ptype_mapping[i].sw_ptype |=
12646                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12647                                 else if (!strncasecmp(name, "UDP", 3) &&
12648                                          !in_tunnel)
12649                                         ptype_mapping[i].sw_ptype |=
12650                                                 RTE_PTYPE_L4_UDP;
12651                                 else if (!strncasecmp(name, "UDP", 3) &&
12652                                          in_tunnel)
12653                                         ptype_mapping[i].sw_ptype |=
12654                                                 RTE_PTYPE_INNER_L4_UDP;
12655                                 else if (!strncasecmp(name, "TCP", 3) &&
12656                                          !in_tunnel)
12657                                         ptype_mapping[i].sw_ptype |=
12658                                                 RTE_PTYPE_L4_TCP;
12659                                 else if (!strncasecmp(name, "TCP", 3) &&
12660                                          in_tunnel)
12661                                         ptype_mapping[i].sw_ptype |=
12662                                                 RTE_PTYPE_INNER_L4_TCP;
12663                                 else if (!strncasecmp(name, "SCTP", 4) &&
12664                                          !in_tunnel)
12665                                         ptype_mapping[i].sw_ptype |=
12666                                                 RTE_PTYPE_L4_SCTP;
12667                                 else if (!strncasecmp(name, "SCTP", 4) &&
12668                                          in_tunnel)
12669                                         ptype_mapping[i].sw_ptype |=
12670                                                 RTE_PTYPE_INNER_L4_SCTP;
12671                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12672                                           !strncasecmp(name, "ICMPV6", 6)) &&
12673                                          !in_tunnel)
12674                                         ptype_mapping[i].sw_ptype |=
12675                                                 RTE_PTYPE_L4_ICMP;
12676                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12677                                           !strncasecmp(name, "ICMPV6", 6)) &&
12678                                          in_tunnel)
12679                                         ptype_mapping[i].sw_ptype |=
12680                                                 RTE_PTYPE_INNER_L4_ICMP;
12681                                 else if (!strncasecmp(name, "GTPC", 4)) {
12682                                         ptype_mapping[i].sw_ptype |=
12683                                                 RTE_PTYPE_TUNNEL_GTPC;
12684                                         in_tunnel = true;
12685                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12686                                         ptype_mapping[i].sw_ptype |=
12687                                                 RTE_PTYPE_TUNNEL_GTPU;
12688                                         in_tunnel = true;
12689                                 } else if (!strncasecmp(name, "ESP", 3)) {
12690                                         ptype_mapping[i].sw_ptype |=
12691                                                 RTE_PTYPE_TUNNEL_ESP;
12692                                         in_tunnel = true;
12693                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12694                                         ptype_mapping[i].sw_ptype |=
12695                                                 RTE_PTYPE_TUNNEL_GRENAT;
12696                                         in_tunnel = true;
12697                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12698                                            !strncasecmp(name, "L2TPV2", 6) ||
12699                                            !strncasecmp(name, "L2TPV3", 6)) {
12700                                         ptype_mapping[i].sw_ptype |=
12701                                                 RTE_PTYPE_TUNNEL_L2TP;
12702                                         in_tunnel = true;
12703                                 }
12704
12705                                 break;
12706                         }
12707                 }
12708         }
12709
12710         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12711                                                 ptype_num, 0);
12712         if (ret)
12713                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12714
12715         rte_free(ptype_mapping);
12716         rte_free(ptype);
12717         return ret;
12718 }
12719
12720 void
12721 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12722                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12723 {
12724         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12725         uint32_t proto_num;
12726         struct rte_pmd_i40e_proto_info *proto;
12727         uint32_t buff_size;
12728         uint32_t i;
12729         int ret;
12730
12731         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12732             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12733                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12734                 return;
12735         }
12736
12737         /* get information about protocol number */
12738         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12739                                        (uint8_t *)&proto_num, sizeof(proto_num),
12740                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12741         if (ret) {
12742                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12743                 return;
12744         }
12745         if (!proto_num) {
12746                 PMD_DRV_LOG(INFO, "No new protocol added");
12747                 return;
12748         }
12749
12750         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12751         proto = rte_zmalloc("new_proto", buff_size, 0);
12752         if (!proto) {
12753                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12754                 return;
12755         }
12756
12757         /* get information about protocol list */
12758         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12759                                         (uint8_t *)proto, buff_size,
12760                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12761         if (ret) {
12762                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12763                 rte_free(proto);
12764                 return;
12765         }
12766
12767         /* Check if GTP is supported. */
12768         for (i = 0; i < proto_num; i++) {
12769                 if (!strncmp(proto[i].name, "GTP", 3)) {
12770                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12771                                 pf->gtp_support = true;
12772                         else
12773                                 pf->gtp_support = false;
12774                         break;
12775                 }
12776         }
12777
12778         /* Check if ESP is supported. */
12779         for (i = 0; i < proto_num; i++) {
12780                 if (!strncmp(proto[i].name, "ESP", 3)) {
12781                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12782                                 pf->esp_support = true;
12783                         else
12784                                 pf->esp_support = false;
12785                         break;
12786                 }
12787         }
12788
12789         /* Update customized pctype info */
12790         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12791                                             proto_num, proto, op);
12792         if (ret)
12793                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12794
12795         /* Update customized ptype info */
12796         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12797                                            proto_num, proto, op);
12798         if (ret)
12799                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12800
12801         rte_free(proto);
12802 }
12803
12804 /* Create a QinQ cloud filter
12805  *
12806  * The Fortville NIC has limited resources for tunnel filters,
12807  * so we can only reuse existing filters.
12808  *
12809  * In step 1 we define which Field Vector fields can be used for
12810  * filter types.
12811  * As we do not have the inner tag defined as a field,
12812  * we have to define it first, by reusing one of L1 entries.
12813  *
12814  * In step 2 we are replacing one of existing filter types with
12815  * a new one for QinQ.
12816  * As we reusing L1 and replacing L2, some of the default filter
12817  * types will disappear,which depends on L1 and L2 entries we reuse.
12818  *
12819  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12820  *
12821  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12822  *              later when we define the cloud filter.
12823  *      a.      Valid_flags.replace_cloud = 0
12824  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12825  *      c.      New_filter = 0x10
12826  *      d.      TR bit = 0xff (optional, not used here)
12827  *      e.      Buffer – 2 entries:
12828  *              i.      Byte 0 = 8 (outer vlan FV index).
12829  *                      Byte 1 = 0 (rsv)
12830  *                      Byte 2-3 = 0x0fff
12831  *              ii.     Byte 0 = 37 (inner vlan FV index).
12832  *                      Byte 1 =0 (rsv)
12833  *                      Byte 2-3 = 0x0fff
12834  *
12835  * Step 2:
12836  * 2.   Create cloud filter using two L1 filters entries: stag and
12837  *              new filter(outer vlan+ inner vlan)
12838  *      a.      Valid_flags.replace_cloud = 1
12839  *      b.      Old_filter = 1 (instead of outer IP)
12840  *      c.      New_filter = 0x10
12841  *      d.      Buffer – 2 entries:
12842  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12843  *                      Byte 1-3 = 0 (rsv)
12844  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12845  *                      Byte 9-11 = 0 (rsv)
12846  */
12847 static int
12848 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12849 {
12850         int ret = -ENOTSUP;
12851         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12852         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12853         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12854         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12855
12856         if (pf->support_multi_driver) {
12857                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12858                 return ret;
12859         }
12860
12861         /* Init */
12862         memset(&filter_replace, 0,
12863                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12864         memset(&filter_replace_buf, 0,
12865                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12866
12867         /* create L1 filter */
12868         filter_replace.old_filter_type =
12869                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12870         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12871         filter_replace.tr_bit = 0;
12872
12873         /* Prepare the buffer, 2 entries */
12874         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12875         filter_replace_buf.data[0] |=
12876                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12877         /* Field Vector 12b mask */
12878         filter_replace_buf.data[2] = 0xff;
12879         filter_replace_buf.data[3] = 0x0f;
12880         filter_replace_buf.data[4] =
12881                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12882         filter_replace_buf.data[4] |=
12883                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12884         /* Field Vector 12b mask */
12885         filter_replace_buf.data[6] = 0xff;
12886         filter_replace_buf.data[7] = 0x0f;
12887         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12888                         &filter_replace_buf);
12889         if (ret != I40E_SUCCESS)
12890                 return ret;
12891
12892         if (filter_replace.old_filter_type !=
12893             filter_replace.new_filter_type)
12894                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12895                             " original: 0x%x, new: 0x%x",
12896                             dev->device->name,
12897                             filter_replace.old_filter_type,
12898                             filter_replace.new_filter_type);
12899
12900         /* Apply the second L2 cloud filter */
12901         memset(&filter_replace, 0,
12902                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12903         memset(&filter_replace_buf, 0,
12904                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12905
12906         /* create L2 filter, input for L2 filter will be L1 filter  */
12907         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12908         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12909         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12910
12911         /* Prepare the buffer, 2 entries */
12912         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12913         filter_replace_buf.data[0] |=
12914                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12915         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12916         filter_replace_buf.data[4] |=
12917                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12918         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12919                         &filter_replace_buf);
12920         if (!ret && (filter_replace.old_filter_type !=
12921                      filter_replace.new_filter_type))
12922                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12923                             " original: 0x%x, new: 0x%x",
12924                             dev->device->name,
12925                             filter_replace.old_filter_type,
12926                             filter_replace.new_filter_type);
12927
12928         return ret;
12929 }
12930
12931 int
12932 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12933                    const struct rte_flow_action_rss *in)
12934 {
12935         if (in->key_len > RTE_DIM(out->key) ||
12936             in->queue_num > RTE_DIM(out->queue))
12937                 return -EINVAL;
12938         if (!in->key && in->key_len)
12939                 return -EINVAL;
12940         out->conf = (struct rte_flow_action_rss){
12941                 .func = in->func,
12942                 .level = in->level,
12943                 .types = in->types,
12944                 .key_len = in->key_len,
12945                 .queue_num = in->queue_num,
12946                 .queue = memcpy(out->queue, in->queue,
12947                                 sizeof(*in->queue) * in->queue_num),
12948         };
12949         if (in->key)
12950                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12951         return 0;
12952 }
12953
12954 /* Write HENA register to enable hash */
12955 static int
12956 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
12957 {
12958         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12959         uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
12960         uint64_t hena;
12961         int ret;
12962
12963         ret = i40e_set_rss_key(pf->main_vsi, key,
12964                                rss_conf->conf.key_len);
12965         if (ret)
12966                 return ret;
12967
12968         hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
12969         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
12970         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
12971         I40E_WRITE_FLUSH(hw);
12972
12973         return 0;
12974 }
12975
12976 /* Configure hash input set */
12977 static int
12978 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
12979 {
12980         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12981         struct rte_eth_input_set_conf conf;
12982         uint64_t mask0;
12983         int ret = 0;
12984         uint32_t j;
12985         int i;
12986         static const struct {
12987                 uint64_t type;
12988                 enum rte_eth_input_set_field field;
12989         } inset_match_table[] = {
12990                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
12991                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
12992                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
12993                         RTE_ETH_INPUT_SET_L3_DST_IP4},
12994                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
12995                         RTE_ETH_INPUT_SET_UNKNOWN},
12996                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
12997                         RTE_ETH_INPUT_SET_UNKNOWN},
12998
12999                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13000                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13001                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13002                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13003                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13004                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13005                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13006                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13007
13008                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13009                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13010                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13011                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13012                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13013                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13014                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13015                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13016
13017                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13018                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13019                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13020                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13021                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13022                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13023                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13024                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13025
13026                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13027                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13028                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13029                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13030                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13031                         RTE_ETH_INPUT_SET_UNKNOWN},
13032                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13033                         RTE_ETH_INPUT_SET_UNKNOWN},
13034
13035                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13036                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13037                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13038                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13039                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13040                         RTE_ETH_INPUT_SET_UNKNOWN},
13041                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13042                         RTE_ETH_INPUT_SET_UNKNOWN},
13043
13044                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13045                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13046                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13047                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13048                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13049                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13050                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13051                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13052
13053                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13054                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13055                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13056                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13057                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13058                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13059                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13060                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13061
13062                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13063                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13064                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13065                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13066                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13067                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13068                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13069                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13070
13071                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13072                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13073                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13074                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13075                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13076                         RTE_ETH_INPUT_SET_UNKNOWN},
13077                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13078                         RTE_ETH_INPUT_SET_UNKNOWN},
13079         };
13080
13081         mask0 = types & pf->adapter->flow_types_mask;
13082         conf.op = RTE_ETH_INPUT_SET_SELECT;
13083         conf.inset_size = 0;
13084         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13085                 if (mask0 & (1ULL << i)) {
13086                         conf.flow_type = i;
13087                         break;
13088                 }
13089         }
13090
13091         for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13092                 if ((types & inset_match_table[j].type) ==
13093                     inset_match_table[j].type) {
13094                         if (inset_match_table[j].field ==
13095                             RTE_ETH_INPUT_SET_UNKNOWN)
13096                                 return -EINVAL;
13097
13098                         conf.field[conf.inset_size] =
13099                                 inset_match_table[j].field;
13100                         conf.inset_size++;
13101                 }
13102         }
13103
13104         if (conf.inset_size) {
13105                 ret = i40e_hash_filter_inset_select(hw, &conf);
13106                 if (ret)
13107                         return ret;
13108         }
13109
13110         return ret;
13111 }
13112
13113 /* Look up the conflicted rule then mark it as invalid */
13114 static void
13115 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13116                 struct i40e_rte_flow_rss_conf *conf)
13117 {
13118         struct i40e_rss_filter *rss_item;
13119         uint64_t rss_inset;
13120
13121         /* Clear input set bits before comparing the pctype */
13122         rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13123                 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13124
13125         /* Look up the conflicted rule then mark it as invalid */
13126         TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13127                 if (!rss_item->rss_filter_info.valid)
13128                         continue;
13129
13130                 if (conf->conf.queue_num &&
13131                     rss_item->rss_filter_info.conf.queue_num)
13132                         rss_item->rss_filter_info.valid = false;
13133
13134                 if (conf->conf.types &&
13135                     (rss_item->rss_filter_info.conf.types &
13136                     rss_inset) ==
13137                     (conf->conf.types & rss_inset))
13138                         rss_item->rss_filter_info.valid = false;
13139
13140                 if (conf->conf.func ==
13141                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13142                     rss_item->rss_filter_info.conf.func ==
13143                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13144                         rss_item->rss_filter_info.valid = false;
13145         }
13146 }
13147
13148 /* Configure RSS hash function */
13149 static int
13150 i40e_rss_config_hash_function(struct i40e_pf *pf,
13151                 struct i40e_rte_flow_rss_conf *conf)
13152 {
13153         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13154         uint32_t reg, i;
13155         uint64_t mask0;
13156         uint16_t j;
13157
13158         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13159                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13160                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13161                         PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13162                         I40E_WRITE_FLUSH(hw);
13163                         i40e_rss_mark_invalid_rule(pf, conf);
13164
13165                         return 0;
13166                 }
13167                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13168
13169                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13170                 I40E_WRITE_FLUSH(hw);
13171                 i40e_rss_mark_invalid_rule(pf, conf);
13172         } else if (conf->conf.func ==
13173                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13174                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13175
13176                 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13177                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13178                         if (mask0 & (1UL << i))
13179                                 break;
13180                 }
13181
13182                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13183                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13184                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13185                                 i40e_write_global_rx_ctl(hw,
13186                                         I40E_GLQF_HSYM(j),
13187                                         I40E_GLQF_HSYM_SYMH_ENA_MASK);
13188                 }
13189         }
13190
13191         return 0;
13192 }
13193
13194 /* Enable RSS according to the configuration */
13195 static int
13196 i40e_rss_enable_hash(struct i40e_pf *pf,
13197                 struct i40e_rte_flow_rss_conf *conf)
13198 {
13199         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13200         struct i40e_rte_flow_rss_conf rss_conf;
13201
13202         if (!(conf->conf.types & pf->adapter->flow_types_mask))
13203                 return -ENOTSUP;
13204
13205         memset(&rss_conf, 0, sizeof(rss_conf));
13206         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13207
13208         /* Configure hash input set */
13209         if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13210                 return -EINVAL;
13211
13212         if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13213             (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13214                 /* Random default keys */
13215                 static uint32_t rss_key_default[] = {0x6b793944,
13216                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13217                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13218                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13219
13220                 rss_conf.conf.key = (uint8_t *)rss_key_default;
13221                 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13222                                 sizeof(uint32_t);
13223                 PMD_DRV_LOG(INFO,
13224                         "No valid RSS key config for i40e, using default\n");
13225         }
13226
13227         rss_conf.conf.types |= rss_info->conf.types;
13228         i40e_rss_hash_set(pf, &rss_conf);
13229
13230         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13231                 i40e_rss_config_hash_function(pf, conf);
13232
13233         i40e_rss_mark_invalid_rule(pf, conf);
13234
13235         return 0;
13236 }
13237
13238 /* Configure RSS queue region */
13239 static int
13240 i40e_rss_config_queue_region(struct i40e_pf *pf,
13241                 struct i40e_rte_flow_rss_conf *conf)
13242 {
13243         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13244         uint32_t lut = 0;
13245         uint16_t j, num;
13246         uint32_t i;
13247
13248         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13249          * It's necessary to calculate the actual PF queues that are configured.
13250          */
13251         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13252                 num = i40e_pf_calc_configured_queues_num(pf);
13253         else
13254                 num = pf->dev_data->nb_rx_queues;
13255
13256         num = RTE_MIN(num, conf->conf.queue_num);
13257         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13258                         num);
13259
13260         if (num == 0) {
13261                 PMD_DRV_LOG(ERR,
13262                         "No PF queues are configured to enable RSS for port %u",
13263                         pf->dev_data->port_id);
13264                 return -ENOTSUP;
13265         }
13266
13267         /* Fill in redirection table */
13268         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13269                 if (j == num)
13270                         j = 0;
13271                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13272                         hw->func_caps.rss_table_entry_width) - 1));
13273                 if ((i & 3) == 3)
13274                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13275         }
13276
13277         i40e_rss_mark_invalid_rule(pf, conf);
13278
13279         return 0;
13280 }
13281
13282 /* Configure RSS hash function to default */
13283 static int
13284 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13285                 struct i40e_rte_flow_rss_conf *conf)
13286 {
13287         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13288         uint32_t i, reg;
13289         uint64_t mask0;
13290         uint16_t j;
13291
13292         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13293                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13294                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13295                         PMD_DRV_LOG(DEBUG,
13296                                 "Hash function already set to Toeplitz");
13297                         I40E_WRITE_FLUSH(hw);
13298
13299                         return 0;
13300                 }
13301                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13302
13303                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13304                 I40E_WRITE_FLUSH(hw);
13305         } else if (conf->conf.func ==
13306                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13307                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13308
13309                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13310                         if (mask0 & (1UL << i))
13311                                 break;
13312                 }
13313
13314                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13315                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13316                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13317                                 i40e_write_global_rx_ctl(hw,
13318                                         I40E_GLQF_HSYM(j),
13319                                         0);
13320                 }
13321         }
13322
13323         return 0;
13324 }
13325
13326 /* Disable RSS hash and configure default input set */
13327 static int
13328 i40e_rss_disable_hash(struct i40e_pf *pf,
13329                 struct i40e_rte_flow_rss_conf *conf)
13330 {
13331         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13332         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13333         struct i40e_rte_flow_rss_conf rss_conf;
13334         uint32_t i;
13335
13336         memset(&rss_conf, 0, sizeof(rss_conf));
13337         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13338
13339         /* Disable RSS hash */
13340         rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13341         i40e_rss_hash_set(pf, &rss_conf);
13342
13343         for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13344                 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13345                     !(conf->conf.types & (1ULL << i)))
13346                         continue;
13347
13348                 /* Configure default input set */
13349                 struct rte_eth_input_set_conf input_conf = {
13350                         .op = RTE_ETH_INPUT_SET_SELECT,
13351                         .flow_type = i,
13352                         .inset_size = 1,
13353                 };
13354                 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13355                 i40e_hash_filter_inset_select(hw, &input_conf);
13356         }
13357
13358         rss_info->conf.types = rss_conf.conf.types;
13359
13360         i40e_rss_clear_hash_function(pf, conf);
13361
13362         return 0;
13363 }
13364
13365 /* Configure RSS queue region to default */
13366 static int
13367 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13368 {
13369         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13370         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13371         uint16_t queue[I40E_MAX_Q_PER_TC];
13372         uint32_t num_rxq, i;
13373         uint32_t lut = 0;
13374         uint16_t j, num;
13375
13376         num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13377
13378         for (j = 0; j < num_rxq; j++)
13379                 queue[j] = j;
13380
13381         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13382          * It's necessary to calculate the actual PF queues that are configured.
13383          */
13384         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13385                 num = i40e_pf_calc_configured_queues_num(pf);
13386         else
13387                 num = pf->dev_data->nb_rx_queues;
13388
13389         num = RTE_MIN(num, num_rxq);
13390         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13391                         num);
13392
13393         if (num == 0) {
13394                 PMD_DRV_LOG(ERR,
13395                         "No PF queues are configured to enable RSS for port %u",
13396                         pf->dev_data->port_id);
13397                 return -ENOTSUP;
13398         }
13399
13400         /* Fill in redirection table */
13401         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13402                 if (j == num)
13403                         j = 0;
13404                 lut = (lut << 8) | (queue[j] & ((0x1 <<
13405                         hw->func_caps.rss_table_entry_width) - 1));
13406                 if ((i & 3) == 3)
13407                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13408         }
13409
13410         rss_info->conf.queue_num = 0;
13411         memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13412
13413         return 0;
13414 }
13415
13416 int
13417 i40e_config_rss_filter(struct i40e_pf *pf,
13418                 struct i40e_rte_flow_rss_conf *conf, bool add)
13419 {
13420         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13421         struct rte_flow_action_rss update_conf = rss_info->conf;
13422         int ret = 0;
13423
13424         if (add) {
13425                 if (conf->conf.queue_num) {
13426                         /* Configure RSS queue region */
13427                         ret = i40e_rss_config_queue_region(pf, conf);
13428                         if (ret)
13429                                 return ret;
13430
13431                         update_conf.queue_num = conf->conf.queue_num;
13432                         update_conf.queue = conf->conf.queue;
13433                 } else if (conf->conf.func ==
13434                            RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13435                         /* Configure hash function */
13436                         ret = i40e_rss_config_hash_function(pf, conf);
13437                         if (ret)
13438                                 return ret;
13439
13440                         update_conf.func = conf->conf.func;
13441                 } else {
13442                         /* Configure hash enable and input set */
13443                         ret = i40e_rss_enable_hash(pf, conf);
13444                         if (ret)
13445                                 return ret;
13446
13447                         update_conf.types |= conf->conf.types;
13448                         update_conf.key = conf->conf.key;
13449                         update_conf.key_len = conf->conf.key_len;
13450                 }
13451
13452                 /* Update RSS info in pf */
13453                 if (i40e_rss_conf_init(rss_info, &update_conf))
13454                         return -EINVAL;
13455         } else {
13456                 if (!conf->valid)
13457                         return 0;
13458
13459                 if (conf->conf.queue_num)
13460                         i40e_rss_clear_queue_region(pf);
13461                 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13462                         i40e_rss_clear_hash_function(pf, conf);
13463                 else
13464                         i40e_rss_disable_hash(pf, conf);
13465         }
13466
13467         return 0;
13468 }
13469
13470 RTE_INIT(i40e_init_log)
13471 {
13472         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
13473         if (i40e_logtype_init >= 0)
13474                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
13475         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
13476         if (i40e_logtype_driver >= 0)
13477                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
13478
13479 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13480         i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx");
13481         if (i40e_logtype_rx >= 0)
13482                 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG);
13483 #endif
13484
13485 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13486         i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx");
13487         if (i40e_logtype_tx >= 0)
13488                 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG);
13489 #endif
13490
13491 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13492         i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free");
13493         if (i40e_logtype_tx_free >= 0)
13494                 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG);
13495 #endif
13496 }
13497
13498 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13499                               ETH_I40E_FLOATING_VEB_ARG "=1"
13500                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13501                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13502                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13503                               ETH_I40E_USE_LATEST_VEC "=0|1");