1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
47 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
242 char *fw_version, size_t fw_size);
243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
244 struct rte_eth_dev_info *dev_info);
245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
249 enum rte_vlan_type vlan_type,
251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
259 struct rte_eth_fc_conf *fc_conf);
260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
261 struct rte_eth_fc_conf *fc_conf);
262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
263 struct rte_eth_pfc_conf *pfc_conf);
264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
265 struct rte_ether_addr *mac_addr,
268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
270 struct rte_eth_rss_reta_entry64 *reta_conf,
272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_get_cap(struct i40e_hw *hw);
277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
278 static int i40e_pf_setup(struct i40e_pf *pf);
279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
283 bool offset_loaded, uint64_t *offset, uint64_t *stat);
284 static void i40e_stat_update_48(struct i40e_hw *hw,
290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
291 static void i40e_dev_interrupt_handler(void *param);
292 static void i40e_dev_alarm_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct rte_ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 int i40e_logtype_init;
402 int i40e_logtype_driver;
404 static const char *const valid_keys[] = {
405 ETH_I40E_FLOATING_VEB_ARG,
406 ETH_I40E_FLOATING_VEB_LIST_ARG,
407 ETH_I40E_SUPPORT_MULTI_DRIVER,
408 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
409 ETH_I40E_USE_LATEST_VEC,
413 static const struct rte_pci_id pci_id_i40e_map[] = {
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
437 { .vendor_id = 0, /* sentinel */ },
440 static const struct eth_dev_ops i40e_eth_dev_ops = {
441 .dev_configure = i40e_dev_configure,
442 .dev_start = i40e_dev_start,
443 .dev_stop = i40e_dev_stop,
444 .dev_close = i40e_dev_close,
445 .dev_reset = i40e_dev_reset,
446 .promiscuous_enable = i40e_dev_promiscuous_enable,
447 .promiscuous_disable = i40e_dev_promiscuous_disable,
448 .allmulticast_enable = i40e_dev_allmulticast_enable,
449 .allmulticast_disable = i40e_dev_allmulticast_disable,
450 .dev_set_link_up = i40e_dev_set_link_up,
451 .dev_set_link_down = i40e_dev_set_link_down,
452 .link_update = i40e_dev_link_update,
453 .stats_get = i40e_dev_stats_get,
454 .xstats_get = i40e_dev_xstats_get,
455 .xstats_get_names = i40e_dev_xstats_get_names,
456 .stats_reset = i40e_dev_stats_reset,
457 .xstats_reset = i40e_dev_stats_reset,
458 .fw_version_get = i40e_fw_version_get,
459 .dev_infos_get = i40e_dev_info_get,
460 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
461 .vlan_filter_set = i40e_vlan_filter_set,
462 .vlan_tpid_set = i40e_vlan_tpid_set,
463 .vlan_offload_set = i40e_vlan_offload_set,
464 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
465 .vlan_pvid_set = i40e_vlan_pvid_set,
466 .rx_queue_start = i40e_dev_rx_queue_start,
467 .rx_queue_stop = i40e_dev_rx_queue_stop,
468 .tx_queue_start = i40e_dev_tx_queue_start,
469 .tx_queue_stop = i40e_dev_tx_queue_stop,
470 .rx_queue_setup = i40e_dev_rx_queue_setup,
471 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
472 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
473 .rx_queue_release = i40e_dev_rx_queue_release,
474 .rx_queue_count = i40e_dev_rx_queue_count,
475 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
476 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
477 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
478 .tx_queue_setup = i40e_dev_tx_queue_setup,
479 .tx_queue_release = i40e_dev_tx_queue_release,
480 .dev_led_on = i40e_dev_led_on,
481 .dev_led_off = i40e_dev_led_off,
482 .flow_ctrl_get = i40e_flow_ctrl_get,
483 .flow_ctrl_set = i40e_flow_ctrl_set,
484 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
485 .mac_addr_add = i40e_macaddr_add,
486 .mac_addr_remove = i40e_macaddr_remove,
487 .reta_update = i40e_dev_rss_reta_update,
488 .reta_query = i40e_dev_rss_reta_query,
489 .rss_hash_update = i40e_dev_rss_hash_update,
490 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
491 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
492 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
493 .filter_ctrl = i40e_dev_filter_ctrl,
494 .rxq_info_get = i40e_rxq_info_get,
495 .txq_info_get = i40e_txq_info_get,
496 .mirror_rule_set = i40e_mirror_rule_set,
497 .mirror_rule_reset = i40e_mirror_rule_reset,
498 .timesync_enable = i40e_timesync_enable,
499 .timesync_disable = i40e_timesync_disable,
500 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
501 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
502 .get_dcb_info = i40e_dev_get_dcb_info,
503 .timesync_adjust_time = i40e_timesync_adjust_time,
504 .timesync_read_time = i40e_timesync_read_time,
505 .timesync_write_time = i40e_timesync_write_time,
506 .get_reg = i40e_get_regs,
507 .get_eeprom_length = i40e_get_eeprom_length,
508 .get_eeprom = i40e_get_eeprom,
509 .get_module_info = i40e_get_module_info,
510 .get_module_eeprom = i40e_get_module_eeprom,
511 .mac_addr_set = i40e_set_default_mac_addr,
512 .mtu_set = i40e_dev_mtu_set,
513 .tm_ops_get = i40e_tm_ops_get,
516 /* store statistics names and its offset in stats structure */
517 struct rte_i40e_xstats_name_off {
518 char name[RTE_ETH_XSTATS_NAME_SIZE];
522 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
523 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
524 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
525 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
526 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
527 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
528 rx_unknown_protocol)},
529 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
530 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
531 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
532 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
535 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
536 sizeof(rte_i40e_stats_strings[0]))
538 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
539 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
540 tx_dropped_link_down)},
541 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
542 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
544 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
545 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
547 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
549 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
551 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
552 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
553 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
554 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
555 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
556 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
558 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
560 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
570 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
572 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
573 mac_short_packet_dropped)},
574 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
577 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
578 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
580 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
582 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
590 {"rx_flow_director_atr_match_packets",
591 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
592 {"rx_flow_director_sb_match_packets",
593 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
594 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
596 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
598 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
600 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
604 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
605 sizeof(rte_i40e_hw_port_strings[0]))
607 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
608 {"xon_packets", offsetof(struct i40e_hw_port_stats,
610 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
614 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
615 sizeof(rte_i40e_rxq_prio_strings[0]))
617 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
618 {"xon_packets", offsetof(struct i40e_hw_port_stats,
620 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
622 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
623 priority_xon_2_xoff)},
626 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
627 sizeof(rte_i40e_txq_prio_strings[0]))
630 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
631 struct rte_pci_device *pci_dev)
633 char name[RTE_ETH_NAME_MAX_LEN];
634 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
637 if (pci_dev->device.devargs) {
638 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
644 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
645 sizeof(struct i40e_adapter),
646 eth_dev_pci_specific_init, pci_dev,
647 eth_i40e_dev_init, NULL);
649 if (retval || eth_da.nb_representor_ports < 1)
652 /* probe VF representor ports */
653 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
654 pci_dev->device.name);
656 if (pf_ethdev == NULL)
659 for (i = 0; i < eth_da.nb_representor_ports; i++) {
660 struct i40e_vf_representor representor = {
661 .vf_id = eth_da.representor_ports[i],
662 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
663 pf_ethdev->data->dev_private)->switch_domain_id,
664 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
665 pf_ethdev->data->dev_private)
668 /* representor port net_bdf_port */
669 snprintf(name, sizeof(name), "net_%s_representor_%d",
670 pci_dev->device.name, eth_da.representor_ports[i]);
672 retval = rte_eth_dev_create(&pci_dev->device, name,
673 sizeof(struct i40e_vf_representor), NULL, NULL,
674 i40e_vf_representor_init, &representor);
677 PMD_DRV_LOG(ERR, "failed to create i40e vf "
678 "representor %s.", name);
684 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
686 struct rte_eth_dev *ethdev;
688 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
693 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
694 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
696 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
699 static struct rte_pci_driver rte_i40e_pmd = {
700 .id_table = pci_id_i40e_map,
701 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
702 .probe = eth_i40e_pci_probe,
703 .remove = eth_i40e_pci_remove,
707 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
710 uint32_t ori_reg_val;
711 struct rte_eth_dev *dev;
713 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
714 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
715 i40e_write_rx_ctl(hw, reg_addr, reg_val);
716 if (ori_reg_val != reg_val)
718 "i40e device %s changed global register [0x%08x]."
719 " original: 0x%08x, new: 0x%08x",
720 dev->device->name, reg_addr, ori_reg_val, reg_val);
723 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
724 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
725 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
727 #ifndef I40E_GLQF_ORT
728 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
730 #ifndef I40E_GLQF_PIT
731 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
733 #ifndef I40E_GLQF_L3_MAP
734 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
737 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
740 * Initialize registers for parsing packet type of QinQ
741 * This should be removed from code once proper
742 * configuration API is added to avoid configuration conflicts
743 * between ports of the same device.
745 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
746 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
749 static inline void i40e_config_automask(struct i40e_pf *pf)
751 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
754 /* INTENA flag is not auto-cleared for interrupt */
755 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
756 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
757 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
759 /* If support multi-driver, PF will use INT0. */
760 if (!pf->support_multi_driver)
761 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
763 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
766 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
769 * Add a ethertype filter to drop all flow control frames transmitted
773 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
775 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
776 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
777 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
778 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
781 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
782 I40E_FLOW_CONTROL_ETHERTYPE, flags,
783 pf->main_vsi_seid, 0,
787 "Failed to add filter to drop flow control frames from VSIs.");
791 floating_veb_list_handler(__rte_unused const char *key,
792 const char *floating_veb_value,
796 unsigned int count = 0;
799 bool *vf_floating_veb = opaque;
801 while (isblank(*floating_veb_value))
802 floating_veb_value++;
804 /* Reset floating VEB configuration for VFs */
805 for (idx = 0; idx < I40E_MAX_VF; idx++)
806 vf_floating_veb[idx] = false;
810 while (isblank(*floating_veb_value))
811 floating_veb_value++;
812 if (*floating_veb_value == '\0')
815 idx = strtoul(floating_veb_value, &end, 10);
816 if (errno || end == NULL)
818 while (isblank(*end))
822 } else if ((*end == ';') || (*end == '\0')) {
824 if (min == I40E_MAX_VF)
826 if (max >= I40E_MAX_VF)
827 max = I40E_MAX_VF - 1;
828 for (idx = min; idx <= max; idx++) {
829 vf_floating_veb[idx] = true;
836 floating_veb_value = end + 1;
837 } while (*end != '\0');
846 config_vf_floating_veb(struct rte_devargs *devargs,
847 uint16_t floating_veb,
848 bool *vf_floating_veb)
850 struct rte_kvargs *kvlist;
852 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
856 /* All the VFs attach to the floating VEB by default
857 * when the floating VEB is enabled.
859 for (i = 0; i < I40E_MAX_VF; i++)
860 vf_floating_veb[i] = true;
865 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
869 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
870 rte_kvargs_free(kvlist);
873 /* When the floating_veb_list parameter exists, all the VFs
874 * will attach to the legacy VEB firstly, then configure VFs
875 * to the floating VEB according to the floating_veb_list.
877 if (rte_kvargs_process(kvlist, floating_veb_list,
878 floating_veb_list_handler,
879 vf_floating_veb) < 0) {
880 rte_kvargs_free(kvlist);
883 rte_kvargs_free(kvlist);
887 i40e_check_floating_handler(__rte_unused const char *key,
889 __rte_unused void *opaque)
891 if (strcmp(value, "1"))
898 is_floating_veb_supported(struct rte_devargs *devargs)
900 struct rte_kvargs *kvlist;
901 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
906 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
910 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
911 rte_kvargs_free(kvlist);
914 /* Floating VEB is enabled when there's key-value:
915 * enable_floating_veb=1
917 if (rte_kvargs_process(kvlist, floating_veb_key,
918 i40e_check_floating_handler, NULL) < 0) {
919 rte_kvargs_free(kvlist);
922 rte_kvargs_free(kvlist);
928 config_floating_veb(struct rte_eth_dev *dev)
930 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
931 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
932 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
934 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
936 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
938 is_floating_veb_supported(pci_dev->device.devargs);
939 config_vf_floating_veb(pci_dev->device.devargs,
941 pf->floating_veb_list);
943 pf->floating_veb = false;
947 #define I40E_L2_TAGS_S_TAG_SHIFT 1
948 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
951 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
953 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
954 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
955 char ethertype_hash_name[RTE_HASH_NAMESIZE];
958 struct rte_hash_parameters ethertype_hash_params = {
959 .name = ethertype_hash_name,
960 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
961 .key_len = sizeof(struct i40e_ethertype_filter_input),
962 .hash_func = rte_hash_crc,
963 .hash_func_init_val = 0,
964 .socket_id = rte_socket_id(),
967 /* Initialize ethertype filter rule list and hash */
968 TAILQ_INIT(ðertype_rule->ethertype_list);
969 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
970 "ethertype_%s", dev->device->name);
971 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
972 if (!ethertype_rule->hash_table) {
973 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
976 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
977 sizeof(struct i40e_ethertype_filter *) *
978 I40E_MAX_ETHERTYPE_FILTER_NUM,
980 if (!ethertype_rule->hash_map) {
982 "Failed to allocate memory for ethertype hash map!");
984 goto err_ethertype_hash_map_alloc;
989 err_ethertype_hash_map_alloc:
990 rte_hash_free(ethertype_rule->hash_table);
996 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
998 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
999 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1000 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1003 struct rte_hash_parameters tunnel_hash_params = {
1004 .name = tunnel_hash_name,
1005 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1006 .key_len = sizeof(struct i40e_tunnel_filter_input),
1007 .hash_func = rte_hash_crc,
1008 .hash_func_init_val = 0,
1009 .socket_id = rte_socket_id(),
1012 /* Initialize tunnel filter rule list and hash */
1013 TAILQ_INIT(&tunnel_rule->tunnel_list);
1014 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1015 "tunnel_%s", dev->device->name);
1016 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1017 if (!tunnel_rule->hash_table) {
1018 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1021 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1022 sizeof(struct i40e_tunnel_filter *) *
1023 I40E_MAX_TUNNEL_FILTER_NUM,
1025 if (!tunnel_rule->hash_map) {
1027 "Failed to allocate memory for tunnel hash map!");
1029 goto err_tunnel_hash_map_alloc;
1034 err_tunnel_hash_map_alloc:
1035 rte_hash_free(tunnel_rule->hash_table);
1041 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1043 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1044 struct i40e_fdir_info *fdir_info = &pf->fdir;
1045 char fdir_hash_name[RTE_HASH_NAMESIZE];
1048 struct rte_hash_parameters fdir_hash_params = {
1049 .name = fdir_hash_name,
1050 .entries = I40E_MAX_FDIR_FILTER_NUM,
1051 .key_len = sizeof(struct i40e_fdir_input),
1052 .hash_func = rte_hash_crc,
1053 .hash_func_init_val = 0,
1054 .socket_id = rte_socket_id(),
1057 /* Initialize flow director filter rule list and hash */
1058 TAILQ_INIT(&fdir_info->fdir_list);
1059 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1060 "fdir_%s", dev->device->name);
1061 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1062 if (!fdir_info->hash_table) {
1063 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1066 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1067 sizeof(struct i40e_fdir_filter *) *
1068 I40E_MAX_FDIR_FILTER_NUM,
1070 if (!fdir_info->hash_map) {
1072 "Failed to allocate memory for fdir hash map!");
1074 goto err_fdir_hash_map_alloc;
1078 err_fdir_hash_map_alloc:
1079 rte_hash_free(fdir_info->hash_table);
1085 i40e_init_customized_info(struct i40e_pf *pf)
1089 /* Initialize customized pctype */
1090 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1091 pf->customized_pctype[i].index = i;
1092 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1093 pf->customized_pctype[i].valid = false;
1096 pf->gtp_support = false;
1100 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1102 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1103 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1104 struct i40e_queue_regions *info = &pf->queue_region;
1107 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1108 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1110 memset(info, 0, sizeof(struct i40e_queue_regions));
1114 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1119 unsigned long support_multi_driver;
1122 pf = (struct i40e_pf *)opaque;
1125 support_multi_driver = strtoul(value, &end, 10);
1126 if (errno != 0 || end == value || *end != 0) {
1127 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1131 if (support_multi_driver == 1 || support_multi_driver == 0)
1132 pf->support_multi_driver = (bool)support_multi_driver;
1134 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1135 "enable global configuration by default."
1136 ETH_I40E_SUPPORT_MULTI_DRIVER);
1141 i40e_support_multi_driver(struct rte_eth_dev *dev)
1143 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1144 struct rte_kvargs *kvlist;
1147 /* Enable global configuration by default */
1148 pf->support_multi_driver = false;
1150 if (!dev->device->devargs)
1153 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1157 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1158 if (!kvargs_count) {
1159 rte_kvargs_free(kvlist);
1163 if (kvargs_count > 1)
1164 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1165 "the first invalid or last valid one is used !",
1166 ETH_I40E_SUPPORT_MULTI_DRIVER);
1168 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1169 i40e_parse_multi_drv_handler, pf) < 0) {
1170 rte_kvargs_free(kvlist);
1174 rte_kvargs_free(kvlist);
1179 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1180 uint32_t reg_addr, uint64_t reg_val,
1181 struct i40e_asq_cmd_details *cmd_details)
1183 uint64_t ori_reg_val;
1184 struct rte_eth_dev *dev;
1187 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1188 if (ret != I40E_SUCCESS) {
1190 "Fail to debug read from 0x%08x",
1194 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1196 if (ori_reg_val != reg_val)
1197 PMD_DRV_LOG(WARNING,
1198 "i40e device %s changed global register [0x%08x]."
1199 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1200 dev->device->name, reg_addr, ori_reg_val, reg_val);
1202 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1206 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1210 struct i40e_adapter *ad = opaque;
1213 use_latest_vec = atoi(value);
1215 if (use_latest_vec != 0 && use_latest_vec != 1)
1216 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1218 ad->use_latest_vec = (uint8_t)use_latest_vec;
1224 i40e_use_latest_vec(struct rte_eth_dev *dev)
1226 struct i40e_adapter *ad =
1227 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1228 struct rte_kvargs *kvlist;
1231 ad->use_latest_vec = false;
1233 if (!dev->device->devargs)
1236 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1240 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1241 if (!kvargs_count) {
1242 rte_kvargs_free(kvlist);
1246 if (kvargs_count > 1)
1247 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1248 "the first invalid or last valid one is used !",
1249 ETH_I40E_USE_LATEST_VEC);
1251 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1252 i40e_parse_latest_vec_handler, ad) < 0) {
1253 rte_kvargs_free(kvlist);
1257 rte_kvargs_free(kvlist);
1262 read_vf_msg_config(__rte_unused const char *key,
1266 struct i40e_vf_msg_cfg *cfg = opaque;
1268 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1269 &cfg->ignore_second) != 3) {
1270 memset(cfg, 0, sizeof(*cfg));
1271 PMD_DRV_LOG(ERR, "format error! example: "
1272 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1277 * If the message validation function been enabled, the 'period'
1278 * and 'ignore_second' must greater than 0.
1280 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1281 memset(cfg, 0, sizeof(*cfg));
1282 PMD_DRV_LOG(ERR, "%s error! the second and third"
1283 " number must be greater than 0!",
1284 ETH_I40E_VF_MSG_CFG);
1292 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1293 struct i40e_vf_msg_cfg *msg_cfg)
1295 struct rte_kvargs *kvlist;
1299 memset(msg_cfg, 0, sizeof(*msg_cfg));
1301 if (!dev->device->devargs)
1304 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1308 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1312 if (kvargs_count > 1) {
1313 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1314 ETH_I40E_VF_MSG_CFG);
1319 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1320 read_vf_msg_config, msg_cfg) < 0)
1324 rte_kvargs_free(kvlist);
1328 #define I40E_ALARM_INTERVAL 50000 /* us */
1331 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1333 struct rte_pci_device *pci_dev;
1334 struct rte_intr_handle *intr_handle;
1335 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1336 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337 struct i40e_vsi *vsi;
1340 uint8_t aq_fail = 0;
1342 PMD_INIT_FUNC_TRACE();
1344 dev->dev_ops = &i40e_eth_dev_ops;
1345 dev->rx_pkt_burst = i40e_recv_pkts;
1346 dev->tx_pkt_burst = i40e_xmit_pkts;
1347 dev->tx_pkt_prepare = i40e_prep_pkts;
1349 /* for secondary processes, we don't initialise any further as primary
1350 * has already done this work. Only check we don't need a different
1352 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1353 i40e_set_rx_function(dev);
1354 i40e_set_tx_function(dev);
1357 i40e_set_default_ptype_table(dev);
1358 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1359 intr_handle = &pci_dev->intr_handle;
1361 rte_eth_copy_pci_info(dev, pci_dev);
1363 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1364 pf->adapter->eth_dev = dev;
1365 pf->dev_data = dev->data;
1367 hw->back = I40E_PF_TO_ADAPTER(pf);
1368 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1371 "Hardware is not available, as address is NULL");
1375 hw->vendor_id = pci_dev->id.vendor_id;
1376 hw->device_id = pci_dev->id.device_id;
1377 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1378 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1379 hw->bus.device = pci_dev->addr.devid;
1380 hw->bus.func = pci_dev->addr.function;
1381 hw->adapter_stopped = 0;
1382 hw->adapter_closed = 0;
1385 * Switch Tag value should not be identical to either the First Tag
1386 * or Second Tag values. So set something other than common Ethertype
1387 * for internal switching.
1389 hw->switch_tag = 0xffff;
1391 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1392 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1393 PMD_INIT_LOG(ERR, "\nERROR: "
1394 "Firmware recovery mode detected. Limiting functionality.\n"
1395 "Refer to the Intel(R) Ethernet Adapters and Devices "
1396 "User Guide for details on firmware recovery mode.");
1400 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1401 /* Check if need to support multi-driver */
1402 i40e_support_multi_driver(dev);
1403 /* Check if users want the latest supported vec path */
1404 i40e_use_latest_vec(dev);
1406 /* Make sure all is clean before doing PF reset */
1409 /* Reset here to make sure all is clean for each PF */
1410 ret = i40e_pf_reset(hw);
1412 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1416 /* Initialize the shared code (base driver) */
1417 ret = i40e_init_shared_code(hw);
1419 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1423 /* Initialize the parameters for adminq */
1424 i40e_init_adminq_parameter(hw);
1425 ret = i40e_init_adminq(hw);
1426 if (ret != I40E_SUCCESS) {
1427 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1430 /* Firmware of SFP x722 does not support adminq option */
1431 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1432 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1434 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1435 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1436 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1437 ((hw->nvm.version >> 12) & 0xf),
1438 ((hw->nvm.version >> 4) & 0xff),
1439 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1441 /* Initialize the hardware */
1444 i40e_config_automask(pf);
1446 i40e_set_default_pctype_table(dev);
1449 * To work around the NVM issue, initialize registers
1450 * for packet type of QinQ by software.
1451 * It should be removed once issues are fixed in NVM.
1453 if (!pf->support_multi_driver)
1454 i40e_GLQF_reg_init(hw);
1456 /* Initialize the input set for filters (hash and fd) to default value */
1457 i40e_filter_input_set_init(pf);
1459 /* initialise the L3_MAP register */
1460 if (!pf->support_multi_driver) {
1461 ret = i40e_aq_debug_write_global_register(hw,
1462 I40E_GLQF_L3_MAP(40),
1465 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1468 "Global register 0x%08x is changed with 0x28",
1469 I40E_GLQF_L3_MAP(40));
1472 /* Need the special FW version to support floating VEB */
1473 config_floating_veb(dev);
1474 /* Clear PXE mode */
1475 i40e_clear_pxe_mode(hw);
1476 i40e_dev_sync_phy_type(hw);
1479 * On X710, performance number is far from the expectation on recent
1480 * firmware versions. The fix for this issue may not be integrated in
1481 * the following firmware version. So the workaround in software driver
1482 * is needed. It needs to modify the initial values of 3 internal only
1483 * registers. Note that the workaround can be removed when it is fixed
1484 * in firmware in the future.
1486 i40e_configure_registers(hw);
1488 /* Get hw capabilities */
1489 ret = i40e_get_cap(hw);
1490 if (ret != I40E_SUCCESS) {
1491 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1492 goto err_get_capabilities;
1495 /* Initialize parameters for PF */
1496 ret = i40e_pf_parameter_init(dev);
1498 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1499 goto err_parameter_init;
1502 /* Initialize the queue management */
1503 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1505 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1506 goto err_qp_pool_init;
1508 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1509 hw->func_caps.num_msix_vectors - 1);
1511 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1512 goto err_msix_pool_init;
1515 /* Initialize lan hmc */
1516 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1517 hw->func_caps.num_rx_qp, 0, 0);
1518 if (ret != I40E_SUCCESS) {
1519 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1520 goto err_init_lan_hmc;
1523 /* Configure lan hmc */
1524 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1525 if (ret != I40E_SUCCESS) {
1526 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1527 goto err_configure_lan_hmc;
1530 /* Get and check the mac address */
1531 i40e_get_mac_addr(hw, hw->mac.addr);
1532 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1533 PMD_INIT_LOG(ERR, "mac address is not valid");
1535 goto err_get_mac_addr;
1537 /* Copy the permanent MAC address */
1538 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1539 (struct rte_ether_addr *)hw->mac.perm_addr);
1541 /* Disable flow control */
1542 hw->fc.requested_mode = I40E_FC_NONE;
1543 i40e_set_fc(hw, &aq_fail, TRUE);
1545 /* Set the global registers with default ether type value */
1546 if (!pf->support_multi_driver) {
1547 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1548 RTE_ETHER_TYPE_VLAN);
1549 if (ret != I40E_SUCCESS) {
1551 "Failed to set the default outer "
1553 goto err_setup_pf_switch;
1557 /* PF setup, which includes VSI setup */
1558 ret = i40e_pf_setup(pf);
1560 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1561 goto err_setup_pf_switch;
1566 /* Disable double vlan by default */
1567 i40e_vsi_config_double_vlan(vsi, FALSE);
1569 /* Disable S-TAG identification when floating_veb is disabled */
1570 if (!pf->floating_veb) {
1571 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1572 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1573 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1574 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1578 if (!vsi->max_macaddrs)
1579 len = RTE_ETHER_ADDR_LEN;
1581 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1583 /* Should be after VSI initialized */
1584 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1585 if (!dev->data->mac_addrs) {
1587 "Failed to allocated memory for storing mac address");
1590 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1591 &dev->data->mac_addrs[0]);
1593 /* Init dcb to sw mode by default */
1594 ret = i40e_dcb_init_configure(dev, TRUE);
1595 if (ret != I40E_SUCCESS) {
1596 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1597 pf->flags &= ~I40E_FLAG_DCB;
1599 /* Update HW struct after DCB configuration */
1602 /* initialize pf host driver to setup SRIOV resource if applicable */
1603 i40e_pf_host_init(dev);
1605 /* register callback func to eal lib */
1606 rte_intr_callback_register(intr_handle,
1607 i40e_dev_interrupt_handler, dev);
1609 /* configure and enable device interrupt */
1610 i40e_pf_config_irq0(hw, TRUE);
1611 i40e_pf_enable_irq0(hw);
1613 /* enable uio intr after callback register */
1614 rte_intr_enable(intr_handle);
1616 /* By default disable flexible payload in global configuration */
1617 if (!pf->support_multi_driver)
1618 i40e_flex_payload_reg_set_default(hw);
1621 * Add an ethertype filter to drop all flow control frames transmitted
1622 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1625 i40e_add_tx_flow_control_drop_filter(pf);
1627 /* Set the max frame size to 0x2600 by default,
1628 * in case other drivers changed the default value.
1630 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1632 /* initialize mirror rule list */
1633 TAILQ_INIT(&pf->mirror_list);
1635 /* initialize Traffic Manager configuration */
1636 i40e_tm_conf_init(dev);
1638 /* Initialize customized information */
1639 i40e_init_customized_info(pf);
1641 ret = i40e_init_ethtype_filter_list(dev);
1643 goto err_init_ethtype_filter_list;
1644 ret = i40e_init_tunnel_filter_list(dev);
1646 goto err_init_tunnel_filter_list;
1647 ret = i40e_init_fdir_filter_list(dev);
1649 goto err_init_fdir_filter_list;
1651 /* initialize queue region configuration */
1652 i40e_init_queue_region_conf(dev);
1654 /* initialize rss configuration from rte_flow */
1655 memset(&pf->rss_info, 0,
1656 sizeof(struct i40e_rte_flow_rss_conf));
1658 /* reset all stats of the device, including pf and main vsi */
1659 i40e_dev_stats_reset(dev);
1663 err_init_fdir_filter_list:
1664 rte_free(pf->tunnel.hash_table);
1665 rte_free(pf->tunnel.hash_map);
1666 err_init_tunnel_filter_list:
1667 rte_free(pf->ethertype.hash_table);
1668 rte_free(pf->ethertype.hash_map);
1669 err_init_ethtype_filter_list:
1670 rte_free(dev->data->mac_addrs);
1671 dev->data->mac_addrs = NULL;
1673 i40e_vsi_release(pf->main_vsi);
1674 err_setup_pf_switch:
1676 err_configure_lan_hmc:
1677 (void)i40e_shutdown_lan_hmc(hw);
1679 i40e_res_pool_destroy(&pf->msix_pool);
1681 i40e_res_pool_destroy(&pf->qp_pool);
1684 err_get_capabilities:
1685 (void)i40e_shutdown_adminq(hw);
1691 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1693 struct i40e_ethertype_filter *p_ethertype;
1694 struct i40e_ethertype_rule *ethertype_rule;
1696 ethertype_rule = &pf->ethertype;
1697 /* Remove all ethertype filter rules and hash */
1698 if (ethertype_rule->hash_map)
1699 rte_free(ethertype_rule->hash_map);
1700 if (ethertype_rule->hash_table)
1701 rte_hash_free(ethertype_rule->hash_table);
1703 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1704 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1705 p_ethertype, rules);
1706 rte_free(p_ethertype);
1711 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1713 struct i40e_tunnel_filter *p_tunnel;
1714 struct i40e_tunnel_rule *tunnel_rule;
1716 tunnel_rule = &pf->tunnel;
1717 /* Remove all tunnel director rules and hash */
1718 if (tunnel_rule->hash_map)
1719 rte_free(tunnel_rule->hash_map);
1720 if (tunnel_rule->hash_table)
1721 rte_hash_free(tunnel_rule->hash_table);
1723 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1724 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1730 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1732 struct i40e_fdir_filter *p_fdir;
1733 struct i40e_fdir_info *fdir_info;
1735 fdir_info = &pf->fdir;
1736 /* Remove all flow director rules and hash */
1737 if (fdir_info->hash_map)
1738 rte_free(fdir_info->hash_map);
1739 if (fdir_info->hash_table)
1740 rte_hash_free(fdir_info->hash_table);
1742 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1743 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1748 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1751 * Disable by default flexible payload
1752 * for corresponding L2/L3/L4 layers.
1754 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1755 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1756 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1760 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1763 struct rte_pci_device *pci_dev;
1764 struct rte_intr_handle *intr_handle;
1766 struct i40e_filter_control_settings settings;
1767 struct rte_flow *p_flow;
1769 uint8_t aq_fail = 0;
1772 PMD_INIT_FUNC_TRACE();
1774 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1777 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1778 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1779 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1780 intr_handle = &pci_dev->intr_handle;
1782 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1784 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1786 if (hw->adapter_closed == 0)
1787 i40e_dev_close(dev);
1789 dev->dev_ops = NULL;
1790 dev->rx_pkt_burst = NULL;
1791 dev->tx_pkt_burst = NULL;
1793 /* Clear PXE mode */
1794 i40e_clear_pxe_mode(hw);
1796 /* Unconfigure filter control */
1797 memset(&settings, 0, sizeof(settings));
1798 ret = i40e_set_filter_control(hw, &settings);
1800 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1803 /* Disable flow control */
1804 hw->fc.requested_mode = I40E_FC_NONE;
1805 i40e_set_fc(hw, &aq_fail, TRUE);
1807 /* uninitialize pf host driver */
1808 i40e_pf_host_uninit(dev);
1810 /* disable uio intr before callback unregister */
1811 rte_intr_disable(intr_handle);
1813 /* unregister callback func to eal lib */
1815 ret = rte_intr_callback_unregister(intr_handle,
1816 i40e_dev_interrupt_handler, dev);
1819 } else if (ret != -EAGAIN) {
1821 "intr callback unregister failed: %d",
1825 i40e_msec_delay(500);
1826 } while (retries++ < 5);
1828 i40e_rm_ethtype_filter_list(pf);
1829 i40e_rm_tunnel_filter_list(pf);
1830 i40e_rm_fdir_filter_list(pf);
1832 /* Remove all flows */
1833 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1834 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1838 /* Remove all Traffic Manager configuration */
1839 i40e_tm_conf_uninit(dev);
1845 i40e_dev_configure(struct rte_eth_dev *dev)
1847 struct i40e_adapter *ad =
1848 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1849 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1851 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1854 ret = i40e_dev_sync_phy_type(hw);
1858 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1859 * bulk allocation or vector Rx preconditions we will reset it.
1861 ad->rx_bulk_alloc_allowed = true;
1862 ad->rx_vec_allowed = true;
1863 ad->tx_simple_allowed = true;
1864 ad->tx_vec_allowed = true;
1866 /* Only legacy filter API needs the following fdir config. So when the
1867 * legacy filter API is deprecated, the following codes should also be
1870 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1871 ret = i40e_fdir_setup(pf);
1872 if (ret != I40E_SUCCESS) {
1873 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1876 ret = i40e_fdir_configure(dev);
1878 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1882 i40e_fdir_teardown(pf);
1884 ret = i40e_dev_init_vlan(dev);
1889 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1890 * RSS setting have different requirements.
1891 * General PMD driver call sequence are NIC init, configure,
1892 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1893 * will try to lookup the VSI that specific queue belongs to if VMDQ
1894 * applicable. So, VMDQ setting has to be done before
1895 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1896 * For RSS setting, it will try to calculate actual configured RX queue
1897 * number, which will be available after rx_queue_setup(). dev_start()
1898 * function is good to place RSS setup.
1900 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1901 ret = i40e_vmdq_setup(dev);
1906 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1907 ret = i40e_dcb_setup(dev);
1909 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1914 TAILQ_INIT(&pf->flow_list);
1919 /* need to release vmdq resource if exists */
1920 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1921 i40e_vsi_release(pf->vmdq[i].vsi);
1922 pf->vmdq[i].vsi = NULL;
1927 /* Need to release fdir resource if exists.
1928 * Only legacy filter API needs the following fdir config. So when the
1929 * legacy filter API is deprecated, the following code should also be
1932 i40e_fdir_teardown(pf);
1937 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1939 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1940 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1941 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1942 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1943 uint16_t msix_vect = vsi->msix_intr;
1946 for (i = 0; i < vsi->nb_qps; i++) {
1947 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1948 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1952 if (vsi->type != I40E_VSI_SRIOV) {
1953 if (!rte_intr_allow_others(intr_handle)) {
1954 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1955 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1957 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1960 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1961 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1963 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1968 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1969 vsi->user_param + (msix_vect - 1);
1971 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1972 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1974 I40E_WRITE_FLUSH(hw);
1978 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1979 int base_queue, int nb_queue,
1984 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1985 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1987 /* Bind all RX queues to allocated MSIX interrupt */
1988 for (i = 0; i < nb_queue; i++) {
1989 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1990 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1991 ((base_queue + i + 1) <<
1992 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1993 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1994 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1996 if (i == nb_queue - 1)
1997 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1998 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2001 /* Write first RX queue to Link list register as the head element */
2002 if (vsi->type != I40E_VSI_SRIOV) {
2004 i40e_calc_itr_interval(1, pf->support_multi_driver);
2006 if (msix_vect == I40E_MISC_VEC_ID) {
2007 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2009 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2011 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2013 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2016 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2018 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2020 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2022 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2029 if (msix_vect == I40E_MISC_VEC_ID) {
2031 I40E_VPINT_LNKLST0(vsi->user_param),
2033 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2035 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2037 /* num_msix_vectors_vf needs to minus irq0 */
2038 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2039 vsi->user_param + (msix_vect - 1);
2041 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2043 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2045 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2049 I40E_WRITE_FLUSH(hw);
2053 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2055 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2056 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2059 uint16_t msix_vect = vsi->msix_intr;
2060 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2061 uint16_t queue_idx = 0;
2065 for (i = 0; i < vsi->nb_qps; i++) {
2066 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2067 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2070 /* VF bind interrupt */
2071 if (vsi->type == I40E_VSI_SRIOV) {
2072 __vsi_queues_bind_intr(vsi, msix_vect,
2073 vsi->base_queue, vsi->nb_qps,
2078 /* PF & VMDq bind interrupt */
2079 if (rte_intr_dp_is_en(intr_handle)) {
2080 if (vsi->type == I40E_VSI_MAIN) {
2083 } else if (vsi->type == I40E_VSI_VMDQ2) {
2084 struct i40e_vsi *main_vsi =
2085 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2086 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2091 for (i = 0; i < vsi->nb_used_qps; i++) {
2093 if (!rte_intr_allow_others(intr_handle))
2094 /* allow to share MISC_VEC_ID */
2095 msix_vect = I40E_MISC_VEC_ID;
2097 /* no enough msix_vect, map all to one */
2098 __vsi_queues_bind_intr(vsi, msix_vect,
2099 vsi->base_queue + i,
2100 vsi->nb_used_qps - i,
2102 for (; !!record && i < vsi->nb_used_qps; i++)
2103 intr_handle->intr_vec[queue_idx + i] =
2107 /* 1:1 queue/msix_vect mapping */
2108 __vsi_queues_bind_intr(vsi, msix_vect,
2109 vsi->base_queue + i, 1,
2112 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2120 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2122 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2123 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2124 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2125 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2126 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2127 uint16_t msix_intr, i;
2129 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2130 for (i = 0; i < vsi->nb_msix; i++) {
2131 msix_intr = vsi->msix_intr + i;
2132 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2133 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2134 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2135 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2138 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2139 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2140 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2141 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2143 I40E_WRITE_FLUSH(hw);
2147 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2149 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2150 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2151 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2152 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2153 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2154 uint16_t msix_intr, i;
2156 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2157 for (i = 0; i < vsi->nb_msix; i++) {
2158 msix_intr = vsi->msix_intr + i;
2159 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2160 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2163 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2164 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2166 I40E_WRITE_FLUSH(hw);
2169 static inline uint8_t
2170 i40e_parse_link_speeds(uint16_t link_speeds)
2172 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2174 if (link_speeds & ETH_LINK_SPEED_40G)
2175 link_speed |= I40E_LINK_SPEED_40GB;
2176 if (link_speeds & ETH_LINK_SPEED_25G)
2177 link_speed |= I40E_LINK_SPEED_25GB;
2178 if (link_speeds & ETH_LINK_SPEED_20G)
2179 link_speed |= I40E_LINK_SPEED_20GB;
2180 if (link_speeds & ETH_LINK_SPEED_10G)
2181 link_speed |= I40E_LINK_SPEED_10GB;
2182 if (link_speeds & ETH_LINK_SPEED_1G)
2183 link_speed |= I40E_LINK_SPEED_1GB;
2184 if (link_speeds & ETH_LINK_SPEED_100M)
2185 link_speed |= I40E_LINK_SPEED_100MB;
2191 i40e_phy_conf_link(struct i40e_hw *hw,
2193 uint8_t force_speed,
2196 enum i40e_status_code status;
2197 struct i40e_aq_get_phy_abilities_resp phy_ab;
2198 struct i40e_aq_set_phy_config phy_conf;
2199 enum i40e_aq_phy_type cnt;
2200 uint8_t avail_speed;
2201 uint32_t phy_type_mask = 0;
2203 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2204 I40E_AQ_PHY_FLAG_PAUSE_RX |
2205 I40E_AQ_PHY_FLAG_PAUSE_RX |
2206 I40E_AQ_PHY_FLAG_LOW_POWER;
2209 /* To get phy capabilities of available speeds. */
2210 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2213 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2217 avail_speed = phy_ab.link_speed;
2219 /* To get the current phy config. */
2220 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2223 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2228 /* If link needs to go up and it is in autoneg mode the speed is OK,
2229 * no need to set up again.
2231 if (is_up && phy_ab.phy_type != 0 &&
2232 abilities & I40E_AQ_PHY_AN_ENABLED &&
2233 phy_ab.link_speed != 0)
2234 return I40E_SUCCESS;
2236 memset(&phy_conf, 0, sizeof(phy_conf));
2238 /* bits 0-2 use the values from get_phy_abilities_resp */
2240 abilities |= phy_ab.abilities & mask;
2242 phy_conf.abilities = abilities;
2244 /* If link needs to go up, but the force speed is not supported,
2245 * Warn users and config the default available speeds.
2247 if (is_up && !(force_speed & avail_speed)) {
2248 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2249 phy_conf.link_speed = avail_speed;
2251 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2254 /* PHY type mask needs to include each type except PHY type extension */
2255 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2256 phy_type_mask |= 1 << cnt;
2258 /* use get_phy_abilities_resp value for the rest */
2259 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2260 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2261 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2262 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2263 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2264 phy_conf.eee_capability = phy_ab.eee_capability;
2265 phy_conf.eeer = phy_ab.eeer_val;
2266 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2268 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2269 phy_ab.abilities, phy_ab.link_speed);
2270 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2271 phy_conf.abilities, phy_conf.link_speed);
2273 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2277 return I40E_SUCCESS;
2281 i40e_apply_link_speed(struct rte_eth_dev *dev)
2284 uint8_t abilities = 0;
2285 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2286 struct rte_eth_conf *conf = &dev->data->dev_conf;
2288 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2289 conf->link_speeds = ETH_LINK_SPEED_40G |
2290 ETH_LINK_SPEED_25G |
2291 ETH_LINK_SPEED_20G |
2292 ETH_LINK_SPEED_10G |
2294 ETH_LINK_SPEED_100M;
2296 speed = i40e_parse_link_speeds(conf->link_speeds);
2297 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2298 I40E_AQ_PHY_AN_ENABLED |
2299 I40E_AQ_PHY_LINK_ENABLED;
2301 return i40e_phy_conf_link(hw, abilities, speed, true);
2305 i40e_dev_start(struct rte_eth_dev *dev)
2307 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2308 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2309 struct i40e_vsi *main_vsi = pf->main_vsi;
2311 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2312 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2313 uint32_t intr_vector = 0;
2314 struct i40e_vsi *vsi;
2316 hw->adapter_stopped = 0;
2318 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2320 "Invalid link_speeds for port %u, autonegotiation disabled",
2321 dev->data->port_id);
2325 rte_intr_disable(intr_handle);
2327 if ((rte_intr_cap_multiple(intr_handle) ||
2328 !RTE_ETH_DEV_SRIOV(dev).active) &&
2329 dev->data->dev_conf.intr_conf.rxq != 0) {
2330 intr_vector = dev->data->nb_rx_queues;
2331 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2336 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2337 intr_handle->intr_vec =
2338 rte_zmalloc("intr_vec",
2339 dev->data->nb_rx_queues * sizeof(int),
2341 if (!intr_handle->intr_vec) {
2343 "Failed to allocate %d rx_queues intr_vec",
2344 dev->data->nb_rx_queues);
2349 /* Initialize VSI */
2350 ret = i40e_dev_rxtx_init(pf);
2351 if (ret != I40E_SUCCESS) {
2352 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2356 /* Map queues with MSIX interrupt */
2357 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2358 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2359 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2360 i40e_vsi_enable_queues_intr(main_vsi);
2362 /* Map VMDQ VSI queues with MSIX interrupt */
2363 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2364 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2365 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2366 I40E_ITR_INDEX_DEFAULT);
2367 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2370 /* enable FDIR MSIX interrupt */
2371 if (pf->fdir.fdir_vsi) {
2372 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2373 I40E_ITR_INDEX_NONE);
2374 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2377 /* Enable all queues which have been configured */
2378 ret = i40e_dev_switch_queues(pf, TRUE);
2379 if (ret != I40E_SUCCESS) {
2380 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2384 /* Enable receiving broadcast packets */
2385 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2386 if (ret != I40E_SUCCESS)
2387 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2389 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2390 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2392 if (ret != I40E_SUCCESS)
2393 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2396 /* Enable the VLAN promiscuous mode. */
2398 for (i = 0; i < pf->vf_num; i++) {
2399 vsi = pf->vfs[i].vsi;
2400 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2405 /* Enable mac loopback mode */
2406 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2407 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2408 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2409 if (ret != I40E_SUCCESS) {
2410 PMD_DRV_LOG(ERR, "fail to set loopback link");
2415 /* Apply link configure */
2416 ret = i40e_apply_link_speed(dev);
2417 if (I40E_SUCCESS != ret) {
2418 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2422 if (!rte_intr_allow_others(intr_handle)) {
2423 rte_intr_callback_unregister(intr_handle,
2424 i40e_dev_interrupt_handler,
2426 /* configure and enable device interrupt */
2427 i40e_pf_config_irq0(hw, FALSE);
2428 i40e_pf_enable_irq0(hw);
2430 if (dev->data->dev_conf.intr_conf.lsc != 0)
2432 "lsc won't enable because of no intr multiplex");
2434 ret = i40e_aq_set_phy_int_mask(hw,
2435 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2436 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2437 I40E_AQ_EVENT_MEDIA_NA), NULL);
2438 if (ret != I40E_SUCCESS)
2439 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2441 /* Call get_link_info aq commond to enable/disable LSE */
2442 i40e_dev_link_update(dev, 0);
2445 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2446 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2447 i40e_dev_alarm_handler, dev);
2449 /* enable uio intr after callback register */
2450 rte_intr_enable(intr_handle);
2453 i40e_filter_restore(pf);
2455 if (pf->tm_conf.root && !pf->tm_conf.committed)
2456 PMD_DRV_LOG(WARNING,
2457 "please call hierarchy_commit() "
2458 "before starting the port");
2460 return I40E_SUCCESS;
2463 i40e_dev_switch_queues(pf, FALSE);
2464 i40e_dev_clear_queues(dev);
2470 i40e_dev_stop(struct rte_eth_dev *dev)
2472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2473 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2474 struct i40e_vsi *main_vsi = pf->main_vsi;
2475 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2476 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2479 if (hw->adapter_stopped == 1)
2482 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2483 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2484 rte_intr_enable(intr_handle);
2487 /* Disable all queues */
2488 i40e_dev_switch_queues(pf, FALSE);
2490 /* un-map queues with interrupt registers */
2491 i40e_vsi_disable_queues_intr(main_vsi);
2492 i40e_vsi_queues_unbind_intr(main_vsi);
2494 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2495 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2496 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2499 if (pf->fdir.fdir_vsi) {
2500 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2501 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2503 /* Clear all queues and release memory */
2504 i40e_dev_clear_queues(dev);
2507 i40e_dev_set_link_down(dev);
2509 if (!rte_intr_allow_others(intr_handle))
2510 /* resume to the default handler */
2511 rte_intr_callback_register(intr_handle,
2512 i40e_dev_interrupt_handler,
2515 /* Clean datapath event and queue/vec mapping */
2516 rte_intr_efd_disable(intr_handle);
2517 if (intr_handle->intr_vec) {
2518 rte_free(intr_handle->intr_vec);
2519 intr_handle->intr_vec = NULL;
2522 /* reset hierarchy commit */
2523 pf->tm_conf.committed = false;
2525 hw->adapter_stopped = 1;
2527 pf->adapter->rss_reta_updated = 0;
2531 i40e_dev_close(struct rte_eth_dev *dev)
2533 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2534 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2535 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2536 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2537 struct i40e_mirror_rule *p_mirror;
2542 PMD_INIT_FUNC_TRACE();
2546 /* Remove all mirror rules */
2547 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2548 ret = i40e_aq_del_mirror_rule(hw,
2549 pf->main_vsi->veb->seid,
2550 p_mirror->rule_type,
2552 p_mirror->num_entries,
2555 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2556 "status = %d, aq_err = %d.", ret,
2557 hw->aq.asq_last_status);
2559 /* remove mirror software resource anyway */
2560 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2562 pf->nb_mirror_rule--;
2565 i40e_dev_free_queues(dev);
2567 /* Disable interrupt */
2568 i40e_pf_disable_irq0(hw);
2569 rte_intr_disable(intr_handle);
2572 * Only legacy filter API needs the following fdir config. So when the
2573 * legacy filter API is deprecated, the following code should also be
2576 i40e_fdir_teardown(pf);
2578 /* shutdown and destroy the HMC */
2579 i40e_shutdown_lan_hmc(hw);
2581 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2582 i40e_vsi_release(pf->vmdq[i].vsi);
2583 pf->vmdq[i].vsi = NULL;
2588 /* release all the existing VSIs and VEBs */
2589 i40e_vsi_release(pf->main_vsi);
2591 /* shutdown the adminq */
2592 i40e_aq_queue_shutdown(hw, true);
2593 i40e_shutdown_adminq(hw);
2595 i40e_res_pool_destroy(&pf->qp_pool);
2596 i40e_res_pool_destroy(&pf->msix_pool);
2598 /* Disable flexible payload in global configuration */
2599 if (!pf->support_multi_driver)
2600 i40e_flex_payload_reg_set_default(hw);
2602 /* force a PF reset to clean anything leftover */
2603 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2604 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2605 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2606 I40E_WRITE_FLUSH(hw);
2608 hw->adapter_closed = 1;
2612 * Reset PF device only to re-initialize resources in PMD layer
2615 i40e_dev_reset(struct rte_eth_dev *dev)
2619 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2620 * its VF to make them align with it. The detailed notification
2621 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2622 * To avoid unexpected behavior in VF, currently reset of PF with
2623 * SR-IOV activation is not supported. It might be supported later.
2625 if (dev->data->sriov.active)
2628 ret = eth_i40e_dev_uninit(dev);
2632 ret = eth_i40e_dev_init(dev, NULL);
2638 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2640 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2641 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642 struct i40e_vsi *vsi = pf->main_vsi;
2645 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2647 if (status != I40E_SUCCESS) {
2648 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2652 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2654 if (status != I40E_SUCCESS) {
2655 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2656 /* Rollback unicast promiscuous mode */
2657 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2666 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2668 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2669 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2670 struct i40e_vsi *vsi = pf->main_vsi;
2673 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2675 if (status != I40E_SUCCESS) {
2676 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2680 /* must remain in all_multicast mode */
2681 if (dev->data->all_multicast == 1)
2684 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2686 if (status != I40E_SUCCESS) {
2687 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2688 /* Rollback unicast promiscuous mode */
2689 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2698 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2700 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2701 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2702 struct i40e_vsi *vsi = pf->main_vsi;
2705 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2706 if (ret != I40E_SUCCESS) {
2707 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2715 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2717 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2718 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2719 struct i40e_vsi *vsi = pf->main_vsi;
2722 if (dev->data->promiscuous == 1)
2723 return 0; /* must remain in all_multicast mode */
2725 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2726 vsi->seid, FALSE, NULL);
2727 if (ret != I40E_SUCCESS) {
2728 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2736 * Set device link up.
2739 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2741 /* re-apply link speed setting */
2742 return i40e_apply_link_speed(dev);
2746 * Set device link down.
2749 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2751 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2752 uint8_t abilities = 0;
2753 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2755 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2756 return i40e_phy_conf_link(hw, abilities, speed, false);
2759 static __rte_always_inline void
2760 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2762 /* Link status registers and values*/
2763 #define I40E_PRTMAC_LINKSTA 0x001E2420
2764 #define I40E_REG_LINK_UP 0x40000080
2765 #define I40E_PRTMAC_MACC 0x001E24E0
2766 #define I40E_REG_MACC_25GB 0x00020000
2767 #define I40E_REG_SPEED_MASK 0x38000000
2768 #define I40E_REG_SPEED_0 0x00000000
2769 #define I40E_REG_SPEED_1 0x08000000
2770 #define I40E_REG_SPEED_2 0x10000000
2771 #define I40E_REG_SPEED_3 0x18000000
2772 #define I40E_REG_SPEED_4 0x20000000
2773 uint32_t link_speed;
2776 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2777 link_speed = reg_val & I40E_REG_SPEED_MASK;
2778 reg_val &= I40E_REG_LINK_UP;
2779 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2781 if (unlikely(link->link_status == 0))
2784 /* Parse the link status */
2785 switch (link_speed) {
2786 case I40E_REG_SPEED_0:
2787 link->link_speed = ETH_SPEED_NUM_100M;
2789 case I40E_REG_SPEED_1:
2790 link->link_speed = ETH_SPEED_NUM_1G;
2792 case I40E_REG_SPEED_2:
2793 if (hw->mac.type == I40E_MAC_X722)
2794 link->link_speed = ETH_SPEED_NUM_2_5G;
2796 link->link_speed = ETH_SPEED_NUM_10G;
2798 case I40E_REG_SPEED_3:
2799 if (hw->mac.type == I40E_MAC_X722) {
2800 link->link_speed = ETH_SPEED_NUM_5G;
2802 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2804 if (reg_val & I40E_REG_MACC_25GB)
2805 link->link_speed = ETH_SPEED_NUM_25G;
2807 link->link_speed = ETH_SPEED_NUM_40G;
2810 case I40E_REG_SPEED_4:
2811 if (hw->mac.type == I40E_MAC_X722)
2812 link->link_speed = ETH_SPEED_NUM_10G;
2814 link->link_speed = ETH_SPEED_NUM_20G;
2817 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2822 static __rte_always_inline void
2823 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2824 bool enable_lse, int wait_to_complete)
2826 #define CHECK_INTERVAL 100 /* 100ms */
2827 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2828 uint32_t rep_cnt = MAX_REPEAT_TIME;
2829 struct i40e_link_status link_status;
2832 memset(&link_status, 0, sizeof(link_status));
2835 memset(&link_status, 0, sizeof(link_status));
2837 /* Get link status information from hardware */
2838 status = i40e_aq_get_link_info(hw, enable_lse,
2839 &link_status, NULL);
2840 if (unlikely(status != I40E_SUCCESS)) {
2841 link->link_speed = ETH_SPEED_NUM_100M;
2842 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2843 PMD_DRV_LOG(ERR, "Failed to get link info");
2847 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2848 if (!wait_to_complete || link->link_status)
2851 rte_delay_ms(CHECK_INTERVAL);
2852 } while (--rep_cnt);
2854 /* Parse the link status */
2855 switch (link_status.link_speed) {
2856 case I40E_LINK_SPEED_100MB:
2857 link->link_speed = ETH_SPEED_NUM_100M;
2859 case I40E_LINK_SPEED_1GB:
2860 link->link_speed = ETH_SPEED_NUM_1G;
2862 case I40E_LINK_SPEED_10GB:
2863 link->link_speed = ETH_SPEED_NUM_10G;
2865 case I40E_LINK_SPEED_20GB:
2866 link->link_speed = ETH_SPEED_NUM_20G;
2868 case I40E_LINK_SPEED_25GB:
2869 link->link_speed = ETH_SPEED_NUM_25G;
2871 case I40E_LINK_SPEED_40GB:
2872 link->link_speed = ETH_SPEED_NUM_40G;
2875 link->link_speed = ETH_SPEED_NUM_100M;
2881 i40e_dev_link_update(struct rte_eth_dev *dev,
2882 int wait_to_complete)
2884 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2885 struct rte_eth_link link;
2886 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2889 memset(&link, 0, sizeof(link));
2891 /* i40e uses full duplex only */
2892 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2893 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2894 ETH_LINK_SPEED_FIXED);
2896 if (!wait_to_complete && !enable_lse)
2897 update_link_reg(hw, &link);
2899 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2901 ret = rte_eth_linkstatus_set(dev, &link);
2902 i40e_notify_all_vfs_link_status(dev);
2907 /* Get all the statistics of a VSI */
2909 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2911 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2912 struct i40e_eth_stats *nes = &vsi->eth_stats;
2913 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2914 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2916 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2917 vsi->offset_loaded, &oes->rx_bytes,
2919 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2920 vsi->offset_loaded, &oes->rx_unicast,
2922 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2923 vsi->offset_loaded, &oes->rx_multicast,
2924 &nes->rx_multicast);
2925 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2926 vsi->offset_loaded, &oes->rx_broadcast,
2927 &nes->rx_broadcast);
2928 /* exclude CRC bytes */
2929 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2930 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2932 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2933 &oes->rx_discards, &nes->rx_discards);
2934 /* GLV_REPC not supported */
2935 /* GLV_RMPC not supported */
2936 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2937 &oes->rx_unknown_protocol,
2938 &nes->rx_unknown_protocol);
2939 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2940 vsi->offset_loaded, &oes->tx_bytes,
2942 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2943 vsi->offset_loaded, &oes->tx_unicast,
2945 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2946 vsi->offset_loaded, &oes->tx_multicast,
2947 &nes->tx_multicast);
2948 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2949 vsi->offset_loaded, &oes->tx_broadcast,
2950 &nes->tx_broadcast);
2951 /* GLV_TDPC not supported */
2952 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2953 &oes->tx_errors, &nes->tx_errors);
2954 vsi->offset_loaded = true;
2956 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2958 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2959 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2960 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2961 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2962 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2963 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2964 nes->rx_unknown_protocol);
2965 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2966 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2967 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2968 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2969 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2970 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2971 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2976 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2979 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2980 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2982 /* Get rx/tx bytes of internal transfer packets */
2983 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2984 I40E_GLV_GORCL(hw->port),
2986 &pf->internal_stats_offset.rx_bytes,
2987 &pf->internal_stats.rx_bytes);
2989 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2990 I40E_GLV_GOTCL(hw->port),
2992 &pf->internal_stats_offset.tx_bytes,
2993 &pf->internal_stats.tx_bytes);
2994 /* Get total internal rx packet count */
2995 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2996 I40E_GLV_UPRCL(hw->port),
2998 &pf->internal_stats_offset.rx_unicast,
2999 &pf->internal_stats.rx_unicast);
3000 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3001 I40E_GLV_MPRCL(hw->port),
3003 &pf->internal_stats_offset.rx_multicast,
3004 &pf->internal_stats.rx_multicast);
3005 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3006 I40E_GLV_BPRCL(hw->port),
3008 &pf->internal_stats_offset.rx_broadcast,
3009 &pf->internal_stats.rx_broadcast);
3010 /* Get total internal tx packet count */
3011 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3012 I40E_GLV_UPTCL(hw->port),
3014 &pf->internal_stats_offset.tx_unicast,
3015 &pf->internal_stats.tx_unicast);
3016 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3017 I40E_GLV_MPTCL(hw->port),
3019 &pf->internal_stats_offset.tx_multicast,
3020 &pf->internal_stats.tx_multicast);
3021 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3022 I40E_GLV_BPTCL(hw->port),
3024 &pf->internal_stats_offset.tx_broadcast,
3025 &pf->internal_stats.tx_broadcast);
3027 /* exclude CRC size */
3028 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3029 pf->internal_stats.rx_multicast +
3030 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3032 /* Get statistics of struct i40e_eth_stats */
3033 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3034 I40E_GLPRT_GORCL(hw->port),
3035 pf->offset_loaded, &os->eth.rx_bytes,
3037 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3038 I40E_GLPRT_UPRCL(hw->port),
3039 pf->offset_loaded, &os->eth.rx_unicast,
3040 &ns->eth.rx_unicast);
3041 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3042 I40E_GLPRT_MPRCL(hw->port),
3043 pf->offset_loaded, &os->eth.rx_multicast,
3044 &ns->eth.rx_multicast);
3045 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3046 I40E_GLPRT_BPRCL(hw->port),
3047 pf->offset_loaded, &os->eth.rx_broadcast,
3048 &ns->eth.rx_broadcast);
3049 /* Workaround: CRC size should not be included in byte statistics,
3050 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3053 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3054 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3056 /* exclude internal rx bytes
3057 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3058 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3060 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3062 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3063 ns->eth.rx_bytes = 0;
3065 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3067 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3068 ns->eth.rx_unicast = 0;
3070 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3072 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3073 ns->eth.rx_multicast = 0;
3075 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3077 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3078 ns->eth.rx_broadcast = 0;
3080 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3082 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3083 pf->offset_loaded, &os->eth.rx_discards,
3084 &ns->eth.rx_discards);
3085 /* GLPRT_REPC not supported */
3086 /* GLPRT_RMPC not supported */
3087 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3089 &os->eth.rx_unknown_protocol,
3090 &ns->eth.rx_unknown_protocol);
3091 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3092 I40E_GLPRT_GOTCL(hw->port),
3093 pf->offset_loaded, &os->eth.tx_bytes,
3095 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3096 I40E_GLPRT_UPTCL(hw->port),
3097 pf->offset_loaded, &os->eth.tx_unicast,
3098 &ns->eth.tx_unicast);
3099 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3100 I40E_GLPRT_MPTCL(hw->port),
3101 pf->offset_loaded, &os->eth.tx_multicast,
3102 &ns->eth.tx_multicast);
3103 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3104 I40E_GLPRT_BPTCL(hw->port),
3105 pf->offset_loaded, &os->eth.tx_broadcast,
3106 &ns->eth.tx_broadcast);
3107 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3108 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3110 /* exclude internal tx bytes
3111 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3112 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3114 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3116 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3117 ns->eth.tx_bytes = 0;
3119 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3121 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3122 ns->eth.tx_unicast = 0;
3124 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3126 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3127 ns->eth.tx_multicast = 0;
3129 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3131 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3132 ns->eth.tx_broadcast = 0;
3134 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3136 /* GLPRT_TEPC not supported */
3138 /* additional port specific stats */
3139 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3140 pf->offset_loaded, &os->tx_dropped_link_down,
3141 &ns->tx_dropped_link_down);
3142 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3143 pf->offset_loaded, &os->crc_errors,
3145 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3146 pf->offset_loaded, &os->illegal_bytes,
3147 &ns->illegal_bytes);
3148 /* GLPRT_ERRBC not supported */
3149 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3150 pf->offset_loaded, &os->mac_local_faults,
3151 &ns->mac_local_faults);
3152 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3153 pf->offset_loaded, &os->mac_remote_faults,
3154 &ns->mac_remote_faults);
3155 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3156 pf->offset_loaded, &os->rx_length_errors,
3157 &ns->rx_length_errors);
3158 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3159 pf->offset_loaded, &os->link_xon_rx,
3161 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3162 pf->offset_loaded, &os->link_xoff_rx,
3164 for (i = 0; i < 8; i++) {
3165 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3167 &os->priority_xon_rx[i],
3168 &ns->priority_xon_rx[i]);
3169 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3171 &os->priority_xoff_rx[i],
3172 &ns->priority_xoff_rx[i]);
3174 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3175 pf->offset_loaded, &os->link_xon_tx,
3177 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3178 pf->offset_loaded, &os->link_xoff_tx,
3180 for (i = 0; i < 8; i++) {
3181 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3183 &os->priority_xon_tx[i],
3184 &ns->priority_xon_tx[i]);
3185 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3187 &os->priority_xoff_tx[i],
3188 &ns->priority_xoff_tx[i]);
3189 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3191 &os->priority_xon_2_xoff[i],
3192 &ns->priority_xon_2_xoff[i]);
3194 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3195 I40E_GLPRT_PRC64L(hw->port),
3196 pf->offset_loaded, &os->rx_size_64,
3198 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3199 I40E_GLPRT_PRC127L(hw->port),
3200 pf->offset_loaded, &os->rx_size_127,
3202 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3203 I40E_GLPRT_PRC255L(hw->port),
3204 pf->offset_loaded, &os->rx_size_255,
3206 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3207 I40E_GLPRT_PRC511L(hw->port),
3208 pf->offset_loaded, &os->rx_size_511,
3210 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3211 I40E_GLPRT_PRC1023L(hw->port),
3212 pf->offset_loaded, &os->rx_size_1023,
3214 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3215 I40E_GLPRT_PRC1522L(hw->port),
3216 pf->offset_loaded, &os->rx_size_1522,
3218 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3219 I40E_GLPRT_PRC9522L(hw->port),
3220 pf->offset_loaded, &os->rx_size_big,
3222 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3223 pf->offset_loaded, &os->rx_undersize,
3225 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3226 pf->offset_loaded, &os->rx_fragments,
3228 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3229 pf->offset_loaded, &os->rx_oversize,
3231 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3232 pf->offset_loaded, &os->rx_jabber,
3234 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3235 I40E_GLPRT_PTC64L(hw->port),
3236 pf->offset_loaded, &os->tx_size_64,
3238 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3239 I40E_GLPRT_PTC127L(hw->port),
3240 pf->offset_loaded, &os->tx_size_127,
3242 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3243 I40E_GLPRT_PTC255L(hw->port),
3244 pf->offset_loaded, &os->tx_size_255,
3246 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3247 I40E_GLPRT_PTC511L(hw->port),
3248 pf->offset_loaded, &os->tx_size_511,
3250 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3251 I40E_GLPRT_PTC1023L(hw->port),
3252 pf->offset_loaded, &os->tx_size_1023,
3254 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3255 I40E_GLPRT_PTC1522L(hw->port),
3256 pf->offset_loaded, &os->tx_size_1522,
3258 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3259 I40E_GLPRT_PTC9522L(hw->port),
3260 pf->offset_loaded, &os->tx_size_big,
3262 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3264 &os->fd_sb_match, &ns->fd_sb_match);
3265 /* GLPRT_MSPDC not supported */
3266 /* GLPRT_XEC not supported */
3268 pf->offset_loaded = true;
3271 i40e_update_vsi_stats(pf->main_vsi);
3274 /* Get all statistics of a port */
3276 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3278 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3279 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3280 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3281 struct i40e_vsi *vsi;
3284 /* call read registers - updates values, now write them to struct */
3285 i40e_read_stats_registers(pf, hw);
3287 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3288 pf->main_vsi->eth_stats.rx_multicast +
3289 pf->main_vsi->eth_stats.rx_broadcast -
3290 pf->main_vsi->eth_stats.rx_discards;
3291 stats->opackets = ns->eth.tx_unicast +
3292 ns->eth.tx_multicast +
3293 ns->eth.tx_broadcast;
3294 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3295 stats->obytes = ns->eth.tx_bytes;
3296 stats->oerrors = ns->eth.tx_errors +
3297 pf->main_vsi->eth_stats.tx_errors;
3300 stats->imissed = ns->eth.rx_discards +
3301 pf->main_vsi->eth_stats.rx_discards;
3302 stats->ierrors = ns->crc_errors +
3303 ns->rx_length_errors + ns->rx_undersize +
3304 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3307 for (i = 0; i < pf->vf_num; i++) {
3308 vsi = pf->vfs[i].vsi;
3309 i40e_update_vsi_stats(vsi);
3311 stats->ipackets += (vsi->eth_stats.rx_unicast +
3312 vsi->eth_stats.rx_multicast +
3313 vsi->eth_stats.rx_broadcast -
3314 vsi->eth_stats.rx_discards);
3315 stats->ibytes += vsi->eth_stats.rx_bytes;
3316 stats->oerrors += vsi->eth_stats.tx_errors;
3317 stats->imissed += vsi->eth_stats.rx_discards;
3321 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3322 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3323 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3324 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3325 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3326 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3327 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3328 ns->eth.rx_unknown_protocol);
3329 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3330 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3331 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3332 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3333 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3334 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3336 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3337 ns->tx_dropped_link_down);
3338 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3339 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3341 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3342 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3343 ns->mac_local_faults);
3344 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3345 ns->mac_remote_faults);
3346 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3347 ns->rx_length_errors);
3348 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3349 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3350 for (i = 0; i < 8; i++) {
3351 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3352 i, ns->priority_xon_rx[i]);
3353 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3354 i, ns->priority_xoff_rx[i]);
3356 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3357 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3358 for (i = 0; i < 8; i++) {
3359 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3360 i, ns->priority_xon_tx[i]);
3361 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3362 i, ns->priority_xoff_tx[i]);
3363 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3364 i, ns->priority_xon_2_xoff[i]);
3366 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3367 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3368 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3369 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3370 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3371 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3372 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3373 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3374 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3375 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3376 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3377 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3378 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3379 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3380 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3381 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3382 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3383 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3384 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3385 ns->mac_short_packet_dropped);
3386 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3387 ns->checksum_error);
3388 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3389 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3393 /* Reset the statistics */
3395 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3397 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3398 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3400 /* Mark PF and VSI stats to update the offset, aka "reset" */
3401 pf->offset_loaded = false;
3403 pf->main_vsi->offset_loaded = false;
3405 /* read the stats, reading current register values into offset */
3406 i40e_read_stats_registers(pf, hw);
3412 i40e_xstats_calc_num(void)
3414 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3415 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3416 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3419 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3420 struct rte_eth_xstat_name *xstats_names,
3421 __rte_unused unsigned limit)
3426 if (xstats_names == NULL)
3427 return i40e_xstats_calc_num();
3429 /* Note: limit checked in rte_eth_xstats_names() */
3431 /* Get stats from i40e_eth_stats struct */
3432 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3433 strlcpy(xstats_names[count].name,
3434 rte_i40e_stats_strings[i].name,
3435 sizeof(xstats_names[count].name));
3439 /* Get individiual stats from i40e_hw_port struct */
3440 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3441 strlcpy(xstats_names[count].name,
3442 rte_i40e_hw_port_strings[i].name,
3443 sizeof(xstats_names[count].name));
3447 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3448 for (prio = 0; prio < 8; prio++) {
3449 snprintf(xstats_names[count].name,
3450 sizeof(xstats_names[count].name),
3451 "rx_priority%u_%s", prio,
3452 rte_i40e_rxq_prio_strings[i].name);
3457 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3458 for (prio = 0; prio < 8; prio++) {
3459 snprintf(xstats_names[count].name,
3460 sizeof(xstats_names[count].name),
3461 "tx_priority%u_%s", prio,
3462 rte_i40e_txq_prio_strings[i].name);
3470 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3473 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3474 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3475 unsigned i, count, prio;
3476 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3478 count = i40e_xstats_calc_num();
3482 i40e_read_stats_registers(pf, hw);
3489 /* Get stats from i40e_eth_stats struct */
3490 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3491 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3492 rte_i40e_stats_strings[i].offset);
3493 xstats[count].id = count;
3497 /* Get individiual stats from i40e_hw_port struct */
3498 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3499 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3500 rte_i40e_hw_port_strings[i].offset);
3501 xstats[count].id = count;
3505 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3506 for (prio = 0; prio < 8; prio++) {
3507 xstats[count].value =
3508 *(uint64_t *)(((char *)hw_stats) +
3509 rte_i40e_rxq_prio_strings[i].offset +
3510 (sizeof(uint64_t) * prio));
3511 xstats[count].id = count;
3516 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3517 for (prio = 0; prio < 8; prio++) {
3518 xstats[count].value =
3519 *(uint64_t *)(((char *)hw_stats) +
3520 rte_i40e_txq_prio_strings[i].offset +
3521 (sizeof(uint64_t) * prio));
3522 xstats[count].id = count;
3531 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3533 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539 full_ver = hw->nvm.oem_ver;
3540 ver = (u8)(full_ver >> 24);
3541 build = (u16)((full_ver >> 8) & 0xffff);
3542 patch = (u8)(full_ver & 0xff);
3544 ret = snprintf(fw_version, fw_size,
3545 "%d.%d%d 0x%08x %d.%d.%d",
3546 ((hw->nvm.version >> 12) & 0xf),
3547 ((hw->nvm.version >> 4) & 0xff),
3548 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3551 ret += 1; /* add the size of '\0' */
3552 if (fw_size < (u32)ret)
3559 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3560 * the Rx data path does not hang if the FW LLDP is stopped.
3561 * return true if lldp need to stop
3562 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3565 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3568 char ver_str[64] = {0};
3569 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3571 i40e_fw_version_get(dev, ver_str, 64);
3572 nvm_ver = atof(ver_str);
3573 if ((hw->mac.type == I40E_MAC_X722 ||
3574 hw->mac.type == I40E_MAC_X722_VF) &&
3575 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3577 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3584 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3586 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3587 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3588 struct i40e_vsi *vsi = pf->main_vsi;
3589 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3591 dev_info->max_rx_queues = vsi->nb_qps;
3592 dev_info->max_tx_queues = vsi->nb_qps;
3593 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3594 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3595 dev_info->max_mac_addrs = vsi->max_macaddrs;
3596 dev_info->max_vfs = pci_dev->max_vfs;
3597 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3598 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3599 dev_info->rx_queue_offload_capa = 0;
3600 dev_info->rx_offload_capa =
3601 DEV_RX_OFFLOAD_VLAN_STRIP |
3602 DEV_RX_OFFLOAD_QINQ_STRIP |
3603 DEV_RX_OFFLOAD_IPV4_CKSUM |
3604 DEV_RX_OFFLOAD_UDP_CKSUM |
3605 DEV_RX_OFFLOAD_TCP_CKSUM |
3606 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3607 DEV_RX_OFFLOAD_KEEP_CRC |
3608 DEV_RX_OFFLOAD_SCATTER |
3609 DEV_RX_OFFLOAD_VLAN_EXTEND |
3610 DEV_RX_OFFLOAD_VLAN_FILTER |
3611 DEV_RX_OFFLOAD_JUMBO_FRAME;
3613 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3614 dev_info->tx_offload_capa =
3615 DEV_TX_OFFLOAD_VLAN_INSERT |
3616 DEV_TX_OFFLOAD_QINQ_INSERT |
3617 DEV_TX_OFFLOAD_IPV4_CKSUM |
3618 DEV_TX_OFFLOAD_UDP_CKSUM |
3619 DEV_TX_OFFLOAD_TCP_CKSUM |
3620 DEV_TX_OFFLOAD_SCTP_CKSUM |
3621 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3622 DEV_TX_OFFLOAD_TCP_TSO |
3623 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3624 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3625 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3626 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3627 DEV_TX_OFFLOAD_MULTI_SEGS |
3628 dev_info->tx_queue_offload_capa;
3629 dev_info->dev_capa =
3630 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3631 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3633 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3635 dev_info->reta_size = pf->hash_lut_size;
3636 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3638 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3640 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3641 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3642 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3644 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3649 dev_info->default_txconf = (struct rte_eth_txconf) {
3651 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3652 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3653 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3655 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3656 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3660 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3661 .nb_max = I40E_MAX_RING_DESC,
3662 .nb_min = I40E_MIN_RING_DESC,
3663 .nb_align = I40E_ALIGN_RING_DESC,
3666 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3667 .nb_max = I40E_MAX_RING_DESC,
3668 .nb_min = I40E_MIN_RING_DESC,
3669 .nb_align = I40E_ALIGN_RING_DESC,
3670 .nb_seg_max = I40E_TX_MAX_SEG,
3671 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3674 if (pf->flags & I40E_FLAG_VMDQ) {
3675 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3676 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3677 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3678 pf->max_nb_vmdq_vsi;
3679 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3680 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3681 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3684 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3686 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3687 dev_info->default_rxportconf.nb_queues = 2;
3688 dev_info->default_txportconf.nb_queues = 2;
3689 if (dev->data->nb_rx_queues == 1)
3690 dev_info->default_rxportconf.ring_size = 2048;
3692 dev_info->default_rxportconf.ring_size = 1024;
3693 if (dev->data->nb_tx_queues == 1)
3694 dev_info->default_txportconf.ring_size = 1024;
3696 dev_info->default_txportconf.ring_size = 512;
3698 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3700 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3701 dev_info->default_rxportconf.nb_queues = 1;
3702 dev_info->default_txportconf.nb_queues = 1;
3703 dev_info->default_rxportconf.ring_size = 256;
3704 dev_info->default_txportconf.ring_size = 256;
3707 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3708 dev_info->default_rxportconf.nb_queues = 1;
3709 dev_info->default_txportconf.nb_queues = 1;
3710 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3711 dev_info->default_rxportconf.ring_size = 512;
3712 dev_info->default_txportconf.ring_size = 256;
3714 dev_info->default_rxportconf.ring_size = 256;
3715 dev_info->default_txportconf.ring_size = 256;
3718 dev_info->default_rxportconf.burst_size = 32;
3719 dev_info->default_txportconf.burst_size = 32;
3725 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3727 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3728 struct i40e_vsi *vsi = pf->main_vsi;
3729 PMD_INIT_FUNC_TRACE();
3732 return i40e_vsi_add_vlan(vsi, vlan_id);
3734 return i40e_vsi_delete_vlan(vsi, vlan_id);
3738 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3739 enum rte_vlan_type vlan_type,
3740 uint16_t tpid, int qinq)
3742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3745 uint16_t reg_id = 3;
3749 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3753 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3755 if (ret != I40E_SUCCESS) {
3757 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3762 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3765 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3766 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3767 if (reg_r == reg_w) {
3768 PMD_DRV_LOG(DEBUG, "No need to write");
3772 ret = i40e_aq_debug_write_global_register(hw,
3773 I40E_GL_SWT_L2TAGCTRL(reg_id),
3775 if (ret != I40E_SUCCESS) {
3777 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3782 "Global register 0x%08x is changed with value 0x%08x",
3783 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3789 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3790 enum rte_vlan_type vlan_type,
3793 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3794 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3795 int qinq = dev->data->dev_conf.rxmode.offloads &
3796 DEV_RX_OFFLOAD_VLAN_EXTEND;
3799 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3800 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3801 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3803 "Unsupported vlan type.");
3807 if (pf->support_multi_driver) {
3808 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3812 /* 802.1ad frames ability is added in NVM API 1.7*/
3813 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3815 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3816 hw->first_tag = rte_cpu_to_le_16(tpid);
3817 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3818 hw->second_tag = rte_cpu_to_le_16(tpid);
3820 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3821 hw->second_tag = rte_cpu_to_le_16(tpid);
3823 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3824 if (ret != I40E_SUCCESS) {
3826 "Set switch config failed aq_err: %d",
3827 hw->aq.asq_last_status);
3831 /* If NVM API < 1.7, keep the register setting */
3832 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3839 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3841 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3842 struct i40e_vsi *vsi = pf->main_vsi;
3843 struct rte_eth_rxmode *rxmode;
3845 rxmode = &dev->data->dev_conf.rxmode;
3846 if (mask & ETH_VLAN_FILTER_MASK) {
3847 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3848 i40e_vsi_config_vlan_filter(vsi, TRUE);
3850 i40e_vsi_config_vlan_filter(vsi, FALSE);
3853 if (mask & ETH_VLAN_STRIP_MASK) {
3854 /* Enable or disable VLAN stripping */
3855 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3856 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3858 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3861 if (mask & ETH_VLAN_EXTEND_MASK) {
3862 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3863 i40e_vsi_config_double_vlan(vsi, TRUE);
3864 /* Set global registers with default ethertype. */
3865 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3866 RTE_ETHER_TYPE_VLAN);
3867 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3868 RTE_ETHER_TYPE_VLAN);
3871 i40e_vsi_config_double_vlan(vsi, FALSE);
3878 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3879 __rte_unused uint16_t queue,
3880 __rte_unused int on)
3882 PMD_INIT_FUNC_TRACE();
3886 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3888 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3889 struct i40e_vsi *vsi = pf->main_vsi;
3890 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3891 struct i40e_vsi_vlan_pvid_info info;
3893 memset(&info, 0, sizeof(info));
3896 info.config.pvid = pvid;
3898 info.config.reject.tagged =
3899 data->dev_conf.txmode.hw_vlan_reject_tagged;
3900 info.config.reject.untagged =
3901 data->dev_conf.txmode.hw_vlan_reject_untagged;
3904 return i40e_vsi_vlan_pvid_set(vsi, &info);
3908 i40e_dev_led_on(struct rte_eth_dev *dev)
3910 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3911 uint32_t mode = i40e_led_get(hw);
3914 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3920 i40e_dev_led_off(struct rte_eth_dev *dev)
3922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3923 uint32_t mode = i40e_led_get(hw);
3926 i40e_led_set(hw, 0, false);
3932 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3937 fc_conf->pause_time = pf->fc_conf.pause_time;
3939 /* read out from register, in case they are modified by other port */
3940 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3941 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3942 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3943 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3945 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3946 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3948 /* Return current mode according to actual setting*/
3949 switch (hw->fc.current_mode) {
3951 fc_conf->mode = RTE_FC_FULL;
3953 case I40E_FC_TX_PAUSE:
3954 fc_conf->mode = RTE_FC_TX_PAUSE;
3956 case I40E_FC_RX_PAUSE:
3957 fc_conf->mode = RTE_FC_RX_PAUSE;
3961 fc_conf->mode = RTE_FC_NONE;
3968 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3970 uint32_t mflcn_reg, fctrl_reg, reg;
3971 uint32_t max_high_water;
3972 uint8_t i, aq_failure;
3976 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3977 [RTE_FC_NONE] = I40E_FC_NONE,
3978 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3979 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3980 [RTE_FC_FULL] = I40E_FC_FULL
3983 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3985 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3986 if ((fc_conf->high_water > max_high_water) ||
3987 (fc_conf->high_water < fc_conf->low_water)) {
3989 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3994 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3996 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3998 pf->fc_conf.pause_time = fc_conf->pause_time;
3999 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4000 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4002 PMD_INIT_FUNC_TRACE();
4004 /* All the link flow control related enable/disable register
4005 * configuration is handle by the F/W
4007 err = i40e_set_fc(hw, &aq_failure, true);
4011 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4012 /* Configure flow control refresh threshold,
4013 * the value for stat_tx_pause_refresh_timer[8]
4014 * is used for global pause operation.
4018 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4019 pf->fc_conf.pause_time);
4021 /* configure the timer value included in transmitted pause
4023 * the value for stat_tx_pause_quanta[8] is used for global
4026 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4027 pf->fc_conf.pause_time);
4029 fctrl_reg = I40E_READ_REG(hw,
4030 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4032 if (fc_conf->mac_ctrl_frame_fwd != 0)
4033 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4035 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4037 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4040 /* Configure pause time (2 TCs per register) */
4041 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4042 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4043 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4045 /* Configure flow control refresh threshold value */
4046 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4047 pf->fc_conf.pause_time / 2);
4049 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4051 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4052 *depending on configuration
4054 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4055 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4056 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4058 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4059 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4062 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4065 if (!pf->support_multi_driver) {
4066 /* config water marker both based on the packets and bytes */
4067 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4068 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4069 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4070 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4071 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4072 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4073 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4074 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4076 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4077 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4081 "Water marker configuration is not supported.");
4084 I40E_WRITE_FLUSH(hw);
4090 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4091 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4093 PMD_INIT_FUNC_TRACE();
4098 /* Add a MAC address, and update filters */
4100 i40e_macaddr_add(struct rte_eth_dev *dev,
4101 struct rte_ether_addr *mac_addr,
4102 __rte_unused uint32_t index,
4105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4106 struct i40e_mac_filter_info mac_filter;
4107 struct i40e_vsi *vsi;
4108 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4111 /* If VMDQ not enabled or configured, return */
4112 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4113 !pf->nb_cfg_vmdq_vsi)) {
4114 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4115 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4120 if (pool > pf->nb_cfg_vmdq_vsi) {
4121 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4122 pool, pf->nb_cfg_vmdq_vsi);
4126 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4127 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4128 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4130 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4135 vsi = pf->vmdq[pool - 1].vsi;
4137 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4138 if (ret != I40E_SUCCESS) {
4139 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4145 /* Remove a MAC address, and update filters */
4147 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4149 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4150 struct i40e_vsi *vsi;
4151 struct rte_eth_dev_data *data = dev->data;
4152 struct rte_ether_addr *macaddr;
4157 macaddr = &(data->mac_addrs[index]);
4159 pool_sel = dev->data->mac_pool_sel[index];
4161 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4162 if (pool_sel & (1ULL << i)) {
4166 /* No VMDQ pool enabled or configured */
4167 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4168 (i > pf->nb_cfg_vmdq_vsi)) {
4170 "No VMDQ pool enabled/configured");
4173 vsi = pf->vmdq[i - 1].vsi;
4175 ret = i40e_vsi_delete_mac(vsi, macaddr);
4178 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4185 /* Set perfect match or hash match of MAC and VLAN for a VF */
4187 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4188 struct rte_eth_mac_filter *filter,
4192 struct i40e_mac_filter_info mac_filter;
4193 struct rte_ether_addr old_mac;
4194 struct rte_ether_addr *new_mac;
4195 struct i40e_pf_vf *vf = NULL;
4200 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4203 hw = I40E_PF_TO_HW(pf);
4205 if (filter == NULL) {
4206 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4210 new_mac = &filter->mac_addr;
4212 if (rte_is_zero_ether_addr(new_mac)) {
4213 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4217 vf_id = filter->dst_id;
4219 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4220 PMD_DRV_LOG(ERR, "Invalid argument.");
4223 vf = &pf->vfs[vf_id];
4225 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4226 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4231 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4232 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4233 RTE_ETHER_ADDR_LEN);
4234 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4235 RTE_ETHER_ADDR_LEN);
4237 mac_filter.filter_type = filter->filter_type;
4238 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4239 if (ret != I40E_SUCCESS) {
4240 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4243 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4245 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4246 RTE_ETHER_ADDR_LEN);
4247 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4248 if (ret != I40E_SUCCESS) {
4249 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4253 /* Clear device address as it has been removed */
4254 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4255 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4261 /* MAC filter handle */
4263 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4266 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4267 struct rte_eth_mac_filter *filter;
4268 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4269 int ret = I40E_NOT_SUPPORTED;
4271 filter = (struct rte_eth_mac_filter *)(arg);
4273 switch (filter_op) {
4274 case RTE_ETH_FILTER_NOP:
4277 case RTE_ETH_FILTER_ADD:
4278 i40e_pf_disable_irq0(hw);
4280 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4281 i40e_pf_enable_irq0(hw);
4283 case RTE_ETH_FILTER_DELETE:
4284 i40e_pf_disable_irq0(hw);
4286 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4287 i40e_pf_enable_irq0(hw);
4290 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4291 ret = I40E_ERR_PARAM;
4299 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4301 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4302 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4309 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4310 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4311 vsi->type != I40E_VSI_SRIOV,
4314 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4318 uint32_t *lut_dw = (uint32_t *)lut;
4319 uint16_t i, lut_size_dw = lut_size / 4;
4321 if (vsi->type == I40E_VSI_SRIOV) {
4322 for (i = 0; i <= lut_size_dw; i++) {
4323 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4324 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4327 for (i = 0; i < lut_size_dw; i++)
4328 lut_dw[i] = I40E_READ_REG(hw,
4337 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4346 pf = I40E_VSI_TO_PF(vsi);
4347 hw = I40E_VSI_TO_HW(vsi);
4349 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4350 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4351 vsi->type != I40E_VSI_SRIOV,
4354 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4358 uint32_t *lut_dw = (uint32_t *)lut;
4359 uint16_t i, lut_size_dw = lut_size / 4;
4361 if (vsi->type == I40E_VSI_SRIOV) {
4362 for (i = 0; i < lut_size_dw; i++)
4365 I40E_VFQF_HLUT1(i, vsi->user_param),
4368 for (i = 0; i < lut_size_dw; i++)
4369 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4372 I40E_WRITE_FLUSH(hw);
4379 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4380 struct rte_eth_rss_reta_entry64 *reta_conf,
4383 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4384 uint16_t i, lut_size = pf->hash_lut_size;
4385 uint16_t idx, shift;
4389 if (reta_size != lut_size ||
4390 reta_size > ETH_RSS_RETA_SIZE_512) {
4392 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4393 reta_size, lut_size);
4397 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4399 PMD_DRV_LOG(ERR, "No memory can be allocated");
4402 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4405 for (i = 0; i < reta_size; i++) {
4406 idx = i / RTE_RETA_GROUP_SIZE;
4407 shift = i % RTE_RETA_GROUP_SIZE;
4408 if (reta_conf[idx].mask & (1ULL << shift))
4409 lut[i] = reta_conf[idx].reta[shift];
4411 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4413 pf->adapter->rss_reta_updated = 1;
4422 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4423 struct rte_eth_rss_reta_entry64 *reta_conf,
4426 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4427 uint16_t i, lut_size = pf->hash_lut_size;
4428 uint16_t idx, shift;
4432 if (reta_size != lut_size ||
4433 reta_size > ETH_RSS_RETA_SIZE_512) {
4435 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4436 reta_size, lut_size);
4440 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4442 PMD_DRV_LOG(ERR, "No memory can be allocated");
4446 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4449 for (i = 0; i < reta_size; i++) {
4450 idx = i / RTE_RETA_GROUP_SIZE;
4451 shift = i % RTE_RETA_GROUP_SIZE;
4452 if (reta_conf[idx].mask & (1ULL << shift))
4453 reta_conf[idx].reta[shift] = lut[i];
4463 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4464 * @hw: pointer to the HW structure
4465 * @mem: pointer to mem struct to fill out
4466 * @size: size of memory requested
4467 * @alignment: what to align the allocation to
4469 enum i40e_status_code
4470 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4471 struct i40e_dma_mem *mem,
4475 const struct rte_memzone *mz = NULL;
4476 char z_name[RTE_MEMZONE_NAMESIZE];
4479 return I40E_ERR_PARAM;
4481 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4482 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4483 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4485 return I40E_ERR_NO_MEMORY;
4490 mem->zone = (const void *)mz;
4492 "memzone %s allocated with physical address: %"PRIu64,
4495 return I40E_SUCCESS;
4499 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4500 * @hw: pointer to the HW structure
4501 * @mem: ptr to mem struct to free
4503 enum i40e_status_code
4504 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4505 struct i40e_dma_mem *mem)
4508 return I40E_ERR_PARAM;
4511 "memzone %s to be freed with physical address: %"PRIu64,
4512 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4513 rte_memzone_free((const struct rte_memzone *)mem->zone);
4518 return I40E_SUCCESS;
4522 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4523 * @hw: pointer to the HW structure
4524 * @mem: pointer to mem struct to fill out
4525 * @size: size of memory requested
4527 enum i40e_status_code
4528 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4529 struct i40e_virt_mem *mem,
4533 return I40E_ERR_PARAM;
4536 mem->va = rte_zmalloc("i40e", size, 0);
4539 return I40E_SUCCESS;
4541 return I40E_ERR_NO_MEMORY;
4545 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4546 * @hw: pointer to the HW structure
4547 * @mem: pointer to mem struct to free
4549 enum i40e_status_code
4550 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4551 struct i40e_virt_mem *mem)
4554 return I40E_ERR_PARAM;
4559 return I40E_SUCCESS;
4563 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4565 rte_spinlock_init(&sp->spinlock);
4569 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4571 rte_spinlock_lock(&sp->spinlock);
4575 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4577 rte_spinlock_unlock(&sp->spinlock);
4581 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4587 * Get the hardware capabilities, which will be parsed
4588 * and saved into struct i40e_hw.
4591 i40e_get_cap(struct i40e_hw *hw)
4593 struct i40e_aqc_list_capabilities_element_resp *buf;
4594 uint16_t len, size = 0;
4597 /* Calculate a huge enough buff for saving response data temporarily */
4598 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4599 I40E_MAX_CAP_ELE_NUM;
4600 buf = rte_zmalloc("i40e", len, 0);
4602 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4603 return I40E_ERR_NO_MEMORY;
4606 /* Get, parse the capabilities and save it to hw */
4607 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4608 i40e_aqc_opc_list_func_capabilities, NULL);
4609 if (ret != I40E_SUCCESS)
4610 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4612 /* Free the temporary buffer after being used */
4618 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4620 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4628 pf = (struct i40e_pf *)opaque;
4632 num = strtoul(value, &end, 0);
4633 if (errno != 0 || end == value || *end != 0) {
4634 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4635 "kept the value = %hu", value, pf->vf_nb_qp_max);
4639 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4640 pf->vf_nb_qp_max = (uint16_t)num;
4642 /* here return 0 to make next valid same argument work */
4643 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4644 "power of 2 and equal or less than 16 !, Now it is "
4645 "kept the value = %hu", num, pf->vf_nb_qp_max);
4650 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4652 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4653 struct rte_kvargs *kvlist;
4656 /* set default queue number per VF as 4 */
4657 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4659 if (dev->device->devargs == NULL)
4662 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4666 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4667 if (!kvargs_count) {
4668 rte_kvargs_free(kvlist);
4672 if (kvargs_count > 1)
4673 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4674 "the first invalid or last valid one is used !",
4675 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4677 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4678 i40e_pf_parse_vf_queue_number_handler, pf);
4680 rte_kvargs_free(kvlist);
4686 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4688 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4689 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4690 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4691 uint16_t qp_count = 0, vsi_count = 0;
4693 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4694 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4698 i40e_pf_config_vf_rxq_number(dev);
4700 /* Add the parameter init for LFC */
4701 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4702 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4703 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4705 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4706 pf->max_num_vsi = hw->func_caps.num_vsis;
4707 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4708 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4710 /* FDir queue/VSI allocation */
4711 pf->fdir_qp_offset = 0;
4712 if (hw->func_caps.fd) {
4713 pf->flags |= I40E_FLAG_FDIR;
4714 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4716 pf->fdir_nb_qps = 0;
4718 qp_count += pf->fdir_nb_qps;
4721 /* LAN queue/VSI allocation */
4722 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4723 if (!hw->func_caps.rss) {
4726 pf->flags |= I40E_FLAG_RSS;
4727 if (hw->mac.type == I40E_MAC_X722)
4728 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4729 pf->lan_nb_qps = pf->lan_nb_qp_max;
4731 qp_count += pf->lan_nb_qps;
4734 /* VF queue/VSI allocation */
4735 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4736 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4737 pf->flags |= I40E_FLAG_SRIOV;
4738 pf->vf_nb_qps = pf->vf_nb_qp_max;
4739 pf->vf_num = pci_dev->max_vfs;
4741 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4742 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4747 qp_count += pf->vf_nb_qps * pf->vf_num;
4748 vsi_count += pf->vf_num;
4750 /* VMDq queue/VSI allocation */
4751 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4752 pf->vmdq_nb_qps = 0;
4753 pf->max_nb_vmdq_vsi = 0;
4754 if (hw->func_caps.vmdq) {
4755 if (qp_count < hw->func_caps.num_tx_qp &&
4756 vsi_count < hw->func_caps.num_vsis) {
4757 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4758 qp_count) / pf->vmdq_nb_qp_max;
4760 /* Limit the maximum number of VMDq vsi to the maximum
4761 * ethdev can support
4763 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4764 hw->func_caps.num_vsis - vsi_count);
4765 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4767 if (pf->max_nb_vmdq_vsi) {
4768 pf->flags |= I40E_FLAG_VMDQ;
4769 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4771 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4772 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4773 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4776 "No enough queues left for VMDq");
4779 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4782 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4783 vsi_count += pf->max_nb_vmdq_vsi;
4785 if (hw->func_caps.dcb)
4786 pf->flags |= I40E_FLAG_DCB;
4788 if (qp_count > hw->func_caps.num_tx_qp) {
4790 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4791 qp_count, hw->func_caps.num_tx_qp);
4794 if (vsi_count > hw->func_caps.num_vsis) {
4796 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4797 vsi_count, hw->func_caps.num_vsis);
4805 i40e_pf_get_switch_config(struct i40e_pf *pf)
4807 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4808 struct i40e_aqc_get_switch_config_resp *switch_config;
4809 struct i40e_aqc_switch_config_element_resp *element;
4810 uint16_t start_seid = 0, num_reported;
4813 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4814 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4815 if (!switch_config) {
4816 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4820 /* Get the switch configurations */
4821 ret = i40e_aq_get_switch_config(hw, switch_config,
4822 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4823 if (ret != I40E_SUCCESS) {
4824 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4827 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4828 if (num_reported != 1) { /* The number should be 1 */
4829 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4833 /* Parse the switch configuration elements */
4834 element = &(switch_config->element[0]);
4835 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4836 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4837 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4839 PMD_DRV_LOG(INFO, "Unknown element type");
4842 rte_free(switch_config);
4848 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4851 struct pool_entry *entry;
4853 if (pool == NULL || num == 0)
4856 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4857 if (entry == NULL) {
4858 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4862 /* queue heap initialize */
4863 pool->num_free = num;
4864 pool->num_alloc = 0;
4866 LIST_INIT(&pool->alloc_list);
4867 LIST_INIT(&pool->free_list);
4869 /* Initialize element */
4873 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4878 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4880 struct pool_entry *entry, *next_entry;
4885 for (entry = LIST_FIRST(&pool->alloc_list);
4886 entry && (next_entry = LIST_NEXT(entry, next), 1);
4887 entry = next_entry) {
4888 LIST_REMOVE(entry, next);
4892 for (entry = LIST_FIRST(&pool->free_list);
4893 entry && (next_entry = LIST_NEXT(entry, next), 1);
4894 entry = next_entry) {
4895 LIST_REMOVE(entry, next);
4900 pool->num_alloc = 0;
4902 LIST_INIT(&pool->alloc_list);
4903 LIST_INIT(&pool->free_list);
4907 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4910 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4911 uint32_t pool_offset;
4915 PMD_DRV_LOG(ERR, "Invalid parameter");
4919 pool_offset = base - pool->base;
4920 /* Lookup in alloc list */
4921 LIST_FOREACH(entry, &pool->alloc_list, next) {
4922 if (entry->base == pool_offset) {
4923 valid_entry = entry;
4924 LIST_REMOVE(entry, next);
4929 /* Not find, return */
4930 if (valid_entry == NULL) {
4931 PMD_DRV_LOG(ERR, "Failed to find entry");
4936 * Found it, move it to free list and try to merge.
4937 * In order to make merge easier, always sort it by qbase.
4938 * Find adjacent prev and last entries.
4941 LIST_FOREACH(entry, &pool->free_list, next) {
4942 if (entry->base > valid_entry->base) {
4950 /* Try to merge with next one*/
4952 /* Merge with next one */
4953 if (valid_entry->base + valid_entry->len == next->base) {
4954 next->base = valid_entry->base;
4955 next->len += valid_entry->len;
4956 rte_free(valid_entry);
4963 /* Merge with previous one */
4964 if (prev->base + prev->len == valid_entry->base) {
4965 prev->len += valid_entry->len;
4966 /* If it merge with next one, remove next node */
4968 LIST_REMOVE(valid_entry, next);
4969 rte_free(valid_entry);
4971 rte_free(valid_entry);
4977 /* Not find any entry to merge, insert */
4980 LIST_INSERT_AFTER(prev, valid_entry, next);
4981 else if (next != NULL)
4982 LIST_INSERT_BEFORE(next, valid_entry, next);
4983 else /* It's empty list, insert to head */
4984 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4987 pool->num_free += valid_entry->len;
4988 pool->num_alloc -= valid_entry->len;
4994 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4997 struct pool_entry *entry, *valid_entry;
4999 if (pool == NULL || num == 0) {
5000 PMD_DRV_LOG(ERR, "Invalid parameter");
5004 if (pool->num_free < num) {
5005 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5006 num, pool->num_free);
5011 /* Lookup in free list and find most fit one */
5012 LIST_FOREACH(entry, &pool->free_list, next) {
5013 if (entry->len >= num) {
5015 if (entry->len == num) {
5016 valid_entry = entry;
5019 if (valid_entry == NULL || valid_entry->len > entry->len)
5020 valid_entry = entry;
5024 /* Not find one to satisfy the request, return */
5025 if (valid_entry == NULL) {
5026 PMD_DRV_LOG(ERR, "No valid entry found");
5030 * The entry have equal queue number as requested,
5031 * remove it from alloc_list.
5033 if (valid_entry->len == num) {
5034 LIST_REMOVE(valid_entry, next);
5037 * The entry have more numbers than requested,
5038 * create a new entry for alloc_list and minus its
5039 * queue base and number in free_list.
5041 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5042 if (entry == NULL) {
5044 "Failed to allocate memory for resource pool");
5047 entry->base = valid_entry->base;
5049 valid_entry->base += num;
5050 valid_entry->len -= num;
5051 valid_entry = entry;
5054 /* Insert it into alloc list, not sorted */
5055 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5057 pool->num_free -= valid_entry->len;
5058 pool->num_alloc += valid_entry->len;
5060 return valid_entry->base + pool->base;
5064 * bitmap_is_subset - Check whether src2 is subset of src1
5067 bitmap_is_subset(uint8_t src1, uint8_t src2)
5069 return !((src1 ^ src2) & src2);
5072 static enum i40e_status_code
5073 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5075 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5077 /* If DCB is not supported, only default TC is supported */
5078 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5079 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5080 return I40E_NOT_SUPPORTED;
5083 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5085 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5086 hw->func_caps.enabled_tcmap, enabled_tcmap);
5087 return I40E_NOT_SUPPORTED;
5089 return I40E_SUCCESS;
5093 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5094 struct i40e_vsi_vlan_pvid_info *info)
5097 struct i40e_vsi_context ctxt;
5098 uint8_t vlan_flags = 0;
5101 if (vsi == NULL || info == NULL) {
5102 PMD_DRV_LOG(ERR, "invalid parameters");
5103 return I40E_ERR_PARAM;
5107 vsi->info.pvid = info->config.pvid;
5109 * If insert pvid is enabled, only tagged pkts are
5110 * allowed to be sent out.
5112 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5113 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5116 if (info->config.reject.tagged == 0)
5117 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5119 if (info->config.reject.untagged == 0)
5120 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5122 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5123 I40E_AQ_VSI_PVLAN_MODE_MASK);
5124 vsi->info.port_vlan_flags |= vlan_flags;
5125 vsi->info.valid_sections =
5126 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5127 memset(&ctxt, 0, sizeof(ctxt));
5128 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5129 ctxt.seid = vsi->seid;
5131 hw = I40E_VSI_TO_HW(vsi);
5132 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5133 if (ret != I40E_SUCCESS)
5134 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5140 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5142 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5144 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5146 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5147 if (ret != I40E_SUCCESS)
5151 PMD_DRV_LOG(ERR, "seid not valid");
5155 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5156 tc_bw_data.tc_valid_bits = enabled_tcmap;
5157 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5158 tc_bw_data.tc_bw_credits[i] =
5159 (enabled_tcmap & (1 << i)) ? 1 : 0;
5161 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5162 if (ret != I40E_SUCCESS) {
5163 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5167 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5168 sizeof(vsi->info.qs_handle));
5169 return I40E_SUCCESS;
5172 static enum i40e_status_code
5173 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5174 struct i40e_aqc_vsi_properties_data *info,
5175 uint8_t enabled_tcmap)
5177 enum i40e_status_code ret;
5178 int i, total_tc = 0;
5179 uint16_t qpnum_per_tc, bsf, qp_idx;
5181 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5182 if (ret != I40E_SUCCESS)
5185 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5186 if (enabled_tcmap & (1 << i))
5190 vsi->enabled_tc = enabled_tcmap;
5192 /* Number of queues per enabled TC */
5193 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5194 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5195 bsf = rte_bsf32(qpnum_per_tc);
5197 /* Adjust the queue number to actual queues that can be applied */
5198 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5199 vsi->nb_qps = qpnum_per_tc * total_tc;
5202 * Configure TC and queue mapping parameters, for enabled TC,
5203 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5204 * default queue will serve it.
5207 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5208 if (vsi->enabled_tc & (1 << i)) {
5209 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5210 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5211 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5212 qp_idx += qpnum_per_tc;
5214 info->tc_mapping[i] = 0;
5217 /* Associate queue number with VSI */
5218 if (vsi->type == I40E_VSI_SRIOV) {
5219 info->mapping_flags |=
5220 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5221 for (i = 0; i < vsi->nb_qps; i++)
5222 info->queue_mapping[i] =
5223 rte_cpu_to_le_16(vsi->base_queue + i);
5225 info->mapping_flags |=
5226 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5227 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5229 info->valid_sections |=
5230 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5232 return I40E_SUCCESS;
5236 i40e_veb_release(struct i40e_veb *veb)
5238 struct i40e_vsi *vsi;
5244 if (!TAILQ_EMPTY(&veb->head)) {
5245 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5248 /* associate_vsi field is NULL for floating VEB */
5249 if (veb->associate_vsi != NULL) {
5250 vsi = veb->associate_vsi;
5251 hw = I40E_VSI_TO_HW(vsi);
5253 vsi->uplink_seid = veb->uplink_seid;
5256 veb->associate_pf->main_vsi->floating_veb = NULL;
5257 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5260 i40e_aq_delete_element(hw, veb->seid, NULL);
5262 return I40E_SUCCESS;
5266 static struct i40e_veb *
5267 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5269 struct i40e_veb *veb;
5275 "veb setup failed, associated PF shouldn't null");
5278 hw = I40E_PF_TO_HW(pf);
5280 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5282 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5286 veb->associate_vsi = vsi;
5287 veb->associate_pf = pf;
5288 TAILQ_INIT(&veb->head);
5289 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5291 /* create floating veb if vsi is NULL */
5293 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5294 I40E_DEFAULT_TCMAP, false,
5295 &veb->seid, false, NULL);
5297 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5298 true, &veb->seid, false, NULL);
5301 if (ret != I40E_SUCCESS) {
5302 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5303 hw->aq.asq_last_status);
5306 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5308 /* get statistics index */
5309 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5310 &veb->stats_idx, NULL, NULL, NULL);
5311 if (ret != I40E_SUCCESS) {
5312 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5313 hw->aq.asq_last_status);
5316 /* Get VEB bandwidth, to be implemented */
5317 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5319 vsi->uplink_seid = veb->seid;
5328 i40e_vsi_release(struct i40e_vsi *vsi)
5332 struct i40e_vsi_list *vsi_list;
5335 struct i40e_mac_filter *f;
5336 uint16_t user_param;
5339 return I40E_SUCCESS;
5344 user_param = vsi->user_param;
5346 pf = I40E_VSI_TO_PF(vsi);
5347 hw = I40E_VSI_TO_HW(vsi);
5349 /* VSI has child to attach, release child first */
5351 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5352 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5355 i40e_veb_release(vsi->veb);
5358 if (vsi->floating_veb) {
5359 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5360 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5365 /* Remove all macvlan filters of the VSI */
5366 i40e_vsi_remove_all_macvlan_filter(vsi);
5367 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5370 if (vsi->type != I40E_VSI_MAIN &&
5371 ((vsi->type != I40E_VSI_SRIOV) ||
5372 !pf->floating_veb_list[user_param])) {
5373 /* Remove vsi from parent's sibling list */
5374 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5375 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5376 return I40E_ERR_PARAM;
5378 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5379 &vsi->sib_vsi_list, list);
5381 /* Remove all switch element of the VSI */
5382 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5383 if (ret != I40E_SUCCESS)
5384 PMD_DRV_LOG(ERR, "Failed to delete element");
5387 if ((vsi->type == I40E_VSI_SRIOV) &&
5388 pf->floating_veb_list[user_param]) {
5389 /* Remove vsi from parent's sibling list */
5390 if (vsi->parent_vsi == NULL ||
5391 vsi->parent_vsi->floating_veb == NULL) {
5392 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5393 return I40E_ERR_PARAM;
5395 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5396 &vsi->sib_vsi_list, list);
5398 /* Remove all switch element of the VSI */
5399 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5400 if (ret != I40E_SUCCESS)
5401 PMD_DRV_LOG(ERR, "Failed to delete element");
5404 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5406 if (vsi->type != I40E_VSI_SRIOV)
5407 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5410 return I40E_SUCCESS;
5414 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5416 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5417 struct i40e_aqc_remove_macvlan_element_data def_filter;
5418 struct i40e_mac_filter_info filter;
5421 if (vsi->type != I40E_VSI_MAIN)
5422 return I40E_ERR_CONFIG;
5423 memset(&def_filter, 0, sizeof(def_filter));
5424 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5426 def_filter.vlan_tag = 0;
5427 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5428 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5429 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5430 if (ret != I40E_SUCCESS) {
5431 struct i40e_mac_filter *f;
5432 struct rte_ether_addr *mac;
5435 "Cannot remove the default macvlan filter");
5436 /* It needs to add the permanent mac into mac list */
5437 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5439 PMD_DRV_LOG(ERR, "failed to allocate memory");
5440 return I40E_ERR_NO_MEMORY;
5442 mac = &f->mac_info.mac_addr;
5443 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5445 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5446 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5451 rte_memcpy(&filter.mac_addr,
5452 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5453 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5454 return i40e_vsi_add_mac(vsi, &filter);
5458 * i40e_vsi_get_bw_config - Query VSI BW Information
5459 * @vsi: the VSI to be queried
5461 * Returns 0 on success, negative value on failure
5463 static enum i40e_status_code
5464 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5466 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5467 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5468 struct i40e_hw *hw = &vsi->adapter->hw;
5473 memset(&bw_config, 0, sizeof(bw_config));
5474 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5475 if (ret != I40E_SUCCESS) {
5476 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5477 hw->aq.asq_last_status);
5481 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5482 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5483 &ets_sla_config, NULL);
5484 if (ret != I40E_SUCCESS) {
5486 "VSI failed to get TC bandwdith configuration %u",
5487 hw->aq.asq_last_status);
5491 /* store and print out BW info */
5492 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5493 vsi->bw_info.bw_max = bw_config.max_bw;
5494 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5495 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5496 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5497 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5499 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5500 vsi->bw_info.bw_ets_share_credits[i] =
5501 ets_sla_config.share_credits[i];
5502 vsi->bw_info.bw_ets_credits[i] =
5503 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5504 /* 4 bits per TC, 4th bit is reserved */
5505 vsi->bw_info.bw_ets_max[i] =
5506 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5507 RTE_LEN2MASK(3, uint8_t));
5508 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5509 vsi->bw_info.bw_ets_share_credits[i]);
5510 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5511 vsi->bw_info.bw_ets_credits[i]);
5512 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5513 vsi->bw_info.bw_ets_max[i]);
5516 return I40E_SUCCESS;
5519 /* i40e_enable_pf_lb
5520 * @pf: pointer to the pf structure
5522 * allow loopback on pf
5525 i40e_enable_pf_lb(struct i40e_pf *pf)
5527 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5528 struct i40e_vsi_context ctxt;
5531 /* Use the FW API if FW >= v5.0 */
5532 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5533 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5537 memset(&ctxt, 0, sizeof(ctxt));
5538 ctxt.seid = pf->main_vsi_seid;
5539 ctxt.pf_num = hw->pf_id;
5540 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5542 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5543 ret, hw->aq.asq_last_status);
5546 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5547 ctxt.info.valid_sections =
5548 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5549 ctxt.info.switch_id |=
5550 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5552 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5554 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5555 hw->aq.asq_last_status);
5560 i40e_vsi_setup(struct i40e_pf *pf,
5561 enum i40e_vsi_type type,
5562 struct i40e_vsi *uplink_vsi,
5563 uint16_t user_param)
5565 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5566 struct i40e_vsi *vsi;
5567 struct i40e_mac_filter_info filter;
5569 struct i40e_vsi_context ctxt;
5570 struct rte_ether_addr broadcast =
5571 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5573 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5574 uplink_vsi == NULL) {
5576 "VSI setup failed, VSI link shouldn't be NULL");
5580 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5582 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5587 * 1.type is not MAIN and uplink vsi is not NULL
5588 * If uplink vsi didn't setup VEB, create one first under veb field
5589 * 2.type is SRIOV and the uplink is NULL
5590 * If floating VEB is NULL, create one veb under floating veb field
5593 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5594 uplink_vsi->veb == NULL) {
5595 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5597 if (uplink_vsi->veb == NULL) {
5598 PMD_DRV_LOG(ERR, "VEB setup failed");
5601 /* set ALLOWLOOPBACk on pf, when veb is created */
5602 i40e_enable_pf_lb(pf);
5605 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5606 pf->main_vsi->floating_veb == NULL) {
5607 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5609 if (pf->main_vsi->floating_veb == NULL) {
5610 PMD_DRV_LOG(ERR, "VEB setup failed");
5615 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5617 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5620 TAILQ_INIT(&vsi->mac_list);
5622 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5623 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5624 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5625 vsi->user_param = user_param;
5626 vsi->vlan_anti_spoof_on = 0;
5627 vsi->vlan_filter_on = 0;
5628 /* Allocate queues */
5629 switch (vsi->type) {
5630 case I40E_VSI_MAIN :
5631 vsi->nb_qps = pf->lan_nb_qps;
5633 case I40E_VSI_SRIOV :
5634 vsi->nb_qps = pf->vf_nb_qps;
5636 case I40E_VSI_VMDQ2:
5637 vsi->nb_qps = pf->vmdq_nb_qps;
5640 vsi->nb_qps = pf->fdir_nb_qps;
5646 * The filter status descriptor is reported in rx queue 0,
5647 * while the tx queue for fdir filter programming has no
5648 * such constraints, can be non-zero queues.
5649 * To simplify it, choose FDIR vsi use queue 0 pair.
5650 * To make sure it will use queue 0 pair, queue allocation
5651 * need be done before this function is called
5653 if (type != I40E_VSI_FDIR) {
5654 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5656 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5660 vsi->base_queue = ret;
5662 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5664 /* VF has MSIX interrupt in VF range, don't allocate here */
5665 if (type == I40E_VSI_MAIN) {
5666 if (pf->support_multi_driver) {
5667 /* If support multi-driver, need to use INT0 instead of
5668 * allocating from msix pool. The Msix pool is init from
5669 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5670 * to 1 without calling i40e_res_pool_alloc.
5675 ret = i40e_res_pool_alloc(&pf->msix_pool,
5676 RTE_MIN(vsi->nb_qps,
5677 RTE_MAX_RXTX_INTR_VEC_ID));
5680 "VSI MAIN %d get heap failed %d",
5682 goto fail_queue_alloc;
5684 vsi->msix_intr = ret;
5685 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5686 RTE_MAX_RXTX_INTR_VEC_ID);
5688 } else if (type != I40E_VSI_SRIOV) {
5689 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5691 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5692 goto fail_queue_alloc;
5694 vsi->msix_intr = ret;
5702 if (type == I40E_VSI_MAIN) {
5703 /* For main VSI, no need to add since it's default one */
5704 vsi->uplink_seid = pf->mac_seid;
5705 vsi->seid = pf->main_vsi_seid;
5706 /* Bind queues with specific MSIX interrupt */
5708 * Needs 2 interrupt at least, one for misc cause which will
5709 * enabled from OS side, Another for queues binding the
5710 * interrupt from device side only.
5713 /* Get default VSI parameters from hardware */
5714 memset(&ctxt, 0, sizeof(ctxt));
5715 ctxt.seid = vsi->seid;
5716 ctxt.pf_num = hw->pf_id;
5717 ctxt.uplink_seid = vsi->uplink_seid;
5719 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5720 if (ret != I40E_SUCCESS) {
5721 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5722 goto fail_msix_alloc;
5724 rte_memcpy(&vsi->info, &ctxt.info,
5725 sizeof(struct i40e_aqc_vsi_properties_data));
5726 vsi->vsi_id = ctxt.vsi_number;
5727 vsi->info.valid_sections = 0;
5729 /* Configure tc, enabled TC0 only */
5730 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5732 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5733 goto fail_msix_alloc;
5736 /* TC, queue mapping */
5737 memset(&ctxt, 0, sizeof(ctxt));
5738 vsi->info.valid_sections |=
5739 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5740 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5741 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5742 rte_memcpy(&ctxt.info, &vsi->info,
5743 sizeof(struct i40e_aqc_vsi_properties_data));
5744 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5745 I40E_DEFAULT_TCMAP);
5746 if (ret != I40E_SUCCESS) {
5748 "Failed to configure TC queue mapping");
5749 goto fail_msix_alloc;
5751 ctxt.seid = vsi->seid;
5752 ctxt.pf_num = hw->pf_id;
5753 ctxt.uplink_seid = vsi->uplink_seid;
5756 /* Update VSI parameters */
5757 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5758 if (ret != I40E_SUCCESS) {
5759 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5760 goto fail_msix_alloc;
5763 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5764 sizeof(vsi->info.tc_mapping));
5765 rte_memcpy(&vsi->info.queue_mapping,
5766 &ctxt.info.queue_mapping,
5767 sizeof(vsi->info.queue_mapping));
5768 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5769 vsi->info.valid_sections = 0;
5771 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5775 * Updating default filter settings are necessary to prevent
5776 * reception of tagged packets.
5777 * Some old firmware configurations load a default macvlan
5778 * filter which accepts both tagged and untagged packets.
5779 * The updating is to use a normal filter instead if needed.
5780 * For NVM 4.2.2 or after, the updating is not needed anymore.
5781 * The firmware with correct configurations load the default
5782 * macvlan filter which is expected and cannot be removed.
5784 i40e_update_default_filter_setting(vsi);
5785 i40e_config_qinq(hw, vsi);
5786 } else if (type == I40E_VSI_SRIOV) {
5787 memset(&ctxt, 0, sizeof(ctxt));
5789 * For other VSI, the uplink_seid equals to uplink VSI's
5790 * uplink_seid since they share same VEB
5792 if (uplink_vsi == NULL)
5793 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5795 vsi->uplink_seid = uplink_vsi->uplink_seid;
5796 ctxt.pf_num = hw->pf_id;
5797 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5798 ctxt.uplink_seid = vsi->uplink_seid;
5799 ctxt.connection_type = 0x1;
5800 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5802 /* Use the VEB configuration if FW >= v5.0 */
5803 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5804 /* Configure switch ID */
5805 ctxt.info.valid_sections |=
5806 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5807 ctxt.info.switch_id =
5808 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5811 /* Configure port/vlan */
5812 ctxt.info.valid_sections |=
5813 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5814 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5815 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5816 hw->func_caps.enabled_tcmap);
5817 if (ret != I40E_SUCCESS) {
5819 "Failed to configure TC queue mapping");
5820 goto fail_msix_alloc;
5823 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5824 ctxt.info.valid_sections |=
5825 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5827 * Since VSI is not created yet, only configure parameter,
5828 * will add vsi below.
5831 i40e_config_qinq(hw, vsi);
5832 } else if (type == I40E_VSI_VMDQ2) {
5833 memset(&ctxt, 0, sizeof(ctxt));
5835 * For other VSI, the uplink_seid equals to uplink VSI's
5836 * uplink_seid since they share same VEB
5838 vsi->uplink_seid = uplink_vsi->uplink_seid;
5839 ctxt.pf_num = hw->pf_id;
5841 ctxt.uplink_seid = vsi->uplink_seid;
5842 ctxt.connection_type = 0x1;
5843 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5845 ctxt.info.valid_sections |=
5846 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5847 /* user_param carries flag to enable loop back */
5849 ctxt.info.switch_id =
5850 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5851 ctxt.info.switch_id |=
5852 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5855 /* Configure port/vlan */
5856 ctxt.info.valid_sections |=
5857 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5858 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5859 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5860 I40E_DEFAULT_TCMAP);
5861 if (ret != I40E_SUCCESS) {
5863 "Failed to configure TC queue mapping");
5864 goto fail_msix_alloc;
5866 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5867 ctxt.info.valid_sections |=
5868 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5869 } else if (type == I40E_VSI_FDIR) {
5870 memset(&ctxt, 0, sizeof(ctxt));
5871 vsi->uplink_seid = uplink_vsi->uplink_seid;
5872 ctxt.pf_num = hw->pf_id;
5874 ctxt.uplink_seid = vsi->uplink_seid;
5875 ctxt.connection_type = 0x1; /* regular data port */
5876 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5877 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5878 I40E_DEFAULT_TCMAP);
5879 if (ret != I40E_SUCCESS) {
5881 "Failed to configure TC queue mapping.");
5882 goto fail_msix_alloc;
5884 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5885 ctxt.info.valid_sections |=
5886 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5888 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5889 goto fail_msix_alloc;
5892 if (vsi->type != I40E_VSI_MAIN) {
5893 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5894 if (ret != I40E_SUCCESS) {
5895 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5896 hw->aq.asq_last_status);
5897 goto fail_msix_alloc;
5899 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5900 vsi->info.valid_sections = 0;
5901 vsi->seid = ctxt.seid;
5902 vsi->vsi_id = ctxt.vsi_number;
5903 vsi->sib_vsi_list.vsi = vsi;
5904 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5905 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5906 &vsi->sib_vsi_list, list);
5908 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5909 &vsi->sib_vsi_list, list);
5913 /* MAC/VLAN configuration */
5914 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5915 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5917 ret = i40e_vsi_add_mac(vsi, &filter);
5918 if (ret != I40E_SUCCESS) {
5919 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5920 goto fail_msix_alloc;
5923 /* Get VSI BW information */
5924 i40e_vsi_get_bw_config(vsi);
5927 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5929 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5935 /* Configure vlan filter on or off */
5937 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5940 struct i40e_mac_filter *f;
5942 struct i40e_mac_filter_info *mac_filter;
5943 enum rte_mac_filter_type desired_filter;
5944 int ret = I40E_SUCCESS;
5947 /* Filter to match MAC and VLAN */
5948 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5950 /* Filter to match only MAC */
5951 desired_filter = RTE_MAC_PERFECT_MATCH;
5956 mac_filter = rte_zmalloc("mac_filter_info_data",
5957 num * sizeof(*mac_filter), 0);
5958 if (mac_filter == NULL) {
5959 PMD_DRV_LOG(ERR, "failed to allocate memory");
5960 return I40E_ERR_NO_MEMORY;
5965 /* Remove all existing mac */
5966 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5967 mac_filter[i] = f->mac_info;
5968 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5970 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5971 on ? "enable" : "disable");
5977 /* Override with new filter */
5978 for (i = 0; i < num; i++) {
5979 mac_filter[i].filter_type = desired_filter;
5980 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5982 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5983 on ? "enable" : "disable");
5989 rte_free(mac_filter);
5993 /* Configure vlan stripping on or off */
5995 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5997 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5998 struct i40e_vsi_context ctxt;
6000 int ret = I40E_SUCCESS;
6002 /* Check if it has been already on or off */
6003 if (vsi->info.valid_sections &
6004 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6006 if ((vsi->info.port_vlan_flags &
6007 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6008 return 0; /* already on */
6010 if ((vsi->info.port_vlan_flags &
6011 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6012 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6013 return 0; /* already off */
6018 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6020 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6021 vsi->info.valid_sections =
6022 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6023 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6024 vsi->info.port_vlan_flags |= vlan_flags;
6025 ctxt.seid = vsi->seid;
6026 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6027 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6029 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6030 on ? "enable" : "disable");
6036 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6038 struct rte_eth_dev_data *data = dev->data;
6042 /* Apply vlan offload setting */
6043 mask = ETH_VLAN_STRIP_MASK |
6044 ETH_VLAN_FILTER_MASK |
6045 ETH_VLAN_EXTEND_MASK;
6046 ret = i40e_vlan_offload_set(dev, mask);
6048 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6052 /* Apply pvid setting */
6053 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6054 data->dev_conf.txmode.hw_vlan_insert_pvid);
6056 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6062 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6064 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6066 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6070 i40e_update_flow_control(struct i40e_hw *hw)
6072 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6073 struct i40e_link_status link_status;
6074 uint32_t rxfc = 0, txfc = 0, reg;
6078 memset(&link_status, 0, sizeof(link_status));
6079 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6080 if (ret != I40E_SUCCESS) {
6081 PMD_DRV_LOG(ERR, "Failed to get link status information");
6082 goto write_reg; /* Disable flow control */
6085 an_info = hw->phy.link_info.an_info;
6086 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6087 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6088 ret = I40E_ERR_NOT_READY;
6089 goto write_reg; /* Disable flow control */
6092 * If link auto negotiation is enabled, flow control needs to
6093 * be configured according to it
6095 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6096 case I40E_LINK_PAUSE_RXTX:
6099 hw->fc.current_mode = I40E_FC_FULL;
6101 case I40E_AQ_LINK_PAUSE_RX:
6103 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6105 case I40E_AQ_LINK_PAUSE_TX:
6107 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6110 hw->fc.current_mode = I40E_FC_NONE;
6115 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6116 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6117 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6118 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6119 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6120 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6127 i40e_pf_setup(struct i40e_pf *pf)
6129 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6130 struct i40e_filter_control_settings settings;
6131 struct i40e_vsi *vsi;
6134 /* Clear all stats counters */
6135 pf->offset_loaded = FALSE;
6136 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6137 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6138 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6139 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6141 ret = i40e_pf_get_switch_config(pf);
6142 if (ret != I40E_SUCCESS) {
6143 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6147 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6149 PMD_INIT_LOG(WARNING,
6150 "failed to allocate switch domain for device %d", ret);
6152 if (pf->flags & I40E_FLAG_FDIR) {
6153 /* make queue allocated first, let FDIR use queue pair 0*/
6154 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6155 if (ret != I40E_FDIR_QUEUE_ID) {
6157 "queue allocation fails for FDIR: ret =%d",
6159 pf->flags &= ~I40E_FLAG_FDIR;
6162 /* main VSI setup */
6163 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6165 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6166 return I40E_ERR_NOT_READY;
6170 /* Configure filter control */
6171 memset(&settings, 0, sizeof(settings));
6172 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6173 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6174 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6175 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6177 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6178 hw->func_caps.rss_table_size);
6179 return I40E_ERR_PARAM;
6181 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6182 hw->func_caps.rss_table_size);
6183 pf->hash_lut_size = hw->func_caps.rss_table_size;
6185 /* Enable ethtype and macvlan filters */
6186 settings.enable_ethtype = TRUE;
6187 settings.enable_macvlan = TRUE;
6188 ret = i40e_set_filter_control(hw, &settings);
6190 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6193 /* Update flow control according to the auto negotiation */
6194 i40e_update_flow_control(hw);
6196 return I40E_SUCCESS;
6200 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6206 * Set or clear TX Queue Disable flags,
6207 * which is required by hardware.
6209 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6210 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6212 /* Wait until the request is finished */
6213 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6214 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6215 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6216 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6217 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6223 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6224 return I40E_SUCCESS; /* already on, skip next steps */
6226 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6227 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6229 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6230 return I40E_SUCCESS; /* already off, skip next steps */
6231 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6233 /* Write the register */
6234 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6235 /* Check the result */
6236 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6237 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6238 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6240 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6241 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6244 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6245 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6249 /* Check if it is timeout */
6250 if (j >= I40E_CHK_Q_ENA_COUNT) {
6251 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6252 (on ? "enable" : "disable"), q_idx);
6253 return I40E_ERR_TIMEOUT;
6256 return I40E_SUCCESS;
6259 /* Swith on or off the tx queues */
6261 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6263 struct rte_eth_dev_data *dev_data = pf->dev_data;
6264 struct i40e_tx_queue *txq;
6265 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6269 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6270 txq = dev_data->tx_queues[i];
6271 /* Don't operate the queue if not configured or
6272 * if starting only per queue */
6273 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6276 ret = i40e_dev_tx_queue_start(dev, i);
6278 ret = i40e_dev_tx_queue_stop(dev, i);
6279 if ( ret != I40E_SUCCESS)
6283 return I40E_SUCCESS;
6287 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6292 /* Wait until the request is finished */
6293 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6294 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6295 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6296 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6297 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6302 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6303 return I40E_SUCCESS; /* Already on, skip next steps */
6304 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6306 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6307 return I40E_SUCCESS; /* Already off, skip next steps */
6308 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6311 /* Write the register */
6312 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6313 /* Check the result */
6314 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6315 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6316 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6318 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6319 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6322 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6323 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6328 /* Check if it is timeout */
6329 if (j >= I40E_CHK_Q_ENA_COUNT) {
6330 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6331 (on ? "enable" : "disable"), q_idx);
6332 return I40E_ERR_TIMEOUT;
6335 return I40E_SUCCESS;
6337 /* Switch on or off the rx queues */
6339 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6341 struct rte_eth_dev_data *dev_data = pf->dev_data;
6342 struct i40e_rx_queue *rxq;
6343 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6347 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6348 rxq = dev_data->rx_queues[i];
6349 /* Don't operate the queue if not configured or
6350 * if starting only per queue */
6351 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6354 ret = i40e_dev_rx_queue_start(dev, i);
6356 ret = i40e_dev_rx_queue_stop(dev, i);
6357 if (ret != I40E_SUCCESS)
6361 return I40E_SUCCESS;
6364 /* Switch on or off all the rx/tx queues */
6366 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6371 /* enable rx queues before enabling tx queues */
6372 ret = i40e_dev_switch_rx_queues(pf, on);
6374 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6377 ret = i40e_dev_switch_tx_queues(pf, on);
6379 /* Stop tx queues before stopping rx queues */
6380 ret = i40e_dev_switch_tx_queues(pf, on);
6382 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6385 ret = i40e_dev_switch_rx_queues(pf, on);
6391 /* Initialize VSI for TX */
6393 i40e_dev_tx_init(struct i40e_pf *pf)
6395 struct rte_eth_dev_data *data = pf->dev_data;
6397 uint32_t ret = I40E_SUCCESS;
6398 struct i40e_tx_queue *txq;
6400 for (i = 0; i < data->nb_tx_queues; i++) {
6401 txq = data->tx_queues[i];
6402 if (!txq || !txq->q_set)
6404 ret = i40e_tx_queue_init(txq);
6405 if (ret != I40E_SUCCESS)
6408 if (ret == I40E_SUCCESS)
6409 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6415 /* Initialize VSI for RX */
6417 i40e_dev_rx_init(struct i40e_pf *pf)
6419 struct rte_eth_dev_data *data = pf->dev_data;
6420 int ret = I40E_SUCCESS;
6422 struct i40e_rx_queue *rxq;
6424 i40e_pf_config_mq_rx(pf);
6425 for (i = 0; i < data->nb_rx_queues; i++) {
6426 rxq = data->rx_queues[i];
6427 if (!rxq || !rxq->q_set)
6430 ret = i40e_rx_queue_init(rxq);
6431 if (ret != I40E_SUCCESS) {
6433 "Failed to do RX queue initialization");
6437 if (ret == I40E_SUCCESS)
6438 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6445 i40e_dev_rxtx_init(struct i40e_pf *pf)
6449 err = i40e_dev_tx_init(pf);
6451 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6454 err = i40e_dev_rx_init(pf);
6456 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6464 i40e_vmdq_setup(struct rte_eth_dev *dev)
6466 struct rte_eth_conf *conf = &dev->data->dev_conf;
6467 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6468 int i, err, conf_vsis, j, loop;
6469 struct i40e_vsi *vsi;
6470 struct i40e_vmdq_info *vmdq_info;
6471 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6472 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6475 * Disable interrupt to avoid message from VF. Furthermore, it will
6476 * avoid race condition in VSI creation/destroy.
6478 i40e_pf_disable_irq0(hw);
6480 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6481 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6485 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6486 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6487 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6488 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6489 pf->max_nb_vmdq_vsi);
6493 if (pf->vmdq != NULL) {
6494 PMD_INIT_LOG(INFO, "VMDQ already configured");
6498 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6499 sizeof(*vmdq_info) * conf_vsis, 0);
6501 if (pf->vmdq == NULL) {
6502 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6506 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6508 /* Create VMDQ VSI */
6509 for (i = 0; i < conf_vsis; i++) {
6510 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6511 vmdq_conf->enable_loop_back);
6513 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6517 vmdq_info = &pf->vmdq[i];
6519 vmdq_info->vsi = vsi;
6521 pf->nb_cfg_vmdq_vsi = conf_vsis;
6523 /* Configure Vlan */
6524 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6525 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6526 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6527 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6528 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6529 vmdq_conf->pool_map[i].vlan_id, j);
6531 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6532 vmdq_conf->pool_map[i].vlan_id);
6534 PMD_INIT_LOG(ERR, "Failed to add vlan");
6542 i40e_pf_enable_irq0(hw);
6547 for (i = 0; i < conf_vsis; i++)
6548 if (pf->vmdq[i].vsi == NULL)
6551 i40e_vsi_release(pf->vmdq[i].vsi);
6555 i40e_pf_enable_irq0(hw);
6560 i40e_stat_update_32(struct i40e_hw *hw,
6568 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6572 if (new_data >= *offset)
6573 *stat = (uint64_t)(new_data - *offset);
6575 *stat = (uint64_t)((new_data +
6576 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6580 i40e_stat_update_48(struct i40e_hw *hw,
6589 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6590 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6591 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6596 if (new_data >= *offset)
6597 *stat = new_data - *offset;
6599 *stat = (uint64_t)((new_data +
6600 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6602 *stat &= I40E_48_BIT_MASK;
6607 i40e_pf_disable_irq0(struct i40e_hw *hw)
6609 /* Disable all interrupt types */
6610 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6611 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6612 I40E_WRITE_FLUSH(hw);
6617 i40e_pf_enable_irq0(struct i40e_hw *hw)
6619 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6620 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6621 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6622 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6623 I40E_WRITE_FLUSH(hw);
6627 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6629 /* read pending request and disable first */
6630 i40e_pf_disable_irq0(hw);
6631 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6632 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6633 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6636 /* Link no queues with irq0 */
6637 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6638 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6642 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6644 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6645 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6648 uint32_t index, offset, val;
6653 * Try to find which VF trigger a reset, use absolute VF id to access
6654 * since the reg is global register.
6656 for (i = 0; i < pf->vf_num; i++) {
6657 abs_vf_id = hw->func_caps.vf_base_id + i;
6658 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6659 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6660 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6661 /* VFR event occurred */
6662 if (val & (0x1 << offset)) {
6665 /* Clear the event first */
6666 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6668 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6670 * Only notify a VF reset event occurred,
6671 * don't trigger another SW reset
6673 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6674 if (ret != I40E_SUCCESS)
6675 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6681 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6683 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6686 for (i = 0; i < pf->vf_num; i++)
6687 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6691 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6693 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6694 struct i40e_arq_event_info info;
6695 uint16_t pending, opcode;
6698 info.buf_len = I40E_AQ_BUF_SZ;
6699 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6700 if (!info.msg_buf) {
6701 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6707 ret = i40e_clean_arq_element(hw, &info, &pending);
6709 if (ret != I40E_SUCCESS) {
6711 "Failed to read msg from AdminQ, aq_err: %u",
6712 hw->aq.asq_last_status);
6715 opcode = rte_le_to_cpu_16(info.desc.opcode);
6718 case i40e_aqc_opc_send_msg_to_pf:
6719 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6720 i40e_pf_host_handle_vf_msg(dev,
6721 rte_le_to_cpu_16(info.desc.retval),
6722 rte_le_to_cpu_32(info.desc.cookie_high),
6723 rte_le_to_cpu_32(info.desc.cookie_low),
6727 case i40e_aqc_opc_get_link_status:
6728 ret = i40e_dev_link_update(dev, 0);
6730 _rte_eth_dev_callback_process(dev,
6731 RTE_ETH_EVENT_INTR_LSC, NULL);
6734 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6739 rte_free(info.msg_buf);
6743 * Interrupt handler triggered by NIC for handling
6744 * specific interrupt.
6747 * Pointer to interrupt handle.
6749 * The address of parameter (struct rte_eth_dev *) regsitered before.
6755 i40e_dev_interrupt_handler(void *param)
6757 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6758 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6761 /* Disable interrupt */
6762 i40e_pf_disable_irq0(hw);
6764 /* read out interrupt causes */
6765 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6767 /* No interrupt event indicated */
6768 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6769 PMD_DRV_LOG(INFO, "No interrupt event");
6772 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6773 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6774 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6775 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6776 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6777 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6778 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6779 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6780 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6781 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6782 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6783 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6784 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6785 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6787 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6788 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6789 i40e_dev_handle_vfr_event(dev);
6791 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6792 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6793 i40e_dev_handle_aq_msg(dev);
6797 /* Enable interrupt */
6798 i40e_pf_enable_irq0(hw);
6802 i40e_dev_alarm_handler(void *param)
6804 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6805 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6808 /* Disable interrupt */
6809 i40e_pf_disable_irq0(hw);
6811 /* read out interrupt causes */
6812 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6814 /* No interrupt event indicated */
6815 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6817 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6818 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6819 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6820 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6821 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6822 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6823 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6824 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6825 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6826 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6827 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6828 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6829 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6830 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6832 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6833 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6834 i40e_dev_handle_vfr_event(dev);
6836 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6837 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6838 i40e_dev_handle_aq_msg(dev);
6842 /* Enable interrupt */
6843 i40e_pf_enable_irq0(hw);
6844 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6845 i40e_dev_alarm_handler, dev);
6849 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6850 struct i40e_macvlan_filter *filter,
6853 int ele_num, ele_buff_size;
6854 int num, actual_num, i;
6856 int ret = I40E_SUCCESS;
6857 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6858 struct i40e_aqc_add_macvlan_element_data *req_list;
6860 if (filter == NULL || total == 0)
6861 return I40E_ERR_PARAM;
6862 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6863 ele_buff_size = hw->aq.asq_buf_size;
6865 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6866 if (req_list == NULL) {
6867 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6868 return I40E_ERR_NO_MEMORY;
6873 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6874 memset(req_list, 0, ele_buff_size);
6876 for (i = 0; i < actual_num; i++) {
6877 rte_memcpy(req_list[i].mac_addr,
6878 &filter[num + i].macaddr, ETH_ADDR_LEN);
6879 req_list[i].vlan_tag =
6880 rte_cpu_to_le_16(filter[num + i].vlan_id);
6882 switch (filter[num + i].filter_type) {
6883 case RTE_MAC_PERFECT_MATCH:
6884 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6885 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6887 case RTE_MACVLAN_PERFECT_MATCH:
6888 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6890 case RTE_MAC_HASH_MATCH:
6891 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6892 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6894 case RTE_MACVLAN_HASH_MATCH:
6895 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6898 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6899 ret = I40E_ERR_PARAM;
6903 req_list[i].queue_number = 0;
6905 req_list[i].flags = rte_cpu_to_le_16(flags);
6908 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6910 if (ret != I40E_SUCCESS) {
6911 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6915 } while (num < total);
6923 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6924 struct i40e_macvlan_filter *filter,
6927 int ele_num, ele_buff_size;
6928 int num, actual_num, i;
6930 int ret = I40E_SUCCESS;
6931 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6932 struct i40e_aqc_remove_macvlan_element_data *req_list;
6934 if (filter == NULL || total == 0)
6935 return I40E_ERR_PARAM;
6937 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6938 ele_buff_size = hw->aq.asq_buf_size;
6940 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6941 if (req_list == NULL) {
6942 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6943 return I40E_ERR_NO_MEMORY;
6948 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6949 memset(req_list, 0, ele_buff_size);
6951 for (i = 0; i < actual_num; i++) {
6952 rte_memcpy(req_list[i].mac_addr,
6953 &filter[num + i].macaddr, ETH_ADDR_LEN);
6954 req_list[i].vlan_tag =
6955 rte_cpu_to_le_16(filter[num + i].vlan_id);
6957 switch (filter[num + i].filter_type) {
6958 case RTE_MAC_PERFECT_MATCH:
6959 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6960 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6962 case RTE_MACVLAN_PERFECT_MATCH:
6963 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6965 case RTE_MAC_HASH_MATCH:
6966 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6967 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6969 case RTE_MACVLAN_HASH_MATCH:
6970 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6973 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6974 ret = I40E_ERR_PARAM;
6977 req_list[i].flags = rte_cpu_to_le_16(flags);
6980 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6982 if (ret != I40E_SUCCESS) {
6983 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6987 } while (num < total);
6994 /* Find out specific MAC filter */
6995 static struct i40e_mac_filter *
6996 i40e_find_mac_filter(struct i40e_vsi *vsi,
6997 struct rte_ether_addr *macaddr)
6999 struct i40e_mac_filter *f;
7001 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7002 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7010 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7013 uint32_t vid_idx, vid_bit;
7015 if (vlan_id > ETH_VLAN_ID_MAX)
7018 vid_idx = I40E_VFTA_IDX(vlan_id);
7019 vid_bit = I40E_VFTA_BIT(vlan_id);
7021 if (vsi->vfta[vid_idx] & vid_bit)
7028 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7029 uint16_t vlan_id, bool on)
7031 uint32_t vid_idx, vid_bit;
7033 vid_idx = I40E_VFTA_IDX(vlan_id);
7034 vid_bit = I40E_VFTA_BIT(vlan_id);
7037 vsi->vfta[vid_idx] |= vid_bit;
7039 vsi->vfta[vid_idx] &= ~vid_bit;
7043 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7044 uint16_t vlan_id, bool on)
7046 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7047 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7050 if (vlan_id > ETH_VLAN_ID_MAX)
7053 i40e_store_vlan_filter(vsi, vlan_id, on);
7055 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7058 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7061 ret = i40e_aq_add_vlan(hw, vsi->seid,
7062 &vlan_data, 1, NULL);
7063 if (ret != I40E_SUCCESS)
7064 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7066 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7067 &vlan_data, 1, NULL);
7068 if (ret != I40E_SUCCESS)
7070 "Failed to remove vlan filter");
7075 * Find all vlan options for specific mac addr,
7076 * return with actual vlan found.
7079 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7080 struct i40e_macvlan_filter *mv_f,
7081 int num, struct rte_ether_addr *addr)
7087 * Not to use i40e_find_vlan_filter to decrease the loop time,
7088 * although the code looks complex.
7090 if (num < vsi->vlan_num)
7091 return I40E_ERR_PARAM;
7094 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7096 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7097 if (vsi->vfta[j] & (1 << k)) {
7100 "vlan number doesn't match");
7101 return I40E_ERR_PARAM;
7103 rte_memcpy(&mv_f[i].macaddr,
7104 addr, ETH_ADDR_LEN);
7106 j * I40E_UINT32_BIT_SIZE + k;
7112 return I40E_SUCCESS;
7116 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7117 struct i40e_macvlan_filter *mv_f,
7122 struct i40e_mac_filter *f;
7124 if (num < vsi->mac_num)
7125 return I40E_ERR_PARAM;
7127 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7129 PMD_DRV_LOG(ERR, "buffer number not match");
7130 return I40E_ERR_PARAM;
7132 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7134 mv_f[i].vlan_id = vlan;
7135 mv_f[i].filter_type = f->mac_info.filter_type;
7139 return I40E_SUCCESS;
7143 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7146 struct i40e_mac_filter *f;
7147 struct i40e_macvlan_filter *mv_f;
7148 int ret = I40E_SUCCESS;
7150 if (vsi == NULL || vsi->mac_num == 0)
7151 return I40E_ERR_PARAM;
7153 /* Case that no vlan is set */
7154 if (vsi->vlan_num == 0)
7157 num = vsi->mac_num * vsi->vlan_num;
7159 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7161 PMD_DRV_LOG(ERR, "failed to allocate memory");
7162 return I40E_ERR_NO_MEMORY;
7166 if (vsi->vlan_num == 0) {
7167 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7168 rte_memcpy(&mv_f[i].macaddr,
7169 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7170 mv_f[i].filter_type = f->mac_info.filter_type;
7171 mv_f[i].vlan_id = 0;
7175 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7176 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7177 vsi->vlan_num, &f->mac_info.mac_addr);
7178 if (ret != I40E_SUCCESS)
7180 for (j = i; j < i + vsi->vlan_num; j++)
7181 mv_f[j].filter_type = f->mac_info.filter_type;
7186 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7194 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7196 struct i40e_macvlan_filter *mv_f;
7198 int ret = I40E_SUCCESS;
7200 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7201 return I40E_ERR_PARAM;
7203 /* If it's already set, just return */
7204 if (i40e_find_vlan_filter(vsi,vlan))
7205 return I40E_SUCCESS;
7207 mac_num = vsi->mac_num;
7210 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7211 return I40E_ERR_PARAM;
7214 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7217 PMD_DRV_LOG(ERR, "failed to allocate memory");
7218 return I40E_ERR_NO_MEMORY;
7221 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7223 if (ret != I40E_SUCCESS)
7226 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7228 if (ret != I40E_SUCCESS)
7231 i40e_set_vlan_filter(vsi, vlan, 1);
7241 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7243 struct i40e_macvlan_filter *mv_f;
7245 int ret = I40E_SUCCESS;
7248 * Vlan 0 is the generic filter for untagged packets
7249 * and can't be removed.
7251 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7252 return I40E_ERR_PARAM;
7254 /* If can't find it, just return */
7255 if (!i40e_find_vlan_filter(vsi, vlan))
7256 return I40E_ERR_PARAM;
7258 mac_num = vsi->mac_num;
7261 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7262 return I40E_ERR_PARAM;
7265 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7268 PMD_DRV_LOG(ERR, "failed to allocate memory");
7269 return I40E_ERR_NO_MEMORY;
7272 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7274 if (ret != I40E_SUCCESS)
7277 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7279 if (ret != I40E_SUCCESS)
7282 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7283 if (vsi->vlan_num == 1) {
7284 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7285 if (ret != I40E_SUCCESS)
7288 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7289 if (ret != I40E_SUCCESS)
7293 i40e_set_vlan_filter(vsi, vlan, 0);
7303 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7305 struct i40e_mac_filter *f;
7306 struct i40e_macvlan_filter *mv_f;
7307 int i, vlan_num = 0;
7308 int ret = I40E_SUCCESS;
7310 /* If it's add and we've config it, return */
7311 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7313 return I40E_SUCCESS;
7314 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7315 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7318 * If vlan_num is 0, that's the first time to add mac,
7319 * set mask for vlan_id 0.
7321 if (vsi->vlan_num == 0) {
7322 i40e_set_vlan_filter(vsi, 0, 1);
7325 vlan_num = vsi->vlan_num;
7326 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7327 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7330 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7332 PMD_DRV_LOG(ERR, "failed to allocate memory");
7333 return I40E_ERR_NO_MEMORY;
7336 for (i = 0; i < vlan_num; i++) {
7337 mv_f[i].filter_type = mac_filter->filter_type;
7338 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7342 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7343 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7344 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7345 &mac_filter->mac_addr);
7346 if (ret != I40E_SUCCESS)
7350 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7351 if (ret != I40E_SUCCESS)
7354 /* Add the mac addr into mac list */
7355 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7357 PMD_DRV_LOG(ERR, "failed to allocate memory");
7358 ret = I40E_ERR_NO_MEMORY;
7361 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7363 f->mac_info.filter_type = mac_filter->filter_type;
7364 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7375 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7377 struct i40e_mac_filter *f;
7378 struct i40e_macvlan_filter *mv_f;
7380 enum rte_mac_filter_type filter_type;
7381 int ret = I40E_SUCCESS;
7383 /* Can't find it, return an error */
7384 f = i40e_find_mac_filter(vsi, addr);
7386 return I40E_ERR_PARAM;
7388 vlan_num = vsi->vlan_num;
7389 filter_type = f->mac_info.filter_type;
7390 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7391 filter_type == RTE_MACVLAN_HASH_MATCH) {
7392 if (vlan_num == 0) {
7393 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7394 return I40E_ERR_PARAM;
7396 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7397 filter_type == RTE_MAC_HASH_MATCH)
7400 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7402 PMD_DRV_LOG(ERR, "failed to allocate memory");
7403 return I40E_ERR_NO_MEMORY;
7406 for (i = 0; i < vlan_num; i++) {
7407 mv_f[i].filter_type = filter_type;
7408 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7411 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7412 filter_type == RTE_MACVLAN_HASH_MATCH) {
7413 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7414 if (ret != I40E_SUCCESS)
7418 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7419 if (ret != I40E_SUCCESS)
7422 /* Remove the mac addr into mac list */
7423 TAILQ_REMOVE(&vsi->mac_list, f, next);
7433 /* Configure hash enable flags for RSS */
7435 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7443 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7444 if (flags & (1ULL << i))
7445 hena |= adapter->pctypes_tbl[i];
7451 /* Parse the hash enable flags */
7453 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7455 uint64_t rss_hf = 0;
7461 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7462 if (flags & adapter->pctypes_tbl[i])
7463 rss_hf |= (1ULL << i);
7470 i40e_pf_disable_rss(struct i40e_pf *pf)
7472 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7474 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7475 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7476 I40E_WRITE_FLUSH(hw);
7480 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7482 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7483 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7484 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7485 I40E_VFQF_HKEY_MAX_INDEX :
7486 I40E_PFQF_HKEY_MAX_INDEX;
7489 if (!key || key_len == 0) {
7490 PMD_DRV_LOG(DEBUG, "No key to be configured");
7492 } else if (key_len != (key_idx + 1) *
7494 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7498 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7499 struct i40e_aqc_get_set_rss_key_data *key_dw =
7500 (struct i40e_aqc_get_set_rss_key_data *)key;
7502 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7504 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7506 uint32_t *hash_key = (uint32_t *)key;
7509 if (vsi->type == I40E_VSI_SRIOV) {
7510 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7513 I40E_VFQF_HKEY1(i, vsi->user_param),
7517 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7518 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7521 I40E_WRITE_FLUSH(hw);
7528 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7530 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7531 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7535 if (!key || !key_len)
7538 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7539 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7540 (struct i40e_aqc_get_set_rss_key_data *)key);
7542 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7546 uint32_t *key_dw = (uint32_t *)key;
7549 if (vsi->type == I40E_VSI_SRIOV) {
7550 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7551 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7552 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7554 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7557 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7558 reg = I40E_PFQF_HKEY(i);
7559 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7561 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7569 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7571 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7575 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7576 rss_conf->rss_key_len);
7580 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7581 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7582 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7583 I40E_WRITE_FLUSH(hw);
7589 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7590 struct rte_eth_rss_conf *rss_conf)
7592 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7593 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7594 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7597 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7598 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7600 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7601 if (rss_hf != 0) /* Enable RSS */
7603 return 0; /* Nothing to do */
7606 if (rss_hf == 0) /* Disable RSS */
7609 return i40e_hw_rss_hash_set(pf, rss_conf);
7613 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7614 struct rte_eth_rss_conf *rss_conf)
7616 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7617 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7624 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7625 &rss_conf->rss_key_len);
7629 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7630 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7631 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7637 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7639 switch (filter_type) {
7640 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7641 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7643 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7644 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7646 case RTE_TUNNEL_FILTER_IMAC_TENID:
7647 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7649 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7650 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7652 case ETH_TUNNEL_FILTER_IMAC:
7653 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7655 case ETH_TUNNEL_FILTER_OIP:
7656 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7658 case ETH_TUNNEL_FILTER_IIP:
7659 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7662 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7669 /* Convert tunnel filter structure */
7671 i40e_tunnel_filter_convert(
7672 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7673 struct i40e_tunnel_filter *tunnel_filter)
7675 rte_ether_addr_copy((struct rte_ether_addr *)
7676 &cld_filter->element.outer_mac,
7677 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7678 rte_ether_addr_copy((struct rte_ether_addr *)
7679 &cld_filter->element.inner_mac,
7680 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7681 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7682 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7683 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7684 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7685 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7687 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7688 tunnel_filter->input.flags = cld_filter->element.flags;
7689 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7690 tunnel_filter->queue = cld_filter->element.queue_number;
7691 rte_memcpy(tunnel_filter->input.general_fields,
7692 cld_filter->general_fields,
7693 sizeof(cld_filter->general_fields));
7698 /* Check if there exists the tunnel filter */
7699 struct i40e_tunnel_filter *
7700 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7701 const struct i40e_tunnel_filter_input *input)
7705 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7709 return tunnel_rule->hash_map[ret];
7712 /* Add a tunnel filter into the SW list */
7714 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7715 struct i40e_tunnel_filter *tunnel_filter)
7717 struct i40e_tunnel_rule *rule = &pf->tunnel;
7720 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7723 "Failed to insert tunnel filter to hash table %d!",
7727 rule->hash_map[ret] = tunnel_filter;
7729 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7734 /* Delete a tunnel filter from the SW list */
7736 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7737 struct i40e_tunnel_filter_input *input)
7739 struct i40e_tunnel_rule *rule = &pf->tunnel;
7740 struct i40e_tunnel_filter *tunnel_filter;
7743 ret = rte_hash_del_key(rule->hash_table, input);
7746 "Failed to delete tunnel filter to hash table %d!",
7750 tunnel_filter = rule->hash_map[ret];
7751 rule->hash_map[ret] = NULL;
7753 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7754 rte_free(tunnel_filter);
7760 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7761 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7765 uint32_t ipv4_addr, ipv4_addr_le;
7766 uint8_t i, tun_type = 0;
7767 /* internal varialbe to convert ipv6 byte order */
7768 uint32_t convert_ipv6[4];
7770 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7771 struct i40e_vsi *vsi = pf->main_vsi;
7772 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7773 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7774 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7775 struct i40e_tunnel_filter *tunnel, *node;
7776 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7778 cld_filter = rte_zmalloc("tunnel_filter",
7779 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7782 if (NULL == cld_filter) {
7783 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7786 pfilter = cld_filter;
7788 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7789 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7790 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7791 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7793 pfilter->element.inner_vlan =
7794 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7795 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7796 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7797 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7798 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7799 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7801 sizeof(pfilter->element.ipaddr.v4.data));
7803 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7804 for (i = 0; i < 4; i++) {
7806 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7808 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7810 sizeof(pfilter->element.ipaddr.v6.data));
7813 /* check tunneled type */
7814 switch (tunnel_filter->tunnel_type) {
7815 case RTE_TUNNEL_TYPE_VXLAN:
7816 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7818 case RTE_TUNNEL_TYPE_NVGRE:
7819 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7821 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7822 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7824 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7825 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7828 /* Other tunnel types is not supported. */
7829 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7830 rte_free(cld_filter);
7834 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7835 &pfilter->element.flags);
7837 rte_free(cld_filter);
7841 pfilter->element.flags |= rte_cpu_to_le_16(
7842 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7843 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7844 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7845 pfilter->element.queue_number =
7846 rte_cpu_to_le_16(tunnel_filter->queue_id);
7848 /* Check if there is the filter in SW list */
7849 memset(&check_filter, 0, sizeof(check_filter));
7850 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7851 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7853 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7854 rte_free(cld_filter);
7858 if (!add && !node) {
7859 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7860 rte_free(cld_filter);
7865 ret = i40e_aq_add_cloud_filters(hw,
7866 vsi->seid, &cld_filter->element, 1);
7868 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7869 rte_free(cld_filter);
7872 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7873 if (tunnel == NULL) {
7874 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7875 rte_free(cld_filter);
7879 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7880 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7884 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7885 &cld_filter->element, 1);
7887 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7888 rte_free(cld_filter);
7891 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7894 rte_free(cld_filter);
7898 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7899 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7900 #define I40E_TR_GENEVE_KEY_MASK 0x8
7901 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7902 #define I40E_TR_GRE_KEY_MASK 0x400
7903 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7904 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7907 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7909 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7910 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7911 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7912 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7913 enum i40e_status_code status = I40E_SUCCESS;
7915 if (pf->support_multi_driver) {
7916 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7917 return I40E_NOT_SUPPORTED;
7920 memset(&filter_replace, 0,
7921 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7922 memset(&filter_replace_buf, 0,
7923 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7925 /* create L1 filter */
7926 filter_replace.old_filter_type =
7927 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7928 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7929 filter_replace.tr_bit = 0;
7931 /* Prepare the buffer, 3 entries */
7932 filter_replace_buf.data[0] =
7933 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7934 filter_replace_buf.data[0] |=
7935 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7936 filter_replace_buf.data[2] = 0xFF;
7937 filter_replace_buf.data[3] = 0xFF;
7938 filter_replace_buf.data[4] =
7939 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7940 filter_replace_buf.data[4] |=
7941 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7942 filter_replace_buf.data[7] = 0xF0;
7943 filter_replace_buf.data[8]
7944 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7945 filter_replace_buf.data[8] |=
7946 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7947 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7948 I40E_TR_GENEVE_KEY_MASK |
7949 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7950 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7951 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7952 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7954 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7955 &filter_replace_buf);
7956 if (!status && (filter_replace.old_filter_type !=
7957 filter_replace.new_filter_type))
7958 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7959 " original: 0x%x, new: 0x%x",
7961 filter_replace.old_filter_type,
7962 filter_replace.new_filter_type);
7968 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7970 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7971 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7972 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7973 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7974 enum i40e_status_code status = I40E_SUCCESS;
7976 if (pf->support_multi_driver) {
7977 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7978 return I40E_NOT_SUPPORTED;
7982 memset(&filter_replace, 0,
7983 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7984 memset(&filter_replace_buf, 0,
7985 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7986 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7987 I40E_AQC_MIRROR_CLOUD_FILTER;
7988 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7989 filter_replace.new_filter_type =
7990 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7991 /* Prepare the buffer, 2 entries */
7992 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7993 filter_replace_buf.data[0] |=
7994 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7995 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7996 filter_replace_buf.data[4] |=
7997 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7998 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7999 &filter_replace_buf);
8002 if (filter_replace.old_filter_type !=
8003 filter_replace.new_filter_type)
8004 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8005 " original: 0x%x, new: 0x%x",
8007 filter_replace.old_filter_type,
8008 filter_replace.new_filter_type);
8011 memset(&filter_replace, 0,
8012 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8013 memset(&filter_replace_buf, 0,
8014 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8016 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8017 I40E_AQC_MIRROR_CLOUD_FILTER;
8018 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8019 filter_replace.new_filter_type =
8020 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8021 /* Prepare the buffer, 2 entries */
8022 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8023 filter_replace_buf.data[0] |=
8024 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8025 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8026 filter_replace_buf.data[4] |=
8027 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8029 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8030 &filter_replace_buf);
8031 if (!status && (filter_replace.old_filter_type !=
8032 filter_replace.new_filter_type))
8033 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8034 " original: 0x%x, new: 0x%x",
8036 filter_replace.old_filter_type,
8037 filter_replace.new_filter_type);
8042 static enum i40e_status_code
8043 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8045 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8046 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8047 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8048 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8049 enum i40e_status_code status = I40E_SUCCESS;
8051 if (pf->support_multi_driver) {
8052 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8053 return I40E_NOT_SUPPORTED;
8057 memset(&filter_replace, 0,
8058 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8059 memset(&filter_replace_buf, 0,
8060 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8061 /* create L1 filter */
8062 filter_replace.old_filter_type =
8063 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8064 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8065 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8066 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8067 /* Prepare the buffer, 2 entries */
8068 filter_replace_buf.data[0] =
8069 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8070 filter_replace_buf.data[0] |=
8071 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8072 filter_replace_buf.data[2] = 0xFF;
8073 filter_replace_buf.data[3] = 0xFF;
8074 filter_replace_buf.data[4] =
8075 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8076 filter_replace_buf.data[4] |=
8077 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8078 filter_replace_buf.data[6] = 0xFF;
8079 filter_replace_buf.data[7] = 0xFF;
8080 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8081 &filter_replace_buf);
8084 if (filter_replace.old_filter_type !=
8085 filter_replace.new_filter_type)
8086 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8087 " original: 0x%x, new: 0x%x",
8089 filter_replace.old_filter_type,
8090 filter_replace.new_filter_type);
8093 memset(&filter_replace, 0,
8094 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8095 memset(&filter_replace_buf, 0,
8096 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8097 /* create L1 filter */
8098 filter_replace.old_filter_type =
8099 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8100 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8101 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8102 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8103 /* Prepare the buffer, 2 entries */
8104 filter_replace_buf.data[0] =
8105 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8106 filter_replace_buf.data[0] |=
8107 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8108 filter_replace_buf.data[2] = 0xFF;
8109 filter_replace_buf.data[3] = 0xFF;
8110 filter_replace_buf.data[4] =
8111 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8112 filter_replace_buf.data[4] |=
8113 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8114 filter_replace_buf.data[6] = 0xFF;
8115 filter_replace_buf.data[7] = 0xFF;
8117 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8118 &filter_replace_buf);
8119 if (!status && (filter_replace.old_filter_type !=
8120 filter_replace.new_filter_type))
8121 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8122 " original: 0x%x, new: 0x%x",
8124 filter_replace.old_filter_type,
8125 filter_replace.new_filter_type);
8131 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8133 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8134 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8135 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8136 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8137 enum i40e_status_code status = I40E_SUCCESS;
8139 if (pf->support_multi_driver) {
8140 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8141 return I40E_NOT_SUPPORTED;
8145 memset(&filter_replace, 0,
8146 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8147 memset(&filter_replace_buf, 0,
8148 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8149 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8150 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8151 filter_replace.new_filter_type =
8152 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8153 /* Prepare the buffer, 2 entries */
8154 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8155 filter_replace_buf.data[0] |=
8156 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8157 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8158 filter_replace_buf.data[4] |=
8159 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8160 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8161 &filter_replace_buf);
8164 if (filter_replace.old_filter_type !=
8165 filter_replace.new_filter_type)
8166 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8167 " original: 0x%x, new: 0x%x",
8169 filter_replace.old_filter_type,
8170 filter_replace.new_filter_type);
8173 memset(&filter_replace, 0,
8174 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8175 memset(&filter_replace_buf, 0,
8176 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8177 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8178 filter_replace.old_filter_type =
8179 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8180 filter_replace.new_filter_type =
8181 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8182 /* Prepare the buffer, 2 entries */
8183 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8184 filter_replace_buf.data[0] |=
8185 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8186 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8187 filter_replace_buf.data[4] |=
8188 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8190 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8191 &filter_replace_buf);
8192 if (!status && (filter_replace.old_filter_type !=
8193 filter_replace.new_filter_type))
8194 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8195 " original: 0x%x, new: 0x%x",
8197 filter_replace.old_filter_type,
8198 filter_replace.new_filter_type);
8204 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8205 struct i40e_tunnel_filter_conf *tunnel_filter,
8209 uint32_t ipv4_addr, ipv4_addr_le;
8210 uint8_t i, tun_type = 0;
8211 /* internal variable to convert ipv6 byte order */
8212 uint32_t convert_ipv6[4];
8214 struct i40e_pf_vf *vf = NULL;
8215 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8216 struct i40e_vsi *vsi;
8217 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8218 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8219 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8220 struct i40e_tunnel_filter *tunnel, *node;
8221 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8223 bool big_buffer = 0;
8225 cld_filter = rte_zmalloc("tunnel_filter",
8226 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8229 if (cld_filter == NULL) {
8230 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8233 pfilter = cld_filter;
8235 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8236 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8237 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8238 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8240 pfilter->element.inner_vlan =
8241 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8242 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8243 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8244 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8245 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8246 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8248 sizeof(pfilter->element.ipaddr.v4.data));
8250 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8251 for (i = 0; i < 4; i++) {
8253 rte_cpu_to_le_32(rte_be_to_cpu_32(
8254 tunnel_filter->ip_addr.ipv6_addr[i]));
8256 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8258 sizeof(pfilter->element.ipaddr.v6.data));
8261 /* check tunneled type */
8262 switch (tunnel_filter->tunnel_type) {
8263 case I40E_TUNNEL_TYPE_VXLAN:
8264 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8266 case I40E_TUNNEL_TYPE_NVGRE:
8267 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8269 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8270 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8272 case I40E_TUNNEL_TYPE_MPLSoUDP:
8273 if (!pf->mpls_replace_flag) {
8274 i40e_replace_mpls_l1_filter(pf);
8275 i40e_replace_mpls_cloud_filter(pf);
8276 pf->mpls_replace_flag = 1;
8278 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8279 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8281 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8282 (teid_le & 0xF) << 12;
8283 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8286 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8288 case I40E_TUNNEL_TYPE_MPLSoGRE:
8289 if (!pf->mpls_replace_flag) {
8290 i40e_replace_mpls_l1_filter(pf);
8291 i40e_replace_mpls_cloud_filter(pf);
8292 pf->mpls_replace_flag = 1;
8294 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8295 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8297 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8298 (teid_le & 0xF) << 12;
8299 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8302 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8304 case I40E_TUNNEL_TYPE_GTPC:
8305 if (!pf->gtp_replace_flag) {
8306 i40e_replace_gtp_l1_filter(pf);
8307 i40e_replace_gtp_cloud_filter(pf);
8308 pf->gtp_replace_flag = 1;
8310 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8311 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8312 (teid_le >> 16) & 0xFFFF;
8313 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8315 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8319 case I40E_TUNNEL_TYPE_GTPU:
8320 if (!pf->gtp_replace_flag) {
8321 i40e_replace_gtp_l1_filter(pf);
8322 i40e_replace_gtp_cloud_filter(pf);
8323 pf->gtp_replace_flag = 1;
8325 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8326 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8327 (teid_le >> 16) & 0xFFFF;
8328 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8330 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8334 case I40E_TUNNEL_TYPE_QINQ:
8335 if (!pf->qinq_replace_flag) {
8336 ret = i40e_cloud_filter_qinq_create(pf);
8339 "QinQ tunnel filter already created.");
8340 pf->qinq_replace_flag = 1;
8342 /* Add in the General fields the values of
8343 * the Outer and Inner VLAN
8344 * Big Buffer should be set, see changes in
8345 * i40e_aq_add_cloud_filters
8347 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8348 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8352 /* Other tunnel types is not supported. */
8353 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8354 rte_free(cld_filter);
8358 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8359 pfilter->element.flags =
8360 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8361 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8362 pfilter->element.flags =
8363 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8364 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8365 pfilter->element.flags =
8366 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8367 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8368 pfilter->element.flags =
8369 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8370 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8371 pfilter->element.flags |=
8372 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8374 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8375 &pfilter->element.flags);
8377 rte_free(cld_filter);
8382 pfilter->element.flags |= rte_cpu_to_le_16(
8383 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8384 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8385 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8386 pfilter->element.queue_number =
8387 rte_cpu_to_le_16(tunnel_filter->queue_id);
8389 if (!tunnel_filter->is_to_vf)
8392 if (tunnel_filter->vf_id >= pf->vf_num) {
8393 PMD_DRV_LOG(ERR, "Invalid argument.");
8394 rte_free(cld_filter);
8397 vf = &pf->vfs[tunnel_filter->vf_id];
8401 /* Check if there is the filter in SW list */
8402 memset(&check_filter, 0, sizeof(check_filter));
8403 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8404 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8405 check_filter.vf_id = tunnel_filter->vf_id;
8406 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8408 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8409 rte_free(cld_filter);
8413 if (!add && !node) {
8414 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8415 rte_free(cld_filter);
8421 ret = i40e_aq_add_cloud_filters_bb(hw,
8422 vsi->seid, cld_filter, 1);
8424 ret = i40e_aq_add_cloud_filters(hw,
8425 vsi->seid, &cld_filter->element, 1);
8427 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8428 rte_free(cld_filter);
8431 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8432 if (tunnel == NULL) {
8433 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8434 rte_free(cld_filter);
8438 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8439 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8444 ret = i40e_aq_rem_cloud_filters_bb(
8445 hw, vsi->seid, cld_filter, 1);
8447 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8448 &cld_filter->element, 1);
8450 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8451 rte_free(cld_filter);
8454 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8457 rte_free(cld_filter);
8462 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8466 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8467 if (pf->vxlan_ports[i] == port)
8475 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8479 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8481 idx = i40e_get_vxlan_port_idx(pf, port);
8483 /* Check if port already exists */
8485 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8489 /* Now check if there is space to add the new port */
8490 idx = i40e_get_vxlan_port_idx(pf, 0);
8493 "Maximum number of UDP ports reached, not adding port %d",
8498 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8501 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8505 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8508 /* New port: add it and mark its index in the bitmap */
8509 pf->vxlan_ports[idx] = port;
8510 pf->vxlan_bitmap |= (1 << idx);
8512 if (!(pf->flags & I40E_FLAG_VXLAN))
8513 pf->flags |= I40E_FLAG_VXLAN;
8519 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8522 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8524 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8525 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8529 idx = i40e_get_vxlan_port_idx(pf, port);
8532 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8536 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8537 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8541 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8544 pf->vxlan_ports[idx] = 0;
8545 pf->vxlan_bitmap &= ~(1 << idx);
8547 if (!pf->vxlan_bitmap)
8548 pf->flags &= ~I40E_FLAG_VXLAN;
8553 /* Add UDP tunneling port */
8555 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8556 struct rte_eth_udp_tunnel *udp_tunnel)
8559 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8561 if (udp_tunnel == NULL)
8564 switch (udp_tunnel->prot_type) {
8565 case RTE_TUNNEL_TYPE_VXLAN:
8566 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8567 I40E_AQC_TUNNEL_TYPE_VXLAN);
8569 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8570 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8571 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8573 case RTE_TUNNEL_TYPE_GENEVE:
8574 case RTE_TUNNEL_TYPE_TEREDO:
8575 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8580 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8588 /* Remove UDP tunneling port */
8590 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8591 struct rte_eth_udp_tunnel *udp_tunnel)
8594 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8596 if (udp_tunnel == NULL)
8599 switch (udp_tunnel->prot_type) {
8600 case RTE_TUNNEL_TYPE_VXLAN:
8601 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8602 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8604 case RTE_TUNNEL_TYPE_GENEVE:
8605 case RTE_TUNNEL_TYPE_TEREDO:
8606 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8610 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8618 /* Calculate the maximum number of contiguous PF queues that are configured */
8620 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8622 struct rte_eth_dev_data *data = pf->dev_data;
8624 struct i40e_rx_queue *rxq;
8627 for (i = 0; i < pf->lan_nb_qps; i++) {
8628 rxq = data->rx_queues[i];
8629 if (rxq && rxq->q_set)
8640 i40e_pf_config_rss(struct i40e_pf *pf)
8642 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8643 struct rte_eth_rss_conf rss_conf;
8644 uint32_t i, lut = 0;
8648 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8649 * It's necessary to calculate the actual PF queues that are configured.
8651 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8652 num = i40e_pf_calc_configured_queues_num(pf);
8654 num = pf->dev_data->nb_rx_queues;
8656 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8657 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8661 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8665 if (pf->adapter->rss_reta_updated == 0) {
8666 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8669 lut = (lut << 8) | (j & ((0x1 <<
8670 hw->func_caps.rss_table_entry_width) - 1));
8672 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8677 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8678 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8679 i40e_pf_disable_rss(pf);
8682 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8683 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8684 /* Random default keys */
8685 static uint32_t rss_key_default[] = {0x6b793944,
8686 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8687 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8688 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8690 rss_conf.rss_key = (uint8_t *)rss_key_default;
8691 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8695 return i40e_hw_rss_hash_set(pf, &rss_conf);
8699 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8700 struct rte_eth_tunnel_filter_conf *filter)
8702 if (pf == NULL || filter == NULL) {
8703 PMD_DRV_LOG(ERR, "Invalid parameter");
8707 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8708 PMD_DRV_LOG(ERR, "Invalid queue ID");
8712 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8713 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8717 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8718 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8719 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8723 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8724 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8725 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8732 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8733 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8735 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8737 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8741 if (pf->support_multi_driver) {
8742 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8746 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8747 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8750 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8751 } else if (len == 4) {
8752 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8754 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8759 ret = i40e_aq_debug_write_global_register(hw,
8760 I40E_GL_PRS_FVBM(2),
8764 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8765 "with value 0x%08x",
8766 I40E_GL_PRS_FVBM(2), reg);
8770 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8771 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8777 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8784 switch (cfg->cfg_type) {
8785 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8786 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8789 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8797 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8798 enum rte_filter_op filter_op,
8801 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8802 int ret = I40E_ERR_PARAM;
8804 switch (filter_op) {
8805 case RTE_ETH_FILTER_SET:
8806 ret = i40e_dev_global_config_set(hw,
8807 (struct rte_eth_global_cfg *)arg);
8810 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8818 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8819 enum rte_filter_op filter_op,
8822 struct rte_eth_tunnel_filter_conf *filter;
8823 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8824 int ret = I40E_SUCCESS;
8826 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8828 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8829 return I40E_ERR_PARAM;
8831 switch (filter_op) {
8832 case RTE_ETH_FILTER_NOP:
8833 if (!(pf->flags & I40E_FLAG_VXLAN))
8834 ret = I40E_NOT_SUPPORTED;
8836 case RTE_ETH_FILTER_ADD:
8837 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8839 case RTE_ETH_FILTER_DELETE:
8840 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8843 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8844 ret = I40E_ERR_PARAM;
8852 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8855 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8858 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8859 ret = i40e_pf_config_rss(pf);
8861 i40e_pf_disable_rss(pf);
8866 /* Get the symmetric hash enable configurations per port */
8868 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8870 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8872 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8875 /* Set the symmetric hash enable configurations per port */
8877 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8879 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8882 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8884 "Symmetric hash has already been enabled");
8887 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8889 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8891 "Symmetric hash has already been disabled");
8894 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8896 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8897 I40E_WRITE_FLUSH(hw);
8901 * Get global configurations of hash function type and symmetric hash enable
8902 * per flow type (pctype). Note that global configuration means it affects all
8903 * the ports on the same NIC.
8906 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8907 struct rte_eth_hash_global_conf *g_cfg)
8909 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8913 memset(g_cfg, 0, sizeof(*g_cfg));
8914 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8915 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8916 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8918 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8919 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8920 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8923 * As i40e supports less than 64 flow types, only first 64 bits need to
8926 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8927 g_cfg->valid_bit_mask[i] = 0ULL;
8928 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8931 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8933 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8934 if (!adapter->pctypes_tbl[i])
8936 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8937 j < I40E_FILTER_PCTYPE_MAX; j++) {
8938 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8939 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8940 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8941 g_cfg->sym_hash_enable_mask[0] |=
8952 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8953 const struct rte_eth_hash_global_conf *g_cfg)
8956 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8958 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8959 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8960 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8961 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8967 * As i40e supports less than 64 flow types, only first 64 bits need to
8970 mask0 = g_cfg->valid_bit_mask[0];
8971 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8973 /* Check if any unsupported flow type configured */
8974 if ((mask0 | i40e_mask) ^ i40e_mask)
8977 if (g_cfg->valid_bit_mask[i])
8985 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8991 * Set global configurations of hash function type and symmetric hash enable
8992 * per flow type (pctype). Note any modifying global configuration will affect
8993 * all the ports on the same NIC.
8996 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8997 struct rte_eth_hash_global_conf *g_cfg)
8999 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9000 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9004 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9006 if (pf->support_multi_driver) {
9007 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9011 /* Check the input parameters */
9012 ret = i40e_hash_global_config_check(adapter, g_cfg);
9017 * As i40e supports less than 64 flow types, only first 64 bits need to
9020 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9021 if (mask0 & (1UL << i)) {
9022 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9023 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9025 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9026 j < I40E_FILTER_PCTYPE_MAX; j++) {
9027 if (adapter->pctypes_tbl[i] & (1ULL << j))
9028 i40e_write_global_rx_ctl(hw,
9035 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9036 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9038 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9040 "Hash function already set to Toeplitz");
9043 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9044 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9046 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9048 "Hash function already set to Simple XOR");
9051 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9053 /* Use the default, and keep it as it is */
9056 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9059 I40E_WRITE_FLUSH(hw);
9065 * Valid input sets for hash and flow director filters per PCTYPE
9068 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9069 enum rte_filter_type filter)
9073 static const uint64_t valid_hash_inset_table[] = {
9074 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9075 I40E_INSET_DMAC | I40E_INSET_SMAC |
9076 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9077 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9078 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9079 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9080 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9081 I40E_INSET_FLEX_PAYLOAD,
9082 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9083 I40E_INSET_DMAC | I40E_INSET_SMAC |
9084 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9085 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9086 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9087 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9088 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9089 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9090 I40E_INSET_FLEX_PAYLOAD,
9091 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9092 I40E_INSET_DMAC | I40E_INSET_SMAC |
9093 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9094 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9095 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9096 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9097 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9098 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9099 I40E_INSET_FLEX_PAYLOAD,
9100 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9101 I40E_INSET_DMAC | I40E_INSET_SMAC |
9102 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9103 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9104 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9105 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9106 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9107 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9108 I40E_INSET_FLEX_PAYLOAD,
9109 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9110 I40E_INSET_DMAC | I40E_INSET_SMAC |
9111 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9112 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9113 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9114 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9115 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9116 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9117 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9118 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9119 I40E_INSET_DMAC | I40E_INSET_SMAC |
9120 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9121 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9122 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9123 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9124 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9125 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9126 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9127 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9128 I40E_INSET_DMAC | I40E_INSET_SMAC |
9129 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9130 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9131 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9132 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9133 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9134 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9135 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9136 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9137 I40E_INSET_DMAC | I40E_INSET_SMAC |
9138 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9139 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9140 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9141 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9142 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9143 I40E_INSET_FLEX_PAYLOAD,
9144 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9145 I40E_INSET_DMAC | I40E_INSET_SMAC |
9146 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9147 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9148 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9149 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9150 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9151 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9152 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9153 I40E_INSET_DMAC | I40E_INSET_SMAC |
9154 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9155 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9156 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9157 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9158 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9159 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9160 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9161 I40E_INSET_DMAC | I40E_INSET_SMAC |
9162 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9163 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9164 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9165 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9166 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9167 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9168 I40E_INSET_FLEX_PAYLOAD,
9169 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9170 I40E_INSET_DMAC | I40E_INSET_SMAC |
9171 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9172 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9173 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9174 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9175 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9176 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9177 I40E_INSET_FLEX_PAYLOAD,
9178 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9179 I40E_INSET_DMAC | I40E_INSET_SMAC |
9180 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9181 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9182 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9183 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9184 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9185 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9186 I40E_INSET_FLEX_PAYLOAD,
9187 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9188 I40E_INSET_DMAC | I40E_INSET_SMAC |
9189 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9190 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9191 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9192 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9193 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9194 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9195 I40E_INSET_FLEX_PAYLOAD,
9196 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9197 I40E_INSET_DMAC | I40E_INSET_SMAC |
9198 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9199 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9200 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9201 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9202 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9203 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9204 I40E_INSET_FLEX_PAYLOAD,
9205 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9206 I40E_INSET_DMAC | I40E_INSET_SMAC |
9207 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9208 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9209 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9210 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9211 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9212 I40E_INSET_FLEX_PAYLOAD,
9213 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9214 I40E_INSET_DMAC | I40E_INSET_SMAC |
9215 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9216 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9217 I40E_INSET_FLEX_PAYLOAD,
9221 * Flow director supports only fields defined in
9222 * union rte_eth_fdir_flow.
9224 static const uint64_t valid_fdir_inset_table[] = {
9225 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9226 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9227 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9228 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9229 I40E_INSET_IPV4_TTL,
9230 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9231 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9232 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9233 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9234 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9235 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9236 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9237 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9238 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9239 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9240 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9241 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9242 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9243 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9244 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9245 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9246 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9247 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9248 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9249 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9250 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9251 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9252 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9253 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9254 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9255 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9256 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9257 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9258 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9259 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9261 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9262 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9263 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9264 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9265 I40E_INSET_IPV4_TTL,
9266 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9267 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9268 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9269 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9270 I40E_INSET_IPV6_HOP_LIMIT,
9271 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9272 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9273 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9274 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9275 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9276 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9277 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9278 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9279 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9280 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9281 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9282 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9283 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9284 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9285 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9286 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9287 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9288 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9289 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9290 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9291 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9292 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9293 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9294 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9295 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9296 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9297 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9298 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9299 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9300 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9302 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9303 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9304 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9305 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9306 I40E_INSET_IPV6_HOP_LIMIT,
9307 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9308 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9309 I40E_INSET_LAST_ETHER_TYPE,
9312 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9314 if (filter == RTE_ETH_FILTER_HASH)
9315 valid = valid_hash_inset_table[pctype];
9317 valid = valid_fdir_inset_table[pctype];
9323 * Validate if the input set is allowed for a specific PCTYPE
9326 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9327 enum rte_filter_type filter, uint64_t inset)
9331 valid = i40e_get_valid_input_set(pctype, filter);
9332 if (inset & (~valid))
9338 /* default input set fields combination per pctype */
9340 i40e_get_default_input_set(uint16_t pctype)
9342 static const uint64_t default_inset_table[] = {
9343 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9344 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9345 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9346 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9347 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9348 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9349 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9350 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9351 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9352 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9353 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9354 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9355 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9356 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9357 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9358 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9359 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9360 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9361 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9362 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9364 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9365 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9366 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9367 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9368 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9369 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9370 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9371 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9372 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9373 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9374 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9375 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9376 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9377 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9378 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9379 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9380 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9381 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9382 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9383 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9384 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9385 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9387 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9388 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9389 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9390 I40E_INSET_LAST_ETHER_TYPE,
9393 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9396 return default_inset_table[pctype];
9400 * Parse the input set from index to logical bit masks
9403 i40e_parse_input_set(uint64_t *inset,
9404 enum i40e_filter_pctype pctype,
9405 enum rte_eth_input_set_field *field,
9411 static const struct {
9412 enum rte_eth_input_set_field field;
9414 } inset_convert_table[] = {
9415 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9416 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9417 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9418 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9419 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9420 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9421 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9422 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9423 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9424 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9425 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9426 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9427 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9428 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9429 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9430 I40E_INSET_IPV6_NEXT_HDR},
9431 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9432 I40E_INSET_IPV6_HOP_LIMIT},
9433 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9434 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9435 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9436 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9437 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9438 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9439 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9440 I40E_INSET_SCTP_VT},
9441 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9442 I40E_INSET_TUNNEL_DMAC},
9443 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9444 I40E_INSET_VLAN_TUNNEL},
9445 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9446 I40E_INSET_TUNNEL_ID},
9447 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9448 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9449 I40E_INSET_FLEX_PAYLOAD_W1},
9450 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9451 I40E_INSET_FLEX_PAYLOAD_W2},
9452 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9453 I40E_INSET_FLEX_PAYLOAD_W3},
9454 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9455 I40E_INSET_FLEX_PAYLOAD_W4},
9456 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9457 I40E_INSET_FLEX_PAYLOAD_W5},
9458 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9459 I40E_INSET_FLEX_PAYLOAD_W6},
9460 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9461 I40E_INSET_FLEX_PAYLOAD_W7},
9462 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9463 I40E_INSET_FLEX_PAYLOAD_W8},
9466 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9469 /* Only one item allowed for default or all */
9471 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9472 *inset = i40e_get_default_input_set(pctype);
9474 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9475 *inset = I40E_INSET_NONE;
9480 for (i = 0, *inset = 0; i < size; i++) {
9481 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9482 if (field[i] == inset_convert_table[j].field) {
9483 *inset |= inset_convert_table[j].inset;
9488 /* It contains unsupported input set, return immediately */
9489 if (j == RTE_DIM(inset_convert_table))
9497 * Translate the input set from bit masks to register aware bit masks
9501 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9511 static const struct inset_map inset_map_common[] = {
9512 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9513 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9514 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9515 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9516 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9517 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9518 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9519 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9520 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9521 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9522 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9523 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9524 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9525 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9526 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9527 {I40E_INSET_TUNNEL_DMAC,
9528 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9529 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9530 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9531 {I40E_INSET_TUNNEL_SRC_PORT,
9532 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9533 {I40E_INSET_TUNNEL_DST_PORT,
9534 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9535 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9536 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9537 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9538 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9539 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9540 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9541 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9542 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9543 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9546 /* some different registers map in x722*/
9547 static const struct inset_map inset_map_diff_x722[] = {
9548 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9549 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9550 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9551 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9554 static const struct inset_map inset_map_diff_not_x722[] = {
9555 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9556 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9557 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9558 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9564 /* Translate input set to register aware inset */
9565 if (type == I40E_MAC_X722) {
9566 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9567 if (input & inset_map_diff_x722[i].inset)
9568 val |= inset_map_diff_x722[i].inset_reg;
9571 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9572 if (input & inset_map_diff_not_x722[i].inset)
9573 val |= inset_map_diff_not_x722[i].inset_reg;
9577 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9578 if (input & inset_map_common[i].inset)
9579 val |= inset_map_common[i].inset_reg;
9586 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9589 uint64_t inset_need_mask = inset;
9591 static const struct {
9594 } inset_mask_map[] = {
9595 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9596 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9597 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9598 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9599 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9600 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9601 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9602 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9605 if (!inset || !mask || !nb_elem)
9608 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9609 /* Clear the inset bit, if no MASK is required,
9610 * for example proto + ttl
9612 if ((inset & inset_mask_map[i].inset) ==
9613 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9614 inset_need_mask &= ~inset_mask_map[i].inset;
9615 if (!inset_need_mask)
9618 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9619 if ((inset_need_mask & inset_mask_map[i].inset) ==
9620 inset_mask_map[i].inset) {
9621 if (idx >= nb_elem) {
9622 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9625 mask[idx] = inset_mask_map[i].mask;
9634 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9636 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9638 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9640 i40e_write_rx_ctl(hw, addr, val);
9641 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9642 (uint32_t)i40e_read_rx_ctl(hw, addr));
9646 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9648 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9649 struct rte_eth_dev *dev;
9651 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9653 i40e_write_rx_ctl(hw, addr, val);
9654 PMD_DRV_LOG(WARNING,
9655 "i40e device %s changed global register [0x%08x]."
9656 " original: 0x%08x, new: 0x%08x",
9657 dev->device->name, addr, reg,
9658 (uint32_t)i40e_read_rx_ctl(hw, addr));
9663 i40e_filter_input_set_init(struct i40e_pf *pf)
9665 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9666 enum i40e_filter_pctype pctype;
9667 uint64_t input_set, inset_reg;
9668 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9672 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9673 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9674 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9676 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9679 input_set = i40e_get_default_input_set(pctype);
9681 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9682 I40E_INSET_MASK_NUM_REG);
9685 if (pf->support_multi_driver && num > 0) {
9686 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9689 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9692 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9693 (uint32_t)(inset_reg & UINT32_MAX));
9694 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9695 (uint32_t)((inset_reg >>
9696 I40E_32_BIT_WIDTH) & UINT32_MAX));
9697 if (!pf->support_multi_driver) {
9698 i40e_check_write_global_reg(hw,
9699 I40E_GLQF_HASH_INSET(0, pctype),
9700 (uint32_t)(inset_reg & UINT32_MAX));
9701 i40e_check_write_global_reg(hw,
9702 I40E_GLQF_HASH_INSET(1, pctype),
9703 (uint32_t)((inset_reg >>
9704 I40E_32_BIT_WIDTH) & UINT32_MAX));
9706 for (i = 0; i < num; i++) {
9707 i40e_check_write_global_reg(hw,
9708 I40E_GLQF_FD_MSK(i, pctype),
9710 i40e_check_write_global_reg(hw,
9711 I40E_GLQF_HASH_MSK(i, pctype),
9714 /*clear unused mask registers of the pctype */
9715 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9716 i40e_check_write_global_reg(hw,
9717 I40E_GLQF_FD_MSK(i, pctype),
9719 i40e_check_write_global_reg(hw,
9720 I40E_GLQF_HASH_MSK(i, pctype),
9724 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9726 I40E_WRITE_FLUSH(hw);
9728 /* store the default input set */
9729 if (!pf->support_multi_driver)
9730 pf->hash_input_set[pctype] = input_set;
9731 pf->fdir.input_set[pctype] = input_set;
9736 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9737 struct rte_eth_input_set_conf *conf)
9739 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9740 enum i40e_filter_pctype pctype;
9741 uint64_t input_set, inset_reg = 0;
9742 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9746 PMD_DRV_LOG(ERR, "Invalid pointer");
9749 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9750 conf->op != RTE_ETH_INPUT_SET_ADD) {
9751 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9755 if (pf->support_multi_driver) {
9756 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9760 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9761 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9762 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9766 if (hw->mac.type == I40E_MAC_X722) {
9767 /* get translated pctype value in fd pctype register */
9768 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9769 I40E_GLQF_FD_PCTYPES((int)pctype));
9772 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9775 PMD_DRV_LOG(ERR, "Failed to parse input set");
9779 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9780 /* get inset value in register */
9781 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9782 inset_reg <<= I40E_32_BIT_WIDTH;
9783 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9784 input_set |= pf->hash_input_set[pctype];
9786 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9787 I40E_INSET_MASK_NUM_REG);
9791 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9793 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9794 (uint32_t)(inset_reg & UINT32_MAX));
9795 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9796 (uint32_t)((inset_reg >>
9797 I40E_32_BIT_WIDTH) & UINT32_MAX));
9799 for (i = 0; i < num; i++)
9800 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9802 /*clear unused mask registers of the pctype */
9803 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9804 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9806 I40E_WRITE_FLUSH(hw);
9808 pf->hash_input_set[pctype] = input_set;
9813 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9814 struct rte_eth_input_set_conf *conf)
9816 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9817 enum i40e_filter_pctype pctype;
9818 uint64_t input_set, inset_reg = 0;
9819 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9823 PMD_DRV_LOG(ERR, "Invalid pointer");
9826 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9827 conf->op != RTE_ETH_INPUT_SET_ADD) {
9828 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9832 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9834 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9835 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9839 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9842 PMD_DRV_LOG(ERR, "Failed to parse input set");
9846 /* get inset value in register */
9847 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9848 inset_reg <<= I40E_32_BIT_WIDTH;
9849 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9851 /* Can not change the inset reg for flex payload for fdir,
9852 * it is done by writing I40E_PRTQF_FD_FLXINSET
9853 * in i40e_set_flex_mask_on_pctype.
9855 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9856 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9858 input_set |= pf->fdir.input_set[pctype];
9859 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9860 I40E_INSET_MASK_NUM_REG);
9863 if (pf->support_multi_driver && num > 0) {
9864 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9868 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9870 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9871 (uint32_t)(inset_reg & UINT32_MAX));
9872 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9873 (uint32_t)((inset_reg >>
9874 I40E_32_BIT_WIDTH) & UINT32_MAX));
9876 if (!pf->support_multi_driver) {
9877 for (i = 0; i < num; i++)
9878 i40e_check_write_global_reg(hw,
9879 I40E_GLQF_FD_MSK(i, pctype),
9881 /*clear unused mask registers of the pctype */
9882 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9883 i40e_check_write_global_reg(hw,
9884 I40E_GLQF_FD_MSK(i, pctype),
9887 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9889 I40E_WRITE_FLUSH(hw);
9891 pf->fdir.input_set[pctype] = input_set;
9896 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9901 PMD_DRV_LOG(ERR, "Invalid pointer");
9905 switch (info->info_type) {
9906 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9907 i40e_get_symmetric_hash_enable_per_port(hw,
9908 &(info->info.enable));
9910 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9911 ret = i40e_get_hash_filter_global_config(hw,
9912 &(info->info.global_conf));
9915 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9925 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9930 PMD_DRV_LOG(ERR, "Invalid pointer");
9934 switch (info->info_type) {
9935 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9936 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9938 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9939 ret = i40e_set_hash_filter_global_config(hw,
9940 &(info->info.global_conf));
9942 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9943 ret = i40e_hash_filter_inset_select(hw,
9944 &(info->info.input_set_conf));
9948 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9957 /* Operations for hash function */
9959 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9960 enum rte_filter_op filter_op,
9963 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9966 switch (filter_op) {
9967 case RTE_ETH_FILTER_NOP:
9969 case RTE_ETH_FILTER_GET:
9970 ret = i40e_hash_filter_get(hw,
9971 (struct rte_eth_hash_filter_info *)arg);
9973 case RTE_ETH_FILTER_SET:
9974 ret = i40e_hash_filter_set(hw,
9975 (struct rte_eth_hash_filter_info *)arg);
9978 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9987 /* Convert ethertype filter structure */
9989 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9990 struct i40e_ethertype_filter *filter)
9992 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9993 RTE_ETHER_ADDR_LEN);
9994 filter->input.ether_type = input->ether_type;
9995 filter->flags = input->flags;
9996 filter->queue = input->queue;
10001 /* Check if there exists the ehtertype filter */
10002 struct i40e_ethertype_filter *
10003 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10004 const struct i40e_ethertype_filter_input *input)
10008 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10012 return ethertype_rule->hash_map[ret];
10015 /* Add ethertype filter in SW list */
10017 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10018 struct i40e_ethertype_filter *filter)
10020 struct i40e_ethertype_rule *rule = &pf->ethertype;
10023 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10026 "Failed to insert ethertype filter"
10027 " to hash table %d!",
10031 rule->hash_map[ret] = filter;
10033 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10038 /* Delete ethertype filter in SW list */
10040 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10041 struct i40e_ethertype_filter_input *input)
10043 struct i40e_ethertype_rule *rule = &pf->ethertype;
10044 struct i40e_ethertype_filter *filter;
10047 ret = rte_hash_del_key(rule->hash_table, input);
10050 "Failed to delete ethertype filter"
10051 " to hash table %d!",
10055 filter = rule->hash_map[ret];
10056 rule->hash_map[ret] = NULL;
10058 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10065 * Configure ethertype filter, which can director packet by filtering
10066 * with mac address and ether_type or only ether_type
10069 i40e_ethertype_filter_set(struct i40e_pf *pf,
10070 struct rte_eth_ethertype_filter *filter,
10073 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10074 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10075 struct i40e_ethertype_filter *ethertype_filter, *node;
10076 struct i40e_ethertype_filter check_filter;
10077 struct i40e_control_filter_stats stats;
10078 uint16_t flags = 0;
10081 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10082 PMD_DRV_LOG(ERR, "Invalid queue ID");
10085 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10086 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10088 "unsupported ether_type(0x%04x) in control packet filter.",
10089 filter->ether_type);
10092 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10093 PMD_DRV_LOG(WARNING,
10094 "filter vlan ether_type in first tag is not supported.");
10096 /* Check if there is the filter in SW list */
10097 memset(&check_filter, 0, sizeof(check_filter));
10098 i40e_ethertype_filter_convert(filter, &check_filter);
10099 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10100 &check_filter.input);
10102 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10106 if (!add && !node) {
10107 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10111 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10112 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10113 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10114 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10115 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10117 memset(&stats, 0, sizeof(stats));
10118 ret = i40e_aq_add_rem_control_packet_filter(hw,
10119 filter->mac_addr.addr_bytes,
10120 filter->ether_type, flags,
10121 pf->main_vsi->seid,
10122 filter->queue, add, &stats, NULL);
10125 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10126 ret, stats.mac_etype_used, stats.etype_used,
10127 stats.mac_etype_free, stats.etype_free);
10131 /* Add or delete a filter in SW list */
10133 ethertype_filter = rte_zmalloc("ethertype_filter",
10134 sizeof(*ethertype_filter), 0);
10135 if (ethertype_filter == NULL) {
10136 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10140 rte_memcpy(ethertype_filter, &check_filter,
10141 sizeof(check_filter));
10142 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10144 rte_free(ethertype_filter);
10146 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10153 * Handle operations for ethertype filter.
10156 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10157 enum rte_filter_op filter_op,
10160 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10163 if (filter_op == RTE_ETH_FILTER_NOP)
10167 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10172 switch (filter_op) {
10173 case RTE_ETH_FILTER_ADD:
10174 ret = i40e_ethertype_filter_set(pf,
10175 (struct rte_eth_ethertype_filter *)arg,
10178 case RTE_ETH_FILTER_DELETE:
10179 ret = i40e_ethertype_filter_set(pf,
10180 (struct rte_eth_ethertype_filter *)arg,
10184 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10192 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10193 enum rte_filter_type filter_type,
10194 enum rte_filter_op filter_op,
10202 switch (filter_type) {
10203 case RTE_ETH_FILTER_NONE:
10204 /* For global configuration */
10205 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10207 case RTE_ETH_FILTER_HASH:
10208 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10210 case RTE_ETH_FILTER_MACVLAN:
10211 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10213 case RTE_ETH_FILTER_ETHERTYPE:
10214 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10216 case RTE_ETH_FILTER_TUNNEL:
10217 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10219 case RTE_ETH_FILTER_FDIR:
10220 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10222 case RTE_ETH_FILTER_GENERIC:
10223 if (filter_op != RTE_ETH_FILTER_GET)
10225 *(const void **)arg = &i40e_flow_ops;
10228 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10238 * Check and enable Extended Tag.
10239 * Enabling Extended Tag is important for 40G performance.
10242 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10244 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10248 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10251 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10255 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10256 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10261 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10264 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10268 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10269 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10272 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10273 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10276 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10283 * As some registers wouldn't be reset unless a global hardware reset,
10284 * hardware initialization is needed to put those registers into an
10285 * expected initial state.
10288 i40e_hw_init(struct rte_eth_dev *dev)
10290 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10292 i40e_enable_extended_tag(dev);
10294 /* clear the PF Queue Filter control register */
10295 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10297 /* Disable symmetric hash per port */
10298 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10302 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10303 * however this function will return only one highest pctype index,
10304 * which is not quite correct. This is known problem of i40e driver
10305 * and needs to be fixed later.
10307 enum i40e_filter_pctype
10308 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10311 uint64_t pctype_mask;
10313 if (flow_type < I40E_FLOW_TYPE_MAX) {
10314 pctype_mask = adapter->pctypes_tbl[flow_type];
10315 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10316 if (pctype_mask & (1ULL << i))
10317 return (enum i40e_filter_pctype)i;
10320 return I40E_FILTER_PCTYPE_INVALID;
10324 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10325 enum i40e_filter_pctype pctype)
10328 uint64_t pctype_mask = 1ULL << pctype;
10330 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10332 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10336 return RTE_ETH_FLOW_UNKNOWN;
10340 * On X710, performance number is far from the expectation on recent firmware
10341 * versions; on XL710, performance number is also far from the expectation on
10342 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10343 * mode is enabled and port MAC address is equal to the packet destination MAC
10344 * address. The fix for this issue may not be integrated in the following
10345 * firmware version. So the workaround in software driver is needed. It needs
10346 * to modify the initial values of 3 internal only registers for both X710 and
10347 * XL710. Note that the values for X710 or XL710 could be different, and the
10348 * workaround can be removed when it is fixed in firmware in the future.
10351 /* For both X710 and XL710 */
10352 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10353 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10354 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10356 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10357 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10360 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10361 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10364 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10366 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10367 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10370 * GL_SWR_PM_UP_THR:
10371 * The value is not impacted from the link speed, its value is set according
10372 * to the total number of ports for a better pipe-monitor configuration.
10375 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10377 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10378 .device_id = (dev), \
10379 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10381 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10382 .device_id = (dev), \
10383 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10385 static const struct {
10386 uint16_t device_id;
10388 } swr_pm_table[] = {
10389 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10390 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10391 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10392 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10394 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10395 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10396 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10397 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10398 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10399 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10400 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10404 if (value == NULL) {
10405 PMD_DRV_LOG(ERR, "value is NULL");
10409 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10410 if (hw->device_id == swr_pm_table[i].device_id) {
10411 *value = swr_pm_table[i].val;
10413 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10415 hw->device_id, *value);
10424 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10426 enum i40e_status_code status;
10427 struct i40e_aq_get_phy_abilities_resp phy_ab;
10428 int ret = -ENOTSUP;
10431 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10435 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10438 rte_delay_us(100000);
10440 status = i40e_aq_get_phy_capabilities(hw, false,
10441 true, &phy_ab, NULL);
10449 i40e_configure_registers(struct i40e_hw *hw)
10455 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10456 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10457 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10463 for (i = 0; i < RTE_DIM(reg_table); i++) {
10464 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10465 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10467 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10468 else /* For X710/XL710/XXV710 */
10469 if (hw->aq.fw_maj_ver < 6)
10471 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10474 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10477 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10478 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10480 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10481 else /* For X710/XL710/XXV710 */
10483 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10486 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10489 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10490 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10491 "GL_SWR_PM_UP_THR value fixup",
10496 reg_table[i].val = cfg_val;
10499 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10502 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10503 reg_table[i].addr);
10506 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10507 reg_table[i].addr, reg);
10508 if (reg == reg_table[i].val)
10511 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10512 reg_table[i].val, NULL);
10515 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10516 reg_table[i].val, reg_table[i].addr);
10519 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10520 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10524 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10525 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10526 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10527 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10529 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10534 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10535 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10539 /* Configure for double VLAN RX stripping */
10540 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10541 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10542 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10543 ret = i40e_aq_debug_write_register(hw,
10544 I40E_VSI_TSR(vsi->vsi_id),
10547 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10549 return I40E_ERR_CONFIG;
10553 /* Configure for double VLAN TX insertion */
10554 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10555 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10556 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10557 ret = i40e_aq_debug_write_register(hw,
10558 I40E_VSI_L2TAGSTXVALID(
10559 vsi->vsi_id), reg, NULL);
10562 "Failed to update VSI_L2TAGSTXVALID[%d]",
10564 return I40E_ERR_CONFIG;
10572 * i40e_aq_add_mirror_rule
10573 * @hw: pointer to the hardware structure
10574 * @seid: VEB seid to add mirror rule to
10575 * @dst_id: destination vsi seid
10576 * @entries: Buffer which contains the entities to be mirrored
10577 * @count: number of entities contained in the buffer
10578 * @rule_id:the rule_id of the rule to be added
10580 * Add a mirror rule for a given veb.
10583 static enum i40e_status_code
10584 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10585 uint16_t seid, uint16_t dst_id,
10586 uint16_t rule_type, uint16_t *entries,
10587 uint16_t count, uint16_t *rule_id)
10589 struct i40e_aq_desc desc;
10590 struct i40e_aqc_add_delete_mirror_rule cmd;
10591 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10592 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10595 enum i40e_status_code status;
10597 i40e_fill_default_direct_cmd_desc(&desc,
10598 i40e_aqc_opc_add_mirror_rule);
10599 memset(&cmd, 0, sizeof(cmd));
10601 buff_len = sizeof(uint16_t) * count;
10602 desc.datalen = rte_cpu_to_le_16(buff_len);
10604 desc.flags |= rte_cpu_to_le_16(
10605 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10606 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10607 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10608 cmd.num_entries = rte_cpu_to_le_16(count);
10609 cmd.seid = rte_cpu_to_le_16(seid);
10610 cmd.destination = rte_cpu_to_le_16(dst_id);
10612 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10613 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10615 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10616 hw->aq.asq_last_status, resp->rule_id,
10617 resp->mirror_rules_used, resp->mirror_rules_free);
10618 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10624 * i40e_aq_del_mirror_rule
10625 * @hw: pointer to the hardware structure
10626 * @seid: VEB seid to add mirror rule to
10627 * @entries: Buffer which contains the entities to be mirrored
10628 * @count: number of entities contained in the buffer
10629 * @rule_id:the rule_id of the rule to be delete
10631 * Delete a mirror rule for a given veb.
10634 static enum i40e_status_code
10635 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10636 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10637 uint16_t count, uint16_t rule_id)
10639 struct i40e_aq_desc desc;
10640 struct i40e_aqc_add_delete_mirror_rule cmd;
10641 uint16_t buff_len = 0;
10642 enum i40e_status_code status;
10645 i40e_fill_default_direct_cmd_desc(&desc,
10646 i40e_aqc_opc_delete_mirror_rule);
10647 memset(&cmd, 0, sizeof(cmd));
10648 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10649 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10651 cmd.num_entries = count;
10652 buff_len = sizeof(uint16_t) * count;
10653 desc.datalen = rte_cpu_to_le_16(buff_len);
10654 buff = (void *)entries;
10656 /* rule id is filled in destination field for deleting mirror rule */
10657 cmd.destination = rte_cpu_to_le_16(rule_id);
10659 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10660 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10661 cmd.seid = rte_cpu_to_le_16(seid);
10663 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10664 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10670 * i40e_mirror_rule_set
10671 * @dev: pointer to the hardware structure
10672 * @mirror_conf: mirror rule info
10673 * @sw_id: mirror rule's sw_id
10674 * @on: enable/disable
10676 * set a mirror rule.
10680 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10681 struct rte_eth_mirror_conf *mirror_conf,
10682 uint8_t sw_id, uint8_t on)
10684 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10685 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10686 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10687 struct i40e_mirror_rule *parent = NULL;
10688 uint16_t seid, dst_seid, rule_id;
10692 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10694 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10696 "mirror rule can not be configured without veb or vfs.");
10699 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10700 PMD_DRV_LOG(ERR, "mirror table is full.");
10703 if (mirror_conf->dst_pool > pf->vf_num) {
10704 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10705 mirror_conf->dst_pool);
10709 seid = pf->main_vsi->veb->seid;
10711 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10712 if (sw_id <= it->index) {
10718 if (mirr_rule && sw_id == mirr_rule->index) {
10720 PMD_DRV_LOG(ERR, "mirror rule exists.");
10723 ret = i40e_aq_del_mirror_rule(hw, seid,
10724 mirr_rule->rule_type,
10725 mirr_rule->entries,
10726 mirr_rule->num_entries, mirr_rule->id);
10729 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10730 ret, hw->aq.asq_last_status);
10733 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10734 rte_free(mirr_rule);
10735 pf->nb_mirror_rule--;
10739 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10743 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10744 sizeof(struct i40e_mirror_rule) , 0);
10746 PMD_DRV_LOG(ERR, "failed to allocate memory");
10747 return I40E_ERR_NO_MEMORY;
10749 switch (mirror_conf->rule_type) {
10750 case ETH_MIRROR_VLAN:
10751 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10752 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10753 mirr_rule->entries[j] =
10754 mirror_conf->vlan.vlan_id[i];
10759 PMD_DRV_LOG(ERR, "vlan is not specified.");
10760 rte_free(mirr_rule);
10763 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10765 case ETH_MIRROR_VIRTUAL_POOL_UP:
10766 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10767 /* check if the specified pool bit is out of range */
10768 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10769 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10770 rte_free(mirr_rule);
10773 for (i = 0, j = 0; i < pf->vf_num; i++) {
10774 if (mirror_conf->pool_mask & (1ULL << i)) {
10775 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10779 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10780 /* add pf vsi to entries */
10781 mirr_rule->entries[j] = pf->main_vsi_seid;
10785 PMD_DRV_LOG(ERR, "pool is not specified.");
10786 rte_free(mirr_rule);
10789 /* egress and ingress in aq commands means from switch but not port */
10790 mirr_rule->rule_type =
10791 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10792 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10793 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10795 case ETH_MIRROR_UPLINK_PORT:
10796 /* egress and ingress in aq commands means from switch but not port*/
10797 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10799 case ETH_MIRROR_DOWNLINK_PORT:
10800 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10803 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10804 mirror_conf->rule_type);
10805 rte_free(mirr_rule);
10809 /* If the dst_pool is equal to vf_num, consider it as PF */
10810 if (mirror_conf->dst_pool == pf->vf_num)
10811 dst_seid = pf->main_vsi_seid;
10813 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10815 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10816 mirr_rule->rule_type, mirr_rule->entries,
10820 "failed to add mirror rule: ret = %d, aq_err = %d.",
10821 ret, hw->aq.asq_last_status);
10822 rte_free(mirr_rule);
10826 mirr_rule->index = sw_id;
10827 mirr_rule->num_entries = j;
10828 mirr_rule->id = rule_id;
10829 mirr_rule->dst_vsi_seid = dst_seid;
10832 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10834 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10836 pf->nb_mirror_rule++;
10841 * i40e_mirror_rule_reset
10842 * @dev: pointer to the device
10843 * @sw_id: mirror rule's sw_id
10845 * reset a mirror rule.
10849 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10851 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10852 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10853 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10857 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10859 seid = pf->main_vsi->veb->seid;
10861 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10862 if (sw_id == it->index) {
10868 ret = i40e_aq_del_mirror_rule(hw, seid,
10869 mirr_rule->rule_type,
10870 mirr_rule->entries,
10871 mirr_rule->num_entries, mirr_rule->id);
10874 "failed to remove mirror rule: status = %d, aq_err = %d.",
10875 ret, hw->aq.asq_last_status);
10878 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10879 rte_free(mirr_rule);
10880 pf->nb_mirror_rule--;
10882 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10889 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10891 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10892 uint64_t systim_cycles;
10894 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10895 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10898 return systim_cycles;
10902 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10904 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10905 uint64_t rx_tstamp;
10907 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10908 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10915 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10917 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10918 uint64_t tx_tstamp;
10920 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10921 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10928 i40e_start_timecounters(struct rte_eth_dev *dev)
10930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10931 struct i40e_adapter *adapter = dev->data->dev_private;
10932 struct rte_eth_link link;
10933 uint32_t tsync_inc_l;
10934 uint32_t tsync_inc_h;
10936 /* Get current link speed. */
10937 i40e_dev_link_update(dev, 1);
10938 rte_eth_linkstatus_get(dev, &link);
10940 switch (link.link_speed) {
10941 case ETH_SPEED_NUM_40G:
10942 case ETH_SPEED_NUM_25G:
10943 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10944 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10946 case ETH_SPEED_NUM_10G:
10947 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10948 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10950 case ETH_SPEED_NUM_1G:
10951 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10952 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10959 /* Set the timesync increment value. */
10960 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10961 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10963 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10964 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10965 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10967 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10968 adapter->systime_tc.cc_shift = 0;
10969 adapter->systime_tc.nsec_mask = 0;
10971 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10972 adapter->rx_tstamp_tc.cc_shift = 0;
10973 adapter->rx_tstamp_tc.nsec_mask = 0;
10975 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10976 adapter->tx_tstamp_tc.cc_shift = 0;
10977 adapter->tx_tstamp_tc.nsec_mask = 0;
10981 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10983 struct i40e_adapter *adapter = dev->data->dev_private;
10985 adapter->systime_tc.nsec += delta;
10986 adapter->rx_tstamp_tc.nsec += delta;
10987 adapter->tx_tstamp_tc.nsec += delta;
10993 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10996 struct i40e_adapter *adapter = dev->data->dev_private;
10998 ns = rte_timespec_to_ns(ts);
11000 /* Set the timecounters to a new value. */
11001 adapter->systime_tc.nsec = ns;
11002 adapter->rx_tstamp_tc.nsec = ns;
11003 adapter->tx_tstamp_tc.nsec = ns;
11009 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11011 uint64_t ns, systime_cycles;
11012 struct i40e_adapter *adapter = dev->data->dev_private;
11014 systime_cycles = i40e_read_systime_cyclecounter(dev);
11015 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11016 *ts = rte_ns_to_timespec(ns);
11022 i40e_timesync_enable(struct rte_eth_dev *dev)
11024 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11025 uint32_t tsync_ctl_l;
11026 uint32_t tsync_ctl_h;
11028 /* Stop the timesync system time. */
11029 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11030 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11031 /* Reset the timesync system time value. */
11032 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11033 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11035 i40e_start_timecounters(dev);
11037 /* Clear timesync registers. */
11038 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11039 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11040 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11041 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11042 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11043 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11045 /* Enable timestamping of PTP packets. */
11046 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11047 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11049 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11050 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11051 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11053 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11054 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11060 i40e_timesync_disable(struct rte_eth_dev *dev)
11062 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11063 uint32_t tsync_ctl_l;
11064 uint32_t tsync_ctl_h;
11066 /* Disable timestamping of transmitted PTP packets. */
11067 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11068 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11070 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11071 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11073 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11074 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11076 /* Reset the timesync increment value. */
11077 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11078 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11084 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11085 struct timespec *timestamp, uint32_t flags)
11087 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11088 struct i40e_adapter *adapter = dev->data->dev_private;
11089 uint32_t sync_status;
11090 uint32_t index = flags & 0x03;
11091 uint64_t rx_tstamp_cycles;
11094 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11095 if ((sync_status & (1 << index)) == 0)
11098 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11099 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11100 *timestamp = rte_ns_to_timespec(ns);
11106 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11107 struct timespec *timestamp)
11109 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11110 struct i40e_adapter *adapter = dev->data->dev_private;
11111 uint32_t sync_status;
11112 uint64_t tx_tstamp_cycles;
11115 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11116 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11119 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11120 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11121 *timestamp = rte_ns_to_timespec(ns);
11127 * i40e_parse_dcb_configure - parse dcb configure from user
11128 * @dev: the device being configured
11129 * @dcb_cfg: pointer of the result of parse
11130 * @*tc_map: bit map of enabled traffic classes
11132 * Returns 0 on success, negative value on failure
11135 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11136 struct i40e_dcbx_config *dcb_cfg,
11139 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11140 uint8_t i, tc_bw, bw_lf;
11142 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11144 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11145 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11146 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11150 /* assume each tc has the same bw */
11151 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11152 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11153 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11154 /* to ensure the sum of tcbw is equal to 100 */
11155 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11156 for (i = 0; i < bw_lf; i++)
11157 dcb_cfg->etscfg.tcbwtable[i]++;
11159 /* assume each tc has the same Transmission Selection Algorithm */
11160 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11161 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11163 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11164 dcb_cfg->etscfg.prioritytable[i] =
11165 dcb_rx_conf->dcb_tc[i];
11167 /* FW needs one App to configure HW */
11168 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11169 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11170 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11171 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11173 if (dcb_rx_conf->nb_tcs == 0)
11174 *tc_map = 1; /* tc0 only */
11176 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11178 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11179 dcb_cfg->pfc.willing = 0;
11180 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11181 dcb_cfg->pfc.pfcenable = *tc_map;
11187 static enum i40e_status_code
11188 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11189 struct i40e_aqc_vsi_properties_data *info,
11190 uint8_t enabled_tcmap)
11192 enum i40e_status_code ret;
11193 int i, total_tc = 0;
11194 uint16_t qpnum_per_tc, bsf, qp_idx;
11195 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11196 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11197 uint16_t used_queues;
11199 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11200 if (ret != I40E_SUCCESS)
11203 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11204 if (enabled_tcmap & (1 << i))
11209 vsi->enabled_tc = enabled_tcmap;
11211 /* different VSI has different queues assigned */
11212 if (vsi->type == I40E_VSI_MAIN)
11213 used_queues = dev_data->nb_rx_queues -
11214 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11215 else if (vsi->type == I40E_VSI_VMDQ2)
11216 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11218 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11219 return I40E_ERR_NO_AVAILABLE_VSI;
11222 qpnum_per_tc = used_queues / total_tc;
11223 /* Number of queues per enabled TC */
11224 if (qpnum_per_tc == 0) {
11225 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11226 return I40E_ERR_INVALID_QP_ID;
11228 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11229 I40E_MAX_Q_PER_TC);
11230 bsf = rte_bsf32(qpnum_per_tc);
11233 * Configure TC and queue mapping parameters, for enabled TC,
11234 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11235 * default queue will serve it.
11238 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11239 if (vsi->enabled_tc & (1 << i)) {
11240 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11241 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11242 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11243 qp_idx += qpnum_per_tc;
11245 info->tc_mapping[i] = 0;
11248 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11249 if (vsi->type == I40E_VSI_SRIOV) {
11250 info->mapping_flags |=
11251 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11252 for (i = 0; i < vsi->nb_qps; i++)
11253 info->queue_mapping[i] =
11254 rte_cpu_to_le_16(vsi->base_queue + i);
11256 info->mapping_flags |=
11257 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11258 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11260 info->valid_sections |=
11261 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11263 return I40E_SUCCESS;
11267 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11268 * @veb: VEB to be configured
11269 * @tc_map: enabled TC bitmap
11271 * Returns 0 on success, negative value on failure
11273 static enum i40e_status_code
11274 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11276 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11277 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11278 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11279 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11280 enum i40e_status_code ret = I40E_SUCCESS;
11284 /* Check if enabled_tc is same as existing or new TCs */
11285 if (veb->enabled_tc == tc_map)
11288 /* configure tc bandwidth */
11289 memset(&veb_bw, 0, sizeof(veb_bw));
11290 veb_bw.tc_valid_bits = tc_map;
11291 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11292 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11293 if (tc_map & BIT_ULL(i))
11294 veb_bw.tc_bw_share_credits[i] = 1;
11296 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11300 "AQ command Config switch_comp BW allocation per TC failed = %d",
11301 hw->aq.asq_last_status);
11305 memset(&ets_query, 0, sizeof(ets_query));
11306 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11308 if (ret != I40E_SUCCESS) {
11310 "Failed to get switch_comp ETS configuration %u",
11311 hw->aq.asq_last_status);
11314 memset(&bw_query, 0, sizeof(bw_query));
11315 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11317 if (ret != I40E_SUCCESS) {
11319 "Failed to get switch_comp bandwidth configuration %u",
11320 hw->aq.asq_last_status);
11324 /* store and print out BW info */
11325 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11326 veb->bw_info.bw_max = ets_query.tc_bw_max;
11327 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11328 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11329 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11330 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11331 I40E_16_BIT_WIDTH);
11332 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11333 veb->bw_info.bw_ets_share_credits[i] =
11334 bw_query.tc_bw_share_credits[i];
11335 veb->bw_info.bw_ets_credits[i] =
11336 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11337 /* 4 bits per TC, 4th bit is reserved */
11338 veb->bw_info.bw_ets_max[i] =
11339 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11340 RTE_LEN2MASK(3, uint8_t));
11341 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11342 veb->bw_info.bw_ets_share_credits[i]);
11343 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11344 veb->bw_info.bw_ets_credits[i]);
11345 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11346 veb->bw_info.bw_ets_max[i]);
11349 veb->enabled_tc = tc_map;
11356 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11357 * @vsi: VSI to be configured
11358 * @tc_map: enabled TC bitmap
11360 * Returns 0 on success, negative value on failure
11362 static enum i40e_status_code
11363 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11365 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11366 struct i40e_vsi_context ctxt;
11367 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11368 enum i40e_status_code ret = I40E_SUCCESS;
11371 /* Check if enabled_tc is same as existing or new TCs */
11372 if (vsi->enabled_tc == tc_map)
11375 /* configure tc bandwidth */
11376 memset(&bw_data, 0, sizeof(bw_data));
11377 bw_data.tc_valid_bits = tc_map;
11378 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11379 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11380 if (tc_map & BIT_ULL(i))
11381 bw_data.tc_bw_credits[i] = 1;
11383 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11386 "AQ command Config VSI BW allocation per TC failed = %d",
11387 hw->aq.asq_last_status);
11390 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11391 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11393 /* Update Queue Pairs Mapping for currently enabled UPs */
11394 ctxt.seid = vsi->seid;
11395 ctxt.pf_num = hw->pf_id;
11397 ctxt.uplink_seid = vsi->uplink_seid;
11398 ctxt.info = vsi->info;
11400 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11404 /* Update the VSI after updating the VSI queue-mapping information */
11405 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11407 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11408 hw->aq.asq_last_status);
11411 /* update the local VSI info with updated queue map */
11412 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11413 sizeof(vsi->info.tc_mapping));
11414 rte_memcpy(&vsi->info.queue_mapping,
11415 &ctxt.info.queue_mapping,
11416 sizeof(vsi->info.queue_mapping));
11417 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11418 vsi->info.valid_sections = 0;
11420 /* query and update current VSI BW information */
11421 ret = i40e_vsi_get_bw_config(vsi);
11424 "Failed updating vsi bw info, err %s aq_err %s",
11425 i40e_stat_str(hw, ret),
11426 i40e_aq_str(hw, hw->aq.asq_last_status));
11430 vsi->enabled_tc = tc_map;
11437 * i40e_dcb_hw_configure - program the dcb setting to hw
11438 * @pf: pf the configuration is taken on
11439 * @new_cfg: new configuration
11440 * @tc_map: enabled TC bitmap
11442 * Returns 0 on success, negative value on failure
11444 static enum i40e_status_code
11445 i40e_dcb_hw_configure(struct i40e_pf *pf,
11446 struct i40e_dcbx_config *new_cfg,
11449 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11450 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11451 struct i40e_vsi *main_vsi = pf->main_vsi;
11452 struct i40e_vsi_list *vsi_list;
11453 enum i40e_status_code ret;
11457 /* Use the FW API if FW > v4.4*/
11458 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11459 (hw->aq.fw_maj_ver >= 5))) {
11461 "FW < v4.4, can not use FW LLDP API to configure DCB");
11462 return I40E_ERR_FIRMWARE_API_VERSION;
11465 /* Check if need reconfiguration */
11466 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11467 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11468 return I40E_SUCCESS;
11471 /* Copy the new config to the current config */
11472 *old_cfg = *new_cfg;
11473 old_cfg->etsrec = old_cfg->etscfg;
11474 ret = i40e_set_dcb_config(hw);
11476 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11477 i40e_stat_str(hw, ret),
11478 i40e_aq_str(hw, hw->aq.asq_last_status));
11481 /* set receive Arbiter to RR mode and ETS scheme by default */
11482 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11483 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11484 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11485 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11486 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11487 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11488 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11489 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11490 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11491 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11492 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11493 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11494 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11496 /* get local mib to check whether it is configured correctly */
11498 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11499 /* Get Local DCB Config */
11500 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11501 &hw->local_dcbx_config);
11503 /* if Veb is created, need to update TC of it at first */
11504 if (main_vsi->veb) {
11505 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11507 PMD_INIT_LOG(WARNING,
11508 "Failed configuring TC for VEB seid=%d",
11509 main_vsi->veb->seid);
11511 /* Update each VSI */
11512 i40e_vsi_config_tc(main_vsi, tc_map);
11513 if (main_vsi->veb) {
11514 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11515 /* Beside main VSI and VMDQ VSIs, only enable default
11516 * TC for other VSIs
11518 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11519 ret = i40e_vsi_config_tc(vsi_list->vsi,
11522 ret = i40e_vsi_config_tc(vsi_list->vsi,
11523 I40E_DEFAULT_TCMAP);
11525 PMD_INIT_LOG(WARNING,
11526 "Failed configuring TC for VSI seid=%d",
11527 vsi_list->vsi->seid);
11531 return I40E_SUCCESS;
11535 * i40e_dcb_init_configure - initial dcb config
11536 * @dev: device being configured
11537 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11539 * Returns 0 on success, negative value on failure
11542 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11544 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11545 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11548 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11549 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11553 /* DCB initialization:
11554 * Update DCB configuration from the Firmware and configure
11555 * LLDP MIB change event.
11557 if (sw_dcb == TRUE) {
11558 if (i40e_need_stop_lldp(dev)) {
11559 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11560 if (ret != I40E_SUCCESS)
11561 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11564 ret = i40e_init_dcb(hw);
11565 /* If lldp agent is stopped, the return value from
11566 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11567 * adminq status. Otherwise, it should return success.
11569 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11570 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11571 memset(&hw->local_dcbx_config, 0,
11572 sizeof(struct i40e_dcbx_config));
11573 /* set dcb default configuration */
11574 hw->local_dcbx_config.etscfg.willing = 0;
11575 hw->local_dcbx_config.etscfg.maxtcs = 0;
11576 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11577 hw->local_dcbx_config.etscfg.tsatable[0] =
11579 /* all UPs mapping to TC0 */
11580 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11581 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11582 hw->local_dcbx_config.etsrec =
11583 hw->local_dcbx_config.etscfg;
11584 hw->local_dcbx_config.pfc.willing = 0;
11585 hw->local_dcbx_config.pfc.pfccap =
11586 I40E_MAX_TRAFFIC_CLASS;
11587 /* FW needs one App to configure HW */
11588 hw->local_dcbx_config.numapps = 1;
11589 hw->local_dcbx_config.app[0].selector =
11590 I40E_APP_SEL_ETHTYPE;
11591 hw->local_dcbx_config.app[0].priority = 3;
11592 hw->local_dcbx_config.app[0].protocolid =
11593 I40E_APP_PROTOID_FCOE;
11594 ret = i40e_set_dcb_config(hw);
11597 "default dcb config fails. err = %d, aq_err = %d.",
11598 ret, hw->aq.asq_last_status);
11603 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11604 ret, hw->aq.asq_last_status);
11608 ret = i40e_aq_start_lldp(hw, NULL);
11609 if (ret != I40E_SUCCESS)
11610 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11612 ret = i40e_init_dcb(hw);
11614 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11616 "HW doesn't support DCBX offload.");
11621 "DCBX configuration failed, err = %d, aq_err = %d.",
11622 ret, hw->aq.asq_last_status);
11630 * i40e_dcb_setup - setup dcb related config
11631 * @dev: device being configured
11633 * Returns 0 on success, negative value on failure
11636 i40e_dcb_setup(struct rte_eth_dev *dev)
11638 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11639 struct i40e_dcbx_config dcb_cfg;
11640 uint8_t tc_map = 0;
11643 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11644 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11648 if (pf->vf_num != 0)
11649 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11651 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11653 PMD_INIT_LOG(ERR, "invalid dcb config");
11656 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11658 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11666 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11667 struct rte_eth_dcb_info *dcb_info)
11669 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11670 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11671 struct i40e_vsi *vsi = pf->main_vsi;
11672 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11673 uint16_t bsf, tc_mapping;
11676 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11677 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11679 dcb_info->nb_tcs = 1;
11680 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11681 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11682 for (i = 0; i < dcb_info->nb_tcs; i++)
11683 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11685 /* get queue mapping if vmdq is disabled */
11686 if (!pf->nb_cfg_vmdq_vsi) {
11687 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11688 if (!(vsi->enabled_tc & (1 << i)))
11690 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11691 dcb_info->tc_queue.tc_rxq[j][i].base =
11692 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11693 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11694 dcb_info->tc_queue.tc_txq[j][i].base =
11695 dcb_info->tc_queue.tc_rxq[j][i].base;
11696 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11697 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11698 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11699 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11700 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11705 /* get queue mapping if vmdq is enabled */
11707 vsi = pf->vmdq[j].vsi;
11708 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11709 if (!(vsi->enabled_tc & (1 << i)))
11711 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11712 dcb_info->tc_queue.tc_rxq[j][i].base =
11713 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11714 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11715 dcb_info->tc_queue.tc_txq[j][i].base =
11716 dcb_info->tc_queue.tc_rxq[j][i].base;
11717 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11718 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11719 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11720 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11721 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11724 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11729 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11732 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11733 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11734 uint16_t msix_intr;
11736 msix_intr = intr_handle->intr_vec[queue_id];
11737 if (msix_intr == I40E_MISC_VEC_ID)
11738 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11739 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11740 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11741 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11744 I40E_PFINT_DYN_CTLN(msix_intr -
11745 I40E_RX_VEC_START),
11746 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11747 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11748 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11750 I40E_WRITE_FLUSH(hw);
11751 rte_intr_ack(&pci_dev->intr_handle);
11757 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11759 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11760 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11761 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11762 uint16_t msix_intr;
11764 msix_intr = intr_handle->intr_vec[queue_id];
11765 if (msix_intr == I40E_MISC_VEC_ID)
11766 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11767 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11770 I40E_PFINT_DYN_CTLN(msix_intr -
11771 I40E_RX_VEC_START),
11772 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11773 I40E_WRITE_FLUSH(hw);
11779 * This function is used to check if the register is valid.
11780 * Below is the valid registers list for X722 only:
11784 * 0x208e00--0x209000
11785 * 0x20be00--0x20c000
11786 * 0x263c00--0x264000
11787 * 0x265c00--0x266000
11789 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11791 if ((type != I40E_MAC_X722) &&
11792 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11793 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11794 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11795 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11796 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11797 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11798 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11804 static int i40e_get_regs(struct rte_eth_dev *dev,
11805 struct rte_dev_reg_info *regs)
11807 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11808 uint32_t *ptr_data = regs->data;
11809 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11810 const struct i40e_reg_info *reg_info;
11812 if (ptr_data == NULL) {
11813 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11814 regs->width = sizeof(uint32_t);
11818 /* The first few registers have to be read using AQ operations */
11820 while (i40e_regs_adminq[reg_idx].name) {
11821 reg_info = &i40e_regs_adminq[reg_idx++];
11822 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11824 arr_idx2 <= reg_info->count2;
11826 reg_offset = arr_idx * reg_info->stride1 +
11827 arr_idx2 * reg_info->stride2;
11828 reg_offset += reg_info->base_addr;
11829 ptr_data[reg_offset >> 2] =
11830 i40e_read_rx_ctl(hw, reg_offset);
11834 /* The remaining registers can be read using primitives */
11836 while (i40e_regs_others[reg_idx].name) {
11837 reg_info = &i40e_regs_others[reg_idx++];
11838 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11840 arr_idx2 <= reg_info->count2;
11842 reg_offset = arr_idx * reg_info->stride1 +
11843 arr_idx2 * reg_info->stride2;
11844 reg_offset += reg_info->base_addr;
11845 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11846 ptr_data[reg_offset >> 2] = 0;
11848 ptr_data[reg_offset >> 2] =
11849 I40E_READ_REG(hw, reg_offset);
11856 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11858 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11860 /* Convert word count to byte count */
11861 return hw->nvm.sr_size << 1;
11864 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11865 struct rte_dev_eeprom_info *eeprom)
11867 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11868 uint16_t *data = eeprom->data;
11869 uint16_t offset, length, cnt_words;
11872 offset = eeprom->offset >> 1;
11873 length = eeprom->length >> 1;
11874 cnt_words = length;
11876 if (offset > hw->nvm.sr_size ||
11877 offset + length > hw->nvm.sr_size) {
11878 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11882 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11884 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11885 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11886 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11893 static int i40e_get_module_info(struct rte_eth_dev *dev,
11894 struct rte_eth_dev_module_info *modinfo)
11896 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11897 uint32_t sff8472_comp = 0;
11898 uint32_t sff8472_swap = 0;
11899 uint32_t sff8636_rev = 0;
11900 i40e_status status;
11903 /* Check if firmware supports reading module EEPROM. */
11904 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11906 "Module EEPROM memory read not supported. "
11907 "Please update the NVM image.\n");
11911 status = i40e_update_link_info(hw);
11915 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11917 "Cannot read module EEPROM memory. "
11918 "No module connected.\n");
11922 type = hw->phy.link_info.module_type[0];
11925 case I40E_MODULE_TYPE_SFP:
11926 status = i40e_aq_get_phy_register(hw,
11927 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11928 I40E_I2C_EEPROM_DEV_ADDR, 1,
11929 I40E_MODULE_SFF_8472_COMP,
11930 &sff8472_comp, NULL);
11934 status = i40e_aq_get_phy_register(hw,
11935 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11936 I40E_I2C_EEPROM_DEV_ADDR, 1,
11937 I40E_MODULE_SFF_8472_SWAP,
11938 &sff8472_swap, NULL);
11942 /* Check if the module requires address swap to access
11943 * the other EEPROM memory page.
11945 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11946 PMD_DRV_LOG(WARNING,
11947 "Module address swap to access "
11948 "page 0xA2 is not supported.\n");
11949 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11950 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11951 } else if (sff8472_comp == 0x00) {
11952 /* Module is not SFF-8472 compliant */
11953 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11954 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11956 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11957 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11960 case I40E_MODULE_TYPE_QSFP_PLUS:
11961 /* Read from memory page 0. */
11962 status = i40e_aq_get_phy_register(hw,
11963 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11965 I40E_MODULE_REVISION_ADDR,
11966 &sff8636_rev, NULL);
11969 /* Determine revision compliance byte */
11970 if (sff8636_rev > 0x02) {
11971 /* Module is SFF-8636 compliant */
11972 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11973 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11975 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11976 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11979 case I40E_MODULE_TYPE_QSFP28:
11980 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11981 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11984 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11990 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11991 struct rte_dev_eeprom_info *info)
11993 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11994 bool is_sfp = false;
11995 i40e_status status;
11997 uint32_t value = 0;
12000 if (!info || !info->length || !info->data)
12003 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12007 for (i = 0; i < info->length; i++) {
12008 u32 offset = i + info->offset;
12009 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12011 /* Check if we need to access the other memory page */
12013 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12014 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12015 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12018 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12019 /* Compute memory page number and offset. */
12020 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12024 status = i40e_aq_get_phy_register(hw,
12025 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12026 addr, offset, 1, &value, NULL);
12029 data[i] = (uint8_t)value;
12034 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12035 struct rte_ether_addr *mac_addr)
12037 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12038 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12039 struct i40e_vsi *vsi = pf->main_vsi;
12040 struct i40e_mac_filter_info mac_filter;
12041 struct i40e_mac_filter *f;
12044 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12045 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12049 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12050 if (rte_is_same_ether_addr(&pf->dev_addr,
12051 &f->mac_info.mac_addr))
12056 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12060 mac_filter = f->mac_info;
12061 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12062 if (ret != I40E_SUCCESS) {
12063 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12066 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12067 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12068 if (ret != I40E_SUCCESS) {
12069 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12072 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12074 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12075 mac_addr->addr_bytes, NULL);
12076 if (ret != I40E_SUCCESS) {
12077 PMD_DRV_LOG(ERR, "Failed to change mac");
12085 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12087 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12088 struct rte_eth_dev_data *dev_data = pf->dev_data;
12089 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12092 /* check if mtu is within the allowed range */
12093 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12096 /* mtu setting is forbidden if port is start */
12097 if (dev_data->dev_started) {
12098 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12099 dev_data->port_id);
12103 if (frame_size > RTE_ETHER_MAX_LEN)
12104 dev_data->dev_conf.rxmode.offloads |=
12105 DEV_RX_OFFLOAD_JUMBO_FRAME;
12107 dev_data->dev_conf.rxmode.offloads &=
12108 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12110 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12115 /* Restore ethertype filter */
12117 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12119 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12120 struct i40e_ethertype_filter_list
12121 *ethertype_list = &pf->ethertype.ethertype_list;
12122 struct i40e_ethertype_filter *f;
12123 struct i40e_control_filter_stats stats;
12126 TAILQ_FOREACH(f, ethertype_list, rules) {
12128 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12129 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12130 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12131 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12132 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12134 memset(&stats, 0, sizeof(stats));
12135 i40e_aq_add_rem_control_packet_filter(hw,
12136 f->input.mac_addr.addr_bytes,
12137 f->input.ether_type,
12138 flags, pf->main_vsi->seid,
12139 f->queue, 1, &stats, NULL);
12141 PMD_DRV_LOG(INFO, "Ethertype filter:"
12142 " mac_etype_used = %u, etype_used = %u,"
12143 " mac_etype_free = %u, etype_free = %u",
12144 stats.mac_etype_used, stats.etype_used,
12145 stats.mac_etype_free, stats.etype_free);
12148 /* Restore tunnel filter */
12150 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12152 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12153 struct i40e_vsi *vsi;
12154 struct i40e_pf_vf *vf;
12155 struct i40e_tunnel_filter_list
12156 *tunnel_list = &pf->tunnel.tunnel_list;
12157 struct i40e_tunnel_filter *f;
12158 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12159 bool big_buffer = 0;
12161 TAILQ_FOREACH(f, tunnel_list, rules) {
12163 vsi = pf->main_vsi;
12165 vf = &pf->vfs[f->vf_id];
12168 memset(&cld_filter, 0, sizeof(cld_filter));
12169 rte_ether_addr_copy((struct rte_ether_addr *)
12170 &f->input.outer_mac,
12171 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12172 rte_ether_addr_copy((struct rte_ether_addr *)
12173 &f->input.inner_mac,
12174 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12175 cld_filter.element.inner_vlan = f->input.inner_vlan;
12176 cld_filter.element.flags = f->input.flags;
12177 cld_filter.element.tenant_id = f->input.tenant_id;
12178 cld_filter.element.queue_number = f->queue;
12179 rte_memcpy(cld_filter.general_fields,
12180 f->input.general_fields,
12181 sizeof(f->input.general_fields));
12183 if (((f->input.flags &
12184 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12185 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12187 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12188 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12190 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12191 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12195 i40e_aq_add_cloud_filters_bb(hw,
12196 vsi->seid, &cld_filter, 1);
12198 i40e_aq_add_cloud_filters(hw, vsi->seid,
12199 &cld_filter.element, 1);
12203 /* Restore rss filter */
12205 i40e_rss_filter_restore(struct i40e_pf *pf)
12207 struct i40e_rte_flow_rss_conf *conf =
12209 if (conf->conf.queue_num)
12210 i40e_config_rss_filter(pf, conf, TRUE);
12214 i40e_filter_restore(struct i40e_pf *pf)
12216 i40e_ethertype_filter_restore(pf);
12217 i40e_tunnel_filter_restore(pf);
12218 i40e_fdir_filter_restore(pf);
12219 i40e_rss_filter_restore(pf);
12223 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12225 if (strcmp(dev->device->driver->name, drv->driver.name))
12232 is_i40e_supported(struct rte_eth_dev *dev)
12234 return is_device_supported(dev, &rte_i40e_pmd);
12237 struct i40e_customized_pctype*
12238 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12242 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12243 if (pf->customized_pctype[i].index == index)
12244 return &pf->customized_pctype[i];
12250 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12251 uint32_t pkg_size, uint32_t proto_num,
12252 struct rte_pmd_i40e_proto_info *proto,
12253 enum rte_pmd_i40e_package_op op)
12255 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12256 uint32_t pctype_num;
12257 struct rte_pmd_i40e_ptype_info *pctype;
12258 uint32_t buff_size;
12259 struct i40e_customized_pctype *new_pctype = NULL;
12261 uint8_t pctype_value;
12266 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12267 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12268 PMD_DRV_LOG(ERR, "Unsupported operation.");
12272 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12273 (uint8_t *)&pctype_num, sizeof(pctype_num),
12274 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12276 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12280 PMD_DRV_LOG(INFO, "No new pctype added");
12284 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12285 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12287 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12290 /* get information about new pctype list */
12291 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12292 (uint8_t *)pctype, buff_size,
12293 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12295 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12300 /* Update customized pctype. */
12301 for (i = 0; i < pctype_num; i++) {
12302 pctype_value = pctype[i].ptype_id;
12303 memset(name, 0, sizeof(name));
12304 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12305 proto_id = pctype[i].protocols[j];
12306 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12308 for (n = 0; n < proto_num; n++) {
12309 if (proto[n].proto_id != proto_id)
12311 strlcat(name, proto[n].name, sizeof(name));
12312 strlcat(name, "_", sizeof(name));
12316 name[strlen(name) - 1] = '\0';
12317 if (!strcmp(name, "GTPC"))
12319 i40e_find_customized_pctype(pf,
12320 I40E_CUSTOMIZED_GTPC);
12321 else if (!strcmp(name, "GTPU_IPV4"))
12323 i40e_find_customized_pctype(pf,
12324 I40E_CUSTOMIZED_GTPU_IPV4);
12325 else if (!strcmp(name, "GTPU_IPV6"))
12327 i40e_find_customized_pctype(pf,
12328 I40E_CUSTOMIZED_GTPU_IPV6);
12329 else if (!strcmp(name, "GTPU"))
12331 i40e_find_customized_pctype(pf,
12332 I40E_CUSTOMIZED_GTPU);
12334 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12335 new_pctype->pctype = pctype_value;
12336 new_pctype->valid = true;
12338 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12339 new_pctype->valid = false;
12349 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12350 uint32_t pkg_size, uint32_t proto_num,
12351 struct rte_pmd_i40e_proto_info *proto,
12352 enum rte_pmd_i40e_package_op op)
12354 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12355 uint16_t port_id = dev->data->port_id;
12356 uint32_t ptype_num;
12357 struct rte_pmd_i40e_ptype_info *ptype;
12358 uint32_t buff_size;
12360 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12365 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12366 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12367 PMD_DRV_LOG(ERR, "Unsupported operation.");
12371 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12372 rte_pmd_i40e_ptype_mapping_reset(port_id);
12376 /* get information about new ptype num */
12377 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12378 (uint8_t *)&ptype_num, sizeof(ptype_num),
12379 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12381 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12385 PMD_DRV_LOG(INFO, "No new ptype added");
12389 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12390 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12392 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12396 /* get information about new ptype list */
12397 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12398 (uint8_t *)ptype, buff_size,
12399 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12401 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12406 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12407 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12408 if (!ptype_mapping) {
12409 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12414 /* Update ptype mapping table. */
12415 for (i = 0; i < ptype_num; i++) {
12416 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12417 ptype_mapping[i].sw_ptype = 0;
12419 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12420 proto_id = ptype[i].protocols[j];
12421 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12423 for (n = 0; n < proto_num; n++) {
12424 if (proto[n].proto_id != proto_id)
12426 memset(name, 0, sizeof(name));
12427 strcpy(name, proto[n].name);
12428 if (!strncasecmp(name, "PPPOE", 5))
12429 ptype_mapping[i].sw_ptype |=
12430 RTE_PTYPE_L2_ETHER_PPPOE;
12431 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12433 ptype_mapping[i].sw_ptype |=
12434 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12435 ptype_mapping[i].sw_ptype |=
12437 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12439 ptype_mapping[i].sw_ptype |=
12440 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12441 ptype_mapping[i].sw_ptype |=
12442 RTE_PTYPE_INNER_L4_FRAG;
12443 } else if (!strncasecmp(name, "OIPV4", 5)) {
12444 ptype_mapping[i].sw_ptype |=
12445 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12447 } else if (!strncasecmp(name, "IPV4", 4) &&
12449 ptype_mapping[i].sw_ptype |=
12450 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12451 else if (!strncasecmp(name, "IPV4", 4) &&
12453 ptype_mapping[i].sw_ptype |=
12454 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12455 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12457 ptype_mapping[i].sw_ptype |=
12458 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12459 ptype_mapping[i].sw_ptype |=
12461 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12463 ptype_mapping[i].sw_ptype |=
12464 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12465 ptype_mapping[i].sw_ptype |=
12466 RTE_PTYPE_INNER_L4_FRAG;
12467 } else if (!strncasecmp(name, "OIPV6", 5)) {
12468 ptype_mapping[i].sw_ptype |=
12469 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12471 } else if (!strncasecmp(name, "IPV6", 4) &&
12473 ptype_mapping[i].sw_ptype |=
12474 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12475 else if (!strncasecmp(name, "IPV6", 4) &&
12477 ptype_mapping[i].sw_ptype |=
12478 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12479 else if (!strncasecmp(name, "UDP", 3) &&
12481 ptype_mapping[i].sw_ptype |=
12483 else if (!strncasecmp(name, "UDP", 3) &&
12485 ptype_mapping[i].sw_ptype |=
12486 RTE_PTYPE_INNER_L4_UDP;
12487 else if (!strncasecmp(name, "TCP", 3) &&
12489 ptype_mapping[i].sw_ptype |=
12491 else if (!strncasecmp(name, "TCP", 3) &&
12493 ptype_mapping[i].sw_ptype |=
12494 RTE_PTYPE_INNER_L4_TCP;
12495 else if (!strncasecmp(name, "SCTP", 4) &&
12497 ptype_mapping[i].sw_ptype |=
12499 else if (!strncasecmp(name, "SCTP", 4) &&
12501 ptype_mapping[i].sw_ptype |=
12502 RTE_PTYPE_INNER_L4_SCTP;
12503 else if ((!strncasecmp(name, "ICMP", 4) ||
12504 !strncasecmp(name, "ICMPV6", 6)) &&
12506 ptype_mapping[i].sw_ptype |=
12508 else if ((!strncasecmp(name, "ICMP", 4) ||
12509 !strncasecmp(name, "ICMPV6", 6)) &&
12511 ptype_mapping[i].sw_ptype |=
12512 RTE_PTYPE_INNER_L4_ICMP;
12513 else if (!strncasecmp(name, "GTPC", 4)) {
12514 ptype_mapping[i].sw_ptype |=
12515 RTE_PTYPE_TUNNEL_GTPC;
12517 } else if (!strncasecmp(name, "GTPU", 4)) {
12518 ptype_mapping[i].sw_ptype |=
12519 RTE_PTYPE_TUNNEL_GTPU;
12521 } else if (!strncasecmp(name, "GRENAT", 6)) {
12522 ptype_mapping[i].sw_ptype |=
12523 RTE_PTYPE_TUNNEL_GRENAT;
12525 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12526 !strncasecmp(name, "L2TPV2", 6)) {
12527 ptype_mapping[i].sw_ptype |=
12528 RTE_PTYPE_TUNNEL_L2TP;
12537 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12540 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12542 rte_free(ptype_mapping);
12548 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12549 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12551 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12552 uint32_t proto_num;
12553 struct rte_pmd_i40e_proto_info *proto;
12554 uint32_t buff_size;
12558 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12559 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12560 PMD_DRV_LOG(ERR, "Unsupported operation.");
12564 /* get information about protocol number */
12565 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12566 (uint8_t *)&proto_num, sizeof(proto_num),
12567 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12569 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12573 PMD_DRV_LOG(INFO, "No new protocol added");
12577 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12578 proto = rte_zmalloc("new_proto", buff_size, 0);
12580 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12584 /* get information about protocol list */
12585 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12586 (uint8_t *)proto, buff_size,
12587 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12589 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12594 /* Check if GTP is supported. */
12595 for (i = 0; i < proto_num; i++) {
12596 if (!strncmp(proto[i].name, "GTP", 3)) {
12597 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12598 pf->gtp_support = true;
12600 pf->gtp_support = false;
12605 /* Update customized pctype info */
12606 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12607 proto_num, proto, op);
12609 PMD_DRV_LOG(INFO, "No pctype is updated.");
12611 /* Update customized ptype info */
12612 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12613 proto_num, proto, op);
12615 PMD_DRV_LOG(INFO, "No ptype is updated.");
12620 /* Create a QinQ cloud filter
12622 * The Fortville NIC has limited resources for tunnel filters,
12623 * so we can only reuse existing filters.
12625 * In step 1 we define which Field Vector fields can be used for
12627 * As we do not have the inner tag defined as a field,
12628 * we have to define it first, by reusing one of L1 entries.
12630 * In step 2 we are replacing one of existing filter types with
12631 * a new one for QinQ.
12632 * As we reusing L1 and replacing L2, some of the default filter
12633 * types will disappear,which depends on L1 and L2 entries we reuse.
12635 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12637 * 1. Create L1 filter of outer vlan (12b) which will be in use
12638 * later when we define the cloud filter.
12639 * a. Valid_flags.replace_cloud = 0
12640 * b. Old_filter = 10 (Stag_Inner_Vlan)
12641 * c. New_filter = 0x10
12642 * d. TR bit = 0xff (optional, not used here)
12643 * e. Buffer – 2 entries:
12644 * i. Byte 0 = 8 (outer vlan FV index).
12646 * Byte 2-3 = 0x0fff
12647 * ii. Byte 0 = 37 (inner vlan FV index).
12649 * Byte 2-3 = 0x0fff
12652 * 2. Create cloud filter using two L1 filters entries: stag and
12653 * new filter(outer vlan+ inner vlan)
12654 * a. Valid_flags.replace_cloud = 1
12655 * b. Old_filter = 1 (instead of outer IP)
12656 * c. New_filter = 0x10
12657 * d. Buffer – 2 entries:
12658 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12659 * Byte 1-3 = 0 (rsv)
12660 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12661 * Byte 9-11 = 0 (rsv)
12664 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12666 int ret = -ENOTSUP;
12667 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12668 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12669 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12670 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12672 if (pf->support_multi_driver) {
12673 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12678 memset(&filter_replace, 0,
12679 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12680 memset(&filter_replace_buf, 0,
12681 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12683 /* create L1 filter */
12684 filter_replace.old_filter_type =
12685 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12686 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12687 filter_replace.tr_bit = 0;
12689 /* Prepare the buffer, 2 entries */
12690 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12691 filter_replace_buf.data[0] |=
12692 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12693 /* Field Vector 12b mask */
12694 filter_replace_buf.data[2] = 0xff;
12695 filter_replace_buf.data[3] = 0x0f;
12696 filter_replace_buf.data[4] =
12697 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12698 filter_replace_buf.data[4] |=
12699 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12700 /* Field Vector 12b mask */
12701 filter_replace_buf.data[6] = 0xff;
12702 filter_replace_buf.data[7] = 0x0f;
12703 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12704 &filter_replace_buf);
12705 if (ret != I40E_SUCCESS)
12708 if (filter_replace.old_filter_type !=
12709 filter_replace.new_filter_type)
12710 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12711 " original: 0x%x, new: 0x%x",
12713 filter_replace.old_filter_type,
12714 filter_replace.new_filter_type);
12716 /* Apply the second L2 cloud filter */
12717 memset(&filter_replace, 0,
12718 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12719 memset(&filter_replace_buf, 0,
12720 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12722 /* create L2 filter, input for L2 filter will be L1 filter */
12723 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12724 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12725 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12727 /* Prepare the buffer, 2 entries */
12728 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12729 filter_replace_buf.data[0] |=
12730 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12731 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12732 filter_replace_buf.data[4] |=
12733 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12734 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12735 &filter_replace_buf);
12736 if (!ret && (filter_replace.old_filter_type !=
12737 filter_replace.new_filter_type))
12738 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12739 " original: 0x%x, new: 0x%x",
12741 filter_replace.old_filter_type,
12742 filter_replace.new_filter_type);
12748 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12749 const struct rte_flow_action_rss *in)
12751 if (in->key_len > RTE_DIM(out->key) ||
12752 in->queue_num > RTE_DIM(out->queue))
12754 if (!in->key && in->key_len)
12756 out->conf = (struct rte_flow_action_rss){
12758 .level = in->level,
12759 .types = in->types,
12760 .key_len = in->key_len,
12761 .queue_num = in->queue_num,
12762 .queue = memcpy(out->queue, in->queue,
12763 sizeof(*in->queue) * in->queue_num),
12766 out->conf.key = memcpy(out->key, in->key, in->key_len);
12771 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12772 const struct rte_flow_action_rss *with)
12774 return (comp->func == with->func &&
12775 comp->level == with->level &&
12776 comp->types == with->types &&
12777 comp->key_len == with->key_len &&
12778 comp->queue_num == with->queue_num &&
12779 !memcmp(comp->key, with->key, with->key_len) &&
12780 !memcmp(comp->queue, with->queue,
12781 sizeof(*with->queue) * with->queue_num));
12785 i40e_config_rss_filter(struct i40e_pf *pf,
12786 struct i40e_rte_flow_rss_conf *conf, bool add)
12788 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12789 uint32_t i, lut = 0;
12791 struct rte_eth_rss_conf rss_conf = {
12792 .rss_key = conf->conf.key_len ?
12793 (void *)(uintptr_t)conf->conf.key : NULL,
12794 .rss_key_len = conf->conf.key_len,
12795 .rss_hf = conf->conf.types,
12797 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12800 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12801 i40e_pf_disable_rss(pf);
12802 memset(rss_info, 0,
12803 sizeof(struct i40e_rte_flow_rss_conf));
12809 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12810 * It's necessary to calculate the actual PF queues that are configured.
12812 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12813 num = i40e_pf_calc_configured_queues_num(pf);
12815 num = pf->dev_data->nb_rx_queues;
12817 num = RTE_MIN(num, conf->conf.queue_num);
12818 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12822 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12826 /* Fill in redirection table */
12827 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12830 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12831 hw->func_caps.rss_table_entry_width) - 1));
12833 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12836 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12837 i40e_pf_disable_rss(pf);
12840 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12841 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12842 /* Random default keys */
12843 static uint32_t rss_key_default[] = {0x6b793944,
12844 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12845 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12846 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12848 rss_conf.rss_key = (uint8_t *)rss_key_default;
12849 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12852 "No valid RSS key config for i40e, using default\n");
12855 i40e_hw_rss_hash_set(pf, &rss_conf);
12857 if (i40e_rss_conf_init(rss_info, &conf->conf))
12863 RTE_INIT(i40e_init_log)
12865 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12866 if (i40e_logtype_init >= 0)
12867 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12868 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12869 if (i40e_logtype_driver >= 0)
12870 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12873 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12874 ETH_I40E_FLOATING_VEB_ARG "=1"
12875 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12876 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12877 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12878 ETH_I40E_USE_LATEST_VEC "=0|1");