drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "base/i40e_diag.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45
  46 #define I40E_CLEAR_PXE_WAIT_MS     200
  47
  48 /* Maximun number of capability elements */
  49 #define I40E_MAX_CAP_ELE_NUM       128
  50
  51 /* Wait count and interval */
  52 #define I40E_CHK_Q_ENA_COUNT       1000
  53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  54
  55 /* Maximun number of VSI */
  56 #define I40E_MAX_NUM_VSIS          (384UL)
  57
  58 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  59
  60 /* Flow control default timer */
  61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  62
  63 /* Flow control enable fwd bit */
  64 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  65
  66 /* Receive Packet Buffer size */
  67 #define I40E_RXPBSIZE (968 * 1024)
  68
  69 /* Kilobytes shift */
  70 #define I40E_KILOSHIFT 10
  71
  72 /* Flow control default high water */
  73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  74
  75 /* Flow control default low water */
  76 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Receive Average Packet Size in Byte*/
  79 #define I40E_PACKET_AVERAGE_SIZE 128
  80
  81 /* Mask of PF interrupt causes */
  82 #define I40E_PFINT_ICR0_ENA_MASK ( \
  83                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  84                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  85                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  86                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  87                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  92
  93 #define I40E_FLOW_TYPES ( \
  94         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  99         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 104         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 105
 106 /* Additional timesync values. */
 107 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 108 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 109 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 110 #define I40E_PRTTSYN_TSYNENA     0x80000000
 111 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 112 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 /**
 115  * Below are values for writing un-exposed registers suggested
 116  * by silicon experts
 117  */
 118 /* Destination MAC address */
 119 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 120 /* Source MAC address */
 121 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 123 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 126 /* Single VLAN tag in the inner L2 header */
 127 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 128 /* Source IPv4 address */
 129 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 130 /* Destination IPv4 address */
 131 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 132 /* Source IPv4 address for X722 */
 133 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 134 /* Destination IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 136 /* IPv4 Protocol for X722 */
 137 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 138 /* IPv4 Time to Live for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 140 /* IPv4 Type of Service (TOS) */
 141 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 142 /* IPv4 Protocol */
 143 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 144 /* IPv4 Time to Live */
 145 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 146 /* Source IPv6 address */
 147 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 148 /* Destination IPv6 address */
 149 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 150 /* IPv6 Traffic Class (TC) */
 151 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 152 /* IPv6 Next Header */
 153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 154 /* IPv6 Hop Limit */
 155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 156 /* Source L4 port */
 157 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 158 /* Destination L4 port */
 159 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 160 /* SCTP verification tag */
 161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 164 /* Source port of tunneling UDP */
 165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 166 /* Destination port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 168 /* UDP Tunneling ID, NVGRE/GRE key */
 169 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 170 /* Last ether type */
 171 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 172 /* Tunneling outer destination IPv4 address */
 173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 174 /* Tunneling outer destination IPv6 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 176 /* 1st word of flex payload */
 177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 178 /* 2nd word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 180 /* 3rd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 182 /* 4th word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 184 /* 5th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 186 /* 6th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 188 /* 7th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 190 /* 8th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 192 /* all 8 words flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 194 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 195
 196 #define I40E_TRANSLATE_INSET 0
 197 #define I40E_TRANSLATE_REG   1
 198
 199 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 200 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 201 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 202 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 204 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 205
 206 /* PCI offset for querying capability */
 207 #define PCI_DEV_CAP_REG            0xA4
 208 /* PCI offset for enabling/disabling Extended Tag */
 209 #define PCI_DEV_CTRL_REG           0xA8
 210 /* Bit mask of Extended Tag capability */
 211 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 212 /* Bit shift of Extended Tag enable/disable */
 213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 214 /* Bit mask of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 216
 217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 219 static int i40e_dev_configure(struct rte_eth_dev *dev);
 220 static int i40e_dev_start(struct rte_eth_dev *dev);
 221 static void i40e_dev_stop(struct rte_eth_dev *dev);
 222 static void i40e_dev_close(struct rte_eth_dev *dev);
 223 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_stats *stats);
 232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_xstat *xstats, unsigned n);
 234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 235                                      struct rte_eth_xstat_name *xstats_names,
 236                                      unsigned limit);
 237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 239                                             uint16_t queue_id,
 240                                             uint8_t stat_idx,
 241                                             uint8_t is_rx);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 245                               struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 374                                       struct ether_addr *mac_addr);
 375
 376 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 377
 378 static int i40e_ethertype_filter_convert(
 379         const struct rte_eth_ethertype_filter *input,
 380         struct i40e_ethertype_filter *filter);
 381 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 382                                    struct i40e_ethertype_filter *filter);
 383
 384 static int i40e_tunnel_filter_convert(
 385         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 386         struct i40e_tunnel_filter *tunnel_filter);
 387 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 388                                 struct i40e_tunnel_filter *tunnel_filter);
 389 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 390
 391 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 392 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 393 static void i40e_filter_restore(struct i40e_pf *pf);
 394 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 395
 396 int i40e_logtype_init;
 397 int i40e_logtype_driver;
 398
 399 static const struct rte_pci_id pci_id_i40e_map[] = {
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 420         { .vendor_id = 0, /* sentinel */ },
 421 };
 422
 423 static const struct eth_dev_ops i40e_eth_dev_ops = {
 424         .dev_configure                = i40e_dev_configure,
 425         .dev_start                    = i40e_dev_start,
 426         .dev_stop                     = i40e_dev_stop,
 427         .dev_close                    = i40e_dev_close,
 428         .dev_reset                    = i40e_dev_reset,
 429         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 430         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 431         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 432         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 433         .dev_set_link_up              = i40e_dev_set_link_up,
 434         .dev_set_link_down            = i40e_dev_set_link_down,
 435         .link_update                  = i40e_dev_link_update,
 436         .stats_get                    = i40e_dev_stats_get,
 437         .xstats_get                   = i40e_dev_xstats_get,
 438         .xstats_get_names             = i40e_dev_xstats_get_names,
 439         .stats_reset                  = i40e_dev_stats_reset,
 440         .xstats_reset                 = i40e_dev_stats_reset,
 441         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 442         .fw_version_get               = i40e_fw_version_get,
 443         .dev_infos_get                = i40e_dev_info_get,
 444         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 445         .vlan_filter_set              = i40e_vlan_filter_set,
 446         .vlan_tpid_set                = i40e_vlan_tpid_set,
 447         .vlan_offload_set             = i40e_vlan_offload_set,
 448         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 449         .vlan_pvid_set                = i40e_vlan_pvid_set,
 450         .rx_queue_start               = i40e_dev_rx_queue_start,
 451         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 452         .tx_queue_start               = i40e_dev_tx_queue_start,
 453         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 454         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 455         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 456         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 457         .rx_queue_release             = i40e_dev_rx_queue_release,
 458         .rx_queue_count               = i40e_dev_rx_queue_count,
 459         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 460         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 461         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 462         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 463         .tx_queue_release             = i40e_dev_tx_queue_release,
 464         .dev_led_on                   = i40e_dev_led_on,
 465         .dev_led_off                  = i40e_dev_led_off,
 466         .flow_ctrl_get                = i40e_flow_ctrl_get,
 467         .flow_ctrl_set                = i40e_flow_ctrl_set,
 468         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 469         .mac_addr_add                 = i40e_macaddr_add,
 470         .mac_addr_remove              = i40e_macaddr_remove,
 471         .reta_update                  = i40e_dev_rss_reta_update,
 472         .reta_query                   = i40e_dev_rss_reta_query,
 473         .rss_hash_update              = i40e_dev_rss_hash_update,
 474         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 475         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 476         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 477         .filter_ctrl                  = i40e_dev_filter_ctrl,
 478         .rxq_info_get                 = i40e_rxq_info_get,
 479         .txq_info_get                 = i40e_txq_info_get,
 480         .mirror_rule_set              = i40e_mirror_rule_set,
 481         .mirror_rule_reset            = i40e_mirror_rule_reset,
 482         .timesync_enable              = i40e_timesync_enable,
 483         .timesync_disable             = i40e_timesync_disable,
 484         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 485         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 486         .get_dcb_info                 = i40e_dev_get_dcb_info,
 487         .timesync_adjust_time         = i40e_timesync_adjust_time,
 488         .timesync_read_time           = i40e_timesync_read_time,
 489         .timesync_write_time          = i40e_timesync_write_time,
 490         .get_reg                      = i40e_get_regs,
 491         .get_eeprom_length            = i40e_get_eeprom_length,
 492         .get_eeprom                   = i40e_get_eeprom,
 493         .mac_addr_set                 = i40e_set_default_mac_addr,
 494         .mtu_set                      = i40e_dev_mtu_set,
 495         .tm_ops_get                   = i40e_tm_ops_get,
 496 };
 497
 498 /* store statistics names and its offset in stats structure */
 499 struct rte_i40e_xstats_name_off {
 500         char name[RTE_ETH_XSTATS_NAME_SIZE];
 501         unsigned offset;
 502 };
 503
 504 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 505         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 506         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 507         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 508         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 509         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 510                 rx_unknown_protocol)},
 511         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 512         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 513         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 514         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 515 };
 516
 517 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 518                 sizeof(rte_i40e_stats_strings[0]))
 519
 520 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 521         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 522                 tx_dropped_link_down)},
 523         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 524         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 525                 illegal_bytes)},
 526         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 527         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 528                 mac_local_faults)},
 529         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 530                 mac_remote_faults)},
 531         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 532                 rx_length_errors)},
 533         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 534         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 535         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 536         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 537         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 538         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 539                 rx_size_127)},
 540         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 541                 rx_size_255)},
 542         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 543                 rx_size_511)},
 544         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 545                 rx_size_1023)},
 546         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 547                 rx_size_1522)},
 548         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 549                 rx_size_big)},
 550         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_undersize)},
 552         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_oversize)},
 554         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 555                 mac_short_packet_dropped)},
 556         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_fragments)},
 558         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 559         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 560         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 tx_size_127)},
 562         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 tx_size_255)},
 564         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 tx_size_511)},
 566         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 tx_size_1023)},
 568         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 tx_size_1522)},
 570         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 tx_size_big)},
 572         {"rx_flow_director_atr_match_packets",
 573                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 574         {"rx_flow_director_sb_match_packets",
 575                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 576         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 577                 tx_lpi_status)},
 578         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 579                 rx_lpi_status)},
 580         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 581                 tx_lpi_count)},
 582         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 583                 rx_lpi_count)},
 584 };
 585
 586 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 587                 sizeof(rte_i40e_hw_port_strings[0]))
 588
 589 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 590         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 591                 priority_xon_rx)},
 592         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 593                 priority_xoff_rx)},
 594 };
 595
 596 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 597                 sizeof(rte_i40e_rxq_prio_strings[0]))
 598
 599 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 600         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 601                 priority_xon_tx)},
 602         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 603                 priority_xoff_tx)},
 604         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 605                 priority_xon_2_xoff)},
 606 };
 607
 608 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 609                 sizeof(rte_i40e_txq_prio_strings[0]))
 610
 611 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 612         struct rte_pci_device *pci_dev)
 613 {
 614         return rte_eth_dev_pci_generic_probe(pci_dev,
 615                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 616 }
 617
 618 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 619 {
 620         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 621 }
 622
 623 static struct rte_pci_driver rte_i40e_pmd = {
 624         .id_table = pci_id_i40e_map,
 625         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 626                      RTE_PCI_DRV_IOVA_AS_VA,
 627         .probe = eth_i40e_pci_probe,
 628         .remove = eth_i40e_pci_remove,
 629 };
 630
 631 static inline int
 632 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 633                                      struct rte_eth_link *link)
 634 {
 635         struct rte_eth_link *dst = link;
 636         struct rte_eth_link *src = &(dev->data->dev_link);
 637
 638         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 639                                         *(uint64_t *)src) == 0)
 640                 return -1;
 641
 642         return 0;
 643 }
 644
 645 static inline int
 646 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 647                                       struct rte_eth_link *link)
 648 {
 649         struct rte_eth_link *dst = &(dev->data->dev_link);
 650         struct rte_eth_link *src = link;
 651
 652         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 653                                         *(uint64_t *)src) == 0)
 654                 return -1;
 655
 656         return 0;
 657 }
 658
 659 static inline void
 660 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 661 {
 662         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 663         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 664                     "with value 0x%08x",
 665                     reg_addr, reg_val);
 666 }
 667
 668 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 669 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 670 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 671
 672 #ifndef I40E_GLQF_ORT
 673 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 674 #endif
 675 #ifndef I40E_GLQF_PIT
 676 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 677 #endif
 678 #ifndef I40E_GLQF_L3_MAP
 679 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 680 #endif
 681
 682 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 683 {
 684         /*
 685          * Initialize registers for parsing packet type of QinQ
 686          * This should be removed from code once proper
 687          * configuration API is added to avoid configuration conflicts
 688          * between ports of the same device.
 689          */
 690         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 691         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 692         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 693 }
 694
 695 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 696
 697 /*
 698  * Add a ethertype filter to drop all flow control frames transmitted
 699  * from VSIs.
 700 */
 701 static void
 702 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 703 {
 704         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 705         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 706                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 707                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 708         int ret;
 709
 710         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 711                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 712                                 pf->main_vsi_seid, 0,
 713                                 TRUE, NULL, NULL);
 714         if (ret)
 715                 PMD_INIT_LOG(ERR,
 716                         "Failed to add filter to drop flow control frames from VSIs.");
 717 }
 718
 719 static int
 720 floating_veb_list_handler(__rte_unused const char *key,
 721                           const char *floating_veb_value,
 722                           void *opaque)
 723 {
 724         int idx = 0;
 725         unsigned int count = 0;
 726         char *end = NULL;
 727         int min, max;
 728         bool *vf_floating_veb = opaque;
 729
 730         while (isblank(*floating_veb_value))
 731                 floating_veb_value++;
 732
 733         /* Reset floating VEB configuration for VFs */
 734         for (idx = 0; idx < I40E_MAX_VF; idx++)
 735                 vf_floating_veb[idx] = false;
 736
 737         min = I40E_MAX_VF;
 738         do {
 739                 while (isblank(*floating_veb_value))
 740                         floating_veb_value++;
 741                 if (*floating_veb_value == '\0')
 742                         return -1;
 743                 errno = 0;
 744                 idx = strtoul(floating_veb_value, &end, 10);
 745                 if (errno || end == NULL)
 746                         return -1;
 747                 while (isblank(*end))
 748                         end++;
 749                 if (*end == '-') {
 750                         min = idx;
 751                 } else if ((*end == ';') || (*end == '\0')) {
 752                         max = idx;
 753                         if (min == I40E_MAX_VF)
 754                                 min = idx;
 755                         if (max >= I40E_MAX_VF)
 756                                 max = I40E_MAX_VF - 1;
 757                         for (idx = min; idx <= max; idx++) {
 758                                 vf_floating_veb[idx] = true;
 759                                 count++;
 760                         }
 761                         min = I40E_MAX_VF;
 762                 } else {
 763                         return -1;
 764                 }
 765                 floating_veb_value = end + 1;
 766         } while (*end != '\0');
 767
 768         if (count == 0)
 769                 return -1;
 770
 771         return 0;
 772 }
 773
 774 static void
 775 config_vf_floating_veb(struct rte_devargs *devargs,
 776                        uint16_t floating_veb,
 777                        bool *vf_floating_veb)
 778 {
 779         struct rte_kvargs *kvlist;
 780         int i;
 781         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 782
 783         if (!floating_veb)
 784                 return;
 785         /* All the VFs attach to the floating VEB by default
 786          * when the floating VEB is enabled.
 787          */
 788         for (i = 0; i < I40E_MAX_VF; i++)
 789                 vf_floating_veb[i] = true;
 790
 791         if (devargs == NULL)
 792                 return;
 793
 794         kvlist = rte_kvargs_parse(devargs->args, NULL);
 795         if (kvlist == NULL)
 796                 return;
 797
 798         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 799                 rte_kvargs_free(kvlist);
 800                 return;
 801         }
 802         /* When the floating_veb_list parameter exists, all the VFs
 803          * will attach to the legacy VEB firstly, then configure VFs
 804          * to the floating VEB according to the floating_veb_list.
 805          */
 806         if (rte_kvargs_process(kvlist, floating_veb_list,
 807                                floating_veb_list_handler,
 808                                vf_floating_veb) < 0) {
 809                 rte_kvargs_free(kvlist);
 810                 return;
 811         }
 812         rte_kvargs_free(kvlist);
 813 }
 814
 815 static int
 816 i40e_check_floating_handler(__rte_unused const char *key,
 817                             const char *value,
 818                             __rte_unused void *opaque)
 819 {
 820         if (strcmp(value, "1"))
 821                 return -1;
 822
 823         return 0;
 824 }
 825
 826 static int
 827 is_floating_veb_supported(struct rte_devargs *devargs)
 828 {
 829         struct rte_kvargs *kvlist;
 830         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 831
 832         if (devargs == NULL)
 833                 return 0;
 834
 835         kvlist = rte_kvargs_parse(devargs->args, NULL);
 836         if (kvlist == NULL)
 837                 return 0;
 838
 839         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 840                 rte_kvargs_free(kvlist);
 841                 return 0;
 842         }
 843         /* Floating VEB is enabled when there's key-value:
 844          * enable_floating_veb=1
 845          */
 846         if (rte_kvargs_process(kvlist, floating_veb_key,
 847                                i40e_check_floating_handler, NULL) < 0) {
 848                 rte_kvargs_free(kvlist);
 849                 return 0;
 850         }
 851         rte_kvargs_free(kvlist);
 852
 853         return 1;
 854 }
 855
 856 static void
 857 config_floating_veb(struct rte_eth_dev *dev)
 858 {
 859         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 862
 863         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 864
 865         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 866                 pf->floating_veb =
 867                         is_floating_veb_supported(pci_dev->device.devargs);
 868                 config_vf_floating_veb(pci_dev->device.devargs,
 869                                        pf->floating_veb,
 870                                        pf->floating_veb_list);
 871         } else {
 872                 pf->floating_veb = false;
 873         }
 874 }
 875
 876 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 877 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 878
 879 static int
 880 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 881 {
 882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 883         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 884         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 885         int ret;
 886
 887         struct rte_hash_parameters ethertype_hash_params = {
 888                 .name = ethertype_hash_name,
 889                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 890                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 891                 .hash_func = rte_hash_crc,
 892                 .hash_func_init_val = 0,
 893                 .socket_id = rte_socket_id(),
 894         };
 895
 896         /* Initialize ethertype filter rule list and hash */
 897         TAILQ_INIT(&ethertype_rule->ethertype_list);
 898         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 899                  "ethertype_%s", dev->device->name);
 900         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 901         if (!ethertype_rule->hash_table) {
 902                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 903                 return -EINVAL;
 904         }
 905         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 906                                        sizeof(struct i40e_ethertype_filter *) *
 907                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 908                                        0);
 909         if (!ethertype_rule->hash_map) {
 910                 PMD_INIT_LOG(ERR,
 911                              "Failed to allocate memory for ethertype hash map!");
 912                 ret = -ENOMEM;
 913                 goto err_ethertype_hash_map_alloc;
 914         }
 915
 916         return 0;
 917
 918 err_ethertype_hash_map_alloc:
 919         rte_hash_free(ethertype_rule->hash_table);
 920
 921         return ret;
 922 }
 923
 924 static int
 925 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 926 {
 927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 928         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 929         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 930         int ret;
 931
 932         struct rte_hash_parameters tunnel_hash_params = {
 933                 .name = tunnel_hash_name,
 934                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 935                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 936                 .hash_func = rte_hash_crc,
 937                 .hash_func_init_val = 0,
 938                 .socket_id = rte_socket_id(),
 939         };
 940
 941         /* Initialize tunnel filter rule list and hash */
 942         TAILQ_INIT(&tunnel_rule->tunnel_list);
 943         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 944                  "tunnel_%s", dev->device->name);
 945         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 946         if (!tunnel_rule->hash_table) {
 947                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 948                 return -EINVAL;
 949         }
 950         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 951                                     sizeof(struct i40e_tunnel_filter *) *
 952                                     I40E_MAX_TUNNEL_FILTER_NUM,
 953                                     0);
 954         if (!tunnel_rule->hash_map) {
 955                 PMD_INIT_LOG(ERR,
 956                              "Failed to allocate memory for tunnel hash map!");
 957                 ret = -ENOMEM;
 958                 goto err_tunnel_hash_map_alloc;
 959         }
 960
 961         return 0;
 962
 963 err_tunnel_hash_map_alloc:
 964         rte_hash_free(tunnel_rule->hash_table);
 965
 966         return ret;
 967 }
 968
 969 static int
 970 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 971 {
 972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 973         struct i40e_fdir_info *fdir_info = &pf->fdir;
 974         char fdir_hash_name[RTE_HASH_NAMESIZE];
 975         int ret;
 976
 977         struct rte_hash_parameters fdir_hash_params = {
 978                 .name = fdir_hash_name,
 979                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 980                 .key_len = sizeof(struct i40e_fdir_input),
 981                 .hash_func = rte_hash_crc,
 982                 .hash_func_init_val = 0,
 983                 .socket_id = rte_socket_id(),
 984         };
 985
 986         /* Initialize flow director filter rule list and hash */
 987         TAILQ_INIT(&fdir_info->fdir_list);
 988         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 989                  "fdir_%s", dev->device->name);
 990         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 991         if (!fdir_info->hash_table) {
 992                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 993                 return -EINVAL;
 994         }
 995         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 996                                           sizeof(struct i40e_fdir_filter *) *
 997                                           I40E_MAX_FDIR_FILTER_NUM,
 998                                           0);
 999         if (!fdir_info->hash_map) {
1000                 PMD_INIT_LOG(ERR,
1001                              "Failed to allocate memory for fdir hash map!");
1002                 ret = -ENOMEM;
1003                 goto err_fdir_hash_map_alloc;
1004         }
1005         return 0;
1006
1007 err_fdir_hash_map_alloc:
1008         rte_hash_free(fdir_info->hash_table);
1009
1010         return ret;
1011 }
1012
1013 static void
1014 i40e_init_customized_info(struct i40e_pf *pf)
1015 {
1016         int i;
1017
1018         /* Initialize customized pctype */
1019         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1020                 pf->customized_pctype[i].index = i;
1021                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1022                 pf->customized_pctype[i].valid = false;
1023         }
1024
1025         pf->gtp_support = false;
1026 }
1027
1028 void
1029 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1030 {
1031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1033         struct i40e_queue_regions *info = &pf->queue_region;
1034         uint16_t i;
1035
1036         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1037                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1038
1039         memset(info, 0, sizeof(struct i40e_queue_regions));
1040 }
1041
1042 static int
1043 eth_i40e_dev_init(struct rte_eth_dev *dev)
1044 {
1045         struct rte_pci_device *pci_dev;
1046         struct rte_intr_handle *intr_handle;
1047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049         struct i40e_vsi *vsi;
1050         int ret;
1051         uint32_t len;
1052         uint8_t aq_fail = 0;
1053
1054         PMD_INIT_FUNC_TRACE();
1055
1056         dev->dev_ops = &i40e_eth_dev_ops;
1057         dev->rx_pkt_burst = i40e_recv_pkts;
1058         dev->tx_pkt_burst = i40e_xmit_pkts;
1059         dev->tx_pkt_prepare = i40e_prep_pkts;
1060
1061         /* for secondary processes, we don't initialise any further as primary
1062          * has already done this work. Only check we don't need a different
1063          * RX function */
1064         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1065                 i40e_set_rx_function(dev);
1066                 i40e_set_tx_function(dev);
1067                 return 0;
1068         }
1069         i40e_set_default_ptype_table(dev);
1070         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1071         intr_handle = &pci_dev->intr_handle;
1072
1073         rte_eth_copy_pci_info(dev, pci_dev);
1074
1075         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1076         pf->adapter->eth_dev = dev;
1077         pf->dev_data = dev->data;
1078
1079         hw->back = I40E_PF_TO_ADAPTER(pf);
1080         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1081         if (!hw->hw_addr) {
1082                 PMD_INIT_LOG(ERR,
1083                         "Hardware is not available, as address is NULL");
1084                 return -ENODEV;
1085         }
1086
1087         hw->vendor_id = pci_dev->id.vendor_id;
1088         hw->device_id = pci_dev->id.device_id;
1089         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1090         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1091         hw->bus.device = pci_dev->addr.devid;
1092         hw->bus.func = pci_dev->addr.function;
1093         hw->adapter_stopped = 0;
1094
1095         /* Make sure all is clean before doing PF reset */
1096         i40e_clear_hw(hw);
1097
1098         /* Initialize the hardware */
1099         i40e_hw_init(dev);
1100
1101         /* Reset here to make sure all is clean for each PF */
1102         ret = i40e_pf_reset(hw);
1103         if (ret) {
1104                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1105                 return ret;
1106         }
1107
1108         /* Initialize the shared code (base driver) */
1109         ret = i40e_init_shared_code(hw);
1110         if (ret) {
1111                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1112                 return ret;
1113         }
1114
1115         i40e_set_default_pctype_table(dev);
1116
1117         /*
1118          * To work around the NVM issue, initialize registers
1119          * for packet type of QinQ by software.
1120          * It should be removed once issues are fixed in NVM.
1121          */
1122         i40e_GLQF_reg_init(hw);
1123
1124         /* Initialize the input set for filters (hash and fd) to default value */
1125         i40e_filter_input_set_init(pf);
1126
1127         /* Initialize the parameters for adminq */
1128         i40e_init_adminq_parameter(hw);
1129         ret = i40e_init_adminq(hw);
1130         if (ret != I40E_SUCCESS) {
1131                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1132                 return -EIO;
1133         }
1134         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1135                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1136                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1137                      ((hw->nvm.version >> 12) & 0xf),
1138                      ((hw->nvm.version >> 4) & 0xff),
1139                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1140
1141         /* initialise the L3_MAP register */
1142         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1143                                    0x00000028,  NULL);
1144         if (ret)
1145                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1146         PMD_INIT_LOG(DEBUG, "Global register 0x%08x is changed with value 0x28",
1147                      I40E_GLQF_L3_MAP(40));
1148         i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1149
1150         /* Need the special FW version to support floating VEB */
1151         config_floating_veb(dev);
1152         /* Clear PXE mode */
1153         i40e_clear_pxe_mode(hw);
1154         i40e_dev_sync_phy_type(hw);
1155
1156         /*
1157          * On X710, performance number is far from the expectation on recent
1158          * firmware versions. The fix for this issue may not be integrated in
1159          * the following firmware version. So the workaround in software driver
1160          * is needed. It needs to modify the initial values of 3 internal only
1161          * registers. Note that the workaround can be removed when it is fixed
1162          * in firmware in the future.
1163          */
1164         i40e_configure_registers(hw);
1165
1166         /* Get hw capabilities */
1167         ret = i40e_get_cap(hw);
1168         if (ret != I40E_SUCCESS) {
1169                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1170                 goto err_get_capabilities;
1171         }
1172
1173         /* Initialize parameters for PF */
1174         ret = i40e_pf_parameter_init(dev);
1175         if (ret != 0) {
1176                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1177                 goto err_parameter_init;
1178         }
1179
1180         /* Initialize the queue management */
1181         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1182         if (ret < 0) {
1183                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1184                 goto err_qp_pool_init;
1185         }
1186         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1187                                 hw->func_caps.num_msix_vectors - 1);
1188         if (ret < 0) {
1189                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1190                 goto err_msix_pool_init;
1191         }
1192
1193         /* Initialize lan hmc */
1194         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1195                                 hw->func_caps.num_rx_qp, 0, 0);
1196         if (ret != I40E_SUCCESS) {
1197                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1198                 goto err_init_lan_hmc;
1199         }
1200
1201         /* Configure lan hmc */
1202         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1203         if (ret != I40E_SUCCESS) {
1204                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1205                 goto err_configure_lan_hmc;
1206         }
1207
1208         /* Get and check the mac address */
1209         i40e_get_mac_addr(hw, hw->mac.addr);
1210         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1211                 PMD_INIT_LOG(ERR, "mac address is not valid");
1212                 ret = -EIO;
1213                 goto err_get_mac_addr;
1214         }
1215         /* Copy the permanent MAC address */
1216         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1217                         (struct ether_addr *) hw->mac.perm_addr);
1218
1219         /* Disable flow control */
1220         hw->fc.requested_mode = I40E_FC_NONE;
1221         i40e_set_fc(hw, &aq_fail, TRUE);
1222
1223         /* Set the global registers with default ether type value */
1224         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1225         if (ret != I40E_SUCCESS) {
1226                 PMD_INIT_LOG(ERR,
1227                         "Failed to set the default outer VLAN ether type");
1228                 goto err_setup_pf_switch;
1229         }
1230
1231         /* PF setup, which includes VSI setup */
1232         ret = i40e_pf_setup(pf);
1233         if (ret) {
1234                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1235                 goto err_setup_pf_switch;
1236         }
1237
1238         /* reset all stats of the device, including pf and main vsi */
1239         i40e_dev_stats_reset(dev);
1240
1241         vsi = pf->main_vsi;
1242
1243         /* Disable double vlan by default */
1244         i40e_vsi_config_double_vlan(vsi, FALSE);
1245
1246         /* Disable S-TAG identification when floating_veb is disabled */
1247         if (!pf->floating_veb) {
1248                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1249                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1250                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1251                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1252                 }
1253         }
1254
1255         if (!vsi->max_macaddrs)
1256                 len = ETHER_ADDR_LEN;
1257         else
1258                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1259
1260         /* Should be after VSI initialized */
1261         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1262         if (!dev->data->mac_addrs) {
1263                 PMD_INIT_LOG(ERR,
1264                         "Failed to allocated memory for storing mac address");
1265                 goto err_mac_alloc;
1266         }
1267         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1268                                         &dev->data->mac_addrs[0]);
1269
1270         /* Init dcb to sw mode by default */
1271         ret = i40e_dcb_init_configure(dev, TRUE);
1272         if (ret != I40E_SUCCESS) {
1273                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1274                 pf->flags &= ~I40E_FLAG_DCB;
1275         }
1276         /* Update HW struct after DCB configuration */
1277         i40e_get_cap(hw);
1278
1279         /* initialize pf host driver to setup SRIOV resource if applicable */
1280         i40e_pf_host_init(dev);
1281
1282         /* register callback func to eal lib */
1283         rte_intr_callback_register(intr_handle,
1284                                    i40e_dev_interrupt_handler, dev);
1285
1286         /* configure and enable device interrupt */
1287         i40e_pf_config_irq0(hw, TRUE);
1288         i40e_pf_enable_irq0(hw);
1289
1290         /* enable uio intr after callback register */
1291         rte_intr_enable(intr_handle);
1292
1293         /* By default disable flexible payload in global configuration */
1294         i40e_flex_payload_reg_set_default(hw);
1295
1296         /*
1297          * Add an ethertype filter to drop all flow control frames transmitted
1298          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1299          * frames to wire.
1300          */
1301         i40e_add_tx_flow_control_drop_filter(pf);
1302
1303         /* Set the max frame size to 0x2600 by default,
1304          * in case other drivers changed the default value.
1305          */
1306         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1307
1308         /* initialize mirror rule list */
1309         TAILQ_INIT(&pf->mirror_list);
1310
1311         /* initialize Traffic Manager configuration */
1312         i40e_tm_conf_init(dev);
1313
1314         /* Initialize customized information */
1315         i40e_init_customized_info(pf);
1316
1317         ret = i40e_init_ethtype_filter_list(dev);
1318         if (ret < 0)
1319                 goto err_init_ethtype_filter_list;
1320         ret = i40e_init_tunnel_filter_list(dev);
1321         if (ret < 0)
1322                 goto err_init_tunnel_filter_list;
1323         ret = i40e_init_fdir_filter_list(dev);
1324         if (ret < 0)
1325                 goto err_init_fdir_filter_list;
1326
1327         /* initialize queue region configuration */
1328         i40e_init_queue_region_conf(dev);
1329
1330         /* initialize rss configuration from rte_flow */
1331         memset(&pf->rss_info, 0,
1332                 sizeof(struct i40e_rte_flow_rss_conf));
1333
1334         return 0;
1335
1336 err_init_fdir_filter_list:
1337         rte_free(pf->tunnel.hash_table);
1338         rte_free(pf->tunnel.hash_map);
1339 err_init_tunnel_filter_list:
1340         rte_free(pf->ethertype.hash_table);
1341         rte_free(pf->ethertype.hash_map);
1342 err_init_ethtype_filter_list:
1343         rte_free(dev->data->mac_addrs);
1344 err_mac_alloc:
1345         i40e_vsi_release(pf->main_vsi);
1346 err_setup_pf_switch:
1347 err_get_mac_addr:
1348 err_configure_lan_hmc:
1349         (void)i40e_shutdown_lan_hmc(hw);
1350 err_init_lan_hmc:
1351         i40e_res_pool_destroy(&pf->msix_pool);
1352 err_msix_pool_init:
1353         i40e_res_pool_destroy(&pf->qp_pool);
1354 err_qp_pool_init:
1355 err_parameter_init:
1356 err_get_capabilities:
1357         (void)i40e_shutdown_adminq(hw);
1358
1359         return ret;
1360 }
1361
1362 static void
1363 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1364 {
1365         struct i40e_ethertype_filter *p_ethertype;
1366         struct i40e_ethertype_rule *ethertype_rule;
1367
1368         ethertype_rule = &pf->ethertype;
1369         /* Remove all ethertype filter rules and hash */
1370         if (ethertype_rule->hash_map)
1371                 rte_free(ethertype_rule->hash_map);
1372         if (ethertype_rule->hash_table)
1373                 rte_hash_free(ethertype_rule->hash_table);
1374
1375         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1376                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1377                              p_ethertype, rules);
1378                 rte_free(p_ethertype);
1379         }
1380 }
1381
1382 static void
1383 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1384 {
1385         struct i40e_tunnel_filter *p_tunnel;
1386         struct i40e_tunnel_rule *tunnel_rule;
1387
1388         tunnel_rule = &pf->tunnel;
1389         /* Remove all tunnel director rules and hash */
1390         if (tunnel_rule->hash_map)
1391                 rte_free(tunnel_rule->hash_map);
1392         if (tunnel_rule->hash_table)
1393                 rte_hash_free(tunnel_rule->hash_table);
1394
1395         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1396                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1397                 rte_free(p_tunnel);
1398         }
1399 }
1400
1401 static void
1402 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1403 {
1404         struct i40e_fdir_filter *p_fdir;
1405         struct i40e_fdir_info *fdir_info;
1406
1407         fdir_info = &pf->fdir;
1408         /* Remove all flow director rules and hash */
1409         if (fdir_info->hash_map)
1410                 rte_free(fdir_info->hash_map);
1411         if (fdir_info->hash_table)
1412                 rte_hash_free(fdir_info->hash_table);
1413
1414         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1415                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1416                 rte_free(p_fdir);
1417         }
1418 }
1419
1420 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1421 {
1422         /*
1423          * Disable by default flexible payload
1424          * for corresponding L2/L3/L4 layers.
1425          */
1426         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1427         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1428         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1429         i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1430 }
1431
1432 static int
1433 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1434 {
1435         struct i40e_pf *pf;
1436         struct rte_pci_device *pci_dev;
1437         struct rte_intr_handle *intr_handle;
1438         struct i40e_hw *hw;
1439         struct i40e_filter_control_settings settings;
1440         struct rte_flow *p_flow;
1441         int ret;
1442         uint8_t aq_fail = 0;
1443
1444         PMD_INIT_FUNC_TRACE();
1445
1446         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1447                 return 0;
1448
1449         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1450         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1451         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1452         intr_handle = &pci_dev->intr_handle;
1453
1454         if (hw->adapter_stopped == 0)
1455                 i40e_dev_close(dev);
1456
1457         dev->dev_ops = NULL;
1458         dev->rx_pkt_burst = NULL;
1459         dev->tx_pkt_burst = NULL;
1460
1461         /* Clear PXE mode */
1462         i40e_clear_pxe_mode(hw);
1463
1464         /* Unconfigure filter control */
1465         memset(&settings, 0, sizeof(settings));
1466         ret = i40e_set_filter_control(hw, &settings);
1467         if (ret)
1468                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1469                                         ret);
1470
1471         /* Disable flow control */
1472         hw->fc.requested_mode = I40E_FC_NONE;
1473         i40e_set_fc(hw, &aq_fail, TRUE);
1474
1475         /* uninitialize pf host driver */
1476         i40e_pf_host_uninit(dev);
1477
1478         rte_free(dev->data->mac_addrs);
1479         dev->data->mac_addrs = NULL;
1480
1481         /* disable uio intr before callback unregister */
1482         rte_intr_disable(intr_handle);
1483
1484         /* register callback func to eal lib */
1485         rte_intr_callback_unregister(intr_handle,
1486                                      i40e_dev_interrupt_handler, dev);
1487
1488         i40e_rm_ethtype_filter_list(pf);
1489         i40e_rm_tunnel_filter_list(pf);
1490         i40e_rm_fdir_filter_list(pf);
1491
1492         /* Remove all flows */
1493         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1494                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1495                 rte_free(p_flow);
1496         }
1497
1498         /* Remove all Traffic Manager configuration */
1499         i40e_tm_conf_uninit(dev);
1500
1501         return 0;
1502 }
1503
1504 static int
1505 i40e_dev_configure(struct rte_eth_dev *dev)
1506 {
1507         struct i40e_adapter *ad =
1508                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1509         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1510         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1511         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1512         int i, ret;
1513
1514         ret = i40e_dev_sync_phy_type(hw);
1515         if (ret)
1516                 return ret;
1517
1518         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1519          * bulk allocation or vector Rx preconditions we will reset it.
1520          */
1521         ad->rx_bulk_alloc_allowed = true;
1522         ad->rx_vec_allowed = true;
1523         ad->tx_simple_allowed = true;
1524         ad->tx_vec_allowed = true;
1525
1526         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1527                 ret = i40e_fdir_setup(pf);
1528                 if (ret != I40E_SUCCESS) {
1529                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1530                         return -ENOTSUP;
1531                 }
1532                 ret = i40e_fdir_configure(dev);
1533                 if (ret < 0) {
1534                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1535                         goto err;
1536                 }
1537         } else
1538                 i40e_fdir_teardown(pf);
1539
1540         ret = i40e_dev_init_vlan(dev);
1541         if (ret < 0)
1542                 goto err;
1543
1544         /* VMDQ setup.
1545          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1546          *  RSS setting have different requirements.
1547          *  General PMD driver call sequence are NIC init, configure,
1548          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1549          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1550          *  applicable. So, VMDQ setting has to be done before
1551          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1552          *  For RSS setting, it will try to calculate actual configured RX queue
1553          *  number, which will be available after rx_queue_setup(). dev_start()
1554          *  function is good to place RSS setup.
1555          */
1556         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1557                 ret = i40e_vmdq_setup(dev);
1558                 if (ret)
1559                         goto err;
1560         }
1561
1562         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1563                 ret = i40e_dcb_setup(dev);
1564                 if (ret) {
1565                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1566                         goto err_dcb;
1567                 }
1568         }
1569
1570         TAILQ_INIT(&pf->flow_list);
1571
1572         return 0;
1573
1574 err_dcb:
1575         /* need to release vmdq resource if exists */
1576         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1577                 i40e_vsi_release(pf->vmdq[i].vsi);
1578                 pf->vmdq[i].vsi = NULL;
1579         }
1580         rte_free(pf->vmdq);
1581         pf->vmdq = NULL;
1582 err:
1583         /* need to release fdir resource if exists */
1584         i40e_fdir_teardown(pf);
1585         return ret;
1586 }
1587
1588 void
1589 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1590 {
1591         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1592         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1593         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1594         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1595         uint16_t msix_vect = vsi->msix_intr;
1596         uint16_t i;
1597
1598         for (i = 0; i < vsi->nb_qps; i++) {
1599                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1600                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1601                 rte_wmb();
1602         }
1603
1604         if (vsi->type != I40E_VSI_SRIOV) {
1605                 if (!rte_intr_allow_others(intr_handle)) {
1606                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1607                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1608                         I40E_WRITE_REG(hw,
1609                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1610                                        0);
1611                 } else {
1612                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1613                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1614                         I40E_WRITE_REG(hw,
1615                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1616                                                        msix_vect - 1), 0);
1617                 }
1618         } else {
1619                 uint32_t reg;
1620                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1621                         vsi->user_param + (msix_vect - 1);
1622
1623                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1624                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1625         }
1626         I40E_WRITE_FLUSH(hw);
1627 }
1628
1629 static void
1630 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1631                        int base_queue, int nb_queue,
1632                        uint16_t itr_idx)
1633 {
1634         int i;
1635         uint32_t val;
1636         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1637
1638         /* Bind all RX queues to allocated MSIX interrupt */
1639         for (i = 0; i < nb_queue; i++) {
1640                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1641                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1642                         ((base_queue + i + 1) <<
1643                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1644                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1645                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1646
1647                 if (i == nb_queue - 1)
1648                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1649                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1650         }
1651
1652         /* Write first RX queue to Link list register as the head element */
1653         if (vsi->type != I40E_VSI_SRIOV) {
1654                 uint16_t interval =
1655                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1656
1657                 if (msix_vect == I40E_MISC_VEC_ID) {
1658                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1659                                        (base_queue <<
1660                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1661                                        (0x0 <<
1662                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1663                         I40E_WRITE_REG(hw,
1664                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1665                                        interval);
1666                 } else {
1667                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1668                                        (base_queue <<
1669                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1670                                        (0x0 <<
1671                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1672                         I40E_WRITE_REG(hw,
1673                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1674                                                        msix_vect - 1),
1675                                        interval);
1676                 }
1677         } else {
1678                 uint32_t reg;
1679
1680                 if (msix_vect == I40E_MISC_VEC_ID) {
1681                         I40E_WRITE_REG(hw,
1682                                        I40E_VPINT_LNKLST0(vsi->user_param),
1683                                        (base_queue <<
1684                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1685                                        (0x0 <<
1686                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1687                 } else {
1688                         /* num_msix_vectors_vf needs to minus irq0 */
1689                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1690                                 vsi->user_param + (msix_vect - 1);
1691
1692                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1693                                        (base_queue <<
1694                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1695                                        (0x0 <<
1696                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1697                 }
1698         }
1699
1700         I40E_WRITE_FLUSH(hw);
1701 }
1702
1703 void
1704 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1705 {
1706         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1707         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1708         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1709         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1710         uint16_t msix_vect = vsi->msix_intr;
1711         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1712         uint16_t queue_idx = 0;
1713         int record = 0;
1714         uint32_t val;
1715         int i;
1716
1717         for (i = 0; i < vsi->nb_qps; i++) {
1718                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1719                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1720         }
1721
1722         /* INTENA flag is not auto-cleared for interrupt */
1723         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1724         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1725                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1726                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1727         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1728
1729         /* VF bind interrupt */
1730         if (vsi->type == I40E_VSI_SRIOV) {
1731                 __vsi_queues_bind_intr(vsi, msix_vect,
1732                                        vsi->base_queue, vsi->nb_qps,
1733                                        itr_idx);
1734                 return;
1735         }
1736
1737         /* PF & VMDq bind interrupt */
1738         if (rte_intr_dp_is_en(intr_handle)) {
1739                 if (vsi->type == I40E_VSI_MAIN) {
1740                         queue_idx = 0;
1741                         record = 1;
1742                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1743                         struct i40e_vsi *main_vsi =
1744                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1745                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1746                         record = 1;
1747                 }
1748         }
1749
1750         for (i = 0; i < vsi->nb_used_qps; i++) {
1751                 if (nb_msix <= 1) {
1752                         if (!rte_intr_allow_others(intr_handle))
1753                                 /* allow to share MISC_VEC_ID */
1754                                 msix_vect = I40E_MISC_VEC_ID;
1755
1756                         /* no enough msix_vect, map all to one */
1757                         __vsi_queues_bind_intr(vsi, msix_vect,
1758                                                vsi->base_queue + i,
1759                                                vsi->nb_used_qps - i,
1760                                                itr_idx);
1761                         for (; !!record && i < vsi->nb_used_qps; i++)
1762                                 intr_handle->intr_vec[queue_idx + i] =
1763                                         msix_vect;
1764                         break;
1765                 }
1766                 /* 1:1 queue/msix_vect mapping */
1767                 __vsi_queues_bind_intr(vsi, msix_vect,
1768                                        vsi->base_queue + i, 1,
1769                                        itr_idx);
1770                 if (!!record)
1771                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1772
1773                 msix_vect++;
1774                 nb_msix--;
1775         }
1776 }
1777
1778 static void
1779 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1780 {
1781         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1782         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1783         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1784         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1785         uint16_t interval = i40e_calc_itr_interval(\
1786                 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1787         uint16_t msix_intr, i;
1788
1789         if (rte_intr_allow_others(intr_handle))
1790                 for (i = 0; i < vsi->nb_msix; i++) {
1791                         msix_intr = vsi->msix_intr + i;
1792                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1793                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1794                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1795                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1796                                 (interval <<
1797                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1798                 }
1799         else
1800                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1801                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1802                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1803                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1804                                (interval <<
1805                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1806
1807         I40E_WRITE_FLUSH(hw);
1808 }
1809
1810 static void
1811 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1812 {
1813         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1814         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1815         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1816         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1817         uint16_t msix_intr, i;
1818
1819         if (rte_intr_allow_others(intr_handle))
1820                 for (i = 0; i < vsi->nb_msix; i++) {
1821                         msix_intr = vsi->msix_intr + i;
1822                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1823                                        0);
1824                 }
1825         else
1826                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1827
1828         I40E_WRITE_FLUSH(hw);
1829 }
1830
1831 static inline uint8_t
1832 i40e_parse_link_speeds(uint16_t link_speeds)
1833 {
1834         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1835
1836         if (link_speeds & ETH_LINK_SPEED_40G)
1837                 link_speed |= I40E_LINK_SPEED_40GB;
1838         if (link_speeds & ETH_LINK_SPEED_25G)
1839                 link_speed |= I40E_LINK_SPEED_25GB;
1840         if (link_speeds & ETH_LINK_SPEED_20G)
1841                 link_speed |= I40E_LINK_SPEED_20GB;
1842         if (link_speeds & ETH_LINK_SPEED_10G)
1843                 link_speed |= I40E_LINK_SPEED_10GB;
1844         if (link_speeds & ETH_LINK_SPEED_1G)
1845                 link_speed |= I40E_LINK_SPEED_1GB;
1846         if (link_speeds & ETH_LINK_SPEED_100M)
1847                 link_speed |= I40E_LINK_SPEED_100MB;
1848
1849         return link_speed;
1850 }
1851
1852 static int
1853 i40e_phy_conf_link(struct i40e_hw *hw,
1854                    uint8_t abilities,
1855                    uint8_t force_speed,
1856                    bool is_up)
1857 {
1858         enum i40e_status_code status;
1859         struct i40e_aq_get_phy_abilities_resp phy_ab;
1860         struct i40e_aq_set_phy_config phy_conf;
1861         enum i40e_aq_phy_type cnt;
1862         uint32_t phy_type_mask = 0;
1863
1864         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1865                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1866                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1867                         I40E_AQ_PHY_FLAG_LOW_POWER;
1868         const uint8_t advt = I40E_LINK_SPEED_40GB |
1869                         I40E_LINK_SPEED_25GB |
1870                         I40E_LINK_SPEED_10GB |
1871                         I40E_LINK_SPEED_1GB |
1872                         I40E_LINK_SPEED_100MB;
1873         int ret = -ENOTSUP;
1874
1875
1876         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1877                                               NULL);
1878         if (status)
1879                 return ret;
1880
1881         /* If link already up, no need to set up again */
1882         if (is_up && phy_ab.phy_type != 0)
1883                 return I40E_SUCCESS;
1884
1885         memset(&phy_conf, 0, sizeof(phy_conf));
1886
1887         /* bits 0-2 use the values from get_phy_abilities_resp */
1888         abilities &= ~mask;
1889         abilities |= phy_ab.abilities & mask;
1890
1891         /* update ablities and speed */
1892         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1893                 phy_conf.link_speed = advt;
1894         else
1895                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1896
1897         phy_conf.abilities = abilities;
1898
1899
1900
1901         /* To enable link, phy_type mask needs to include each type */
1902         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1903                 phy_type_mask |= 1 << cnt;
1904
1905         /* use get_phy_abilities_resp value for the rest */
1906         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1907         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1908                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1909                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1910         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1911         phy_conf.eee_capability = phy_ab.eee_capability;
1912         phy_conf.eeer = phy_ab.eeer_val;
1913         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1914
1915         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1916                     phy_ab.abilities, phy_ab.link_speed);
1917         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1918                     phy_conf.abilities, phy_conf.link_speed);
1919
1920         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1921         if (status)
1922                 return ret;
1923
1924         return I40E_SUCCESS;
1925 }
1926
1927 static int
1928 i40e_apply_link_speed(struct rte_eth_dev *dev)
1929 {
1930         uint8_t speed;
1931         uint8_t abilities = 0;
1932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933         struct rte_eth_conf *conf = &dev->data->dev_conf;
1934
1935         speed = i40e_parse_link_speeds(conf->link_speeds);
1936         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1937         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1938                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1939         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1940
1941         return i40e_phy_conf_link(hw, abilities, speed, true);
1942 }
1943
1944 static int
1945 i40e_dev_start(struct rte_eth_dev *dev)
1946 {
1947         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949         struct i40e_vsi *main_vsi = pf->main_vsi;
1950         int ret, i;
1951         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1952         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1953         uint32_t intr_vector = 0;
1954         struct i40e_vsi *vsi;
1955
1956         hw->adapter_stopped = 0;
1957
1958         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1959                 PMD_INIT_LOG(ERR,
1960                 "Invalid link_speeds for port %u, autonegotiation disabled",
1961                               dev->data->port_id);
1962                 return -EINVAL;
1963         }
1964
1965         rte_intr_disable(intr_handle);
1966
1967         if ((rte_intr_cap_multiple(intr_handle) ||
1968              !RTE_ETH_DEV_SRIOV(dev).active) &&
1969             dev->data->dev_conf.intr_conf.rxq != 0) {
1970                 intr_vector = dev->data->nb_rx_queues;
1971                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1972                 if (ret)
1973                         return ret;
1974         }
1975
1976         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1977                 intr_handle->intr_vec =
1978                         rte_zmalloc("intr_vec",
1979                                     dev->data->nb_rx_queues * sizeof(int),
1980                                     0);
1981                 if (!intr_handle->intr_vec) {
1982                         PMD_INIT_LOG(ERR,
1983                                 "Failed to allocate %d rx_queues intr_vec",
1984                                 dev->data->nb_rx_queues);
1985                         return -ENOMEM;
1986                 }
1987         }
1988
1989         /* Initialize VSI */
1990         ret = i40e_dev_rxtx_init(pf);
1991         if (ret != I40E_SUCCESS) {
1992                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1993                 goto err_up;
1994         }
1995
1996         /* Map queues with MSIX interrupt */
1997         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1998                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1999         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2000         i40e_vsi_enable_queues_intr(main_vsi);
2001
2002         /* Map VMDQ VSI queues with MSIX interrupt */
2003         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2004                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2005                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2006                                           I40E_ITR_INDEX_DEFAULT);
2007                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2008         }
2009
2010         /* enable FDIR MSIX interrupt */
2011         if (pf->fdir.fdir_vsi) {
2012                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2013                                           I40E_ITR_INDEX_NONE);
2014                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2015         }
2016
2017         /* Enable all queues which have been configured */
2018         ret = i40e_dev_switch_queues(pf, TRUE);
2019
2020         if (ret != I40E_SUCCESS) {
2021                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2022                 goto err_up;
2023         }
2024
2025         /* Enable receiving broadcast packets */
2026         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2027         if (ret != I40E_SUCCESS)
2028                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2029
2030         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2031                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2032                                                 true, NULL);
2033                 if (ret != I40E_SUCCESS)
2034                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2035         }
2036
2037         /* Enable the VLAN promiscuous mode. */
2038         if (pf->vfs) {
2039                 for (i = 0; i < pf->vf_num; i++) {
2040                         vsi = pf->vfs[i].vsi;
2041                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2042                                                      true, NULL);
2043                 }
2044         }
2045
2046         /* Enable mac loopback mode */
2047         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2048             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2049                 ret = i40e_diag_set_loopback(hw, dev->data->dev_conf.lpbk_mode);
2050                 if (ret != I40E_SUCCESS) {
2051                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2052                         goto err_up;
2053                 }
2054         }
2055
2056         /* Apply link configure */
2057         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2058                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2059                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2060                                 ETH_LINK_SPEED_40G)) {
2061                 PMD_DRV_LOG(ERR, "Invalid link setting");
2062                 goto err_up;
2063         }
2064         ret = i40e_apply_link_speed(dev);
2065         if (I40E_SUCCESS != ret) {
2066                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2067                 goto err_up;
2068         }
2069
2070         if (!rte_intr_allow_others(intr_handle)) {
2071                 rte_intr_callback_unregister(intr_handle,
2072                                              i40e_dev_interrupt_handler,
2073                                              (void *)dev);
2074                 /* configure and enable device interrupt */
2075                 i40e_pf_config_irq0(hw, FALSE);
2076                 i40e_pf_enable_irq0(hw);
2077
2078                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2079                         PMD_INIT_LOG(INFO,
2080                                 "lsc won't enable because of no intr multiplex");
2081         } else {
2082                 ret = i40e_aq_set_phy_int_mask(hw,
2083                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2084                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2085                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2086                 if (ret != I40E_SUCCESS)
2087                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2088
2089                 /* Call get_link_info aq commond to enable/disable LSE */
2090                 i40e_dev_link_update(dev, 0);
2091         }
2092
2093         /* enable uio intr after callback register */
2094         rte_intr_enable(intr_handle);
2095
2096         i40e_filter_restore(pf);
2097
2098         if (pf->tm_conf.root && !pf->tm_conf.committed)
2099                 PMD_DRV_LOG(WARNING,
2100                             "please call hierarchy_commit() "
2101                             "before starting the port");
2102
2103         return I40E_SUCCESS;
2104
2105 err_up:
2106         i40e_dev_switch_queues(pf, FALSE);
2107         i40e_dev_clear_queues(dev);
2108
2109         return ret;
2110 }
2111
2112 static void
2113 i40e_dev_stop(struct rte_eth_dev *dev)
2114 {
2115         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2116         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117         struct i40e_vsi *main_vsi = pf->main_vsi;
2118         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2119         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2120         int i;
2121
2122         if (hw->adapter_stopped == 1)
2123                 return;
2124         /* Disable all queues */
2125         i40e_dev_switch_queues(pf, FALSE);
2126
2127         /* un-map queues with interrupt registers */
2128         i40e_vsi_disable_queues_intr(main_vsi);
2129         i40e_vsi_queues_unbind_intr(main_vsi);
2130
2131         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2132                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2133                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2134         }
2135
2136         if (pf->fdir.fdir_vsi) {
2137                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2138                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2139         }
2140         /* Clear all queues and release memory */
2141         i40e_dev_clear_queues(dev);
2142
2143         /* Set link down */
2144         i40e_dev_set_link_down(dev);
2145
2146         if (!rte_intr_allow_others(intr_handle))
2147                 /* resume to the default handler */
2148                 rte_intr_callback_register(intr_handle,
2149                                            i40e_dev_interrupt_handler,
2150                                            (void *)dev);
2151
2152         /* Clean datapath event and queue/vec mapping */
2153         rte_intr_efd_disable(intr_handle);
2154         if (intr_handle->intr_vec) {
2155                 rte_free(intr_handle->intr_vec);
2156                 intr_handle->intr_vec = NULL;
2157         }
2158
2159         /* reset hierarchy commit */
2160         pf->tm_conf.committed = false;
2161
2162         hw->adapter_stopped = 1;
2163 }
2164
2165 static void
2166 i40e_dev_close(struct rte_eth_dev *dev)
2167 {
2168         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2169         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2170         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2171         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2172         struct i40e_mirror_rule *p_mirror;
2173         uint32_t reg;
2174         int i;
2175         int ret;
2176
2177         PMD_INIT_FUNC_TRACE();
2178
2179         i40e_dev_stop(dev);
2180
2181         /* Remove all mirror rules */
2182         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2183                 ret = i40e_aq_del_mirror_rule(hw,
2184                                               pf->main_vsi->veb->seid,
2185                                               p_mirror->rule_type,
2186                                               p_mirror->entries,
2187                                               p_mirror->num_entries,
2188                                               p_mirror->id);
2189                 if (ret < 0)
2190                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2191                                     "status = %d, aq_err = %d.", ret,
2192                                     hw->aq.asq_last_status);
2193
2194                 /* remove mirror software resource anyway */
2195                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2196                 rte_free(p_mirror);
2197                 pf->nb_mirror_rule--;
2198         }
2199
2200         i40e_dev_free_queues(dev);
2201
2202         /* Disable interrupt */
2203         i40e_pf_disable_irq0(hw);
2204         rte_intr_disable(intr_handle);
2205
2206         /* shutdown and destroy the HMC */
2207         i40e_shutdown_lan_hmc(hw);
2208
2209         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2210                 i40e_vsi_release(pf->vmdq[i].vsi);
2211                 pf->vmdq[i].vsi = NULL;
2212         }
2213         rte_free(pf->vmdq);
2214         pf->vmdq = NULL;
2215
2216         /* release all the existing VSIs and VEBs */
2217         i40e_fdir_teardown(pf);
2218         i40e_vsi_release(pf->main_vsi);
2219
2220         /* shutdown the adminq */
2221         i40e_aq_queue_shutdown(hw, true);
2222         i40e_shutdown_adminq(hw);
2223
2224         i40e_res_pool_destroy(&pf->qp_pool);
2225         i40e_res_pool_destroy(&pf->msix_pool);
2226
2227         /* Disable flexible payload in global configuration */
2228         i40e_flex_payload_reg_set_default(hw);
2229
2230         /* force a PF reset to clean anything leftover */
2231         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2232         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2233                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2234         I40E_WRITE_FLUSH(hw);
2235 }
2236
2237 /*
2238  * Reset PF device only to re-initialize resources in PMD layer
2239  */
2240 static int
2241 i40e_dev_reset(struct rte_eth_dev *dev)
2242 {
2243         int ret;
2244
2245         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2246          * its VF to make them align with it. The detailed notification
2247          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2248          * To avoid unexpected behavior in VF, currently reset of PF with
2249          * SR-IOV activation is not supported. It might be supported later.
2250          */
2251         if (dev->data->sriov.active)
2252                 return -ENOTSUP;
2253
2254         ret = eth_i40e_dev_uninit(dev);
2255         if (ret)
2256                 return ret;
2257
2258         ret = eth_i40e_dev_init(dev);
2259
2260         return ret;
2261 }
2262
2263 static void
2264 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2265 {
2266         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2268         struct i40e_vsi *vsi = pf->main_vsi;
2269         int status;
2270
2271         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2272                                                      true, NULL, true);
2273         if (status != I40E_SUCCESS)
2274                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2275
2276         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2277                                                         TRUE, NULL);
2278         if (status != I40E_SUCCESS)
2279                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2280
2281 }
2282
2283 static void
2284 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2285 {
2286         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2287         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2288         struct i40e_vsi *vsi = pf->main_vsi;
2289         int status;
2290
2291         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2292                                                      false, NULL, true);
2293         if (status != I40E_SUCCESS)
2294                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2295
2296         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2297                                                         false, NULL);
2298         if (status != I40E_SUCCESS)
2299                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2300 }
2301
2302 static void
2303 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2304 {
2305         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307         struct i40e_vsi *vsi = pf->main_vsi;
2308         int ret;
2309
2310         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2311         if (ret != I40E_SUCCESS)
2312                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2313 }
2314
2315 static void
2316 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2317 {
2318         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2319         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320         struct i40e_vsi *vsi = pf->main_vsi;
2321         int ret;
2322
2323         if (dev->data->promiscuous == 1)
2324                 return; /* must remain in all_multicast mode */
2325
2326         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2327                                 vsi->seid, FALSE, NULL);
2328         if (ret != I40E_SUCCESS)
2329                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2330 }
2331
2332 /*
2333  * Set device link up.
2334  */
2335 static int
2336 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2337 {
2338         /* re-apply link speed setting */
2339         return i40e_apply_link_speed(dev);
2340 }
2341
2342 /*
2343  * Set device link down.
2344  */
2345 static int
2346 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2347 {
2348         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2349         uint8_t abilities = 0;
2350         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351
2352         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2353         return i40e_phy_conf_link(hw, abilities, speed, false);
2354 }
2355
2356 int
2357 i40e_dev_link_update(struct rte_eth_dev *dev,
2358                      int wait_to_complete)
2359 {
2360 #define CHECK_INTERVAL 100  /* 100ms */
2361 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363         struct i40e_link_status link_status;
2364         struct rte_eth_link link, old;
2365         int status;
2366         unsigned rep_cnt = MAX_REPEAT_TIME;
2367         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2368
2369         memset(&link, 0, sizeof(link));
2370         memset(&old, 0, sizeof(old));
2371         memset(&link_status, 0, sizeof(link_status));
2372         rte_i40e_dev_atomic_read_link_status(dev, &old);
2373
2374         do {
2375                 /* Get link status information from hardware */
2376                 status = i40e_aq_get_link_info(hw, enable_lse,
2377                                                 &link_status, NULL);
2378                 if (status != I40E_SUCCESS) {
2379                         link.link_speed = ETH_SPEED_NUM_100M;
2380                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2381                         PMD_DRV_LOG(ERR, "Failed to get link info");
2382                         goto out;
2383                 }
2384
2385                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2386                 if (!wait_to_complete || link.link_status)
2387                         break;
2388
2389                 rte_delay_ms(CHECK_INTERVAL);
2390         } while (--rep_cnt);
2391
2392         if (!link.link_status)
2393                 goto out;
2394
2395         /* i40e uses full duplex only */
2396         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2397
2398         /* Parse the link status */
2399         switch (link_status.link_speed) {
2400         case I40E_LINK_SPEED_100MB:
2401                 link.link_speed = ETH_SPEED_NUM_100M;
2402                 break;
2403         case I40E_LINK_SPEED_1GB:
2404                 link.link_speed = ETH_SPEED_NUM_1G;
2405                 break;
2406         case I40E_LINK_SPEED_10GB:
2407                 link.link_speed = ETH_SPEED_NUM_10G;
2408                 break;
2409         case I40E_LINK_SPEED_20GB:
2410                 link.link_speed = ETH_SPEED_NUM_20G;
2411                 break;
2412         case I40E_LINK_SPEED_25GB:
2413                 link.link_speed = ETH_SPEED_NUM_25G;
2414                 break;
2415         case I40E_LINK_SPEED_40GB:
2416                 link.link_speed = ETH_SPEED_NUM_40G;
2417                 break;
2418         default:
2419                 link.link_speed = ETH_SPEED_NUM_100M;
2420                 break;
2421         }
2422
2423         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2424                         ETH_LINK_SPEED_FIXED);
2425
2426 out:
2427         rte_i40e_dev_atomic_write_link_status(dev, &link);
2428         if (link.link_status == old.link_status)
2429                 return -1;
2430
2431         i40e_notify_all_vfs_link_status(dev);
2432
2433         return 0;
2434 }
2435
2436 /* Get all the statistics of a VSI */
2437 void
2438 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2439 {
2440         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2441         struct i40e_eth_stats *nes = &vsi->eth_stats;
2442         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2443         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2444
2445         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2446                             vsi->offset_loaded, &oes->rx_bytes,
2447                             &nes->rx_bytes);
2448         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2449                             vsi->offset_loaded, &oes->rx_unicast,
2450                             &nes->rx_unicast);
2451         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2452                             vsi->offset_loaded, &oes->rx_multicast,
2453                             &nes->rx_multicast);
2454         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2455                             vsi->offset_loaded, &oes->rx_broadcast,
2456                             &nes->rx_broadcast);
2457         /* exclude CRC bytes */
2458         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2459                 nes->rx_broadcast) * ETHER_CRC_LEN;
2460
2461         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2462                             &oes->rx_discards, &nes->rx_discards);
2463         /* GLV_REPC not supported */
2464         /* GLV_RMPC not supported */
2465         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2466                             &oes->rx_unknown_protocol,
2467                             &nes->rx_unknown_protocol);
2468         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2469                             vsi->offset_loaded, &oes->tx_bytes,
2470                             &nes->tx_bytes);
2471         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2472                             vsi->offset_loaded, &oes->tx_unicast,
2473                             &nes->tx_unicast);
2474         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2475                             vsi->offset_loaded, &oes->tx_multicast,
2476                             &nes->tx_multicast);
2477         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2478                             vsi->offset_loaded,  &oes->tx_broadcast,
2479                             &nes->tx_broadcast);
2480         /* GLV_TDPC not supported */
2481         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2482                             &oes->tx_errors, &nes->tx_errors);
2483         vsi->offset_loaded = true;
2484
2485         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2486                     vsi->vsi_id);
2487         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2488         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2489         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2490         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2491         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2492         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2493                     nes->rx_unknown_protocol);
2494         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2495         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2496         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2497         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2498         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2499         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2500         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2501                     vsi->vsi_id);
2502 }
2503
2504 static void
2505 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2506 {
2507         unsigned int i;
2508         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2509         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2510
2511         /* Get rx/tx bytes of internal transfer packets */
2512         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2513                         I40E_GLV_GORCL(hw->port),
2514                         pf->offset_loaded,
2515                         &pf->internal_stats_offset.rx_bytes,
2516                         &pf->internal_stats.rx_bytes);
2517
2518         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2519                         I40E_GLV_GOTCL(hw->port),
2520                         pf->offset_loaded,
2521                         &pf->internal_stats_offset.tx_bytes,
2522                         &pf->internal_stats.tx_bytes);
2523         /* Get total internal rx packet count */
2524         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2525                             I40E_GLV_UPRCL(hw->port),
2526                             pf->offset_loaded,
2527                             &pf->internal_stats_offset.rx_unicast,
2528                             &pf->internal_stats.rx_unicast);
2529         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2530                             I40E_GLV_MPRCL(hw->port),
2531                             pf->offset_loaded,
2532                             &pf->internal_stats_offset.rx_multicast,
2533                             &pf->internal_stats.rx_multicast);
2534         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2535                             I40E_GLV_BPRCL(hw->port),
2536                             pf->offset_loaded,
2537                             &pf->internal_stats_offset.rx_broadcast,
2538                             &pf->internal_stats.rx_broadcast);
2539         /* Get total internal tx packet count */
2540         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2541                             I40E_GLV_UPTCL(hw->port),
2542                             pf->offset_loaded,
2543                             &pf->internal_stats_offset.tx_unicast,
2544                             &pf->internal_stats.tx_unicast);
2545         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2546                             I40E_GLV_MPTCL(hw->port),
2547                             pf->offset_loaded,
2548                             &pf->internal_stats_offset.tx_multicast,
2549                             &pf->internal_stats.tx_multicast);
2550         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2551                             I40E_GLV_BPTCL(hw->port),
2552                             pf->offset_loaded,
2553                             &pf->internal_stats_offset.tx_broadcast,
2554                             &pf->internal_stats.tx_broadcast);
2555
2556         /* exclude CRC size */
2557         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2558                 pf->internal_stats.rx_multicast +
2559                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2560
2561         /* Get statistics of struct i40e_eth_stats */
2562         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2563                             I40E_GLPRT_GORCL(hw->port),
2564                             pf->offset_loaded, &os->eth.rx_bytes,
2565                             &ns->eth.rx_bytes);
2566         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2567                             I40E_GLPRT_UPRCL(hw->port),
2568                             pf->offset_loaded, &os->eth.rx_unicast,
2569                             &ns->eth.rx_unicast);
2570         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2571                             I40E_GLPRT_MPRCL(hw->port),
2572                             pf->offset_loaded, &os->eth.rx_multicast,
2573                             &ns->eth.rx_multicast);
2574         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2575                             I40E_GLPRT_BPRCL(hw->port),
2576                             pf->offset_loaded, &os->eth.rx_broadcast,
2577                             &ns->eth.rx_broadcast);
2578         /* Workaround: CRC size should not be included in byte statistics,
2579          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2580          */
2581         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2582                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2583
2584         /* exclude internal rx bytes
2585          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2586          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2587          * value.
2588          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2589          */
2590         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2591                 ns->eth.rx_bytes = 0;
2592         else
2593                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2594
2595         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2596                 ns->eth.rx_unicast = 0;
2597         else
2598                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2599
2600         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2601                 ns->eth.rx_multicast = 0;
2602         else
2603                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2604
2605         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2606                 ns->eth.rx_broadcast = 0;
2607         else
2608                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2609
2610         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2611                             pf->offset_loaded, &os->eth.rx_discards,
2612                             &ns->eth.rx_discards);
2613         /* GLPRT_REPC not supported */
2614         /* GLPRT_RMPC not supported */
2615         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2616                             pf->offset_loaded,
2617                             &os->eth.rx_unknown_protocol,
2618                             &ns->eth.rx_unknown_protocol);
2619         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2620                             I40E_GLPRT_GOTCL(hw->port),
2621                             pf->offset_loaded, &os->eth.tx_bytes,
2622                             &ns->eth.tx_bytes);
2623         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2624                             I40E_GLPRT_UPTCL(hw->port),
2625                             pf->offset_loaded, &os->eth.tx_unicast,
2626                             &ns->eth.tx_unicast);
2627         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2628                             I40E_GLPRT_MPTCL(hw->port),
2629                             pf->offset_loaded, &os->eth.tx_multicast,
2630                             &ns->eth.tx_multicast);
2631         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2632                             I40E_GLPRT_BPTCL(hw->port),
2633                             pf->offset_loaded, &os->eth.tx_broadcast,
2634                             &ns->eth.tx_broadcast);
2635         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2636                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2637
2638         /* exclude internal tx bytes
2639          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2640          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2641          * value.
2642          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2643          */
2644         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2645                 ns->eth.tx_bytes = 0;
2646         else
2647                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2648
2649         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2650                 ns->eth.tx_unicast = 0;
2651         else
2652                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2653
2654         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2655                 ns->eth.tx_multicast = 0;
2656         else
2657                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2658
2659         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2660                 ns->eth.tx_broadcast = 0;
2661         else
2662                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2663
2664         /* GLPRT_TEPC not supported */
2665
2666         /* additional port specific stats */
2667         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2668                             pf->offset_loaded, &os->tx_dropped_link_down,
2669                             &ns->tx_dropped_link_down);
2670         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2671                             pf->offset_loaded, &os->crc_errors,
2672                             &ns->crc_errors);
2673         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2674                             pf->offset_loaded, &os->illegal_bytes,
2675                             &ns->illegal_bytes);
2676         /* GLPRT_ERRBC not supported */
2677         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2678                             pf->offset_loaded, &os->mac_local_faults,
2679                             &ns->mac_local_faults);
2680         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2681                             pf->offset_loaded, &os->mac_remote_faults,
2682                             &ns->mac_remote_faults);
2683         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2684                             pf->offset_loaded, &os->rx_length_errors,
2685                             &ns->rx_length_errors);
2686         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2687                             pf->offset_loaded, &os->link_xon_rx,
2688                             &ns->link_xon_rx);
2689         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2690                             pf->offset_loaded, &os->link_xoff_rx,
2691                             &ns->link_xoff_rx);
2692         for (i = 0; i < 8; i++) {
2693                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2694                                     pf->offset_loaded,
2695                                     &os->priority_xon_rx[i],
2696                                     &ns->priority_xon_rx[i]);
2697                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2698                                     pf->offset_loaded,
2699                                     &os->priority_xoff_rx[i],
2700                                     &ns->priority_xoff_rx[i]);
2701         }
2702         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2703                             pf->offset_loaded, &os->link_xon_tx,
2704                             &ns->link_xon_tx);
2705         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2706                             pf->offset_loaded, &os->link_xoff_tx,
2707                             &ns->link_xoff_tx);
2708         for (i = 0; i < 8; i++) {
2709                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2710                                     pf->offset_loaded,
2711                                     &os->priority_xon_tx[i],
2712                                     &ns->priority_xon_tx[i]);
2713                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2714                                     pf->offset_loaded,
2715                                     &os->priority_xoff_tx[i],
2716                                     &ns->priority_xoff_tx[i]);
2717                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2718                                     pf->offset_loaded,
2719                                     &os->priority_xon_2_xoff[i],
2720                                     &ns->priority_xon_2_xoff[i]);
2721         }
2722         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2723                             I40E_GLPRT_PRC64L(hw->port),
2724                             pf->offset_loaded, &os->rx_size_64,
2725                             &ns->rx_size_64);
2726         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2727                             I40E_GLPRT_PRC127L(hw->port),
2728                             pf->offset_loaded, &os->rx_size_127,
2729                             &ns->rx_size_127);
2730         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2731                             I40E_GLPRT_PRC255L(hw->port),
2732                             pf->offset_loaded, &os->rx_size_255,
2733                             &ns->rx_size_255);
2734         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2735                             I40E_GLPRT_PRC511L(hw->port),
2736                             pf->offset_loaded, &os->rx_size_511,
2737                             &ns->rx_size_511);
2738         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2739                             I40E_GLPRT_PRC1023L(hw->port),
2740                             pf->offset_loaded, &os->rx_size_1023,
2741                             &ns->rx_size_1023);
2742         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2743                             I40E_GLPRT_PRC1522L(hw->port),
2744                             pf->offset_loaded, &os->rx_size_1522,
2745                             &ns->rx_size_1522);
2746         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2747                             I40E_GLPRT_PRC9522L(hw->port),
2748                             pf->offset_loaded, &os->rx_size_big,
2749                             &ns->rx_size_big);
2750         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2751                             pf->offset_loaded, &os->rx_undersize,
2752                             &ns->rx_undersize);
2753         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2754                             pf->offset_loaded, &os->rx_fragments,
2755                             &ns->rx_fragments);
2756         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2757                             pf->offset_loaded, &os->rx_oversize,
2758                             &ns->rx_oversize);
2759         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2760                             pf->offset_loaded, &os->rx_jabber,
2761                             &ns->rx_jabber);
2762         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2763                             I40E_GLPRT_PTC64L(hw->port),
2764                             pf->offset_loaded, &os->tx_size_64,
2765                             &ns->tx_size_64);
2766         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2767                             I40E_GLPRT_PTC127L(hw->port),
2768                             pf->offset_loaded, &os->tx_size_127,
2769                             &ns->tx_size_127);
2770         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2771                             I40E_GLPRT_PTC255L(hw->port),
2772                             pf->offset_loaded, &os->tx_size_255,
2773                             &ns->tx_size_255);
2774         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2775                             I40E_GLPRT_PTC511L(hw->port),
2776                             pf->offset_loaded, &os->tx_size_511,
2777                             &ns->tx_size_511);
2778         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2779                             I40E_GLPRT_PTC1023L(hw->port),
2780                             pf->offset_loaded, &os->tx_size_1023,
2781                             &ns->tx_size_1023);
2782         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2783                             I40E_GLPRT_PTC1522L(hw->port),
2784                             pf->offset_loaded, &os->tx_size_1522,
2785                             &ns->tx_size_1522);
2786         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2787                             I40E_GLPRT_PTC9522L(hw->port),
2788                             pf->offset_loaded, &os->tx_size_big,
2789                             &ns->tx_size_big);
2790         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2791                            pf->offset_loaded,
2792                            &os->fd_sb_match, &ns->fd_sb_match);
2793         /* GLPRT_MSPDC not supported */
2794         /* GLPRT_XEC not supported */
2795
2796         pf->offset_loaded = true;
2797
2798         if (pf->main_vsi)
2799                 i40e_update_vsi_stats(pf->main_vsi);
2800 }
2801
2802 /* Get all statistics of a port */
2803 static int
2804 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2805 {
2806         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2807         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2809         unsigned i;
2810
2811         /* call read registers - updates values, now write them to struct */
2812         i40e_read_stats_registers(pf, hw);
2813
2814         stats->ipackets = ns->eth.rx_unicast +
2815                         ns->eth.rx_multicast +
2816                         ns->eth.rx_broadcast -
2817                         ns->eth.rx_discards -
2818                         pf->main_vsi->eth_stats.rx_discards;
2819         stats->opackets = ns->eth.tx_unicast +
2820                         ns->eth.tx_multicast +
2821                         ns->eth.tx_broadcast;
2822         stats->ibytes   = ns->eth.rx_bytes;
2823         stats->obytes   = ns->eth.tx_bytes;
2824         stats->oerrors  = ns->eth.tx_errors +
2825                         pf->main_vsi->eth_stats.tx_errors;
2826
2827         /* Rx Errors */
2828         stats->imissed  = ns->eth.rx_discards +
2829                         pf->main_vsi->eth_stats.rx_discards;
2830         stats->ierrors  = ns->crc_errors +
2831                         ns->rx_length_errors + ns->rx_undersize +
2832                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2833
2834         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2835         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2836         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2837         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2838         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2839         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2840         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2841                     ns->eth.rx_unknown_protocol);
2842         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2843         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2844         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2845         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2846         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2847         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2848
2849         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2850                     ns->tx_dropped_link_down);
2851         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2852         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2853                     ns->illegal_bytes);
2854         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2855         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2856                     ns->mac_local_faults);
2857         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2858                     ns->mac_remote_faults);
2859         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2860                     ns->rx_length_errors);
2861         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2862         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2863         for (i = 0; i < 8; i++) {
2864                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2865                                 i, ns->priority_xon_rx[i]);
2866                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2867                                 i, ns->priority_xoff_rx[i]);
2868         }
2869         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2870         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2871         for (i = 0; i < 8; i++) {
2872                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2873                                 i, ns->priority_xon_tx[i]);
2874                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2875                                 i, ns->priority_xoff_tx[i]);
2876                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2877                                 i, ns->priority_xon_2_xoff[i]);
2878         }
2879         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2880         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2881         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2882         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2883         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2884         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2885         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2886         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2887         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2888         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2889         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2890         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2891         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2892         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2893         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2894         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2895         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2896         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2897         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2898                         ns->mac_short_packet_dropped);
2899         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2900                     ns->checksum_error);
2901         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2902         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2903         return 0;
2904 }
2905
2906 /* Reset the statistics */
2907 static void
2908 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2909 {
2910         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2912
2913         /* Mark PF and VSI stats to update the offset, aka "reset" */
2914         pf->offset_loaded = false;
2915         if (pf->main_vsi)
2916                 pf->main_vsi->offset_loaded = false;
2917
2918         /* read the stats, reading current register values into offset */
2919         i40e_read_stats_registers(pf, hw);
2920 }
2921
2922 static uint32_t
2923 i40e_xstats_calc_num(void)
2924 {
2925         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2926                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2927                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2928 }
2929
2930 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2931                                      struct rte_eth_xstat_name *xstats_names,
2932                                      __rte_unused unsigned limit)
2933 {
2934         unsigned count = 0;
2935         unsigned i, prio;
2936
2937         if (xstats_names == NULL)
2938                 return i40e_xstats_calc_num();
2939
2940         /* Note: limit checked in rte_eth_xstats_names() */
2941
2942         /* Get stats from i40e_eth_stats struct */
2943         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2944                 snprintf(xstats_names[count].name,
2945                          sizeof(xstats_names[count].name),
2946                          "%s", rte_i40e_stats_strings[i].name);
2947                 count++;
2948         }
2949
2950         /* Get individiual stats from i40e_hw_port struct */
2951         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2952                 snprintf(xstats_names[count].name,
2953                         sizeof(xstats_names[count].name),
2954                          "%s", rte_i40e_hw_port_strings[i].name);
2955                 count++;
2956         }
2957
2958         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2959                 for (prio = 0; prio < 8; prio++) {
2960                         snprintf(xstats_names[count].name,
2961                                  sizeof(xstats_names[count].name),
2962                                  "rx_priority%u_%s", prio,
2963                                  rte_i40e_rxq_prio_strings[i].name);
2964                         count++;
2965                 }
2966         }
2967
2968         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2969                 for (prio = 0; prio < 8; prio++) {
2970                         snprintf(xstats_names[count].name,
2971                                  sizeof(xstats_names[count].name),
2972                                  "tx_priority%u_%s", prio,
2973                                  rte_i40e_txq_prio_strings[i].name);
2974                         count++;
2975                 }
2976         }
2977         return count;
2978 }
2979
2980 static int
2981 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2982                     unsigned n)
2983 {
2984         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2985         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986         unsigned i, count, prio;
2987         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2988
2989         count = i40e_xstats_calc_num();
2990         if (n < count)
2991                 return count;
2992
2993         i40e_read_stats_registers(pf, hw);
2994
2995         if (xstats == NULL)
2996                 return 0;
2997
2998         count = 0;
2999
3000         /* Get stats from i40e_eth_stats struct */
3001         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3002                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3003                         rte_i40e_stats_strings[i].offset);
3004                 xstats[count].id = count;
3005                 count++;
3006         }
3007
3008         /* Get individiual stats from i40e_hw_port struct */
3009         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3010                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3011                         rte_i40e_hw_port_strings[i].offset);
3012                 xstats[count].id = count;
3013                 count++;
3014         }
3015
3016         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3017                 for (prio = 0; prio < 8; prio++) {
3018                         xstats[count].value =
3019                                 *(uint64_t *)(((char *)hw_stats) +
3020                                 rte_i40e_rxq_prio_strings[i].offset +
3021                                 (sizeof(uint64_t) * prio));
3022                         xstats[count].id = count;
3023                         count++;
3024                 }
3025         }
3026
3027         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3028                 for (prio = 0; prio < 8; prio++) {
3029                         xstats[count].value =
3030                                 *(uint64_t *)(((char *)hw_stats) +
3031                                 rte_i40e_txq_prio_strings[i].offset +
3032                                 (sizeof(uint64_t) * prio));
3033                         xstats[count].id = count;
3034                         count++;
3035                 }
3036         }
3037
3038         return count;
3039 }
3040
3041 static int
3042 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3043                                  __rte_unused uint16_t queue_id,
3044                                  __rte_unused uint8_t stat_idx,
3045                                  __rte_unused uint8_t is_rx)
3046 {
3047         PMD_INIT_FUNC_TRACE();
3048
3049         return -ENOSYS;
3050 }
3051
3052 static int
3053 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3054 {
3055         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3056         u32 full_ver;
3057         u8 ver, patch;
3058         u16 build;
3059         int ret;
3060
3061         full_ver = hw->nvm.oem_ver;
3062         ver = (u8)(full_ver >> 24);
3063         build = (u16)((full_ver >> 8) & 0xffff);
3064         patch = (u8)(full_ver & 0xff);
3065
3066         ret = snprintf(fw_version, fw_size,
3067                  "%d.%d%d 0x%08x %d.%d.%d",
3068                  ((hw->nvm.version >> 12) & 0xf),
3069                  ((hw->nvm.version >> 4) & 0xff),
3070                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3071                  ver, build, patch);
3072
3073         ret += 1; /* add the size of '\0' */
3074         if (fw_size < (u32)ret)
3075                 return ret;
3076         else
3077                 return 0;
3078 }
3079
3080 static void
3081 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3082 {
3083         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3085         struct i40e_vsi *vsi = pf->main_vsi;
3086         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3087
3088         dev_info->pci_dev = pci_dev;
3089         dev_info->max_rx_queues = vsi->nb_qps;
3090         dev_info->max_tx_queues = vsi->nb_qps;
3091         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3092         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3093         dev_info->max_mac_addrs = vsi->max_macaddrs;
3094         dev_info->max_vfs = pci_dev->max_vfs;
3095         dev_info->rx_offload_capa =
3096                 DEV_RX_OFFLOAD_VLAN_STRIP |
3097                 DEV_RX_OFFLOAD_QINQ_STRIP |
3098                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3099                 DEV_RX_OFFLOAD_UDP_CKSUM |
3100                 DEV_RX_OFFLOAD_TCP_CKSUM |
3101                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3102                 DEV_RX_OFFLOAD_CRC_STRIP;
3103         dev_info->tx_offload_capa =
3104                 DEV_TX_OFFLOAD_VLAN_INSERT |
3105                 DEV_TX_OFFLOAD_QINQ_INSERT |
3106                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3107                 DEV_TX_OFFLOAD_UDP_CKSUM |
3108                 DEV_TX_OFFLOAD_TCP_CKSUM |
3109                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3110                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3111                 DEV_TX_OFFLOAD_TCP_TSO |
3112                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3113                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3114                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3115                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3116         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3117                                                 sizeof(uint32_t);
3118         dev_info->reta_size = pf->hash_lut_size;
3119         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3120
3121         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3122                 .rx_thresh = {
3123                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3124                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3125                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3126                 },
3127                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3128                 .rx_drop_en = 0,
3129         };
3130
3131         dev_info->default_txconf = (struct rte_eth_txconf) {
3132                 .tx_thresh = {
3133                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3134                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3135                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3136                 },
3137                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3138                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3139                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3140                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3141         };
3142
3143         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3144                 .nb_max = I40E_MAX_RING_DESC,
3145                 .nb_min = I40E_MIN_RING_DESC,
3146                 .nb_align = I40E_ALIGN_RING_DESC,
3147         };
3148
3149         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3150                 .nb_max = I40E_MAX_RING_DESC,
3151                 .nb_min = I40E_MIN_RING_DESC,
3152                 .nb_align = I40E_ALIGN_RING_DESC,
3153                 .nb_seg_max = I40E_TX_MAX_SEG,
3154                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3155         };
3156
3157         if (pf->flags & I40E_FLAG_VMDQ) {
3158                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3159                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3160                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3161                                                 pf->max_nb_vmdq_vsi;
3162                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3163                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3164                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3165         }
3166
3167         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3168                 /* For XL710 */
3169                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3170         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3171                 /* For XXV710 */
3172                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3173         else
3174                 /* For X710 */
3175                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3176 }
3177
3178 static int
3179 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3180 {
3181         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3182         struct i40e_vsi *vsi = pf->main_vsi;
3183         PMD_INIT_FUNC_TRACE();
3184
3185         if (on)
3186                 return i40e_vsi_add_vlan(vsi, vlan_id);
3187         else
3188                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3189 }
3190
3191 static int
3192 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3193                                 enum rte_vlan_type vlan_type,
3194                                 uint16_t tpid, int qinq)
3195 {
3196         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3197         uint64_t reg_r = 0;
3198         uint64_t reg_w = 0;
3199         uint16_t reg_id = 3;
3200         int ret;
3201
3202         if (qinq) {
3203                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3204                         reg_id = 2;
3205         }
3206
3207         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3208                                           &reg_r, NULL);
3209         if (ret != I40E_SUCCESS) {
3210                 PMD_DRV_LOG(ERR,
3211                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3212                            reg_id);
3213                 return -EIO;
3214         }
3215         PMD_DRV_LOG(DEBUG,
3216                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3217                     reg_id, reg_r);
3218
3219         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3220         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3221         if (reg_r == reg_w) {
3222                 PMD_DRV_LOG(DEBUG, "No need to write");
3223                 return 0;
3224         }
3225
3226         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3227                                            reg_w, NULL);
3228         if (ret != I40E_SUCCESS) {
3229                 PMD_DRV_LOG(ERR,
3230                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3231                             reg_id);
3232                 return -EIO;
3233         }
3234         PMD_DRV_LOG(DEBUG,
3235                     "Global register 0x%08x is changed with value 0x%08x",
3236                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3237
3238         return 0;
3239 }
3240
3241 static int
3242 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3243                    enum rte_vlan_type vlan_type,
3244                    uint16_t tpid)
3245 {
3246         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3247         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3248         int ret = 0;
3249
3250         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3251              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3252             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3253                 PMD_DRV_LOG(ERR,
3254                             "Unsupported vlan type.");
3255                 return -EINVAL;
3256         }
3257         /* 802.1ad frames ability is added in NVM API 1.7*/
3258         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3259                 if (qinq) {
3260                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3261                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3262                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3263                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3264                 } else {
3265                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3266                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3267                 }
3268                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3269                 if (ret != I40E_SUCCESS) {
3270                         PMD_DRV_LOG(ERR,
3271                                     "Set switch config failed aq_err: %d",
3272                                     hw->aq.asq_last_status);
3273                         ret = -EIO;
3274                 }
3275         } else
3276                 /* If NVM API < 1.7, keep the register setting */
3277                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3278                                                       tpid, qinq);
3279         i40e_global_cfg_warning(I40E_WARNING_TPID);
3280
3281         return ret;
3282 }
3283
3284 static int
3285 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3286 {
3287         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3288         struct i40e_vsi *vsi = pf->main_vsi;
3289
3290         if (mask & ETH_VLAN_FILTER_MASK) {
3291                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3292                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3293                 else
3294                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3295         }
3296
3297         if (mask & ETH_VLAN_STRIP_MASK) {
3298                 /* Enable or disable VLAN stripping */
3299                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3300                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3301                 else
3302                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3303         }
3304
3305         if (mask & ETH_VLAN_EXTEND_MASK) {
3306                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3307                         i40e_vsi_config_double_vlan(vsi, TRUE);
3308                         /* Set global registers with default ethertype. */
3309                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3310                                            ETHER_TYPE_VLAN);
3311                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3312                                            ETHER_TYPE_VLAN);
3313                 }
3314                 else
3315                         i40e_vsi_config_double_vlan(vsi, FALSE);
3316         }
3317
3318         return 0;
3319 }
3320
3321 static void
3322 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3323                           __rte_unused uint16_t queue,
3324                           __rte_unused int on)
3325 {
3326         PMD_INIT_FUNC_TRACE();
3327 }
3328
3329 static int
3330 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3331 {
3332         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3333         struct i40e_vsi *vsi = pf->main_vsi;
3334         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3335         struct i40e_vsi_vlan_pvid_info info;
3336
3337         memset(&info, 0, sizeof(info));
3338         info.on = on;
3339         if (info.on)
3340                 info.config.pvid = pvid;
3341         else {
3342                 info.config.reject.tagged =
3343                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3344                 info.config.reject.untagged =
3345                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3346         }
3347
3348         return i40e_vsi_vlan_pvid_set(vsi, &info);
3349 }
3350
3351 static int
3352 i40e_dev_led_on(struct rte_eth_dev *dev)
3353 {
3354         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3355         uint32_t mode = i40e_led_get(hw);
3356
3357         if (mode == 0)
3358                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3359
3360         return 0;
3361 }
3362
3363 static int
3364 i40e_dev_led_off(struct rte_eth_dev *dev)
3365 {
3366         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3367         uint32_t mode = i40e_led_get(hw);
3368
3369         if (mode != 0)
3370                 i40e_led_set(hw, 0, false);
3371
3372         return 0;
3373 }
3374
3375 static int
3376 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3377 {
3378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3379         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3380
3381         fc_conf->pause_time = pf->fc_conf.pause_time;
3382
3383         /* read out from register, in case they are modified by other port */
3384         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3385                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3386         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3387                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3388
3389         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3390         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3391
3392          /* Return current mode according to actual setting*/
3393         switch (hw->fc.current_mode) {
3394         case I40E_FC_FULL:
3395                 fc_conf->mode = RTE_FC_FULL;
3396                 break;
3397         case I40E_FC_TX_PAUSE:
3398                 fc_conf->mode = RTE_FC_TX_PAUSE;
3399                 break;
3400         case I40E_FC_RX_PAUSE:
3401                 fc_conf->mode = RTE_FC_RX_PAUSE;
3402                 break;
3403         case I40E_FC_NONE:
3404         default:
3405                 fc_conf->mode = RTE_FC_NONE;
3406         };
3407
3408         return 0;
3409 }
3410
3411 static int
3412 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3413 {
3414         uint32_t mflcn_reg, fctrl_reg, reg;
3415         uint32_t max_high_water;
3416         uint8_t i, aq_failure;
3417         int err;
3418         struct i40e_hw *hw;
3419         struct i40e_pf *pf;
3420         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3421                 [RTE_FC_NONE] = I40E_FC_NONE,
3422                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3423                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3424                 [RTE_FC_FULL] = I40E_FC_FULL
3425         };
3426
3427         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3428
3429         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3430         if ((fc_conf->high_water > max_high_water) ||
3431                         (fc_conf->high_water < fc_conf->low_water)) {
3432                 PMD_INIT_LOG(ERR,
3433                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3434                         max_high_water);
3435                 return -EINVAL;
3436         }
3437
3438         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3440         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3441
3442         pf->fc_conf.pause_time = fc_conf->pause_time;
3443         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3444         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3445
3446         PMD_INIT_FUNC_TRACE();
3447
3448         /* All the link flow control related enable/disable register
3449          * configuration is handle by the F/W
3450          */
3451         err = i40e_set_fc(hw, &aq_failure, true);
3452         if (err < 0)
3453                 return -ENOSYS;
3454
3455         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3456                 /* Configure flow control refresh threshold,
3457                  * the value for stat_tx_pause_refresh_timer[8]
3458                  * is used for global pause operation.
3459                  */
3460
3461                 I40E_WRITE_REG(hw,
3462                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3463                                pf->fc_conf.pause_time);
3464
3465                 /* configure the timer value included in transmitted pause
3466                  * frame,
3467                  * the value for stat_tx_pause_quanta[8] is used for global
3468                  * pause operation
3469                  */
3470                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3471                                pf->fc_conf.pause_time);
3472
3473                 fctrl_reg = I40E_READ_REG(hw,
3474                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3475
3476                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3477                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3478                 else
3479                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3480
3481                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3482                                fctrl_reg);
3483         } else {
3484                 /* Configure pause time (2 TCs per register) */
3485                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3486                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3487                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3488
3489                 /* Configure flow control refresh threshold value */
3490                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3491                                pf->fc_conf.pause_time / 2);
3492
3493                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3494
3495                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3496                  *depending on configuration
3497                  */
3498                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3499                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3500                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3501                 } else {
3502                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3503                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3504                 }
3505
3506                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3507         }
3508
3509         /* config the water marker both based on the packets and bytes */
3510         I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3511                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3512                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3513         I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3514                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3515                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3516         I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3517                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3518                        << I40E_KILOSHIFT);
3519         I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3520                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3521                        << I40E_KILOSHIFT);
3522         i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3523
3524         I40E_WRITE_FLUSH(hw);
3525
3526         return 0;
3527 }
3528
3529 static int
3530 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3531                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3532 {
3533         PMD_INIT_FUNC_TRACE();
3534
3535         return -ENOSYS;
3536 }
3537
3538 /* Add a MAC address, and update filters */
3539 static int
3540 i40e_macaddr_add(struct rte_eth_dev *dev,
3541                  struct ether_addr *mac_addr,
3542                  __rte_unused uint32_t index,
3543                  uint32_t pool)
3544 {
3545         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3546         struct i40e_mac_filter_info mac_filter;
3547         struct i40e_vsi *vsi;
3548         int ret;
3549
3550         /* If VMDQ not enabled or configured, return */
3551         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3552                           !pf->nb_cfg_vmdq_vsi)) {
3553                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3554                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3555                         pool);
3556                 return -ENOTSUP;
3557         }
3558
3559         if (pool > pf->nb_cfg_vmdq_vsi) {
3560                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3561                                 pool, pf->nb_cfg_vmdq_vsi);
3562                 return -EINVAL;
3563         }
3564
3565         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3566         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3567                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3568         else
3569                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3570
3571         if (pool == 0)
3572                 vsi = pf->main_vsi;
3573         else
3574                 vsi = pf->vmdq[pool - 1].vsi;
3575
3576         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3577         if (ret != I40E_SUCCESS) {
3578                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3579                 return -ENODEV;
3580         }
3581         return 0;
3582 }
3583
3584 /* Remove a MAC address, and update filters */
3585 static void
3586 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3587 {
3588         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3589         struct i40e_vsi *vsi;
3590         struct rte_eth_dev_data *data = dev->data;
3591         struct ether_addr *macaddr;
3592         int ret;
3593         uint32_t i;
3594         uint64_t pool_sel;
3595
3596         macaddr = &(data->mac_addrs[index]);
3597
3598         pool_sel = dev->data->mac_pool_sel[index];
3599
3600         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3601                 if (pool_sel & (1ULL << i)) {
3602                         if (i == 0)
3603                                 vsi = pf->main_vsi;
3604                         else {
3605                                 /* No VMDQ pool enabled or configured */
3606                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3607                                         (i > pf->nb_cfg_vmdq_vsi)) {
3608                                         PMD_DRV_LOG(ERR,
3609                                                 "No VMDQ pool enabled/configured");
3610                                         return;
3611                                 }
3612                                 vsi = pf->vmdq[i - 1].vsi;
3613                         }
3614                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3615
3616                         if (ret) {
3617                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3618                                 return;
3619                         }
3620                 }
3621         }
3622 }
3623
3624 /* Set perfect match or hash match of MAC and VLAN for a VF */
3625 static int
3626 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3627                  struct rte_eth_mac_filter *filter,
3628                  bool add)
3629 {
3630         struct i40e_hw *hw;
3631         struct i40e_mac_filter_info mac_filter;
3632         struct ether_addr old_mac;
3633         struct ether_addr *new_mac;
3634         struct i40e_pf_vf *vf = NULL;
3635         uint16_t vf_id;
3636         int ret;
3637
3638         if (pf == NULL) {
3639                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3640                 return -EINVAL;
3641         }
3642         hw = I40E_PF_TO_HW(pf);
3643
3644         if (filter == NULL) {
3645                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3646                 return -EINVAL;
3647         }
3648
3649         new_mac = &filter->mac_addr;
3650
3651         if (is_zero_ether_addr(new_mac)) {
3652                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3653                 return -EINVAL;
3654         }
3655
3656         vf_id = filter->dst_id;
3657
3658         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3659                 PMD_DRV_LOG(ERR, "Invalid argument.");
3660                 return -EINVAL;
3661         }
3662         vf = &pf->vfs[vf_id];
3663
3664         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3665                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3666                 return -EINVAL;
3667         }
3668
3669         if (add) {
3670                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3671                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3672                                 ETHER_ADDR_LEN);
3673                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3674                                  ETHER_ADDR_LEN);
3675
3676                 mac_filter.filter_type = filter->filter_type;
3677                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3678                 if (ret != I40E_SUCCESS) {
3679                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3680                         return -1;
3681                 }
3682                 ether_addr_copy(new_mac, &pf->dev_addr);
3683         } else {
3684                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3685                                 ETHER_ADDR_LEN);
3686                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3687                 if (ret != I40E_SUCCESS) {
3688                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3689                         return -1;
3690                 }
3691
3692                 /* Clear device address as it has been removed */
3693                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3694                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3695         }
3696
3697         return 0;
3698 }
3699
3700 /* MAC filter handle */
3701 static int
3702 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3703                 void *arg)
3704 {
3705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3706         struct rte_eth_mac_filter *filter;
3707         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3708         int ret = I40E_NOT_SUPPORTED;
3709
3710         filter = (struct rte_eth_mac_filter *)(arg);
3711
3712         switch (filter_op) {
3713         case RTE_ETH_FILTER_NOP:
3714                 ret = I40E_SUCCESS;
3715                 break;
3716         case RTE_ETH_FILTER_ADD:
3717                 i40e_pf_disable_irq0(hw);
3718                 if (filter->is_vf)
3719                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3720                 i40e_pf_enable_irq0(hw);
3721                 break;
3722         case RTE_ETH_FILTER_DELETE:
3723                 i40e_pf_disable_irq0(hw);
3724                 if (filter->is_vf)
3725                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3726                 i40e_pf_enable_irq0(hw);
3727                 break;
3728         default:
3729                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3730                 ret = I40E_ERR_PARAM;
3731                 break;
3732         }
3733
3734         return ret;
3735 }
3736
3737 static int
3738 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3739 {
3740         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3741         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3742         uint32_t reg;
3743         int ret;
3744
3745         if (!lut)
3746                 return -EINVAL;
3747
3748         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3749                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3750                                           lut, lut_size);
3751                 if (ret) {
3752                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3753                         return ret;
3754                 }
3755         } else {
3756                 uint32_t *lut_dw = (uint32_t *)lut;
3757                 uint16_t i, lut_size_dw = lut_size / 4;
3758
3759                 if (vsi->type == I40E_VSI_SRIOV) {
3760                         for (i = 0; i <= lut_size_dw; i++) {
3761                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3762                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3763                         }
3764                 } else {
3765                         for (i = 0; i < lut_size_dw; i++)
3766                                 lut_dw[i] = I40E_READ_REG(hw,
3767                                                           I40E_PFQF_HLUT(i));
3768                 }
3769         }
3770
3771         return 0;
3772 }
3773
3774 int
3775 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3776 {
3777         struct i40e_pf *pf;
3778         struct i40e_hw *hw;
3779         int ret;
3780
3781         if (!vsi || !lut)
3782                 return -EINVAL;
3783
3784         pf = I40E_VSI_TO_PF(vsi);
3785         hw = I40E_VSI_TO_HW(vsi);
3786
3787         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3788                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3789                                           lut, lut_size);
3790                 if (ret) {
3791                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3792                         return ret;
3793                 }
3794         } else {
3795                 uint32_t *lut_dw = (uint32_t *)lut;
3796                 uint16_t i, lut_size_dw = lut_size / 4;
3797
3798                 if (vsi->type == I40E_VSI_SRIOV) {
3799                         for (i = 0; i < lut_size_dw; i++)
3800                                 I40E_WRITE_REG(
3801                                         hw,
3802                                         I40E_VFQF_HLUT1(i, vsi->user_param),
3803                                         lut_dw[i]);
3804                 } else {
3805                         for (i = 0; i < lut_size_dw; i++)
3806                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3807                                                lut_dw[i]);
3808                 }
3809                 I40E_WRITE_FLUSH(hw);
3810         }
3811
3812         return 0;
3813 }
3814
3815 static int
3816 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3817                          struct rte_eth_rss_reta_entry64 *reta_conf,
3818                          uint16_t reta_size)
3819 {
3820         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3821         uint16_t i, lut_size = pf->hash_lut_size;
3822         uint16_t idx, shift;
3823         uint8_t *lut;
3824         int ret;
3825
3826         if (reta_size != lut_size ||
3827                 reta_size > ETH_RSS_RETA_SIZE_512) {
3828                 PMD_DRV_LOG(ERR,
3829                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3830                         reta_size, lut_size);
3831                 return -EINVAL;
3832         }
3833
3834         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3835         if (!lut) {
3836                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3837                 return -ENOMEM;
3838         }
3839         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3840         if (ret)
3841                 goto out;
3842         for (i = 0; i < reta_size; i++) {
3843                 idx = i / RTE_RETA_GROUP_SIZE;
3844                 shift = i % RTE_RETA_GROUP_SIZE;
3845                 if (reta_conf[idx].mask & (1ULL << shift))
3846                         lut[i] = reta_conf[idx].reta[shift];
3847         }
3848         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3849
3850 out:
3851         rte_free(lut);
3852
3853         return ret;
3854 }
3855
3856 static int
3857 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3858                         struct rte_eth_rss_reta_entry64 *reta_conf,
3859                         uint16_t reta_size)
3860 {
3861         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3862         uint16_t i, lut_size = pf->hash_lut_size;
3863         uint16_t idx, shift;
3864         uint8_t *lut;
3865         int ret;
3866
3867         if (reta_size != lut_size ||
3868                 reta_size > ETH_RSS_RETA_SIZE_512) {
3869                 PMD_DRV_LOG(ERR,
3870                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3871                         reta_size, lut_size);
3872                 return -EINVAL;
3873         }
3874
3875         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3876         if (!lut) {
3877                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3878                 return -ENOMEM;
3879         }
3880
3881         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3882         if (ret)
3883                 goto out;
3884         for (i = 0; i < reta_size; i++) {
3885                 idx = i / RTE_RETA_GROUP_SIZE;
3886                 shift = i % RTE_RETA_GROUP_SIZE;
3887                 if (reta_conf[idx].mask & (1ULL << shift))
3888                         reta_conf[idx].reta[shift] = lut[i];
3889         }
3890
3891 out:
3892         rte_free(lut);
3893
3894         return ret;
3895 }
3896
3897 /**
3898  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3899  * @hw:   pointer to the HW structure
3900  * @mem:  pointer to mem struct to fill out
3901  * @size: size of memory requested
3902  * @alignment: what to align the allocation to
3903  **/
3904 enum i40e_status_code
3905 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3906                         struct i40e_dma_mem *mem,
3907                         u64 size,
3908                         u32 alignment)
3909 {
3910         const struct rte_memzone *mz = NULL;
3911         char z_name[RTE_MEMZONE_NAMESIZE];
3912
3913         if (!mem)
3914                 return I40E_ERR_PARAM;
3915
3916         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3917         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3918                                          alignment, RTE_PGSIZE_2M);
3919         if (!mz)
3920                 return I40E_ERR_NO_MEMORY;
3921
3922         mem->size = size;
3923         mem->va = mz->addr;
3924         mem->pa = mz->iova;
3925         mem->zone = (const void *)mz;
3926         PMD_DRV_LOG(DEBUG,
3927                 "memzone %s allocated with physical address: %"PRIu64,
3928                 mz->name, mem->pa);
3929
3930         return I40E_SUCCESS;
3931 }
3932
3933 /**
3934  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3935  * @hw:   pointer to the HW structure
3936  * @mem:  ptr to mem struct to free
3937  **/
3938 enum i40e_status_code
3939 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3940                     struct i40e_dma_mem *mem)
3941 {
3942         if (!mem)
3943                 return I40E_ERR_PARAM;
3944
3945         PMD_DRV_LOG(DEBUG,
3946                 "memzone %s to be freed with physical address: %"PRIu64,
3947                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3948         rte_memzone_free((const struct rte_memzone *)mem->zone);
3949         mem->zone = NULL;
3950         mem->va = NULL;
3951         mem->pa = (u64)0;
3952
3953         return I40E_SUCCESS;
3954 }
3955
3956 /**
3957  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3958  * @hw:   pointer to the HW structure
3959  * @mem:  pointer to mem struct to fill out
3960  * @size: size of memory requested
3961  **/
3962 enum i40e_status_code
3963 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3964                          struct i40e_virt_mem *mem,
3965                          u32 size)
3966 {
3967         if (!mem)
3968                 return I40E_ERR_PARAM;
3969
3970         mem->size = size;
3971         mem->va = rte_zmalloc("i40e", size, 0);
3972
3973         if (mem->va)
3974                 return I40E_SUCCESS;
3975         else
3976                 return I40E_ERR_NO_MEMORY;
3977 }
3978
3979 /**
3980  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3981  * @hw:   pointer to the HW structure
3982  * @mem:  pointer to mem struct to free
3983  **/
3984 enum i40e_status_code
3985 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3986                      struct i40e_virt_mem *mem)
3987 {
3988         if (!mem)
3989                 return I40E_ERR_PARAM;
3990
3991         rte_free(mem->va);
3992         mem->va = NULL;
3993
3994         return I40E_SUCCESS;
3995 }
3996
3997 void
3998 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3999 {
4000         rte_spinlock_init(&sp->spinlock);
4001 }
4002
4003 void
4004 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4005 {
4006         rte_spinlock_lock(&sp->spinlock);
4007 }
4008
4009 void
4010 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4011 {
4012         rte_spinlock_unlock(&sp->spinlock);
4013 }
4014
4015 void
4016 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4017 {
4018         return;
4019 }
4020
4021 /**
4022  * Get the hardware capabilities, which will be parsed
4023  * and saved into struct i40e_hw.
4024  */
4025 static int
4026 i40e_get_cap(struct i40e_hw *hw)
4027 {
4028         struct i40e_aqc_list_capabilities_element_resp *buf;
4029         uint16_t len, size = 0;
4030         int ret;
4031
4032         /* Calculate a huge enough buff for saving response data temporarily */
4033         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4034                                                 I40E_MAX_CAP_ELE_NUM;
4035         buf = rte_zmalloc("i40e", len, 0);
4036         if (!buf) {
4037                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4038                 return I40E_ERR_NO_MEMORY;
4039         }
4040
4041         /* Get, parse the capabilities and save it to hw */
4042         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4043                         i40e_aqc_opc_list_func_capabilities, NULL);
4044         if (ret != I40E_SUCCESS)
4045                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4046
4047         /* Free the temporary buffer after being used */
4048         rte_free(buf);
4049
4050         return ret;
4051 }
4052
4053 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4054 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4055 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16");
4056
4057 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4058                 const char *value,
4059                 void *opaque)
4060 {
4061         struct i40e_pf *pf;
4062         unsigned long num;
4063         char *end;
4064
4065         pf = (struct i40e_pf *)opaque;
4066         RTE_SET_USED(key);
4067
4068         errno = 0;
4069         num = strtoul(value, &end, 0);
4070         if (errno != 0 || end == value || *end != 0) {
4071                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4072                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4073                 return -(EINVAL);
4074         }
4075
4076         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4077                 pf->vf_nb_qp_max = (uint16_t)num;
4078         else
4079                 /* here return 0 to make next valid same argument work */
4080                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4081                             "power of 2 and equal or less than 16 !, Now it is "
4082                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4083
4084         return 0;
4085 }
4086
4087 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4088 {
4089         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4090         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4091         struct rte_kvargs *kvlist;
4092
4093         /* set default queue number per VF as 4 */
4094         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4095
4096         if (dev->device->devargs == NULL)
4097                 return 0;
4098
4099         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4100         if (kvlist == NULL)
4101                 return -(EINVAL);
4102
4103         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4104                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4105                             "the first invalid or last valid one is used !",
4106                             QUEUE_NUM_PER_VF_ARG);
4107
4108         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4109                            i40e_pf_parse_vf_queue_number_handler, pf);
4110
4111         rte_kvargs_free(kvlist);
4112
4113         return 0;
4114 }
4115
4116 static int
4117 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4118 {
4119         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4120         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4121         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4122         uint16_t qp_count = 0, vsi_count = 0;
4123
4124         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4125                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4126                 return -EINVAL;
4127         }
4128
4129         i40e_pf_config_vf_rxq_number(dev);
4130
4131         /* Add the parameter init for LFC */
4132         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4133         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4134         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4135
4136         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4137         pf->max_num_vsi = hw->func_caps.num_vsis;
4138         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4139         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4140
4141         /* FDir queue/VSI allocation */
4142         pf->fdir_qp_offset = 0;
4143         if (hw->func_caps.fd) {
4144                 pf->flags |= I40E_FLAG_FDIR;
4145                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4146         } else {
4147                 pf->fdir_nb_qps = 0;
4148         }
4149         qp_count += pf->fdir_nb_qps;
4150         vsi_count += 1;
4151
4152         /* LAN queue/VSI allocation */
4153         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4154         if (!hw->func_caps.rss) {
4155                 pf->lan_nb_qps = 1;
4156         } else {
4157                 pf->flags |= I40E_FLAG_RSS;
4158                 if (hw->mac.type == I40E_MAC_X722)
4159                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4160                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4161         }
4162         qp_count += pf->lan_nb_qps;
4163         vsi_count += 1;
4164
4165         /* VF queue/VSI allocation */
4166         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4167         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4168                 pf->flags |= I40E_FLAG_SRIOV;
4169                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4170                 pf->vf_num = pci_dev->max_vfs;
4171                 PMD_DRV_LOG(DEBUG,
4172                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4173                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4174         } else {
4175                 pf->vf_nb_qps = 0;
4176                 pf->vf_num = 0;
4177         }
4178         qp_count += pf->vf_nb_qps * pf->vf_num;
4179         vsi_count += pf->vf_num;
4180
4181         /* VMDq queue/VSI allocation */
4182         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4183         pf->vmdq_nb_qps = 0;
4184         pf->max_nb_vmdq_vsi = 0;
4185         if (hw->func_caps.vmdq) {
4186                 if (qp_count < hw->func_caps.num_tx_qp &&
4187                         vsi_count < hw->func_caps.num_vsis) {
4188                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4189                                 qp_count) / pf->vmdq_nb_qp_max;
4190
4191                         /* Limit the maximum number of VMDq vsi to the maximum
4192                          * ethdev can support
4193                          */
4194                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4195                                 hw->func_caps.num_vsis - vsi_count);
4196                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4197                                 ETH_64_POOLS);
4198                         if (pf->max_nb_vmdq_vsi) {
4199                                 pf->flags |= I40E_FLAG_VMDQ;
4200                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4201                                 PMD_DRV_LOG(DEBUG,
4202                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4203                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4204                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4205                         } else {
4206                                 PMD_DRV_LOG(INFO,
4207                                         "No enough queues left for VMDq");
4208                         }
4209                 } else {
4210                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4211                 }
4212         }
4213         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4214         vsi_count += pf->max_nb_vmdq_vsi;
4215
4216         if (hw->func_caps.dcb)
4217                 pf->flags |= I40E_FLAG_DCB;
4218
4219         if (qp_count > hw->func_caps.num_tx_qp) {
4220                 PMD_DRV_LOG(ERR,
4221                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4222                         qp_count, hw->func_caps.num_tx_qp);
4223                 return -EINVAL;
4224         }
4225         if (vsi_count > hw->func_caps.num_vsis) {
4226                 PMD_DRV_LOG(ERR,
4227                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4228                         vsi_count, hw->func_caps.num_vsis);
4229                 return -EINVAL;
4230         }
4231
4232         return 0;
4233 }
4234
4235 static int
4236 i40e_pf_get_switch_config(struct i40e_pf *pf)
4237 {
4238         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4239         struct i40e_aqc_get_switch_config_resp *switch_config;
4240         struct i40e_aqc_switch_config_element_resp *element;
4241         uint16_t start_seid = 0, num_reported;
4242         int ret;
4243
4244         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4245                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4246         if (!switch_config) {
4247                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4248                 return -ENOMEM;
4249         }
4250
4251         /* Get the switch configurations */
4252         ret = i40e_aq_get_switch_config(hw, switch_config,
4253                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4254         if (ret != I40E_SUCCESS) {
4255                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4256                 goto fail;
4257         }
4258         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4259         if (num_reported != 1) { /* The number should be 1 */
4260                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4261                 goto fail;
4262         }
4263
4264         /* Parse the switch configuration elements */
4265         element = &(switch_config->element[0]);
4266         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4267                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4268                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4269         } else
4270                 PMD_DRV_LOG(INFO, "Unknown element type");
4271
4272 fail:
4273         rte_free(switch_config);
4274
4275         return ret;
4276 }
4277
4278 static int
4279 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4280                         uint32_t num)
4281 {
4282         struct pool_entry *entry;
4283
4284         if (pool == NULL || num == 0)
4285                 return -EINVAL;
4286
4287         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4288         if (entry == NULL) {
4289                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4290                 return -ENOMEM;
4291         }
4292
4293         /* queue heap initialize */
4294         pool->num_free = num;
4295         pool->num_alloc = 0;
4296         pool->base = base;
4297         LIST_INIT(&pool->alloc_list);
4298         LIST_INIT(&pool->free_list);
4299
4300         /* Initialize element  */
4301         entry->base = 0;
4302         entry->len = num;
4303
4304         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4305         return 0;
4306 }
4307
4308 static void
4309 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4310 {
4311         struct pool_entry *entry, *next_entry;
4312
4313         if (pool == NULL)
4314                 return;
4315
4316         for (entry = LIST_FIRST(&pool->alloc_list);
4317                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4318                         entry = next_entry) {
4319                 LIST_REMOVE(entry, next);
4320                 rte_free(entry);
4321         }
4322
4323         for (entry = LIST_FIRST(&pool->free_list);
4324                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4325                         entry = next_entry) {
4326                 LIST_REMOVE(entry, next);
4327                 rte_free(entry);
4328         }
4329
4330         pool->num_free = 0;
4331         pool->num_alloc = 0;
4332         pool->base = 0;
4333         LIST_INIT(&pool->alloc_list);
4334         LIST_INIT(&pool->free_list);
4335 }
4336
4337 static int
4338 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4339                        uint32_t base)
4340 {
4341         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4342         uint32_t pool_offset;
4343         int insert;
4344
4345         if (pool == NULL) {
4346                 PMD_DRV_LOG(ERR, "Invalid parameter");
4347                 return -EINVAL;
4348         }
4349
4350         pool_offset = base - pool->base;
4351         /* Lookup in alloc list */
4352         LIST_FOREACH(entry, &pool->alloc_list, next) {
4353                 if (entry->base == pool_offset) {
4354                         valid_entry = entry;
4355                         LIST_REMOVE(entry, next);
4356                         break;
4357                 }
4358         }
4359
4360         /* Not find, return */
4361         if (valid_entry == NULL) {
4362                 PMD_DRV_LOG(ERR, "Failed to find entry");
4363                 return -EINVAL;
4364         }
4365
4366         /**
4367          * Found it, move it to free list  and try to merge.
4368          * In order to make merge easier, always sort it by qbase.
4369          * Find adjacent prev and last entries.
4370          */
4371         prev = next = NULL;
4372         LIST_FOREACH(entry, &pool->free_list, next) {
4373                 if (entry->base > valid_entry->base) {
4374                         next = entry;
4375                         break;
4376                 }
4377                 prev = entry;
4378         }
4379
4380         insert = 0;
4381         /* Try to merge with next one*/
4382         if (next != NULL) {
4383                 /* Merge with next one */
4384                 if (valid_entry->base + valid_entry->len == next->base) {
4385                         next->base = valid_entry->base;
4386                         next->len += valid_entry->len;
4387                         rte_free(valid_entry);
4388                         valid_entry = next;
4389                         insert = 1;
4390                 }
4391         }
4392
4393         if (prev != NULL) {
4394                 /* Merge with previous one */
4395                 if (prev->base + prev->len == valid_entry->base) {
4396                         prev->len += valid_entry->len;
4397                         /* If it merge with next one, remove next node */
4398                         if (insert == 1) {
4399                                 LIST_REMOVE(valid_entry, next);
4400                                 rte_free(valid_entry);
4401                         } else {
4402                                 rte_free(valid_entry);
4403                                 insert = 1;
4404                         }
4405                 }
4406         }
4407
4408         /* Not find any entry to merge, insert */
4409         if (insert == 0) {
4410                 if (prev != NULL)
4411                         LIST_INSERT_AFTER(prev, valid_entry, next);
4412                 else if (next != NULL)
4413                         LIST_INSERT_BEFORE(next, valid_entry, next);
4414                 else /* It's empty list, insert to head */
4415                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4416         }
4417
4418         pool->num_free += valid_entry->len;
4419         pool->num_alloc -= valid_entry->len;
4420
4421         return 0;
4422 }
4423
4424 static int
4425 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4426                        uint16_t num)
4427 {
4428         struct pool_entry *entry, *valid_entry;
4429
4430         if (pool == NULL || num == 0) {
4431                 PMD_DRV_LOG(ERR, "Invalid parameter");
4432                 return -EINVAL;
4433         }
4434
4435         if (pool->num_free < num) {
4436                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4437                             num, pool->num_free);
4438                 return -ENOMEM;
4439         }
4440
4441         valid_entry = NULL;
4442         /* Lookup  in free list and find most fit one */
4443         LIST_FOREACH(entry, &pool->free_list, next) {
4444                 if (entry->len >= num) {
4445                         /* Find best one */
4446                         if (entry->len == num) {
4447                                 valid_entry = entry;
4448                                 break;
4449                         }
4450                         if (valid_entry == NULL || valid_entry->len > entry->len)
4451                                 valid_entry = entry;
4452                 }
4453         }
4454
4455         /* Not find one to satisfy the request, return */
4456         if (valid_entry == NULL) {
4457                 PMD_DRV_LOG(ERR, "No valid entry found");
4458                 return -ENOMEM;
4459         }
4460         /**
4461          * The entry have equal queue number as requested,
4462          * remove it from alloc_list.
4463          */
4464         if (valid_entry->len == num) {
4465                 LIST_REMOVE(valid_entry, next);
4466         } else {
4467                 /**
4468                  * The entry have more numbers than requested,
4469                  * create a new entry for alloc_list and minus its
4470                  * queue base and number in free_list.
4471                  */
4472                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4473                 if (entry == NULL) {
4474                         PMD_DRV_LOG(ERR,
4475                                 "Failed to allocate memory for resource pool");
4476                         return -ENOMEM;
4477                 }
4478                 entry->base = valid_entry->base;
4479                 entry->len = num;
4480                 valid_entry->base += num;
4481                 valid_entry->len -= num;
4482                 valid_entry = entry;
4483         }
4484
4485         /* Insert it into alloc list, not sorted */
4486         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4487
4488         pool->num_free -= valid_entry->len;
4489         pool->num_alloc += valid_entry->len;
4490
4491         return valid_entry->base + pool->base;
4492 }
4493
4494 /**
4495  * bitmap_is_subset - Check whether src2 is subset of src1
4496  **/
4497 static inline int
4498 bitmap_is_subset(uint8_t src1, uint8_t src2)
4499 {
4500         return !((src1 ^ src2) & src2);
4501 }
4502
4503 static enum i40e_status_code
4504 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4505 {
4506         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4507
4508         /* If DCB is not supported, only default TC is supported */
4509         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4510                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4511                 return I40E_NOT_SUPPORTED;
4512         }
4513
4514         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4515                 PMD_DRV_LOG(ERR,
4516                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4517                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4518                 return I40E_NOT_SUPPORTED;
4519         }
4520         return I40E_SUCCESS;
4521 }
4522
4523 int
4524 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4525                                 struct i40e_vsi_vlan_pvid_info *info)
4526 {
4527         struct i40e_hw *hw;
4528         struct i40e_vsi_context ctxt;
4529         uint8_t vlan_flags = 0;
4530         int ret;
4531
4532         if (vsi == NULL || info == NULL) {
4533                 PMD_DRV_LOG(ERR, "invalid parameters");
4534                 return I40E_ERR_PARAM;
4535         }
4536
4537         if (info->on) {
4538                 vsi->info.pvid = info->config.pvid;
4539                 /**
4540                  * If insert pvid is enabled, only tagged pkts are
4541                  * allowed to be sent out.
4542                  */
4543                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4544                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4545         } else {
4546                 vsi->info.pvid = 0;
4547                 if (info->config.reject.tagged == 0)
4548                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4549
4550                 if (info->config.reject.untagged == 0)
4551                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4552         }
4553         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4554                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4555         vsi->info.port_vlan_flags |= vlan_flags;
4556         vsi->info.valid_sections =
4557                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4558         memset(&ctxt, 0, sizeof(ctxt));
4559         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4560         ctxt.seid = vsi->seid;
4561
4562         hw = I40E_VSI_TO_HW(vsi);
4563         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4564         if (ret != I40E_SUCCESS)
4565                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4566
4567         return ret;
4568 }
4569
4570 static int
4571 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4572 {
4573         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4574         int i, ret;
4575         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4576
4577         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4578         if (ret != I40E_SUCCESS)
4579                 return ret;
4580
4581         if (!vsi->seid) {
4582                 PMD_DRV_LOG(ERR, "seid not valid");
4583                 return -EINVAL;
4584         }
4585
4586         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4587         tc_bw_data.tc_valid_bits = enabled_tcmap;
4588         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4589                 tc_bw_data.tc_bw_credits[i] =
4590                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4591
4592         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4593         if (ret != I40E_SUCCESS) {
4594                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4595                 return ret;
4596         }
4597
4598         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4599                                         sizeof(vsi->info.qs_handle));
4600         return I40E_SUCCESS;
4601 }
4602
4603 static enum i40e_status_code
4604 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4605                                  struct i40e_aqc_vsi_properties_data *info,
4606                                  uint8_t enabled_tcmap)
4607 {
4608         enum i40e_status_code ret;
4609         int i, total_tc = 0;
4610         uint16_t qpnum_per_tc, bsf, qp_idx;
4611
4612         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4613         if (ret != I40E_SUCCESS)
4614                 return ret;
4615
4616         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4617                 if (enabled_tcmap & (1 << i))
4618                         total_tc++;
4619         if (total_tc == 0)
4620                 total_tc = 1;
4621         vsi->enabled_tc = enabled_tcmap;
4622
4623         /* Number of queues per enabled TC */
4624         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4625         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4626         bsf = rte_bsf32(qpnum_per_tc);
4627
4628         /* Adjust the queue number to actual queues that can be applied */
4629         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4630                 vsi->nb_qps = qpnum_per_tc * total_tc;
4631
4632         /**
4633          * Configure TC and queue mapping parameters, for enabled TC,
4634          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4635          * default queue will serve it.
4636          */
4637         qp_idx = 0;
4638         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4639                 if (vsi->enabled_tc & (1 << i)) {
4640                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4641                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4642                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4643                         qp_idx += qpnum_per_tc;
4644                 } else
4645                         info->tc_mapping[i] = 0;
4646         }
4647
4648         /* Associate queue number with VSI */
4649         if (vsi->type == I40E_VSI_SRIOV) {
4650                 info->mapping_flags |=
4651                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4652                 for (i = 0; i < vsi->nb_qps; i++)
4653                         info->queue_mapping[i] =
4654                                 rte_cpu_to_le_16(vsi->base_queue + i);
4655         } else {
4656                 info->mapping_flags |=
4657                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4658                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4659         }
4660         info->valid_sections |=
4661                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4662
4663         return I40E_SUCCESS;
4664 }
4665
4666 static int
4667 i40e_veb_release(struct i40e_veb *veb)
4668 {
4669         struct i40e_vsi *vsi;
4670         struct i40e_hw *hw;
4671
4672         if (veb == NULL)
4673                 return -EINVAL;
4674
4675         if (!TAILQ_EMPTY(&veb->head)) {
4676                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4677                 return -EACCES;
4678         }
4679         /* associate_vsi field is NULL for floating VEB */
4680         if (veb->associate_vsi != NULL) {
4681                 vsi = veb->associate_vsi;
4682                 hw = I40E_VSI_TO_HW(vsi);
4683
4684                 vsi->uplink_seid = veb->uplink_seid;
4685                 vsi->veb = NULL;
4686         } else {
4687                 veb->associate_pf->main_vsi->floating_veb = NULL;
4688                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4689         }
4690
4691         i40e_aq_delete_element(hw, veb->seid, NULL);
4692         rte_free(veb);
4693         return I40E_SUCCESS;
4694 }
4695
4696 /* Setup a veb */
4697 static struct i40e_veb *
4698 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4699 {
4700         struct i40e_veb *veb;
4701         int ret;
4702         struct i40e_hw *hw;
4703
4704         if (pf == NULL) {
4705                 PMD_DRV_LOG(ERR,
4706                             "veb setup failed, associated PF shouldn't null");
4707                 return NULL;
4708         }
4709         hw = I40E_PF_TO_HW(pf);
4710
4711         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4712         if (!veb) {
4713                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4714                 goto fail;
4715         }
4716
4717         veb->associate_vsi = vsi;
4718         veb->associate_pf = pf;
4719         TAILQ_INIT(&veb->head);
4720         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4721
4722         /* create floating veb if vsi is NULL */
4723         if (vsi != NULL) {
4724                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4725                                       I40E_DEFAULT_TCMAP, false,
4726                                       &veb->seid, false, NULL);
4727         } else {
4728                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4729                                       true, &veb->seid, false, NULL);
4730         }
4731
4732         if (ret != I40E_SUCCESS) {
4733                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4734                             hw->aq.asq_last_status);
4735                 goto fail;
4736         }
4737         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4738
4739         /* get statistics index */
4740         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4741                                 &veb->stats_idx, NULL, NULL, NULL);
4742         if (ret != I40E_SUCCESS) {
4743                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4744                             hw->aq.asq_last_status);
4745                 goto fail;
4746         }
4747         /* Get VEB bandwidth, to be implemented */
4748         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4749         if (vsi)
4750                 vsi->uplink_seid = veb->seid;
4751
4752         return veb;
4753 fail:
4754         rte_free(veb);
4755         return NULL;
4756 }
4757
4758 int
4759 i40e_vsi_release(struct i40e_vsi *vsi)
4760 {
4761         struct i40e_pf *pf;
4762         struct i40e_hw *hw;
4763         struct i40e_vsi_list *vsi_list;
4764         void *temp;
4765         int ret;
4766         struct i40e_mac_filter *f;
4767         uint16_t user_param;
4768
4769         if (!vsi)
4770                 return I40E_SUCCESS;
4771
4772         if (!vsi->adapter)
4773                 return -EFAULT;
4774
4775         user_param = vsi->user_param;
4776
4777         pf = I40E_VSI_TO_PF(vsi);
4778         hw = I40E_VSI_TO_HW(vsi);
4779
4780         /* VSI has child to attach, release child first */
4781         if (vsi->veb) {
4782                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4783                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4784                                 return -1;
4785                 }
4786                 i40e_veb_release(vsi->veb);
4787         }
4788
4789         if (vsi->floating_veb) {
4790                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4791                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4792                                 return -1;
4793                 }
4794         }
4795
4796         /* Remove all macvlan filters of the VSI */
4797         i40e_vsi_remove_all_macvlan_filter(vsi);
4798         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4799                 rte_free(f);
4800
4801         if (vsi->type != I40E_VSI_MAIN &&
4802             ((vsi->type != I40E_VSI_SRIOV) ||
4803             !pf->floating_veb_list[user_param])) {
4804                 /* Remove vsi from parent's sibling list */
4805                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4806                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4807                         return I40E_ERR_PARAM;
4808                 }
4809                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4810                                 &vsi->sib_vsi_list, list);
4811
4812                 /* Remove all switch element of the VSI */
4813                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4814                 if (ret != I40E_SUCCESS)
4815                         PMD_DRV_LOG(ERR, "Failed to delete element");
4816         }
4817
4818         if ((vsi->type == I40E_VSI_SRIOV) &&
4819             pf->floating_veb_list[user_param]) {
4820                 /* Remove vsi from parent's sibling list */
4821                 if (vsi->parent_vsi == NULL ||
4822                     vsi->parent_vsi->floating_veb == NULL) {
4823                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4824                         return I40E_ERR_PARAM;
4825                 }
4826                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4827                              &vsi->sib_vsi_list, list);
4828
4829                 /* Remove all switch element of the VSI */
4830                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4831                 if (ret != I40E_SUCCESS)
4832                         PMD_DRV_LOG(ERR, "Failed to delete element");
4833         }
4834
4835         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4836
4837         if (vsi->type != I40E_VSI_SRIOV)
4838                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4839         rte_free(vsi);
4840
4841         return I40E_SUCCESS;
4842 }
4843
4844 static int
4845 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4846 {
4847         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4848         struct i40e_aqc_remove_macvlan_element_data def_filter;
4849         struct i40e_mac_filter_info filter;
4850         int ret;
4851
4852         if (vsi->type != I40E_VSI_MAIN)
4853                 return I40E_ERR_CONFIG;
4854         memset(&def_filter, 0, sizeof(def_filter));
4855         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4856                                         ETH_ADDR_LEN);
4857         def_filter.vlan_tag = 0;
4858         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4859                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4860         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4861         if (ret != I40E_SUCCESS) {
4862                 struct i40e_mac_filter *f;
4863                 struct ether_addr *mac;
4864
4865                 PMD_DRV_LOG(DEBUG,
4866                             "Cannot remove the default macvlan filter");
4867                 /* It needs to add the permanent mac into mac list */
4868                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4869                 if (f == NULL) {
4870                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4871                         return I40E_ERR_NO_MEMORY;
4872                 }
4873                 mac = &f->mac_info.mac_addr;
4874                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4875                                 ETH_ADDR_LEN);
4876                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4877                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4878                 vsi->mac_num++;
4879
4880                 return ret;
4881         }
4882         rte_memcpy(&filter.mac_addr,
4883                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4884         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4885         return i40e_vsi_add_mac(vsi, &filter);
4886 }
4887
4888 /*
4889  * i40e_vsi_get_bw_config - Query VSI BW Information
4890  * @vsi: the VSI to be queried
4891  *
4892  * Returns 0 on success, negative value on failure
4893  */
4894 static enum i40e_status_code
4895 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4896 {
4897         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4898         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4899         struct i40e_hw *hw = &vsi->adapter->hw;
4900         i40e_status ret;
4901         int i;
4902         uint32_t bw_max;
4903
4904         memset(&bw_config, 0, sizeof(bw_config));
4905         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4906         if (ret != I40E_SUCCESS) {
4907                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4908                             hw->aq.asq_last_status);
4909                 return ret;
4910         }
4911
4912         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4913         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4914                                         &ets_sla_config, NULL);
4915         if (ret != I40E_SUCCESS) {
4916                 PMD_DRV_LOG(ERR,
4917                         "VSI failed to get TC bandwdith configuration %u",
4918                         hw->aq.asq_last_status);
4919                 return ret;
4920         }
4921
4922         /* store and print out BW info */
4923         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4924         vsi->bw_info.bw_max = bw_config.max_bw;
4925         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4926         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4927         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4928                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4929                      I40E_16_BIT_WIDTH);
4930         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4931                 vsi->bw_info.bw_ets_share_credits[i] =
4932                                 ets_sla_config.share_credits[i];
4933                 vsi->bw_info.bw_ets_credits[i] =
4934                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4935                 /* 4 bits per TC, 4th bit is reserved */
4936                 vsi->bw_info.bw_ets_max[i] =
4937                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4938                                   RTE_LEN2MASK(3, uint8_t));
4939                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4940                             vsi->bw_info.bw_ets_share_credits[i]);
4941                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4942                             vsi->bw_info.bw_ets_credits[i]);
4943                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4944                             vsi->bw_info.bw_ets_max[i]);
4945         }
4946
4947         return I40E_SUCCESS;
4948 }
4949
4950 /* i40e_enable_pf_lb
4951  * @pf: pointer to the pf structure
4952  *
4953  * allow loopback on pf
4954  */
4955 static inline void
4956 i40e_enable_pf_lb(struct i40e_pf *pf)
4957 {
4958         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4959         struct i40e_vsi_context ctxt;
4960         int ret;
4961
4962         /* Use the FW API if FW >= v5.0 */
4963         if (hw->aq.fw_maj_ver < 5) {
4964                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4965                 return;
4966         }
4967
4968         memset(&ctxt, 0, sizeof(ctxt));
4969         ctxt.seid = pf->main_vsi_seid;
4970         ctxt.pf_num = hw->pf_id;
4971         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4972         if (ret) {
4973                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4974                             ret, hw->aq.asq_last_status);
4975                 return;
4976         }
4977         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4978         ctxt.info.valid_sections =
4979                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4980         ctxt.info.switch_id |=
4981                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4982
4983         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4984         if (ret)
4985                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4986                             hw->aq.asq_last_status);
4987 }
4988
4989 /* Setup a VSI */
4990 struct i40e_vsi *
4991 i40e_vsi_setup(struct i40e_pf *pf,
4992                enum i40e_vsi_type type,
4993                struct i40e_vsi *uplink_vsi,
4994                uint16_t user_param)
4995 {
4996         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4997         struct i40e_vsi *vsi;
4998         struct i40e_mac_filter_info filter;
4999         int ret;
5000         struct i40e_vsi_context ctxt;
5001         struct ether_addr broadcast =
5002                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5003
5004         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5005             uplink_vsi == NULL) {
5006                 PMD_DRV_LOG(ERR,
5007                         "VSI setup failed, VSI link shouldn't be NULL");
5008                 return NULL;
5009         }
5010
5011         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5012                 PMD_DRV_LOG(ERR,
5013                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5014                 return NULL;
5015         }
5016
5017         /* two situations
5018          * 1.type is not MAIN and uplink vsi is not NULL
5019          * If uplink vsi didn't setup VEB, create one first under veb field
5020          * 2.type is SRIOV and the uplink is NULL
5021          * If floating VEB is NULL, create one veb under floating veb field
5022          */
5023
5024         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5025             uplink_vsi->veb == NULL) {
5026                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5027
5028                 if (uplink_vsi->veb == NULL) {
5029                         PMD_DRV_LOG(ERR, "VEB setup failed");
5030                         return NULL;
5031                 }
5032                 /* set ALLOWLOOPBACk on pf, when veb is created */
5033                 i40e_enable_pf_lb(pf);
5034         }
5035
5036         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5037             pf->main_vsi->floating_veb == NULL) {
5038                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5039
5040                 if (pf->main_vsi->floating_veb == NULL) {
5041                         PMD_DRV_LOG(ERR, "VEB setup failed");
5042                         return NULL;
5043                 }
5044         }
5045
5046         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5047         if (!vsi) {
5048                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5049                 return NULL;
5050         }
5051         TAILQ_INIT(&vsi->mac_list);
5052         vsi->type = type;
5053         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5054         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5055         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5056         vsi->user_param = user_param;
5057         vsi->vlan_anti_spoof_on = 0;
5058         vsi->vlan_filter_on = 0;
5059         /* Allocate queues */
5060         switch (vsi->type) {
5061         case I40E_VSI_MAIN  :
5062                 vsi->nb_qps = pf->lan_nb_qps;
5063                 break;
5064         case I40E_VSI_SRIOV :
5065                 vsi->nb_qps = pf->vf_nb_qps;
5066                 break;
5067         case I40E_VSI_VMDQ2:
5068                 vsi->nb_qps = pf->vmdq_nb_qps;
5069                 break;
5070         case I40E_VSI_FDIR:
5071                 vsi->nb_qps = pf->fdir_nb_qps;
5072                 break;
5073         default:
5074                 goto fail_mem;
5075         }
5076         /*
5077          * The filter status descriptor is reported in rx queue 0,
5078          * while the tx queue for fdir filter programming has no
5079          * such constraints, can be non-zero queues.
5080          * To simplify it, choose FDIR vsi use queue 0 pair.
5081          * To make sure it will use queue 0 pair, queue allocation
5082          * need be done before this function is called
5083          */
5084         if (type != I40E_VSI_FDIR) {
5085                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5086                         if (ret < 0) {
5087                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5088                                                 vsi->seid, ret);
5089                                 goto fail_mem;
5090                         }
5091                         vsi->base_queue = ret;
5092         } else
5093                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5094
5095         /* VF has MSIX interrupt in VF range, don't allocate here */
5096         if (type == I40E_VSI_MAIN) {
5097                 ret = i40e_res_pool_alloc(&pf->msix_pool,
5098                                           RTE_MIN(vsi->nb_qps,
5099                                                   RTE_MAX_RXTX_INTR_VEC_ID));
5100                 if (ret < 0) {
5101                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
5102                                     vsi->seid, ret);
5103                         goto fail_queue_alloc;
5104                 }
5105                 vsi->msix_intr = ret;
5106                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
5107         } else if (type != I40E_VSI_SRIOV) {
5108                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5109                 if (ret < 0) {
5110                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5111                         goto fail_queue_alloc;
5112                 }
5113                 vsi->msix_intr = ret;
5114                 vsi->nb_msix = 1;
5115         } else {
5116                 vsi->msix_intr = 0;
5117                 vsi->nb_msix = 0;
5118         }
5119
5120         /* Add VSI */
5121         if (type == I40E_VSI_MAIN) {
5122                 /* For main VSI, no need to add since it's default one */
5123                 vsi->uplink_seid = pf->mac_seid;
5124                 vsi->seid = pf->main_vsi_seid;
5125                 /* Bind queues with specific MSIX interrupt */
5126                 /**
5127                  * Needs 2 interrupt at least, one for misc cause which will
5128                  * enabled from OS side, Another for queues binding the
5129                  * interrupt from device side only.
5130                  */
5131
5132                 /* Get default VSI parameters from hardware */
5133                 memset(&ctxt, 0, sizeof(ctxt));
5134                 ctxt.seid = vsi->seid;
5135                 ctxt.pf_num = hw->pf_id;
5136                 ctxt.uplink_seid = vsi->uplink_seid;
5137                 ctxt.vf_num = 0;
5138                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5139                 if (ret != I40E_SUCCESS) {
5140                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5141                         goto fail_msix_alloc;
5142                 }
5143                 rte_memcpy(&vsi->info, &ctxt.info,
5144                         sizeof(struct i40e_aqc_vsi_properties_data));
5145                 vsi->vsi_id = ctxt.vsi_number;
5146                 vsi->info.valid_sections = 0;
5147
5148                 /* Configure tc, enabled TC0 only */
5149                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5150                         I40E_SUCCESS) {
5151                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5152                         goto fail_msix_alloc;
5153                 }
5154
5155                 /* TC, queue mapping */
5156                 memset(&ctxt, 0, sizeof(ctxt));
5157                 vsi->info.valid_sections |=
5158                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5159                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5160                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5161                 rte_memcpy(&ctxt.info, &vsi->info,
5162                         sizeof(struct i40e_aqc_vsi_properties_data));
5163                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5164                                                 I40E_DEFAULT_TCMAP);
5165                 if (ret != I40E_SUCCESS) {
5166                         PMD_DRV_LOG(ERR,
5167                                 "Failed to configure TC queue mapping");
5168                         goto fail_msix_alloc;
5169                 }
5170                 ctxt.seid = vsi->seid;
5171                 ctxt.pf_num = hw->pf_id;
5172                 ctxt.uplink_seid = vsi->uplink_seid;
5173                 ctxt.vf_num = 0;
5174
5175                 /* Update VSI parameters */
5176                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5177                 if (ret != I40E_SUCCESS) {
5178                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5179                         goto fail_msix_alloc;
5180                 }
5181
5182                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5183                                                 sizeof(vsi->info.tc_mapping));
5184                 rte_memcpy(&vsi->info.queue_mapping,
5185                                 &ctxt.info.queue_mapping,
5186                         sizeof(vsi->info.queue_mapping));
5187                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5188                 vsi->info.valid_sections = 0;
5189
5190                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5191                                 ETH_ADDR_LEN);
5192
5193                 /**
5194                  * Updating default filter settings are necessary to prevent
5195                  * reception of tagged packets.
5196                  * Some old firmware configurations load a default macvlan
5197                  * filter which accepts both tagged and untagged packets.
5198                  * The updating is to use a normal filter instead if needed.
5199                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5200                  * The firmware with correct configurations load the default
5201                  * macvlan filter which is expected and cannot be removed.
5202                  */
5203                 i40e_update_default_filter_setting(vsi);
5204                 i40e_config_qinq(hw, vsi);
5205         } else if (type == I40E_VSI_SRIOV) {
5206                 memset(&ctxt, 0, sizeof(ctxt));
5207                 /**
5208                  * For other VSI, the uplink_seid equals to uplink VSI's
5209                  * uplink_seid since they share same VEB
5210                  */
5211                 if (uplink_vsi == NULL)
5212                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5213                 else
5214                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5215                 ctxt.pf_num = hw->pf_id;
5216                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5217                 ctxt.uplink_seid = vsi->uplink_seid;
5218                 ctxt.connection_type = 0x1;
5219                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5220
5221                 /* Use the VEB configuration if FW >= v5.0 */
5222                 if (hw->aq.fw_maj_ver >= 5) {
5223                         /* Configure switch ID */
5224                         ctxt.info.valid_sections |=
5225                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5226                         ctxt.info.switch_id =
5227                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5228                 }
5229
5230                 /* Configure port/vlan */
5231                 ctxt.info.valid_sections |=
5232                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5233                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5234                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5235                                                 hw->func_caps.enabled_tcmap);
5236                 if (ret != I40E_SUCCESS) {
5237                         PMD_DRV_LOG(ERR,
5238                                 "Failed to configure TC queue mapping");
5239                         goto fail_msix_alloc;
5240                 }
5241
5242                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5243                 ctxt.info.valid_sections |=
5244                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5245                 /**
5246                  * Since VSI is not created yet, only configure parameter,
5247                  * will add vsi below.
5248                  */
5249
5250                 i40e_config_qinq(hw, vsi);
5251         } else if (type == I40E_VSI_VMDQ2) {
5252                 memset(&ctxt, 0, sizeof(ctxt));
5253                 /*
5254                  * For other VSI, the uplink_seid equals to uplink VSI's
5255                  * uplink_seid since they share same VEB
5256                  */
5257                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5258                 ctxt.pf_num = hw->pf_id;
5259                 ctxt.vf_num = 0;
5260                 ctxt.uplink_seid = vsi->uplink_seid;
5261                 ctxt.connection_type = 0x1;
5262                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5263
5264                 ctxt.info.valid_sections |=
5265                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5266                 /* user_param carries flag to enable loop back */
5267                 if (user_param) {
5268                         ctxt.info.switch_id =
5269                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5270                         ctxt.info.switch_id |=
5271                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5272                 }
5273
5274                 /* Configure port/vlan */
5275                 ctxt.info.valid_sections |=
5276                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5277                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5278                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5279                                                 I40E_DEFAULT_TCMAP);
5280                 if (ret != I40E_SUCCESS) {
5281                         PMD_DRV_LOG(ERR,
5282                                 "Failed to configure TC queue mapping");
5283                         goto fail_msix_alloc;
5284                 }
5285                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5286                 ctxt.info.valid_sections |=
5287                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5288         } else if (type == I40E_VSI_FDIR) {
5289                 memset(&ctxt, 0, sizeof(ctxt));
5290                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5291                 ctxt.pf_num = hw->pf_id;
5292                 ctxt.vf_num = 0;
5293                 ctxt.uplink_seid = vsi->uplink_seid;
5294                 ctxt.connection_type = 0x1;     /* regular data port */
5295                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5296                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5297                                                 I40E_DEFAULT_TCMAP);
5298                 if (ret != I40E_SUCCESS) {
5299                         PMD_DRV_LOG(ERR,
5300                                 "Failed to configure TC queue mapping.");
5301                         goto fail_msix_alloc;
5302                 }
5303                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5304                 ctxt.info.valid_sections |=
5305                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5306         } else {
5307                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5308                 goto fail_msix_alloc;
5309         }
5310
5311         if (vsi->type != I40E_VSI_MAIN) {
5312                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5313                 if (ret != I40E_SUCCESS) {
5314                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5315                                     hw->aq.asq_last_status);
5316                         goto fail_msix_alloc;
5317                 }
5318                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5319                 vsi->info.valid_sections = 0;
5320                 vsi->seid = ctxt.seid;
5321                 vsi->vsi_id = ctxt.vsi_number;
5322                 vsi->sib_vsi_list.vsi = vsi;
5323                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5324                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5325                                           &vsi->sib_vsi_list, list);
5326                 } else {
5327                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5328                                           &vsi->sib_vsi_list, list);
5329                 }
5330         }
5331
5332         /* MAC/VLAN configuration */
5333         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5334         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5335
5336         ret = i40e_vsi_add_mac(vsi, &filter);
5337         if (ret != I40E_SUCCESS) {
5338                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5339                 goto fail_msix_alloc;
5340         }
5341
5342         /* Get VSI BW information */
5343         i40e_vsi_get_bw_config(vsi);
5344         return vsi;
5345 fail_msix_alloc:
5346         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5347 fail_queue_alloc:
5348         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5349 fail_mem:
5350         rte_free(vsi);
5351         return NULL;
5352 }
5353
5354 /* Configure vlan filter on or off */
5355 int
5356 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5357 {
5358         int i, num;
5359         struct i40e_mac_filter *f;
5360         void *temp;
5361         struct i40e_mac_filter_info *mac_filter;
5362         enum rte_mac_filter_type desired_filter;
5363         int ret = I40E_SUCCESS;
5364
5365         if (on) {
5366                 /* Filter to match MAC and VLAN */
5367                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5368         } else {
5369                 /* Filter to match only MAC */
5370                 desired_filter = RTE_MAC_PERFECT_MATCH;
5371         }
5372
5373         num = vsi->mac_num;
5374
5375         mac_filter = rte_zmalloc("mac_filter_info_data",
5376                                  num * sizeof(*mac_filter), 0);
5377         if (mac_filter == NULL) {
5378                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5379                 return I40E_ERR_NO_MEMORY;
5380         }
5381
5382         i = 0;
5383
5384         /* Remove all existing mac */
5385         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5386                 mac_filter[i] = f->mac_info;
5387                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5388                 if (ret) {
5389                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5390                                     on ? "enable" : "disable");
5391                         goto DONE;
5392                 }
5393                 i++;
5394         }
5395
5396         /* Override with new filter */
5397         for (i = 0; i < num; i++) {
5398                 mac_filter[i].filter_type = desired_filter;
5399                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5400                 if (ret) {
5401                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5402                                     on ? "enable" : "disable");
5403                         goto DONE;
5404                 }
5405         }
5406
5407 DONE:
5408         rte_free(mac_filter);
5409         return ret;
5410 }
5411
5412 /* Configure vlan stripping on or off */
5413 int
5414 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5415 {
5416         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5417         struct i40e_vsi_context ctxt;
5418         uint8_t vlan_flags;
5419         int ret = I40E_SUCCESS;
5420
5421         /* Check if it has been already on or off */
5422         if (vsi->info.valid_sections &
5423                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5424                 if (on) {
5425                         if ((vsi->info.port_vlan_flags &
5426                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5427                                 return 0; /* already on */
5428                 } else {
5429                         if ((vsi->info.port_vlan_flags &
5430                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5431                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5432                                 return 0; /* already off */
5433                 }
5434         }
5435
5436         if (on)
5437                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5438         else
5439                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5440         vsi->info.valid_sections =
5441                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5442         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5443         vsi->info.port_vlan_flags |= vlan_flags;
5444         ctxt.seid = vsi->seid;
5445         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5446         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5447         if (ret)
5448                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5449                             on ? "enable" : "disable");
5450
5451         return ret;
5452 }
5453
5454 static int
5455 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5456 {
5457         struct rte_eth_dev_data *data = dev->data;
5458         int ret;
5459         int mask = 0;
5460
5461         /* Apply vlan offload setting */
5462         mask = ETH_VLAN_STRIP_MASK |
5463                ETH_VLAN_FILTER_MASK |
5464                ETH_VLAN_EXTEND_MASK;
5465         ret = i40e_vlan_offload_set(dev, mask);
5466         if (ret) {
5467                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5468                 return ret;
5469         }
5470
5471         /* Apply pvid setting */
5472         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5473                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5474         if (ret)
5475                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5476
5477         return ret;
5478 }
5479
5480 static int
5481 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5482 {
5483         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5484
5485         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5486 }
5487
5488 static int
5489 i40e_update_flow_control(struct i40e_hw *hw)
5490 {
5491 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5492         struct i40e_link_status link_status;
5493         uint32_t rxfc = 0, txfc = 0, reg;
5494         uint8_t an_info;
5495         int ret;
5496
5497         memset(&link_status, 0, sizeof(link_status));
5498         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5499         if (ret != I40E_SUCCESS) {
5500                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5501                 goto write_reg; /* Disable flow control */
5502         }
5503
5504         an_info = hw->phy.link_info.an_info;
5505         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5506                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5507                 ret = I40E_ERR_NOT_READY;
5508                 goto write_reg; /* Disable flow control */
5509         }
5510         /**
5511          * If link auto negotiation is enabled, flow control needs to
5512          * be configured according to it
5513          */
5514         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5515         case I40E_LINK_PAUSE_RXTX:
5516                 rxfc = 1;
5517                 txfc = 1;
5518                 hw->fc.current_mode = I40E_FC_FULL;
5519                 break;
5520         case I40E_AQ_LINK_PAUSE_RX:
5521                 rxfc = 1;
5522                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5523                 break;
5524         case I40E_AQ_LINK_PAUSE_TX:
5525                 txfc = 1;
5526                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5527                 break;
5528         default:
5529                 hw->fc.current_mode = I40E_FC_NONE;
5530                 break;
5531         }
5532
5533 write_reg:
5534         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5535                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5536         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5537         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5538         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5539         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5540
5541         return ret;
5542 }
5543
5544 /* PF setup */
5545 static int
5546 i40e_pf_setup(struct i40e_pf *pf)
5547 {
5548         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5549         struct i40e_filter_control_settings settings;
5550         struct i40e_vsi *vsi;
5551         int ret;
5552
5553         /* Clear all stats counters */
5554         pf->offset_loaded = FALSE;
5555         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5556         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5557         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5558         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5559
5560         ret = i40e_pf_get_switch_config(pf);
5561         if (ret != I40E_SUCCESS) {
5562                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5563                 return ret;
5564         }
5565         if (pf->flags & I40E_FLAG_FDIR) {
5566                 /* make queue allocated first, let FDIR use queue pair 0*/
5567                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5568                 if (ret != I40E_FDIR_QUEUE_ID) {
5569                         PMD_DRV_LOG(ERR,
5570                                 "queue allocation fails for FDIR: ret =%d",
5571                                 ret);
5572                         pf->flags &= ~I40E_FLAG_FDIR;
5573                 }
5574         }
5575         /*  main VSI setup */
5576         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5577         if (!vsi) {
5578                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5579                 return I40E_ERR_NOT_READY;
5580         }
5581         pf->main_vsi = vsi;
5582
5583         /* Configure filter control */
5584         memset(&settings, 0, sizeof(settings));
5585         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5586                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5587         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5588                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5589         else {
5590                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5591                         hw->func_caps.rss_table_size);
5592                 return I40E_ERR_PARAM;
5593         }
5594         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5595                 hw->func_caps.rss_table_size);
5596         pf->hash_lut_size = hw->func_caps.rss_table_size;
5597
5598         /* Enable ethtype and macvlan filters */
5599         settings.enable_ethtype = TRUE;
5600         settings.enable_macvlan = TRUE;
5601         ret = i40e_set_filter_control(hw, &settings);
5602         if (ret)
5603                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5604                                                                 ret);
5605
5606         /* Update flow control according to the auto negotiation */
5607         i40e_update_flow_control(hw);
5608
5609         return I40E_SUCCESS;
5610 }
5611
5612 int
5613 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5614 {
5615         uint32_t reg;
5616         uint16_t j;
5617
5618         /**
5619          * Set or clear TX Queue Disable flags,
5620          * which is required by hardware.
5621          */
5622         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5623         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5624
5625         /* Wait until the request is finished */
5626         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5627                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5628                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5629                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5630                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5631                                                         & 0x1))) {
5632                         break;
5633                 }
5634         }
5635         if (on) {
5636                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5637                         return I40E_SUCCESS; /* already on, skip next steps */
5638
5639                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5640                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5641         } else {
5642                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5643                         return I40E_SUCCESS; /* already off, skip next steps */
5644                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5645         }
5646         /* Write the register */
5647         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5648         /* Check the result */
5649         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5650                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5651                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5652                 if (on) {
5653                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5654                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5655                                 break;
5656                 } else {
5657                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5658                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5659                                 break;
5660                 }
5661         }
5662         /* Check if it is timeout */
5663         if (j >= I40E_CHK_Q_ENA_COUNT) {
5664                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5665                             (on ? "enable" : "disable"), q_idx);
5666                 return I40E_ERR_TIMEOUT;
5667         }
5668
5669         return I40E_SUCCESS;
5670 }
5671
5672 /* Swith on or off the tx queues */
5673 static int
5674 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5675 {
5676         struct rte_eth_dev_data *dev_data = pf->dev_data;
5677         struct i40e_tx_queue *txq;
5678         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5679         uint16_t i;
5680         int ret;
5681
5682         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5683                 txq = dev_data->tx_queues[i];
5684                 /* Don't operate the queue if not configured or
5685                  * if starting only per queue */
5686                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5687                         continue;
5688                 if (on)
5689                         ret = i40e_dev_tx_queue_start(dev, i);
5690                 else
5691                         ret = i40e_dev_tx_queue_stop(dev, i);
5692                 if ( ret != I40E_SUCCESS)
5693                         return ret;
5694         }
5695
5696         return I40E_SUCCESS;
5697 }
5698
5699 int
5700 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5701 {
5702         uint32_t reg;
5703         uint16_t j;
5704
5705         /* Wait until the request is finished */
5706         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5707                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5708                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5709                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5710                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5711                         break;
5712         }
5713
5714         if (on) {
5715                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5716                         return I40E_SUCCESS; /* Already on, skip next steps */
5717                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5718         } else {
5719                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5720                         return I40E_SUCCESS; /* Already off, skip next steps */
5721                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5722         }
5723
5724         /* Write the register */
5725         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5726         /* Check the result */
5727         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5728                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5729                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5730                 if (on) {
5731                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5732                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5733                                 break;
5734                 } else {
5735                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5736                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5737                                 break;
5738                 }
5739         }
5740
5741         /* Check if it is timeout */
5742         if (j >= I40E_CHK_Q_ENA_COUNT) {
5743                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5744                             (on ? "enable" : "disable"), q_idx);
5745                 return I40E_ERR_TIMEOUT;
5746         }
5747
5748         return I40E_SUCCESS;
5749 }
5750 /* Switch on or off the rx queues */
5751 static int
5752 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5753 {
5754         struct rte_eth_dev_data *dev_data = pf->dev_data;
5755         struct i40e_rx_queue *rxq;
5756         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5757         uint16_t i;
5758         int ret;
5759
5760         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5761                 rxq = dev_data->rx_queues[i];
5762                 /* Don't operate the queue if not configured or
5763                  * if starting only per queue */
5764                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5765                         continue;
5766                 if (on)
5767                         ret = i40e_dev_rx_queue_start(dev, i);
5768                 else
5769                         ret = i40e_dev_rx_queue_stop(dev, i);
5770                 if (ret != I40E_SUCCESS)
5771                         return ret;
5772         }
5773
5774         return I40E_SUCCESS;
5775 }
5776
5777 /* Switch on or off all the rx/tx queues */
5778 int
5779 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5780 {
5781         int ret;
5782
5783         if (on) {
5784                 /* enable rx queues before enabling tx queues */
5785                 ret = i40e_dev_switch_rx_queues(pf, on);
5786                 if (ret) {
5787                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5788                         return ret;
5789                 }
5790                 ret = i40e_dev_switch_tx_queues(pf, on);
5791         } else {
5792                 /* Stop tx queues before stopping rx queues */
5793                 ret = i40e_dev_switch_tx_queues(pf, on);
5794                 if (ret) {
5795                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5796                         return ret;
5797                 }
5798                 ret = i40e_dev_switch_rx_queues(pf, on);
5799         }
5800
5801         return ret;
5802 }
5803
5804 /* Initialize VSI for TX */
5805 static int
5806 i40e_dev_tx_init(struct i40e_pf *pf)
5807 {
5808         struct rte_eth_dev_data *data = pf->dev_data;
5809         uint16_t i;
5810         uint32_t ret = I40E_SUCCESS;
5811         struct i40e_tx_queue *txq;
5812
5813         for (i = 0; i < data->nb_tx_queues; i++) {
5814                 txq = data->tx_queues[i];
5815                 if (!txq || !txq->q_set)
5816                         continue;
5817                 ret = i40e_tx_queue_init(txq);
5818                 if (ret != I40E_SUCCESS)
5819                         break;
5820         }
5821         if (ret == I40E_SUCCESS)
5822                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5823                                      ->eth_dev);
5824
5825         return ret;
5826 }
5827
5828 /* Initialize VSI for RX */
5829 static int
5830 i40e_dev_rx_init(struct i40e_pf *pf)
5831 {
5832         struct rte_eth_dev_data *data = pf->dev_data;
5833         int ret = I40E_SUCCESS;
5834         uint16_t i;
5835         struct i40e_rx_queue *rxq;
5836
5837         i40e_pf_config_mq_rx(pf);
5838         for (i = 0; i < data->nb_rx_queues; i++) {
5839                 rxq = data->rx_queues[i];
5840                 if (!rxq || !rxq->q_set)
5841                         continue;
5842
5843                 ret = i40e_rx_queue_init(rxq);
5844                 if (ret != I40E_SUCCESS) {
5845                         PMD_DRV_LOG(ERR,
5846                                 "Failed to do RX queue initialization");
5847                         break;
5848                 }
5849         }
5850         if (ret == I40E_SUCCESS)
5851                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5852                                      ->eth_dev);
5853
5854         return ret;
5855 }
5856
5857 static int
5858 i40e_dev_rxtx_init(struct i40e_pf *pf)
5859 {
5860         int err;
5861
5862         err = i40e_dev_tx_init(pf);
5863         if (err) {
5864                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5865                 return err;
5866         }
5867         err = i40e_dev_rx_init(pf);
5868         if (err) {
5869                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5870                 return err;
5871         }
5872
5873         return err;
5874 }
5875
5876 static int
5877 i40e_vmdq_setup(struct rte_eth_dev *dev)
5878 {
5879         struct rte_eth_conf *conf = &dev->data->dev_conf;
5880         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5881         int i, err, conf_vsis, j, loop;
5882         struct i40e_vsi *vsi;
5883         struct i40e_vmdq_info *vmdq_info;
5884         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5885         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5886
5887         /*
5888          * Disable interrupt to avoid message from VF. Furthermore, it will
5889          * avoid race condition in VSI creation/destroy.
5890          */
5891         i40e_pf_disable_irq0(hw);
5892
5893         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5894                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5895                 return -ENOTSUP;
5896         }
5897
5898         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5899         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5900                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5901                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5902                         pf->max_nb_vmdq_vsi);
5903                 return -ENOTSUP;
5904         }
5905
5906         if (pf->vmdq != NULL) {
5907                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5908                 return 0;
5909         }
5910
5911         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5912                                 sizeof(*vmdq_info) * conf_vsis, 0);
5913
5914         if (pf->vmdq == NULL) {
5915                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5916                 return -ENOMEM;
5917         }
5918
5919         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5920
5921         /* Create VMDQ VSI */
5922         for (i = 0; i < conf_vsis; i++) {
5923                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5924                                 vmdq_conf->enable_loop_back);
5925                 if (vsi == NULL) {
5926                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5927                         err = -1;
5928                         goto err_vsi_setup;
5929                 }
5930                 vmdq_info = &pf->vmdq[i];
5931                 vmdq_info->pf = pf;
5932                 vmdq_info->vsi = vsi;
5933         }
5934         pf->nb_cfg_vmdq_vsi = conf_vsis;
5935
5936         /* Configure Vlan */
5937         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5938         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5939                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5940                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5941                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5942                                         vmdq_conf->pool_map[i].vlan_id, j);
5943
5944                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5945                                                 vmdq_conf->pool_map[i].vlan_id);
5946                                 if (err) {
5947                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5948                                         err = -1;
5949                                         goto err_vsi_setup;
5950                                 }
5951                         }
5952                 }
5953         }
5954
5955         i40e_pf_enable_irq0(hw);
5956
5957         return 0;
5958
5959 err_vsi_setup:
5960         for (i = 0; i < conf_vsis; i++)
5961                 if (pf->vmdq[i].vsi == NULL)
5962                         break;
5963                 else
5964                         i40e_vsi_release(pf->vmdq[i].vsi);
5965
5966         rte_free(pf->vmdq);
5967         pf->vmdq = NULL;
5968         i40e_pf_enable_irq0(hw);
5969         return err;
5970 }
5971
5972 static void
5973 i40e_stat_update_32(struct i40e_hw *hw,
5974                    uint32_t reg,
5975                    bool offset_loaded,
5976                    uint64_t *offset,
5977                    uint64_t *stat)
5978 {
5979         uint64_t new_data;
5980
5981         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5982         if (!offset_loaded)
5983                 *offset = new_data;
5984
5985         if (new_data >= *offset)
5986                 *stat = (uint64_t)(new_data - *offset);
5987         else
5988                 *stat = (uint64_t)((new_data +
5989                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5990 }
5991
5992 static void
5993 i40e_stat_update_48(struct i40e_hw *hw,
5994                    uint32_t hireg,
5995                    uint32_t loreg,
5996                    bool offset_loaded,
5997                    uint64_t *offset,
5998                    uint64_t *stat)
5999 {
6000         uint64_t new_data;
6001
6002         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6003         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6004                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6005
6006         if (!offset_loaded)
6007                 *offset = new_data;
6008
6009         if (new_data >= *offset)
6010                 *stat = new_data - *offset;
6011         else
6012                 *stat = (uint64_t)((new_data +
6013                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6014
6015         *stat &= I40E_48_BIT_MASK;
6016 }
6017
6018 /* Disable IRQ0 */
6019 void
6020 i40e_pf_disable_irq0(struct i40e_hw *hw)
6021 {
6022         /* Disable all interrupt types */
6023         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
6024         I40E_WRITE_FLUSH(hw);
6025 }
6026
6027 /* Enable IRQ0 */
6028 void
6029 i40e_pf_enable_irq0(struct i40e_hw *hw)
6030 {
6031         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6032                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6033                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6034                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6035         I40E_WRITE_FLUSH(hw);
6036 }
6037
6038 static void
6039 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6040 {
6041         /* read pending request and disable first */
6042         i40e_pf_disable_irq0(hw);
6043         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6044         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6045                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6046
6047         if (no_queue)
6048                 /* Link no queues with irq0 */
6049                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6050                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6051 }
6052
6053 static void
6054 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6055 {
6056         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6057         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6058         int i;
6059         uint16_t abs_vf_id;
6060         uint32_t index, offset, val;
6061
6062         if (!pf->vfs)
6063                 return;
6064         /**
6065          * Try to find which VF trigger a reset, use absolute VF id to access
6066          * since the reg is global register.
6067          */
6068         for (i = 0; i < pf->vf_num; i++) {
6069                 abs_vf_id = hw->func_caps.vf_base_id + i;
6070                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6071                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6072                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6073                 /* VFR event occurred */
6074                 if (val & (0x1 << offset)) {
6075                         int ret;
6076
6077                         /* Clear the event first */
6078                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6079                                                         (0x1 << offset));
6080                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6081                         /**
6082                          * Only notify a VF reset event occurred,
6083                          * don't trigger another SW reset
6084                          */
6085                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6086                         if (ret != I40E_SUCCESS)
6087                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6088                 }
6089         }
6090 }
6091
6092 static void
6093 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6094 {
6095         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6096         int i;
6097
6098         for (i = 0; i < pf->vf_num; i++)
6099                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6100 }
6101
6102 static void
6103 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6104 {
6105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6106         struct i40e_arq_event_info info;
6107         uint16_t pending, opcode;
6108         int ret;
6109
6110         info.buf_len = I40E_AQ_BUF_SZ;
6111         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6112         if (!info.msg_buf) {
6113                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6114                 return;
6115         }
6116
6117         pending = 1;
6118         while (pending) {
6119                 ret = i40e_clean_arq_element(hw, &info, &pending);
6120
6121                 if (ret != I40E_SUCCESS) {
6122                         PMD_DRV_LOG(INFO,
6123                                 "Failed to read msg from AdminQ, aq_err: %u",
6124                                 hw->aq.asq_last_status);
6125                         break;
6126                 }
6127                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6128
6129                 switch (opcode) {
6130                 case i40e_aqc_opc_send_msg_to_pf:
6131                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6132                         i40e_pf_host_handle_vf_msg(dev,
6133                                         rte_le_to_cpu_16(info.desc.retval),
6134                                         rte_le_to_cpu_32(info.desc.cookie_high),
6135                                         rte_le_to_cpu_32(info.desc.cookie_low),
6136                                         info.msg_buf,
6137                                         info.msg_len);
6138                         break;
6139                 case i40e_aqc_opc_get_link_status:
6140                         ret = i40e_dev_link_update(dev, 0);
6141                         if (!ret)
6142                                 _rte_eth_dev_callback_process(dev,
6143                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6144                         break;
6145                 default:
6146                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6147                                     opcode);
6148                         break;
6149                 }
6150         }
6151         rte_free(info.msg_buf);
6152 }
6153
6154 /**
6155  * Interrupt handler triggered by NIC  for handling
6156  * specific interrupt.
6157  *
6158  * @param handle
6159  *  Pointer to interrupt handle.
6160  * @param param
6161  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6162  *
6163  * @return
6164  *  void
6165  */
6166 static void
6167 i40e_dev_interrupt_handler(void *param)
6168 {
6169         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6170         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6171         uint32_t icr0;
6172
6173         /* Disable interrupt */
6174         i40e_pf_disable_irq0(hw);
6175
6176         /* read out interrupt causes */
6177         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6178
6179         /* No interrupt event indicated */
6180         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6181                 PMD_DRV_LOG(INFO, "No interrupt event");
6182                 goto done;
6183         }
6184         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6185                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6186         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6187                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6188         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6189                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6190         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6191                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6192         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6193                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6194         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6195                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6196         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6197                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6198
6199         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6200                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6201                 i40e_dev_handle_vfr_event(dev);
6202         }
6203         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6204                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6205                 i40e_dev_handle_aq_msg(dev);
6206         }
6207
6208 done:
6209         /* Enable interrupt */
6210         i40e_pf_enable_irq0(hw);
6211         rte_intr_enable(dev->intr_handle);
6212 }
6213
6214 int
6215 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6216                          struct i40e_macvlan_filter *filter,
6217                          int total)
6218 {
6219         int ele_num, ele_buff_size;
6220         int num, actual_num, i;
6221         uint16_t flags;
6222         int ret = I40E_SUCCESS;
6223         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6224         struct i40e_aqc_add_macvlan_element_data *req_list;
6225
6226         if (filter == NULL  || total == 0)
6227                 return I40E_ERR_PARAM;
6228         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6229         ele_buff_size = hw->aq.asq_buf_size;
6230
6231         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6232         if (req_list == NULL) {
6233                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6234                 return I40E_ERR_NO_MEMORY;
6235         }
6236
6237         num = 0;
6238         do {
6239                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6240                 memset(req_list, 0, ele_buff_size);
6241
6242                 for (i = 0; i < actual_num; i++) {
6243                         rte_memcpy(req_list[i].mac_addr,
6244                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6245                         req_list[i].vlan_tag =
6246                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6247
6248                         switch (filter[num + i].filter_type) {
6249                         case RTE_MAC_PERFECT_MATCH:
6250                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6251                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6252                                 break;
6253                         case RTE_MACVLAN_PERFECT_MATCH:
6254                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6255                                 break;
6256                         case RTE_MAC_HASH_MATCH:
6257                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6258                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6259                                 break;
6260                         case RTE_MACVLAN_HASH_MATCH:
6261                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6262                                 break;
6263                         default:
6264                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6265                                 ret = I40E_ERR_PARAM;
6266                                 goto DONE;
6267                         }
6268
6269                         req_list[i].queue_number = 0;
6270
6271                         req_list[i].flags = rte_cpu_to_le_16(flags);
6272                 }
6273
6274                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6275                                                 actual_num, NULL);
6276                 if (ret != I40E_SUCCESS) {
6277                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6278                         goto DONE;
6279                 }
6280                 num += actual_num;
6281         } while (num < total);
6282
6283 DONE:
6284         rte_free(req_list);
6285         return ret;
6286 }
6287
6288 int
6289 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6290                             struct i40e_macvlan_filter *filter,
6291                             int total)
6292 {
6293         int ele_num, ele_buff_size;
6294         int num, actual_num, i;
6295         uint16_t flags;
6296         int ret = I40E_SUCCESS;
6297         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6298         struct i40e_aqc_remove_macvlan_element_data *req_list;
6299
6300         if (filter == NULL  || total == 0)
6301                 return I40E_ERR_PARAM;
6302
6303         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6304         ele_buff_size = hw->aq.asq_buf_size;
6305
6306         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6307         if (req_list == NULL) {
6308                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6309                 return I40E_ERR_NO_MEMORY;
6310         }
6311
6312         num = 0;
6313         do {
6314                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6315                 memset(req_list, 0, ele_buff_size);
6316
6317                 for (i = 0; i < actual_num; i++) {
6318                         rte_memcpy(req_list[i].mac_addr,
6319                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6320                         req_list[i].vlan_tag =
6321                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6322
6323                         switch (filter[num + i].filter_type) {
6324                         case RTE_MAC_PERFECT_MATCH:
6325                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6326                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6327                                 break;
6328                         case RTE_MACVLAN_PERFECT_MATCH:
6329                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6330                                 break;
6331                         case RTE_MAC_HASH_MATCH:
6332                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6333                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6334                                 break;
6335                         case RTE_MACVLAN_HASH_MATCH:
6336                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6337                                 break;
6338                         default:
6339                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6340                                 ret = I40E_ERR_PARAM;
6341                                 goto DONE;
6342                         }
6343                         req_list[i].flags = rte_cpu_to_le_16(flags);
6344                 }
6345
6346                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6347                                                 actual_num, NULL);
6348                 if (ret != I40E_SUCCESS) {
6349                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6350                         goto DONE;
6351                 }
6352                 num += actual_num;
6353         } while (num < total);
6354
6355 DONE:
6356         rte_free(req_list);
6357         return ret;
6358 }
6359
6360 /* Find out specific MAC filter */
6361 static struct i40e_mac_filter *
6362 i40e_find_mac_filter(struct i40e_vsi *vsi,
6363                          struct ether_addr *macaddr)
6364 {
6365         struct i40e_mac_filter *f;
6366
6367         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6368                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6369                         return f;
6370         }
6371
6372         return NULL;
6373 }
6374
6375 static bool
6376 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6377                          uint16_t vlan_id)
6378 {
6379         uint32_t vid_idx, vid_bit;
6380
6381         if (vlan_id > ETH_VLAN_ID_MAX)
6382                 return 0;
6383
6384         vid_idx = I40E_VFTA_IDX(vlan_id);
6385         vid_bit = I40E_VFTA_BIT(vlan_id);
6386
6387         if (vsi->vfta[vid_idx] & vid_bit)
6388                 return 1;
6389         else
6390                 return 0;
6391 }
6392
6393 static void
6394 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6395                        uint16_t vlan_id, bool on)
6396 {
6397         uint32_t vid_idx, vid_bit;
6398
6399         vid_idx = I40E_VFTA_IDX(vlan_id);
6400         vid_bit = I40E_VFTA_BIT(vlan_id);
6401
6402         if (on)
6403                 vsi->vfta[vid_idx] |= vid_bit;
6404         else
6405                 vsi->vfta[vid_idx] &= ~vid_bit;
6406 }
6407
6408 void
6409 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6410                      uint16_t vlan_id, bool on)
6411 {
6412         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6413         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6414         int ret;
6415
6416         if (vlan_id > ETH_VLAN_ID_MAX)
6417                 return;
6418
6419         i40e_store_vlan_filter(vsi, vlan_id, on);
6420
6421         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6422                 return;
6423
6424         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6425
6426         if (on) {
6427                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6428                                        &vlan_data, 1, NULL);
6429                 if (ret != I40E_SUCCESS)
6430                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6431         } else {
6432                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6433                                           &vlan_data, 1, NULL);
6434                 if (ret != I40E_SUCCESS)
6435                         PMD_DRV_LOG(ERR,
6436                                     "Failed to remove vlan filter");
6437         }
6438 }
6439
6440 /**
6441  * Find all vlan options for specific mac addr,
6442  * return with actual vlan found.
6443  */
6444 int
6445 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6446                            struct i40e_macvlan_filter *mv_f,
6447                            int num, struct ether_addr *addr)
6448 {
6449         int i;
6450         uint32_t j, k;
6451
6452         /**
6453          * Not to use i40e_find_vlan_filter to decrease the loop time,
6454          * although the code looks complex.
6455           */
6456         if (num < vsi->vlan_num)
6457                 return I40E_ERR_PARAM;
6458
6459         i = 0;
6460         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6461                 if (vsi->vfta[j]) {
6462                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6463                                 if (vsi->vfta[j] & (1 << k)) {
6464                                         if (i > num - 1) {
6465                                                 PMD_DRV_LOG(ERR,
6466                                                         "vlan number doesn't match");
6467                                                 return I40E_ERR_PARAM;
6468                                         }
6469                                         rte_memcpy(&mv_f[i].macaddr,
6470                                                         addr, ETH_ADDR_LEN);
6471                                         mv_f[i].vlan_id =
6472                                                 j * I40E_UINT32_BIT_SIZE + k;
6473                                         i++;
6474                                 }
6475                         }
6476                 }
6477         }
6478         return I40E_SUCCESS;
6479 }
6480
6481 static inline int
6482 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6483                            struct i40e_macvlan_filter *mv_f,
6484                            int num,
6485                            uint16_t vlan)
6486 {
6487         int i = 0;
6488         struct i40e_mac_filter *f;
6489
6490         if (num < vsi->mac_num)
6491                 return I40E_ERR_PARAM;
6492
6493         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6494                 if (i > num - 1) {
6495                         PMD_DRV_LOG(ERR, "buffer number not match");
6496                         return I40E_ERR_PARAM;
6497                 }
6498                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6499                                 ETH_ADDR_LEN);
6500                 mv_f[i].vlan_id = vlan;
6501                 mv_f[i].filter_type = f->mac_info.filter_type;
6502                 i++;
6503         }
6504
6505         return I40E_SUCCESS;
6506 }
6507
6508 static int
6509 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6510 {
6511         int i, j, num;
6512         struct i40e_mac_filter *f;
6513         struct i40e_macvlan_filter *mv_f;
6514         int ret = I40E_SUCCESS;
6515
6516         if (vsi == NULL || vsi->mac_num == 0)
6517                 return I40E_ERR_PARAM;
6518
6519         /* Case that no vlan is set */
6520         if (vsi->vlan_num == 0)
6521                 num = vsi->mac_num;
6522         else
6523                 num = vsi->mac_num * vsi->vlan_num;
6524
6525         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6526         if (mv_f == NULL) {
6527                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6528                 return I40E_ERR_NO_MEMORY;
6529         }
6530
6531         i = 0;
6532         if (vsi->vlan_num == 0) {
6533                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6534                         rte_memcpy(&mv_f[i].macaddr,
6535                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6536                         mv_f[i].filter_type = f->mac_info.filter_type;
6537                         mv_f[i].vlan_id = 0;
6538                         i++;
6539                 }
6540         } else {
6541                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6542                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6543                                         vsi->vlan_num, &f->mac_info.mac_addr);
6544                         if (ret != I40E_SUCCESS)
6545                                 goto DONE;
6546                         for (j = i; j < i + vsi->vlan_num; j++)
6547                                 mv_f[j].filter_type = f->mac_info.filter_type;
6548                         i += vsi->vlan_num;
6549                 }
6550         }
6551
6552         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6553 DONE:
6554         rte_free(mv_f);
6555
6556         return ret;
6557 }
6558
6559 int
6560 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6561 {
6562         struct i40e_macvlan_filter *mv_f;
6563         int mac_num;
6564         int ret = I40E_SUCCESS;
6565
6566         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6567                 return I40E_ERR_PARAM;
6568
6569         /* If it's already set, just return */
6570         if (i40e_find_vlan_filter(vsi,vlan))
6571                 return I40E_SUCCESS;
6572
6573         mac_num = vsi->mac_num;
6574
6575         if (mac_num == 0) {
6576                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6577                 return I40E_ERR_PARAM;
6578         }
6579
6580         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6581
6582         if (mv_f == NULL) {
6583                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6584                 return I40E_ERR_NO_MEMORY;
6585         }
6586
6587         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6588
6589         if (ret != I40E_SUCCESS)
6590                 goto DONE;
6591
6592         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6593
6594         if (ret != I40E_SUCCESS)
6595                 goto DONE;
6596
6597         i40e_set_vlan_filter(vsi, vlan, 1);
6598
6599         vsi->vlan_num++;
6600         ret = I40E_SUCCESS;
6601 DONE:
6602         rte_free(mv_f);
6603         return ret;
6604 }
6605
6606 int
6607 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6608 {
6609         struct i40e_macvlan_filter *mv_f;
6610         int mac_num;
6611         int ret = I40E_SUCCESS;
6612
6613         /**
6614          * Vlan 0 is the generic filter for untagged packets
6615          * and can't be removed.
6616          */
6617         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6618                 return I40E_ERR_PARAM;
6619
6620         /* If can't find it, just return */
6621         if (!i40e_find_vlan_filter(vsi, vlan))
6622                 return I40E_ERR_PARAM;
6623
6624         mac_num = vsi->mac_num;
6625
6626         if (mac_num == 0) {
6627                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6628                 return I40E_ERR_PARAM;
6629         }
6630
6631         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6632
6633         if (mv_f == NULL) {
6634                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6635                 return I40E_ERR_NO_MEMORY;
6636         }
6637
6638         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6639
6640         if (ret != I40E_SUCCESS)
6641                 goto DONE;
6642
6643         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6644
6645         if (ret != I40E_SUCCESS)
6646                 goto DONE;
6647
6648         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6649         if (vsi->vlan_num == 1) {
6650                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6651                 if (ret != I40E_SUCCESS)
6652                         goto DONE;
6653
6654                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6655                 if (ret != I40E_SUCCESS)
6656                         goto DONE;
6657         }
6658
6659         i40e_set_vlan_filter(vsi, vlan, 0);
6660
6661         vsi->vlan_num--;
6662         ret = I40E_SUCCESS;
6663 DONE:
6664         rte_free(mv_f);
6665         return ret;
6666 }
6667
6668 int
6669 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6670 {
6671         struct i40e_mac_filter *f;
6672         struct i40e_macvlan_filter *mv_f;
6673         int i, vlan_num = 0;
6674         int ret = I40E_SUCCESS;
6675
6676         /* If it's add and we've config it, return */
6677         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6678         if (f != NULL)
6679                 return I40E_SUCCESS;
6680         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6681                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6682
6683                 /**
6684                  * If vlan_num is 0, that's the first time to add mac,
6685                  * set mask for vlan_id 0.
6686                  */
6687                 if (vsi->vlan_num == 0) {
6688                         i40e_set_vlan_filter(vsi, 0, 1);
6689                         vsi->vlan_num = 1;
6690                 }
6691                 vlan_num = vsi->vlan_num;
6692         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6693                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6694                 vlan_num = 1;
6695
6696         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6697         if (mv_f == NULL) {
6698                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6699                 return I40E_ERR_NO_MEMORY;
6700         }
6701
6702         for (i = 0; i < vlan_num; i++) {
6703                 mv_f[i].filter_type = mac_filter->filter_type;
6704                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6705                                 ETH_ADDR_LEN);
6706         }
6707
6708         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6709                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6710                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6711                                         &mac_filter->mac_addr);
6712                 if (ret != I40E_SUCCESS)
6713                         goto DONE;
6714         }
6715
6716         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6717         if (ret != I40E_SUCCESS)
6718                 goto DONE;
6719
6720         /* Add the mac addr into mac list */
6721         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6722         if (f == NULL) {
6723                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6724                 ret = I40E_ERR_NO_MEMORY;
6725                 goto DONE;
6726         }
6727         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6728                         ETH_ADDR_LEN);
6729         f->mac_info.filter_type = mac_filter->filter_type;
6730         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6731         vsi->mac_num++;
6732
6733         ret = I40E_SUCCESS;
6734 DONE:
6735         rte_free(mv_f);
6736
6737         return ret;
6738 }
6739
6740 int
6741 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6742 {
6743         struct i40e_mac_filter *f;
6744         struct i40e_macvlan_filter *mv_f;
6745         int i, vlan_num;
6746         enum rte_mac_filter_type filter_type;
6747         int ret = I40E_SUCCESS;
6748
6749         /* Can't find it, return an error */
6750         f = i40e_find_mac_filter(vsi, addr);
6751         if (f == NULL)
6752                 return I40E_ERR_PARAM;
6753
6754         vlan_num = vsi->vlan_num;
6755         filter_type = f->mac_info.filter_type;
6756         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6757                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6758                 if (vlan_num == 0) {
6759                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6760                         return I40E_ERR_PARAM;
6761                 }
6762         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6763                         filter_type == RTE_MAC_HASH_MATCH)
6764                 vlan_num = 1;
6765
6766         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6767         if (mv_f == NULL) {
6768                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6769                 return I40E_ERR_NO_MEMORY;
6770         }
6771
6772         for (i = 0; i < vlan_num; i++) {
6773                 mv_f[i].filter_type = filter_type;
6774                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6775                                 ETH_ADDR_LEN);
6776         }
6777         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6778                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6779                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6780                 if (ret != I40E_SUCCESS)
6781                         goto DONE;
6782         }
6783
6784         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6785         if (ret != I40E_SUCCESS)
6786                 goto DONE;
6787
6788         /* Remove the mac addr into mac list */
6789         TAILQ_REMOVE(&vsi->mac_list, f, next);
6790         rte_free(f);
6791         vsi->mac_num--;
6792
6793         ret = I40E_SUCCESS;
6794 DONE:
6795         rte_free(mv_f);
6796         return ret;
6797 }
6798
6799 /* Configure hash enable flags for RSS */
6800 uint64_t
6801 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6802 {
6803         uint64_t hena = 0;
6804         int i;
6805
6806         if (!flags)
6807                 return hena;
6808
6809         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6810                 if (flags & (1ULL << i))
6811                         hena |= adapter->pctypes_tbl[i];
6812         }
6813
6814         return hena;
6815 }
6816
6817 /* Parse the hash enable flags */
6818 uint64_t
6819 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6820 {
6821         uint64_t rss_hf = 0;
6822
6823         if (!flags)
6824                 return rss_hf;
6825         int i;
6826
6827         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6828                 if (flags & adapter->pctypes_tbl[i])
6829                         rss_hf |= (1ULL << i);
6830         }
6831         return rss_hf;
6832 }
6833
6834 /* Disable RSS */
6835 static void
6836 i40e_pf_disable_rss(struct i40e_pf *pf)
6837 {
6838         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6839
6840         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6841         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6842         I40E_WRITE_FLUSH(hw);
6843 }
6844
6845 int
6846 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6847 {
6848         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6849         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6850         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
6851                            I40E_VFQF_HKEY_MAX_INDEX :
6852                            I40E_PFQF_HKEY_MAX_INDEX;
6853         int ret = 0;
6854
6855         if (!key || key_len == 0) {
6856                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6857                 return 0;
6858         } else if (key_len != (key_idx + 1) *
6859                 sizeof(uint32_t)) {
6860                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6861                 return -EINVAL;
6862         }
6863
6864         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6865                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6866                         (struct i40e_aqc_get_set_rss_key_data *)key;
6867
6868                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6869                 if (ret)
6870                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6871         } else {
6872                 uint32_t *hash_key = (uint32_t *)key;
6873                 uint16_t i;
6874
6875                 if (vsi->type == I40E_VSI_SRIOV) {
6876                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
6877                                 I40E_WRITE_REG(
6878                                         hw,
6879                                         I40E_VFQF_HKEY1(i, vsi->user_param),
6880                                         hash_key[i]);
6881
6882                 } else {
6883                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6884                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
6885                                                hash_key[i]);
6886                 }
6887                 I40E_WRITE_FLUSH(hw);
6888         }
6889
6890         return ret;
6891 }
6892
6893 static int
6894 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6895 {
6896         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6897         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6898         uint32_t reg;
6899         int ret;
6900
6901         if (!key || !key_len)
6902                 return -EINVAL;
6903
6904         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6905                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6906                         (struct i40e_aqc_get_set_rss_key_data *)key);
6907                 if (ret) {
6908                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6909                         return ret;
6910                 }
6911         } else {
6912                 uint32_t *key_dw = (uint32_t *)key;
6913                 uint16_t i;
6914
6915                 if (vsi->type == I40E_VSI_SRIOV) {
6916                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
6917                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
6918                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6919                         }
6920                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
6921                                    sizeof(uint32_t);
6922                 } else {
6923                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
6924                                 reg = I40E_PFQF_HKEY(i);
6925                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6926                         }
6927                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6928                                    sizeof(uint32_t);
6929                 }
6930         }
6931         return 0;
6932 }
6933
6934 static int
6935 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6936 {
6937         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6938         uint64_t hena;
6939         int ret;
6940
6941         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6942                                rss_conf->rss_key_len);
6943         if (ret)
6944                 return ret;
6945
6946         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6947         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6948         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6949         I40E_WRITE_FLUSH(hw);
6950
6951         return 0;
6952 }
6953
6954 static int
6955 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6956                          struct rte_eth_rss_conf *rss_conf)
6957 {
6958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6959         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6960         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6961         uint64_t hena;
6962
6963         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6964         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6965
6966         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6967                 if (rss_hf != 0) /* Enable RSS */
6968                         return -EINVAL;
6969                 return 0; /* Nothing to do */
6970         }
6971         /* RSS enabled */
6972         if (rss_hf == 0) /* Disable RSS */
6973                 return -EINVAL;
6974
6975         return i40e_hw_rss_hash_set(pf, rss_conf);
6976 }
6977
6978 static int
6979 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6980                            struct rte_eth_rss_conf *rss_conf)
6981 {
6982         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6984         uint64_t hena;
6985
6986         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6987                          &rss_conf->rss_key_len);
6988
6989         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6990         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6991         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6992
6993         return 0;
6994 }
6995
6996 static int
6997 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6998 {
6999         switch (filter_type) {
7000         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7001                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7002                 break;
7003         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7004                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7005                 break;
7006         case RTE_TUNNEL_FILTER_IMAC_TENID:
7007                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7008                 break;
7009         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7010                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7011                 break;
7012         case ETH_TUNNEL_FILTER_IMAC:
7013                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7014                 break;
7015         case ETH_TUNNEL_FILTER_OIP:
7016                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7017                 break;
7018         case ETH_TUNNEL_FILTER_IIP:
7019                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7020                 break;
7021         default:
7022                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7023                 return -EINVAL;
7024         }
7025
7026         return 0;
7027 }
7028
7029 /* Convert tunnel filter structure */
7030 static int
7031 i40e_tunnel_filter_convert(
7032         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7033         struct i40e_tunnel_filter *tunnel_filter)
7034 {
7035         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7036                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7037         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7038                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7039         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7040         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7041              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7042             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7043                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7044         else
7045                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7046         tunnel_filter->input.flags = cld_filter->element.flags;
7047         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7048         tunnel_filter->queue = cld_filter->element.queue_number;
7049         rte_memcpy(tunnel_filter->input.general_fields,
7050                    cld_filter->general_fields,
7051                    sizeof(cld_filter->general_fields));
7052
7053         return 0;
7054 }
7055
7056 /* Check if there exists the tunnel filter */
7057 struct i40e_tunnel_filter *
7058 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7059                              const struct i40e_tunnel_filter_input *input)
7060 {
7061         int ret;
7062
7063         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7064         if (ret < 0)
7065                 return NULL;
7066
7067         return tunnel_rule->hash_map[ret];
7068 }
7069
7070 /* Add a tunnel filter into the SW list */
7071 static int
7072 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7073                              struct i40e_tunnel_filter *tunnel_filter)
7074 {
7075         struct i40e_tunnel_rule *rule = &pf->tunnel;
7076         int ret;
7077
7078         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7079         if (ret < 0) {
7080                 PMD_DRV_LOG(ERR,
7081                             "Failed to insert tunnel filter to hash table %d!",
7082                             ret);
7083                 return ret;
7084         }
7085         rule->hash_map[ret] = tunnel_filter;
7086
7087         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7088
7089         return 0;
7090 }
7091
7092 /* Delete a tunnel filter from the SW list */
7093 int
7094 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7095                           struct i40e_tunnel_filter_input *input)
7096 {
7097         struct i40e_tunnel_rule *rule = &pf->tunnel;
7098         struct i40e_tunnel_filter *tunnel_filter;
7099         int ret;
7100
7101         ret = rte_hash_del_key(rule->hash_table, input);
7102         if (ret < 0) {
7103                 PMD_DRV_LOG(ERR,
7104                             "Failed to delete tunnel filter to hash table %d!",
7105                             ret);
7106                 return ret;
7107         }
7108         tunnel_filter = rule->hash_map[ret];
7109         rule->hash_map[ret] = NULL;
7110
7111         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7112         rte_free(tunnel_filter);
7113
7114         return 0;
7115 }
7116
7117 int
7118 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7119                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7120                         uint8_t add)
7121 {
7122         uint16_t ip_type;
7123         uint32_t ipv4_addr, ipv4_addr_le;
7124         uint8_t i, tun_type = 0;
7125         /* internal varialbe to convert ipv6 byte order */
7126         uint32_t convert_ipv6[4];
7127         int val, ret = 0;
7128         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7129         struct i40e_vsi *vsi = pf->main_vsi;
7130         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7131         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7132         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7133         struct i40e_tunnel_filter *tunnel, *node;
7134         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7135
7136         cld_filter = rte_zmalloc("tunnel_filter",
7137                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7138         0);
7139
7140         if (NULL == cld_filter) {
7141                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7142                 return -ENOMEM;
7143         }
7144         pfilter = cld_filter;
7145
7146         ether_addr_copy(&tunnel_filter->outer_mac,
7147                         (struct ether_addr *)&pfilter->element.outer_mac);
7148         ether_addr_copy(&tunnel_filter->inner_mac,
7149                         (struct ether_addr *)&pfilter->element.inner_mac);
7150
7151         pfilter->element.inner_vlan =
7152                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7153         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7154                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7155                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7156                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7157                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7158                                 &ipv4_addr_le,
7159                                 sizeof(pfilter->element.ipaddr.v4.data));
7160         } else {
7161                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7162                 for (i = 0; i < 4; i++) {
7163                         convert_ipv6[i] =
7164                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7165                 }
7166                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7167                            &convert_ipv6,
7168                            sizeof(pfilter->element.ipaddr.v6.data));
7169         }
7170
7171         /* check tunneled type */
7172         switch (tunnel_filter->tunnel_type) {
7173         case RTE_TUNNEL_TYPE_VXLAN:
7174                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7175                 break;
7176         case RTE_TUNNEL_TYPE_NVGRE:
7177                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7178                 break;
7179         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7180                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7181                 break;
7182         default:
7183                 /* Other tunnel types is not supported. */
7184                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7185                 rte_free(cld_filter);
7186                 return -EINVAL;
7187         }
7188
7189         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7190                                        &pfilter->element.flags);
7191         if (val < 0) {
7192                 rte_free(cld_filter);
7193                 return -EINVAL;
7194         }
7195
7196         pfilter->element.flags |= rte_cpu_to_le_16(
7197                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7198                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7199         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7200         pfilter->element.queue_number =
7201                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7202
7203         /* Check if there is the filter in SW list */
7204         memset(&check_filter, 0, sizeof(check_filter));
7205         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7206         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7207         if (add && node) {
7208                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7209                 rte_free(cld_filter);
7210                 return -EINVAL;
7211         }
7212
7213         if (!add && !node) {
7214                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7215                 rte_free(cld_filter);
7216                 return -EINVAL;
7217         }
7218
7219         if (add) {
7220                 ret = i40e_aq_add_cloud_filters(hw,
7221                                         vsi->seid, &cld_filter->element, 1);
7222                 if (ret < 0) {
7223                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7224                         rte_free(cld_filter);
7225                         return -ENOTSUP;
7226                 }
7227                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7228                 if (tunnel == NULL) {
7229                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7230                         rte_free(cld_filter);
7231                         return -ENOMEM;
7232                 }
7233
7234                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7235                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7236                 if (ret < 0)
7237                         rte_free(tunnel);
7238         } else {
7239                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7240                                                    &cld_filter->element, 1);
7241                 if (ret < 0) {
7242                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7243                         rte_free(cld_filter);
7244                         return -ENOTSUP;
7245                 }
7246                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7247         }
7248
7249         rte_free(cld_filter);
7250         return ret;
7251 }
7252
7253 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7254 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7255 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7256 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7257 #define I40E_TR_GRE_KEY_MASK                    0x400
7258 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7259 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7260
7261 static enum
7262 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7263 {
7264         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7265         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7266         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7267         enum i40e_status_code status = I40E_SUCCESS;
7268
7269         memset(&filter_replace, 0,
7270                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7271         memset(&filter_replace_buf, 0,
7272                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7273
7274         /* create L1 filter */
7275         filter_replace.old_filter_type =
7276                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7277         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7278         filter_replace.tr_bit = 0;
7279
7280         /* Prepare the buffer, 3 entries */
7281         filter_replace_buf.data[0] =
7282                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7283         filter_replace_buf.data[0] |=
7284                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7285         filter_replace_buf.data[2] = 0xFF;
7286         filter_replace_buf.data[3] = 0xFF;
7287         filter_replace_buf.data[4] =
7288                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7289         filter_replace_buf.data[4] |=
7290                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7291         filter_replace_buf.data[7] = 0xF0;
7292         filter_replace_buf.data[8]
7293                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7294         filter_replace_buf.data[8] |=
7295                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7296         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7297                 I40E_TR_GENEVE_KEY_MASK |
7298                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7299         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7300                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7301                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7302
7303         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7304                                                &filter_replace_buf);
7305         if (!status) {
7306                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7307                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7308                             "cloud l1 type is changed from 0x%x to 0x%x",
7309                             filter_replace.old_filter_type,
7310                             filter_replace.new_filter_type);
7311         }
7312         return status;
7313 }
7314
7315 static enum
7316 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7317 {
7318         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7319         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7320         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7321         enum i40e_status_code status = I40E_SUCCESS;
7322
7323         /* For MPLSoUDP */
7324         memset(&filter_replace, 0,
7325                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7326         memset(&filter_replace_buf, 0,
7327                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7328         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7329                 I40E_AQC_MIRROR_CLOUD_FILTER;
7330         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7331         filter_replace.new_filter_type =
7332                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7333         /* Prepare the buffer, 2 entries */
7334         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7335         filter_replace_buf.data[0] |=
7336                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7337         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7338         filter_replace_buf.data[4] |=
7339                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7340         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7341                                                &filter_replace_buf);
7342         if (status < 0)
7343                 return status;
7344         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7345                     "cloud filter type is changed from 0x%x to 0x%x",
7346                     filter_replace.old_filter_type,
7347                     filter_replace.new_filter_type);
7348
7349         /* For MPLSoGRE */
7350         memset(&filter_replace, 0,
7351                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7352         memset(&filter_replace_buf, 0,
7353                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7354
7355         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7356                 I40E_AQC_MIRROR_CLOUD_FILTER;
7357         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7358         filter_replace.new_filter_type =
7359                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7360         /* Prepare the buffer, 2 entries */
7361         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7362         filter_replace_buf.data[0] |=
7363                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7364         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7365         filter_replace_buf.data[4] |=
7366                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7367
7368         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7369                                                &filter_replace_buf);
7370         if (!status) {
7371                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7372                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7373                             "cloud filter type is changed from 0x%x to 0x%x",
7374                             filter_replace.old_filter_type,
7375                             filter_replace.new_filter_type);
7376         }
7377         return status;
7378 }
7379
7380 static enum i40e_status_code
7381 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7382 {
7383         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7384         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7385         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7386         enum i40e_status_code status = I40E_SUCCESS;
7387
7388         /* For GTP-C */
7389         memset(&filter_replace, 0,
7390                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7391         memset(&filter_replace_buf, 0,
7392                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7393         /* create L1 filter */
7394         filter_replace.old_filter_type =
7395                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7396         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7397         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7398                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7399         /* Prepare the buffer, 2 entries */
7400         filter_replace_buf.data[0] =
7401                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7402         filter_replace_buf.data[0] |=
7403                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7404         filter_replace_buf.data[2] = 0xFF;
7405         filter_replace_buf.data[3] = 0xFF;
7406         filter_replace_buf.data[4] =
7407                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7408         filter_replace_buf.data[4] |=
7409                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7410         filter_replace_buf.data[6] = 0xFF;
7411         filter_replace_buf.data[7] = 0xFF;
7412         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7413                                                &filter_replace_buf);
7414         if (status < 0)
7415                 return status;
7416         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7417                     "cloud l1 type is changed from 0x%x to 0x%x",
7418                     filter_replace.old_filter_type,
7419                     filter_replace.new_filter_type);
7420
7421         /* for GTP-U */
7422         memset(&filter_replace, 0,
7423                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7424         memset(&filter_replace_buf, 0,
7425                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7426         /* create L1 filter */
7427         filter_replace.old_filter_type =
7428                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7429         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7430         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7431                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7432         /* Prepare the buffer, 2 entries */
7433         filter_replace_buf.data[0] =
7434                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7435         filter_replace_buf.data[0] |=
7436                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7437         filter_replace_buf.data[2] = 0xFF;
7438         filter_replace_buf.data[3] = 0xFF;
7439         filter_replace_buf.data[4] =
7440                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7441         filter_replace_buf.data[4] |=
7442                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7443         filter_replace_buf.data[6] = 0xFF;
7444         filter_replace_buf.data[7] = 0xFF;
7445
7446         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7447                                                &filter_replace_buf);
7448         if (!status) {
7449                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7450                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7451                             "cloud l1 type is changed from 0x%x to 0x%x",
7452                             filter_replace.old_filter_type,
7453                             filter_replace.new_filter_type);
7454         }
7455         return status;
7456 }
7457
7458 static enum
7459 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7460 {
7461         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7462         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7463         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7464         enum i40e_status_code status = I40E_SUCCESS;
7465
7466         /* for GTP-C */
7467         memset(&filter_replace, 0,
7468                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7469         memset(&filter_replace_buf, 0,
7470                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7471         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7472         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7473         filter_replace.new_filter_type =
7474                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7475         /* Prepare the buffer, 2 entries */
7476         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7477         filter_replace_buf.data[0] |=
7478                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7479         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7480         filter_replace_buf.data[4] |=
7481                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7482         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7483                                                &filter_replace_buf);
7484         if (status < 0)
7485                 return status;
7486         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7487                     "cloud filter type is changed from 0x%x to 0x%x",
7488                     filter_replace.old_filter_type,
7489                     filter_replace.new_filter_type);
7490
7491         /* for GTP-U */
7492         memset(&filter_replace, 0,
7493                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7494         memset(&filter_replace_buf, 0,
7495                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7496         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7497         filter_replace.old_filter_type =
7498                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7499         filter_replace.new_filter_type =
7500                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7501         /* Prepare the buffer, 2 entries */
7502         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7503         filter_replace_buf.data[0] |=
7504                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7505         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7506         filter_replace_buf.data[4] |=
7507                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7508
7509         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7510                                                &filter_replace_buf);
7511         if (!status) {
7512                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7513                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7514                             "cloud filter type is changed from 0x%x to 0x%x",
7515                             filter_replace.old_filter_type,
7516                             filter_replace.new_filter_type);
7517         }
7518         return status;
7519 }
7520
7521 int
7522 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7523                       struct i40e_tunnel_filter_conf *tunnel_filter,
7524                       uint8_t add)
7525 {
7526         uint16_t ip_type;
7527         uint32_t ipv4_addr, ipv4_addr_le;
7528         uint8_t i, tun_type = 0;
7529         /* internal variable to convert ipv6 byte order */
7530         uint32_t convert_ipv6[4];
7531         int val, ret = 0;
7532         struct i40e_pf_vf *vf = NULL;
7533         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7534         struct i40e_vsi *vsi;
7535         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7536         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7537         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7538         struct i40e_tunnel_filter *tunnel, *node;
7539         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7540         uint32_t teid_le;
7541         bool big_buffer = 0;
7542
7543         cld_filter = rte_zmalloc("tunnel_filter",
7544                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7545                          0);
7546
7547         if (cld_filter == NULL) {
7548                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7549                 return -ENOMEM;
7550         }
7551         pfilter = cld_filter;
7552
7553         ether_addr_copy(&tunnel_filter->outer_mac,
7554                         (struct ether_addr *)&pfilter->element.outer_mac);
7555         ether_addr_copy(&tunnel_filter->inner_mac,
7556                         (struct ether_addr *)&pfilter->element.inner_mac);
7557
7558         pfilter->element.inner_vlan =
7559                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7560         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7561                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7562                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7563                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7564                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7565                                 &ipv4_addr_le,
7566                                 sizeof(pfilter->element.ipaddr.v4.data));
7567         } else {
7568                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7569                 for (i = 0; i < 4; i++) {
7570                         convert_ipv6[i] =
7571                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7572                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7573                 }
7574                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7575                            &convert_ipv6,
7576                            sizeof(pfilter->element.ipaddr.v6.data));
7577         }
7578
7579         /* check tunneled type */
7580         switch (tunnel_filter->tunnel_type) {
7581         case I40E_TUNNEL_TYPE_VXLAN:
7582                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7583                 break;
7584         case I40E_TUNNEL_TYPE_NVGRE:
7585                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7586                 break;
7587         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7588                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7589                 break;
7590         case I40E_TUNNEL_TYPE_MPLSoUDP:
7591                 if (!pf->mpls_replace_flag) {
7592                         i40e_replace_mpls_l1_filter(pf);
7593                         i40e_replace_mpls_cloud_filter(pf);
7594                         pf->mpls_replace_flag = 1;
7595                 }
7596                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7597                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7598                         teid_le >> 4;
7599                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7600                         (teid_le & 0xF) << 12;
7601                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7602                         0x40;
7603                 big_buffer = 1;
7604                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7605                 break;
7606         case I40E_TUNNEL_TYPE_MPLSoGRE:
7607                 if (!pf->mpls_replace_flag) {
7608                         i40e_replace_mpls_l1_filter(pf);
7609                         i40e_replace_mpls_cloud_filter(pf);
7610                         pf->mpls_replace_flag = 1;
7611                 }
7612                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7613                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7614                         teid_le >> 4;
7615                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7616                         (teid_le & 0xF) << 12;
7617                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7618                         0x0;
7619                 big_buffer = 1;
7620                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7621                 break;
7622         case I40E_TUNNEL_TYPE_GTPC:
7623                 if (!pf->gtp_replace_flag) {
7624                         i40e_replace_gtp_l1_filter(pf);
7625                         i40e_replace_gtp_cloud_filter(pf);
7626                         pf->gtp_replace_flag = 1;
7627                 }
7628                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7629                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7630                         (teid_le >> 16) & 0xFFFF;
7631                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7632                         teid_le & 0xFFFF;
7633                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7634                         0x0;
7635                 big_buffer = 1;
7636                 break;
7637         case I40E_TUNNEL_TYPE_GTPU:
7638                 if (!pf->gtp_replace_flag) {
7639                         i40e_replace_gtp_l1_filter(pf);
7640                         i40e_replace_gtp_cloud_filter(pf);
7641                         pf->gtp_replace_flag = 1;
7642                 }
7643                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7644                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7645                         (teid_le >> 16) & 0xFFFF;
7646                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7647                         teid_le & 0xFFFF;
7648                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7649                         0x0;
7650                 big_buffer = 1;
7651                 break;
7652         case I40E_TUNNEL_TYPE_QINQ:
7653                 if (!pf->qinq_replace_flag) {
7654                         ret = i40e_cloud_filter_qinq_create(pf);
7655                         if (ret < 0)
7656                                 PMD_DRV_LOG(DEBUG,
7657                                             "QinQ tunnel filter already created.");
7658                         pf->qinq_replace_flag = 1;
7659                 }
7660                 /*      Add in the General fields the values of
7661                  *      the Outer and Inner VLAN
7662                  *      Big Buffer should be set, see changes in
7663                  *      i40e_aq_add_cloud_filters
7664                  */
7665                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7666                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7667                 big_buffer = 1;
7668                 break;
7669         default:
7670                 /* Other tunnel types is not supported. */
7671                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7672                 rte_free(cld_filter);
7673                 return -EINVAL;
7674         }
7675
7676         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7677                 pfilter->element.flags =
7678                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7679         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7680                 pfilter->element.flags =
7681                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7682         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7683                 pfilter->element.flags =
7684                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7685         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7686                 pfilter->element.flags =
7687                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7688         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7689                 pfilter->element.flags |=
7690                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7691         else {
7692                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7693                                                 &pfilter->element.flags);
7694                 if (val < 0) {
7695                         rte_free(cld_filter);
7696                         return -EINVAL;
7697                 }
7698         }
7699
7700         pfilter->element.flags |= rte_cpu_to_le_16(
7701                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7702                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7703         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7704         pfilter->element.queue_number =
7705                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7706
7707         if (!tunnel_filter->is_to_vf)
7708                 vsi = pf->main_vsi;
7709         else {
7710                 if (tunnel_filter->vf_id >= pf->vf_num) {
7711                         PMD_DRV_LOG(ERR, "Invalid argument.");
7712                         rte_free(cld_filter);
7713                         return -EINVAL;
7714                 }
7715                 vf = &pf->vfs[tunnel_filter->vf_id];
7716                 vsi = vf->vsi;
7717         }
7718
7719         /* Check if there is the filter in SW list */
7720         memset(&check_filter, 0, sizeof(check_filter));
7721         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7722         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7723         check_filter.vf_id = tunnel_filter->vf_id;
7724         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7725         if (add && node) {
7726                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7727                 rte_free(cld_filter);
7728                 return -EINVAL;
7729         }
7730
7731         if (!add && !node) {
7732                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7733                 rte_free(cld_filter);
7734                 return -EINVAL;
7735         }
7736
7737         if (add) {
7738                 if (big_buffer)
7739                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7740                                                    vsi->seid, cld_filter, 1);
7741                 else
7742                         ret = i40e_aq_add_cloud_filters(hw,
7743                                         vsi->seid, &cld_filter->element, 1);
7744                 if (ret < 0) {
7745                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7746                         rte_free(cld_filter);
7747                         return -ENOTSUP;
7748                 }
7749                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7750                 if (tunnel == NULL) {
7751                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7752                         rte_free(cld_filter);
7753                         return -ENOMEM;
7754                 }
7755
7756                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7757                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7758                 if (ret < 0)
7759                         rte_free(tunnel);
7760         } else {
7761                 if (big_buffer)
7762                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7763                                 hw, vsi->seid, cld_filter, 1);
7764                 else
7765                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7766                                                    &cld_filter->element, 1);
7767                 if (ret < 0) {
7768                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7769                         rte_free(cld_filter);
7770                         return -ENOTSUP;
7771                 }
7772                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7773         }
7774
7775         rte_free(cld_filter);
7776         return ret;
7777 }
7778
7779 static int
7780 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7781 {
7782         uint8_t i;
7783
7784         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7785                 if (pf->vxlan_ports[i] == port)
7786                         return i;
7787         }
7788
7789         return -1;
7790 }
7791
7792 static int
7793 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7794 {
7795         int  idx, ret;
7796         uint8_t filter_idx;
7797         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7798
7799         idx = i40e_get_vxlan_port_idx(pf, port);
7800
7801         /* Check if port already exists */
7802         if (idx >= 0) {
7803                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7804                 return -EINVAL;
7805         }
7806
7807         /* Now check if there is space to add the new port */
7808         idx = i40e_get_vxlan_port_idx(pf, 0);
7809         if (idx < 0) {
7810                 PMD_DRV_LOG(ERR,
7811                         "Maximum number of UDP ports reached, not adding port %d",
7812                         port);
7813                 return -ENOSPC;
7814         }
7815
7816         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7817                                         &filter_idx, NULL);
7818         if (ret < 0) {
7819                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7820                 return -1;
7821         }
7822
7823         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7824                          port,  filter_idx);
7825
7826         /* New port: add it and mark its index in the bitmap */
7827         pf->vxlan_ports[idx] = port;
7828         pf->vxlan_bitmap |= (1 << idx);
7829
7830         if (!(pf->flags & I40E_FLAG_VXLAN))
7831                 pf->flags |= I40E_FLAG_VXLAN;
7832
7833         return 0;
7834 }
7835
7836 static int
7837 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7838 {
7839         int idx;
7840         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7841
7842         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7843                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7844                 return -EINVAL;
7845         }
7846
7847         idx = i40e_get_vxlan_port_idx(pf, port);
7848
7849         if (idx < 0) {
7850                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7851                 return -EINVAL;
7852         }
7853
7854         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7855                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7856                 return -1;
7857         }
7858
7859         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7860                         port, idx);
7861
7862         pf->vxlan_ports[idx] = 0;
7863         pf->vxlan_bitmap &= ~(1 << idx);
7864
7865         if (!pf->vxlan_bitmap)
7866                 pf->flags &= ~I40E_FLAG_VXLAN;
7867
7868         return 0;
7869 }
7870
7871 /* Add UDP tunneling port */
7872 static int
7873 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7874                              struct rte_eth_udp_tunnel *udp_tunnel)
7875 {
7876         int ret = 0;
7877         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7878
7879         if (udp_tunnel == NULL)
7880                 return -EINVAL;
7881
7882         switch (udp_tunnel->prot_type) {
7883         case RTE_TUNNEL_TYPE_VXLAN:
7884                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7885                 break;
7886
7887         case RTE_TUNNEL_TYPE_GENEVE:
7888         case RTE_TUNNEL_TYPE_TEREDO:
7889                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7890                 ret = -1;
7891                 break;
7892
7893         default:
7894                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7895                 ret = -1;
7896                 break;
7897         }
7898
7899         return ret;
7900 }
7901
7902 /* Remove UDP tunneling port */
7903 static int
7904 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7905                              struct rte_eth_udp_tunnel *udp_tunnel)
7906 {
7907         int ret = 0;
7908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7909
7910         if (udp_tunnel == NULL)
7911                 return -EINVAL;
7912
7913         switch (udp_tunnel->prot_type) {
7914         case RTE_TUNNEL_TYPE_VXLAN:
7915                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7916                 break;
7917         case RTE_TUNNEL_TYPE_GENEVE:
7918         case RTE_TUNNEL_TYPE_TEREDO:
7919                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7920                 ret = -1;
7921                 break;
7922         default:
7923                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7924                 ret = -1;
7925                 break;
7926         }
7927
7928         return ret;
7929 }
7930
7931 /* Calculate the maximum number of contiguous PF queues that are configured */
7932 static int
7933 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7934 {
7935         struct rte_eth_dev_data *data = pf->dev_data;
7936         int i, num;
7937         struct i40e_rx_queue *rxq;
7938
7939         num = 0;
7940         for (i = 0; i < pf->lan_nb_qps; i++) {
7941                 rxq = data->rx_queues[i];
7942                 if (rxq && rxq->q_set)
7943                         num++;
7944                 else
7945                         break;
7946         }
7947
7948         return num;
7949 }
7950
7951 /* Configure RSS */
7952 static int
7953 i40e_pf_config_rss(struct i40e_pf *pf)
7954 {
7955         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7956         struct rte_eth_rss_conf rss_conf;
7957         uint32_t i, lut = 0;
7958         uint16_t j, num;
7959
7960         /*
7961          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7962          * It's necessary to calculate the actual PF queues that are configured.
7963          */
7964         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7965                 num = i40e_pf_calc_configured_queues_num(pf);
7966         else
7967                 num = pf->dev_data->nb_rx_queues;
7968
7969         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7970         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7971                         num);
7972
7973         if (num == 0) {
7974                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7975                 return -ENOTSUP;
7976         }
7977
7978         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7979                 if (j == num)
7980                         j = 0;
7981                 lut = (lut << 8) | (j & ((0x1 <<
7982                         hw->func_caps.rss_table_entry_width) - 1));
7983                 if ((i & 3) == 3)
7984                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7985         }
7986
7987         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7988         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7989                 i40e_pf_disable_rss(pf);
7990                 return 0;
7991         }
7992         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7993                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7994                 /* Random default keys */
7995                 static uint32_t rss_key_default[] = {0x6b793944,
7996                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7997                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7998                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7999
8000                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8001                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8002                                                         sizeof(uint32_t);
8003         }
8004
8005         return i40e_hw_rss_hash_set(pf, &rss_conf);
8006 }
8007
8008 static int
8009 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8010                                struct rte_eth_tunnel_filter_conf *filter)
8011 {
8012         if (pf == NULL || filter == NULL) {
8013                 PMD_DRV_LOG(ERR, "Invalid parameter");
8014                 return -EINVAL;
8015         }
8016
8017         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8018                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8019                 return -EINVAL;
8020         }
8021
8022         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8023                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8024                 return -EINVAL;
8025         }
8026
8027         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8028                 (is_zero_ether_addr(&filter->outer_mac))) {
8029                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8030                 return -EINVAL;
8031         }
8032
8033         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8034                 (is_zero_ether_addr(&filter->inner_mac))) {
8035                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8036                 return -EINVAL;
8037         }
8038
8039         return 0;
8040 }
8041
8042 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8043 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8044 static int
8045 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8046 {
8047         uint32_t val, reg;
8048         int ret = -EINVAL;
8049
8050         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8051         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8052
8053         if (len == 3) {
8054                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8055         } else if (len == 4) {
8056                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8057         } else {
8058                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8059                 return ret;
8060         }
8061
8062         if (reg != val) {
8063                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8064                                                    reg, NULL);
8065                 if (ret != 0)
8066                         return ret;
8067                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8068                             "with value 0x%08x",
8069                             I40E_GL_PRS_FVBM(2), reg);
8070                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8071         } else {
8072                 ret = 0;
8073         }
8074         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8075                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8076
8077         return ret;
8078 }
8079
8080 static int
8081 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8082 {
8083         int ret = -EINVAL;
8084
8085         if (!hw || !cfg)
8086                 return -EINVAL;
8087
8088         switch (cfg->cfg_type) {
8089         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8090                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8091                 break;
8092         default:
8093                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8094                 break;
8095         }
8096
8097         return ret;
8098 }
8099
8100 static int
8101 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8102                                enum rte_filter_op filter_op,
8103                                void *arg)
8104 {
8105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8106         int ret = I40E_ERR_PARAM;
8107
8108         switch (filter_op) {
8109         case RTE_ETH_FILTER_SET:
8110                 ret = i40e_dev_global_config_set(hw,
8111                         (struct rte_eth_global_cfg *)arg);
8112                 break;
8113         default:
8114                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8115                 break;
8116         }
8117
8118         return ret;
8119 }
8120
8121 static int
8122 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8123                           enum rte_filter_op filter_op,
8124                           void *arg)
8125 {
8126         struct rte_eth_tunnel_filter_conf *filter;
8127         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8128         int ret = I40E_SUCCESS;
8129
8130         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8131
8132         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8133                 return I40E_ERR_PARAM;
8134
8135         switch (filter_op) {
8136         case RTE_ETH_FILTER_NOP:
8137                 if (!(pf->flags & I40E_FLAG_VXLAN))
8138                         ret = I40E_NOT_SUPPORTED;
8139                 break;
8140         case RTE_ETH_FILTER_ADD:
8141                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8142                 break;
8143         case RTE_ETH_FILTER_DELETE:
8144                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8145                 break;
8146         default:
8147                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8148                 ret = I40E_ERR_PARAM;
8149                 break;
8150         }
8151
8152         return ret;
8153 }
8154
8155 static int
8156 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8157 {
8158         int ret = 0;
8159         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8160
8161         /* RSS setup */
8162         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8163                 ret = i40e_pf_config_rss(pf);
8164         else
8165                 i40e_pf_disable_rss(pf);
8166
8167         return ret;
8168 }
8169
8170 /* Get the symmetric hash enable configurations per port */
8171 static void
8172 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8173 {
8174         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8175
8176         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8177 }
8178
8179 /* Set the symmetric hash enable configurations per port */
8180 static void
8181 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8182 {
8183         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8184
8185         if (enable > 0) {
8186                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8187                         PMD_DRV_LOG(INFO,
8188                                 "Symmetric hash has already been enabled");
8189                         return;
8190                 }
8191                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8192         } else {
8193                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8194                         PMD_DRV_LOG(INFO,
8195                                 "Symmetric hash has already been disabled");
8196                         return;
8197                 }
8198                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8199         }
8200         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8201         I40E_WRITE_FLUSH(hw);
8202 }
8203
8204 /*
8205  * Get global configurations of hash function type and symmetric hash enable
8206  * per flow type (pctype). Note that global configuration means it affects all
8207  * the ports on the same NIC.
8208  */
8209 static int
8210 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8211                                    struct rte_eth_hash_global_conf *g_cfg)
8212 {
8213         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8214         uint32_t reg;
8215         uint16_t i, j;
8216
8217         memset(g_cfg, 0, sizeof(*g_cfg));
8218         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8219         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8220                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8221         else
8222                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8223         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8224                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8225
8226         /*
8227          * As i40e supports less than 64 flow types, only first 64 bits need to
8228          * be checked.
8229          */
8230         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8231                 g_cfg->valid_bit_mask[i] = 0ULL;
8232                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8233         }
8234
8235         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8236
8237         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8238                 if (!adapter->pctypes_tbl[i])
8239                         continue;
8240                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8241                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8242                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8243                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8244                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8245                                         g_cfg->sym_hash_enable_mask[0] |=
8246                                                                 (1ULL << i);
8247                                 }
8248                         }
8249                 }
8250         }
8251
8252         return 0;
8253 }
8254
8255 static int
8256 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8257                               const struct rte_eth_hash_global_conf *g_cfg)
8258 {
8259         uint32_t i;
8260         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8261
8262         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8263                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8264                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8265                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8266                                                 g_cfg->hash_func);
8267                 return -EINVAL;
8268         }
8269
8270         /*
8271          * As i40e supports less than 64 flow types, only first 64 bits need to
8272          * be checked.
8273          */
8274         mask0 = g_cfg->valid_bit_mask[0];
8275         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8276                 if (i == 0) {
8277                         /* Check if any unsupported flow type configured */
8278                         if ((mask0 | i40e_mask) ^ i40e_mask)
8279                                 goto mask_err;
8280                 } else {
8281                         if (g_cfg->valid_bit_mask[i])
8282                                 goto mask_err;
8283                 }
8284         }
8285
8286         return 0;
8287
8288 mask_err:
8289         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8290
8291         return -EINVAL;
8292 }
8293
8294 /*
8295  * Set global configurations of hash function type and symmetric hash enable
8296  * per flow type (pctype). Note any modifying global configuration will affect
8297  * all the ports on the same NIC.
8298  */
8299 static int
8300 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8301                                    struct rte_eth_hash_global_conf *g_cfg)
8302 {
8303         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8304         int ret;
8305         uint16_t i, j;
8306         uint32_t reg;
8307         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8308
8309         /* Check the input parameters */
8310         ret = i40e_hash_global_config_check(adapter, g_cfg);
8311         if (ret < 0)
8312                 return ret;
8313
8314         /*
8315          * As i40e supports less than 64 flow types, only first 64 bits need to
8316          * be configured.
8317          */
8318         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8319                 if (mask0 & (1UL << i)) {
8320                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8321                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8322
8323                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8324                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8325                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8326                                         i40e_write_global_rx_ctl(hw,
8327                                                           I40E_GLQF_HSYM(j),
8328                                                           reg);
8329                         }
8330                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8331                 }
8332         }
8333
8334         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8335         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8336                 /* Toeplitz */
8337                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8338                         PMD_DRV_LOG(DEBUG,
8339                                 "Hash function already set to Toeplitz");
8340                         goto out;
8341                 }
8342                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8343         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8344                 /* Simple XOR */
8345                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8346                         PMD_DRV_LOG(DEBUG,
8347                                 "Hash function already set to Simple XOR");
8348                         goto out;
8349                 }
8350                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8351         } else
8352                 /* Use the default, and keep it as it is */
8353                 goto out;
8354
8355         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8356         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8357
8358 out:
8359         I40E_WRITE_FLUSH(hw);
8360
8361         return 0;
8362 }
8363
8364 /**
8365  * Valid input sets for hash and flow director filters per PCTYPE
8366  */
8367 static uint64_t
8368 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8369                 enum rte_filter_type filter)
8370 {
8371         uint64_t valid;
8372
8373         static const uint64_t valid_hash_inset_table[] = {
8374                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8375                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8376                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8377                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8378                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8379                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8380                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8381                         I40E_INSET_FLEX_PAYLOAD,
8382                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8383                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8384                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8385                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8386                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8387                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8388                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8389                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8390                         I40E_INSET_FLEX_PAYLOAD,
8391                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8392                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8393                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8394                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8395                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8396                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8397                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8398                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8399                         I40E_INSET_FLEX_PAYLOAD,
8400                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8401                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8402                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8403                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8404                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8405                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8406                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8407                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8408                         I40E_INSET_FLEX_PAYLOAD,
8409                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8410                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8411                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8412                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8413                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8414                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8415                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8416                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8417                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8418                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8419                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8420                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8421                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8422                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8423                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8424                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8425                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8426                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8427                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8428                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8429                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8430                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8431                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8432                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8433                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8434                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8435                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8436                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8437                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8438                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8439                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8440                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8441                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8442                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8443                         I40E_INSET_FLEX_PAYLOAD,
8444                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8445                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8446                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8447                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8448                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8449                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8450                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8451                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8452                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8453                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8454                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8455                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8456                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8457                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8458                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8459                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8460                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8461                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8462                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8463                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8464                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8465                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8466                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8467                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8468                         I40E_INSET_FLEX_PAYLOAD,
8469                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8470                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8471                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8472                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8473                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8474                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8475                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8476                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8477                         I40E_INSET_FLEX_PAYLOAD,
8478                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8479                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8480                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8481                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8482                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8483                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8484                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8485                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8486                         I40E_INSET_FLEX_PAYLOAD,
8487                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8488                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8489                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8490                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8491                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8492                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8493                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8494                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8495                         I40E_INSET_FLEX_PAYLOAD,
8496                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8497                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8498                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8499                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8500                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8501                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8502                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8503                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8504                         I40E_INSET_FLEX_PAYLOAD,
8505                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8506                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8507                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8508                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8509                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8510                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8511                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8512                         I40E_INSET_FLEX_PAYLOAD,
8513                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8514                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8515                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8516                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8517                         I40E_INSET_FLEX_PAYLOAD,
8518         };
8519
8520         /**
8521          * Flow director supports only fields defined in
8522          * union rte_eth_fdir_flow.
8523          */
8524         static const uint64_t valid_fdir_inset_table[] = {
8525                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8526                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8527                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8528                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8529                 I40E_INSET_IPV4_TTL,
8530                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8531                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8532                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8533                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8534                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8535                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8536                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8537                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8538                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8539                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8540                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8541                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8542                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8543                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8544                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8545                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8546                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8547                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8548                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8549                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8550                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8551                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8552                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8553                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8554                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8555                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8556                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8557                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8558                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8559                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8560                 I40E_INSET_SCTP_VT,
8561                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8562                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8563                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8564                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8565                 I40E_INSET_IPV4_TTL,
8566                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8567                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8568                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8569                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8570                 I40E_INSET_IPV6_HOP_LIMIT,
8571                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8572                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8573                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8574                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8575                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8576                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8577                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8578                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8579                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8580                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8581                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8582                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8583                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8584                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8585                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8586                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8587                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8588                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8589                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8590                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8591                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8592                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8593                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8594                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8595                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8596                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8597                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8598                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8599                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8600                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8601                 I40E_INSET_SCTP_VT,
8602                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8603                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8604                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8605                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8606                 I40E_INSET_IPV6_HOP_LIMIT,
8607                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8608                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8609                 I40E_INSET_LAST_ETHER_TYPE,
8610         };
8611
8612         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8613                 return 0;
8614         if (filter == RTE_ETH_FILTER_HASH)
8615                 valid = valid_hash_inset_table[pctype];
8616         else
8617                 valid = valid_fdir_inset_table[pctype];
8618
8619         return valid;
8620 }
8621
8622 /**
8623  * Validate if the input set is allowed for a specific PCTYPE
8624  */
8625 int
8626 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8627                 enum rte_filter_type filter, uint64_t inset)
8628 {
8629         uint64_t valid;
8630
8631         valid = i40e_get_valid_input_set(pctype, filter);
8632         if (inset & (~valid))
8633                 return -EINVAL;
8634
8635         return 0;
8636 }
8637
8638 /* default input set fields combination per pctype */
8639 uint64_t
8640 i40e_get_default_input_set(uint16_t pctype)
8641 {
8642         static const uint64_t default_inset_table[] = {
8643                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8644                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8645                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8646                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8647                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8648                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8649                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8650                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8651                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8652                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8653                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8654                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8655                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8656                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8657                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8658                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8659                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8660                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8661                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8662                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8663                         I40E_INSET_SCTP_VT,
8664                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8665                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8666                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8667                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8668                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8669                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8670                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8671                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8672                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8673                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8674                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8675                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8676                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8677                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8678                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8679                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8680                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8681                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8682                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8683                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8684                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8685                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8686                         I40E_INSET_SCTP_VT,
8687                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8688                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8689                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8690                         I40E_INSET_LAST_ETHER_TYPE,
8691         };
8692
8693         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8694                 return 0;
8695
8696         return default_inset_table[pctype];
8697 }
8698
8699 /**
8700  * Parse the input set from index to logical bit masks
8701  */
8702 static int
8703 i40e_parse_input_set(uint64_t *inset,
8704                      enum i40e_filter_pctype pctype,
8705                      enum rte_eth_input_set_field *field,
8706                      uint16_t size)
8707 {
8708         uint16_t i, j;
8709         int ret = -EINVAL;
8710
8711         static const struct {
8712                 enum rte_eth_input_set_field field;
8713                 uint64_t inset;
8714         } inset_convert_table[] = {
8715                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8716                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8717                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8718                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8719                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8720                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8721                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8722                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8723                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8724                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8725                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8726                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8727                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8728                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8729                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8730                         I40E_INSET_IPV6_NEXT_HDR},
8731                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8732                         I40E_INSET_IPV6_HOP_LIMIT},
8733                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8734                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8735                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8736                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8737                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8738                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8739                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8740                         I40E_INSET_SCTP_VT},
8741                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8742                         I40E_INSET_TUNNEL_DMAC},
8743                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8744                         I40E_INSET_VLAN_TUNNEL},
8745                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8746                         I40E_INSET_TUNNEL_ID},
8747                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8748                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8749                         I40E_INSET_FLEX_PAYLOAD_W1},
8750                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8751                         I40E_INSET_FLEX_PAYLOAD_W2},
8752                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8753                         I40E_INSET_FLEX_PAYLOAD_W3},
8754                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8755                         I40E_INSET_FLEX_PAYLOAD_W4},
8756                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8757                         I40E_INSET_FLEX_PAYLOAD_W5},
8758                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8759                         I40E_INSET_FLEX_PAYLOAD_W6},
8760                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8761                         I40E_INSET_FLEX_PAYLOAD_W7},
8762                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8763                         I40E_INSET_FLEX_PAYLOAD_W8},
8764         };
8765
8766         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8767                 return ret;
8768
8769         /* Only one item allowed for default or all */
8770         if (size == 1) {
8771                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8772                         *inset = i40e_get_default_input_set(pctype);
8773                         return 0;
8774                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8775                         *inset = I40E_INSET_NONE;
8776                         return 0;
8777                 }
8778         }
8779
8780         for (i = 0, *inset = 0; i < size; i++) {
8781                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8782                         if (field[i] == inset_convert_table[j].field) {
8783                                 *inset |= inset_convert_table[j].inset;
8784                                 break;
8785                         }
8786                 }
8787
8788                 /* It contains unsupported input set, return immediately */
8789                 if (j == RTE_DIM(inset_convert_table))
8790                         return ret;
8791         }
8792
8793         return 0;
8794 }
8795
8796 /**
8797  * Translate the input set from bit masks to register aware bit masks
8798  * and vice versa
8799  */
8800 uint64_t
8801 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8802 {
8803         uint64_t val = 0;
8804         uint16_t i;
8805
8806         struct inset_map {
8807                 uint64_t inset;
8808                 uint64_t inset_reg;
8809         };
8810
8811         static const struct inset_map inset_map_common[] = {
8812                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8813                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8814                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8815                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8816                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8817                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8818                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8819                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8820                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8821                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8822                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8823                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8824                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8825                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8826                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8827                 {I40E_INSET_TUNNEL_DMAC,
8828                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8829                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8830                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8831                 {I40E_INSET_TUNNEL_SRC_PORT,
8832                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8833                 {I40E_INSET_TUNNEL_DST_PORT,
8834                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8835                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8836                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8837                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8838                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8839                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8840                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8841                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8842                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8843                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8844         };
8845
8846     /* some different registers map in x722*/
8847         static const struct inset_map inset_map_diff_x722[] = {
8848                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8849                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8850                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8851                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8852         };
8853
8854         static const struct inset_map inset_map_diff_not_x722[] = {
8855                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8856                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8857                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8858                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8859         };
8860
8861         if (input == 0)
8862                 return val;
8863
8864         /* Translate input set to register aware inset */
8865         if (type == I40E_MAC_X722) {
8866                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8867                         if (input & inset_map_diff_x722[i].inset)
8868                                 val |= inset_map_diff_x722[i].inset_reg;
8869                 }
8870         } else {
8871                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8872                         if (input & inset_map_diff_not_x722[i].inset)
8873                                 val |= inset_map_diff_not_x722[i].inset_reg;
8874                 }
8875         }
8876
8877         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8878                 if (input & inset_map_common[i].inset)
8879                         val |= inset_map_common[i].inset_reg;
8880         }
8881
8882         return val;
8883 }
8884
8885 int
8886 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8887 {
8888         uint8_t i, idx = 0;
8889         uint64_t inset_need_mask = inset;
8890
8891         static const struct {
8892                 uint64_t inset;
8893                 uint32_t mask;
8894         } inset_mask_map[] = {
8895                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8896                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8897                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8898                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8899                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8900                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8901                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8902                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8903         };
8904
8905         if (!inset || !mask || !nb_elem)
8906                 return 0;
8907
8908         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8909                 /* Clear the inset bit, if no MASK is required,
8910                  * for example proto + ttl
8911                  */
8912                 if ((inset & inset_mask_map[i].inset) ==
8913                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8914                         inset_need_mask &= ~inset_mask_map[i].inset;
8915                 if (!inset_need_mask)
8916                         return 0;
8917         }
8918         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8919                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8920                     inset_mask_map[i].inset) {
8921                         if (idx >= nb_elem) {
8922                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8923                                 return -EINVAL;
8924                         }
8925                         mask[idx] = inset_mask_map[i].mask;
8926                         idx++;
8927                 }
8928         }
8929
8930         return idx;
8931 }
8932
8933 void
8934 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8935 {
8936         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8937
8938         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8939         if (reg != val)
8940                 i40e_write_rx_ctl(hw, addr, val);
8941         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8942                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8943 }
8944
8945 void
8946 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8947 {
8948         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8949
8950         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8951         if (reg != val)
8952                 i40e_write_global_rx_ctl(hw, addr, val);
8953         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8954                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8955 }
8956
8957 static void
8958 i40e_filter_input_set_init(struct i40e_pf *pf)
8959 {
8960         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8961         enum i40e_filter_pctype pctype;
8962         uint64_t input_set, inset_reg;
8963         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8964         int num, i;
8965         uint16_t flow_type;
8966
8967         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8968              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8969                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8970
8971                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8972                         continue;
8973
8974                 input_set = i40e_get_default_input_set(pctype);
8975
8976                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8977                                                    I40E_INSET_MASK_NUM_REG);
8978                 if (num < 0)
8979                         return;
8980                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8981                                         input_set);
8982
8983                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8984                                       (uint32_t)(inset_reg & UINT32_MAX));
8985                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8986                                      (uint32_t)((inset_reg >>
8987                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8988                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8989                                       (uint32_t)(inset_reg & UINT32_MAX));
8990                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8991                                      (uint32_t)((inset_reg >>
8992                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8993
8994                 for (i = 0; i < num; i++) {
8995                         i40e_check_write_global_reg(hw,
8996                                                     I40E_GLQF_FD_MSK(i, pctype),
8997                                                     mask_reg[i]);
8998                         i40e_check_write_global_reg(hw,
8999                                                   I40E_GLQF_HASH_MSK(i, pctype),
9000                                                   mask_reg[i]);
9001                 }
9002                 /*clear unused mask registers of the pctype */
9003                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9004                         i40e_check_write_global_reg(hw,
9005                                                     I40E_GLQF_FD_MSK(i, pctype),
9006                                                     0);
9007                         i40e_check_write_global_reg(hw,
9008                                                   I40E_GLQF_HASH_MSK(i, pctype),
9009                                                   0);
9010                 }
9011                 I40E_WRITE_FLUSH(hw);
9012
9013                 /* store the default input set */
9014                 pf->hash_input_set[pctype] = input_set;
9015                 pf->fdir.input_set[pctype] = input_set;
9016         }
9017
9018         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9019         i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9020         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9021 }
9022
9023 int
9024 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9025                          struct rte_eth_input_set_conf *conf)
9026 {
9027         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9028         enum i40e_filter_pctype pctype;
9029         uint64_t input_set, inset_reg = 0;
9030         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9031         int ret, i, num;
9032
9033         if (!conf) {
9034                 PMD_DRV_LOG(ERR, "Invalid pointer");
9035                 return -EFAULT;
9036         }
9037         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9038             conf->op != RTE_ETH_INPUT_SET_ADD) {
9039                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9040                 return -EINVAL;
9041         }
9042
9043         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9044         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9045                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9046                 return -EINVAL;
9047         }
9048
9049         if (hw->mac.type == I40E_MAC_X722) {
9050                 /* get translated pctype value in fd pctype register */
9051                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9052                         I40E_GLQF_FD_PCTYPES((int)pctype));
9053         }
9054
9055         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9056                                    conf->inset_size);
9057         if (ret) {
9058                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9059                 return -EINVAL;
9060         }
9061
9062         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9063                 /* get inset value in register */
9064                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9065                 inset_reg <<= I40E_32_BIT_WIDTH;
9066                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9067                 input_set |= pf->hash_input_set[pctype];
9068         }
9069         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9070                                            I40E_INSET_MASK_NUM_REG);
9071         if (num < 0)
9072                 return -EINVAL;
9073
9074         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9075
9076         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9077                                     (uint32_t)(inset_reg & UINT32_MAX));
9078         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9079                                     (uint32_t)((inset_reg >>
9080                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9081         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9082
9083         for (i = 0; i < num; i++)
9084                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9085                                             mask_reg[i]);
9086         /*clear unused mask registers of the pctype */
9087         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9088                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9089                                             0);
9090         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9091         I40E_WRITE_FLUSH(hw);
9092
9093         pf->hash_input_set[pctype] = input_set;
9094         return 0;
9095 }
9096
9097 int
9098 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9099                          struct rte_eth_input_set_conf *conf)
9100 {
9101         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9102         enum i40e_filter_pctype pctype;
9103         uint64_t input_set, inset_reg = 0;
9104         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9105         int ret, i, num;
9106
9107         if (!hw || !conf) {
9108                 PMD_DRV_LOG(ERR, "Invalid pointer");
9109                 return -EFAULT;
9110         }
9111         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9112             conf->op != RTE_ETH_INPUT_SET_ADD) {
9113                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9114                 return -EINVAL;
9115         }
9116
9117         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9118
9119         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9120                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9121                 return -EINVAL;
9122         }
9123
9124         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9125                                    conf->inset_size);
9126         if (ret) {
9127                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9128                 return -EINVAL;
9129         }
9130
9131         /* get inset value in register */
9132         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9133         inset_reg <<= I40E_32_BIT_WIDTH;
9134         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9135
9136         /* Can not change the inset reg for flex payload for fdir,
9137          * it is done by writing I40E_PRTQF_FD_FLXINSET
9138          * in i40e_set_flex_mask_on_pctype.
9139          */
9140         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9141                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9142         else
9143                 input_set |= pf->fdir.input_set[pctype];
9144         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9145                                            I40E_INSET_MASK_NUM_REG);
9146         if (num < 0)
9147                 return -EINVAL;
9148
9149         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9150
9151         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9152                               (uint32_t)(inset_reg & UINT32_MAX));
9153         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9154                              (uint32_t)((inset_reg >>
9155                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9156
9157         for (i = 0; i < num; i++)
9158                 i40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9159                                             mask_reg[i]);
9160         /*clear unused mask registers of the pctype */
9161         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9162                 i40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9163                                             0);
9164         i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9165         I40E_WRITE_FLUSH(hw);
9166
9167         pf->fdir.input_set[pctype] = input_set;
9168         return 0;
9169 }
9170
9171 static int
9172 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9173 {
9174         int ret = 0;
9175
9176         if (!hw || !info) {
9177                 PMD_DRV_LOG(ERR, "Invalid pointer");
9178                 return -EFAULT;
9179         }
9180
9181         switch (info->info_type) {
9182         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9183                 i40e_get_symmetric_hash_enable_per_port(hw,
9184                                         &(info->info.enable));
9185                 break;
9186         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9187                 ret = i40e_get_hash_filter_global_config(hw,
9188                                 &(info->info.global_conf));
9189                 break;
9190         default:
9191                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9192                                                         info->info_type);
9193                 ret = -EINVAL;
9194                 break;
9195         }
9196
9197         return ret;
9198 }
9199
9200 static int
9201 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9202 {
9203         int ret = 0;
9204
9205         if (!hw || !info) {
9206                 PMD_DRV_LOG(ERR, "Invalid pointer");
9207                 return -EFAULT;
9208         }
9209
9210         switch (info->info_type) {
9211         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9212                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9213                 break;
9214         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9215                 ret = i40e_set_hash_filter_global_config(hw,
9216                                 &(info->info.global_conf));
9217                 break;
9218         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9219                 ret = i40e_hash_filter_inset_select(hw,
9220                                                &(info->info.input_set_conf));
9221                 break;
9222
9223         default:
9224                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9225                                                         info->info_type);
9226                 ret = -EINVAL;
9227                 break;
9228         }
9229
9230         return ret;
9231 }
9232
9233 /* Operations for hash function */
9234 static int
9235 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9236                       enum rte_filter_op filter_op,
9237                       void *arg)
9238 {
9239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9240         int ret = 0;
9241
9242         switch (filter_op) {
9243         case RTE_ETH_FILTER_NOP:
9244                 break;
9245         case RTE_ETH_FILTER_GET:
9246                 ret = i40e_hash_filter_get(hw,
9247                         (struct rte_eth_hash_filter_info *)arg);
9248                 break;
9249         case RTE_ETH_FILTER_SET:
9250                 ret = i40e_hash_filter_set(hw,
9251                         (struct rte_eth_hash_filter_info *)arg);
9252                 break;
9253         default:
9254                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9255                                                                 filter_op);
9256                 ret = -ENOTSUP;
9257                 break;
9258         }
9259
9260         return ret;
9261 }
9262
9263 /* Convert ethertype filter structure */
9264 static int
9265 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9266                               struct i40e_ethertype_filter *filter)
9267 {
9268         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9269         filter->input.ether_type = input->ether_type;
9270         filter->flags = input->flags;
9271         filter->queue = input->queue;
9272
9273         return 0;
9274 }
9275
9276 /* Check if there exists the ehtertype filter */
9277 struct i40e_ethertype_filter *
9278 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9279                                 const struct i40e_ethertype_filter_input *input)
9280 {
9281         int ret;
9282
9283         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9284         if (ret < 0)
9285                 return NULL;
9286
9287         return ethertype_rule->hash_map[ret];
9288 }
9289
9290 /* Add ethertype filter in SW list */
9291 static int
9292 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9293                                 struct i40e_ethertype_filter *filter)
9294 {
9295         struct i40e_ethertype_rule *rule = &pf->ethertype;
9296         int ret;
9297
9298         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9299         if (ret < 0) {
9300                 PMD_DRV_LOG(ERR,
9301                             "Failed to insert ethertype filter"
9302                             " to hash table %d!",
9303                             ret);
9304                 return ret;
9305         }
9306         rule->hash_map[ret] = filter;
9307
9308         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9309
9310         return 0;
9311 }
9312
9313 /* Delete ethertype filter in SW list */
9314 int
9315 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9316                              struct i40e_ethertype_filter_input *input)
9317 {
9318         struct i40e_ethertype_rule *rule = &pf->ethertype;
9319         struct i40e_ethertype_filter *filter;
9320         int ret;
9321
9322         ret = rte_hash_del_key(rule->hash_table, input);
9323         if (ret < 0) {
9324                 PMD_DRV_LOG(ERR,
9325                             "Failed to delete ethertype filter"
9326                             " to hash table %d!",
9327                             ret);
9328                 return ret;
9329         }
9330         filter = rule->hash_map[ret];
9331         rule->hash_map[ret] = NULL;
9332
9333         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9334         rte_free(filter);
9335
9336         return 0;
9337 }
9338
9339 /*
9340  * Configure ethertype filter, which can director packet by filtering
9341  * with mac address and ether_type or only ether_type
9342  */
9343 int
9344 i40e_ethertype_filter_set(struct i40e_pf *pf,
9345                         struct rte_eth_ethertype_filter *filter,
9346                         bool add)
9347 {
9348         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9349         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9350         struct i40e_ethertype_filter *ethertype_filter, *node;
9351         struct i40e_ethertype_filter check_filter;
9352         struct i40e_control_filter_stats stats;
9353         uint16_t flags = 0;
9354         int ret;
9355
9356         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9357                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9358                 return -EINVAL;
9359         }
9360         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9361                 filter->ether_type == ETHER_TYPE_IPv6) {
9362                 PMD_DRV_LOG(ERR,
9363                         "unsupported ether_type(0x%04x) in control packet filter.",
9364                         filter->ether_type);
9365                 return -EINVAL;
9366         }
9367         if (filter->ether_type == ETHER_TYPE_VLAN)
9368                 PMD_DRV_LOG(WARNING,
9369                         "filter vlan ether_type in first tag is not supported.");
9370
9371         /* Check if there is the filter in SW list */
9372         memset(&check_filter, 0, sizeof(check_filter));
9373         i40e_ethertype_filter_convert(filter, &check_filter);
9374         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9375                                                &check_filter.input);
9376         if (add && node) {
9377                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9378                 return -EINVAL;
9379         }
9380
9381         if (!add && !node) {
9382                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9383                 return -EINVAL;
9384         }
9385
9386         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9387                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9388         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9389                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9390         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9391
9392         memset(&stats, 0, sizeof(stats));
9393         ret = i40e_aq_add_rem_control_packet_filter(hw,
9394                         filter->mac_addr.addr_bytes,
9395                         filter->ether_type, flags,
9396                         pf->main_vsi->seid,
9397                         filter->queue, add, &stats, NULL);
9398
9399         PMD_DRV_LOG(INFO,
9400                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9401                 ret, stats.mac_etype_used, stats.etype_used,
9402                 stats.mac_etype_free, stats.etype_free);
9403         if (ret < 0)
9404                 return -ENOSYS;
9405
9406         /* Add or delete a filter in SW list */
9407         if (add) {
9408                 ethertype_filter = rte_zmalloc("ethertype_filter",
9409                                        sizeof(*ethertype_filter), 0);
9410                 if (ethertype_filter == NULL) {
9411                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9412                         return -ENOMEM;
9413                 }
9414
9415                 rte_memcpy(ethertype_filter, &check_filter,
9416                            sizeof(check_filter));
9417                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9418                 if (ret < 0)
9419                         rte_free(ethertype_filter);
9420         } else {
9421                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9422         }
9423
9424         return ret;
9425 }
9426
9427 /*
9428  * Handle operations for ethertype filter.
9429  */
9430 static int
9431 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9432                                 enum rte_filter_op filter_op,
9433                                 void *arg)
9434 {
9435         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9436         int ret = 0;
9437
9438         if (filter_op == RTE_ETH_FILTER_NOP)
9439                 return ret;
9440
9441         if (arg == NULL) {
9442                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9443                             filter_op);
9444                 return -EINVAL;
9445         }
9446
9447         switch (filter_op) {
9448         case RTE_ETH_FILTER_ADD:
9449                 ret = i40e_ethertype_filter_set(pf,
9450                         (struct rte_eth_ethertype_filter *)arg,
9451                         TRUE);
9452                 break;
9453         case RTE_ETH_FILTER_DELETE:
9454                 ret = i40e_ethertype_filter_set(pf,
9455                         (struct rte_eth_ethertype_filter *)arg,
9456                         FALSE);
9457                 break;
9458         default:
9459                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9460                 ret = -ENOSYS;
9461                 break;
9462         }
9463         return ret;
9464 }
9465
9466 static int
9467 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9468                      enum rte_filter_type filter_type,
9469                      enum rte_filter_op filter_op,
9470                      void *arg)
9471 {
9472         int ret = 0;
9473
9474         if (dev == NULL)
9475                 return -EINVAL;
9476
9477         switch (filter_type) {
9478         case RTE_ETH_FILTER_NONE:
9479                 /* For global configuration */
9480                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9481                 break;
9482         case RTE_ETH_FILTER_HASH:
9483                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9484                 break;
9485         case RTE_ETH_FILTER_MACVLAN:
9486                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9487                 break;
9488         case RTE_ETH_FILTER_ETHERTYPE:
9489                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9490                 break;
9491         case RTE_ETH_FILTER_TUNNEL:
9492                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9493                 break;
9494         case RTE_ETH_FILTER_FDIR:
9495                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9496                 break;
9497         case RTE_ETH_FILTER_GENERIC:
9498                 if (filter_op != RTE_ETH_FILTER_GET)
9499                         return -EINVAL;
9500                 *(const void **)arg = &i40e_flow_ops;
9501                 break;
9502         default:
9503                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9504                                                         filter_type);
9505                 ret = -EINVAL;
9506                 break;
9507         }
9508
9509         return ret;
9510 }
9511
9512 /*
9513  * Check and enable Extended Tag.
9514  * Enabling Extended Tag is important for 40G performance.
9515  */
9516 static void
9517 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9518 {
9519         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9520         uint32_t buf = 0;
9521         int ret;
9522
9523         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9524                                       PCI_DEV_CAP_REG);
9525         if (ret < 0) {
9526                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9527                             PCI_DEV_CAP_REG);
9528                 return;
9529         }
9530         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9531                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9532                 return;
9533         }
9534
9535         buf = 0;
9536         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9537                                       PCI_DEV_CTRL_REG);
9538         if (ret < 0) {
9539                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9540                             PCI_DEV_CTRL_REG);
9541                 return;
9542         }
9543         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9544                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9545                 return;
9546         }
9547         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9548         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9549                                        PCI_DEV_CTRL_REG);
9550         if (ret < 0) {
9551                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9552                             PCI_DEV_CTRL_REG);
9553                 return;
9554         }
9555 }
9556
9557 /*
9558  * As some registers wouldn't be reset unless a global hardware reset,
9559  * hardware initialization is needed to put those registers into an
9560  * expected initial state.
9561  */
9562 static void
9563 i40e_hw_init(struct rte_eth_dev *dev)
9564 {
9565         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9566
9567         i40e_enable_extended_tag(dev);
9568
9569         /* clear the PF Queue Filter control register */
9570         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9571
9572         /* Disable symmetric hash per port */
9573         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9574 }
9575
9576 /*
9577  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9578  * however this function will return only one highest pctype index,
9579  * which is not quite correct. This is known problem of i40e driver
9580  * and needs to be fixed later.
9581  */
9582 enum i40e_filter_pctype
9583 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9584 {
9585         int i;
9586         uint64_t pctype_mask;
9587
9588         if (flow_type < I40E_FLOW_TYPE_MAX) {
9589                 pctype_mask = adapter->pctypes_tbl[flow_type];
9590                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9591                         if (pctype_mask & (1ULL << i))
9592                                 return (enum i40e_filter_pctype)i;
9593                 }
9594         }
9595         return I40E_FILTER_PCTYPE_INVALID;
9596 }
9597
9598 uint16_t
9599 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9600                         enum i40e_filter_pctype pctype)
9601 {
9602         uint16_t flowtype;
9603         uint64_t pctype_mask = 1ULL << pctype;
9604
9605         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9606              flowtype++) {
9607                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9608                         return flowtype;
9609         }
9610
9611         return RTE_ETH_FLOW_UNKNOWN;
9612 }
9613
9614 /*
9615  * On X710, performance number is far from the expectation on recent firmware
9616  * versions; on XL710, performance number is also far from the expectation on
9617  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9618  * mode is enabled and port MAC address is equal to the packet destination MAC
9619  * address. The fix for this issue may not be integrated in the following
9620  * firmware version. So the workaround in software driver is needed. It needs
9621  * to modify the initial values of 3 internal only registers for both X710 and
9622  * XL710. Note that the values for X710 or XL710 could be different, and the
9623  * workaround can be removed when it is fixed in firmware in the future.
9624  */
9625
9626 /* For both X710 and XL710 */
9627 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9628 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9629 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9630
9631 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9632 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9633
9634 /* For X722 */
9635 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9636 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9637
9638 /* For X710 */
9639 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9640 /* For XL710 */
9641 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9642 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9643
9644 static int
9645 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9646 {
9647         enum i40e_status_code status;
9648         struct i40e_aq_get_phy_abilities_resp phy_ab;
9649         int ret = -ENOTSUP;
9650         int retries = 0;
9651
9652         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9653                                               NULL);
9654
9655         while (status) {
9656                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9657                         status);
9658                 retries++;
9659                 rte_delay_us(100000);
9660                 if  (retries < 5)
9661                         status = i40e_aq_get_phy_capabilities(hw, false,
9662                                         true, &phy_ab, NULL);
9663                 else
9664                         return ret;
9665         }
9666         return 0;
9667 }
9668
9669 static void
9670 i40e_configure_registers(struct i40e_hw *hw)
9671 {
9672         static struct {
9673                 uint32_t addr;
9674                 uint64_t val;
9675         } reg_table[] = {
9676                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9677                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9678                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9679         };
9680         uint64_t reg;
9681         uint32_t i;
9682         int ret;
9683
9684         for (i = 0; i < RTE_DIM(reg_table); i++) {
9685                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9686                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9687                                 reg_table[i].val =
9688                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9689                         else /* For X710/XL710/XXV710 */
9690                                 if (hw->aq.fw_maj_ver < 6)
9691                                         reg_table[i].val =
9692                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9693                                 else
9694                                         reg_table[i].val =
9695                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9696                 }
9697
9698                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9699                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9700                                 reg_table[i].val =
9701                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9702                         else /* For X710/XL710/XXV710 */
9703                                 reg_table[i].val =
9704                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9705                 }
9706
9707                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9708                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9709                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9710                                 reg_table[i].val =
9711                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9712                         else /* For X710 */
9713                                 reg_table[i].val =
9714                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9715                 }
9716
9717                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9718                                                         &reg, NULL);
9719                 if (ret < 0) {
9720                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9721                                                         reg_table[i].addr);
9722                         break;
9723                 }
9724                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9725                                                 reg_table[i].addr, reg);
9726                 if (reg == reg_table[i].val)
9727                         continue;
9728
9729                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9730                                                 reg_table[i].val, NULL);
9731                 if (ret < 0) {
9732                         PMD_DRV_LOG(ERR,
9733                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9734                                 reg_table[i].val, reg_table[i].addr);
9735                         break;
9736                 }
9737                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9738                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9739         }
9740 }
9741
9742 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9743 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9744 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9745 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9746 static int
9747 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9748 {
9749         uint32_t reg;
9750         int ret;
9751
9752         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9753                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9754                 return -EINVAL;
9755         }
9756
9757         /* Configure for double VLAN RX stripping */
9758         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9759         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9760                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9761                 ret = i40e_aq_debug_write_register(hw,
9762                                                    I40E_VSI_TSR(vsi->vsi_id),
9763                                                    reg, NULL);
9764                 if (ret < 0) {
9765                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9766                                     vsi->vsi_id);
9767                         return I40E_ERR_CONFIG;
9768                 }
9769         }
9770
9771         /* Configure for double VLAN TX insertion */
9772         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9773         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9774                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9775                 ret = i40e_aq_debug_write_register(hw,
9776                                                    I40E_VSI_L2TAGSTXVALID(
9777                                                    vsi->vsi_id), reg, NULL);
9778                 if (ret < 0) {
9779                         PMD_DRV_LOG(ERR,
9780                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9781                                 vsi->vsi_id);
9782                         return I40E_ERR_CONFIG;
9783                 }
9784         }
9785
9786         return 0;
9787 }
9788
9789 /**
9790  * i40e_aq_add_mirror_rule
9791  * @hw: pointer to the hardware structure
9792  * @seid: VEB seid to add mirror rule to
9793  * @dst_id: destination vsi seid
9794  * @entries: Buffer which contains the entities to be mirrored
9795  * @count: number of entities contained in the buffer
9796  * @rule_id:the rule_id of the rule to be added
9797  *
9798  * Add a mirror rule for a given veb.
9799  *
9800  **/
9801 static enum i40e_status_code
9802 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9803                         uint16_t seid, uint16_t dst_id,
9804                         uint16_t rule_type, uint16_t *entries,
9805                         uint16_t count, uint16_t *rule_id)
9806 {
9807         struct i40e_aq_desc desc;
9808         struct i40e_aqc_add_delete_mirror_rule cmd;
9809         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9810                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9811                 &desc.params.raw;
9812         uint16_t buff_len;
9813         enum i40e_status_code status;
9814
9815         i40e_fill_default_direct_cmd_desc(&desc,
9816                                           i40e_aqc_opc_add_mirror_rule);
9817         memset(&cmd, 0, sizeof(cmd));
9818
9819         buff_len = sizeof(uint16_t) * count;
9820         desc.datalen = rte_cpu_to_le_16(buff_len);
9821         if (buff_len > 0)
9822                 desc.flags |= rte_cpu_to_le_16(
9823                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9824         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9825                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9826         cmd.num_entries = rte_cpu_to_le_16(count);
9827         cmd.seid = rte_cpu_to_le_16(seid);
9828         cmd.destination = rte_cpu_to_le_16(dst_id);
9829
9830         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9831         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9832         PMD_DRV_LOG(INFO,
9833                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9834                 hw->aq.asq_last_status, resp->rule_id,
9835                 resp->mirror_rules_used, resp->mirror_rules_free);
9836         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9837
9838         return status;
9839 }
9840
9841 /**
9842  * i40e_aq_del_mirror_rule
9843  * @hw: pointer to the hardware structure
9844  * @seid: VEB seid to add mirror rule to
9845  * @entries: Buffer which contains the entities to be mirrored
9846  * @count: number of entities contained in the buffer
9847  * @rule_id:the rule_id of the rule to be delete
9848  *
9849  * Delete a mirror rule for a given veb.
9850  *
9851  **/
9852 static enum i40e_status_code
9853 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9854                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9855                 uint16_t count, uint16_t rule_id)
9856 {
9857         struct i40e_aq_desc desc;
9858         struct i40e_aqc_add_delete_mirror_rule cmd;
9859         uint16_t buff_len = 0;
9860         enum i40e_status_code status;
9861         void *buff = NULL;
9862
9863         i40e_fill_default_direct_cmd_desc(&desc,
9864                                           i40e_aqc_opc_delete_mirror_rule);
9865         memset(&cmd, 0, sizeof(cmd));
9866         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9867                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9868                                                           I40E_AQ_FLAG_RD));
9869                 cmd.num_entries = count;
9870                 buff_len = sizeof(uint16_t) * count;
9871                 desc.datalen = rte_cpu_to_le_16(buff_len);
9872                 buff = (void *)entries;
9873         } else
9874                 /* rule id is filled in destination field for deleting mirror rule */
9875                 cmd.destination = rte_cpu_to_le_16(rule_id);
9876
9877         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9878                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9879         cmd.seid = rte_cpu_to_le_16(seid);
9880
9881         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9882         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9883
9884         return status;
9885 }
9886
9887 /**
9888  * i40e_mirror_rule_set
9889  * @dev: pointer to the hardware structure
9890  * @mirror_conf: mirror rule info
9891  * @sw_id: mirror rule's sw_id
9892  * @on: enable/disable
9893  *
9894  * set a mirror rule.
9895  *
9896  **/
9897 static int
9898 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9899                         struct rte_eth_mirror_conf *mirror_conf,
9900                         uint8_t sw_id, uint8_t on)
9901 {
9902         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9903         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9904         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9905         struct i40e_mirror_rule *parent = NULL;
9906         uint16_t seid, dst_seid, rule_id;
9907         uint16_t i, j = 0;
9908         int ret;
9909
9910         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9911
9912         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9913                 PMD_DRV_LOG(ERR,
9914                         "mirror rule can not be configured without veb or vfs.");
9915                 return -ENOSYS;
9916         }
9917         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9918                 PMD_DRV_LOG(ERR, "mirror table is full.");
9919                 return -ENOSPC;
9920         }
9921         if (mirror_conf->dst_pool > pf->vf_num) {
9922                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9923                                  mirror_conf->dst_pool);
9924                 return -EINVAL;
9925         }
9926
9927         seid = pf->main_vsi->veb->seid;
9928
9929         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9930                 if (sw_id <= it->index) {
9931                         mirr_rule = it;
9932                         break;
9933                 }
9934                 parent = it;
9935         }
9936         if (mirr_rule && sw_id == mirr_rule->index) {
9937                 if (on) {
9938                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9939                         return -EEXIST;
9940                 } else {
9941                         ret = i40e_aq_del_mirror_rule(hw, seid,
9942                                         mirr_rule->rule_type,
9943                                         mirr_rule->entries,
9944                                         mirr_rule->num_entries, mirr_rule->id);
9945                         if (ret < 0) {
9946                                 PMD_DRV_LOG(ERR,
9947                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9948                                         ret, hw->aq.asq_last_status);
9949                                 return -ENOSYS;
9950                         }
9951                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9952                         rte_free(mirr_rule);
9953                         pf->nb_mirror_rule--;
9954                         return 0;
9955                 }
9956         } else if (!on) {
9957                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9958                 return -ENOENT;
9959         }
9960
9961         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9962                                 sizeof(struct i40e_mirror_rule) , 0);
9963         if (!mirr_rule) {
9964                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9965                 return I40E_ERR_NO_MEMORY;
9966         }
9967         switch (mirror_conf->rule_type) {
9968         case ETH_MIRROR_VLAN:
9969                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9970                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9971                                 mirr_rule->entries[j] =
9972                                         mirror_conf->vlan.vlan_id[i];
9973                                 j++;
9974                         }
9975                 }
9976                 if (j == 0) {
9977                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9978                         rte_free(mirr_rule);
9979                         return -EINVAL;
9980                 }
9981                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9982                 break;
9983         case ETH_MIRROR_VIRTUAL_POOL_UP:
9984         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9985                 /* check if the specified pool bit is out of range */
9986                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9987                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9988                         rte_free(mirr_rule);
9989                         return -EINVAL;
9990                 }
9991                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9992                         if (mirror_conf->pool_mask & (1ULL << i)) {
9993                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9994                                 j++;
9995                         }
9996                 }
9997                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9998                         /* add pf vsi to entries */
9999                         mirr_rule->entries[j] = pf->main_vsi_seid;
10000                         j++;
10001                 }
10002                 if (j == 0) {
10003                         PMD_DRV_LOG(ERR, "pool is not specified.");
10004                         rte_free(mirr_rule);
10005                         return -EINVAL;
10006                 }
10007                 /* egress and ingress in aq commands means from switch but not port */
10008                 mirr_rule->rule_type =
10009                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10010                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10011                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10012                 break;
10013         case ETH_MIRROR_UPLINK_PORT:
10014                 /* egress and ingress in aq commands means from switch but not port*/
10015                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10016                 break;
10017         case ETH_MIRROR_DOWNLINK_PORT:
10018                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10019                 break;
10020         default:
10021                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10022                         mirror_conf->rule_type);
10023                 rte_free(mirr_rule);
10024                 return -EINVAL;
10025         }
10026
10027         /* If the dst_pool is equal to vf_num, consider it as PF */
10028         if (mirror_conf->dst_pool == pf->vf_num)
10029                 dst_seid = pf->main_vsi_seid;
10030         else
10031                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10032
10033         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10034                                       mirr_rule->rule_type, mirr_rule->entries,
10035                                       j, &rule_id);
10036         if (ret < 0) {
10037                 PMD_DRV_LOG(ERR,
10038                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10039                         ret, hw->aq.asq_last_status);
10040                 rte_free(mirr_rule);
10041                 return -ENOSYS;
10042         }
10043
10044         mirr_rule->index = sw_id;
10045         mirr_rule->num_entries = j;
10046         mirr_rule->id = rule_id;
10047         mirr_rule->dst_vsi_seid = dst_seid;
10048
10049         if (parent)
10050                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10051         else
10052                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10053
10054         pf->nb_mirror_rule++;
10055         return 0;
10056 }
10057
10058 /**
10059  * i40e_mirror_rule_reset
10060  * @dev: pointer to the device
10061  * @sw_id: mirror rule's sw_id
10062  *
10063  * reset a mirror rule.
10064  *
10065  **/
10066 static int
10067 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10068 {
10069         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10070         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10071         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10072         uint16_t seid;
10073         int ret;
10074
10075         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10076
10077         seid = pf->main_vsi->veb->seid;
10078
10079         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10080                 if (sw_id == it->index) {
10081                         mirr_rule = it;
10082                         break;
10083                 }
10084         }
10085         if (mirr_rule) {
10086                 ret = i40e_aq_del_mirror_rule(hw, seid,
10087                                 mirr_rule->rule_type,
10088                                 mirr_rule->entries,
10089                                 mirr_rule->num_entries, mirr_rule->id);
10090                 if (ret < 0) {
10091                         PMD_DRV_LOG(ERR,
10092                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10093                                 ret, hw->aq.asq_last_status);
10094                         return -ENOSYS;
10095                 }
10096                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10097                 rte_free(mirr_rule);
10098                 pf->nb_mirror_rule--;
10099         } else {
10100                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10101                 return -ENOENT;
10102         }
10103         return 0;
10104 }
10105
10106 static uint64_t
10107 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10108 {
10109         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10110         uint64_t systim_cycles;
10111
10112         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10113         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10114                         << 32;
10115
10116         return systim_cycles;
10117 }
10118
10119 static uint64_t
10120 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10121 {
10122         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10123         uint64_t rx_tstamp;
10124
10125         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10126         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10127                         << 32;
10128
10129         return rx_tstamp;
10130 }
10131
10132 static uint64_t
10133 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10134 {
10135         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10136         uint64_t tx_tstamp;
10137
10138         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10139         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10140                         << 32;
10141
10142         return tx_tstamp;
10143 }
10144
10145 static void
10146 i40e_start_timecounters(struct rte_eth_dev *dev)
10147 {
10148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10149         struct i40e_adapter *adapter =
10150                         (struct i40e_adapter *)dev->data->dev_private;
10151         struct rte_eth_link link;
10152         uint32_t tsync_inc_l;
10153         uint32_t tsync_inc_h;
10154
10155         /* Get current link speed. */
10156         memset(&link, 0, sizeof(link));
10157         i40e_dev_link_update(dev, 1);
10158         rte_i40e_dev_atomic_read_link_status(dev, &link);
10159
10160         switch (link.link_speed) {
10161         case ETH_SPEED_NUM_40G:
10162                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10163                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10164                 break;
10165         case ETH_SPEED_NUM_10G:
10166                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10167                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10168                 break;
10169         case ETH_SPEED_NUM_1G:
10170                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10171                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10172                 break;
10173         default:
10174                 tsync_inc_l = 0x0;
10175                 tsync_inc_h = 0x0;
10176         }
10177
10178         /* Set the timesync increment value. */
10179         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10180         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10181
10182         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10183         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10184         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10185
10186         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10187         adapter->systime_tc.cc_shift = 0;
10188         adapter->systime_tc.nsec_mask = 0;
10189
10190         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10191         adapter->rx_tstamp_tc.cc_shift = 0;
10192         adapter->rx_tstamp_tc.nsec_mask = 0;
10193
10194         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10195         adapter->tx_tstamp_tc.cc_shift = 0;
10196         adapter->tx_tstamp_tc.nsec_mask = 0;
10197 }
10198
10199 static int
10200 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10201 {
10202         struct i40e_adapter *adapter =
10203                         (struct i40e_adapter *)dev->data->dev_private;
10204
10205         adapter->systime_tc.nsec += delta;
10206         adapter->rx_tstamp_tc.nsec += delta;
10207         adapter->tx_tstamp_tc.nsec += delta;
10208
10209         return 0;
10210 }
10211
10212 static int
10213 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10214 {
10215         uint64_t ns;
10216         struct i40e_adapter *adapter =
10217                         (struct i40e_adapter *)dev->data->dev_private;
10218
10219         ns = rte_timespec_to_ns(ts);
10220
10221         /* Set the timecounters to a new value. */
10222         adapter->systime_tc.nsec = ns;
10223         adapter->rx_tstamp_tc.nsec = ns;
10224         adapter->tx_tstamp_tc.nsec = ns;
10225
10226         return 0;
10227 }
10228
10229 static int
10230 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10231 {
10232         uint64_t ns, systime_cycles;
10233         struct i40e_adapter *adapter =
10234                         (struct i40e_adapter *)dev->data->dev_private;
10235
10236         systime_cycles = i40e_read_systime_cyclecounter(dev);
10237         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10238         *ts = rte_ns_to_timespec(ns);
10239
10240         return 0;
10241 }
10242
10243 static int
10244 i40e_timesync_enable(struct rte_eth_dev *dev)
10245 {
10246         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10247         uint32_t tsync_ctl_l;
10248         uint32_t tsync_ctl_h;
10249
10250         /* Stop the timesync system time. */
10251         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10252         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10253         /* Reset the timesync system time value. */
10254         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10255         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10256
10257         i40e_start_timecounters(dev);
10258
10259         /* Clear timesync registers. */
10260         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10261         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10262         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10263         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10264         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10265         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10266
10267         /* Enable timestamping of PTP packets. */
10268         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10269         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10270
10271         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10272         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10273         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10274
10275         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10276         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10277
10278         return 0;
10279 }
10280
10281 static int
10282 i40e_timesync_disable(struct rte_eth_dev *dev)
10283 {
10284         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10285         uint32_t tsync_ctl_l;
10286         uint32_t tsync_ctl_h;
10287
10288         /* Disable timestamping of transmitted PTP packets. */
10289         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10290         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10291
10292         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10293         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10294
10295         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10296         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10297
10298         /* Reset the timesync increment value. */
10299         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10300         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10301
10302         return 0;
10303 }
10304
10305 static int
10306 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10307                                 struct timespec *timestamp, uint32_t flags)
10308 {
10309         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10310         struct i40e_adapter *adapter =
10311                 (struct i40e_adapter *)dev->data->dev_private;
10312
10313         uint32_t sync_status;
10314         uint32_t index = flags & 0x03;
10315         uint64_t rx_tstamp_cycles;
10316         uint64_t ns;
10317
10318         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10319         if ((sync_status & (1 << index)) == 0)
10320                 return -EINVAL;
10321
10322         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10323         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10324         *timestamp = rte_ns_to_timespec(ns);
10325
10326         return 0;
10327 }
10328
10329 static int
10330 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10331                                 struct timespec *timestamp)
10332 {
10333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10334         struct i40e_adapter *adapter =
10335                 (struct i40e_adapter *)dev->data->dev_private;
10336
10337         uint32_t sync_status;
10338         uint64_t tx_tstamp_cycles;
10339         uint64_t ns;
10340
10341         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10342         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10343                 return -EINVAL;
10344
10345         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10346         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10347         *timestamp = rte_ns_to_timespec(ns);
10348
10349         return 0;
10350 }
10351
10352 /*
10353  * i40e_parse_dcb_configure - parse dcb configure from user
10354  * @dev: the device being configured
10355  * @dcb_cfg: pointer of the result of parse
10356  * @*tc_map: bit map of enabled traffic classes
10357  *
10358  * Returns 0 on success, negative value on failure
10359  */
10360 static int
10361 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10362                          struct i40e_dcbx_config *dcb_cfg,
10363                          uint8_t *tc_map)
10364 {
10365         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10366         uint8_t i, tc_bw, bw_lf;
10367
10368         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10369
10370         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10371         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10372                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10373                 return -EINVAL;
10374         }
10375
10376         /* assume each tc has the same bw */
10377         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10378         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10379                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10380         /* to ensure the sum of tcbw is equal to 100 */
10381         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10382         for (i = 0; i < bw_lf; i++)
10383                 dcb_cfg->etscfg.tcbwtable[i]++;
10384
10385         /* assume each tc has the same Transmission Selection Algorithm */
10386         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10387                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10388
10389         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10390                 dcb_cfg->etscfg.prioritytable[i] =
10391                                 dcb_rx_conf->dcb_tc[i];
10392
10393         /* FW needs one App to configure HW */
10394         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10395         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10396         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10397         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10398
10399         if (dcb_rx_conf->nb_tcs == 0)
10400                 *tc_map = 1; /* tc0 only */
10401         else
10402                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10403
10404         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10405                 dcb_cfg->pfc.willing = 0;
10406                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10407                 dcb_cfg->pfc.pfcenable = *tc_map;
10408         }
10409         return 0;
10410 }
10411
10412
10413 static enum i40e_status_code
10414 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10415                               struct i40e_aqc_vsi_properties_data *info,
10416                               uint8_t enabled_tcmap)
10417 {
10418         enum i40e_status_code ret;
10419         int i, total_tc = 0;
10420         uint16_t qpnum_per_tc, bsf, qp_idx;
10421         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10422         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10423         uint16_t used_queues;
10424
10425         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10426         if (ret != I40E_SUCCESS)
10427                 return ret;
10428
10429         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10430                 if (enabled_tcmap & (1 << i))
10431                         total_tc++;
10432         }
10433         if (total_tc == 0)
10434                 total_tc = 1;
10435         vsi->enabled_tc = enabled_tcmap;
10436
10437         /* different VSI has different queues assigned */
10438         if (vsi->type == I40E_VSI_MAIN)
10439                 used_queues = dev_data->nb_rx_queues -
10440                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10441         else if (vsi->type == I40E_VSI_VMDQ2)
10442                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10443         else {
10444                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10445                 return I40E_ERR_NO_AVAILABLE_VSI;
10446         }
10447
10448         qpnum_per_tc = used_queues / total_tc;
10449         /* Number of queues per enabled TC */
10450         if (qpnum_per_tc == 0) {
10451                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10452                 return I40E_ERR_INVALID_QP_ID;
10453         }
10454         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10455                                 I40E_MAX_Q_PER_TC);
10456         bsf = rte_bsf32(qpnum_per_tc);
10457
10458         /**
10459          * Configure TC and queue mapping parameters, for enabled TC,
10460          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10461          * default queue will serve it.
10462          */
10463         qp_idx = 0;
10464         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10465                 if (vsi->enabled_tc & (1 << i)) {
10466                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10467                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10468                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10469                         qp_idx += qpnum_per_tc;
10470                 } else
10471                         info->tc_mapping[i] = 0;
10472         }
10473
10474         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10475         if (vsi->type == I40E_VSI_SRIOV) {
10476                 info->mapping_flags |=
10477                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10478                 for (i = 0; i < vsi->nb_qps; i++)
10479                         info->queue_mapping[i] =
10480                                 rte_cpu_to_le_16(vsi->base_queue + i);
10481         } else {
10482                 info->mapping_flags |=
10483                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10484                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10485         }
10486         info->valid_sections |=
10487                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10488
10489         return I40E_SUCCESS;
10490 }
10491
10492 /*
10493  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10494  * @veb: VEB to be configured
10495  * @tc_map: enabled TC bitmap
10496  *
10497  * Returns 0 on success, negative value on failure
10498  */
10499 static enum i40e_status_code
10500 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10501 {
10502         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10503         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10504         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10505         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10506         enum i40e_status_code ret = I40E_SUCCESS;
10507         int i;
10508         uint32_t bw_max;
10509
10510         /* Check if enabled_tc is same as existing or new TCs */
10511         if (veb->enabled_tc == tc_map)
10512                 return ret;
10513
10514         /* configure tc bandwidth */
10515         memset(&veb_bw, 0, sizeof(veb_bw));
10516         veb_bw.tc_valid_bits = tc_map;
10517         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10518         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10519                 if (tc_map & BIT_ULL(i))
10520                         veb_bw.tc_bw_share_credits[i] = 1;
10521         }
10522         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10523                                                    &veb_bw, NULL);
10524         if (ret) {
10525                 PMD_INIT_LOG(ERR,
10526                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10527                         hw->aq.asq_last_status);
10528                 return ret;
10529         }
10530
10531         memset(&ets_query, 0, sizeof(ets_query));
10532         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10533                                                    &ets_query, NULL);
10534         if (ret != I40E_SUCCESS) {
10535                 PMD_DRV_LOG(ERR,
10536                         "Failed to get switch_comp ETS configuration %u",
10537                         hw->aq.asq_last_status);
10538                 return ret;
10539         }
10540         memset(&bw_query, 0, sizeof(bw_query));
10541         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10542                                                   &bw_query, NULL);
10543         if (ret != I40E_SUCCESS) {
10544                 PMD_DRV_LOG(ERR,
10545                         "Failed to get switch_comp bandwidth configuration %u",
10546                         hw->aq.asq_last_status);
10547                 return ret;
10548         }
10549
10550         /* store and print out BW info */
10551         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10552         veb->bw_info.bw_max = ets_query.tc_bw_max;
10553         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10554         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10555         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10556                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10557                      I40E_16_BIT_WIDTH);
10558         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10559                 veb->bw_info.bw_ets_share_credits[i] =
10560                                 bw_query.tc_bw_share_credits[i];
10561                 veb->bw_info.bw_ets_credits[i] =
10562                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10563                 /* 4 bits per TC, 4th bit is reserved */
10564                 veb->bw_info.bw_ets_max[i] =
10565                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10566                                   RTE_LEN2MASK(3, uint8_t));
10567                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10568                             veb->bw_info.bw_ets_share_credits[i]);
10569                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10570                             veb->bw_info.bw_ets_credits[i]);
10571                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10572                             veb->bw_info.bw_ets_max[i]);
10573         }
10574
10575         veb->enabled_tc = tc_map;
10576
10577         return ret;
10578 }
10579
10580
10581 /*
10582  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10583  * @vsi: VSI to be configured
10584  * @tc_map: enabled TC bitmap
10585  *
10586  * Returns 0 on success, negative value on failure
10587  */
10588 static enum i40e_status_code
10589 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10590 {
10591         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10592         struct i40e_vsi_context ctxt;
10593         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10594         enum i40e_status_code ret = I40E_SUCCESS;
10595         int i;
10596
10597         /* Check if enabled_tc is same as existing or new TCs */
10598         if (vsi->enabled_tc == tc_map)
10599                 return ret;
10600
10601         /* configure tc bandwidth */
10602         memset(&bw_data, 0, sizeof(bw_data));
10603         bw_data.tc_valid_bits = tc_map;
10604         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10605         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10606                 if (tc_map & BIT_ULL(i))
10607                         bw_data.tc_bw_credits[i] = 1;
10608         }
10609         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10610         if (ret) {
10611                 PMD_INIT_LOG(ERR,
10612                         "AQ command Config VSI BW allocation per TC failed = %d",
10613                         hw->aq.asq_last_status);
10614                 goto out;
10615         }
10616         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10617                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10618
10619         /* Update Queue Pairs Mapping for currently enabled UPs */
10620         ctxt.seid = vsi->seid;
10621         ctxt.pf_num = hw->pf_id;
10622         ctxt.vf_num = 0;
10623         ctxt.uplink_seid = vsi->uplink_seid;
10624         ctxt.info = vsi->info;
10625         i40e_get_cap(hw);
10626         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10627         if (ret)
10628                 goto out;
10629
10630         /* Update the VSI after updating the VSI queue-mapping information */
10631         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10632         if (ret) {
10633                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10634                         hw->aq.asq_last_status);
10635                 goto out;
10636         }
10637         /* update the local VSI info with updated queue map */
10638         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10639                                         sizeof(vsi->info.tc_mapping));
10640         rte_memcpy(&vsi->info.queue_mapping,
10641                         &ctxt.info.queue_mapping,
10642                 sizeof(vsi->info.queue_mapping));
10643         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10644         vsi->info.valid_sections = 0;
10645
10646         /* query and update current VSI BW information */
10647         ret = i40e_vsi_get_bw_config(vsi);
10648         if (ret) {
10649                 PMD_INIT_LOG(ERR,
10650                          "Failed updating vsi bw info, err %s aq_err %s",
10651                          i40e_stat_str(hw, ret),
10652                          i40e_aq_str(hw, hw->aq.asq_last_status));
10653                 goto out;
10654         }
10655
10656         vsi->enabled_tc = tc_map;
10657
10658 out:
10659         return ret;
10660 }
10661
10662 /*
10663  * i40e_dcb_hw_configure - program the dcb setting to hw
10664  * @pf: pf the configuration is taken on
10665  * @new_cfg: new configuration
10666  * @tc_map: enabled TC bitmap
10667  *
10668  * Returns 0 on success, negative value on failure
10669  */
10670 static enum i40e_status_code
10671 i40e_dcb_hw_configure(struct i40e_pf *pf,
10672                       struct i40e_dcbx_config *new_cfg,
10673                       uint8_t tc_map)
10674 {
10675         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10676         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10677         struct i40e_vsi *main_vsi = pf->main_vsi;
10678         struct i40e_vsi_list *vsi_list;
10679         enum i40e_status_code ret;
10680         int i;
10681         uint32_t val;
10682
10683         /* Use the FW API if FW > v4.4*/
10684         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10685               (hw->aq.fw_maj_ver >= 5))) {
10686                 PMD_INIT_LOG(ERR,
10687                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10688                 return I40E_ERR_FIRMWARE_API_VERSION;
10689         }
10690
10691         /* Check if need reconfiguration */
10692         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10693                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10694                 return I40E_SUCCESS;
10695         }
10696
10697         /* Copy the new config to the current config */
10698         *old_cfg = *new_cfg;
10699         old_cfg->etsrec = old_cfg->etscfg;
10700         ret = i40e_set_dcb_config(hw);
10701         if (ret) {
10702                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10703                          i40e_stat_str(hw, ret),
10704                          i40e_aq_str(hw, hw->aq.asq_last_status));
10705                 return ret;
10706         }
10707         /* set receive Arbiter to RR mode and ETS scheme by default */
10708         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10709                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10710                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10711                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10712                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10713                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10714                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10715                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10716                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10717                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10718                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10719                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10720                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10721         }
10722         /* get local mib to check whether it is configured correctly */
10723         /* IEEE mode */
10724         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10725         /* Get Local DCB Config */
10726         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10727                                      &hw->local_dcbx_config);
10728
10729         /* if Veb is created, need to update TC of it at first */
10730         if (main_vsi->veb) {
10731                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10732                 if (ret)
10733                         PMD_INIT_LOG(WARNING,
10734                                  "Failed configuring TC for VEB seid=%d",
10735                                  main_vsi->veb->seid);
10736         }
10737         /* Update each VSI */
10738         i40e_vsi_config_tc(main_vsi, tc_map);
10739         if (main_vsi->veb) {
10740                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10741                         /* Beside main VSI and VMDQ VSIs, only enable default
10742                          * TC for other VSIs
10743                          */
10744                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10745                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10746                                                          tc_map);
10747                         else
10748                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10749                                                          I40E_DEFAULT_TCMAP);
10750                         if (ret)
10751                                 PMD_INIT_LOG(WARNING,
10752                                         "Failed configuring TC for VSI seid=%d",
10753                                         vsi_list->vsi->seid);
10754                         /* continue */
10755                 }
10756         }
10757         return I40E_SUCCESS;
10758 }
10759
10760 /*
10761  * i40e_dcb_init_configure - initial dcb config
10762  * @dev: device being configured
10763  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10764  *
10765  * Returns 0 on success, negative value on failure
10766  */
10767 int
10768 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10769 {
10770         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10771         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10772         int i, ret = 0;
10773
10774         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10775                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10776                 return -ENOTSUP;
10777         }
10778
10779         /* DCB initialization:
10780          * Update DCB configuration from the Firmware and configure
10781          * LLDP MIB change event.
10782          */
10783         if (sw_dcb == TRUE) {
10784                 ret = i40e_init_dcb(hw);
10785                 /* If lldp agent is stopped, the return value from
10786                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10787                  * adminq status. Otherwise, it should return success.
10788                  */
10789                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10790                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10791                         memset(&hw->local_dcbx_config, 0,
10792                                 sizeof(struct i40e_dcbx_config));
10793                         /* set dcb default configuration */
10794                         hw->local_dcbx_config.etscfg.willing = 0;
10795                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10796                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10797                         hw->local_dcbx_config.etscfg.tsatable[0] =
10798                                                 I40E_IEEE_TSA_ETS;
10799                         /* all UPs mapping to TC0 */
10800                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10801                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10802                         hw->local_dcbx_config.etsrec =
10803                                 hw->local_dcbx_config.etscfg;
10804                         hw->local_dcbx_config.pfc.willing = 0;
10805                         hw->local_dcbx_config.pfc.pfccap =
10806                                                 I40E_MAX_TRAFFIC_CLASS;
10807                         /* FW needs one App to configure HW */
10808                         hw->local_dcbx_config.numapps = 1;
10809                         hw->local_dcbx_config.app[0].selector =
10810                                                 I40E_APP_SEL_ETHTYPE;
10811                         hw->local_dcbx_config.app[0].priority = 3;
10812                         hw->local_dcbx_config.app[0].protocolid =
10813                                                 I40E_APP_PROTOID_FCOE;
10814                         ret = i40e_set_dcb_config(hw);
10815                         if (ret) {
10816                                 PMD_INIT_LOG(ERR,
10817                                         "default dcb config fails. err = %d, aq_err = %d.",
10818                                         ret, hw->aq.asq_last_status);
10819                                 return -ENOSYS;
10820                         }
10821                 } else {
10822                         PMD_INIT_LOG(ERR,
10823                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10824                                 ret, hw->aq.asq_last_status);
10825                         return -ENOTSUP;
10826                 }
10827         } else {
10828                 ret = i40e_aq_start_lldp(hw, NULL);
10829                 if (ret != I40E_SUCCESS)
10830                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10831
10832                 ret = i40e_init_dcb(hw);
10833                 if (!ret) {
10834                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10835                                 PMD_INIT_LOG(ERR,
10836                                         "HW doesn't support DCBX offload.");
10837                                 return -ENOTSUP;
10838                         }
10839                 } else {
10840                         PMD_INIT_LOG(ERR,
10841                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10842                                 ret, hw->aq.asq_last_status);
10843                         return -ENOTSUP;
10844                 }
10845         }
10846         return 0;
10847 }
10848
10849 /*
10850  * i40e_dcb_setup - setup dcb related config
10851  * @dev: device being configured
10852  *
10853  * Returns 0 on success, negative value on failure
10854  */
10855 static int
10856 i40e_dcb_setup(struct rte_eth_dev *dev)
10857 {
10858         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10859         struct i40e_dcbx_config dcb_cfg;
10860         uint8_t tc_map = 0;
10861         int ret = 0;
10862
10863         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10864                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10865                 return -ENOTSUP;
10866         }
10867
10868         if (pf->vf_num != 0)
10869                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10870
10871         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10872         if (ret) {
10873                 PMD_INIT_LOG(ERR, "invalid dcb config");
10874                 return -EINVAL;
10875         }
10876         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10877         if (ret) {
10878                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10879                 return -ENOSYS;
10880         }
10881
10882         return 0;
10883 }
10884
10885 static int
10886 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10887                       struct rte_eth_dcb_info *dcb_info)
10888 {
10889         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10890         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10891         struct i40e_vsi *vsi = pf->main_vsi;
10892         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10893         uint16_t bsf, tc_mapping;
10894         int i, j = 0;
10895
10896         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10897                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10898         else
10899                 dcb_info->nb_tcs = 1;
10900         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10901                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10902         for (i = 0; i < dcb_info->nb_tcs; i++)
10903                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10904
10905         /* get queue mapping if vmdq is disabled */
10906         if (!pf->nb_cfg_vmdq_vsi) {
10907                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10908                         if (!(vsi->enabled_tc & (1 << i)))
10909                                 continue;
10910                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10911                         dcb_info->tc_queue.tc_rxq[j][i].base =
10912                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10913                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10914                         dcb_info->tc_queue.tc_txq[j][i].base =
10915                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10916                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10917                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10918                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10919                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10920                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10921                 }
10922                 return 0;
10923         }
10924
10925         /* get queue mapping if vmdq is enabled */
10926         do {
10927                 vsi = pf->vmdq[j].vsi;
10928                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10929                         if (!(vsi->enabled_tc & (1 << i)))
10930                                 continue;
10931                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10932                         dcb_info->tc_queue.tc_rxq[j][i].base =
10933                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10934                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10935                         dcb_info->tc_queue.tc_txq[j][i].base =
10936                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10937                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10938                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10939                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10940                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10941                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10942                 }
10943                 j++;
10944         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10945         return 0;
10946 }
10947
10948 static int
10949 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10950 {
10951         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10952         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10954         uint16_t interval =
10955                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10956         uint16_t msix_intr;
10957
10958         msix_intr = intr_handle->intr_vec[queue_id];
10959         if (msix_intr == I40E_MISC_VEC_ID)
10960                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10961                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10962                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10963                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10964                                (interval <<
10965                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10966         else
10967                 I40E_WRITE_REG(hw,
10968                                I40E_PFINT_DYN_CTLN(msix_intr -
10969                                                    I40E_RX_VEC_START),
10970                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10971                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10972                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10973                                (interval <<
10974                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10975
10976         I40E_WRITE_FLUSH(hw);
10977         rte_intr_enable(&pci_dev->intr_handle);
10978
10979         return 0;
10980 }
10981
10982 static int
10983 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10984 {
10985         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10986         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10987         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10988         uint16_t msix_intr;
10989
10990         msix_intr = intr_handle->intr_vec[queue_id];
10991         if (msix_intr == I40E_MISC_VEC_ID)
10992                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10993         else
10994                 I40E_WRITE_REG(hw,
10995                                I40E_PFINT_DYN_CTLN(msix_intr -
10996                                                    I40E_RX_VEC_START),
10997                                0);
10998         I40E_WRITE_FLUSH(hw);
10999
11000         return 0;
11001 }
11002
11003 static int i40e_get_regs(struct rte_eth_dev *dev,
11004                          struct rte_dev_reg_info *regs)
11005 {
11006         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11007         uint32_t *ptr_data = regs->data;
11008         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11009         const struct i40e_reg_info *reg_info;
11010
11011         if (ptr_data == NULL) {
11012                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11013                 regs->width = sizeof(uint32_t);
11014                 return 0;
11015         }
11016
11017         /* The first few registers have to be read using AQ operations */
11018         reg_idx = 0;
11019         while (i40e_regs_adminq[reg_idx].name) {
11020                 reg_info = &i40e_regs_adminq[reg_idx++];
11021                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11022                         for (arr_idx2 = 0;
11023                                         arr_idx2 <= reg_info->count2;
11024                                         arr_idx2++) {
11025                                 reg_offset = arr_idx * reg_info->stride1 +
11026                                         arr_idx2 * reg_info->stride2;
11027                                 reg_offset += reg_info->base_addr;
11028                                 ptr_data[reg_offset >> 2] =
11029                                         i40e_read_rx_ctl(hw, reg_offset);
11030                         }
11031         }
11032
11033         /* The remaining registers can be read using primitives */
11034         reg_idx = 0;
11035         while (i40e_regs_others[reg_idx].name) {
11036                 reg_info = &i40e_regs_others[reg_idx++];
11037                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11038                         for (arr_idx2 = 0;
11039                                         arr_idx2 <= reg_info->count2;
11040                                         arr_idx2++) {
11041                                 reg_offset = arr_idx * reg_info->stride1 +
11042                                         arr_idx2 * reg_info->stride2;
11043                                 reg_offset += reg_info->base_addr;
11044                                 ptr_data[reg_offset >> 2] =
11045                                         I40E_READ_REG(hw, reg_offset);
11046                         }
11047         }
11048
11049         return 0;
11050 }
11051
11052 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11053 {
11054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11055
11056         /* Convert word count to byte count */
11057         return hw->nvm.sr_size << 1;
11058 }
11059
11060 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11061                            struct rte_dev_eeprom_info *eeprom)
11062 {
11063         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11064         uint16_t *data = eeprom->data;
11065         uint16_t offset, length, cnt_words;
11066         int ret_code;
11067
11068         offset = eeprom->offset >> 1;
11069         length = eeprom->length >> 1;
11070         cnt_words = length;
11071
11072         if (offset > hw->nvm.sr_size ||
11073                 offset + length > hw->nvm.sr_size) {
11074                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11075                 return -EINVAL;
11076         }
11077
11078         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11079
11080         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11081         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11082                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11083                 return -EIO;
11084         }
11085
11086         return 0;
11087 }
11088
11089 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11090                                       struct ether_addr *mac_addr)
11091 {
11092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11093         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11094         struct i40e_vsi *vsi = pf->main_vsi;
11095         struct i40e_mac_filter_info mac_filter;
11096         struct i40e_mac_filter *f;
11097         int ret;
11098
11099         if (!is_valid_assigned_ether_addr(mac_addr)) {
11100                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11101                 return;
11102         }
11103
11104         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11105                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11106                         break;
11107         }
11108
11109         if (f == NULL) {
11110                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11111                 return;
11112         }
11113
11114         mac_filter = f->mac_info;
11115         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11116         if (ret != I40E_SUCCESS) {
11117                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11118                 return;
11119         }
11120         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11121         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11122         if (ret != I40E_SUCCESS) {
11123                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11124                 return;
11125         }
11126         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11127
11128         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11129                                   mac_addr->addr_bytes, NULL);
11130 }
11131
11132 static int
11133 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11134 {
11135         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11136         struct rte_eth_dev_data *dev_data = pf->dev_data;
11137         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11138         int ret = 0;
11139
11140         /* check if mtu is within the allowed range */
11141         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11142                 return -EINVAL;
11143
11144         /* mtu setting is forbidden if port is start */
11145         if (dev_data->dev_started) {
11146                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11147                             dev_data->port_id);
11148                 return -EBUSY;
11149         }
11150
11151         if (frame_size > ETHER_MAX_LEN)
11152                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11153         else
11154                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11155
11156         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11157
11158         return ret;
11159 }
11160
11161 /* Restore ethertype filter */
11162 static void
11163 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11164 {
11165         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11166         struct i40e_ethertype_filter_list
11167                 *ethertype_list = &pf->ethertype.ethertype_list;
11168         struct i40e_ethertype_filter *f;
11169         struct i40e_control_filter_stats stats;
11170         uint16_t flags;
11171
11172         TAILQ_FOREACH(f, ethertype_list, rules) {
11173                 flags = 0;
11174                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11175                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11176                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11177                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11178                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11179
11180                 memset(&stats, 0, sizeof(stats));
11181                 i40e_aq_add_rem_control_packet_filter(hw,
11182                                             f->input.mac_addr.addr_bytes,
11183                                             f->input.ether_type,
11184                                             flags, pf->main_vsi->seid,
11185                                             f->queue, 1, &stats, NULL);
11186         }
11187         PMD_DRV_LOG(INFO, "Ethertype filter:"
11188                     " mac_etype_used = %u, etype_used = %u,"
11189                     " mac_etype_free = %u, etype_free = %u",
11190                     stats.mac_etype_used, stats.etype_used,
11191                     stats.mac_etype_free, stats.etype_free);
11192 }
11193
11194 /* Restore tunnel filter */
11195 static void
11196 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11197 {
11198         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11199         struct i40e_vsi *vsi;
11200         struct i40e_pf_vf *vf;
11201         struct i40e_tunnel_filter_list
11202                 *tunnel_list = &pf->tunnel.tunnel_list;
11203         struct i40e_tunnel_filter *f;
11204         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11205         bool big_buffer = 0;
11206
11207         TAILQ_FOREACH(f, tunnel_list, rules) {
11208                 if (!f->is_to_vf)
11209                         vsi = pf->main_vsi;
11210                 else {
11211                         vf = &pf->vfs[f->vf_id];
11212                         vsi = vf->vsi;
11213                 }
11214                 memset(&cld_filter, 0, sizeof(cld_filter));
11215                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11216                         (struct ether_addr *)&cld_filter.element.outer_mac);
11217                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11218                         (struct ether_addr *)&cld_filter.element.inner_mac);
11219                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11220                 cld_filter.element.flags = f->input.flags;
11221                 cld_filter.element.tenant_id = f->input.tenant_id;
11222                 cld_filter.element.queue_number = f->queue;
11223                 rte_memcpy(cld_filter.general_fields,
11224                            f->input.general_fields,
11225                            sizeof(f->input.general_fields));
11226
11227                 if (((f->input.flags &
11228                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11229                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11230                     ((f->input.flags &
11231                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11232                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11233                     ((f->input.flags &
11234                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11235                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11236                         big_buffer = 1;
11237
11238                 if (big_buffer)
11239                         i40e_aq_add_cloud_filters_big_buffer(hw,
11240                                              vsi->seid, &cld_filter, 1);
11241                 else
11242                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11243                                                   &cld_filter.element, 1);
11244         }
11245 }
11246
11247 /* Restore rss filter */
11248 static inline void
11249 i40e_rss_filter_restore(struct i40e_pf *pf)
11250 {
11251         struct i40e_rte_flow_rss_conf *conf =
11252                                         &pf->rss_info;
11253         if (conf->num)
11254                 i40e_config_rss_filter(pf, conf, TRUE);
11255 }
11256
11257 static void
11258 i40e_filter_restore(struct i40e_pf *pf)
11259 {
11260         i40e_ethertype_filter_restore(pf);
11261         i40e_tunnel_filter_restore(pf);
11262         i40e_fdir_filter_restore(pf);
11263         i40e_rss_filter_restore(pf);
11264 }
11265
11266 static bool
11267 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11268 {
11269         if (strcmp(dev->device->driver->name, drv->driver.name))
11270                 return false;
11271
11272         return true;
11273 }
11274
11275 bool
11276 is_i40e_supported(struct rte_eth_dev *dev)
11277 {
11278         return is_device_supported(dev, &rte_i40e_pmd);
11279 }
11280
11281 struct i40e_customized_pctype*
11282 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11283 {
11284         int i;
11285
11286         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11287                 if (pf->customized_pctype[i].index == index)
11288                         return &pf->customized_pctype[i];
11289         }
11290         return NULL;
11291 }
11292
11293 static int
11294 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11295                               uint32_t pkg_size, uint32_t proto_num,
11296                               struct rte_pmd_i40e_proto_info *proto)
11297 {
11298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11299         uint32_t pctype_num;
11300         struct rte_pmd_i40e_ptype_info *pctype;
11301         uint32_t buff_size;
11302         struct i40e_customized_pctype *new_pctype = NULL;
11303         uint8_t proto_id;
11304         uint8_t pctype_value;
11305         char name[64];
11306         uint32_t i, j, n;
11307         int ret;
11308
11309         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11310                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11311                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11312         if (ret) {
11313                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11314                 return -1;
11315         }
11316         if (!pctype_num) {
11317                 PMD_DRV_LOG(INFO, "No new pctype added");
11318                 return -1;
11319         }
11320
11321         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11322         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11323         if (!pctype) {
11324                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11325                 return -1;
11326         }
11327         /* get information about new pctype list */
11328         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11329                                         (uint8_t *)pctype, buff_size,
11330                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11331         if (ret) {
11332                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11333                 rte_free(pctype);
11334                 return -1;
11335         }
11336
11337         /* Update customized pctype. */
11338         for (i = 0; i < pctype_num; i++) {
11339                 pctype_value = pctype[i].ptype_id;
11340                 memset(name, 0, sizeof(name));
11341                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11342                         proto_id = pctype[i].protocols[j];
11343                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11344                                 continue;
11345                         for (n = 0; n < proto_num; n++) {
11346                                 if (proto[n].proto_id != proto_id)
11347                                         continue;
11348                                 strcat(name, proto[n].name);
11349                                 strcat(name, "_");
11350                                 break;
11351                         }
11352                 }
11353                 name[strlen(name) - 1] = '\0';
11354                 if (!strcmp(name, "GTPC"))
11355                         new_pctype =
11356                                 i40e_find_customized_pctype(pf,
11357                                                       I40E_CUSTOMIZED_GTPC);
11358                 else if (!strcmp(name, "GTPU_IPV4"))
11359                         new_pctype =
11360                                 i40e_find_customized_pctype(pf,
11361                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11362                 else if (!strcmp(name, "GTPU_IPV6"))
11363                         new_pctype =
11364                                 i40e_find_customized_pctype(pf,
11365                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11366                 else if (!strcmp(name, "GTPU"))
11367                         new_pctype =
11368                                 i40e_find_customized_pctype(pf,
11369                                                       I40E_CUSTOMIZED_GTPU);
11370                 if (new_pctype) {
11371                         new_pctype->pctype = pctype_value;
11372                         new_pctype->valid = true;
11373                 }
11374         }
11375
11376         rte_free(pctype);
11377         return 0;
11378 }
11379
11380 static int
11381 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11382                                uint32_t pkg_size, uint32_t proto_num,
11383                                struct rte_pmd_i40e_proto_info *proto)
11384 {
11385         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11386         uint16_t port_id = dev->data->port_id;
11387         uint32_t ptype_num;
11388         struct rte_pmd_i40e_ptype_info *ptype;
11389         uint32_t buff_size;
11390         uint8_t proto_id;
11391         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11392         uint32_t i, j, n;
11393         bool in_tunnel;
11394         int ret;
11395
11396         /* get information about new ptype num */
11397         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11398                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11399                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11400         if (ret) {
11401                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11402                 return ret;
11403         }
11404         if (!ptype_num) {
11405                 PMD_DRV_LOG(INFO, "No new ptype added");
11406                 return -1;
11407         }
11408
11409         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11410         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11411         if (!ptype) {
11412                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11413                 return -1;
11414         }
11415
11416         /* get information about new ptype list */
11417         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11418                                         (uint8_t *)ptype, buff_size,
11419                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11420         if (ret) {
11421                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11422                 rte_free(ptype);
11423                 return ret;
11424         }
11425
11426         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11427         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11428         if (!ptype_mapping) {
11429                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11430                 rte_free(ptype);
11431                 return -1;
11432         }
11433
11434         /* Update ptype mapping table. */
11435         for (i = 0; i < ptype_num; i++) {
11436                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11437                 ptype_mapping[i].sw_ptype = 0;
11438                 in_tunnel = false;
11439                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11440                         proto_id = ptype[i].protocols[j];
11441                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11442                                 continue;
11443                         for (n = 0; n < proto_num; n++) {
11444                                 if (proto[n].proto_id != proto_id)
11445                                         continue;
11446                                 memset(name, 0, sizeof(name));
11447                                 strcpy(name, proto[n].name);
11448                                 if (!strncasecmp(name, "PPPOE", 5))
11449                                         ptype_mapping[i].sw_ptype |=
11450                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11451                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11452                                          !in_tunnel) {
11453                                         ptype_mapping[i].sw_ptype |=
11454                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11455                                         ptype_mapping[i].sw_ptype |=
11456                                                 RTE_PTYPE_L4_FRAG;
11457                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11458                                            in_tunnel) {
11459                                         ptype_mapping[i].sw_ptype |=
11460                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11461                                         ptype_mapping[i].sw_ptype |=
11462                                                 RTE_PTYPE_INNER_L4_FRAG;
11463                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11464                                         ptype_mapping[i].sw_ptype |=
11465                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11466                                         in_tunnel = true;
11467                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11468                                            !in_tunnel)
11469                                         ptype_mapping[i].sw_ptype |=
11470                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11471                                 else if (!strncasecmp(name, "IPV4", 4) &&
11472                                          in_tunnel)
11473                                         ptype_mapping[i].sw_ptype |=
11474                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11475                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11476                                          !in_tunnel) {
11477                                         ptype_mapping[i].sw_ptype |=
11478                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11479                                         ptype_mapping[i].sw_ptype |=
11480                                                 RTE_PTYPE_L4_FRAG;
11481                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11482                                            in_tunnel) {
11483                                         ptype_mapping[i].sw_ptype |=
11484                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11485                                         ptype_mapping[i].sw_ptype |=
11486                                                 RTE_PTYPE_INNER_L4_FRAG;
11487                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11488                                         ptype_mapping[i].sw_ptype |=
11489                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11490                                         in_tunnel = true;
11491                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11492                                            !in_tunnel)
11493                                         ptype_mapping[i].sw_ptype |=
11494                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11495                                 else if (!strncasecmp(name, "IPV6", 4) &&
11496                                          in_tunnel)
11497                                         ptype_mapping[i].sw_ptype |=
11498                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11499                                 else if (!strncasecmp(name, "UDP", 3) &&
11500                                          !in_tunnel)
11501                                         ptype_mapping[i].sw_ptype |=
11502                                                 RTE_PTYPE_L4_UDP;
11503                                 else if (!strncasecmp(name, "UDP", 3) &&
11504                                          in_tunnel)
11505                                         ptype_mapping[i].sw_ptype |=
11506                                                 RTE_PTYPE_INNER_L4_UDP;
11507                                 else if (!strncasecmp(name, "TCP", 3) &&
11508                                          !in_tunnel)
11509                                         ptype_mapping[i].sw_ptype |=
11510                                                 RTE_PTYPE_L4_TCP;
11511                                 else if (!strncasecmp(name, "TCP", 3) &&
11512                                          in_tunnel)
11513                                         ptype_mapping[i].sw_ptype |=
11514                                                 RTE_PTYPE_INNER_L4_TCP;
11515                                 else if (!strncasecmp(name, "SCTP", 4) &&
11516                                          !in_tunnel)
11517                                         ptype_mapping[i].sw_ptype |=
11518                                                 RTE_PTYPE_L4_SCTP;
11519                                 else if (!strncasecmp(name, "SCTP", 4) &&
11520                                          in_tunnel)
11521                                         ptype_mapping[i].sw_ptype |=
11522                                                 RTE_PTYPE_INNER_L4_SCTP;
11523                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11524                                           !strncasecmp(name, "ICMPV6", 6)) &&
11525                                          !in_tunnel)
11526                                         ptype_mapping[i].sw_ptype |=
11527                                                 RTE_PTYPE_L4_ICMP;
11528                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11529                                           !strncasecmp(name, "ICMPV6", 6)) &&
11530                                          in_tunnel)
11531                                         ptype_mapping[i].sw_ptype |=
11532                                                 RTE_PTYPE_INNER_L4_ICMP;
11533                                 else if (!strncasecmp(name, "GTPC", 4)) {
11534                                         ptype_mapping[i].sw_ptype |=
11535                                                 RTE_PTYPE_TUNNEL_GTPC;
11536                                         in_tunnel = true;
11537                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11538                                         ptype_mapping[i].sw_ptype |=
11539                                                 RTE_PTYPE_TUNNEL_GTPU;
11540                                         in_tunnel = true;
11541                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11542                                         ptype_mapping[i].sw_ptype |=
11543                                                 RTE_PTYPE_TUNNEL_GRENAT;
11544                                         in_tunnel = true;
11545                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11546                                         ptype_mapping[i].sw_ptype |=
11547                                                 RTE_PTYPE_TUNNEL_L2TP;
11548                                         in_tunnel = true;
11549                                 }
11550
11551                                 break;
11552                         }
11553                 }
11554         }
11555
11556         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11557                                                 ptype_num, 0);
11558         if (ret)
11559                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11560
11561         rte_free(ptype_mapping);
11562         rte_free(ptype);
11563         return ret;
11564 }
11565
11566 void
11567 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11568                               uint32_t pkg_size)
11569 {
11570         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11571         uint32_t proto_num;
11572         struct rte_pmd_i40e_proto_info *proto;
11573         uint32_t buff_size;
11574         uint32_t i;
11575         int ret;
11576
11577         /* get information about protocol number */
11578         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11579                                        (uint8_t *)&proto_num, sizeof(proto_num),
11580                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11581         if (ret) {
11582                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11583                 return;
11584         }
11585         if (!proto_num) {
11586                 PMD_DRV_LOG(INFO, "No new protocol added");
11587                 return;
11588         }
11589
11590         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11591         proto = rte_zmalloc("new_proto", buff_size, 0);
11592         if (!proto) {
11593                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11594                 return;
11595         }
11596
11597         /* get information about protocol list */
11598         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11599                                         (uint8_t *)proto, buff_size,
11600                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11601         if (ret) {
11602                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11603                 rte_free(proto);
11604                 return;
11605         }
11606
11607         /* Check if GTP is supported. */
11608         for (i = 0; i < proto_num; i++) {
11609                 if (!strncmp(proto[i].name, "GTP", 3)) {
11610                         pf->gtp_support = true;
11611                         break;
11612                 }
11613         }
11614
11615         /* Update customized pctype info */
11616         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11617                                             proto_num, proto);
11618         if (ret)
11619                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11620
11621         /* Update customized ptype info */
11622         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11623                                            proto_num, proto);
11624         if (ret)
11625                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11626
11627         rte_free(proto);
11628 }
11629
11630 /* Create a QinQ cloud filter
11631  *
11632  * The Fortville NIC has limited resources for tunnel filters,
11633  * so we can only reuse existing filters.
11634  *
11635  * In step 1 we define which Field Vector fields can be used for
11636  * filter types.
11637  * As we do not have the inner tag defined as a field,
11638  * we have to define it first, by reusing one of L1 entries.
11639  *
11640  * In step 2 we are replacing one of existing filter types with
11641  * a new one for QinQ.
11642  * As we reusing L1 and replacing L2, some of the default filter
11643  * types will disappear,which depends on L1 and L2 entries we reuse.
11644  *
11645  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11646  *
11647  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11648  *              later when we define the cloud filter.
11649  *      a.      Valid_flags.replace_cloud = 0
11650  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11651  *      c.      New_filter = 0x10
11652  *      d.      TR bit = 0xff (optional, not used here)
11653  *      e.      Buffer – 2 entries:
11654  *              i.      Byte 0 = 8 (outer vlan FV index).
11655  *                      Byte 1 = 0 (rsv)
11656  *                      Byte 2-3 = 0x0fff
11657  *              ii.     Byte 0 = 37 (inner vlan FV index).
11658  *                      Byte 1 =0 (rsv)
11659  *                      Byte 2-3 = 0x0fff
11660  *
11661  * Step 2:
11662  * 2.   Create cloud filter using two L1 filters entries: stag and
11663  *              new filter(outer vlan+ inner vlan)
11664  *      a.      Valid_flags.replace_cloud = 1
11665  *      b.      Old_filter = 1 (instead of outer IP)
11666  *      c.      New_filter = 0x10
11667  *      d.      Buffer – 2 entries:
11668  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11669  *                      Byte 1-3 = 0 (rsv)
11670  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11671  *                      Byte 9-11 = 0 (rsv)
11672  */
11673 static int
11674 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11675 {
11676         int ret = -ENOTSUP;
11677         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11678         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11679         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11680
11681         /* Init */
11682         memset(&filter_replace, 0,
11683                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11684         memset(&filter_replace_buf, 0,
11685                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11686
11687         /* create L1 filter */
11688         filter_replace.old_filter_type =
11689                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11690         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11691         filter_replace.tr_bit = 0;
11692
11693         /* Prepare the buffer, 2 entries */
11694         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11695         filter_replace_buf.data[0] |=
11696                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11697         /* Field Vector 12b mask */
11698         filter_replace_buf.data[2] = 0xff;
11699         filter_replace_buf.data[3] = 0x0f;
11700         filter_replace_buf.data[4] =
11701                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11702         filter_replace_buf.data[4] |=
11703                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11704         /* Field Vector 12b mask */
11705         filter_replace_buf.data[6] = 0xff;
11706         filter_replace_buf.data[7] = 0x0f;
11707         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11708                         &filter_replace_buf);
11709         if (ret != I40E_SUCCESS)
11710                 return ret;
11711         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11712                     "cloud l1 type is changed from 0x%x to 0x%x",
11713                     filter_replace.old_filter_type,
11714                     filter_replace.new_filter_type);
11715
11716         /* Apply the second L2 cloud filter */
11717         memset(&filter_replace, 0,
11718                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11719         memset(&filter_replace_buf, 0,
11720                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11721
11722         /* create L2 filter, input for L2 filter will be L1 filter  */
11723         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11724         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11725         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11726
11727         /* Prepare the buffer, 2 entries */
11728         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11729         filter_replace_buf.data[0] |=
11730                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11731         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11732         filter_replace_buf.data[4] |=
11733                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11734         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11735                         &filter_replace_buf);
11736         if (!ret) {
11737                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
11738                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11739                             "cloud filter type is changed from 0x%x to 0x%x",
11740                             filter_replace.old_filter_type,
11741                             filter_replace.new_filter_type);
11742         }
11743         return ret;
11744 }
11745
11746 int
11747 i40e_config_rss_filter(struct i40e_pf *pf,
11748                 struct i40e_rte_flow_rss_conf *conf, bool add)
11749 {
11750         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11751         uint32_t i, lut = 0;
11752         uint16_t j, num;
11753         struct rte_eth_rss_conf rss_conf = conf->rss_conf;
11754         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
11755
11756         if (!add) {
11757                 if (memcmp(conf, rss_info,
11758                         sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
11759                         i40e_pf_disable_rss(pf);
11760                         memset(rss_info, 0,
11761                                 sizeof(struct i40e_rte_flow_rss_conf));
11762                         return 0;
11763                 }
11764                 return -EINVAL;
11765         }
11766
11767         if (rss_info->num)
11768                 return -EINVAL;
11769
11770         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
11771          * It's necessary to calculate the actual PF queues that are configured.
11772          */
11773         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
11774                 num = i40e_pf_calc_configured_queues_num(pf);
11775         else
11776                 num = pf->dev_data->nb_rx_queues;
11777
11778         num = RTE_MIN(num, conf->num);
11779         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
11780                         num);
11781
11782         if (num == 0) {
11783                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
11784                 return -ENOTSUP;
11785         }
11786
11787         /* Fill in redirection table */
11788         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
11789                 if (j == num)
11790                         j = 0;
11791                 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
11792                         hw->func_caps.rss_table_entry_width) - 1));
11793                 if ((i & 3) == 3)
11794                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
11795         }
11796
11797         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
11798                 i40e_pf_disable_rss(pf);
11799                 return 0;
11800         }
11801         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
11802                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
11803                 /* Random default keys */
11804                 static uint32_t rss_key_default[] = {0x6b793944,
11805                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
11806                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
11807                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
11808
11809                 rss_conf.rss_key = (uint8_t *)rss_key_default;
11810                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
11811                                                         sizeof(uint32_t);
11812         }
11813
11814         i40e_hw_rss_hash_set(pf, &rss_conf);
11815
11816         rte_memcpy(rss_info,
11817                 conf, sizeof(struct i40e_rte_flow_rss_conf));
11818
11819         return 0;
11820 }
11821
11822 RTE_INIT(i40e_init_log);
11823 static void
11824 i40e_init_log(void)
11825 {
11826         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
11827         if (i40e_logtype_init >= 0)
11828                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11829         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
11830         if (i40e_logtype_driver >= 0)
11831                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11832 }