drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66 #include "rte_pmd_i40e.h"
  67
  68 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  69 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  70
  71 #define I40E_CLEAR_PXE_WAIT_MS     200
  72
  73 /* Maximun number of capability elements */
  74 #define I40E_MAX_CAP_ELE_NUM       128
  75
  76 /* Wait count and inteval */
  77 #define I40E_CHK_Q_ENA_COUNT       1000
  78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  79
  80 /* Maximun number of VSI */
  81 #define I40E_MAX_NUM_VSIS          (384UL)
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 117
 118 #define I40E_FLOW_TYPES ( \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 129         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 130
 131 /* Additional timesync values. */
 132 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA     0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 137 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 138
 139 #define I40E_MAX_PERCENT            100
 140 #define I40E_DEFAULT_DCB_APP_NUM    1
 141 #define I40E_DEFAULT_DCB_APP_PRIO   3
 142
 143 /**
 144  * Below are values for writing un-exposed registers suggested
 145  * by silicon experts
 146  */
 147 /* Destination MAC address */
 148 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 149 /* Source MAC address */
 150 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 155 /* Single VLAN tag in the inner L2 header */
 156 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 157 /* Source IPv4 address */
 158 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 159 /* Destination IPv4 address */
 160 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 161 /* Source IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 163 /* Destination IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 165 /* IPv4 Protocol for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 167 /* IPv4 Time to Live for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 169 /* IPv4 Type of Service (TOS) */
 170 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 171 /* IPv4 Protocol */
 172 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 173 /* IPv4 Time to Live */
 174 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 175 /* Source IPv6 address */
 176 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 177 /* Destination IPv6 address */
 178 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 179 /* IPv6 Traffic Class (TC) */
 180 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 181 /* IPv6 Next Header */
 182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 183 /* IPv6 Hop Limit */
 184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 185 /* Source L4 port */
 186 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 187 /* Destination L4 port */
 188 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 189 /* SCTP verification tag */
 190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 193 /* Source port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 195 /* Destination port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 197 /* UDP Tunneling ID, NVGRE/GRE key */
 198 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 199 /* Last ether type */
 200 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 201 /* Tunneling outer destination IPv4 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 203 /* Tunneling outer destination IPv6 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 205 /* 1st word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 207 /* 2nd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 209 /* 3rd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 211 /* 4th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 213 /* 5th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 215 /* 6th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 217 /* 7th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 219 /* 8th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 221 /* all 8 words flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 223 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 224
 225 #define I40E_TRANSLATE_INSET 0
 226 #define I40E_TRANSLATE_REG   1
 227
 228 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 229 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 230 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 231 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 233 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 234
 235 /* PCI offset for querying capability */
 236 #define PCI_DEV_CAP_REG            0xA4
 237 /* PCI offset for enabling/disabling Extended Tag */
 238 #define PCI_DEV_CTRL_REG           0xA8
 239 /* Bit mask of Extended Tag capability */
 240 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 241 /* Bit shift of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 243 /* Bit mask of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 245
 246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int i40e_dev_configure(struct rte_eth_dev *dev);
 249 static int i40e_dev_start(struct rte_eth_dev *dev);
 250 static void i40e_dev_stop(struct rte_eth_dev *dev);
 251 static void i40e_dev_close(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_stats *stats);
 260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_xstat *xstats, unsigned n);
 262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 263                                      struct rte_eth_xstat_name *xstats_names,
 264                                      unsigned limit);
 265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id,
 268                                             uint8_t stat_idx,
 269                                             uint8_t is_rx);
 270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 271                                 char *fw_version, size_t fw_size);
 272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 273                               struct rte_eth_dev_info *dev_info);
 274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 275                                 uint16_t vlan_id,
 276                                 int on);
 277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 278                               enum rte_vlan_type vlan_type,
 279                               uint16_t tpid);
 280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 282                                       uint16_t queue,
 283                                       int on);
 284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 288                               struct rte_eth_fc_conf *fc_conf);
 289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 292                                        struct rte_eth_pfc_conf *pfc_conf);
 293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 294                           struct ether_addr *mac_addr,
 295                           uint32_t index,
 296                           uint32_t pool);
 297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 299                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 300                                     uint16_t reta_size);
 301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 302                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                    uint16_t reta_size);
 304
 305 static int i40e_get_cap(struct i40e_hw *hw);
 306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 307 static int i40e_pf_setup(struct i40e_pf *pf);
 308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 313                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 314 static void i40e_stat_update_48(struct i40e_hw *hw,
 315                                uint32_t hireg,
 316                                uint32_t loreg,
 317                                bool offset_loaded,
 318                                uint64_t *offset,
 319                                uint64_t *stat);
 320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 322                                        void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              struct ether_addr *addr);
 340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 341                                              struct i40e_macvlan_filter *mv_f,
 342                                              int num,
 343                                              uint16_t vlan);
 344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 346                                     struct rte_eth_rss_conf *rss_conf);
 347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 348                                       struct rte_eth_rss_conf *rss_conf);
 349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 350                                         struct rte_eth_udp_tunnel *udp_tunnel);
 351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 352                                         struct rte_eth_udp_tunnel *udp_tunnel);
 353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 358                                 enum rte_filter_type filter_type,
 359                                 enum rte_filter_op filter_op,
 360                                 void *arg);
 361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 362                                   struct rte_eth_dcb_info *dcb_info);
 363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 364 static void i40e_configure_registers(struct i40e_hw *hw);
 365 static void i40e_hw_init(struct rte_eth_dev *dev);
 366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 368                         struct rte_eth_mirror_conf *mirror_conf,
 369                         uint8_t sw_id, uint8_t on);
 370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 371
 372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp,
 376                                            uint32_t flags);
 377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 378                                            struct timespec *timestamp);
 379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 380
 381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 382
 383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 384                                    struct timespec *timestamp);
 385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 386                                     const struct timespec *timestamp);
 387
 388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 389                                          uint16_t queue_id);
 390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 391                                           uint16_t queue_id);
 392
 393 static int i40e_get_regs(struct rte_eth_dev *dev,
 394                          struct rte_dev_reg_info *regs);
 395
 396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 397
 398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 399                            struct rte_dev_eeprom_info *eeprom);
 400
 401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 402                                       struct ether_addr *mac_addr);
 403
 404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 405
 406 static int i40e_ethertype_filter_convert(
 407         const struct rte_eth_ethertype_filter *input,
 408         struct i40e_ethertype_filter *filter);
 409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 410                                    struct i40e_ethertype_filter *filter);
 411
 412 static int i40e_tunnel_filter_convert(
 413         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 414         struct i40e_tunnel_filter *tunnel_filter);
 415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 416                                 struct i40e_tunnel_filter *tunnel_filter);
 417
 418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 420 static void i40e_filter_restore(struct i40e_pf *pf);
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { .vendor_id = 0, /* sentinel */ },
 444 };
 445
 446 static const struct eth_dev_ops i40e_eth_dev_ops = {
 447         .dev_configure                = i40e_dev_configure,
 448         .dev_start                    = i40e_dev_start,
 449         .dev_stop                     = i40e_dev_stop,
 450         .dev_close                    = i40e_dev_close,
 451         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 452         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 453         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 454         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 455         .dev_set_link_up              = i40e_dev_set_link_up,
 456         .dev_set_link_down            = i40e_dev_set_link_down,
 457         .link_update                  = i40e_dev_link_update,
 458         .stats_get                    = i40e_dev_stats_get,
 459         .xstats_get                   = i40e_dev_xstats_get,
 460         .xstats_get_names             = i40e_dev_xstats_get_names,
 461         .stats_reset                  = i40e_dev_stats_reset,
 462         .xstats_reset                 = i40e_dev_stats_reset,
 463         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 464         .fw_version_get               = i40e_fw_version_get,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .rx_queue_count               = i40e_dev_rx_queue_count,
 481         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 482         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 483         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 484         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 485         .tx_queue_release             = i40e_dev_tx_queue_release,
 486         .dev_led_on                   = i40e_dev_led_on,
 487         .dev_led_off                  = i40e_dev_led_off,
 488         .flow_ctrl_get                = i40e_flow_ctrl_get,
 489         .flow_ctrl_set                = i40e_flow_ctrl_set,
 490         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 491         .mac_addr_add                 = i40e_macaddr_add,
 492         .mac_addr_remove              = i40e_macaddr_remove,
 493         .reta_update                  = i40e_dev_rss_reta_update,
 494         .reta_query                   = i40e_dev_rss_reta_query,
 495         .rss_hash_update              = i40e_dev_rss_hash_update,
 496         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 497         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 498         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 499         .filter_ctrl                  = i40e_dev_filter_ctrl,
 500         .rxq_info_get                 = i40e_rxq_info_get,
 501         .txq_info_get                 = i40e_txq_info_get,
 502         .mirror_rule_set              = i40e_mirror_rule_set,
 503         .mirror_rule_reset            = i40e_mirror_rule_reset,
 504         .timesync_enable              = i40e_timesync_enable,
 505         .timesync_disable             = i40e_timesync_disable,
 506         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 507         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 508         .get_dcb_info                 = i40e_dev_get_dcb_info,
 509         .timesync_adjust_time         = i40e_timesync_adjust_time,
 510         .timesync_read_time           = i40e_timesync_read_time,
 511         .timesync_write_time          = i40e_timesync_write_time,
 512         .get_reg                      = i40e_get_regs,
 513         .get_eeprom_length            = i40e_get_eeprom_length,
 514         .get_eeprom                   = i40e_get_eeprom,
 515         .mac_addr_set                 = i40e_set_default_mac_addr,
 516         .mtu_set                      = i40e_dev_mtu_set,
 517 };
 518
 519 /* store statistics names and its offset in stats structure */
 520 struct rte_i40e_xstats_name_off {
 521         char name[RTE_ETH_XSTATS_NAME_SIZE];
 522         unsigned offset;
 523 };
 524
 525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 526         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 527         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 528         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 529         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 530         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 531                 rx_unknown_protocol)},
 532         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 533         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 534         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 535         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 536 };
 537
 538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 539                 sizeof(rte_i40e_stats_strings[0]))
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 542         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 543                 tx_dropped_link_down)},
 544         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 545         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 546                 illegal_bytes)},
 547         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 548         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_local_faults)},
 550         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_remote_faults)},
 552         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_length_errors)},
 554         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 555         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 556         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 557         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 558         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 559         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_127)},
 561         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_255)},
 563         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_511)},
 565         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1023)},
 567         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1522)},
 569         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_big)},
 571         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_undersize)},
 573         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_oversize)},
 575         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 576                 mac_short_packet_dropped)},
 577         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_fragments)},
 579         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 580         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 581         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_127)},
 583         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_255)},
 585         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_511)},
 587         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1023)},
 589         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1522)},
 591         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_big)},
 593         {"rx_flow_director_atr_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 595         {"rx_flow_director_sb_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 597         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_status)},
 599         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_status)},
 601         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_count)},
 603         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_count)},
 605 };
 606
 607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 608                 sizeof(rte_i40e_hw_port_strings[0]))
 609
 610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 611         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_rx)},
 613         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xoff_rx)},
 615 };
 616
 617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 618                 sizeof(rte_i40e_rxq_prio_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_tx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_tx)},
 625         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_2_xoff)},
 627 };
 628
 629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 630                 sizeof(rte_i40e_txq_prio_strings[0]))
 631
 632 static struct eth_driver rte_i40e_pmd = {
 633         .pci_drv = {
 634                 .id_table = pci_id_i40e_map,
 635                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 636                 .probe = rte_eth_dev_pci_probe,
 637                 .remove = rte_eth_dev_pci_remove,
 638         },
 639         .eth_dev_init = eth_i40e_dev_init,
 640         .eth_dev_uninit = eth_i40e_dev_uninit,
 641         .dev_private_size = sizeof(struct i40e_adapter),
 642 };
 643
 644 static inline int
 645 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 646                                      struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = link;
 649         struct rte_eth_link *src = &(dev->data->dev_link);
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 static inline int
 659 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 660                                       struct rte_eth_link *link)
 661 {
 662         struct rte_eth_link *dst = &(dev->data->dev_link);
 663         struct rte_eth_link *src = link;
 664
 665         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 666                                         *(uint64_t *)src) == 0)
 667                 return -1;
 668
 669         return 0;
 670 }
 671
 672 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 673 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 674 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 675
 676 #ifndef I40E_GLQF_ORT
 677 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 678 #endif
 679 #ifndef I40E_GLQF_PIT
 680 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 681 #endif
 682
 683 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 684 {
 685         /*
 686          * Initialize registers for flexible payload, which should be set by NVM.
 687          * This should be removed from code once it is fixed in NVM.
 688          */
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 696         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 697         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 698         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 699         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 700         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 701
 702         /* Initialize registers for parsing packet type of QinQ */
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 704         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 705 }
 706
 707 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 708
 709 /*
 710  * Add a ethertype filter to drop all flow control frames transmitted
 711  * from VSIs.
 712 */
 713 static void
 714 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 715 {
 716         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 717         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 718                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 719                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 720         int ret;
 721
 722         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 723                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 724                                 pf->main_vsi_seid, 0,
 725                                 TRUE, NULL, NULL);
 726         if (ret)
 727                 PMD_INIT_LOG(ERR,
 728                         "Failed to add filter to drop flow control frames from VSIs.");
 729 }
 730
 731 static int
 732 floating_veb_list_handler(__rte_unused const char *key,
 733                           const char *floating_veb_value,
 734                           void *opaque)
 735 {
 736         int idx = 0;
 737         unsigned int count = 0;
 738         char *end = NULL;
 739         int min, max;
 740         bool *vf_floating_veb = opaque;
 741
 742         while (isblank(*floating_veb_value))
 743                 floating_veb_value++;
 744
 745         /* Reset floating VEB configuration for VFs */
 746         for (idx = 0; idx < I40E_MAX_VF; idx++)
 747                 vf_floating_veb[idx] = false;
 748
 749         min = I40E_MAX_VF;
 750         do {
 751                 while (isblank(*floating_veb_value))
 752                         floating_veb_value++;
 753                 if (*floating_veb_value == '\0')
 754                         return -1;
 755                 errno = 0;
 756                 idx = strtoul(floating_veb_value, &end, 10);
 757                 if (errno || end == NULL)
 758                         return -1;
 759                 while (isblank(*end))
 760                         end++;
 761                 if (*end == '-') {
 762                         min = idx;
 763                 } else if ((*end == ';') || (*end == '\0')) {
 764                         max = idx;
 765                         if (min == I40E_MAX_VF)
 766                                 min = idx;
 767                         if (max >= I40E_MAX_VF)
 768                                 max = I40E_MAX_VF - 1;
 769                         for (idx = min; idx <= max; idx++) {
 770                                 vf_floating_veb[idx] = true;
 771                                 count++;
 772                         }
 773                         min = I40E_MAX_VF;
 774                 } else {
 775                         return -1;
 776                 }
 777                 floating_veb_value = end + 1;
 778         } while (*end != '\0');
 779
 780         if (count == 0)
 781                 return -1;
 782
 783         return 0;
 784 }
 785
 786 static void
 787 config_vf_floating_veb(struct rte_devargs *devargs,
 788                        uint16_t floating_veb,
 789                        bool *vf_floating_veb)
 790 {
 791         struct rte_kvargs *kvlist;
 792         int i;
 793         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 794
 795         if (!floating_veb)
 796                 return;
 797         /* All the VFs attach to the floating VEB by default
 798          * when the floating VEB is enabled.
 799          */
 800         for (i = 0; i < I40E_MAX_VF; i++)
 801                 vf_floating_veb[i] = true;
 802
 803         if (devargs == NULL)
 804                 return;
 805
 806         kvlist = rte_kvargs_parse(devargs->args, NULL);
 807         if (kvlist == NULL)
 808                 return;
 809
 810         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 811                 rte_kvargs_free(kvlist);
 812                 return;
 813         }
 814         /* When the floating_veb_list parameter exists, all the VFs
 815          * will attach to the legacy VEB firstly, then configure VFs
 816          * to the floating VEB according to the floating_veb_list.
 817          */
 818         if (rte_kvargs_process(kvlist, floating_veb_list,
 819                                floating_veb_list_handler,
 820                                vf_floating_veb) < 0) {
 821                 rte_kvargs_free(kvlist);
 822                 return;
 823         }
 824         rte_kvargs_free(kvlist);
 825 }
 826
 827 static int
 828 i40e_check_floating_handler(__rte_unused const char *key,
 829                             const char *value,
 830                             __rte_unused void *opaque)
 831 {
 832         if (strcmp(value, "1"))
 833                 return -1;
 834
 835         return 0;
 836 }
 837
 838 static int
 839 is_floating_veb_supported(struct rte_devargs *devargs)
 840 {
 841         struct rte_kvargs *kvlist;
 842         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 843
 844         if (devargs == NULL)
 845                 return 0;
 846
 847         kvlist = rte_kvargs_parse(devargs->args, NULL);
 848         if (kvlist == NULL)
 849                 return 0;
 850
 851         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 852                 rte_kvargs_free(kvlist);
 853                 return 0;
 854         }
 855         /* Floating VEB is enabled when there's key-value:
 856          * enable_floating_veb=1
 857          */
 858         if (rte_kvargs_process(kvlist, floating_veb_key,
 859                                i40e_check_floating_handler, NULL) < 0) {
 860                 rte_kvargs_free(kvlist);
 861                 return 0;
 862         }
 863         rte_kvargs_free(kvlist);
 864
 865         return 1;
 866 }
 867
 868 static void
 869 config_floating_veb(struct rte_eth_dev *dev)
 870 {
 871         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 873         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 874
 875         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 876
 877         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 878                 pf->floating_veb =
 879                         is_floating_veb_supported(pci_dev->device.devargs);
 880                 config_vf_floating_veb(pci_dev->device.devargs,
 881                                        pf->floating_veb,
 882                                        pf->floating_veb_list);
 883         } else {
 884                 pf->floating_veb = false;
 885         }
 886 }
 887
 888 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 889 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 890
 891 static int
 892 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 893 {
 894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 895         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 896         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 897         int ret;
 898
 899         struct rte_hash_parameters ethertype_hash_params = {
 900                 .name = ethertype_hash_name,
 901                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 902                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 903                 .hash_func = rte_hash_crc,
 904                 .hash_func_init_val = 0,
 905                 .socket_id = rte_socket_id(),
 906         };
 907
 908         /* Initialize ethertype filter rule list and hash */
 909         TAILQ_INIT(&ethertype_rule->ethertype_list);
 910         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 911                  "ethertype_%s", dev->data->name);
 912         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 913         if (!ethertype_rule->hash_table) {
 914                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 915                 return -EINVAL;
 916         }
 917         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 918                                        sizeof(struct i40e_ethertype_filter *) *
 919                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 920                                        0);
 921         if (!ethertype_rule->hash_map) {
 922                 PMD_INIT_LOG(ERR,
 923                              "Failed to allocate memory for ethertype hash map!");
 924                 ret = -ENOMEM;
 925                 goto err_ethertype_hash_map_alloc;
 926         }
 927
 928         return 0;
 929
 930 err_ethertype_hash_map_alloc:
 931         rte_hash_free(ethertype_rule->hash_table);
 932
 933         return ret;
 934 }
 935
 936 static int
 937 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 938 {
 939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 940         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 941         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 942         int ret;
 943
 944         struct rte_hash_parameters tunnel_hash_params = {
 945                 .name = tunnel_hash_name,
 946                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 947                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 948                 .hash_func = rte_hash_crc,
 949                 .hash_func_init_val = 0,
 950                 .socket_id = rte_socket_id(),
 951         };
 952
 953         /* Initialize tunnel filter rule list and hash */
 954         TAILQ_INIT(&tunnel_rule->tunnel_list);
 955         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 956                  "tunnel_%s", dev->data->name);
 957         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 958         if (!tunnel_rule->hash_table) {
 959                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 960                 return -EINVAL;
 961         }
 962         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 963                                     sizeof(struct i40e_tunnel_filter *) *
 964                                     I40E_MAX_TUNNEL_FILTER_NUM,
 965                                     0);
 966         if (!tunnel_rule->hash_map) {
 967                 PMD_INIT_LOG(ERR,
 968                              "Failed to allocate memory for tunnel hash map!");
 969                 ret = -ENOMEM;
 970                 goto err_tunnel_hash_map_alloc;
 971         }
 972
 973         return 0;
 974
 975 err_tunnel_hash_map_alloc:
 976         rte_hash_free(tunnel_rule->hash_table);
 977
 978         return ret;
 979 }
 980
 981 static int
 982 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 983 {
 984         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 985         struct i40e_fdir_info *fdir_info = &pf->fdir;
 986         char fdir_hash_name[RTE_HASH_NAMESIZE];
 987         int ret;
 988
 989         struct rte_hash_parameters fdir_hash_params = {
 990                 .name = fdir_hash_name,
 991                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 992                 .key_len = sizeof(struct rte_eth_fdir_input),
 993                 .hash_func = rte_hash_crc,
 994                 .hash_func_init_val = 0,
 995                 .socket_id = rte_socket_id(),
 996         };
 997
 998         /* Initialize flow director filter rule list and hash */
 999         TAILQ_INIT(&fdir_info->fdir_list);
1000         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1001                  "fdir_%s", dev->data->name);
1002         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1003         if (!fdir_info->hash_table) {
1004                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1005                 return -EINVAL;
1006         }
1007         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1008                                           sizeof(struct i40e_fdir_filter *) *
1009                                           I40E_MAX_FDIR_FILTER_NUM,
1010                                           0);
1011         if (!fdir_info->hash_map) {
1012                 PMD_INIT_LOG(ERR,
1013                              "Failed to allocate memory for fdir hash map!");
1014                 ret = -ENOMEM;
1015                 goto err_fdir_hash_map_alloc;
1016         }
1017         return 0;
1018
1019 err_fdir_hash_map_alloc:
1020         rte_hash_free(fdir_info->hash_table);
1021
1022         return ret;
1023 }
1024
1025 static int
1026 eth_i40e_dev_init(struct rte_eth_dev *dev)
1027 {
1028         struct rte_pci_device *pci_dev;
1029         struct rte_intr_handle *intr_handle;
1030         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032         struct i40e_vsi *vsi;
1033         int ret;
1034         uint32_t len;
1035         uint8_t aq_fail = 0;
1036
1037         PMD_INIT_FUNC_TRACE();
1038
1039         dev->dev_ops = &i40e_eth_dev_ops;
1040         dev->rx_pkt_burst = i40e_recv_pkts;
1041         dev->tx_pkt_burst = i40e_xmit_pkts;
1042         dev->tx_pkt_prepare = i40e_prep_pkts;
1043
1044         /* for secondary processes, we don't initialise any further as primary
1045          * has already done this work. Only check we don't need a different
1046          * RX function */
1047         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1048                 i40e_set_rx_function(dev);
1049                 i40e_set_tx_function(dev);
1050                 return 0;
1051         }
1052         pci_dev = I40E_DEV_TO_PCI(dev);
1053         intr_handle = &pci_dev->intr_handle;
1054
1055         rte_eth_copy_pci_info(dev, pci_dev);
1056         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1057
1058         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1059         pf->adapter->eth_dev = dev;
1060         pf->dev_data = dev->data;
1061
1062         hw->back = I40E_PF_TO_ADAPTER(pf);
1063         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1064         if (!hw->hw_addr) {
1065                 PMD_INIT_LOG(ERR,
1066                         "Hardware is not available, as address is NULL");
1067                 return -ENODEV;
1068         }
1069
1070         hw->vendor_id = pci_dev->id.vendor_id;
1071         hw->device_id = pci_dev->id.device_id;
1072         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1073         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1074         hw->bus.device = pci_dev->addr.devid;
1075         hw->bus.func = pci_dev->addr.function;
1076         hw->adapter_stopped = 0;
1077
1078         /* Make sure all is clean before doing PF reset */
1079         i40e_clear_hw(hw);
1080
1081         /* Initialize the hardware */
1082         i40e_hw_init(dev);
1083
1084         /* Reset here to make sure all is clean for each PF */
1085         ret = i40e_pf_reset(hw);
1086         if (ret) {
1087                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1088                 return ret;
1089         }
1090
1091         /* Initialize the shared code (base driver) */
1092         ret = i40e_init_shared_code(hw);
1093         if (ret) {
1094                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1095                 return ret;
1096         }
1097
1098         /*
1099          * To work around the NVM issue, initialize registers
1100          * for flexible payload and packet type of QinQ by
1101          * software. It should be removed once issues are fixed
1102          * in NVM.
1103          */
1104         i40e_GLQF_reg_init(hw);
1105
1106         /* Initialize the input set for filters (hash and fd) to default value */
1107         i40e_filter_input_set_init(pf);
1108
1109         /* Initialize the parameters for adminq */
1110         i40e_init_adminq_parameter(hw);
1111         ret = i40e_init_adminq(hw);
1112         if (ret != I40E_SUCCESS) {
1113                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1114                 return -EIO;
1115         }
1116         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1117                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1118                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1119                      ((hw->nvm.version >> 12) & 0xf),
1120                      ((hw->nvm.version >> 4) & 0xff),
1121                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1122
1123         /* Need the special FW version to support floating VEB */
1124         config_floating_veb(dev);
1125         /* Clear PXE mode */
1126         i40e_clear_pxe_mode(hw);
1127         ret = i40e_dev_sync_phy_type(hw);
1128         if (ret) {
1129                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1130                 goto err_sync_phy_type;
1131         }
1132         /*
1133          * On X710, performance number is far from the expectation on recent
1134          * firmware versions. The fix for this issue may not be integrated in
1135          * the following firmware version. So the workaround in software driver
1136          * is needed. It needs to modify the initial values of 3 internal only
1137          * registers. Note that the workaround can be removed when it is fixed
1138          * in firmware in the future.
1139          */
1140         i40e_configure_registers(hw);
1141
1142         /* Get hw capabilities */
1143         ret = i40e_get_cap(hw);
1144         if (ret != I40E_SUCCESS) {
1145                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1146                 goto err_get_capabilities;
1147         }
1148
1149         /* Initialize parameters for PF */
1150         ret = i40e_pf_parameter_init(dev);
1151         if (ret != 0) {
1152                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1153                 goto err_parameter_init;
1154         }
1155
1156         /* Initialize the queue management */
1157         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1158         if (ret < 0) {
1159                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1160                 goto err_qp_pool_init;
1161         }
1162         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1163                                 hw->func_caps.num_msix_vectors - 1);
1164         if (ret < 0) {
1165                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1166                 goto err_msix_pool_init;
1167         }
1168
1169         /* Initialize lan hmc */
1170         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1171                                 hw->func_caps.num_rx_qp, 0, 0);
1172         if (ret != I40E_SUCCESS) {
1173                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1174                 goto err_init_lan_hmc;
1175         }
1176
1177         /* Configure lan hmc */
1178         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1179         if (ret != I40E_SUCCESS) {
1180                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1181                 goto err_configure_lan_hmc;
1182         }
1183
1184         /* Get and check the mac address */
1185         i40e_get_mac_addr(hw, hw->mac.addr);
1186         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1187                 PMD_INIT_LOG(ERR, "mac address is not valid");
1188                 ret = -EIO;
1189                 goto err_get_mac_addr;
1190         }
1191         /* Copy the permanent MAC address */
1192         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1193                         (struct ether_addr *) hw->mac.perm_addr);
1194
1195         /* Disable flow control */
1196         hw->fc.requested_mode = I40E_FC_NONE;
1197         i40e_set_fc(hw, &aq_fail, TRUE);
1198
1199         /* Set the global registers with default ether type value */
1200         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1201         if (ret != I40E_SUCCESS) {
1202                 PMD_INIT_LOG(ERR,
1203                         "Failed to set the default outer VLAN ether type");
1204                 goto err_setup_pf_switch;
1205         }
1206
1207         /* PF setup, which includes VSI setup */
1208         ret = i40e_pf_setup(pf);
1209         if (ret) {
1210                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1211                 goto err_setup_pf_switch;
1212         }
1213
1214         /* reset all stats of the device, including pf and main vsi */
1215         i40e_dev_stats_reset(dev);
1216
1217         vsi = pf->main_vsi;
1218
1219         /* Disable double vlan by default */
1220         i40e_vsi_config_double_vlan(vsi, FALSE);
1221
1222         /* Disable S-TAG identification when floating_veb is disabled */
1223         if (!pf->floating_veb) {
1224                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1225                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1226                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1227                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1228                 }
1229         }
1230
1231         if (!vsi->max_macaddrs)
1232                 len = ETHER_ADDR_LEN;
1233         else
1234                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1235
1236         /* Should be after VSI initialized */
1237         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1238         if (!dev->data->mac_addrs) {
1239                 PMD_INIT_LOG(ERR,
1240                         "Failed to allocated memory for storing mac address");
1241                 goto err_mac_alloc;
1242         }
1243         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1244                                         &dev->data->mac_addrs[0]);
1245
1246         /* initialize pf host driver to setup SRIOV resource if applicable */
1247         i40e_pf_host_init(dev);
1248
1249         /* register callback func to eal lib */
1250         rte_intr_callback_register(intr_handle,
1251                                    i40e_dev_interrupt_handler, dev);
1252
1253         /* configure and enable device interrupt */
1254         i40e_pf_config_irq0(hw, TRUE);
1255         i40e_pf_enable_irq0(hw);
1256
1257         /* enable uio intr after callback register */
1258         rte_intr_enable(intr_handle);
1259         /*
1260          * Add an ethertype filter to drop all flow control frames transmitted
1261          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1262          * frames to wire.
1263          */
1264         i40e_add_tx_flow_control_drop_filter(pf);
1265
1266         /* Set the max frame size to 0x2600 by default,
1267          * in case other drivers changed the default value.
1268          */
1269         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1270
1271         /* initialize mirror rule list */
1272         TAILQ_INIT(&pf->mirror_list);
1273
1274         /* Init dcb to sw mode by default */
1275         ret = i40e_dcb_init_configure(dev, TRUE);
1276         if (ret != I40E_SUCCESS) {
1277                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1278                 pf->flags &= ~I40E_FLAG_DCB;
1279         }
1280
1281         ret = i40e_init_ethtype_filter_list(dev);
1282         if (ret < 0)
1283                 goto err_init_ethtype_filter_list;
1284         ret = i40e_init_tunnel_filter_list(dev);
1285         if (ret < 0)
1286                 goto err_init_tunnel_filter_list;
1287         ret = i40e_init_fdir_filter_list(dev);
1288         if (ret < 0)
1289                 goto err_init_fdir_filter_list;
1290
1291         return 0;
1292
1293 err_init_fdir_filter_list:
1294         rte_free(pf->tunnel.hash_table);
1295         rte_free(pf->tunnel.hash_map);
1296 err_init_tunnel_filter_list:
1297         rte_free(pf->ethertype.hash_table);
1298         rte_free(pf->ethertype.hash_map);
1299 err_init_ethtype_filter_list:
1300         rte_free(dev->data->mac_addrs);
1301 err_mac_alloc:
1302         i40e_vsi_release(pf->main_vsi);
1303 err_setup_pf_switch:
1304 err_get_mac_addr:
1305 err_configure_lan_hmc:
1306         (void)i40e_shutdown_lan_hmc(hw);
1307 err_init_lan_hmc:
1308         i40e_res_pool_destroy(&pf->msix_pool);
1309 err_msix_pool_init:
1310         i40e_res_pool_destroy(&pf->qp_pool);
1311 err_qp_pool_init:
1312 err_parameter_init:
1313 err_get_capabilities:
1314 err_sync_phy_type:
1315         (void)i40e_shutdown_adminq(hw);
1316
1317         return ret;
1318 }
1319
1320 static void
1321 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1322 {
1323         struct i40e_ethertype_filter *p_ethertype;
1324         struct i40e_ethertype_rule *ethertype_rule;
1325
1326         ethertype_rule = &pf->ethertype;
1327         /* Remove all ethertype filter rules and hash */
1328         if (ethertype_rule->hash_map)
1329                 rte_free(ethertype_rule->hash_map);
1330         if (ethertype_rule->hash_table)
1331                 rte_hash_free(ethertype_rule->hash_table);
1332
1333         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1334                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1335                              p_ethertype, rules);
1336                 rte_free(p_ethertype);
1337         }
1338 }
1339
1340 static void
1341 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1342 {
1343         struct i40e_tunnel_filter *p_tunnel;
1344         struct i40e_tunnel_rule *tunnel_rule;
1345
1346         tunnel_rule = &pf->tunnel;
1347         /* Remove all tunnel director rules and hash */
1348         if (tunnel_rule->hash_map)
1349                 rte_free(tunnel_rule->hash_map);
1350         if (tunnel_rule->hash_table)
1351                 rte_hash_free(tunnel_rule->hash_table);
1352
1353         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1354                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1355                 rte_free(p_tunnel);
1356         }
1357 }
1358
1359 static void
1360 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1361 {
1362         struct i40e_fdir_filter *p_fdir;
1363         struct i40e_fdir_info *fdir_info;
1364
1365         fdir_info = &pf->fdir;
1366         /* Remove all flow director rules and hash */
1367         if (fdir_info->hash_map)
1368                 rte_free(fdir_info->hash_map);
1369         if (fdir_info->hash_table)
1370                 rte_hash_free(fdir_info->hash_table);
1371
1372         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1373                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1374                 rte_free(p_fdir);
1375         }
1376 }
1377
1378 static int
1379 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1380 {
1381         struct i40e_pf *pf;
1382         struct rte_pci_device *pci_dev;
1383         struct rte_intr_handle *intr_handle;
1384         struct i40e_hw *hw;
1385         struct i40e_filter_control_settings settings;
1386         struct rte_flow *p_flow;
1387         int ret;
1388         uint8_t aq_fail = 0;
1389
1390         PMD_INIT_FUNC_TRACE();
1391
1392         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1393                 return 0;
1394
1395         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1396         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397         pci_dev = I40E_DEV_TO_PCI(dev);
1398         intr_handle = &pci_dev->intr_handle;
1399
1400         if (hw->adapter_stopped == 0)
1401                 i40e_dev_close(dev);
1402
1403         dev->dev_ops = NULL;
1404         dev->rx_pkt_burst = NULL;
1405         dev->tx_pkt_burst = NULL;
1406
1407         /* Clear PXE mode */
1408         i40e_clear_pxe_mode(hw);
1409
1410         /* Unconfigure filter control */
1411         memset(&settings, 0, sizeof(settings));
1412         ret = i40e_set_filter_control(hw, &settings);
1413         if (ret)
1414                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1415                                         ret);
1416
1417         /* Disable flow control */
1418         hw->fc.requested_mode = I40E_FC_NONE;
1419         i40e_set_fc(hw, &aq_fail, TRUE);
1420
1421         /* uninitialize pf host driver */
1422         i40e_pf_host_uninit(dev);
1423
1424         rte_free(dev->data->mac_addrs);
1425         dev->data->mac_addrs = NULL;
1426
1427         /* disable uio intr before callback unregister */
1428         rte_intr_disable(intr_handle);
1429
1430         /* register callback func to eal lib */
1431         rte_intr_callback_unregister(intr_handle,
1432                                      i40e_dev_interrupt_handler, dev);
1433
1434         i40e_rm_ethtype_filter_list(pf);
1435         i40e_rm_tunnel_filter_list(pf);
1436         i40e_rm_fdir_filter_list(pf);
1437
1438         /* Remove all flows */
1439         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1440                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1441                 rte_free(p_flow);
1442         }
1443
1444         return 0;
1445 }
1446
1447 static int
1448 i40e_dev_configure(struct rte_eth_dev *dev)
1449 {
1450         struct i40e_adapter *ad =
1451                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1452         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1453         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1454         int i, ret;
1455
1456         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1457          * bulk allocation or vector Rx preconditions we will reset it.
1458          */
1459         ad->rx_bulk_alloc_allowed = true;
1460         ad->rx_vec_allowed = true;
1461         ad->tx_simple_allowed = true;
1462         ad->tx_vec_allowed = true;
1463
1464         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1465                 ret = i40e_fdir_setup(pf);
1466                 if (ret != I40E_SUCCESS) {
1467                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1468                         return -ENOTSUP;
1469                 }
1470                 ret = i40e_fdir_configure(dev);
1471                 if (ret < 0) {
1472                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1473                         goto err;
1474                 }
1475         } else
1476                 i40e_fdir_teardown(pf);
1477
1478         ret = i40e_dev_init_vlan(dev);
1479         if (ret < 0)
1480                 goto err;
1481
1482         /* VMDQ setup.
1483          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1484          *  RSS setting have different requirements.
1485          *  General PMD driver call sequence are NIC init, configure,
1486          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1487          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1488          *  applicable. So, VMDQ setting has to be done before
1489          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1490          *  For RSS setting, it will try to calculate actual configured RX queue
1491          *  number, which will be available after rx_queue_setup(). dev_start()
1492          *  function is good to place RSS setup.
1493          */
1494         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1495                 ret = i40e_vmdq_setup(dev);
1496                 if (ret)
1497                         goto err;
1498         }
1499
1500         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1501                 ret = i40e_dcb_setup(dev);
1502                 if (ret) {
1503                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1504                         goto err_dcb;
1505                 }
1506         }
1507
1508         TAILQ_INIT(&pf->flow_list);
1509
1510         return 0;
1511
1512 err_dcb:
1513         /* need to release vmdq resource if exists */
1514         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1515                 i40e_vsi_release(pf->vmdq[i].vsi);
1516                 pf->vmdq[i].vsi = NULL;
1517         }
1518         rte_free(pf->vmdq);
1519         pf->vmdq = NULL;
1520 err:
1521         /* need to release fdir resource if exists */
1522         i40e_fdir_teardown(pf);
1523         return ret;
1524 }
1525
1526 void
1527 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1528 {
1529         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1530         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1531         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1532         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1533         uint16_t msix_vect = vsi->msix_intr;
1534         uint16_t i;
1535
1536         for (i = 0; i < vsi->nb_qps; i++) {
1537                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1538                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1539                 rte_wmb();
1540         }
1541
1542         if (vsi->type != I40E_VSI_SRIOV) {
1543                 if (!rte_intr_allow_others(intr_handle)) {
1544                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1545                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1546                         I40E_WRITE_REG(hw,
1547                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1548                                        0);
1549                 } else {
1550                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1551                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1552                         I40E_WRITE_REG(hw,
1553                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1554                                                        msix_vect - 1), 0);
1555                 }
1556         } else {
1557                 uint32_t reg;
1558                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1559                         vsi->user_param + (msix_vect - 1);
1560
1561                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1562                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1563         }
1564         I40E_WRITE_FLUSH(hw);
1565 }
1566
1567 static void
1568 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1569                        int base_queue, int nb_queue)
1570 {
1571         int i;
1572         uint32_t val;
1573         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1574
1575         /* Bind all RX queues to allocated MSIX interrupt */
1576         for (i = 0; i < nb_queue; i++) {
1577                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1578                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1579                         ((base_queue + i + 1) <<
1580                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1581                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1582                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1583
1584                 if (i == nb_queue - 1)
1585                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1586                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1587         }
1588
1589         /* Write first RX queue to Link list register as the head element */
1590         if (vsi->type != I40E_VSI_SRIOV) {
1591                 uint16_t interval =
1592                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1593
1594                 if (msix_vect == I40E_MISC_VEC_ID) {
1595                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1596                                        (base_queue <<
1597                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1598                                        (0x0 <<
1599                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1600                         I40E_WRITE_REG(hw,
1601                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1602                                        interval);
1603                 } else {
1604                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1605                                        (base_queue <<
1606                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1607                                        (0x0 <<
1608                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1609                         I40E_WRITE_REG(hw,
1610                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1611                                                        msix_vect - 1),
1612                                        interval);
1613                 }
1614         } else {
1615                 uint32_t reg;
1616
1617                 if (msix_vect == I40E_MISC_VEC_ID) {
1618                         I40E_WRITE_REG(hw,
1619                                        I40E_VPINT_LNKLST0(vsi->user_param),
1620                                        (base_queue <<
1621                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1622                                        (0x0 <<
1623                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1624                 } else {
1625                         /* num_msix_vectors_vf needs to minus irq0 */
1626                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1627                                 vsi->user_param + (msix_vect - 1);
1628
1629                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1630                                        (base_queue <<
1631                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1632                                        (0x0 <<
1633                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1634                 }
1635         }
1636
1637         I40E_WRITE_FLUSH(hw);
1638 }
1639
1640 void
1641 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1642 {
1643         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1644         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1645         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1646         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1647         uint16_t msix_vect = vsi->msix_intr;
1648         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1649         uint16_t queue_idx = 0;
1650         int record = 0;
1651         uint32_t val;
1652         int i;
1653
1654         for (i = 0; i < vsi->nb_qps; i++) {
1655                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1656                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1657         }
1658
1659         /* INTENA flag is not auto-cleared for interrupt */
1660         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1661         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1662                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1663                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1664         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1665
1666         /* VF bind interrupt */
1667         if (vsi->type == I40E_VSI_SRIOV) {
1668                 __vsi_queues_bind_intr(vsi, msix_vect,
1669                                        vsi->base_queue, vsi->nb_qps);
1670                 return;
1671         }
1672
1673         /* PF & VMDq bind interrupt */
1674         if (rte_intr_dp_is_en(intr_handle)) {
1675                 if (vsi->type == I40E_VSI_MAIN) {
1676                         queue_idx = 0;
1677                         record = 1;
1678                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1679                         struct i40e_vsi *main_vsi =
1680                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1681                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1682                         record = 1;
1683                 }
1684         }
1685
1686         for (i = 0; i < vsi->nb_used_qps; i++) {
1687                 if (nb_msix <= 1) {
1688                         if (!rte_intr_allow_others(intr_handle))
1689                                 /* allow to share MISC_VEC_ID */
1690                                 msix_vect = I40E_MISC_VEC_ID;
1691
1692                         /* no enough msix_vect, map all to one */
1693                         __vsi_queues_bind_intr(vsi, msix_vect,
1694                                                vsi->base_queue + i,
1695                                                vsi->nb_used_qps - i);
1696                         for (; !!record && i < vsi->nb_used_qps; i++)
1697                                 intr_handle->intr_vec[queue_idx + i] =
1698                                         msix_vect;
1699                         break;
1700                 }
1701                 /* 1:1 queue/msix_vect mapping */
1702                 __vsi_queues_bind_intr(vsi, msix_vect,
1703                                        vsi->base_queue + i, 1);
1704                 if (!!record)
1705                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1706
1707                 msix_vect++;
1708                 nb_msix--;
1709         }
1710 }
1711
1712 static void
1713 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1714 {
1715         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1716         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1717         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1718         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1719         uint16_t interval = i40e_calc_itr_interval(\
1720                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1721         uint16_t msix_intr, i;
1722
1723         if (rte_intr_allow_others(intr_handle))
1724                 for (i = 0; i < vsi->nb_msix; i++) {
1725                         msix_intr = vsi->msix_intr + i;
1726                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1727                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1728                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1729                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1730                                 (interval <<
1731                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1732                 }
1733         else
1734                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1735                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1736                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1737                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1738                                (interval <<
1739                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1740
1741         I40E_WRITE_FLUSH(hw);
1742 }
1743
1744 static void
1745 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1746 {
1747         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1748         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1749         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1750         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1751         uint16_t msix_intr, i;
1752
1753         if (rte_intr_allow_others(intr_handle))
1754                 for (i = 0; i < vsi->nb_msix; i++) {
1755                         msix_intr = vsi->msix_intr + i;
1756                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1757                                        0);
1758                 }
1759         else
1760                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1761
1762         I40E_WRITE_FLUSH(hw);
1763 }
1764
1765 static inline uint8_t
1766 i40e_parse_link_speeds(uint16_t link_speeds)
1767 {
1768         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1769
1770         if (link_speeds & ETH_LINK_SPEED_40G)
1771                 link_speed |= I40E_LINK_SPEED_40GB;
1772         if (link_speeds & ETH_LINK_SPEED_25G)
1773                 link_speed |= I40E_LINK_SPEED_25GB;
1774         if (link_speeds & ETH_LINK_SPEED_20G)
1775                 link_speed |= I40E_LINK_SPEED_20GB;
1776         if (link_speeds & ETH_LINK_SPEED_10G)
1777                 link_speed |= I40E_LINK_SPEED_10GB;
1778         if (link_speeds & ETH_LINK_SPEED_1G)
1779                 link_speed |= I40E_LINK_SPEED_1GB;
1780         if (link_speeds & ETH_LINK_SPEED_100M)
1781                 link_speed |= I40E_LINK_SPEED_100MB;
1782
1783         return link_speed;
1784 }
1785
1786 static int
1787 i40e_phy_conf_link(struct i40e_hw *hw,
1788                    uint8_t abilities,
1789                    uint8_t force_speed)
1790 {
1791         enum i40e_status_code status;
1792         struct i40e_aq_get_phy_abilities_resp phy_ab;
1793         struct i40e_aq_set_phy_config phy_conf;
1794         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1795                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1796                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1797                         I40E_AQ_PHY_FLAG_LOW_POWER;
1798         const uint8_t advt = I40E_LINK_SPEED_40GB |
1799                         I40E_LINK_SPEED_25GB |
1800                         I40E_LINK_SPEED_10GB |
1801                         I40E_LINK_SPEED_1GB |
1802                         I40E_LINK_SPEED_100MB;
1803         int ret = -ENOTSUP;
1804
1805
1806         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1807                                               NULL);
1808         if (status)
1809                 return ret;
1810
1811         memset(&phy_conf, 0, sizeof(phy_conf));
1812
1813         /* bits 0-2 use the values from get_phy_abilities_resp */
1814         abilities &= ~mask;
1815         abilities |= phy_ab.abilities & mask;
1816
1817         /* update ablities and speed */
1818         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1819                 phy_conf.link_speed = advt;
1820         else
1821                 phy_conf.link_speed = force_speed;
1822
1823         phy_conf.abilities = abilities;
1824
1825         /* use get_phy_abilities_resp value for the rest */
1826         phy_conf.phy_type = phy_ab.phy_type;
1827         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1828         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1829         phy_conf.eee_capability = phy_ab.eee_capability;
1830         phy_conf.eeer = phy_ab.eeer_val;
1831         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1832
1833         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1834                     phy_ab.abilities, phy_ab.link_speed);
1835         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1836                     phy_conf.abilities, phy_conf.link_speed);
1837
1838         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1839         if (status)
1840                 return ret;
1841
1842         return I40E_SUCCESS;
1843 }
1844
1845 static int
1846 i40e_apply_link_speed(struct rte_eth_dev *dev)
1847 {
1848         uint8_t speed;
1849         uint8_t abilities = 0;
1850         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1851         struct rte_eth_conf *conf = &dev->data->dev_conf;
1852
1853         speed = i40e_parse_link_speeds(conf->link_speeds);
1854         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1855         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1856                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1857         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1858
1859         /* Skip changing speed on 40G interfaces, FW does not support */
1860         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1861                 speed =  I40E_LINK_SPEED_UNKNOWN;
1862                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1863         }
1864
1865         return i40e_phy_conf_link(hw, abilities, speed);
1866 }
1867
1868 static int
1869 i40e_dev_start(struct rte_eth_dev *dev)
1870 {
1871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         struct i40e_vsi *main_vsi = pf->main_vsi;
1874         int ret, i;
1875         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1876         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1877         uint32_t intr_vector = 0;
1878
1879         hw->adapter_stopped = 0;
1880
1881         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1882                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1883                              dev->data->port_id);
1884                 return -EINVAL;
1885         }
1886
1887         rte_intr_disable(intr_handle);
1888
1889         if ((rte_intr_cap_multiple(intr_handle) ||
1890              !RTE_ETH_DEV_SRIOV(dev).active) &&
1891             dev->data->dev_conf.intr_conf.rxq != 0) {
1892                 intr_vector = dev->data->nb_rx_queues;
1893                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1894                 if (ret)
1895                         return ret;
1896         }
1897
1898         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1899                 intr_handle->intr_vec =
1900                         rte_zmalloc("intr_vec",
1901                                     dev->data->nb_rx_queues * sizeof(int),
1902                                     0);
1903                 if (!intr_handle->intr_vec) {
1904                         PMD_INIT_LOG(ERR,
1905                                 "Failed to allocate %d rx_queues intr_vec",
1906                                 dev->data->nb_rx_queues);
1907                         return -ENOMEM;
1908                 }
1909         }
1910
1911         /* Initialize VSI */
1912         ret = i40e_dev_rxtx_init(pf);
1913         if (ret != I40E_SUCCESS) {
1914                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1915                 goto err_up;
1916         }
1917
1918         /* Map queues with MSIX interrupt */
1919         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1920                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1921         i40e_vsi_queues_bind_intr(main_vsi);
1922         i40e_vsi_enable_queues_intr(main_vsi);
1923
1924         /* Map VMDQ VSI queues with MSIX interrupt */
1925         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1926                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1927                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1928                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1929         }
1930
1931         /* enable FDIR MSIX interrupt */
1932         if (pf->fdir.fdir_vsi) {
1933                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1934                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1935         }
1936
1937         /* Enable all queues which have been configured */
1938         ret = i40e_dev_switch_queues(pf, TRUE);
1939         if (ret != I40E_SUCCESS) {
1940                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1941                 goto err_up;
1942         }
1943
1944         /* Enable receiving broadcast packets */
1945         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1946         if (ret != I40E_SUCCESS)
1947                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1948
1949         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1950                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1951                                                 true, NULL);
1952                 if (ret != I40E_SUCCESS)
1953                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1954         }
1955
1956         /* Apply link configure */
1957         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1958                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1959                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1960                                 ETH_LINK_SPEED_40G)) {
1961                 PMD_DRV_LOG(ERR, "Invalid link setting");
1962                 goto err_up;
1963         }
1964         ret = i40e_apply_link_speed(dev);
1965         if (I40E_SUCCESS != ret) {
1966                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1967                 goto err_up;
1968         }
1969
1970         if (!rte_intr_allow_others(intr_handle)) {
1971                 rte_intr_callback_unregister(intr_handle,
1972                                              i40e_dev_interrupt_handler,
1973                                              (void *)dev);
1974                 /* configure and enable device interrupt */
1975                 i40e_pf_config_irq0(hw, FALSE);
1976                 i40e_pf_enable_irq0(hw);
1977
1978                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1979                         PMD_INIT_LOG(INFO,
1980                                 "lsc won't enable because of no intr multiplex");
1981         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1982                 ret = i40e_aq_set_phy_int_mask(hw,
1983                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1984                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1985                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1986                 if (ret != I40E_SUCCESS)
1987                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1988
1989                 /* Call get_link_info aq commond to enable LSE */
1990                 i40e_dev_link_update(dev, 0);
1991         }
1992
1993         /* enable uio intr after callback register */
1994         rte_intr_enable(intr_handle);
1995
1996         i40e_filter_restore(pf);
1997
1998         return I40E_SUCCESS;
1999
2000 err_up:
2001         i40e_dev_switch_queues(pf, FALSE);
2002         i40e_dev_clear_queues(dev);
2003
2004         return ret;
2005 }
2006
2007 static void
2008 i40e_dev_stop(struct rte_eth_dev *dev)
2009 {
2010         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2011         struct i40e_vsi *main_vsi = pf->main_vsi;
2012         struct i40e_mirror_rule *p_mirror;
2013         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2014         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2015         int i;
2016
2017         /* Disable all queues */
2018         i40e_dev_switch_queues(pf, FALSE);
2019
2020         /* un-map queues with interrupt registers */
2021         i40e_vsi_disable_queues_intr(main_vsi);
2022         i40e_vsi_queues_unbind_intr(main_vsi);
2023
2024         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2025                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2026                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2027         }
2028
2029         if (pf->fdir.fdir_vsi) {
2030                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2031                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2032         }
2033         /* Clear all queues and release memory */
2034         i40e_dev_clear_queues(dev);
2035
2036         /* Set link down */
2037         i40e_dev_set_link_down(dev);
2038
2039         /* Remove all mirror rules */
2040         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2041                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2042                 rte_free(p_mirror);
2043         }
2044         pf->nb_mirror_rule = 0;
2045
2046         if (!rte_intr_allow_others(intr_handle))
2047                 /* resume to the default handler */
2048                 rte_intr_callback_register(intr_handle,
2049                                            i40e_dev_interrupt_handler,
2050                                            (void *)dev);
2051
2052         /* Clean datapath event and queue/vec mapping */
2053         rte_intr_efd_disable(intr_handle);
2054         if (intr_handle->intr_vec) {
2055                 rte_free(intr_handle->intr_vec);
2056                 intr_handle->intr_vec = NULL;
2057         }
2058 }
2059
2060 static void
2061 i40e_dev_close(struct rte_eth_dev *dev)
2062 {
2063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2064         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2066         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2067         uint32_t reg;
2068         int i;
2069
2070         PMD_INIT_FUNC_TRACE();
2071
2072         i40e_dev_stop(dev);
2073         hw->adapter_stopped = 1;
2074         i40e_dev_free_queues(dev);
2075
2076         /* Disable interrupt */
2077         i40e_pf_disable_irq0(hw);
2078         rte_intr_disable(intr_handle);
2079
2080         /* shutdown and destroy the HMC */
2081         i40e_shutdown_lan_hmc(hw);
2082
2083         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2084                 i40e_vsi_release(pf->vmdq[i].vsi);
2085                 pf->vmdq[i].vsi = NULL;
2086         }
2087         rte_free(pf->vmdq);
2088         pf->vmdq = NULL;
2089
2090         /* release all the existing VSIs and VEBs */
2091         i40e_fdir_teardown(pf);
2092         i40e_vsi_release(pf->main_vsi);
2093
2094         /* shutdown the adminq */
2095         i40e_aq_queue_shutdown(hw, true);
2096         i40e_shutdown_adminq(hw);
2097
2098         i40e_res_pool_destroy(&pf->qp_pool);
2099         i40e_res_pool_destroy(&pf->msix_pool);
2100
2101         /* force a PF reset to clean anything leftover */
2102         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2103         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2104                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2105         I40E_WRITE_FLUSH(hw);
2106 }
2107
2108 static void
2109 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2110 {
2111         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2112         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113         struct i40e_vsi *vsi = pf->main_vsi;
2114         int status;
2115
2116         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2117                                                      true, NULL, true);
2118         if (status != I40E_SUCCESS)
2119                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2120
2121         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2122                                                         TRUE, NULL);
2123         if (status != I40E_SUCCESS)
2124                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2125
2126 }
2127
2128 static void
2129 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2130 {
2131         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2132         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2133         struct i40e_vsi *vsi = pf->main_vsi;
2134         int status;
2135
2136         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2137                                                      false, NULL, true);
2138         if (status != I40E_SUCCESS)
2139                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2140
2141         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2142                                                         false, NULL);
2143         if (status != I40E_SUCCESS)
2144                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2145 }
2146
2147 static void
2148 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2149 {
2150         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2152         struct i40e_vsi *vsi = pf->main_vsi;
2153         int ret;
2154
2155         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2156         if (ret != I40E_SUCCESS)
2157                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2158 }
2159
2160 static void
2161 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2162 {
2163         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2164         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165         struct i40e_vsi *vsi = pf->main_vsi;
2166         int ret;
2167
2168         if (dev->data->promiscuous == 1)
2169                 return; /* must remain in all_multicast mode */
2170
2171         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2172                                 vsi->seid, FALSE, NULL);
2173         if (ret != I40E_SUCCESS)
2174                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2175 }
2176
2177 /*
2178  * Set device link up.
2179  */
2180 static int
2181 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2182 {
2183         /* re-apply link speed setting */
2184         return i40e_apply_link_speed(dev);
2185 }
2186
2187 /*
2188  * Set device link down.
2189  */
2190 static int
2191 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2192 {
2193         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2194         uint8_t abilities = 0;
2195         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2196
2197         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2198         return i40e_phy_conf_link(hw, abilities, speed);
2199 }
2200
2201 int
2202 i40e_dev_link_update(struct rte_eth_dev *dev,
2203                      int wait_to_complete)
2204 {
2205 #define CHECK_INTERVAL 100  /* 100ms */
2206 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2207         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2208         struct i40e_link_status link_status;
2209         struct rte_eth_link link, old;
2210         int status;
2211         unsigned rep_cnt = MAX_REPEAT_TIME;
2212         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2213
2214         memset(&link, 0, sizeof(link));
2215         memset(&old, 0, sizeof(old));
2216         memset(&link_status, 0, sizeof(link_status));
2217         rte_i40e_dev_atomic_read_link_status(dev, &old);
2218
2219         do {
2220                 /* Get link status information from hardware */
2221                 status = i40e_aq_get_link_info(hw, enable_lse,
2222                                                 &link_status, NULL);
2223                 if (status != I40E_SUCCESS) {
2224                         link.link_speed = ETH_SPEED_NUM_100M;
2225                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2226                         PMD_DRV_LOG(ERR, "Failed to get link info");
2227                         goto out;
2228                 }
2229
2230                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2231                 if (!wait_to_complete || link.link_status)
2232                         break;
2233
2234                 rte_delay_ms(CHECK_INTERVAL);
2235         } while (--rep_cnt);
2236
2237         if (!link.link_status)
2238                 goto out;
2239
2240         /* i40e uses full duplex only */
2241         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2242
2243         /* Parse the link status */
2244         switch (link_status.link_speed) {
2245         case I40E_LINK_SPEED_100MB:
2246                 link.link_speed = ETH_SPEED_NUM_100M;
2247                 break;
2248         case I40E_LINK_SPEED_1GB:
2249                 link.link_speed = ETH_SPEED_NUM_1G;
2250                 break;
2251         case I40E_LINK_SPEED_10GB:
2252                 link.link_speed = ETH_SPEED_NUM_10G;
2253                 break;
2254         case I40E_LINK_SPEED_20GB:
2255                 link.link_speed = ETH_SPEED_NUM_20G;
2256                 break;
2257         case I40E_LINK_SPEED_25GB:
2258                 link.link_speed = ETH_SPEED_NUM_25G;
2259                 break;
2260         case I40E_LINK_SPEED_40GB:
2261                 link.link_speed = ETH_SPEED_NUM_40G;
2262                 break;
2263         default:
2264                 link.link_speed = ETH_SPEED_NUM_100M;
2265                 break;
2266         }
2267
2268         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2269                         ETH_LINK_SPEED_FIXED);
2270
2271 out:
2272         rte_i40e_dev_atomic_write_link_status(dev, &link);
2273         if (link.link_status == old.link_status)
2274                 return -1;
2275
2276         return 0;
2277 }
2278
2279 /* Get all the statistics of a VSI */
2280 void
2281 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2282 {
2283         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2284         struct i40e_eth_stats *nes = &vsi->eth_stats;
2285         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2286         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2287
2288         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2289                             vsi->offset_loaded, &oes->rx_bytes,
2290                             &nes->rx_bytes);
2291         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2292                             vsi->offset_loaded, &oes->rx_unicast,
2293                             &nes->rx_unicast);
2294         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2295                             vsi->offset_loaded, &oes->rx_multicast,
2296                             &nes->rx_multicast);
2297         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2298                             vsi->offset_loaded, &oes->rx_broadcast,
2299                             &nes->rx_broadcast);
2300         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2301                             &oes->rx_discards, &nes->rx_discards);
2302         /* GLV_REPC not supported */
2303         /* GLV_RMPC not supported */
2304         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2305                             &oes->rx_unknown_protocol,
2306                             &nes->rx_unknown_protocol);
2307         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2308                             vsi->offset_loaded, &oes->tx_bytes,
2309                             &nes->tx_bytes);
2310         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2311                             vsi->offset_loaded, &oes->tx_unicast,
2312                             &nes->tx_unicast);
2313         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2314                             vsi->offset_loaded, &oes->tx_multicast,
2315                             &nes->tx_multicast);
2316         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2317                             vsi->offset_loaded,  &oes->tx_broadcast,
2318                             &nes->tx_broadcast);
2319         /* GLV_TDPC not supported */
2320         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2321                             &oes->tx_errors, &nes->tx_errors);
2322         vsi->offset_loaded = true;
2323
2324         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2325                     vsi->vsi_id);
2326         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2327         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2328         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2329         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2330         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2331         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2332                     nes->rx_unknown_protocol);
2333         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2334         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2335         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2336         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2337         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2338         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2339         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2340                     vsi->vsi_id);
2341 }
2342
2343 static void
2344 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2345 {
2346         unsigned int i;
2347         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2348         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2349
2350         /* Get statistics of struct i40e_eth_stats */
2351         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2352                             I40E_GLPRT_GORCL(hw->port),
2353                             pf->offset_loaded, &os->eth.rx_bytes,
2354                             &ns->eth.rx_bytes);
2355         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2356                             I40E_GLPRT_UPRCL(hw->port),
2357                             pf->offset_loaded, &os->eth.rx_unicast,
2358                             &ns->eth.rx_unicast);
2359         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2360                             I40E_GLPRT_MPRCL(hw->port),
2361                             pf->offset_loaded, &os->eth.rx_multicast,
2362                             &ns->eth.rx_multicast);
2363         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2364                             I40E_GLPRT_BPRCL(hw->port),
2365                             pf->offset_loaded, &os->eth.rx_broadcast,
2366                             &ns->eth.rx_broadcast);
2367         /* Workaround: CRC size should not be included in byte statistics,
2368          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2369          */
2370         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2371                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2372
2373         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2374                             pf->offset_loaded, &os->eth.rx_discards,
2375                             &ns->eth.rx_discards);
2376         /* GLPRT_REPC not supported */
2377         /* GLPRT_RMPC not supported */
2378         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2379                             pf->offset_loaded,
2380                             &os->eth.rx_unknown_protocol,
2381                             &ns->eth.rx_unknown_protocol);
2382         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2383                             I40E_GLPRT_GOTCL(hw->port),
2384                             pf->offset_loaded, &os->eth.tx_bytes,
2385                             &ns->eth.tx_bytes);
2386         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2387                             I40E_GLPRT_UPTCL(hw->port),
2388                             pf->offset_loaded, &os->eth.tx_unicast,
2389                             &ns->eth.tx_unicast);
2390         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2391                             I40E_GLPRT_MPTCL(hw->port),
2392                             pf->offset_loaded, &os->eth.tx_multicast,
2393                             &ns->eth.tx_multicast);
2394         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2395                             I40E_GLPRT_BPTCL(hw->port),
2396                             pf->offset_loaded, &os->eth.tx_broadcast,
2397                             &ns->eth.tx_broadcast);
2398         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2399                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2400         /* GLPRT_TEPC not supported */
2401
2402         /* additional port specific stats */
2403         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2404                             pf->offset_loaded, &os->tx_dropped_link_down,
2405                             &ns->tx_dropped_link_down);
2406         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2407                             pf->offset_loaded, &os->crc_errors,
2408                             &ns->crc_errors);
2409         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2410                             pf->offset_loaded, &os->illegal_bytes,
2411                             &ns->illegal_bytes);
2412         /* GLPRT_ERRBC not supported */
2413         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2414                             pf->offset_loaded, &os->mac_local_faults,
2415                             &ns->mac_local_faults);
2416         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2417                             pf->offset_loaded, &os->mac_remote_faults,
2418                             &ns->mac_remote_faults);
2419         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2420                             pf->offset_loaded, &os->rx_length_errors,
2421                             &ns->rx_length_errors);
2422         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2423                             pf->offset_loaded, &os->link_xon_rx,
2424                             &ns->link_xon_rx);
2425         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2426                             pf->offset_loaded, &os->link_xoff_rx,
2427                             &ns->link_xoff_rx);
2428         for (i = 0; i < 8; i++) {
2429                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2430                                     pf->offset_loaded,
2431                                     &os->priority_xon_rx[i],
2432                                     &ns->priority_xon_rx[i]);
2433                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2434                                     pf->offset_loaded,
2435                                     &os->priority_xoff_rx[i],
2436                                     &ns->priority_xoff_rx[i]);
2437         }
2438         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2439                             pf->offset_loaded, &os->link_xon_tx,
2440                             &ns->link_xon_tx);
2441         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2442                             pf->offset_loaded, &os->link_xoff_tx,
2443                             &ns->link_xoff_tx);
2444         for (i = 0; i < 8; i++) {
2445                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2446                                     pf->offset_loaded,
2447                                     &os->priority_xon_tx[i],
2448                                     &ns->priority_xon_tx[i]);
2449                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2450                                     pf->offset_loaded,
2451                                     &os->priority_xoff_tx[i],
2452                                     &ns->priority_xoff_tx[i]);
2453                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2454                                     pf->offset_loaded,
2455                                     &os->priority_xon_2_xoff[i],
2456                                     &ns->priority_xon_2_xoff[i]);
2457         }
2458         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2459                             I40E_GLPRT_PRC64L(hw->port),
2460                             pf->offset_loaded, &os->rx_size_64,
2461                             &ns->rx_size_64);
2462         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2463                             I40E_GLPRT_PRC127L(hw->port),
2464                             pf->offset_loaded, &os->rx_size_127,
2465                             &ns->rx_size_127);
2466         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2467                             I40E_GLPRT_PRC255L(hw->port),
2468                             pf->offset_loaded, &os->rx_size_255,
2469                             &ns->rx_size_255);
2470         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2471                             I40E_GLPRT_PRC511L(hw->port),
2472                             pf->offset_loaded, &os->rx_size_511,
2473                             &ns->rx_size_511);
2474         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2475                             I40E_GLPRT_PRC1023L(hw->port),
2476                             pf->offset_loaded, &os->rx_size_1023,
2477                             &ns->rx_size_1023);
2478         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2479                             I40E_GLPRT_PRC1522L(hw->port),
2480                             pf->offset_loaded, &os->rx_size_1522,
2481                             &ns->rx_size_1522);
2482         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2483                             I40E_GLPRT_PRC9522L(hw->port),
2484                             pf->offset_loaded, &os->rx_size_big,
2485                             &ns->rx_size_big);
2486         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2487                             pf->offset_loaded, &os->rx_undersize,
2488                             &ns->rx_undersize);
2489         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2490                             pf->offset_loaded, &os->rx_fragments,
2491                             &ns->rx_fragments);
2492         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2493                             pf->offset_loaded, &os->rx_oversize,
2494                             &ns->rx_oversize);
2495         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2496                             pf->offset_loaded, &os->rx_jabber,
2497                             &ns->rx_jabber);
2498         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2499                             I40E_GLPRT_PTC64L(hw->port),
2500                             pf->offset_loaded, &os->tx_size_64,
2501                             &ns->tx_size_64);
2502         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2503                             I40E_GLPRT_PTC127L(hw->port),
2504                             pf->offset_loaded, &os->tx_size_127,
2505                             &ns->tx_size_127);
2506         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2507                             I40E_GLPRT_PTC255L(hw->port),
2508                             pf->offset_loaded, &os->tx_size_255,
2509                             &ns->tx_size_255);
2510         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2511                             I40E_GLPRT_PTC511L(hw->port),
2512                             pf->offset_loaded, &os->tx_size_511,
2513                             &ns->tx_size_511);
2514         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2515                             I40E_GLPRT_PTC1023L(hw->port),
2516                             pf->offset_loaded, &os->tx_size_1023,
2517                             &ns->tx_size_1023);
2518         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2519                             I40E_GLPRT_PTC1522L(hw->port),
2520                             pf->offset_loaded, &os->tx_size_1522,
2521                             &ns->tx_size_1522);
2522         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2523                             I40E_GLPRT_PTC9522L(hw->port),
2524                             pf->offset_loaded, &os->tx_size_big,
2525                             &ns->tx_size_big);
2526         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2527                            pf->offset_loaded,
2528                            &os->fd_sb_match, &ns->fd_sb_match);
2529         /* GLPRT_MSPDC not supported */
2530         /* GLPRT_XEC not supported */
2531
2532         pf->offset_loaded = true;
2533
2534         if (pf->main_vsi)
2535                 i40e_update_vsi_stats(pf->main_vsi);
2536 }
2537
2538 /* Get all statistics of a port */
2539 static void
2540 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2541 {
2542         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2543         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2544         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2545         unsigned i;
2546
2547         /* call read registers - updates values, now write them to struct */
2548         i40e_read_stats_registers(pf, hw);
2549
2550         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2551                         pf->main_vsi->eth_stats.rx_multicast +
2552                         pf->main_vsi->eth_stats.rx_broadcast -
2553                         pf->main_vsi->eth_stats.rx_discards;
2554         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2555                         pf->main_vsi->eth_stats.tx_multicast +
2556                         pf->main_vsi->eth_stats.tx_broadcast;
2557         stats->ibytes   = ns->eth.rx_bytes;
2558         stats->obytes   = ns->eth.tx_bytes;
2559         stats->oerrors  = ns->eth.tx_errors +
2560                         pf->main_vsi->eth_stats.tx_errors;
2561
2562         /* Rx Errors */
2563         stats->imissed  = ns->eth.rx_discards +
2564                         pf->main_vsi->eth_stats.rx_discards;
2565         stats->ierrors  = ns->crc_errors +
2566                         ns->rx_length_errors + ns->rx_undersize +
2567                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2568
2569         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2570         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2571         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2572         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2573         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2574         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2575         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2576                     ns->eth.rx_unknown_protocol);
2577         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2578         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2579         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2580         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2581         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2582         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2583
2584         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2585                     ns->tx_dropped_link_down);
2586         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2587         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2588                     ns->illegal_bytes);
2589         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2590         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2591                     ns->mac_local_faults);
2592         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2593                     ns->mac_remote_faults);
2594         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2595                     ns->rx_length_errors);
2596         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2597         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2598         for (i = 0; i < 8; i++) {
2599                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2600                                 i, ns->priority_xon_rx[i]);
2601                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2602                                 i, ns->priority_xoff_rx[i]);
2603         }
2604         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2605         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2606         for (i = 0; i < 8; i++) {
2607                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2608                                 i, ns->priority_xon_tx[i]);
2609                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2610                                 i, ns->priority_xoff_tx[i]);
2611                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2612                                 i, ns->priority_xon_2_xoff[i]);
2613         }
2614         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2615         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2616         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2617         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2618         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2619         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2620         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2621         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2622         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2623         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2624         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2625         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2626         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2627         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2628         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2629         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2630         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2631         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2632         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2633                         ns->mac_short_packet_dropped);
2634         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2635                     ns->checksum_error);
2636         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2637         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2638 }
2639
2640 /* Reset the statistics */
2641 static void
2642 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2643 {
2644         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2645         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646
2647         /* Mark PF and VSI stats to update the offset, aka "reset" */
2648         pf->offset_loaded = false;
2649         if (pf->main_vsi)
2650                 pf->main_vsi->offset_loaded = false;
2651
2652         /* read the stats, reading current register values into offset */
2653         i40e_read_stats_registers(pf, hw);
2654 }
2655
2656 static uint32_t
2657 i40e_xstats_calc_num(void)
2658 {
2659         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2660                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2661                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2662 }
2663
2664 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2665                                      struct rte_eth_xstat_name *xstats_names,
2666                                      __rte_unused unsigned limit)
2667 {
2668         unsigned count = 0;
2669         unsigned i, prio;
2670
2671         if (xstats_names == NULL)
2672                 return i40e_xstats_calc_num();
2673
2674         /* Note: limit checked in rte_eth_xstats_names() */
2675
2676         /* Get stats from i40e_eth_stats struct */
2677         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2678                 snprintf(xstats_names[count].name,
2679                          sizeof(xstats_names[count].name),
2680                          "%s", rte_i40e_stats_strings[i].name);
2681                 count++;
2682         }
2683
2684         /* Get individiual stats from i40e_hw_port struct */
2685         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2686                 snprintf(xstats_names[count].name,
2687                         sizeof(xstats_names[count].name),
2688                          "%s", rte_i40e_hw_port_strings[i].name);
2689                 count++;
2690         }
2691
2692         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2693                 for (prio = 0; prio < 8; prio++) {
2694                         snprintf(xstats_names[count].name,
2695                                  sizeof(xstats_names[count].name),
2696                                  "rx_priority%u_%s", prio,
2697                                  rte_i40e_rxq_prio_strings[i].name);
2698                         count++;
2699                 }
2700         }
2701
2702         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2703                 for (prio = 0; prio < 8; prio++) {
2704                         snprintf(xstats_names[count].name,
2705                                  sizeof(xstats_names[count].name),
2706                                  "tx_priority%u_%s", prio,
2707                                  rte_i40e_txq_prio_strings[i].name);
2708                         count++;
2709                 }
2710         }
2711         return count;
2712 }
2713
2714 static int
2715 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2716                     unsigned n)
2717 {
2718         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2719         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2720         unsigned i, count, prio;
2721         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2722
2723         count = i40e_xstats_calc_num();
2724         if (n < count)
2725                 return count;
2726
2727         i40e_read_stats_registers(pf, hw);
2728
2729         if (xstats == NULL)
2730                 return 0;
2731
2732         count = 0;
2733
2734         /* Get stats from i40e_eth_stats struct */
2735         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2736                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2737                         rte_i40e_stats_strings[i].offset);
2738                 xstats[count].id = count;
2739                 count++;
2740         }
2741
2742         /* Get individiual stats from i40e_hw_port struct */
2743         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2744                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2745                         rte_i40e_hw_port_strings[i].offset);
2746                 xstats[count].id = count;
2747                 count++;
2748         }
2749
2750         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2751                 for (prio = 0; prio < 8; prio++) {
2752                         xstats[count].value =
2753                                 *(uint64_t *)(((char *)hw_stats) +
2754                                 rte_i40e_rxq_prio_strings[i].offset +
2755                                 (sizeof(uint64_t) * prio));
2756                         xstats[count].id = count;
2757                         count++;
2758                 }
2759         }
2760
2761         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2762                 for (prio = 0; prio < 8; prio++) {
2763                         xstats[count].value =
2764                                 *(uint64_t *)(((char *)hw_stats) +
2765                                 rte_i40e_txq_prio_strings[i].offset +
2766                                 (sizeof(uint64_t) * prio));
2767                         xstats[count].id = count;
2768                         count++;
2769                 }
2770         }
2771
2772         return count;
2773 }
2774
2775 static int
2776 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2777                                  __rte_unused uint16_t queue_id,
2778                                  __rte_unused uint8_t stat_idx,
2779                                  __rte_unused uint8_t is_rx)
2780 {
2781         PMD_INIT_FUNC_TRACE();
2782
2783         return -ENOSYS;
2784 }
2785
2786 static int
2787 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2788 {
2789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790         u32 full_ver;
2791         u8 ver, patch;
2792         u16 build;
2793         int ret;
2794
2795         full_ver = hw->nvm.oem_ver;
2796         ver = (u8)(full_ver >> 24);
2797         build = (u16)((full_ver >> 8) & 0xffff);
2798         patch = (u8)(full_ver & 0xff);
2799
2800         ret = snprintf(fw_version, fw_size,
2801                  "%d.%d%d 0x%08x %d.%d.%d",
2802                  ((hw->nvm.version >> 12) & 0xf),
2803                  ((hw->nvm.version >> 4) & 0xff),
2804                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2805                  ver, build, patch);
2806
2807         ret += 1; /* add the size of '\0' */
2808         if (fw_size < (u32)ret)
2809                 return ret;
2810         else
2811                 return 0;
2812 }
2813
2814 static void
2815 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2816 {
2817         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2818         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819         struct i40e_vsi *vsi = pf->main_vsi;
2820         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2821
2822         dev_info->pci_dev = pci_dev;
2823         dev_info->max_rx_queues = vsi->nb_qps;
2824         dev_info->max_tx_queues = vsi->nb_qps;
2825         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2826         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2827         dev_info->max_mac_addrs = vsi->max_macaddrs;
2828         dev_info->max_vfs = pci_dev->max_vfs;
2829         dev_info->rx_offload_capa =
2830                 DEV_RX_OFFLOAD_VLAN_STRIP |
2831                 DEV_RX_OFFLOAD_QINQ_STRIP |
2832                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2833                 DEV_RX_OFFLOAD_UDP_CKSUM |
2834                 DEV_RX_OFFLOAD_TCP_CKSUM;
2835         dev_info->tx_offload_capa =
2836                 DEV_TX_OFFLOAD_VLAN_INSERT |
2837                 DEV_TX_OFFLOAD_QINQ_INSERT |
2838                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2839                 DEV_TX_OFFLOAD_UDP_CKSUM |
2840                 DEV_TX_OFFLOAD_TCP_CKSUM |
2841                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2842                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2843                 DEV_TX_OFFLOAD_TCP_TSO |
2844                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2845                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2846                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2847                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2848         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2849                                                 sizeof(uint32_t);
2850         dev_info->reta_size = pf->hash_lut_size;
2851         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2852
2853         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2854                 .rx_thresh = {
2855                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2856                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2857                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2858                 },
2859                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2860                 .rx_drop_en = 0,
2861         };
2862
2863         dev_info->default_txconf = (struct rte_eth_txconf) {
2864                 .tx_thresh = {
2865                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2866                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2867                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2868                 },
2869                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2870                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2871                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2872                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2873         };
2874
2875         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2876                 .nb_max = I40E_MAX_RING_DESC,
2877                 .nb_min = I40E_MIN_RING_DESC,
2878                 .nb_align = I40E_ALIGN_RING_DESC,
2879         };
2880
2881         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2882                 .nb_max = I40E_MAX_RING_DESC,
2883                 .nb_min = I40E_MIN_RING_DESC,
2884                 .nb_align = I40E_ALIGN_RING_DESC,
2885                 .nb_seg_max = I40E_TX_MAX_SEG,
2886                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2887         };
2888
2889         if (pf->flags & I40E_FLAG_VMDQ) {
2890                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2891                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2892                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2893                                                 pf->max_nb_vmdq_vsi;
2894                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2895                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2896                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2897         }
2898
2899         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2900                 /* For XL710 */
2901                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2902         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2903                 /* For XXV710 */
2904                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2905         else
2906                 /* For X710 */
2907                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2908 }
2909
2910 static int
2911 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2912 {
2913         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2914         struct i40e_vsi *vsi = pf->main_vsi;
2915         PMD_INIT_FUNC_TRACE();
2916
2917         if (on)
2918                 return i40e_vsi_add_vlan(vsi, vlan_id);
2919         else
2920                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2921 }
2922
2923 static int
2924 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2925                    enum rte_vlan_type vlan_type,
2926                    uint16_t tpid)
2927 {
2928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929         uint64_t reg_r = 0, reg_w = 0;
2930         uint16_t reg_id = 0;
2931         int ret = 0;
2932         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2933
2934         switch (vlan_type) {
2935         case ETH_VLAN_TYPE_OUTER:
2936                 if (qinq)
2937                         reg_id = 2;
2938                 else
2939                         reg_id = 3;
2940                 break;
2941         case ETH_VLAN_TYPE_INNER:
2942                 if (qinq)
2943                         reg_id = 3;
2944                 else {
2945                         ret = -EINVAL;
2946                         PMD_DRV_LOG(ERR,
2947                                 "Unsupported vlan type in single vlan.");
2948                         return ret;
2949                 }
2950                 break;
2951         default:
2952                 ret = -EINVAL;
2953                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2954                 return ret;
2955         }
2956         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2957                                           &reg_r, NULL);
2958         if (ret != I40E_SUCCESS) {
2959                 PMD_DRV_LOG(ERR,
2960                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2961                            reg_id);
2962                 ret = -EIO;
2963                 return ret;
2964         }
2965         PMD_DRV_LOG(DEBUG,
2966                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2967                 reg_id, reg_r);
2968
2969         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2970         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2971         if (reg_r == reg_w) {
2972                 ret = 0;
2973                 PMD_DRV_LOG(DEBUG, "No need to write");
2974                 return ret;
2975         }
2976
2977         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2978                                            reg_w, NULL);
2979         if (ret != I40E_SUCCESS) {
2980                 ret = -EIO;
2981                 PMD_DRV_LOG(ERR,
2982                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2983                         reg_id);
2984                 return ret;
2985         }
2986         PMD_DRV_LOG(DEBUG,
2987                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2988                 reg_w, reg_id);
2989
2990         return ret;
2991 }
2992
2993 static void
2994 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2995 {
2996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2997         struct i40e_vsi *vsi = pf->main_vsi;
2998
2999         if (mask & ETH_VLAN_FILTER_MASK) {
3000                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3001                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3002                 else
3003                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3004         }
3005
3006         if (mask & ETH_VLAN_STRIP_MASK) {
3007                 /* Enable or disable VLAN stripping */
3008                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3009                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3010                 else
3011                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3012         }
3013
3014         if (mask & ETH_VLAN_EXTEND_MASK) {
3015                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3016                         i40e_vsi_config_double_vlan(vsi, TRUE);
3017                         /* Set global registers with default ether type value */
3018                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3019                                            ETHER_TYPE_VLAN);
3020                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3021                                            ETHER_TYPE_VLAN);
3022                 }
3023                 else
3024                         i40e_vsi_config_double_vlan(vsi, FALSE);
3025         }
3026 }
3027
3028 static void
3029 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3030                           __rte_unused uint16_t queue,
3031                           __rte_unused int on)
3032 {
3033         PMD_INIT_FUNC_TRACE();
3034 }
3035
3036 static int
3037 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3038 {
3039         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3040         struct i40e_vsi *vsi = pf->main_vsi;
3041         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3042         struct i40e_vsi_vlan_pvid_info info;
3043
3044         memset(&info, 0, sizeof(info));
3045         info.on = on;
3046         if (info.on)
3047                 info.config.pvid = pvid;
3048         else {
3049                 info.config.reject.tagged =
3050                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3051                 info.config.reject.untagged =
3052                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3053         }
3054
3055         return i40e_vsi_vlan_pvid_set(vsi, &info);
3056 }
3057
3058 static int
3059 i40e_dev_led_on(struct rte_eth_dev *dev)
3060 {
3061         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3062         uint32_t mode = i40e_led_get(hw);
3063
3064         if (mode == 0)
3065                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3066
3067         return 0;
3068 }
3069
3070 static int
3071 i40e_dev_led_off(struct rte_eth_dev *dev)
3072 {
3073         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074         uint32_t mode = i40e_led_get(hw);
3075
3076         if (mode != 0)
3077                 i40e_led_set(hw, 0, false);
3078
3079         return 0;
3080 }
3081
3082 static int
3083 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3084 {
3085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3087
3088         fc_conf->pause_time = pf->fc_conf.pause_time;
3089         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3090         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3091
3092          /* Return current mode according to actual setting*/
3093         switch (hw->fc.current_mode) {
3094         case I40E_FC_FULL:
3095                 fc_conf->mode = RTE_FC_FULL;
3096                 break;
3097         case I40E_FC_TX_PAUSE:
3098                 fc_conf->mode = RTE_FC_TX_PAUSE;
3099                 break;
3100         case I40E_FC_RX_PAUSE:
3101                 fc_conf->mode = RTE_FC_RX_PAUSE;
3102                 break;
3103         case I40E_FC_NONE:
3104         default:
3105                 fc_conf->mode = RTE_FC_NONE;
3106         };
3107
3108         return 0;
3109 }
3110
3111 static int
3112 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3113 {
3114         uint32_t mflcn_reg, fctrl_reg, reg;
3115         uint32_t max_high_water;
3116         uint8_t i, aq_failure;
3117         int err;
3118         struct i40e_hw *hw;
3119         struct i40e_pf *pf;
3120         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3121                 [RTE_FC_NONE] = I40E_FC_NONE,
3122                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3123                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3124                 [RTE_FC_FULL] = I40E_FC_FULL
3125         };
3126
3127         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3128
3129         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3130         if ((fc_conf->high_water > max_high_water) ||
3131                         (fc_conf->high_water < fc_conf->low_water)) {
3132                 PMD_INIT_LOG(ERR,
3133                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3134                         max_high_water);
3135                 return -EINVAL;
3136         }
3137
3138         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3139         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3140         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3141
3142         pf->fc_conf.pause_time = fc_conf->pause_time;
3143         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3144         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3145
3146         PMD_INIT_FUNC_TRACE();
3147
3148         /* All the link flow control related enable/disable register
3149          * configuration is handle by the F/W
3150          */
3151         err = i40e_set_fc(hw, &aq_failure, true);
3152         if (err < 0)
3153                 return -ENOSYS;
3154
3155         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3156                 /* Configure flow control refresh threshold,
3157                  * the value for stat_tx_pause_refresh_timer[8]
3158                  * is used for global pause operation.
3159                  */
3160
3161                 I40E_WRITE_REG(hw,
3162                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3163                                pf->fc_conf.pause_time);
3164
3165                 /* configure the timer value included in transmitted pause
3166                  * frame,
3167                  * the value for stat_tx_pause_quanta[8] is used for global
3168                  * pause operation
3169                  */
3170                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3171                                pf->fc_conf.pause_time);
3172
3173                 fctrl_reg = I40E_READ_REG(hw,
3174                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3175
3176                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3177                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3178                 else
3179                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3180
3181                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3182                                fctrl_reg);
3183         } else {
3184                 /* Configure pause time (2 TCs per register) */
3185                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3186                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3187                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3188
3189                 /* Configure flow control refresh threshold value */
3190                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3191                                pf->fc_conf.pause_time / 2);
3192
3193                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3194
3195                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3196                  *depending on configuration
3197                  */
3198                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3199                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3200                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3201                 } else {
3202                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3203                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3204                 }
3205
3206                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3207         }
3208
3209         /* config the water marker both based on the packets and bytes */
3210         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3211                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3212                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3213         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3214                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3215                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3216         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3217                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3218                        << I40E_KILOSHIFT);
3219         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3220                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3221                        << I40E_KILOSHIFT);
3222
3223         I40E_WRITE_FLUSH(hw);
3224
3225         return 0;
3226 }
3227
3228 static int
3229 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3230                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3231 {
3232         PMD_INIT_FUNC_TRACE();
3233
3234         return -ENOSYS;
3235 }
3236
3237 /* Add a MAC address, and update filters */
3238 static void
3239 i40e_macaddr_add(struct rte_eth_dev *dev,
3240                  struct ether_addr *mac_addr,
3241                  __rte_unused uint32_t index,
3242                  uint32_t pool)
3243 {
3244         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3245         struct i40e_mac_filter_info mac_filter;
3246         struct i40e_vsi *vsi;
3247         int ret;
3248
3249         /* If VMDQ not enabled or configured, return */
3250         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3251                           !pf->nb_cfg_vmdq_vsi)) {
3252                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3253                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3254                         pool);
3255                 return;
3256         }
3257
3258         if (pool > pf->nb_cfg_vmdq_vsi) {
3259                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3260                                 pool, pf->nb_cfg_vmdq_vsi);
3261                 return;
3262         }
3263
3264         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3265         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3266                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3267         else
3268                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3269
3270         if (pool == 0)
3271                 vsi = pf->main_vsi;
3272         else
3273                 vsi = pf->vmdq[pool - 1].vsi;
3274
3275         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3276         if (ret != I40E_SUCCESS) {
3277                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3278                 return;
3279         }
3280 }
3281
3282 /* Remove a MAC address, and update filters */
3283 static void
3284 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3285 {
3286         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3287         struct i40e_vsi *vsi;
3288         struct rte_eth_dev_data *data = dev->data;
3289         struct ether_addr *macaddr;
3290         int ret;
3291         uint32_t i;
3292         uint64_t pool_sel;
3293
3294         macaddr = &(data->mac_addrs[index]);
3295
3296         pool_sel = dev->data->mac_pool_sel[index];
3297
3298         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3299                 if (pool_sel & (1ULL << i)) {
3300                         if (i == 0)
3301                                 vsi = pf->main_vsi;
3302                         else {
3303                                 /* No VMDQ pool enabled or configured */
3304                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3305                                         (i > pf->nb_cfg_vmdq_vsi)) {
3306                                         PMD_DRV_LOG(ERR,
3307                                                 "No VMDQ pool enabled/configured");
3308                                         return;
3309                                 }
3310                                 vsi = pf->vmdq[i - 1].vsi;
3311                         }
3312                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3313
3314                         if (ret) {
3315                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3316                                 return;
3317                         }
3318                 }
3319         }
3320 }
3321
3322 /* Set perfect match or hash match of MAC and VLAN for a VF */
3323 static int
3324 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3325                  struct rte_eth_mac_filter *filter,
3326                  bool add)
3327 {
3328         struct i40e_hw *hw;
3329         struct i40e_mac_filter_info mac_filter;
3330         struct ether_addr old_mac;
3331         struct ether_addr *new_mac;
3332         struct i40e_pf_vf *vf = NULL;
3333         uint16_t vf_id;
3334         int ret;
3335
3336         if (pf == NULL) {
3337                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3338                 return -EINVAL;
3339         }
3340         hw = I40E_PF_TO_HW(pf);
3341
3342         if (filter == NULL) {
3343                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3344                 return -EINVAL;
3345         }
3346
3347         new_mac = &filter->mac_addr;
3348
3349         if (is_zero_ether_addr(new_mac)) {
3350                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3351                 return -EINVAL;
3352         }
3353
3354         vf_id = filter->dst_id;
3355
3356         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3357                 PMD_DRV_LOG(ERR, "Invalid argument.");
3358                 return -EINVAL;
3359         }
3360         vf = &pf->vfs[vf_id];
3361
3362         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3363                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3364                 return -EINVAL;
3365         }
3366
3367         if (add) {
3368                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3369                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3370                                 ETHER_ADDR_LEN);
3371                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3372                                  ETHER_ADDR_LEN);
3373
3374                 mac_filter.filter_type = filter->filter_type;
3375                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3376                 if (ret != I40E_SUCCESS) {
3377                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3378                         return -1;
3379                 }
3380                 ether_addr_copy(new_mac, &pf->dev_addr);
3381         } else {
3382                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3383                                 ETHER_ADDR_LEN);
3384                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3385                 if (ret != I40E_SUCCESS) {
3386                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3387                         return -1;
3388                 }
3389
3390                 /* Clear device address as it has been removed */
3391                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3392                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3393         }
3394
3395         return 0;
3396 }
3397
3398 /* MAC filter handle */
3399 static int
3400 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3401                 void *arg)
3402 {
3403         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3404         struct rte_eth_mac_filter *filter;
3405         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3406         int ret = I40E_NOT_SUPPORTED;
3407
3408         filter = (struct rte_eth_mac_filter *)(arg);
3409
3410         switch (filter_op) {
3411         case RTE_ETH_FILTER_NOP:
3412                 ret = I40E_SUCCESS;
3413                 break;
3414         case RTE_ETH_FILTER_ADD:
3415                 i40e_pf_disable_irq0(hw);
3416                 if (filter->is_vf)
3417                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3418                 i40e_pf_enable_irq0(hw);
3419                 break;
3420         case RTE_ETH_FILTER_DELETE:
3421                 i40e_pf_disable_irq0(hw);
3422                 if (filter->is_vf)
3423                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3424                 i40e_pf_enable_irq0(hw);
3425                 break;
3426         default:
3427                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3428                 ret = I40E_ERR_PARAM;
3429                 break;
3430         }
3431
3432         return ret;
3433 }
3434
3435 static int
3436 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3437 {
3438         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3439         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3440         int ret;
3441
3442         if (!lut)
3443                 return -EINVAL;
3444
3445         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3446                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3447                                           lut, lut_size);
3448                 if (ret) {
3449                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3450                         return ret;
3451                 }
3452         } else {
3453                 uint32_t *lut_dw = (uint32_t *)lut;
3454                 uint16_t i, lut_size_dw = lut_size / 4;
3455
3456                 for (i = 0; i < lut_size_dw; i++)
3457                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3458         }
3459
3460         return 0;
3461 }
3462
3463 static int
3464 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3465 {
3466         struct i40e_pf *pf;
3467         struct i40e_hw *hw;
3468         int ret;
3469
3470         if (!vsi || !lut)
3471                 return -EINVAL;
3472
3473         pf = I40E_VSI_TO_PF(vsi);
3474         hw = I40E_VSI_TO_HW(vsi);
3475
3476         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3477                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3478                                           lut, lut_size);
3479                 if (ret) {
3480                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3481                         return ret;
3482                 }
3483         } else {
3484                 uint32_t *lut_dw = (uint32_t *)lut;
3485                 uint16_t i, lut_size_dw = lut_size / 4;
3486
3487                 for (i = 0; i < lut_size_dw; i++)
3488                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3489                 I40E_WRITE_FLUSH(hw);
3490         }
3491
3492         return 0;
3493 }
3494
3495 static int
3496 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3497                          struct rte_eth_rss_reta_entry64 *reta_conf,
3498                          uint16_t reta_size)
3499 {
3500         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3501         uint16_t i, lut_size = pf->hash_lut_size;
3502         uint16_t idx, shift;
3503         uint8_t *lut;
3504         int ret;
3505
3506         if (reta_size != lut_size ||
3507                 reta_size > ETH_RSS_RETA_SIZE_512) {
3508                 PMD_DRV_LOG(ERR,
3509                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3510                         reta_size, lut_size);
3511                 return -EINVAL;
3512         }
3513
3514         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3515         if (!lut) {
3516                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3517                 return -ENOMEM;
3518         }
3519         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3520         if (ret)
3521                 goto out;
3522         for (i = 0; i < reta_size; i++) {
3523                 idx = i / RTE_RETA_GROUP_SIZE;
3524                 shift = i % RTE_RETA_GROUP_SIZE;
3525                 if (reta_conf[idx].mask & (1ULL << shift))
3526                         lut[i] = reta_conf[idx].reta[shift];
3527         }
3528         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3529
3530 out:
3531         rte_free(lut);
3532
3533         return ret;
3534 }
3535
3536 static int
3537 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3538                         struct rte_eth_rss_reta_entry64 *reta_conf,
3539                         uint16_t reta_size)
3540 {
3541         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3542         uint16_t i, lut_size = pf->hash_lut_size;
3543         uint16_t idx, shift;
3544         uint8_t *lut;
3545         int ret;
3546
3547         if (reta_size != lut_size ||
3548                 reta_size > ETH_RSS_RETA_SIZE_512) {
3549                 PMD_DRV_LOG(ERR,
3550                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3551                         reta_size, lut_size);
3552                 return -EINVAL;
3553         }
3554
3555         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3556         if (!lut) {
3557                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3558                 return -ENOMEM;
3559         }
3560
3561         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3562         if (ret)
3563                 goto out;
3564         for (i = 0; i < reta_size; i++) {
3565                 idx = i / RTE_RETA_GROUP_SIZE;
3566                 shift = i % RTE_RETA_GROUP_SIZE;
3567                 if (reta_conf[idx].mask & (1ULL << shift))
3568                         reta_conf[idx].reta[shift] = lut[i];
3569         }
3570
3571 out:
3572         rte_free(lut);
3573
3574         return ret;
3575 }
3576
3577 /**
3578  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3579  * @hw:   pointer to the HW structure
3580  * @mem:  pointer to mem struct to fill out
3581  * @size: size of memory requested
3582  * @alignment: what to align the allocation to
3583  **/
3584 enum i40e_status_code
3585 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3586                         struct i40e_dma_mem *mem,
3587                         u64 size,
3588                         u32 alignment)
3589 {
3590         const struct rte_memzone *mz = NULL;
3591         char z_name[RTE_MEMZONE_NAMESIZE];
3592
3593         if (!mem)
3594                 return I40E_ERR_PARAM;
3595
3596         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3597         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3598                                          alignment, RTE_PGSIZE_2M);
3599         if (!mz)
3600                 return I40E_ERR_NO_MEMORY;
3601
3602         mem->size = size;
3603         mem->va = mz->addr;
3604         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3605         mem->zone = (const void *)mz;
3606         PMD_DRV_LOG(DEBUG,
3607                 "memzone %s allocated with physical address: %"PRIu64,
3608                 mz->name, mem->pa);
3609
3610         return I40E_SUCCESS;
3611 }
3612
3613 /**
3614  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3615  * @hw:   pointer to the HW structure
3616  * @mem:  ptr to mem struct to free
3617  **/
3618 enum i40e_status_code
3619 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3620                     struct i40e_dma_mem *mem)
3621 {
3622         if (!mem)
3623                 return I40E_ERR_PARAM;
3624
3625         PMD_DRV_LOG(DEBUG,
3626                 "memzone %s to be freed with physical address: %"PRIu64,
3627                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3628         rte_memzone_free((const struct rte_memzone *)mem->zone);
3629         mem->zone = NULL;
3630         mem->va = NULL;
3631         mem->pa = (u64)0;
3632
3633         return I40E_SUCCESS;
3634 }
3635
3636 /**
3637  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3638  * @hw:   pointer to the HW structure
3639  * @mem:  pointer to mem struct to fill out
3640  * @size: size of memory requested
3641  **/
3642 enum i40e_status_code
3643 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3644                          struct i40e_virt_mem *mem,
3645                          u32 size)
3646 {
3647         if (!mem)
3648                 return I40E_ERR_PARAM;
3649
3650         mem->size = size;
3651         mem->va = rte_zmalloc("i40e", size, 0);
3652
3653         if (mem->va)
3654                 return I40E_SUCCESS;
3655         else
3656                 return I40E_ERR_NO_MEMORY;
3657 }
3658
3659 /**
3660  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3661  * @hw:   pointer to the HW structure
3662  * @mem:  pointer to mem struct to free
3663  **/
3664 enum i40e_status_code
3665 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3666                      struct i40e_virt_mem *mem)
3667 {
3668         if (!mem)
3669                 return I40E_ERR_PARAM;
3670
3671         rte_free(mem->va);
3672         mem->va = NULL;
3673
3674         return I40E_SUCCESS;
3675 }
3676
3677 void
3678 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3679 {
3680         rte_spinlock_init(&sp->spinlock);
3681 }
3682
3683 void
3684 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3685 {
3686         rte_spinlock_lock(&sp->spinlock);
3687 }
3688
3689 void
3690 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3691 {
3692         rte_spinlock_unlock(&sp->spinlock);
3693 }
3694
3695 void
3696 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3697 {
3698         return;
3699 }
3700
3701 /**
3702  * Get the hardware capabilities, which will be parsed
3703  * and saved into struct i40e_hw.
3704  */
3705 static int
3706 i40e_get_cap(struct i40e_hw *hw)
3707 {
3708         struct i40e_aqc_list_capabilities_element_resp *buf;
3709         uint16_t len, size = 0;
3710         int ret;
3711
3712         /* Calculate a huge enough buff for saving response data temporarily */
3713         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3714                                                 I40E_MAX_CAP_ELE_NUM;
3715         buf = rte_zmalloc("i40e", len, 0);
3716         if (!buf) {
3717                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3718                 return I40E_ERR_NO_MEMORY;
3719         }
3720
3721         /* Get, parse the capabilities and save it to hw */
3722         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3723                         i40e_aqc_opc_list_func_capabilities, NULL);
3724         if (ret != I40E_SUCCESS)
3725                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3726
3727         /* Free the temporary buffer after being used */
3728         rte_free(buf);
3729
3730         return ret;
3731 }
3732
3733 static int
3734 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3735 {
3736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3737         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3738         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3739         uint16_t qp_count = 0, vsi_count = 0;
3740
3741         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3742                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3743                 return -EINVAL;
3744         }
3745         /* Add the parameter init for LFC */
3746         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3747         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3748         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3749
3750         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3751         pf->max_num_vsi = hw->func_caps.num_vsis;
3752         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3753         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3754         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3755
3756         /* FDir queue/VSI allocation */
3757         pf->fdir_qp_offset = 0;
3758         if (hw->func_caps.fd) {
3759                 pf->flags |= I40E_FLAG_FDIR;
3760                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3761         } else {
3762                 pf->fdir_nb_qps = 0;
3763         }
3764         qp_count += pf->fdir_nb_qps;
3765         vsi_count += 1;
3766
3767         /* LAN queue/VSI allocation */
3768         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3769         if (!hw->func_caps.rss) {
3770                 pf->lan_nb_qps = 1;
3771         } else {
3772                 pf->flags |= I40E_FLAG_RSS;
3773                 if (hw->mac.type == I40E_MAC_X722)
3774                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3775                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3776         }
3777         qp_count += pf->lan_nb_qps;
3778         vsi_count += 1;
3779
3780         /* VF queue/VSI allocation */
3781         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3782         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3783                 pf->flags |= I40E_FLAG_SRIOV;
3784                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3785                 pf->vf_num = pci_dev->max_vfs;
3786                 PMD_DRV_LOG(DEBUG,
3787                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3788                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3789         } else {
3790                 pf->vf_nb_qps = 0;
3791                 pf->vf_num = 0;
3792         }
3793         qp_count += pf->vf_nb_qps * pf->vf_num;
3794         vsi_count += pf->vf_num;
3795
3796         /* VMDq queue/VSI allocation */
3797         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3798         pf->vmdq_nb_qps = 0;
3799         pf->max_nb_vmdq_vsi = 0;
3800         if (hw->func_caps.vmdq) {
3801                 if (qp_count < hw->func_caps.num_tx_qp &&
3802                         vsi_count < hw->func_caps.num_vsis) {
3803                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3804                                 qp_count) / pf->vmdq_nb_qp_max;
3805
3806                         /* Limit the maximum number of VMDq vsi to the maximum
3807                          * ethdev can support
3808                          */
3809                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3810                                 hw->func_caps.num_vsis - vsi_count);
3811                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3812                                 ETH_64_POOLS);
3813                         if (pf->max_nb_vmdq_vsi) {
3814                                 pf->flags |= I40E_FLAG_VMDQ;
3815                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3816                                 PMD_DRV_LOG(DEBUG,
3817                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3818                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3819                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3820                         } else {
3821                                 PMD_DRV_LOG(INFO,
3822                                         "No enough queues left for VMDq");
3823                         }
3824                 } else {
3825                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3826                 }
3827         }
3828         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3829         vsi_count += pf->max_nb_vmdq_vsi;
3830
3831         if (hw->func_caps.dcb)
3832                 pf->flags |= I40E_FLAG_DCB;
3833
3834         if (qp_count > hw->func_caps.num_tx_qp) {
3835                 PMD_DRV_LOG(ERR,
3836                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3837                         qp_count, hw->func_caps.num_tx_qp);
3838                 return -EINVAL;
3839         }
3840         if (vsi_count > hw->func_caps.num_vsis) {
3841                 PMD_DRV_LOG(ERR,
3842                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3843                         vsi_count, hw->func_caps.num_vsis);
3844                 return -EINVAL;
3845         }
3846
3847         return 0;
3848 }
3849
3850 static int
3851 i40e_pf_get_switch_config(struct i40e_pf *pf)
3852 {
3853         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3854         struct i40e_aqc_get_switch_config_resp *switch_config;
3855         struct i40e_aqc_switch_config_element_resp *element;
3856         uint16_t start_seid = 0, num_reported;
3857         int ret;
3858
3859         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3860                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3861         if (!switch_config) {
3862                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3863                 return -ENOMEM;
3864         }
3865
3866         /* Get the switch configurations */
3867         ret = i40e_aq_get_switch_config(hw, switch_config,
3868                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3869         if (ret != I40E_SUCCESS) {
3870                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3871                 goto fail;
3872         }
3873         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3874         if (num_reported != 1) { /* The number should be 1 */
3875                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3876                 goto fail;
3877         }
3878
3879         /* Parse the switch configuration elements */
3880         element = &(switch_config->element[0]);
3881         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3882                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3883                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3884         } else
3885                 PMD_DRV_LOG(INFO, "Unknown element type");
3886
3887 fail:
3888         rte_free(switch_config);
3889
3890         return ret;
3891 }
3892
3893 static int
3894 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3895                         uint32_t num)
3896 {
3897         struct pool_entry *entry;
3898
3899         if (pool == NULL || num == 0)
3900                 return -EINVAL;
3901
3902         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3903         if (entry == NULL) {
3904                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3905                 return -ENOMEM;
3906         }
3907
3908         /* queue heap initialize */
3909         pool->num_free = num;
3910         pool->num_alloc = 0;
3911         pool->base = base;
3912         LIST_INIT(&pool->alloc_list);
3913         LIST_INIT(&pool->free_list);
3914
3915         /* Initialize element  */
3916         entry->base = 0;
3917         entry->len = num;
3918
3919         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3920         return 0;
3921 }
3922
3923 static void
3924 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3925 {
3926         struct pool_entry *entry, *next_entry;
3927
3928         if (pool == NULL)
3929                 return;
3930
3931         for (entry = LIST_FIRST(&pool->alloc_list);
3932                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3933                         entry = next_entry) {
3934                 LIST_REMOVE(entry, next);
3935                 rte_free(entry);
3936         }
3937
3938         for (entry = LIST_FIRST(&pool->free_list);
3939                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3940                         entry = next_entry) {
3941                 LIST_REMOVE(entry, next);
3942                 rte_free(entry);
3943         }
3944
3945         pool->num_free = 0;
3946         pool->num_alloc = 0;
3947         pool->base = 0;
3948         LIST_INIT(&pool->alloc_list);
3949         LIST_INIT(&pool->free_list);
3950 }
3951
3952 static int
3953 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3954                        uint32_t base)
3955 {
3956         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3957         uint32_t pool_offset;
3958         int insert;
3959
3960         if (pool == NULL) {
3961                 PMD_DRV_LOG(ERR, "Invalid parameter");
3962                 return -EINVAL;
3963         }
3964
3965         pool_offset = base - pool->base;
3966         /* Lookup in alloc list */
3967         LIST_FOREACH(entry, &pool->alloc_list, next) {
3968                 if (entry->base == pool_offset) {
3969                         valid_entry = entry;
3970                         LIST_REMOVE(entry, next);
3971                         break;
3972                 }
3973         }
3974
3975         /* Not find, return */
3976         if (valid_entry == NULL) {
3977                 PMD_DRV_LOG(ERR, "Failed to find entry");
3978                 return -EINVAL;
3979         }
3980
3981         /**
3982          * Found it, move it to free list  and try to merge.
3983          * In order to make merge easier, always sort it by qbase.
3984          * Find adjacent prev and last entries.
3985          */
3986         prev = next = NULL;
3987         LIST_FOREACH(entry, &pool->free_list, next) {
3988                 if (entry->base > valid_entry->base) {
3989                         next = entry;
3990                         break;
3991                 }
3992                 prev = entry;
3993         }
3994
3995         insert = 0;
3996         /* Try to merge with next one*/
3997         if (next != NULL) {
3998                 /* Merge with next one */
3999                 if (valid_entry->base + valid_entry->len == next->base) {
4000                         next->base = valid_entry->base;
4001                         next->len += valid_entry->len;
4002                         rte_free(valid_entry);
4003                         valid_entry = next;
4004                         insert = 1;
4005                 }
4006         }
4007
4008         if (prev != NULL) {
4009                 /* Merge with previous one */
4010                 if (prev->base + prev->len == valid_entry->base) {
4011                         prev->len += valid_entry->len;
4012                         /* If it merge with next one, remove next node */
4013                         if (insert == 1) {
4014                                 LIST_REMOVE(valid_entry, next);
4015                                 rte_free(valid_entry);
4016                         } else {
4017                                 rte_free(valid_entry);
4018                                 insert = 1;
4019                         }
4020                 }
4021         }
4022
4023         /* Not find any entry to merge, insert */
4024         if (insert == 0) {
4025                 if (prev != NULL)
4026                         LIST_INSERT_AFTER(prev, valid_entry, next);
4027                 else if (next != NULL)
4028                         LIST_INSERT_BEFORE(next, valid_entry, next);
4029                 else /* It's empty list, insert to head */
4030                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4031         }
4032
4033         pool->num_free += valid_entry->len;
4034         pool->num_alloc -= valid_entry->len;
4035
4036         return 0;
4037 }
4038
4039 static int
4040 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4041                        uint16_t num)
4042 {
4043         struct pool_entry *entry, *valid_entry;
4044
4045         if (pool == NULL || num == 0) {
4046                 PMD_DRV_LOG(ERR, "Invalid parameter");
4047                 return -EINVAL;
4048         }
4049
4050         if (pool->num_free < num) {
4051                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4052                             num, pool->num_free);
4053                 return -ENOMEM;
4054         }
4055
4056         valid_entry = NULL;
4057         /* Lookup  in free list and find most fit one */
4058         LIST_FOREACH(entry, &pool->free_list, next) {
4059                 if (entry->len >= num) {
4060                         /* Find best one */
4061                         if (entry->len == num) {
4062                                 valid_entry = entry;
4063                                 break;
4064                         }
4065                         if (valid_entry == NULL || valid_entry->len > entry->len)
4066                                 valid_entry = entry;
4067                 }
4068         }
4069
4070         /* Not find one to satisfy the request, return */
4071         if (valid_entry == NULL) {
4072                 PMD_DRV_LOG(ERR, "No valid entry found");
4073                 return -ENOMEM;
4074         }
4075         /**
4076          * The entry have equal queue number as requested,
4077          * remove it from alloc_list.
4078          */
4079         if (valid_entry->len == num) {
4080                 LIST_REMOVE(valid_entry, next);
4081         } else {
4082                 /**
4083                  * The entry have more numbers than requested,
4084                  * create a new entry for alloc_list and minus its
4085                  * queue base and number in free_list.
4086                  */
4087                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4088                 if (entry == NULL) {
4089                         PMD_DRV_LOG(ERR,
4090                                 "Failed to allocate memory for resource pool");
4091                         return -ENOMEM;
4092                 }
4093                 entry->base = valid_entry->base;
4094                 entry->len = num;
4095                 valid_entry->base += num;
4096                 valid_entry->len -= num;
4097                 valid_entry = entry;
4098         }
4099
4100         /* Insert it into alloc list, not sorted */
4101         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4102
4103         pool->num_free -= valid_entry->len;
4104         pool->num_alloc += valid_entry->len;
4105
4106         return valid_entry->base + pool->base;
4107 }
4108
4109 /**
4110  * bitmap_is_subset - Check whether src2 is subset of src1
4111  **/
4112 static inline int
4113 bitmap_is_subset(uint8_t src1, uint8_t src2)
4114 {
4115         return !((src1 ^ src2) & src2);
4116 }
4117
4118 static enum i40e_status_code
4119 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4120 {
4121         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4122
4123         /* If DCB is not supported, only default TC is supported */
4124         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4125                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4126                 return I40E_NOT_SUPPORTED;
4127         }
4128
4129         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4130                 PMD_DRV_LOG(ERR,
4131                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4132                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4133                 return I40E_NOT_SUPPORTED;
4134         }
4135         return I40E_SUCCESS;
4136 }
4137
4138 int
4139 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4140                                 struct i40e_vsi_vlan_pvid_info *info)
4141 {
4142         struct i40e_hw *hw;
4143         struct i40e_vsi_context ctxt;
4144         uint8_t vlan_flags = 0;
4145         int ret;
4146
4147         if (vsi == NULL || info == NULL) {
4148                 PMD_DRV_LOG(ERR, "invalid parameters");
4149                 return I40E_ERR_PARAM;
4150         }
4151
4152         if (info->on) {
4153                 vsi->info.pvid = info->config.pvid;
4154                 /**
4155                  * If insert pvid is enabled, only tagged pkts are
4156                  * allowed to be sent out.
4157                  */
4158                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4159                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4160         } else {
4161                 vsi->info.pvid = 0;
4162                 if (info->config.reject.tagged == 0)
4163                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4164
4165                 if (info->config.reject.untagged == 0)
4166                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4167         }
4168         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4169                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4170         vsi->info.port_vlan_flags |= vlan_flags;
4171         vsi->info.valid_sections =
4172                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4173         memset(&ctxt, 0, sizeof(ctxt));
4174         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4175         ctxt.seid = vsi->seid;
4176
4177         hw = I40E_VSI_TO_HW(vsi);
4178         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4179         if (ret != I40E_SUCCESS)
4180                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4181
4182         return ret;
4183 }
4184
4185 static int
4186 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4187 {
4188         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4189         int i, ret;
4190         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4191
4192         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4193         if (ret != I40E_SUCCESS)
4194                 return ret;
4195
4196         if (!vsi->seid) {
4197                 PMD_DRV_LOG(ERR, "seid not valid");
4198                 return -EINVAL;
4199         }
4200
4201         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4202         tc_bw_data.tc_valid_bits = enabled_tcmap;
4203         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4204                 tc_bw_data.tc_bw_credits[i] =
4205                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4206
4207         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4208         if (ret != I40E_SUCCESS) {
4209                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4210                 return ret;
4211         }
4212
4213         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4214                                         sizeof(vsi->info.qs_handle));
4215         return I40E_SUCCESS;
4216 }
4217
4218 static enum i40e_status_code
4219 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4220                                  struct i40e_aqc_vsi_properties_data *info,
4221                                  uint8_t enabled_tcmap)
4222 {
4223         enum i40e_status_code ret;
4224         int i, total_tc = 0;
4225         uint16_t qpnum_per_tc, bsf, qp_idx;
4226
4227         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4228         if (ret != I40E_SUCCESS)
4229                 return ret;
4230
4231         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4232                 if (enabled_tcmap & (1 << i))
4233                         total_tc++;
4234         vsi->enabled_tc = enabled_tcmap;
4235
4236         /* Number of queues per enabled TC */
4237         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4238         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4239         bsf = rte_bsf32(qpnum_per_tc);
4240
4241         /* Adjust the queue number to actual queues that can be applied */
4242         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4243                 vsi->nb_qps = qpnum_per_tc * total_tc;
4244
4245         /**
4246          * Configure TC and queue mapping parameters, for enabled TC,
4247          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4248          * default queue will serve it.
4249          */
4250         qp_idx = 0;
4251         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4252                 if (vsi->enabled_tc & (1 << i)) {
4253                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4254                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4255                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4256                         qp_idx += qpnum_per_tc;
4257                 } else
4258                         info->tc_mapping[i] = 0;
4259         }
4260
4261         /* Associate queue number with VSI */
4262         if (vsi->type == I40E_VSI_SRIOV) {
4263                 info->mapping_flags |=
4264                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4265                 for (i = 0; i < vsi->nb_qps; i++)
4266                         info->queue_mapping[i] =
4267                                 rte_cpu_to_le_16(vsi->base_queue + i);
4268         } else {
4269                 info->mapping_flags |=
4270                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4271                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4272         }
4273         info->valid_sections |=
4274                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4275
4276         return I40E_SUCCESS;
4277 }
4278
4279 static int
4280 i40e_veb_release(struct i40e_veb *veb)
4281 {
4282         struct i40e_vsi *vsi;
4283         struct i40e_hw *hw;
4284
4285         if (veb == NULL)
4286                 return -EINVAL;
4287
4288         if (!TAILQ_EMPTY(&veb->head)) {
4289                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4290                 return -EACCES;
4291         }
4292         /* associate_vsi field is NULL for floating VEB */
4293         if (veb->associate_vsi != NULL) {
4294                 vsi = veb->associate_vsi;
4295                 hw = I40E_VSI_TO_HW(vsi);
4296
4297                 vsi->uplink_seid = veb->uplink_seid;
4298                 vsi->veb = NULL;
4299         } else {
4300                 veb->associate_pf->main_vsi->floating_veb = NULL;
4301                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4302         }
4303
4304         i40e_aq_delete_element(hw, veb->seid, NULL);
4305         rte_free(veb);
4306         return I40E_SUCCESS;
4307 }
4308
4309 /* Setup a veb */
4310 static struct i40e_veb *
4311 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4312 {
4313         struct i40e_veb *veb;
4314         int ret;
4315         struct i40e_hw *hw;
4316
4317         if (pf == NULL) {
4318                 PMD_DRV_LOG(ERR,
4319                             "veb setup failed, associated PF shouldn't null");
4320                 return NULL;
4321         }
4322         hw = I40E_PF_TO_HW(pf);
4323
4324         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4325         if (!veb) {
4326                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4327                 goto fail;
4328         }
4329
4330         veb->associate_vsi = vsi;
4331         veb->associate_pf = pf;
4332         TAILQ_INIT(&veb->head);
4333         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4334
4335         /* create floating veb if vsi is NULL */
4336         if (vsi != NULL) {
4337                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4338                                       I40E_DEFAULT_TCMAP, false,
4339                                       &veb->seid, false, NULL);
4340         } else {
4341                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4342                                       true, &veb->seid, false, NULL);
4343         }
4344
4345         if (ret != I40E_SUCCESS) {
4346                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4347                             hw->aq.asq_last_status);
4348                 goto fail;
4349         }
4350         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4351
4352         /* get statistics index */
4353         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4354                                 &veb->stats_idx, NULL, NULL, NULL);
4355         if (ret != I40E_SUCCESS) {
4356                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4357                             hw->aq.asq_last_status);
4358                 goto fail;
4359         }
4360         /* Get VEB bandwidth, to be implemented */
4361         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4362         if (vsi)
4363                 vsi->uplink_seid = veb->seid;
4364
4365         return veb;
4366 fail:
4367         rte_free(veb);
4368         return NULL;
4369 }
4370
4371 int
4372 i40e_vsi_release(struct i40e_vsi *vsi)
4373 {
4374         struct i40e_pf *pf;
4375         struct i40e_hw *hw;
4376         struct i40e_vsi_list *vsi_list;
4377         void *temp;
4378         int ret;
4379         struct i40e_mac_filter *f;
4380         uint16_t user_param;
4381
4382         if (!vsi)
4383                 return I40E_SUCCESS;
4384
4385         if (!vsi->adapter)
4386                 return -EFAULT;
4387
4388         user_param = vsi->user_param;
4389
4390         pf = I40E_VSI_TO_PF(vsi);
4391         hw = I40E_VSI_TO_HW(vsi);
4392
4393         /* VSI has child to attach, release child first */
4394         if (vsi->veb) {
4395                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4396                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4397                                 return -1;
4398                 }
4399                 i40e_veb_release(vsi->veb);
4400         }
4401
4402         if (vsi->floating_veb) {
4403                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4404                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4405                                 return -1;
4406                 }
4407         }
4408
4409         /* Remove all macvlan filters of the VSI */
4410         i40e_vsi_remove_all_macvlan_filter(vsi);
4411         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4412                 rte_free(f);
4413
4414         if (vsi->type != I40E_VSI_MAIN &&
4415             ((vsi->type != I40E_VSI_SRIOV) ||
4416             !pf->floating_veb_list[user_param])) {
4417                 /* Remove vsi from parent's sibling list */
4418                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4419                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4420                         return I40E_ERR_PARAM;
4421                 }
4422                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4423                                 &vsi->sib_vsi_list, list);
4424
4425                 /* Remove all switch element of the VSI */
4426                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4427                 if (ret != I40E_SUCCESS)
4428                         PMD_DRV_LOG(ERR, "Failed to delete element");
4429         }
4430
4431         if ((vsi->type == I40E_VSI_SRIOV) &&
4432             pf->floating_veb_list[user_param]) {
4433                 /* Remove vsi from parent's sibling list */
4434                 if (vsi->parent_vsi == NULL ||
4435                     vsi->parent_vsi->floating_veb == NULL) {
4436                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4437                         return I40E_ERR_PARAM;
4438                 }
4439                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4440                              &vsi->sib_vsi_list, list);
4441
4442                 /* Remove all switch element of the VSI */
4443                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4444                 if (ret != I40E_SUCCESS)
4445                         PMD_DRV_LOG(ERR, "Failed to delete element");
4446         }
4447
4448         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4449
4450         if (vsi->type != I40E_VSI_SRIOV)
4451                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4452         rte_free(vsi);
4453
4454         return I40E_SUCCESS;
4455 }
4456
4457 static int
4458 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4459 {
4460         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4461         struct i40e_aqc_remove_macvlan_element_data def_filter;
4462         struct i40e_mac_filter_info filter;
4463         int ret;
4464
4465         if (vsi->type != I40E_VSI_MAIN)
4466                 return I40E_ERR_CONFIG;
4467         memset(&def_filter, 0, sizeof(def_filter));
4468         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4469                                         ETH_ADDR_LEN);
4470         def_filter.vlan_tag = 0;
4471         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4472                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4473         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4474         if (ret != I40E_SUCCESS) {
4475                 struct i40e_mac_filter *f;
4476                 struct ether_addr *mac;
4477
4478                 PMD_DRV_LOG(WARNING,
4479                         "Cannot remove the default macvlan filter");
4480                 /* It needs to add the permanent mac into mac list */
4481                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4482                 if (f == NULL) {
4483                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4484                         return I40E_ERR_NO_MEMORY;
4485                 }
4486                 mac = &f->mac_info.mac_addr;
4487                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4488                                 ETH_ADDR_LEN);
4489                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4490                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4491                 vsi->mac_num++;
4492
4493                 return ret;
4494         }
4495         (void)rte_memcpy(&filter.mac_addr,
4496                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4497         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4498         return i40e_vsi_add_mac(vsi, &filter);
4499 }
4500
4501 /*
4502  * i40e_vsi_get_bw_config - Query VSI BW Information
4503  * @vsi: the VSI to be queried
4504  *
4505  * Returns 0 on success, negative value on failure
4506  */
4507 static enum i40e_status_code
4508 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4509 {
4510         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4511         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4512         struct i40e_hw *hw = &vsi->adapter->hw;
4513         i40e_status ret;
4514         int i;
4515         uint32_t bw_max;
4516
4517         memset(&bw_config, 0, sizeof(bw_config));
4518         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4519         if (ret != I40E_SUCCESS) {
4520                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4521                             hw->aq.asq_last_status);
4522                 return ret;
4523         }
4524
4525         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4526         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4527                                         &ets_sla_config, NULL);
4528         if (ret != I40E_SUCCESS) {
4529                 PMD_DRV_LOG(ERR,
4530                         "VSI failed to get TC bandwdith configuration %u",
4531                         hw->aq.asq_last_status);
4532                 return ret;
4533         }
4534
4535         /* store and print out BW info */
4536         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4537         vsi->bw_info.bw_max = bw_config.max_bw;
4538         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4539         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4540         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4541                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4542                      I40E_16_BIT_WIDTH);
4543         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4544                 vsi->bw_info.bw_ets_share_credits[i] =
4545                                 ets_sla_config.share_credits[i];
4546                 vsi->bw_info.bw_ets_credits[i] =
4547                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4548                 /* 4 bits per TC, 4th bit is reserved */
4549                 vsi->bw_info.bw_ets_max[i] =
4550                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4551                                   RTE_LEN2MASK(3, uint8_t));
4552                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4553                             vsi->bw_info.bw_ets_share_credits[i]);
4554                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4555                             vsi->bw_info.bw_ets_credits[i]);
4556                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4557                             vsi->bw_info.bw_ets_max[i]);
4558         }
4559
4560         return I40E_SUCCESS;
4561 }
4562
4563 /* i40e_enable_pf_lb
4564  * @pf: pointer to the pf structure
4565  *
4566  * allow loopback on pf
4567  */
4568 static inline void
4569 i40e_enable_pf_lb(struct i40e_pf *pf)
4570 {
4571         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4572         struct i40e_vsi_context ctxt;
4573         int ret;
4574
4575         /* Use the FW API if FW >= v5.0 */
4576         if (hw->aq.fw_maj_ver < 5) {
4577                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4578                 return;
4579         }
4580
4581         memset(&ctxt, 0, sizeof(ctxt));
4582         ctxt.seid = pf->main_vsi_seid;
4583         ctxt.pf_num = hw->pf_id;
4584         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4585         if (ret) {
4586                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4587                             ret, hw->aq.asq_last_status);
4588                 return;
4589         }
4590         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4591         ctxt.info.valid_sections =
4592                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4593         ctxt.info.switch_id |=
4594                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4595
4596         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4597         if (ret)
4598                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4599                             hw->aq.asq_last_status);
4600 }
4601
4602 /* Setup a VSI */
4603 struct i40e_vsi *
4604 i40e_vsi_setup(struct i40e_pf *pf,
4605                enum i40e_vsi_type type,
4606                struct i40e_vsi *uplink_vsi,
4607                uint16_t user_param)
4608 {
4609         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4610         struct i40e_vsi *vsi;
4611         struct i40e_mac_filter_info filter;
4612         int ret;
4613         struct i40e_vsi_context ctxt;
4614         struct ether_addr broadcast =
4615                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4616
4617         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4618             uplink_vsi == NULL) {
4619                 PMD_DRV_LOG(ERR,
4620                         "VSI setup failed, VSI link shouldn't be NULL");
4621                 return NULL;
4622         }
4623
4624         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4625                 PMD_DRV_LOG(ERR,
4626                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4627                 return NULL;
4628         }
4629
4630         /* two situations
4631          * 1.type is not MAIN and uplink vsi is not NULL
4632          * If uplink vsi didn't setup VEB, create one first under veb field
4633          * 2.type is SRIOV and the uplink is NULL
4634          * If floating VEB is NULL, create one veb under floating veb field
4635          */
4636
4637         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4638             uplink_vsi->veb == NULL) {
4639                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4640
4641                 if (uplink_vsi->veb == NULL) {
4642                         PMD_DRV_LOG(ERR, "VEB setup failed");
4643                         return NULL;
4644                 }
4645                 /* set ALLOWLOOPBACk on pf, when veb is created */
4646                 i40e_enable_pf_lb(pf);
4647         }
4648
4649         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4650             pf->main_vsi->floating_veb == NULL) {
4651                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4652
4653                 if (pf->main_vsi->floating_veb == NULL) {
4654                         PMD_DRV_LOG(ERR, "VEB setup failed");
4655                         return NULL;
4656                 }
4657         }
4658
4659         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4660         if (!vsi) {
4661                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4662                 return NULL;
4663         }
4664         TAILQ_INIT(&vsi->mac_list);
4665         vsi->type = type;
4666         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4667         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4668         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4669         vsi->user_param = user_param;
4670         vsi->vlan_anti_spoof_on = 0;
4671         /* Allocate queues */
4672         switch (vsi->type) {
4673         case I40E_VSI_MAIN  :
4674                 vsi->nb_qps = pf->lan_nb_qps;
4675                 break;
4676         case I40E_VSI_SRIOV :
4677                 vsi->nb_qps = pf->vf_nb_qps;
4678                 break;
4679         case I40E_VSI_VMDQ2:
4680                 vsi->nb_qps = pf->vmdq_nb_qps;
4681                 break;
4682         case I40E_VSI_FDIR:
4683                 vsi->nb_qps = pf->fdir_nb_qps;
4684                 break;
4685         default:
4686                 goto fail_mem;
4687         }
4688         /*
4689          * The filter status descriptor is reported in rx queue 0,
4690          * while the tx queue for fdir filter programming has no
4691          * such constraints, can be non-zero queues.
4692          * To simplify it, choose FDIR vsi use queue 0 pair.
4693          * To make sure it will use queue 0 pair, queue allocation
4694          * need be done before this function is called
4695          */
4696         if (type != I40E_VSI_FDIR) {
4697                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4698                         if (ret < 0) {
4699                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4700                                                 vsi->seid, ret);
4701                                 goto fail_mem;
4702                         }
4703                         vsi->base_queue = ret;
4704         } else
4705                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4706
4707         /* VF has MSIX interrupt in VF range, don't allocate here */
4708         if (type == I40E_VSI_MAIN) {
4709                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4710                                           RTE_MIN(vsi->nb_qps,
4711                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4712                 if (ret < 0) {
4713                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4714                                     vsi->seid, ret);
4715                         goto fail_queue_alloc;
4716                 }
4717                 vsi->msix_intr = ret;
4718                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4719         } else if (type != I40E_VSI_SRIOV) {
4720                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4721                 if (ret < 0) {
4722                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4723                         goto fail_queue_alloc;
4724                 }
4725                 vsi->msix_intr = ret;
4726                 vsi->nb_msix = 1;
4727         } else {
4728                 vsi->msix_intr = 0;
4729                 vsi->nb_msix = 0;
4730         }
4731
4732         /* Add VSI */
4733         if (type == I40E_VSI_MAIN) {
4734                 /* For main VSI, no need to add since it's default one */
4735                 vsi->uplink_seid = pf->mac_seid;
4736                 vsi->seid = pf->main_vsi_seid;
4737                 /* Bind queues with specific MSIX interrupt */
4738                 /**
4739                  * Needs 2 interrupt at least, one for misc cause which will
4740                  * enabled from OS side, Another for queues binding the
4741                  * interrupt from device side only.
4742                  */
4743
4744                 /* Get default VSI parameters from hardware */
4745                 memset(&ctxt, 0, sizeof(ctxt));
4746                 ctxt.seid = vsi->seid;
4747                 ctxt.pf_num = hw->pf_id;
4748                 ctxt.uplink_seid = vsi->uplink_seid;
4749                 ctxt.vf_num = 0;
4750                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4751                 if (ret != I40E_SUCCESS) {
4752                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4753                         goto fail_msix_alloc;
4754                 }
4755                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4756                         sizeof(struct i40e_aqc_vsi_properties_data));
4757                 vsi->vsi_id = ctxt.vsi_number;
4758                 vsi->info.valid_sections = 0;
4759
4760                 /* Configure tc, enabled TC0 only */
4761                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4762                         I40E_SUCCESS) {
4763                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4764                         goto fail_msix_alloc;
4765                 }
4766
4767                 /* TC, queue mapping */
4768                 memset(&ctxt, 0, sizeof(ctxt));
4769                 vsi->info.valid_sections |=
4770                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4771                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4772                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4773                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4774                         sizeof(struct i40e_aqc_vsi_properties_data));
4775                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4776                                                 I40E_DEFAULT_TCMAP);
4777                 if (ret != I40E_SUCCESS) {
4778                         PMD_DRV_LOG(ERR,
4779                                 "Failed to configure TC queue mapping");
4780                         goto fail_msix_alloc;
4781                 }
4782                 ctxt.seid = vsi->seid;
4783                 ctxt.pf_num = hw->pf_id;
4784                 ctxt.uplink_seid = vsi->uplink_seid;
4785                 ctxt.vf_num = 0;
4786
4787                 /* Update VSI parameters */
4788                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4789                 if (ret != I40E_SUCCESS) {
4790                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4791                         goto fail_msix_alloc;
4792                 }
4793
4794                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4795                                                 sizeof(vsi->info.tc_mapping));
4796                 (void)rte_memcpy(&vsi->info.queue_mapping,
4797                                 &ctxt.info.queue_mapping,
4798                         sizeof(vsi->info.queue_mapping));
4799                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4800                 vsi->info.valid_sections = 0;
4801
4802                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4803                                 ETH_ADDR_LEN);
4804
4805                 /**
4806                  * Updating default filter settings are necessary to prevent
4807                  * reception of tagged packets.
4808                  * Some old firmware configurations load a default macvlan
4809                  * filter which accepts both tagged and untagged packets.
4810                  * The updating is to use a normal filter instead if needed.
4811                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4812                  * The firmware with correct configurations load the default
4813                  * macvlan filter which is expected and cannot be removed.
4814                  */
4815                 i40e_update_default_filter_setting(vsi);
4816                 i40e_config_qinq(hw, vsi);
4817         } else if (type == I40E_VSI_SRIOV) {
4818                 memset(&ctxt, 0, sizeof(ctxt));
4819                 /**
4820                  * For other VSI, the uplink_seid equals to uplink VSI's
4821                  * uplink_seid since they share same VEB
4822                  */
4823                 if (uplink_vsi == NULL)
4824                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4825                 else
4826                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4827                 ctxt.pf_num = hw->pf_id;
4828                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4829                 ctxt.uplink_seid = vsi->uplink_seid;
4830                 ctxt.connection_type = 0x1;
4831                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4832
4833                 /* Use the VEB configuration if FW >= v5.0 */
4834                 if (hw->aq.fw_maj_ver >= 5) {
4835                         /* Configure switch ID */
4836                         ctxt.info.valid_sections |=
4837                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4838                         ctxt.info.switch_id =
4839                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4840                 }
4841
4842                 /* Configure port/vlan */
4843                 ctxt.info.valid_sections |=
4844                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4845                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4846                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4847                                                 I40E_DEFAULT_TCMAP);
4848                 if (ret != I40E_SUCCESS) {
4849                         PMD_DRV_LOG(ERR,
4850                                 "Failed to configure TC queue mapping");
4851                         goto fail_msix_alloc;
4852                 }
4853                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4854                 ctxt.info.valid_sections |=
4855                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4856                 /**
4857                  * Since VSI is not created yet, only configure parameter,
4858                  * will add vsi below.
4859                  */
4860
4861                 i40e_config_qinq(hw, vsi);
4862         } else if (type == I40E_VSI_VMDQ2) {
4863                 memset(&ctxt, 0, sizeof(ctxt));
4864                 /*
4865                  * For other VSI, the uplink_seid equals to uplink VSI's
4866                  * uplink_seid since they share same VEB
4867                  */
4868                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4869                 ctxt.pf_num = hw->pf_id;
4870                 ctxt.vf_num = 0;
4871                 ctxt.uplink_seid = vsi->uplink_seid;
4872                 ctxt.connection_type = 0x1;
4873                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4874
4875                 ctxt.info.valid_sections |=
4876                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4877                 /* user_param carries flag to enable loop back */
4878                 if (user_param) {
4879                         ctxt.info.switch_id =
4880                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4881                         ctxt.info.switch_id |=
4882                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4883                 }
4884
4885                 /* Configure port/vlan */
4886                 ctxt.info.valid_sections |=
4887                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4888                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4889                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4890                                                 I40E_DEFAULT_TCMAP);
4891                 if (ret != I40E_SUCCESS) {
4892                         PMD_DRV_LOG(ERR,
4893                                 "Failed to configure TC queue mapping");
4894                         goto fail_msix_alloc;
4895                 }
4896                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4897                 ctxt.info.valid_sections |=
4898                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4899         } else if (type == I40E_VSI_FDIR) {
4900                 memset(&ctxt, 0, sizeof(ctxt));
4901                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4902                 ctxt.pf_num = hw->pf_id;
4903                 ctxt.vf_num = 0;
4904                 ctxt.uplink_seid = vsi->uplink_seid;
4905                 ctxt.connection_type = 0x1;     /* regular data port */
4906                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4907                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4908                                                 I40E_DEFAULT_TCMAP);
4909                 if (ret != I40E_SUCCESS) {
4910                         PMD_DRV_LOG(ERR,
4911                                 "Failed to configure TC queue mapping.");
4912                         goto fail_msix_alloc;
4913                 }
4914                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4915                 ctxt.info.valid_sections |=
4916                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4917         } else {
4918                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4919                 goto fail_msix_alloc;
4920         }
4921
4922         if (vsi->type != I40E_VSI_MAIN) {
4923                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4924                 if (ret != I40E_SUCCESS) {
4925                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4926                                     hw->aq.asq_last_status);
4927                         goto fail_msix_alloc;
4928                 }
4929                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4930                 vsi->info.valid_sections = 0;
4931                 vsi->seid = ctxt.seid;
4932                 vsi->vsi_id = ctxt.vsi_number;
4933                 vsi->sib_vsi_list.vsi = vsi;
4934                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4935                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4936                                           &vsi->sib_vsi_list, list);
4937                 } else {
4938                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4939                                           &vsi->sib_vsi_list, list);
4940                 }
4941         }
4942
4943         /* MAC/VLAN configuration */
4944         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4945         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4946
4947         ret = i40e_vsi_add_mac(vsi, &filter);
4948         if (ret != I40E_SUCCESS) {
4949                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4950                 goto fail_msix_alloc;
4951         }
4952
4953         /* Get VSI BW information */
4954         i40e_vsi_get_bw_config(vsi);
4955         return vsi;
4956 fail_msix_alloc:
4957         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4958 fail_queue_alloc:
4959         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4960 fail_mem:
4961         rte_free(vsi);
4962         return NULL;
4963 }
4964
4965 /* Configure vlan filter on or off */
4966 int
4967 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4968 {
4969         int i, num;
4970         struct i40e_mac_filter *f;
4971         void *temp;
4972         struct i40e_mac_filter_info *mac_filter;
4973         enum rte_mac_filter_type desired_filter;
4974         int ret = I40E_SUCCESS;
4975
4976         if (on) {
4977                 /* Filter to match MAC and VLAN */
4978                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4979         } else {
4980                 /* Filter to match only MAC */
4981                 desired_filter = RTE_MAC_PERFECT_MATCH;
4982         }
4983
4984         num = vsi->mac_num;
4985
4986         mac_filter = rte_zmalloc("mac_filter_info_data",
4987                                  num * sizeof(*mac_filter), 0);
4988         if (mac_filter == NULL) {
4989                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4990                 return I40E_ERR_NO_MEMORY;
4991         }
4992
4993         i = 0;
4994
4995         /* Remove all existing mac */
4996         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4997                 mac_filter[i] = f->mac_info;
4998                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4999                 if (ret) {
5000                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5001                                     on ? "enable" : "disable");
5002                         goto DONE;
5003                 }
5004                 i++;
5005         }
5006
5007         /* Override with new filter */
5008         for (i = 0; i < num; i++) {
5009                 mac_filter[i].filter_type = desired_filter;
5010                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5011                 if (ret) {
5012                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5013                                     on ? "enable" : "disable");
5014                         goto DONE;
5015                 }
5016         }
5017
5018 DONE:
5019         rte_free(mac_filter);
5020         return ret;
5021 }
5022
5023 /* Configure vlan stripping on or off */
5024 int
5025 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5026 {
5027         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5028         struct i40e_vsi_context ctxt;
5029         uint8_t vlan_flags;
5030         int ret = I40E_SUCCESS;
5031
5032         /* Check if it has been already on or off */
5033         if (vsi->info.valid_sections &
5034                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5035                 if (on) {
5036                         if ((vsi->info.port_vlan_flags &
5037                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5038                                 return 0; /* already on */
5039                 } else {
5040                         if ((vsi->info.port_vlan_flags &
5041                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5042                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5043                                 return 0; /* already off */
5044                 }
5045         }
5046
5047         if (on)
5048                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5049         else
5050                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5051         vsi->info.valid_sections =
5052                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5053         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5054         vsi->info.port_vlan_flags |= vlan_flags;
5055         ctxt.seid = vsi->seid;
5056         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5057         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5058         if (ret)
5059                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5060                             on ? "enable" : "disable");
5061
5062         return ret;
5063 }
5064
5065 static int
5066 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5067 {
5068         struct rte_eth_dev_data *data = dev->data;
5069         int ret;
5070         int mask = 0;
5071
5072         /* Apply vlan offload setting */
5073         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5074         i40e_vlan_offload_set(dev, mask);
5075
5076         /* Apply double-vlan setting, not implemented yet */
5077
5078         /* Apply pvid setting */
5079         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5080                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5081         if (ret)
5082                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5083
5084         return ret;
5085 }
5086
5087 static int
5088 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5089 {
5090         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5091
5092         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5093 }
5094
5095 static int
5096 i40e_update_flow_control(struct i40e_hw *hw)
5097 {
5098 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5099         struct i40e_link_status link_status;
5100         uint32_t rxfc = 0, txfc = 0, reg;
5101         uint8_t an_info;
5102         int ret;
5103
5104         memset(&link_status, 0, sizeof(link_status));
5105         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5106         if (ret != I40E_SUCCESS) {
5107                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5108                 goto write_reg; /* Disable flow control */
5109         }
5110
5111         an_info = hw->phy.link_info.an_info;
5112         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5113                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5114                 ret = I40E_ERR_NOT_READY;
5115                 goto write_reg; /* Disable flow control */
5116         }
5117         /**
5118          * If link auto negotiation is enabled, flow control needs to
5119          * be configured according to it
5120          */
5121         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5122         case I40E_LINK_PAUSE_RXTX:
5123                 rxfc = 1;
5124                 txfc = 1;
5125                 hw->fc.current_mode = I40E_FC_FULL;
5126                 break;
5127         case I40E_AQ_LINK_PAUSE_RX:
5128                 rxfc = 1;
5129                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5130                 break;
5131         case I40E_AQ_LINK_PAUSE_TX:
5132                 txfc = 1;
5133                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5134                 break;
5135         default:
5136                 hw->fc.current_mode = I40E_FC_NONE;
5137                 break;
5138         }
5139
5140 write_reg:
5141         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5142                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5143         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5144         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5145         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5146         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5147
5148         return ret;
5149 }
5150
5151 /* PF setup */
5152 static int
5153 i40e_pf_setup(struct i40e_pf *pf)
5154 {
5155         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5156         struct i40e_filter_control_settings settings;
5157         struct i40e_vsi *vsi;
5158         int ret;
5159
5160         /* Clear all stats counters */
5161         pf->offset_loaded = FALSE;
5162         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5163         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5164
5165         ret = i40e_pf_get_switch_config(pf);
5166         if (ret != I40E_SUCCESS) {
5167                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5168                 return ret;
5169         }
5170         if (pf->flags & I40E_FLAG_FDIR) {
5171                 /* make queue allocated first, let FDIR use queue pair 0*/
5172                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5173                 if (ret != I40E_FDIR_QUEUE_ID) {
5174                         PMD_DRV_LOG(ERR,
5175                                 "queue allocation fails for FDIR: ret =%d",
5176                                 ret);
5177                         pf->flags &= ~I40E_FLAG_FDIR;
5178                 }
5179         }
5180         /*  main VSI setup */
5181         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5182         if (!vsi) {
5183                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5184                 return I40E_ERR_NOT_READY;
5185         }
5186         pf->main_vsi = vsi;
5187
5188         /* Configure filter control */
5189         memset(&settings, 0, sizeof(settings));
5190         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5191                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5192         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5193                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5194         else {
5195                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5196                         hw->func_caps.rss_table_size);
5197                 return I40E_ERR_PARAM;
5198         }
5199         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5200                 hw->func_caps.rss_table_size);
5201         pf->hash_lut_size = hw->func_caps.rss_table_size;
5202
5203         /* Enable ethtype and macvlan filters */
5204         settings.enable_ethtype = TRUE;
5205         settings.enable_macvlan = TRUE;
5206         ret = i40e_set_filter_control(hw, &settings);
5207         if (ret)
5208                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5209                                                                 ret);
5210
5211         /* Update flow control according to the auto negotiation */
5212         i40e_update_flow_control(hw);
5213
5214         return I40E_SUCCESS;
5215 }
5216
5217 int
5218 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5219 {
5220         uint32_t reg;
5221         uint16_t j;
5222
5223         /**
5224          * Set or clear TX Queue Disable flags,
5225          * which is required by hardware.
5226          */
5227         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5228         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5229
5230         /* Wait until the request is finished */
5231         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5232                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5233                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5234                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5235                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5236                                                         & 0x1))) {
5237                         break;
5238                 }
5239         }
5240         if (on) {
5241                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5242                         return I40E_SUCCESS; /* already on, skip next steps */
5243
5244                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5245                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5246         } else {
5247                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5248                         return I40E_SUCCESS; /* already off, skip next steps */
5249                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5250         }
5251         /* Write the register */
5252         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5253         /* Check the result */
5254         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5255                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5256                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5257                 if (on) {
5258                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5259                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5260                                 break;
5261                 } else {
5262                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5263                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5264                                 break;
5265                 }
5266         }
5267         /* Check if it is timeout */
5268         if (j >= I40E_CHK_Q_ENA_COUNT) {
5269                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5270                             (on ? "enable" : "disable"), q_idx);
5271                 return I40E_ERR_TIMEOUT;
5272         }
5273
5274         return I40E_SUCCESS;
5275 }
5276
5277 /* Swith on or off the tx queues */
5278 static int
5279 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5280 {
5281         struct rte_eth_dev_data *dev_data = pf->dev_data;
5282         struct i40e_tx_queue *txq;
5283         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5284         uint16_t i;
5285         int ret;
5286
5287         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5288                 txq = dev_data->tx_queues[i];
5289                 /* Don't operate the queue if not configured or
5290                  * if starting only per queue */
5291                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5292                         continue;
5293                 if (on)
5294                         ret = i40e_dev_tx_queue_start(dev, i);
5295                 else
5296                         ret = i40e_dev_tx_queue_stop(dev, i);
5297                 if ( ret != I40E_SUCCESS)
5298                         return ret;
5299         }
5300
5301         return I40E_SUCCESS;
5302 }
5303
5304 int
5305 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5306 {
5307         uint32_t reg;
5308         uint16_t j;
5309
5310         /* Wait until the request is finished */
5311         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5312                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5313                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5314                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5315                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5316                         break;
5317         }
5318
5319         if (on) {
5320                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5321                         return I40E_SUCCESS; /* Already on, skip next steps */
5322                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5323         } else {
5324                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5325                         return I40E_SUCCESS; /* Already off, skip next steps */
5326                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5327         }
5328
5329         /* Write the register */
5330         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5331         /* Check the result */
5332         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5333                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5334                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5335                 if (on) {
5336                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5337                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5338                                 break;
5339                 } else {
5340                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5341                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5342                                 break;
5343                 }
5344         }
5345
5346         /* Check if it is timeout */
5347         if (j >= I40E_CHK_Q_ENA_COUNT) {
5348                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5349                             (on ? "enable" : "disable"), q_idx);
5350                 return I40E_ERR_TIMEOUT;
5351         }
5352
5353         return I40E_SUCCESS;
5354 }
5355 /* Switch on or off the rx queues */
5356 static int
5357 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5358 {
5359         struct rte_eth_dev_data *dev_data = pf->dev_data;
5360         struct i40e_rx_queue *rxq;
5361         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5362         uint16_t i;
5363         int ret;
5364
5365         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5366                 rxq = dev_data->rx_queues[i];
5367                 /* Don't operate the queue if not configured or
5368                  * if starting only per queue */
5369                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5370                         continue;
5371                 if (on)
5372                         ret = i40e_dev_rx_queue_start(dev, i);
5373                 else
5374                         ret = i40e_dev_rx_queue_stop(dev, i);
5375                 if (ret != I40E_SUCCESS)
5376                         return ret;
5377         }
5378
5379         return I40E_SUCCESS;
5380 }
5381
5382 /* Switch on or off all the rx/tx queues */
5383 int
5384 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5385 {
5386         int ret;
5387
5388         if (on) {
5389                 /* enable rx queues before enabling tx queues */
5390                 ret = i40e_dev_switch_rx_queues(pf, on);
5391                 if (ret) {
5392                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5393                         return ret;
5394                 }
5395                 ret = i40e_dev_switch_tx_queues(pf, on);
5396         } else {
5397                 /* Stop tx queues before stopping rx queues */
5398                 ret = i40e_dev_switch_tx_queues(pf, on);
5399                 if (ret) {
5400                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5401                         return ret;
5402                 }
5403                 ret = i40e_dev_switch_rx_queues(pf, on);
5404         }
5405
5406         return ret;
5407 }
5408
5409 /* Initialize VSI for TX */
5410 static int
5411 i40e_dev_tx_init(struct i40e_pf *pf)
5412 {
5413         struct rte_eth_dev_data *data = pf->dev_data;
5414         uint16_t i;
5415         uint32_t ret = I40E_SUCCESS;
5416         struct i40e_tx_queue *txq;
5417
5418         for (i = 0; i < data->nb_tx_queues; i++) {
5419                 txq = data->tx_queues[i];
5420                 if (!txq || !txq->q_set)
5421                         continue;
5422                 ret = i40e_tx_queue_init(txq);
5423                 if (ret != I40E_SUCCESS)
5424                         break;
5425         }
5426         if (ret == I40E_SUCCESS)
5427                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5428                                      ->eth_dev);
5429
5430         return ret;
5431 }
5432
5433 /* Initialize VSI for RX */
5434 static int
5435 i40e_dev_rx_init(struct i40e_pf *pf)
5436 {
5437         struct rte_eth_dev_data *data = pf->dev_data;
5438         int ret = I40E_SUCCESS;
5439         uint16_t i;
5440         struct i40e_rx_queue *rxq;
5441
5442         i40e_pf_config_mq_rx(pf);
5443         for (i = 0; i < data->nb_rx_queues; i++) {
5444                 rxq = data->rx_queues[i];
5445                 if (!rxq || !rxq->q_set)
5446                         continue;
5447
5448                 ret = i40e_rx_queue_init(rxq);
5449                 if (ret != I40E_SUCCESS) {
5450                         PMD_DRV_LOG(ERR,
5451                                 "Failed to do RX queue initialization");
5452                         break;
5453                 }
5454         }
5455         if (ret == I40E_SUCCESS)
5456                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5457                                      ->eth_dev);
5458
5459         return ret;
5460 }
5461
5462 static int
5463 i40e_dev_rxtx_init(struct i40e_pf *pf)
5464 {
5465         int err;
5466
5467         err = i40e_dev_tx_init(pf);
5468         if (err) {
5469                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5470                 return err;
5471         }
5472         err = i40e_dev_rx_init(pf);
5473         if (err) {
5474                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5475                 return err;
5476         }
5477
5478         return err;
5479 }
5480
5481 static int
5482 i40e_vmdq_setup(struct rte_eth_dev *dev)
5483 {
5484         struct rte_eth_conf *conf = &dev->data->dev_conf;
5485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5486         int i, err, conf_vsis, j, loop;
5487         struct i40e_vsi *vsi;
5488         struct i40e_vmdq_info *vmdq_info;
5489         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5490         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5491
5492         /*
5493          * Disable interrupt to avoid message from VF. Furthermore, it will
5494          * avoid race condition in VSI creation/destroy.
5495          */
5496         i40e_pf_disable_irq0(hw);
5497
5498         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5499                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5500                 return -ENOTSUP;
5501         }
5502
5503         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5504         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5505                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5506                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5507                         pf->max_nb_vmdq_vsi);
5508                 return -ENOTSUP;
5509         }
5510
5511         if (pf->vmdq != NULL) {
5512                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5513                 return 0;
5514         }
5515
5516         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5517                                 sizeof(*vmdq_info) * conf_vsis, 0);
5518
5519         if (pf->vmdq == NULL) {
5520                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5521                 return -ENOMEM;
5522         }
5523
5524         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5525
5526         /* Create VMDQ VSI */
5527         for (i = 0; i < conf_vsis; i++) {
5528                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5529                                 vmdq_conf->enable_loop_back);
5530                 if (vsi == NULL) {
5531                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5532                         err = -1;
5533                         goto err_vsi_setup;
5534                 }
5535                 vmdq_info = &pf->vmdq[i];
5536                 vmdq_info->pf = pf;
5537                 vmdq_info->vsi = vsi;
5538         }
5539         pf->nb_cfg_vmdq_vsi = conf_vsis;
5540
5541         /* Configure Vlan */
5542         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5543         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5544                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5545                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5546                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5547                                         vmdq_conf->pool_map[i].vlan_id, j);
5548
5549                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5550                                                 vmdq_conf->pool_map[i].vlan_id);
5551                                 if (err) {
5552                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5553                                         err = -1;
5554                                         goto err_vsi_setup;
5555                                 }
5556                         }
5557                 }
5558         }
5559
5560         i40e_pf_enable_irq0(hw);
5561
5562         return 0;
5563
5564 err_vsi_setup:
5565         for (i = 0; i < conf_vsis; i++)
5566                 if (pf->vmdq[i].vsi == NULL)
5567                         break;
5568                 else
5569                         i40e_vsi_release(pf->vmdq[i].vsi);
5570
5571         rte_free(pf->vmdq);
5572         pf->vmdq = NULL;
5573         i40e_pf_enable_irq0(hw);
5574         return err;
5575 }
5576
5577 static void
5578 i40e_stat_update_32(struct i40e_hw *hw,
5579                    uint32_t reg,
5580                    bool offset_loaded,
5581                    uint64_t *offset,
5582                    uint64_t *stat)
5583 {
5584         uint64_t new_data;
5585
5586         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5587         if (!offset_loaded)
5588                 *offset = new_data;
5589
5590         if (new_data >= *offset)
5591                 *stat = (uint64_t)(new_data - *offset);
5592         else
5593                 *stat = (uint64_t)((new_data +
5594                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5595 }
5596
5597 static void
5598 i40e_stat_update_48(struct i40e_hw *hw,
5599                    uint32_t hireg,
5600                    uint32_t loreg,
5601                    bool offset_loaded,
5602                    uint64_t *offset,
5603                    uint64_t *stat)
5604 {
5605         uint64_t new_data;
5606
5607         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5608         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5609                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5610
5611         if (!offset_loaded)
5612                 *offset = new_data;
5613
5614         if (new_data >= *offset)
5615                 *stat = new_data - *offset;
5616         else
5617                 *stat = (uint64_t)((new_data +
5618                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5619
5620         *stat &= I40E_48_BIT_MASK;
5621 }
5622
5623 /* Disable IRQ0 */
5624 void
5625 i40e_pf_disable_irq0(struct i40e_hw *hw)
5626 {
5627         /* Disable all interrupt types */
5628         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5629         I40E_WRITE_FLUSH(hw);
5630 }
5631
5632 /* Enable IRQ0 */
5633 void
5634 i40e_pf_enable_irq0(struct i40e_hw *hw)
5635 {
5636         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5637                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5638                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5639                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5640         I40E_WRITE_FLUSH(hw);
5641 }
5642
5643 static void
5644 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5645 {
5646         /* read pending request and disable first */
5647         i40e_pf_disable_irq0(hw);
5648         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5649         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5650                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5651
5652         if (no_queue)
5653                 /* Link no queues with irq0 */
5654                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5655                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5656 }
5657
5658 static void
5659 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5660 {
5661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5662         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5663         int i;
5664         uint16_t abs_vf_id;
5665         uint32_t index, offset, val;
5666
5667         if (!pf->vfs)
5668                 return;
5669         /**
5670          * Try to find which VF trigger a reset, use absolute VF id to access
5671          * since the reg is global register.
5672          */
5673         for (i = 0; i < pf->vf_num; i++) {
5674                 abs_vf_id = hw->func_caps.vf_base_id + i;
5675                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5676                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5677                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5678                 /* VFR event occured */
5679                 if (val & (0x1 << offset)) {
5680                         int ret;
5681
5682                         /* Clear the event first */
5683                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5684                                                         (0x1 << offset));
5685                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5686                         /**
5687                          * Only notify a VF reset event occured,
5688                          * don't trigger another SW reset
5689                          */
5690                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5691                         if (ret != I40E_SUCCESS)
5692                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5693                 }
5694         }
5695 }
5696
5697 static void
5698 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5699 {
5700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5701         struct i40e_virtchnl_pf_event event;
5702         int i;
5703
5704         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5705         event.event_data.link_event.link_status =
5706                 dev->data->dev_link.link_status;
5707         event.event_data.link_event.link_speed =
5708                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5709
5710         for (i = 0; i < pf->vf_num; i++)
5711                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5712                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5713 }
5714
5715 static void
5716 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5717 {
5718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5719         struct i40e_arq_event_info info;
5720         uint16_t pending, opcode;
5721         int ret;
5722
5723         info.buf_len = I40E_AQ_BUF_SZ;
5724         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5725         if (!info.msg_buf) {
5726                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5727                 return;
5728         }
5729
5730         pending = 1;
5731         while (pending) {
5732                 ret = i40e_clean_arq_element(hw, &info, &pending);
5733
5734                 if (ret != I40E_SUCCESS) {
5735                         PMD_DRV_LOG(INFO,
5736                                 "Failed to read msg from AdminQ, aq_err: %u",
5737                                 hw->aq.asq_last_status);
5738                         break;
5739                 }
5740                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5741
5742                 switch (opcode) {
5743                 case i40e_aqc_opc_send_msg_to_pf:
5744                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5745                         i40e_pf_host_handle_vf_msg(dev,
5746                                         rte_le_to_cpu_16(info.desc.retval),
5747                                         rte_le_to_cpu_32(info.desc.cookie_high),
5748                                         rte_le_to_cpu_32(info.desc.cookie_low),
5749                                         info.msg_buf,
5750                                         info.msg_len);
5751                         break;
5752                 case i40e_aqc_opc_get_link_status:
5753                         ret = i40e_dev_link_update(dev, 0);
5754                         if (!ret) {
5755                                 i40e_notify_all_vfs_link_status(dev);
5756                                 _rte_eth_dev_callback_process(dev,
5757                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5758                         }
5759                         break;
5760                 default:
5761                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5762                                     opcode);
5763                         break;
5764                 }
5765         }
5766         rte_free(info.msg_buf);
5767 }
5768
5769 /**
5770  * Interrupt handler triggered by NIC  for handling
5771  * specific interrupt.
5772  *
5773  * @param handle
5774  *  Pointer to interrupt handle.
5775  * @param param
5776  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5777  *
5778  * @return
5779  *  void
5780  */
5781 static void
5782 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5783                            void *param)
5784 {
5785         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5786         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5787         uint32_t icr0;
5788
5789         /* Disable interrupt */
5790         i40e_pf_disable_irq0(hw);
5791
5792         /* read out interrupt causes */
5793         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5794
5795         /* No interrupt event indicated */
5796         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5797                 PMD_DRV_LOG(INFO, "No interrupt event");
5798                 goto done;
5799         }
5800 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5801         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5802                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5803         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5804                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5805         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5806                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5807         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5808                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5809         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5810                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5811         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5812                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5813         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5814                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5815 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5816
5817         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5818                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5819                 i40e_dev_handle_vfr_event(dev);
5820         }
5821         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5822                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5823                 i40e_dev_handle_aq_msg(dev);
5824         }
5825
5826 done:
5827         /* Enable interrupt */
5828         i40e_pf_enable_irq0(hw);
5829         rte_intr_enable(intr_handle);
5830 }
5831
5832 static int
5833 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5834                          struct i40e_macvlan_filter *filter,
5835                          int total)
5836 {
5837         int ele_num, ele_buff_size;
5838         int num, actual_num, i;
5839         uint16_t flags;
5840         int ret = I40E_SUCCESS;
5841         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5842         struct i40e_aqc_add_macvlan_element_data *req_list;
5843
5844         if (filter == NULL  || total == 0)
5845                 return I40E_ERR_PARAM;
5846         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5847         ele_buff_size = hw->aq.asq_buf_size;
5848
5849         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5850         if (req_list == NULL) {
5851                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5852                 return I40E_ERR_NO_MEMORY;
5853         }
5854
5855         num = 0;
5856         do {
5857                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5858                 memset(req_list, 0, ele_buff_size);
5859
5860                 for (i = 0; i < actual_num; i++) {
5861                         (void)rte_memcpy(req_list[i].mac_addr,
5862                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5863                         req_list[i].vlan_tag =
5864                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5865
5866                         switch (filter[num + i].filter_type) {
5867                         case RTE_MAC_PERFECT_MATCH:
5868                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5869                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5870                                 break;
5871                         case RTE_MACVLAN_PERFECT_MATCH:
5872                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5873                                 break;
5874                         case RTE_MAC_HASH_MATCH:
5875                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5876                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5877                                 break;
5878                         case RTE_MACVLAN_HASH_MATCH:
5879                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5880                                 break;
5881                         default:
5882                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5883                                 ret = I40E_ERR_PARAM;
5884                                 goto DONE;
5885                         }
5886
5887                         req_list[i].queue_number = 0;
5888
5889                         req_list[i].flags = rte_cpu_to_le_16(flags);
5890                 }
5891
5892                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5893                                                 actual_num, NULL);
5894                 if (ret != I40E_SUCCESS) {
5895                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5896                         goto DONE;
5897                 }
5898                 num += actual_num;
5899         } while (num < total);
5900
5901 DONE:
5902         rte_free(req_list);
5903         return ret;
5904 }
5905
5906 static int
5907 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5908                             struct i40e_macvlan_filter *filter,
5909                             int total)
5910 {
5911         int ele_num, ele_buff_size;
5912         int num, actual_num, i;
5913         uint16_t flags;
5914         int ret = I40E_SUCCESS;
5915         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5916         struct i40e_aqc_remove_macvlan_element_data *req_list;
5917
5918         if (filter == NULL  || total == 0)
5919                 return I40E_ERR_PARAM;
5920
5921         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5922         ele_buff_size = hw->aq.asq_buf_size;
5923
5924         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5925         if (req_list == NULL) {
5926                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5927                 return I40E_ERR_NO_MEMORY;
5928         }
5929
5930         num = 0;
5931         do {
5932                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5933                 memset(req_list, 0, ele_buff_size);
5934
5935                 for (i = 0; i < actual_num; i++) {
5936                         (void)rte_memcpy(req_list[i].mac_addr,
5937                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5938                         req_list[i].vlan_tag =
5939                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5940
5941                         switch (filter[num + i].filter_type) {
5942                         case RTE_MAC_PERFECT_MATCH:
5943                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5944                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5945                                 break;
5946                         case RTE_MACVLAN_PERFECT_MATCH:
5947                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5948                                 break;
5949                         case RTE_MAC_HASH_MATCH:
5950                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5951                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5952                                 break;
5953                         case RTE_MACVLAN_HASH_MATCH:
5954                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5955                                 break;
5956                         default:
5957                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5958                                 ret = I40E_ERR_PARAM;
5959                                 goto DONE;
5960                         }
5961                         req_list[i].flags = rte_cpu_to_le_16(flags);
5962                 }
5963
5964                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5965                                                 actual_num, NULL);
5966                 if (ret != I40E_SUCCESS) {
5967                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5968                         goto DONE;
5969                 }
5970                 num += actual_num;
5971         } while (num < total);
5972
5973 DONE:
5974         rte_free(req_list);
5975         return ret;
5976 }
5977
5978 /* Find out specific MAC filter */
5979 static struct i40e_mac_filter *
5980 i40e_find_mac_filter(struct i40e_vsi *vsi,
5981                          struct ether_addr *macaddr)
5982 {
5983         struct i40e_mac_filter *f;
5984
5985         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5986                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5987                         return f;
5988         }
5989
5990         return NULL;
5991 }
5992
5993 static bool
5994 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5995                          uint16_t vlan_id)
5996 {
5997         uint32_t vid_idx, vid_bit;
5998
5999         if (vlan_id > ETH_VLAN_ID_MAX)
6000                 return 0;
6001
6002         vid_idx = I40E_VFTA_IDX(vlan_id);
6003         vid_bit = I40E_VFTA_BIT(vlan_id);
6004
6005         if (vsi->vfta[vid_idx] & vid_bit)
6006                 return 1;
6007         else
6008                 return 0;
6009 }
6010
6011 static void
6012 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6013                        uint16_t vlan_id, bool on)
6014 {
6015         uint32_t vid_idx, vid_bit;
6016
6017         vid_idx = I40E_VFTA_IDX(vlan_id);
6018         vid_bit = I40E_VFTA_BIT(vlan_id);
6019
6020         if (on)
6021                 vsi->vfta[vid_idx] |= vid_bit;
6022         else
6023                 vsi->vfta[vid_idx] &= ~vid_bit;
6024 }
6025
6026 static void
6027 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6028                      uint16_t vlan_id, bool on)
6029 {
6030         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6031         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6032         int ret;
6033
6034         if (vlan_id > ETH_VLAN_ID_MAX)
6035                 return;
6036
6037         i40e_store_vlan_filter(vsi, vlan_id, on);
6038
6039         if (!vsi->vlan_anti_spoof_on || !vlan_id)
6040                 return;
6041
6042         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6043
6044         if (on) {
6045                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6046                                        &vlan_data, 1, NULL);
6047                 if (ret != I40E_SUCCESS)
6048                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6049         } else {
6050                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6051                                           &vlan_data, 1, NULL);
6052                 if (ret != I40E_SUCCESS)
6053                         PMD_DRV_LOG(ERR,
6054                                     "Failed to remove vlan filter");
6055         }
6056 }
6057
6058 /**
6059  * Find all vlan options for specific mac addr,
6060  * return with actual vlan found.
6061  */
6062 static inline int
6063 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6064                            struct i40e_macvlan_filter *mv_f,
6065                            int num, struct ether_addr *addr)
6066 {
6067         int i;
6068         uint32_t j, k;
6069
6070         /**
6071          * Not to use i40e_find_vlan_filter to decrease the loop time,
6072          * although the code looks complex.
6073           */
6074         if (num < vsi->vlan_num)
6075                 return I40E_ERR_PARAM;
6076
6077         i = 0;
6078         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6079                 if (vsi->vfta[j]) {
6080                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6081                                 if (vsi->vfta[j] & (1 << k)) {
6082                                         if (i > num - 1) {
6083                                                 PMD_DRV_LOG(ERR,
6084                                                         "vlan number doesn't match");
6085                                                 return I40E_ERR_PARAM;
6086                                         }
6087                                         (void)rte_memcpy(&mv_f[i].macaddr,
6088                                                         addr, ETH_ADDR_LEN);
6089                                         mv_f[i].vlan_id =
6090                                                 j * I40E_UINT32_BIT_SIZE + k;
6091                                         i++;
6092                                 }
6093                         }
6094                 }
6095         }
6096         return I40E_SUCCESS;
6097 }
6098
6099 static inline int
6100 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6101                            struct i40e_macvlan_filter *mv_f,
6102                            int num,
6103                            uint16_t vlan)
6104 {
6105         int i = 0;
6106         struct i40e_mac_filter *f;
6107
6108         if (num < vsi->mac_num)
6109                 return I40E_ERR_PARAM;
6110
6111         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6112                 if (i > num - 1) {
6113                         PMD_DRV_LOG(ERR, "buffer number not match");
6114                         return I40E_ERR_PARAM;
6115                 }
6116                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6117                                 ETH_ADDR_LEN);
6118                 mv_f[i].vlan_id = vlan;
6119                 mv_f[i].filter_type = f->mac_info.filter_type;
6120                 i++;
6121         }
6122
6123         return I40E_SUCCESS;
6124 }
6125
6126 static int
6127 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6128 {
6129         int i, j, num;
6130         struct i40e_mac_filter *f;
6131         struct i40e_macvlan_filter *mv_f;
6132         int ret = I40E_SUCCESS;
6133
6134         if (vsi == NULL || vsi->mac_num == 0)
6135                 return I40E_ERR_PARAM;
6136
6137         /* Case that no vlan is set */
6138         if (vsi->vlan_num == 0)
6139                 num = vsi->mac_num;
6140         else
6141                 num = vsi->mac_num * vsi->vlan_num;
6142
6143         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6144         if (mv_f == NULL) {
6145                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6146                 return I40E_ERR_NO_MEMORY;
6147         }
6148
6149         i = 0;
6150         if (vsi->vlan_num == 0) {
6151                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6152                         (void)rte_memcpy(&mv_f[i].macaddr,
6153                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6154                         mv_f[i].filter_type = f->mac_info.filter_type;
6155                         mv_f[i].vlan_id = 0;
6156                         i++;
6157                 }
6158         } else {
6159                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6160                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6161                                         vsi->vlan_num, &f->mac_info.mac_addr);
6162                         if (ret != I40E_SUCCESS)
6163                                 goto DONE;
6164                         for (j = i; j < i + vsi->vlan_num; j++)
6165                                 mv_f[j].filter_type = f->mac_info.filter_type;
6166                         i += vsi->vlan_num;
6167                 }
6168         }
6169
6170         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6171 DONE:
6172         rte_free(mv_f);
6173
6174         return ret;
6175 }
6176
6177 int
6178 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6179 {
6180         struct i40e_macvlan_filter *mv_f;
6181         int mac_num;
6182         int ret = I40E_SUCCESS;
6183
6184         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6185                 return I40E_ERR_PARAM;
6186
6187         /* If it's already set, just return */
6188         if (i40e_find_vlan_filter(vsi,vlan))
6189                 return I40E_SUCCESS;
6190
6191         mac_num = vsi->mac_num;
6192
6193         if (mac_num == 0) {
6194                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6195                 return I40E_ERR_PARAM;
6196         }
6197
6198         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6199
6200         if (mv_f == NULL) {
6201                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6202                 return I40E_ERR_NO_MEMORY;
6203         }
6204
6205         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6206
6207         if (ret != I40E_SUCCESS)
6208                 goto DONE;
6209
6210         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6211
6212         if (ret != I40E_SUCCESS)
6213                 goto DONE;
6214
6215         i40e_set_vlan_filter(vsi, vlan, 1);
6216
6217         vsi->vlan_num++;
6218         ret = I40E_SUCCESS;
6219 DONE:
6220         rte_free(mv_f);
6221         return ret;
6222 }
6223
6224 int
6225 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6226 {
6227         struct i40e_macvlan_filter *mv_f;
6228         int mac_num;
6229         int ret = I40E_SUCCESS;
6230
6231         /**
6232          * Vlan 0 is the generic filter for untagged packets
6233          * and can't be removed.
6234          */
6235         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6236                 return I40E_ERR_PARAM;
6237
6238         /* If can't find it, just return */
6239         if (!i40e_find_vlan_filter(vsi, vlan))
6240                 return I40E_ERR_PARAM;
6241
6242         mac_num = vsi->mac_num;
6243
6244         if (mac_num == 0) {
6245                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6246                 return I40E_ERR_PARAM;
6247         }
6248
6249         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6250
6251         if (mv_f == NULL) {
6252                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6253                 return I40E_ERR_NO_MEMORY;
6254         }
6255
6256         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6257
6258         if (ret != I40E_SUCCESS)
6259                 goto DONE;
6260
6261         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6262
6263         if (ret != I40E_SUCCESS)
6264                 goto DONE;
6265
6266         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6267         if (vsi->vlan_num == 1) {
6268                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6269                 if (ret != I40E_SUCCESS)
6270                         goto DONE;
6271
6272                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6273                 if (ret != I40E_SUCCESS)
6274                         goto DONE;
6275         }
6276
6277         i40e_set_vlan_filter(vsi, vlan, 0);
6278
6279         vsi->vlan_num--;
6280         ret = I40E_SUCCESS;
6281 DONE:
6282         rte_free(mv_f);
6283         return ret;
6284 }
6285
6286 int
6287 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6288 {
6289         struct i40e_mac_filter *f;
6290         struct i40e_macvlan_filter *mv_f;
6291         int i, vlan_num = 0;
6292         int ret = I40E_SUCCESS;
6293
6294         /* If it's add and we've config it, return */
6295         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6296         if (f != NULL)
6297                 return I40E_SUCCESS;
6298         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6299                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6300
6301                 /**
6302                  * If vlan_num is 0, that's the first time to add mac,
6303                  * set mask for vlan_id 0.
6304                  */
6305                 if (vsi->vlan_num == 0) {
6306                         i40e_set_vlan_filter(vsi, 0, 1);
6307                         vsi->vlan_num = 1;
6308                 }
6309                 vlan_num = vsi->vlan_num;
6310         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6311                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6312                 vlan_num = 1;
6313
6314         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6315         if (mv_f == NULL) {
6316                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6317                 return I40E_ERR_NO_MEMORY;
6318         }
6319
6320         for (i = 0; i < vlan_num; i++) {
6321                 mv_f[i].filter_type = mac_filter->filter_type;
6322                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6323                                 ETH_ADDR_LEN);
6324         }
6325
6326         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6327                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6328                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6329                                         &mac_filter->mac_addr);
6330                 if (ret != I40E_SUCCESS)
6331                         goto DONE;
6332         }
6333
6334         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6335         if (ret != I40E_SUCCESS)
6336                 goto DONE;
6337
6338         /* Add the mac addr into mac list */
6339         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6340         if (f == NULL) {
6341                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6342                 ret = I40E_ERR_NO_MEMORY;
6343                 goto DONE;
6344         }
6345         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6346                         ETH_ADDR_LEN);
6347         f->mac_info.filter_type = mac_filter->filter_type;
6348         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6349         vsi->mac_num++;
6350
6351         ret = I40E_SUCCESS;
6352 DONE:
6353         rte_free(mv_f);
6354
6355         return ret;
6356 }
6357
6358 int
6359 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6360 {
6361         struct i40e_mac_filter *f;
6362         struct i40e_macvlan_filter *mv_f;
6363         int i, vlan_num;
6364         enum rte_mac_filter_type filter_type;
6365         int ret = I40E_SUCCESS;
6366
6367         /* Can't find it, return an error */
6368         f = i40e_find_mac_filter(vsi, addr);
6369         if (f == NULL)
6370                 return I40E_ERR_PARAM;
6371
6372         vlan_num = vsi->vlan_num;
6373         filter_type = f->mac_info.filter_type;
6374         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6375                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6376                 if (vlan_num == 0) {
6377                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6378                         return I40E_ERR_PARAM;
6379                 }
6380         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6381                         filter_type == RTE_MAC_HASH_MATCH)
6382                 vlan_num = 1;
6383
6384         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6385         if (mv_f == NULL) {
6386                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6387                 return I40E_ERR_NO_MEMORY;
6388         }
6389
6390         for (i = 0; i < vlan_num; i++) {
6391                 mv_f[i].filter_type = filter_type;
6392                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6393                                 ETH_ADDR_LEN);
6394         }
6395         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6396                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6397                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6398                 if (ret != I40E_SUCCESS)
6399                         goto DONE;
6400         }
6401
6402         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6403         if (ret != I40E_SUCCESS)
6404                 goto DONE;
6405
6406         /* Remove the mac addr into mac list */
6407         TAILQ_REMOVE(&vsi->mac_list, f, next);
6408         rte_free(f);
6409         vsi->mac_num--;
6410
6411         ret = I40E_SUCCESS;
6412 DONE:
6413         rte_free(mv_f);
6414         return ret;
6415 }
6416
6417 /* Configure hash enable flags for RSS */
6418 uint64_t
6419 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6420 {
6421         uint64_t hena = 0;
6422
6423         if (!flags)
6424                 return hena;
6425
6426         if (flags & ETH_RSS_FRAG_IPV4)
6427                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6428         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6429                 if (type == I40E_MAC_X722) {
6430                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6431                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6432                 } else
6433                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6434         }
6435         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6436                 if (type == I40E_MAC_X722) {
6437                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6438                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6439                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6440                 } else
6441                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6442         }
6443         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6444                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6445         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6446                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6447         if (flags & ETH_RSS_FRAG_IPV6)
6448                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6449         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6450                 if (type == I40E_MAC_X722) {
6451                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6452                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6453                 } else
6454                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6455         }
6456         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6457                 if (type == I40E_MAC_X722) {
6458                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6459                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6460                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6461                 } else
6462                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6463         }
6464         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6465                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6466         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6467                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6468         if (flags & ETH_RSS_L2_PAYLOAD)
6469                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6470
6471         return hena;
6472 }
6473
6474 /* Parse the hash enable flags */
6475 uint64_t
6476 i40e_parse_hena(uint64_t flags)
6477 {
6478         uint64_t rss_hf = 0;
6479
6480         if (!flags)
6481                 return rss_hf;
6482         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6483                 rss_hf |= ETH_RSS_FRAG_IPV4;
6484         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6485                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6486         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6487                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6488         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6489                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6490         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6491                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6492         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6493                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6494         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6495                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6496         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6497                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6498         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6499                 rss_hf |= ETH_RSS_FRAG_IPV6;
6500         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6501                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6502         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6503                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6504         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6505                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6506         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6507                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6508         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6509                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6510         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6511                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6512         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6513                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6514         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6515                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6516
6517         return rss_hf;
6518 }
6519
6520 /* Disable RSS */
6521 static void
6522 i40e_pf_disable_rss(struct i40e_pf *pf)
6523 {
6524         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6525         uint64_t hena;
6526
6527         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6528         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6529         if (hw->mac.type == I40E_MAC_X722)
6530                 hena &= ~I40E_RSS_HENA_ALL_X722;
6531         else
6532                 hena &= ~I40E_RSS_HENA_ALL;
6533         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6534         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6535         I40E_WRITE_FLUSH(hw);
6536 }
6537
6538 static int
6539 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6540 {
6541         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6542         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6543         int ret = 0;
6544
6545         if (!key || key_len == 0) {
6546                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6547                 return 0;
6548         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6549                 sizeof(uint32_t)) {
6550                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6551                 return -EINVAL;
6552         }
6553
6554         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6555                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6556                         (struct i40e_aqc_get_set_rss_key_data *)key;
6557
6558                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6559                 if (ret)
6560                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6561         } else {
6562                 uint32_t *hash_key = (uint32_t *)key;
6563                 uint16_t i;
6564
6565                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6566                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6567                 I40E_WRITE_FLUSH(hw);
6568         }
6569
6570         return ret;
6571 }
6572
6573 static int
6574 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6575 {
6576         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6577         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6578         int ret;
6579
6580         if (!key || !key_len)
6581                 return -EINVAL;
6582
6583         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6584                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6585                         (struct i40e_aqc_get_set_rss_key_data *)key);
6586                 if (ret) {
6587                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6588                         return ret;
6589                 }
6590         } else {
6591                 uint32_t *key_dw = (uint32_t *)key;
6592                 uint16_t i;
6593
6594                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6595                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6596         }
6597         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6598
6599         return 0;
6600 }
6601
6602 static int
6603 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6604 {
6605         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6606         uint64_t rss_hf;
6607         uint64_t hena;
6608         int ret;
6609
6610         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6611                                rss_conf->rss_key_len);
6612         if (ret)
6613                 return ret;
6614
6615         rss_hf = rss_conf->rss_hf;
6616         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6617         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6618         if (hw->mac.type == I40E_MAC_X722)
6619                 hena &= ~I40E_RSS_HENA_ALL_X722;
6620         else
6621                 hena &= ~I40E_RSS_HENA_ALL;
6622         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6623         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6624         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6625         I40E_WRITE_FLUSH(hw);
6626
6627         return 0;
6628 }
6629
6630 static int
6631 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6632                          struct rte_eth_rss_conf *rss_conf)
6633 {
6634         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6635         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6636         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6637         uint64_t hena;
6638
6639         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6640         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6641         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6642                  ? I40E_RSS_HENA_ALL_X722
6643                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6644                 if (rss_hf != 0) /* Enable RSS */
6645                         return -EINVAL;
6646                 return 0; /* Nothing to do */
6647         }
6648         /* RSS enabled */
6649         if (rss_hf == 0) /* Disable RSS */
6650                 return -EINVAL;
6651
6652         return i40e_hw_rss_hash_set(pf, rss_conf);
6653 }
6654
6655 static int
6656 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6657                            struct rte_eth_rss_conf *rss_conf)
6658 {
6659         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6661         uint64_t hena;
6662
6663         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6664                          &rss_conf->rss_key_len);
6665
6666         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6667         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6668         rss_conf->rss_hf = i40e_parse_hena(hena);
6669
6670         return 0;
6671 }
6672
6673 static int
6674 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6675 {
6676         switch (filter_type) {
6677         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6678                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6679                 break;
6680         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6681                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6682                 break;
6683         case RTE_TUNNEL_FILTER_IMAC_TENID:
6684                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6685                 break;
6686         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6687                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6688                 break;
6689         case ETH_TUNNEL_FILTER_IMAC:
6690                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6691                 break;
6692         case ETH_TUNNEL_FILTER_OIP:
6693                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6694                 break;
6695         case ETH_TUNNEL_FILTER_IIP:
6696                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6697                 break;
6698         default:
6699                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6700                 return -EINVAL;
6701         }
6702
6703         return 0;
6704 }
6705
6706 /* Convert tunnel filter structure */
6707 static int
6708 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6709                            *cld_filter,
6710                            struct i40e_tunnel_filter *tunnel_filter)
6711 {
6712         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6713                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6714         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6715                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6716         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6717         if ((rte_le_to_cpu_16(cld_filter->flags) &
6718              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6719             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6720                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6721         else
6722                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6723         tunnel_filter->input.flags = cld_filter->flags;
6724         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6725         tunnel_filter->queue = cld_filter->queue_number;
6726
6727         return 0;
6728 }
6729
6730 /* Check if there exists the tunnel filter */
6731 struct i40e_tunnel_filter *
6732 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6733                              const struct i40e_tunnel_filter_input *input)
6734 {
6735         int ret;
6736
6737         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6738         if (ret < 0)
6739                 return NULL;
6740
6741         return tunnel_rule->hash_map[ret];
6742 }
6743
6744 /* Add a tunnel filter into the SW list */
6745 static int
6746 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6747                              struct i40e_tunnel_filter *tunnel_filter)
6748 {
6749         struct i40e_tunnel_rule *rule = &pf->tunnel;
6750         int ret;
6751
6752         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6753         if (ret < 0) {
6754                 PMD_DRV_LOG(ERR,
6755                             "Failed to insert tunnel filter to hash table %d!",
6756                             ret);
6757                 return ret;
6758         }
6759         rule->hash_map[ret] = tunnel_filter;
6760
6761         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6762
6763         return 0;
6764 }
6765
6766 /* Delete a tunnel filter from the SW list */
6767 int
6768 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6769                           struct i40e_tunnel_filter_input *input)
6770 {
6771         struct i40e_tunnel_rule *rule = &pf->tunnel;
6772         struct i40e_tunnel_filter *tunnel_filter;
6773         int ret;
6774
6775         ret = rte_hash_del_key(rule->hash_table, input);
6776         if (ret < 0) {
6777                 PMD_DRV_LOG(ERR,
6778                             "Failed to delete tunnel filter to hash table %d!",
6779                             ret);
6780                 return ret;
6781         }
6782         tunnel_filter = rule->hash_map[ret];
6783         rule->hash_map[ret] = NULL;
6784
6785         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6786         rte_free(tunnel_filter);
6787
6788         return 0;
6789 }
6790
6791 int
6792 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6793                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6794                         uint8_t add)
6795 {
6796         uint16_t ip_type;
6797         uint32_t ipv4_addr;
6798         uint8_t i, tun_type = 0;
6799         /* internal varialbe to convert ipv6 byte order */
6800         uint32_t convert_ipv6[4];
6801         int val, ret = 0;
6802         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6803         struct i40e_vsi *vsi = pf->main_vsi;
6804         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6805         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6806         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6807         struct i40e_tunnel_filter *tunnel, *node;
6808         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6809
6810         cld_filter = rte_zmalloc("tunnel_filter",
6811                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6812                 0);
6813
6814         if (NULL == cld_filter) {
6815                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6816                 return -EINVAL;
6817         }
6818         pfilter = cld_filter;
6819
6820         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6821         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6822
6823         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6824         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6825                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6826                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6827                 rte_memcpy(&pfilter->ipaddr.v4.data,
6828                                 &rte_cpu_to_le_32(ipv4_addr),
6829                                 sizeof(pfilter->ipaddr.v4.data));
6830         } else {
6831                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6832                 for (i = 0; i < 4; i++) {
6833                         convert_ipv6[i] =
6834                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6835                 }
6836                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6837                                 sizeof(pfilter->ipaddr.v6.data));
6838         }
6839
6840         /* check tunneled type */
6841         switch (tunnel_filter->tunnel_type) {
6842         case RTE_TUNNEL_TYPE_VXLAN:
6843                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6844                 break;
6845         case RTE_TUNNEL_TYPE_NVGRE:
6846                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6847                 break;
6848         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6849                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6850                 break;
6851         default:
6852                 /* Other tunnel types is not supported. */
6853                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6854                 rte_free(cld_filter);
6855                 return -EINVAL;
6856         }
6857
6858         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6859                                                 &pfilter->flags);
6860         if (val < 0) {
6861                 rte_free(cld_filter);
6862                 return -EINVAL;
6863         }
6864
6865         pfilter->flags |= rte_cpu_to_le_16(
6866                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6867                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6868         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6869         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6870
6871         /* Check if there is the filter in SW list */
6872         memset(&check_filter, 0, sizeof(check_filter));
6873         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6874         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6875         if (add && node) {
6876                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6877                 return -EINVAL;
6878         }
6879
6880         if (!add && !node) {
6881                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6882                 return -EINVAL;
6883         }
6884
6885         if (add) {
6886                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6887                 if (ret < 0) {
6888                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6889                         return ret;
6890                 }
6891                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6892                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6893                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6894         } else {
6895                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6896                                                    cld_filter, 1);
6897                 if (ret < 0) {
6898                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6899                         return ret;
6900                 }
6901                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6902         }
6903
6904         rte_free(cld_filter);
6905         return ret;
6906 }
6907
6908 static int
6909 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6910 {
6911         uint8_t i;
6912
6913         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6914                 if (pf->vxlan_ports[i] == port)
6915                         return i;
6916         }
6917
6918         return -1;
6919 }
6920
6921 static int
6922 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6923 {
6924         int  idx, ret;
6925         uint8_t filter_idx;
6926         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6927
6928         idx = i40e_get_vxlan_port_idx(pf, port);
6929
6930         /* Check if port already exists */
6931         if (idx >= 0) {
6932                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6933                 return -EINVAL;
6934         }
6935
6936         /* Now check if there is space to add the new port */
6937         idx = i40e_get_vxlan_port_idx(pf, 0);
6938         if (idx < 0) {
6939                 PMD_DRV_LOG(ERR,
6940                         "Maximum number of UDP ports reached, not adding port %d",
6941                         port);
6942                 return -ENOSPC;
6943         }
6944
6945         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6946                                         &filter_idx, NULL);
6947         if (ret < 0) {
6948                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6949                 return -1;
6950         }
6951
6952         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6953                          port,  filter_idx);
6954
6955         /* New port: add it and mark its index in the bitmap */
6956         pf->vxlan_ports[idx] = port;
6957         pf->vxlan_bitmap |= (1 << idx);
6958
6959         if (!(pf->flags & I40E_FLAG_VXLAN))
6960                 pf->flags |= I40E_FLAG_VXLAN;
6961
6962         return 0;
6963 }
6964
6965 static int
6966 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6967 {
6968         int idx;
6969         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6970
6971         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6972                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6973                 return -EINVAL;
6974         }
6975
6976         idx = i40e_get_vxlan_port_idx(pf, port);
6977
6978         if (idx < 0) {
6979                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6980                 return -EINVAL;
6981         }
6982
6983         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6984                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6985                 return -1;
6986         }
6987
6988         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6989                         port, idx);
6990
6991         pf->vxlan_ports[idx] = 0;
6992         pf->vxlan_bitmap &= ~(1 << idx);
6993
6994         if (!pf->vxlan_bitmap)
6995                 pf->flags &= ~I40E_FLAG_VXLAN;
6996
6997         return 0;
6998 }
6999
7000 /* Add UDP tunneling port */
7001 static int
7002 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7003                              struct rte_eth_udp_tunnel *udp_tunnel)
7004 {
7005         int ret = 0;
7006         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7007
7008         if (udp_tunnel == NULL)
7009                 return -EINVAL;
7010
7011         switch (udp_tunnel->prot_type) {
7012         case RTE_TUNNEL_TYPE_VXLAN:
7013                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7014                 break;
7015
7016         case RTE_TUNNEL_TYPE_GENEVE:
7017         case RTE_TUNNEL_TYPE_TEREDO:
7018                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7019                 ret = -1;
7020                 break;
7021
7022         default:
7023                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7024                 ret = -1;
7025                 break;
7026         }
7027
7028         return ret;
7029 }
7030
7031 /* Remove UDP tunneling port */
7032 static int
7033 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7034                              struct rte_eth_udp_tunnel *udp_tunnel)
7035 {
7036         int ret = 0;
7037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7038
7039         if (udp_tunnel == NULL)
7040                 return -EINVAL;
7041
7042         switch (udp_tunnel->prot_type) {
7043         case RTE_TUNNEL_TYPE_VXLAN:
7044                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7045                 break;
7046         case RTE_TUNNEL_TYPE_GENEVE:
7047         case RTE_TUNNEL_TYPE_TEREDO:
7048                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7049                 ret = -1;
7050                 break;
7051         default:
7052                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7053                 ret = -1;
7054                 break;
7055         }
7056
7057         return ret;
7058 }
7059
7060 /* Calculate the maximum number of contiguous PF queues that are configured */
7061 static int
7062 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7063 {
7064         struct rte_eth_dev_data *data = pf->dev_data;
7065         int i, num;
7066         struct i40e_rx_queue *rxq;
7067
7068         num = 0;
7069         for (i = 0; i < pf->lan_nb_qps; i++) {
7070                 rxq = data->rx_queues[i];
7071                 if (rxq && rxq->q_set)
7072                         num++;
7073                 else
7074                         break;
7075         }
7076
7077         return num;
7078 }
7079
7080 /* Configure RSS */
7081 static int
7082 i40e_pf_config_rss(struct i40e_pf *pf)
7083 {
7084         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7085         struct rte_eth_rss_conf rss_conf;
7086         uint32_t i, lut = 0;
7087         uint16_t j, num;
7088
7089         /*
7090          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7091          * It's necessary to calulate the actual PF queues that are configured.
7092          */
7093         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7094                 num = i40e_pf_calc_configured_queues_num(pf);
7095         else
7096                 num = pf->dev_data->nb_rx_queues;
7097
7098         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7099         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7100                         num);
7101
7102         if (num == 0) {
7103                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7104                 return -ENOTSUP;
7105         }
7106
7107         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7108                 if (j == num)
7109                         j = 0;
7110                 lut = (lut << 8) | (j & ((0x1 <<
7111                         hw->func_caps.rss_table_entry_width) - 1));
7112                 if ((i & 3) == 3)
7113                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7114         }
7115
7116         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7117         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7118                 i40e_pf_disable_rss(pf);
7119                 return 0;
7120         }
7121         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7122                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7123                 /* Random default keys */
7124                 static uint32_t rss_key_default[] = {0x6b793944,
7125                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7126                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7127                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7128
7129                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7130                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7131                                                         sizeof(uint32_t);
7132         }
7133
7134         return i40e_hw_rss_hash_set(pf, &rss_conf);
7135 }
7136
7137 static int
7138 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7139                                struct rte_eth_tunnel_filter_conf *filter)
7140 {
7141         if (pf == NULL || filter == NULL) {
7142                 PMD_DRV_LOG(ERR, "Invalid parameter");
7143                 return -EINVAL;
7144         }
7145
7146         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7147                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7148                 return -EINVAL;
7149         }
7150
7151         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7152                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7153                 return -EINVAL;
7154         }
7155
7156         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7157                 (is_zero_ether_addr(&filter->outer_mac))) {
7158                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7159                 return -EINVAL;
7160         }
7161
7162         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7163                 (is_zero_ether_addr(&filter->inner_mac))) {
7164                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7165                 return -EINVAL;
7166         }
7167
7168         return 0;
7169 }
7170
7171 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7172 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7173 static int
7174 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7175 {
7176         uint32_t val, reg;
7177         int ret = -EINVAL;
7178
7179         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7180         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7181
7182         if (len == 3) {
7183                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7184         } else if (len == 4) {
7185                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7186         } else {
7187                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7188                 return ret;
7189         }
7190
7191         if (reg != val) {
7192                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7193                                                    reg, NULL);
7194                 if (ret != 0)
7195                         return ret;
7196         } else {
7197                 ret = 0;
7198         }
7199         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7200                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7201
7202         return ret;
7203 }
7204
7205 static int
7206 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7207 {
7208         int ret = -EINVAL;
7209
7210         if (!hw || !cfg)
7211                 return -EINVAL;
7212
7213         switch (cfg->cfg_type) {
7214         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7215                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7216                 break;
7217         default:
7218                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7219                 break;
7220         }
7221
7222         return ret;
7223 }
7224
7225 static int
7226 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7227                                enum rte_filter_op filter_op,
7228                                void *arg)
7229 {
7230         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7231         int ret = I40E_ERR_PARAM;
7232
7233         switch (filter_op) {
7234         case RTE_ETH_FILTER_SET:
7235                 ret = i40e_dev_global_config_set(hw,
7236                         (struct rte_eth_global_cfg *)arg);
7237                 break;
7238         default:
7239                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7240                 break;
7241         }
7242
7243         return ret;
7244 }
7245
7246 static int
7247 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7248                           enum rte_filter_op filter_op,
7249                           void *arg)
7250 {
7251         struct rte_eth_tunnel_filter_conf *filter;
7252         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7253         int ret = I40E_SUCCESS;
7254
7255         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7256
7257         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7258                 return I40E_ERR_PARAM;
7259
7260         switch (filter_op) {
7261         case RTE_ETH_FILTER_NOP:
7262                 if (!(pf->flags & I40E_FLAG_VXLAN))
7263                         ret = I40E_NOT_SUPPORTED;
7264                 break;
7265         case RTE_ETH_FILTER_ADD:
7266                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7267                 break;
7268         case RTE_ETH_FILTER_DELETE:
7269                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7270                 break;
7271         default:
7272                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7273                 ret = I40E_ERR_PARAM;
7274                 break;
7275         }
7276
7277         return ret;
7278 }
7279
7280 static int
7281 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7282 {
7283         int ret = 0;
7284         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7285
7286         /* RSS setup */
7287         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7288                 ret = i40e_pf_config_rss(pf);
7289         else
7290                 i40e_pf_disable_rss(pf);
7291
7292         return ret;
7293 }
7294
7295 /* Get the symmetric hash enable configurations per port */
7296 static void
7297 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7298 {
7299         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7300
7301         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7302 }
7303
7304 /* Set the symmetric hash enable configurations per port */
7305 static void
7306 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7307 {
7308         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7309
7310         if (enable > 0) {
7311                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7312                         PMD_DRV_LOG(INFO,
7313                                 "Symmetric hash has already been enabled");
7314                         return;
7315                 }
7316                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7317         } else {
7318                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7319                         PMD_DRV_LOG(INFO,
7320                                 "Symmetric hash has already been disabled");
7321                         return;
7322                 }
7323                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7324         }
7325         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7326         I40E_WRITE_FLUSH(hw);
7327 }
7328
7329 /*
7330  * Get global configurations of hash function type and symmetric hash enable
7331  * per flow type (pctype). Note that global configuration means it affects all
7332  * the ports on the same NIC.
7333  */
7334 static int
7335 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7336                                    struct rte_eth_hash_global_conf *g_cfg)
7337 {
7338         uint32_t reg, mask = I40E_FLOW_TYPES;
7339         uint16_t i;
7340         enum i40e_filter_pctype pctype;
7341
7342         memset(g_cfg, 0, sizeof(*g_cfg));
7343         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7344         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7345                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7346         else
7347                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7348         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7349                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7350
7351         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7352                 if (!(mask & (1UL << i)))
7353                         continue;
7354                 mask &= ~(1UL << i);
7355                 /* Bit set indicats the coresponding flow type is supported */
7356                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7357                 /* if flowtype is invalid, continue */
7358                 if (!I40E_VALID_FLOW(i))
7359                         continue;
7360                 pctype = i40e_flowtype_to_pctype(i);
7361                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7362                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7363                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7364         }
7365
7366         return 0;
7367 }
7368
7369 static int
7370 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7371 {
7372         uint32_t i;
7373         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7374
7375         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7376                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7377                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7378                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7379                                                 g_cfg->hash_func);
7380                 return -EINVAL;
7381         }
7382
7383         /*
7384          * As i40e supports less than 32 flow types, only first 32 bits need to
7385          * be checked.
7386          */
7387         mask0 = g_cfg->valid_bit_mask[0];
7388         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7389                 if (i == 0) {
7390                         /* Check if any unsupported flow type configured */
7391                         if ((mask0 | i40e_mask) ^ i40e_mask)
7392                                 goto mask_err;
7393                 } else {
7394                         if (g_cfg->valid_bit_mask[i])
7395                                 goto mask_err;
7396                 }
7397         }
7398
7399         return 0;
7400
7401 mask_err:
7402         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7403
7404         return -EINVAL;
7405 }
7406
7407 /*
7408  * Set global configurations of hash function type and symmetric hash enable
7409  * per flow type (pctype). Note any modifying global configuration will affect
7410  * all the ports on the same NIC.
7411  */
7412 static int
7413 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7414                                    struct rte_eth_hash_global_conf *g_cfg)
7415 {
7416         int ret;
7417         uint16_t i;
7418         uint32_t reg;
7419         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7420         enum i40e_filter_pctype pctype;
7421
7422         /* Check the input parameters */
7423         ret = i40e_hash_global_config_check(g_cfg);
7424         if (ret < 0)
7425                 return ret;
7426
7427         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7428                 if (!(mask0 & (1UL << i)))
7429                         continue;
7430                 mask0 &= ~(1UL << i);
7431                 /* if flowtype is invalid, continue */
7432                 if (!I40E_VALID_FLOW(i))
7433                         continue;
7434                 pctype = i40e_flowtype_to_pctype(i);
7435                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7436                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7437                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7438         }
7439
7440         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7441         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7442                 /* Toeplitz */
7443                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7444                         PMD_DRV_LOG(DEBUG,
7445                                 "Hash function already set to Toeplitz");
7446                         goto out;
7447                 }
7448                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7449         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7450                 /* Simple XOR */
7451                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7452                         PMD_DRV_LOG(DEBUG,
7453                                 "Hash function already set to Simple XOR");
7454                         goto out;
7455                 }
7456                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7457         } else
7458                 /* Use the default, and keep it as it is */
7459                 goto out;
7460
7461         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7462
7463 out:
7464         I40E_WRITE_FLUSH(hw);
7465
7466         return 0;
7467 }
7468
7469 /**
7470  * Valid input sets for hash and flow director filters per PCTYPE
7471  */
7472 static uint64_t
7473 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7474                 enum rte_filter_type filter)
7475 {
7476         uint64_t valid;
7477
7478         static const uint64_t valid_hash_inset_table[] = {
7479                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7480                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7481                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7482                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7483                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7484                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7485                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7486                         I40E_INSET_FLEX_PAYLOAD,
7487                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7488                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7489                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7490                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7491                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7492                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7493                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7494                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7495                         I40E_INSET_FLEX_PAYLOAD,
7496                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7497                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7498                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7499                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7500                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7501                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7502                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7503                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7504                         I40E_INSET_FLEX_PAYLOAD,
7505                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7506                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7507                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7508                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7509                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7510                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7511                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7512                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7513                         I40E_INSET_FLEX_PAYLOAD,
7514                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7515                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7516                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7517                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7518                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7519                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7520                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7521                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7522                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7523                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7524                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7525                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7526                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7527                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7528                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7529                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7530                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7531                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7532                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7533                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7534                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7535                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7536                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7537                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7538                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7539                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7540                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7541                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7542                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7543                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7544                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7545                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7546                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7547                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7548                         I40E_INSET_FLEX_PAYLOAD,
7549                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7550                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7551                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7552                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7553                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7554                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7555                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7556                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7557                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7558                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7559                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7560                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7561                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7562                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7563                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7564                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7565                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7566                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7567                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7568                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7569                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7570                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7571                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7572                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7573                         I40E_INSET_FLEX_PAYLOAD,
7574                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7575                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7576                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7577                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7578                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7579                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7580                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7581                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7582                         I40E_INSET_FLEX_PAYLOAD,
7583                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7584                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7585                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7586                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7587                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7588                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7589                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7590                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7591                         I40E_INSET_FLEX_PAYLOAD,
7592                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7593                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7594                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7595                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7596                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7597                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7598                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7599                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7600                         I40E_INSET_FLEX_PAYLOAD,
7601                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7602                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7603                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7604                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7605                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7606                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7607                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7608                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7609                         I40E_INSET_FLEX_PAYLOAD,
7610                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7611                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7612                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7613                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7614                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7615                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7616                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7617                         I40E_INSET_FLEX_PAYLOAD,
7618                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7619                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7620                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7621                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7622                         I40E_INSET_FLEX_PAYLOAD,
7623         };
7624
7625         /**
7626          * Flow director supports only fields defined in
7627          * union rte_eth_fdir_flow.
7628          */
7629         static const uint64_t valid_fdir_inset_table[] = {
7630                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7631                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7632                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7633                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7634                 I40E_INSET_IPV4_TTL,
7635                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7636                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7637                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7638                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7639                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7640                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7641                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7642                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7643                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7644                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7645                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7646                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7647                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7648                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7649                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7650                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7651                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7652                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7653                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7654                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7655                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7656                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7657                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7658                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7659                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7660                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7661                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7662                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7663                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7664                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7665                 I40E_INSET_SCTP_VT,
7666                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7667                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7668                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7669                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7670                 I40E_INSET_IPV4_TTL,
7671                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7672                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7673                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7674                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7675                 I40E_INSET_IPV6_HOP_LIMIT,
7676                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7677                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7678                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7679                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7680                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7681                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7682                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7683                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7684                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7685                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7686                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7687                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7688                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7689                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7690                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7691                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7692                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7693                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7694                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7695                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7696                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7697                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7698                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7699                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7700                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7701                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7702                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7703                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7704                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7705                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7706                 I40E_INSET_SCTP_VT,
7707                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7708                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7709                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7710                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7711                 I40E_INSET_IPV6_HOP_LIMIT,
7712                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7713                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7714                 I40E_INSET_LAST_ETHER_TYPE,
7715         };
7716
7717         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7718                 return 0;
7719         if (filter == RTE_ETH_FILTER_HASH)
7720                 valid = valid_hash_inset_table[pctype];
7721         else
7722                 valid = valid_fdir_inset_table[pctype];
7723
7724         return valid;
7725 }
7726
7727 /**
7728  * Validate if the input set is allowed for a specific PCTYPE
7729  */
7730 static int
7731 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7732                 enum rte_filter_type filter, uint64_t inset)
7733 {
7734         uint64_t valid;
7735
7736         valid = i40e_get_valid_input_set(pctype, filter);
7737         if (inset & (~valid))
7738                 return -EINVAL;
7739
7740         return 0;
7741 }
7742
7743 /* default input set fields combination per pctype */
7744 uint64_t
7745 i40e_get_default_input_set(uint16_t pctype)
7746 {
7747         static const uint64_t default_inset_table[] = {
7748                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7749                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7750                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7751                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7752                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7753                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7754                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7755                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7756                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7757                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7758                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7759                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7760                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7761                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7762                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7763                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7764                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7765                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7766                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7767                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7768                         I40E_INSET_SCTP_VT,
7769                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7770                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7771                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7772                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7773                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7774                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7775                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7776                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7777                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7778                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7779                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7780                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7781                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7782                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7783                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7784                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7785                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7786                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7787                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7788                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7789                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7790                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7791                         I40E_INSET_SCTP_VT,
7792                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7793                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7794                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7795                         I40E_INSET_LAST_ETHER_TYPE,
7796         };
7797
7798         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7799                 return 0;
7800
7801         return default_inset_table[pctype];
7802 }
7803
7804 /**
7805  * Parse the input set from index to logical bit masks
7806  */
7807 static int
7808 i40e_parse_input_set(uint64_t *inset,
7809                      enum i40e_filter_pctype pctype,
7810                      enum rte_eth_input_set_field *field,
7811                      uint16_t size)
7812 {
7813         uint16_t i, j;
7814         int ret = -EINVAL;
7815
7816         static const struct {
7817                 enum rte_eth_input_set_field field;
7818                 uint64_t inset;
7819         } inset_convert_table[] = {
7820                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7821                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7822                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7823                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7824                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7825                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7826                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7827                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7828                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7829                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7830                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7831                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7832                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7833                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7834                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7835                         I40E_INSET_IPV6_NEXT_HDR},
7836                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7837                         I40E_INSET_IPV6_HOP_LIMIT},
7838                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7839                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7840                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7841                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7842                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7843                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7844                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7845                         I40E_INSET_SCTP_VT},
7846                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7847                         I40E_INSET_TUNNEL_DMAC},
7848                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7849                         I40E_INSET_VLAN_TUNNEL},
7850                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7851                         I40E_INSET_TUNNEL_ID},
7852                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7853                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7854                         I40E_INSET_FLEX_PAYLOAD_W1},
7855                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7856                         I40E_INSET_FLEX_PAYLOAD_W2},
7857                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7858                         I40E_INSET_FLEX_PAYLOAD_W3},
7859                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7860                         I40E_INSET_FLEX_PAYLOAD_W4},
7861                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7862                         I40E_INSET_FLEX_PAYLOAD_W5},
7863                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7864                         I40E_INSET_FLEX_PAYLOAD_W6},
7865                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7866                         I40E_INSET_FLEX_PAYLOAD_W7},
7867                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7868                         I40E_INSET_FLEX_PAYLOAD_W8},
7869         };
7870
7871         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7872                 return ret;
7873
7874         /* Only one item allowed for default or all */
7875         if (size == 1) {
7876                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7877                         *inset = i40e_get_default_input_set(pctype);
7878                         return 0;
7879                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7880                         *inset = I40E_INSET_NONE;
7881                         return 0;
7882                 }
7883         }
7884
7885         for (i = 0, *inset = 0; i < size; i++) {
7886                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7887                         if (field[i] == inset_convert_table[j].field) {
7888                                 *inset |= inset_convert_table[j].inset;
7889                                 break;
7890                         }
7891                 }
7892
7893                 /* It contains unsupported input set, return immediately */
7894                 if (j == RTE_DIM(inset_convert_table))
7895                         return ret;
7896         }
7897
7898         return 0;
7899 }
7900
7901 /**
7902  * Translate the input set from bit masks to register aware bit masks
7903  * and vice versa
7904  */
7905 static uint64_t
7906 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7907 {
7908         uint64_t val = 0;
7909         uint16_t i;
7910
7911         struct inset_map {
7912                 uint64_t inset;
7913                 uint64_t inset_reg;
7914         };
7915
7916         static const struct inset_map inset_map_common[] = {
7917                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7918                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7919                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7920                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7921                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7922                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7923                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7924                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7925                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7926                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7927                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7928                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7929                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7930                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7931                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7932                 {I40E_INSET_TUNNEL_DMAC,
7933                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7934                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7935                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7936                 {I40E_INSET_TUNNEL_SRC_PORT,
7937                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7938                 {I40E_INSET_TUNNEL_DST_PORT,
7939                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7940                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7941                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7942                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7943                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7944                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7945                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7946                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7947                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7948                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7949         };
7950
7951     /* some different registers map in x722*/
7952         static const struct inset_map inset_map_diff_x722[] = {
7953                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7954                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7955                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7956                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7957         };
7958
7959         static const struct inset_map inset_map_diff_not_x722[] = {
7960                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7961                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7962                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7963                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7964         };
7965
7966         if (input == 0)
7967                 return val;
7968
7969         /* Translate input set to register aware inset */
7970         if (type == I40E_MAC_X722) {
7971                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7972                         if (input & inset_map_diff_x722[i].inset)
7973                                 val |= inset_map_diff_x722[i].inset_reg;
7974                 }
7975         } else {
7976                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7977                         if (input & inset_map_diff_not_x722[i].inset)
7978                                 val |= inset_map_diff_not_x722[i].inset_reg;
7979                 }
7980         }
7981
7982         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7983                 if (input & inset_map_common[i].inset)
7984                         val |= inset_map_common[i].inset_reg;
7985         }
7986
7987         return val;
7988 }
7989
7990 static int
7991 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7992 {
7993         uint8_t i, idx = 0;
7994         uint64_t inset_need_mask = inset;
7995
7996         static const struct {
7997                 uint64_t inset;
7998                 uint32_t mask;
7999         } inset_mask_map[] = {
8000                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8001                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8002                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8003                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8004                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8005                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8006                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8007                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8008         };
8009
8010         if (!inset || !mask || !nb_elem)
8011                 return 0;
8012
8013         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8014                 /* Clear the inset bit, if no MASK is required,
8015                  * for example proto + ttl
8016                  */
8017                 if ((inset & inset_mask_map[i].inset) ==
8018                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8019                         inset_need_mask &= ~inset_mask_map[i].inset;
8020                 if (!inset_need_mask)
8021                         return 0;
8022         }
8023         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8024                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8025                     inset_mask_map[i].inset) {
8026                         if (idx >= nb_elem) {
8027                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8028                                 return -EINVAL;
8029                         }
8030                         mask[idx] = inset_mask_map[i].mask;
8031                         idx++;
8032                 }
8033         }
8034
8035         return idx;
8036 }
8037
8038 static void
8039 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8040 {
8041         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8042
8043         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8044         if (reg != val)
8045                 i40e_write_rx_ctl(hw, addr, val);
8046         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8047                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8048 }
8049
8050 static void
8051 i40e_filter_input_set_init(struct i40e_pf *pf)
8052 {
8053         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8054         enum i40e_filter_pctype pctype;
8055         uint64_t input_set, inset_reg;
8056         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8057         int num, i;
8058
8059         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8060              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8061                 if (hw->mac.type == I40E_MAC_X722) {
8062                         if (!I40E_VALID_PCTYPE_X722(pctype))
8063                                 continue;
8064                 } else {
8065                         if (!I40E_VALID_PCTYPE(pctype))
8066                                 continue;
8067                 }
8068
8069                 input_set = i40e_get_default_input_set(pctype);
8070
8071                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8072                                                    I40E_INSET_MASK_NUM_REG);
8073                 if (num < 0)
8074                         return;
8075                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8076                                         input_set);
8077
8078                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8079                                       (uint32_t)(inset_reg & UINT32_MAX));
8080                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8081                                      (uint32_t)((inset_reg >>
8082                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8083                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8084                                       (uint32_t)(inset_reg & UINT32_MAX));
8085                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8086                                      (uint32_t)((inset_reg >>
8087                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8088
8089                 for (i = 0; i < num; i++) {
8090                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8091                                              mask_reg[i]);
8092                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8093                                              mask_reg[i]);
8094                 }
8095                 /*clear unused mask registers of the pctype */
8096                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8097                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8098                                              0);
8099                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8100                                              0);
8101                 }
8102                 I40E_WRITE_FLUSH(hw);
8103
8104                 /* store the default input set */
8105                 pf->hash_input_set[pctype] = input_set;
8106                 pf->fdir.input_set[pctype] = input_set;
8107         }
8108 }
8109
8110 int
8111 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8112                          struct rte_eth_input_set_conf *conf)
8113 {
8114         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8115         enum i40e_filter_pctype pctype;
8116         uint64_t input_set, inset_reg = 0;
8117         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8118         int ret, i, num;
8119
8120         if (!conf) {
8121                 PMD_DRV_LOG(ERR, "Invalid pointer");
8122                 return -EFAULT;
8123         }
8124         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8125             conf->op != RTE_ETH_INPUT_SET_ADD) {
8126                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8127                 return -EINVAL;
8128         }
8129
8130         if (!I40E_VALID_FLOW(conf->flow_type)) {
8131                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8132                 return -EINVAL;
8133         }
8134
8135         if (hw->mac.type == I40E_MAC_X722) {
8136                 /* get translated pctype value in fd pctype register */
8137                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8138                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8139                         conf->flow_type)));
8140         } else
8141                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8142
8143         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8144                                    conf->inset_size);
8145         if (ret) {
8146                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8147                 return -EINVAL;
8148         }
8149         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8150                                     input_set) != 0) {
8151                 PMD_DRV_LOG(ERR, "Invalid input set");
8152                 return -EINVAL;
8153         }
8154         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8155                 /* get inset value in register */
8156                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8157                 inset_reg <<= I40E_32_BIT_WIDTH;
8158                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8159                 input_set |= pf->hash_input_set[pctype];
8160         }
8161         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8162                                            I40E_INSET_MASK_NUM_REG);
8163         if (num < 0)
8164                 return -EINVAL;
8165
8166         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8167
8168         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8169                               (uint32_t)(inset_reg & UINT32_MAX));
8170         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8171                              (uint32_t)((inset_reg >>
8172                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8173
8174         for (i = 0; i < num; i++)
8175                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8176                                      mask_reg[i]);
8177         /*clear unused mask registers of the pctype */
8178         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8179                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8180                                      0);
8181         I40E_WRITE_FLUSH(hw);
8182
8183         pf->hash_input_set[pctype] = input_set;
8184         return 0;
8185 }
8186
8187 int
8188 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8189                          struct rte_eth_input_set_conf *conf)
8190 {
8191         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8192         enum i40e_filter_pctype pctype;
8193         uint64_t input_set, inset_reg = 0;
8194         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8195         int ret, i, num;
8196
8197         if (!hw || !conf) {
8198                 PMD_DRV_LOG(ERR, "Invalid pointer");
8199                 return -EFAULT;
8200         }
8201         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8202             conf->op != RTE_ETH_INPUT_SET_ADD) {
8203                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8204                 return -EINVAL;
8205         }
8206
8207         if (!I40E_VALID_FLOW(conf->flow_type)) {
8208                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8209                 return -EINVAL;
8210         }
8211
8212         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8213
8214         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8215                                    conf->inset_size);
8216         if (ret) {
8217                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8218                 return -EINVAL;
8219         }
8220         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8221                                     input_set) != 0) {
8222                 PMD_DRV_LOG(ERR, "Invalid input set");
8223                 return -EINVAL;
8224         }
8225
8226         /* get inset value in register */
8227         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8228         inset_reg <<= I40E_32_BIT_WIDTH;
8229         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8230
8231         /* Can not change the inset reg for flex payload for fdir,
8232          * it is done by writing I40E_PRTQF_FD_FLXINSET
8233          * in i40e_set_flex_mask_on_pctype.
8234          */
8235         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8236                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8237         else
8238                 input_set |= pf->fdir.input_set[pctype];
8239         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8240                                            I40E_INSET_MASK_NUM_REG);
8241         if (num < 0)
8242                 return -EINVAL;
8243
8244         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8245
8246         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8247                               (uint32_t)(inset_reg & UINT32_MAX));
8248         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8249                              (uint32_t)((inset_reg >>
8250                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8251
8252         for (i = 0; i < num; i++)
8253                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8254                                      mask_reg[i]);
8255         /*clear unused mask registers of the pctype */
8256         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8257                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8258                                      0);
8259         I40E_WRITE_FLUSH(hw);
8260
8261         pf->fdir.input_set[pctype] = input_set;
8262         return 0;
8263 }
8264
8265 static int
8266 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8267 {
8268         int ret = 0;
8269
8270         if (!hw || !info) {
8271                 PMD_DRV_LOG(ERR, "Invalid pointer");
8272                 return -EFAULT;
8273         }
8274
8275         switch (info->info_type) {
8276         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8277                 i40e_get_symmetric_hash_enable_per_port(hw,
8278                                         &(info->info.enable));
8279                 break;
8280         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8281                 ret = i40e_get_hash_filter_global_config(hw,
8282                                 &(info->info.global_conf));
8283                 break;
8284         default:
8285                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8286                                                         info->info_type);
8287                 ret = -EINVAL;
8288                 break;
8289         }
8290
8291         return ret;
8292 }
8293
8294 static int
8295 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8296 {
8297         int ret = 0;
8298
8299         if (!hw || !info) {
8300                 PMD_DRV_LOG(ERR, "Invalid pointer");
8301                 return -EFAULT;
8302         }
8303
8304         switch (info->info_type) {
8305         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8306                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8307                 break;
8308         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8309                 ret = i40e_set_hash_filter_global_config(hw,
8310                                 &(info->info.global_conf));
8311                 break;
8312         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8313                 ret = i40e_hash_filter_inset_select(hw,
8314                                                &(info->info.input_set_conf));
8315                 break;
8316
8317         default:
8318                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8319                                                         info->info_type);
8320                 ret = -EINVAL;
8321                 break;
8322         }
8323
8324         return ret;
8325 }
8326
8327 /* Operations for hash function */
8328 static int
8329 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8330                       enum rte_filter_op filter_op,
8331                       void *arg)
8332 {
8333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8334         int ret = 0;
8335
8336         switch (filter_op) {
8337         case RTE_ETH_FILTER_NOP:
8338                 break;
8339         case RTE_ETH_FILTER_GET:
8340                 ret = i40e_hash_filter_get(hw,
8341                         (struct rte_eth_hash_filter_info *)arg);
8342                 break;
8343         case RTE_ETH_FILTER_SET:
8344                 ret = i40e_hash_filter_set(hw,
8345                         (struct rte_eth_hash_filter_info *)arg);
8346                 break;
8347         default:
8348                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8349                                                                 filter_op);
8350                 ret = -ENOTSUP;
8351                 break;
8352         }
8353
8354         return ret;
8355 }
8356
8357 /* Convert ethertype filter structure */
8358 static int
8359 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8360                               struct i40e_ethertype_filter *filter)
8361 {
8362         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8363         filter->input.ether_type = input->ether_type;
8364         filter->flags = input->flags;
8365         filter->queue = input->queue;
8366
8367         return 0;
8368 }
8369
8370 /* Check if there exists the ehtertype filter */
8371 struct i40e_ethertype_filter *
8372 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8373                                 const struct i40e_ethertype_filter_input *input)
8374 {
8375         int ret;
8376
8377         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8378         if (ret < 0)
8379                 return NULL;
8380
8381         return ethertype_rule->hash_map[ret];
8382 }
8383
8384 /* Add ethertype filter in SW list */
8385 static int
8386 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8387                                 struct i40e_ethertype_filter *filter)
8388 {
8389         struct i40e_ethertype_rule *rule = &pf->ethertype;
8390         int ret;
8391
8392         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8393         if (ret < 0) {
8394                 PMD_DRV_LOG(ERR,
8395                             "Failed to insert ethertype filter"
8396                             " to hash table %d!",
8397                             ret);
8398                 return ret;
8399         }
8400         rule->hash_map[ret] = filter;
8401
8402         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8403
8404         return 0;
8405 }
8406
8407 /* Delete ethertype filter in SW list */
8408 int
8409 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8410                              struct i40e_ethertype_filter_input *input)
8411 {
8412         struct i40e_ethertype_rule *rule = &pf->ethertype;
8413         struct i40e_ethertype_filter *filter;
8414         int ret;
8415
8416         ret = rte_hash_del_key(rule->hash_table, input);
8417         if (ret < 0) {
8418                 PMD_DRV_LOG(ERR,
8419                             "Failed to delete ethertype filter"
8420                             " to hash table %d!",
8421                             ret);
8422                 return ret;
8423         }
8424         filter = rule->hash_map[ret];
8425         rule->hash_map[ret] = NULL;
8426
8427         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8428         rte_free(filter);
8429
8430         return 0;
8431 }
8432
8433 /*
8434  * Configure ethertype filter, which can director packet by filtering
8435  * with mac address and ether_type or only ether_type
8436  */
8437 int
8438 i40e_ethertype_filter_set(struct i40e_pf *pf,
8439                         struct rte_eth_ethertype_filter *filter,
8440                         bool add)
8441 {
8442         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8443         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8444         struct i40e_ethertype_filter *ethertype_filter, *node;
8445         struct i40e_ethertype_filter check_filter;
8446         struct i40e_control_filter_stats stats;
8447         uint16_t flags = 0;
8448         int ret;
8449
8450         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8451                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8452                 return -EINVAL;
8453         }
8454         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8455                 filter->ether_type == ETHER_TYPE_IPv6) {
8456                 PMD_DRV_LOG(ERR,
8457                         "unsupported ether_type(0x%04x) in control packet filter.",
8458                         filter->ether_type);
8459                 return -EINVAL;
8460         }
8461         if (filter->ether_type == ETHER_TYPE_VLAN)
8462                 PMD_DRV_LOG(WARNING,
8463                         "filter vlan ether_type in first tag is not supported.");
8464
8465         /* Check if there is the filter in SW list */
8466         memset(&check_filter, 0, sizeof(check_filter));
8467         i40e_ethertype_filter_convert(filter, &check_filter);
8468         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8469                                                &check_filter.input);
8470         if (add && node) {
8471                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8472                 return -EINVAL;
8473         }
8474
8475         if (!add && !node) {
8476                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8477                 return -EINVAL;
8478         }
8479
8480         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8481                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8482         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8483                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8484         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8485
8486         memset(&stats, 0, sizeof(stats));
8487         ret = i40e_aq_add_rem_control_packet_filter(hw,
8488                         filter->mac_addr.addr_bytes,
8489                         filter->ether_type, flags,
8490                         pf->main_vsi->seid,
8491                         filter->queue, add, &stats, NULL);
8492
8493         PMD_DRV_LOG(INFO,
8494                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8495                 ret, stats.mac_etype_used, stats.etype_used,
8496                 stats.mac_etype_free, stats.etype_free);
8497         if (ret < 0)
8498                 return -ENOSYS;
8499
8500         /* Add or delete a filter in SW list */
8501         if (add) {
8502                 ethertype_filter = rte_zmalloc("ethertype_filter",
8503                                        sizeof(*ethertype_filter), 0);
8504                 rte_memcpy(ethertype_filter, &check_filter,
8505                            sizeof(check_filter));
8506                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8507         } else {
8508                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8509         }
8510
8511         return ret;
8512 }
8513
8514 /*
8515  * Handle operations for ethertype filter.
8516  */
8517 static int
8518 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8519                                 enum rte_filter_op filter_op,
8520                                 void *arg)
8521 {
8522         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8523         int ret = 0;
8524
8525         if (filter_op == RTE_ETH_FILTER_NOP)
8526                 return ret;
8527
8528         if (arg == NULL) {
8529                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8530                             filter_op);
8531                 return -EINVAL;
8532         }
8533
8534         switch (filter_op) {
8535         case RTE_ETH_FILTER_ADD:
8536                 ret = i40e_ethertype_filter_set(pf,
8537                         (struct rte_eth_ethertype_filter *)arg,
8538                         TRUE);
8539                 break;
8540         case RTE_ETH_FILTER_DELETE:
8541                 ret = i40e_ethertype_filter_set(pf,
8542                         (struct rte_eth_ethertype_filter *)arg,
8543                         FALSE);
8544                 break;
8545         default:
8546                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8547                 ret = -ENOSYS;
8548                 break;
8549         }
8550         return ret;
8551 }
8552
8553 static int
8554 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8555                      enum rte_filter_type filter_type,
8556                      enum rte_filter_op filter_op,
8557                      void *arg)
8558 {
8559         int ret = 0;
8560
8561         if (dev == NULL)
8562                 return -EINVAL;
8563
8564         switch (filter_type) {
8565         case RTE_ETH_FILTER_NONE:
8566                 /* For global configuration */
8567                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8568                 break;
8569         case RTE_ETH_FILTER_HASH:
8570                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8571                 break;
8572         case RTE_ETH_FILTER_MACVLAN:
8573                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8574                 break;
8575         case RTE_ETH_FILTER_ETHERTYPE:
8576                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8577                 break;
8578         case RTE_ETH_FILTER_TUNNEL:
8579                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8580                 break;
8581         case RTE_ETH_FILTER_FDIR:
8582                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8583                 break;
8584         case RTE_ETH_FILTER_GENERIC:
8585                 if (filter_op != RTE_ETH_FILTER_GET)
8586                         return -EINVAL;
8587                 *(const void **)arg = &i40e_flow_ops;
8588                 break;
8589         default:
8590                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8591                                                         filter_type);
8592                 ret = -EINVAL;
8593                 break;
8594         }
8595
8596         return ret;
8597 }
8598
8599 /*
8600  * Check and enable Extended Tag.
8601  * Enabling Extended Tag is important for 40G performance.
8602  */
8603 static void
8604 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8605 {
8606         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8607         uint32_t buf = 0;
8608         int ret;
8609
8610         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8611                                       PCI_DEV_CAP_REG);
8612         if (ret < 0) {
8613                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8614                             PCI_DEV_CAP_REG);
8615                 return;
8616         }
8617         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8618                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8619                 return;
8620         }
8621
8622         buf = 0;
8623         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8624                                       PCI_DEV_CTRL_REG);
8625         if (ret < 0) {
8626                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8627                             PCI_DEV_CTRL_REG);
8628                 return;
8629         }
8630         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8631                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8632                 return;
8633         }
8634         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8635         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8636                                        PCI_DEV_CTRL_REG);
8637         if (ret < 0) {
8638                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8639                             PCI_DEV_CTRL_REG);
8640                 return;
8641         }
8642 }
8643
8644 /*
8645  * As some registers wouldn't be reset unless a global hardware reset,
8646  * hardware initialization is needed to put those registers into an
8647  * expected initial state.
8648  */
8649 static void
8650 i40e_hw_init(struct rte_eth_dev *dev)
8651 {
8652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8653
8654         i40e_enable_extended_tag(dev);
8655
8656         /* clear the PF Queue Filter control register */
8657         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8658
8659         /* Disable symmetric hash per port */
8660         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8661 }
8662
8663 enum i40e_filter_pctype
8664 i40e_flowtype_to_pctype(uint16_t flow_type)
8665 {
8666         static const enum i40e_filter_pctype pctype_table[] = {
8667                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8668                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8669                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8670                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8671                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8672                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8673                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8674                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8675                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8676                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8677                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8678                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8679                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8680                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8681                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8682                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8683                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8684                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8685                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8686         };
8687
8688         return pctype_table[flow_type];
8689 }
8690
8691 uint16_t
8692 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8693 {
8694         static const uint16_t flowtype_table[] = {
8695                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8696                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8697                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8698                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8699                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8700                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8701                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8702                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8703                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8704                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8705                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8706                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8707                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8708                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8709                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8710                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8711                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8712                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8713                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8714                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8715                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8716                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8717                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8718                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8719                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8720                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8721                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8722                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8723                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8724                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8725                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8726         };
8727
8728         return flowtype_table[pctype];
8729 }
8730
8731 /*
8732  * On X710, performance number is far from the expectation on recent firmware
8733  * versions; on XL710, performance number is also far from the expectation on
8734  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8735  * mode is enabled and port MAC address is equal to the packet destination MAC
8736  * address. The fix for this issue may not be integrated in the following
8737  * firmware version. So the workaround in software driver is needed. It needs
8738  * to modify the initial values of 3 internal only registers for both X710 and
8739  * XL710. Note that the values for X710 or XL710 could be different, and the
8740  * workaround can be removed when it is fixed in firmware in the future.
8741  */
8742
8743 /* For both X710 and XL710 */
8744 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8745 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8746
8747 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8748 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8749
8750 /* For X722 */
8751 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8752 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8753
8754 /* For X710 */
8755 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8756 /* For XL710 */
8757 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8758 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8759
8760 static int
8761 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8762 {
8763         enum i40e_status_code status;
8764         struct i40e_aq_get_phy_abilities_resp phy_ab;
8765         int ret = -ENOTSUP;
8766
8767         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8768                                               NULL);
8769
8770         if (status)
8771                 return ret;
8772
8773         return 0;
8774 }
8775
8776 static void
8777 i40e_configure_registers(struct i40e_hw *hw)
8778 {
8779         static struct {
8780                 uint32_t addr;
8781                 uint64_t val;
8782         } reg_table[] = {
8783                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8784                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8785                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8786         };
8787         uint64_t reg;
8788         uint32_t i;
8789         int ret;
8790
8791         for (i = 0; i < RTE_DIM(reg_table); i++) {
8792                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8793                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8794                                 reg_table[i].val =
8795                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8796                         else /* For X710/XL710/XXV710 */
8797                                 reg_table[i].val =
8798                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8799                 }
8800
8801                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8802                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8803                                 reg_table[i].val =
8804                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8805                         else /* For X710/XL710/XXV710 */
8806                                 reg_table[i].val =
8807                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8808                 }
8809
8810                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8811                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8812                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8813                                 reg_table[i].val =
8814                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8815                         else /* For X710 */
8816                                 reg_table[i].val =
8817                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8818                 }
8819
8820                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8821                                                         &reg, NULL);
8822                 if (ret < 0) {
8823                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8824                                                         reg_table[i].addr);
8825                         break;
8826                 }
8827                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8828                                                 reg_table[i].addr, reg);
8829                 if (reg == reg_table[i].val)
8830                         continue;
8831
8832                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8833                                                 reg_table[i].val, NULL);
8834                 if (ret < 0) {
8835                         PMD_DRV_LOG(ERR,
8836                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8837                                 reg_table[i].val, reg_table[i].addr);
8838                         break;
8839                 }
8840                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8841                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8842         }
8843 }
8844
8845 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8846 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8847 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8848 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8849 static int
8850 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8851 {
8852         uint32_t reg;
8853         int ret;
8854
8855         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8856                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8857                 return -EINVAL;
8858         }
8859
8860         /* Configure for double VLAN RX stripping */
8861         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8862         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8863                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8864                 ret = i40e_aq_debug_write_register(hw,
8865                                                    I40E_VSI_TSR(vsi->vsi_id),
8866                                                    reg, NULL);
8867                 if (ret < 0) {
8868                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8869                                     vsi->vsi_id);
8870                         return I40E_ERR_CONFIG;
8871                 }
8872         }
8873
8874         /* Configure for double VLAN TX insertion */
8875         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8876         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8877                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8878                 ret = i40e_aq_debug_write_register(hw,
8879                                                    I40E_VSI_L2TAGSTXVALID(
8880                                                    vsi->vsi_id), reg, NULL);
8881                 if (ret < 0) {
8882                         PMD_DRV_LOG(ERR,
8883                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
8884                                 vsi->vsi_id);
8885                         return I40E_ERR_CONFIG;
8886                 }
8887         }
8888
8889         return 0;
8890 }
8891
8892 /**
8893  * i40e_aq_add_mirror_rule
8894  * @hw: pointer to the hardware structure
8895  * @seid: VEB seid to add mirror rule to
8896  * @dst_id: destination vsi seid
8897  * @entries: Buffer which contains the entities to be mirrored
8898  * @count: number of entities contained in the buffer
8899  * @rule_id:the rule_id of the rule to be added
8900  *
8901  * Add a mirror rule for a given veb.
8902  *
8903  **/
8904 static enum i40e_status_code
8905 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8906                         uint16_t seid, uint16_t dst_id,
8907                         uint16_t rule_type, uint16_t *entries,
8908                         uint16_t count, uint16_t *rule_id)
8909 {
8910         struct i40e_aq_desc desc;
8911         struct i40e_aqc_add_delete_mirror_rule cmd;
8912         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8913                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8914                 &desc.params.raw;
8915         uint16_t buff_len;
8916         enum i40e_status_code status;
8917
8918         i40e_fill_default_direct_cmd_desc(&desc,
8919                                           i40e_aqc_opc_add_mirror_rule);
8920         memset(&cmd, 0, sizeof(cmd));
8921
8922         buff_len = sizeof(uint16_t) * count;
8923         desc.datalen = rte_cpu_to_le_16(buff_len);
8924         if (buff_len > 0)
8925                 desc.flags |= rte_cpu_to_le_16(
8926                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8927         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8928                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8929         cmd.num_entries = rte_cpu_to_le_16(count);
8930         cmd.seid = rte_cpu_to_le_16(seid);
8931         cmd.destination = rte_cpu_to_le_16(dst_id);
8932
8933         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8934         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8935         PMD_DRV_LOG(INFO,
8936                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8937                 hw->aq.asq_last_status, resp->rule_id,
8938                 resp->mirror_rules_used, resp->mirror_rules_free);
8939         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8940
8941         return status;
8942 }
8943
8944 /**
8945  * i40e_aq_del_mirror_rule
8946  * @hw: pointer to the hardware structure
8947  * @seid: VEB seid to add mirror rule to
8948  * @entries: Buffer which contains the entities to be mirrored
8949  * @count: number of entities contained in the buffer
8950  * @rule_id:the rule_id of the rule to be delete
8951  *
8952  * Delete a mirror rule for a given veb.
8953  *
8954  **/
8955 static enum i40e_status_code
8956 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8957                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8958                 uint16_t count, uint16_t rule_id)
8959 {
8960         struct i40e_aq_desc desc;
8961         struct i40e_aqc_add_delete_mirror_rule cmd;
8962         uint16_t buff_len = 0;
8963         enum i40e_status_code status;
8964         void *buff = NULL;
8965
8966         i40e_fill_default_direct_cmd_desc(&desc,
8967                                           i40e_aqc_opc_delete_mirror_rule);
8968         memset(&cmd, 0, sizeof(cmd));
8969         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8970                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8971                                                           I40E_AQ_FLAG_RD));
8972                 cmd.num_entries = count;
8973                 buff_len = sizeof(uint16_t) * count;
8974                 desc.datalen = rte_cpu_to_le_16(buff_len);
8975                 buff = (void *)entries;
8976         } else
8977                 /* rule id is filled in destination field for deleting mirror rule */
8978                 cmd.destination = rte_cpu_to_le_16(rule_id);
8979
8980         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8981                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8982         cmd.seid = rte_cpu_to_le_16(seid);
8983
8984         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8985         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8986
8987         return status;
8988 }
8989
8990 /**
8991  * i40e_mirror_rule_set
8992  * @dev: pointer to the hardware structure
8993  * @mirror_conf: mirror rule info
8994  * @sw_id: mirror rule's sw_id
8995  * @on: enable/disable
8996  *
8997  * set a mirror rule.
8998  *
8999  **/
9000 static int
9001 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9002                         struct rte_eth_mirror_conf *mirror_conf,
9003                         uint8_t sw_id, uint8_t on)
9004 {
9005         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9006         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9007         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9008         struct i40e_mirror_rule *parent = NULL;
9009         uint16_t seid, dst_seid, rule_id;
9010         uint16_t i, j = 0;
9011         int ret;
9012
9013         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9014
9015         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9016                 PMD_DRV_LOG(ERR,
9017                         "mirror rule can not be configured without veb or vfs.");
9018                 return -ENOSYS;
9019         }
9020         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9021                 PMD_DRV_LOG(ERR, "mirror table is full.");
9022                 return -ENOSPC;
9023         }
9024         if (mirror_conf->dst_pool > pf->vf_num) {
9025                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9026                                  mirror_conf->dst_pool);
9027                 return -EINVAL;
9028         }
9029
9030         seid = pf->main_vsi->veb->seid;
9031
9032         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9033                 if (sw_id <= it->index) {
9034                         mirr_rule = it;
9035                         break;
9036                 }
9037                 parent = it;
9038         }
9039         if (mirr_rule && sw_id == mirr_rule->index) {
9040                 if (on) {
9041                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9042                         return -EEXIST;
9043                 } else {
9044                         ret = i40e_aq_del_mirror_rule(hw, seid,
9045                                         mirr_rule->rule_type,
9046                                         mirr_rule->entries,
9047                                         mirr_rule->num_entries, mirr_rule->id);
9048                         if (ret < 0) {
9049                                 PMD_DRV_LOG(ERR,
9050                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9051                                         ret, hw->aq.asq_last_status);
9052                                 return -ENOSYS;
9053                         }
9054                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9055                         rte_free(mirr_rule);
9056                         pf->nb_mirror_rule--;
9057                         return 0;
9058                 }
9059         } else if (!on) {
9060                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9061                 return -ENOENT;
9062         }
9063
9064         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9065                                 sizeof(struct i40e_mirror_rule) , 0);
9066         if (!mirr_rule) {
9067                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9068                 return I40E_ERR_NO_MEMORY;
9069         }
9070         switch (mirror_conf->rule_type) {
9071         case ETH_MIRROR_VLAN:
9072                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9073                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9074                                 mirr_rule->entries[j] =
9075                                         mirror_conf->vlan.vlan_id[i];
9076                                 j++;
9077                         }
9078                 }
9079                 if (j == 0) {
9080                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9081                         rte_free(mirr_rule);
9082                         return -EINVAL;
9083                 }
9084                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9085                 break;
9086         case ETH_MIRROR_VIRTUAL_POOL_UP:
9087         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9088                 /* check if the specified pool bit is out of range */
9089                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9090                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9091                         rte_free(mirr_rule);
9092                         return -EINVAL;
9093                 }
9094                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9095                         if (mirror_conf->pool_mask & (1ULL << i)) {
9096                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9097                                 j++;
9098                         }
9099                 }
9100                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9101                         /* add pf vsi to entries */
9102                         mirr_rule->entries[j] = pf->main_vsi_seid;
9103                         j++;
9104                 }
9105                 if (j == 0) {
9106                         PMD_DRV_LOG(ERR, "pool is not specified.");
9107                         rte_free(mirr_rule);
9108                         return -EINVAL;
9109                 }
9110                 /* egress and ingress in aq commands means from switch but not port */
9111                 mirr_rule->rule_type =
9112                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9113                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9114                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9115                 break;
9116         case ETH_MIRROR_UPLINK_PORT:
9117                 /* egress and ingress in aq commands means from switch but not port*/
9118                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9119                 break;
9120         case ETH_MIRROR_DOWNLINK_PORT:
9121                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9122                 break;
9123         default:
9124                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9125                         mirror_conf->rule_type);
9126                 rte_free(mirr_rule);
9127                 return -EINVAL;
9128         }
9129
9130         /* If the dst_pool is equal to vf_num, consider it as PF */
9131         if (mirror_conf->dst_pool == pf->vf_num)
9132                 dst_seid = pf->main_vsi_seid;
9133         else
9134                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9135
9136         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9137                                       mirr_rule->rule_type, mirr_rule->entries,
9138                                       j, &rule_id);
9139         if (ret < 0) {
9140                 PMD_DRV_LOG(ERR,
9141                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9142                         ret, hw->aq.asq_last_status);
9143                 rte_free(mirr_rule);
9144                 return -ENOSYS;
9145         }
9146
9147         mirr_rule->index = sw_id;
9148         mirr_rule->num_entries = j;
9149         mirr_rule->id = rule_id;
9150         mirr_rule->dst_vsi_seid = dst_seid;
9151
9152         if (parent)
9153                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9154         else
9155                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9156
9157         pf->nb_mirror_rule++;
9158         return 0;
9159 }
9160
9161 /**
9162  * i40e_mirror_rule_reset
9163  * @dev: pointer to the device
9164  * @sw_id: mirror rule's sw_id
9165  *
9166  * reset a mirror rule.
9167  *
9168  **/
9169 static int
9170 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9171 {
9172         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9173         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9174         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9175         uint16_t seid;
9176         int ret;
9177
9178         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9179
9180         seid = pf->main_vsi->veb->seid;
9181
9182         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9183                 if (sw_id == it->index) {
9184                         mirr_rule = it;
9185                         break;
9186                 }
9187         }
9188         if (mirr_rule) {
9189                 ret = i40e_aq_del_mirror_rule(hw, seid,
9190                                 mirr_rule->rule_type,
9191                                 mirr_rule->entries,
9192                                 mirr_rule->num_entries, mirr_rule->id);
9193                 if (ret < 0) {
9194                         PMD_DRV_LOG(ERR,
9195                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9196                                 ret, hw->aq.asq_last_status);
9197                         return -ENOSYS;
9198                 }
9199                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9200                 rte_free(mirr_rule);
9201                 pf->nb_mirror_rule--;
9202         } else {
9203                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9204                 return -ENOENT;
9205         }
9206         return 0;
9207 }
9208
9209 static uint64_t
9210 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9211 {
9212         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9213         uint64_t systim_cycles;
9214
9215         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9216         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9217                         << 32;
9218
9219         return systim_cycles;
9220 }
9221
9222 static uint64_t
9223 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9224 {
9225         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9226         uint64_t rx_tstamp;
9227
9228         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9229         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9230                         << 32;
9231
9232         return rx_tstamp;
9233 }
9234
9235 static uint64_t
9236 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9237 {
9238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9239         uint64_t tx_tstamp;
9240
9241         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9242         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9243                         << 32;
9244
9245         return tx_tstamp;
9246 }
9247
9248 static void
9249 i40e_start_timecounters(struct rte_eth_dev *dev)
9250 {
9251         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9252         struct i40e_adapter *adapter =
9253                         (struct i40e_adapter *)dev->data->dev_private;
9254         struct rte_eth_link link;
9255         uint32_t tsync_inc_l;
9256         uint32_t tsync_inc_h;
9257
9258         /* Get current link speed. */
9259         memset(&link, 0, sizeof(link));
9260         i40e_dev_link_update(dev, 1);
9261         rte_i40e_dev_atomic_read_link_status(dev, &link);
9262
9263         switch (link.link_speed) {
9264         case ETH_SPEED_NUM_40G:
9265                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9266                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9267                 break;
9268         case ETH_SPEED_NUM_10G:
9269                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9270                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9271                 break;
9272         case ETH_SPEED_NUM_1G:
9273                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9274                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9275                 break;
9276         default:
9277                 tsync_inc_l = 0x0;
9278                 tsync_inc_h = 0x0;
9279         }
9280
9281         /* Set the timesync increment value. */
9282         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9283         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9284
9285         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9286         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9287         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9288
9289         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9290         adapter->systime_tc.cc_shift = 0;
9291         adapter->systime_tc.nsec_mask = 0;
9292
9293         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9294         adapter->rx_tstamp_tc.cc_shift = 0;
9295         adapter->rx_tstamp_tc.nsec_mask = 0;
9296
9297         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9298         adapter->tx_tstamp_tc.cc_shift = 0;
9299         adapter->tx_tstamp_tc.nsec_mask = 0;
9300 }
9301
9302 static int
9303 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9304 {
9305         struct i40e_adapter *adapter =
9306                         (struct i40e_adapter *)dev->data->dev_private;
9307
9308         adapter->systime_tc.nsec += delta;
9309         adapter->rx_tstamp_tc.nsec += delta;
9310         adapter->tx_tstamp_tc.nsec += delta;
9311
9312         return 0;
9313 }
9314
9315 static int
9316 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9317 {
9318         uint64_t ns;
9319         struct i40e_adapter *adapter =
9320                         (struct i40e_adapter *)dev->data->dev_private;
9321
9322         ns = rte_timespec_to_ns(ts);
9323
9324         /* Set the timecounters to a new value. */
9325         adapter->systime_tc.nsec = ns;
9326         adapter->rx_tstamp_tc.nsec = ns;
9327         adapter->tx_tstamp_tc.nsec = ns;
9328
9329         return 0;
9330 }
9331
9332 static int
9333 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9334 {
9335         uint64_t ns, systime_cycles;
9336         struct i40e_adapter *adapter =
9337                         (struct i40e_adapter *)dev->data->dev_private;
9338
9339         systime_cycles = i40e_read_systime_cyclecounter(dev);
9340         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9341         *ts = rte_ns_to_timespec(ns);
9342
9343         return 0;
9344 }
9345
9346 static int
9347 i40e_timesync_enable(struct rte_eth_dev *dev)
9348 {
9349         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9350         uint32_t tsync_ctl_l;
9351         uint32_t tsync_ctl_h;
9352
9353         /* Stop the timesync system time. */
9354         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9355         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9356         /* Reset the timesync system time value. */
9357         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9358         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9359
9360         i40e_start_timecounters(dev);
9361
9362         /* Clear timesync registers. */
9363         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9364         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9365         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9366         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9367         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9368         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9369
9370         /* Enable timestamping of PTP packets. */
9371         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9372         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9373
9374         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9375         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9376         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9377
9378         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9379         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9380
9381         return 0;
9382 }
9383
9384 static int
9385 i40e_timesync_disable(struct rte_eth_dev *dev)
9386 {
9387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9388         uint32_t tsync_ctl_l;
9389         uint32_t tsync_ctl_h;
9390
9391         /* Disable timestamping of transmitted PTP packets. */
9392         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9393         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9394
9395         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9396         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9397
9398         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9399         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9400
9401         /* Reset the timesync increment value. */
9402         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9403         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9404
9405         return 0;
9406 }
9407
9408 static int
9409 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9410                                 struct timespec *timestamp, uint32_t flags)
9411 {
9412         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9413         struct i40e_adapter *adapter =
9414                 (struct i40e_adapter *)dev->data->dev_private;
9415
9416         uint32_t sync_status;
9417         uint32_t index = flags & 0x03;
9418         uint64_t rx_tstamp_cycles;
9419         uint64_t ns;
9420
9421         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9422         if ((sync_status & (1 << index)) == 0)
9423                 return -EINVAL;
9424
9425         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9426         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9427         *timestamp = rte_ns_to_timespec(ns);
9428
9429         return 0;
9430 }
9431
9432 static int
9433 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9434                                 struct timespec *timestamp)
9435 {
9436         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9437         struct i40e_adapter *adapter =
9438                 (struct i40e_adapter *)dev->data->dev_private;
9439
9440         uint32_t sync_status;
9441         uint64_t tx_tstamp_cycles;
9442         uint64_t ns;
9443
9444         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9445         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9446                 return -EINVAL;
9447
9448         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9449         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9450         *timestamp = rte_ns_to_timespec(ns);
9451
9452         return 0;
9453 }
9454
9455 /*
9456  * i40e_parse_dcb_configure - parse dcb configure from user
9457  * @dev: the device being configured
9458  * @dcb_cfg: pointer of the result of parse
9459  * @*tc_map: bit map of enabled traffic classes
9460  *
9461  * Returns 0 on success, negative value on failure
9462  */
9463 static int
9464 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9465                          struct i40e_dcbx_config *dcb_cfg,
9466                          uint8_t *tc_map)
9467 {
9468         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9469         uint8_t i, tc_bw, bw_lf;
9470
9471         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9472
9473         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9474         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9475                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9476                 return -EINVAL;
9477         }
9478
9479         /* assume each tc has the same bw */
9480         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9481         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9482                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9483         /* to ensure the sum of tcbw is equal to 100 */
9484         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9485         for (i = 0; i < bw_lf; i++)
9486                 dcb_cfg->etscfg.tcbwtable[i]++;
9487
9488         /* assume each tc has the same Transmission Selection Algorithm */
9489         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9490                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9491
9492         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9493                 dcb_cfg->etscfg.prioritytable[i] =
9494                                 dcb_rx_conf->dcb_tc[i];
9495
9496         /* FW needs one App to configure HW */
9497         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9498         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9499         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9500         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9501
9502         if (dcb_rx_conf->nb_tcs == 0)
9503                 *tc_map = 1; /* tc0 only */
9504         else
9505                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9506
9507         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9508                 dcb_cfg->pfc.willing = 0;
9509                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9510                 dcb_cfg->pfc.pfcenable = *tc_map;
9511         }
9512         return 0;
9513 }
9514
9515
9516 static enum i40e_status_code
9517 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9518                               struct i40e_aqc_vsi_properties_data *info,
9519                               uint8_t enabled_tcmap)
9520 {
9521         enum i40e_status_code ret;
9522         int i, total_tc = 0;
9523         uint16_t qpnum_per_tc, bsf, qp_idx;
9524         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9525         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9526         uint16_t used_queues;
9527
9528         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9529         if (ret != I40E_SUCCESS)
9530                 return ret;
9531
9532         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9533                 if (enabled_tcmap & (1 << i))
9534                         total_tc++;
9535         }
9536         if (total_tc == 0)
9537                 total_tc = 1;
9538         vsi->enabled_tc = enabled_tcmap;
9539
9540         /* different VSI has different queues assigned */
9541         if (vsi->type == I40E_VSI_MAIN)
9542                 used_queues = dev_data->nb_rx_queues -
9543                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9544         else if (vsi->type == I40E_VSI_VMDQ2)
9545                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9546         else {
9547                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9548                 return I40E_ERR_NO_AVAILABLE_VSI;
9549         }
9550
9551         qpnum_per_tc = used_queues / total_tc;
9552         /* Number of queues per enabled TC */
9553         if (qpnum_per_tc == 0) {
9554                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9555                 return I40E_ERR_INVALID_QP_ID;
9556         }
9557         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9558                                 I40E_MAX_Q_PER_TC);
9559         bsf = rte_bsf32(qpnum_per_tc);
9560
9561         /**
9562          * Configure TC and queue mapping parameters, for enabled TC,
9563          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9564          * default queue will serve it.
9565          */
9566         qp_idx = 0;
9567         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9568                 if (vsi->enabled_tc & (1 << i)) {
9569                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9570                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9571                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9572                         qp_idx += qpnum_per_tc;
9573                 } else
9574                         info->tc_mapping[i] = 0;
9575         }
9576
9577         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9578         if (vsi->type == I40E_VSI_SRIOV) {
9579                 info->mapping_flags |=
9580                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9581                 for (i = 0; i < vsi->nb_qps; i++)
9582                         info->queue_mapping[i] =
9583                                 rte_cpu_to_le_16(vsi->base_queue + i);
9584         } else {
9585                 info->mapping_flags |=
9586                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9587                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9588         }
9589         info->valid_sections |=
9590                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9591
9592         return I40E_SUCCESS;
9593 }
9594
9595 /*
9596  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9597  * @veb: VEB to be configured
9598  * @tc_map: enabled TC bitmap
9599  *
9600  * Returns 0 on success, negative value on failure
9601  */
9602 static enum i40e_status_code
9603 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9604 {
9605         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9606         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9607         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9608         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9609         enum i40e_status_code ret = I40E_SUCCESS;
9610         int i;
9611         uint32_t bw_max;
9612
9613         /* Check if enabled_tc is same as existing or new TCs */
9614         if (veb->enabled_tc == tc_map)
9615                 return ret;
9616
9617         /* configure tc bandwidth */
9618         memset(&veb_bw, 0, sizeof(veb_bw));
9619         veb_bw.tc_valid_bits = tc_map;
9620         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9621         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9622                 if (tc_map & BIT_ULL(i))
9623                         veb_bw.tc_bw_share_credits[i] = 1;
9624         }
9625         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9626                                                    &veb_bw, NULL);
9627         if (ret) {
9628                 PMD_INIT_LOG(ERR,
9629                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9630                         hw->aq.asq_last_status);
9631                 return ret;
9632         }
9633
9634         memset(&ets_query, 0, sizeof(ets_query));
9635         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9636                                                    &ets_query, NULL);
9637         if (ret != I40E_SUCCESS) {
9638                 PMD_DRV_LOG(ERR,
9639                         "Failed to get switch_comp ETS configuration %u",
9640                         hw->aq.asq_last_status);
9641                 return ret;
9642         }
9643         memset(&bw_query, 0, sizeof(bw_query));
9644         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9645                                                   &bw_query, NULL);
9646         if (ret != I40E_SUCCESS) {
9647                 PMD_DRV_LOG(ERR,
9648                         "Failed to get switch_comp bandwidth configuration %u",
9649                         hw->aq.asq_last_status);
9650                 return ret;
9651         }
9652
9653         /* store and print out BW info */
9654         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9655         veb->bw_info.bw_max = ets_query.tc_bw_max;
9656         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9657         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9658         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9659                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9660                      I40E_16_BIT_WIDTH);
9661         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9662                 veb->bw_info.bw_ets_share_credits[i] =
9663                                 bw_query.tc_bw_share_credits[i];
9664                 veb->bw_info.bw_ets_credits[i] =
9665                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9666                 /* 4 bits per TC, 4th bit is reserved */
9667                 veb->bw_info.bw_ets_max[i] =
9668                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9669                                   RTE_LEN2MASK(3, uint8_t));
9670                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9671                             veb->bw_info.bw_ets_share_credits[i]);
9672                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9673                             veb->bw_info.bw_ets_credits[i]);
9674                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9675                             veb->bw_info.bw_ets_max[i]);
9676         }
9677
9678         veb->enabled_tc = tc_map;
9679
9680         return ret;
9681 }
9682
9683
9684 /*
9685  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9686  * @vsi: VSI to be configured
9687  * @tc_map: enabled TC bitmap
9688  *
9689  * Returns 0 on success, negative value on failure
9690  */
9691 static enum i40e_status_code
9692 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9693 {
9694         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9695         struct i40e_vsi_context ctxt;
9696         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9697         enum i40e_status_code ret = I40E_SUCCESS;
9698         int i;
9699
9700         /* Check if enabled_tc is same as existing or new TCs */
9701         if (vsi->enabled_tc == tc_map)
9702                 return ret;
9703
9704         /* configure tc bandwidth */
9705         memset(&bw_data, 0, sizeof(bw_data));
9706         bw_data.tc_valid_bits = tc_map;
9707         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9708         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9709                 if (tc_map & BIT_ULL(i))
9710                         bw_data.tc_bw_credits[i] = 1;
9711         }
9712         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9713         if (ret) {
9714                 PMD_INIT_LOG(ERR,
9715                         "AQ command Config VSI BW allocation per TC failed = %d",
9716                         hw->aq.asq_last_status);
9717                 goto out;
9718         }
9719         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9720                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9721
9722         /* Update Queue Pairs Mapping for currently enabled UPs */
9723         ctxt.seid = vsi->seid;
9724         ctxt.pf_num = hw->pf_id;
9725         ctxt.vf_num = 0;
9726         ctxt.uplink_seid = vsi->uplink_seid;
9727         ctxt.info = vsi->info;
9728         i40e_get_cap(hw);
9729         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9730         if (ret)
9731                 goto out;
9732
9733         /* Update the VSI after updating the VSI queue-mapping information */
9734         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9735         if (ret) {
9736                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9737                         hw->aq.asq_last_status);
9738                 goto out;
9739         }
9740         /* update the local VSI info with updated queue map */
9741         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9742                                         sizeof(vsi->info.tc_mapping));
9743         (void)rte_memcpy(&vsi->info.queue_mapping,
9744                         &ctxt.info.queue_mapping,
9745                 sizeof(vsi->info.queue_mapping));
9746         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9747         vsi->info.valid_sections = 0;
9748
9749         /* query and update current VSI BW information */
9750         ret = i40e_vsi_get_bw_config(vsi);
9751         if (ret) {
9752                 PMD_INIT_LOG(ERR,
9753                          "Failed updating vsi bw info, err %s aq_err %s",
9754                          i40e_stat_str(hw, ret),
9755                          i40e_aq_str(hw, hw->aq.asq_last_status));
9756                 goto out;
9757         }
9758
9759         vsi->enabled_tc = tc_map;
9760
9761 out:
9762         return ret;
9763 }
9764
9765 /*
9766  * i40e_dcb_hw_configure - program the dcb setting to hw
9767  * @pf: pf the configuration is taken on
9768  * @new_cfg: new configuration
9769  * @tc_map: enabled TC bitmap
9770  *
9771  * Returns 0 on success, negative value on failure
9772  */
9773 static enum i40e_status_code
9774 i40e_dcb_hw_configure(struct i40e_pf *pf,
9775                       struct i40e_dcbx_config *new_cfg,
9776                       uint8_t tc_map)
9777 {
9778         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9779         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9780         struct i40e_vsi *main_vsi = pf->main_vsi;
9781         struct i40e_vsi_list *vsi_list;
9782         enum i40e_status_code ret;
9783         int i;
9784         uint32_t val;
9785
9786         /* Use the FW API if FW > v4.4*/
9787         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9788               (hw->aq.fw_maj_ver >= 5))) {
9789                 PMD_INIT_LOG(ERR,
9790                         "FW < v4.4, can not use FW LLDP API to configure DCB");
9791                 return I40E_ERR_FIRMWARE_API_VERSION;
9792         }
9793
9794         /* Check if need reconfiguration */
9795         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9796                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9797                 return I40E_SUCCESS;
9798         }
9799
9800         /* Copy the new config to the current config */
9801         *old_cfg = *new_cfg;
9802         old_cfg->etsrec = old_cfg->etscfg;
9803         ret = i40e_set_dcb_config(hw);
9804         if (ret) {
9805                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
9806                          i40e_stat_str(hw, ret),
9807                          i40e_aq_str(hw, hw->aq.asq_last_status));
9808                 return ret;
9809         }
9810         /* set receive Arbiter to RR mode and ETS scheme by default */
9811         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9812                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9813                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9814                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9815                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9816                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9817                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9818                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9819                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9820                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9821                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9822                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9823                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9824         }
9825         /* get local mib to check whether it is configured correctly */
9826         /* IEEE mode */
9827         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9828         /* Get Local DCB Config */
9829         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9830                                      &hw->local_dcbx_config);
9831
9832         /* if Veb is created, need to update TC of it at first */
9833         if (main_vsi->veb) {
9834                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9835                 if (ret)
9836                         PMD_INIT_LOG(WARNING,
9837                                  "Failed configuring TC for VEB seid=%d",
9838                                  main_vsi->veb->seid);
9839         }
9840         /* Update each VSI */
9841         i40e_vsi_config_tc(main_vsi, tc_map);
9842         if (main_vsi->veb) {
9843                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9844                         /* Beside main VSI and VMDQ VSIs, only enable default
9845                          * TC for other VSIs
9846                          */
9847                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9848                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9849                                                          tc_map);
9850                         else
9851                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9852                                                          I40E_DEFAULT_TCMAP);
9853                         if (ret)
9854                                 PMD_INIT_LOG(WARNING,
9855                                         "Failed configuring TC for VSI seid=%d",
9856                                         vsi_list->vsi->seid);
9857                         /* continue */
9858                 }
9859         }
9860         return I40E_SUCCESS;
9861 }
9862
9863 /*
9864  * i40e_dcb_init_configure - initial dcb config
9865  * @dev: device being configured
9866  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9867  *
9868  * Returns 0 on success, negative value on failure
9869  */
9870 static int
9871 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9872 {
9873         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9874         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9875         int ret = 0;
9876
9877         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9878                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9879                 return -ENOTSUP;
9880         }
9881
9882         /* DCB initialization:
9883          * Update DCB configuration from the Firmware and configure
9884          * LLDP MIB change event.
9885          */
9886         if (sw_dcb == TRUE) {
9887                 ret = i40e_init_dcb(hw);
9888                 /* If lldp agent is stopped, the return value from
9889                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9890                  * adminq status. Otherwise, it should return success.
9891                  */
9892                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9893                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9894                         memset(&hw->local_dcbx_config, 0,
9895                                 sizeof(struct i40e_dcbx_config));
9896                         /* set dcb default configuration */
9897                         hw->local_dcbx_config.etscfg.willing = 0;
9898                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9899                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9900                         hw->local_dcbx_config.etscfg.tsatable[0] =
9901                                                 I40E_IEEE_TSA_ETS;
9902                         hw->local_dcbx_config.etsrec =
9903                                 hw->local_dcbx_config.etscfg;
9904                         hw->local_dcbx_config.pfc.willing = 0;
9905                         hw->local_dcbx_config.pfc.pfccap =
9906                                                 I40E_MAX_TRAFFIC_CLASS;
9907                         /* FW needs one App to configure HW */
9908                         hw->local_dcbx_config.numapps = 1;
9909                         hw->local_dcbx_config.app[0].selector =
9910                                                 I40E_APP_SEL_ETHTYPE;
9911                         hw->local_dcbx_config.app[0].priority = 3;
9912                         hw->local_dcbx_config.app[0].protocolid =
9913                                                 I40E_APP_PROTOID_FCOE;
9914                         ret = i40e_set_dcb_config(hw);
9915                         if (ret) {
9916                                 PMD_INIT_LOG(ERR,
9917                                         "default dcb config fails. err = %d, aq_err = %d.",
9918                                         ret, hw->aq.asq_last_status);
9919                                 return -ENOSYS;
9920                         }
9921                 } else {
9922                         PMD_INIT_LOG(ERR,
9923                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9924                                 ret, hw->aq.asq_last_status);
9925                         return -ENOTSUP;
9926                 }
9927         } else {
9928                 ret = i40e_aq_start_lldp(hw, NULL);
9929                 if (ret != I40E_SUCCESS)
9930                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9931
9932                 ret = i40e_init_dcb(hw);
9933                 if (!ret) {
9934                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9935                                 PMD_INIT_LOG(ERR,
9936                                         "HW doesn't support DCBX offload.");
9937                                 return -ENOTSUP;
9938                         }
9939                 } else {
9940                         PMD_INIT_LOG(ERR,
9941                                 "DCBX configuration failed, err = %d, aq_err = %d.",
9942                                 ret, hw->aq.asq_last_status);
9943                         return -ENOTSUP;
9944                 }
9945         }
9946         return 0;
9947 }
9948
9949 /*
9950  * i40e_dcb_setup - setup dcb related config
9951  * @dev: device being configured
9952  *
9953  * Returns 0 on success, negative value on failure
9954  */
9955 static int
9956 i40e_dcb_setup(struct rte_eth_dev *dev)
9957 {
9958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9959         struct i40e_dcbx_config dcb_cfg;
9960         uint8_t tc_map = 0;
9961         int ret = 0;
9962
9963         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9964                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9965                 return -ENOTSUP;
9966         }
9967
9968         if (pf->vf_num != 0)
9969                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9970
9971         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9972         if (ret) {
9973                 PMD_INIT_LOG(ERR, "invalid dcb config");
9974                 return -EINVAL;
9975         }
9976         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9977         if (ret) {
9978                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9979                 return -ENOSYS;
9980         }
9981
9982         return 0;
9983 }
9984
9985 static int
9986 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9987                       struct rte_eth_dcb_info *dcb_info)
9988 {
9989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9990         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9991         struct i40e_vsi *vsi = pf->main_vsi;
9992         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9993         uint16_t bsf, tc_mapping;
9994         int i, j = 0;
9995
9996         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9997                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9998         else
9999                 dcb_info->nb_tcs = 1;
10000         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10001                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10002         for (i = 0; i < dcb_info->nb_tcs; i++)
10003                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10004
10005         /* get queue mapping if vmdq is disabled */
10006         if (!pf->nb_cfg_vmdq_vsi) {
10007                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10008                         if (!(vsi->enabled_tc & (1 << i)))
10009                                 continue;
10010                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10011                         dcb_info->tc_queue.tc_rxq[j][i].base =
10012                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10013                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10014                         dcb_info->tc_queue.tc_txq[j][i].base =
10015                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10016                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10017                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10018                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10019                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10020                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10021                 }
10022                 return 0;
10023         }
10024
10025         /* get queue mapping if vmdq is enabled */
10026         do {
10027                 vsi = pf->vmdq[j].vsi;
10028                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10029                         if (!(vsi->enabled_tc & (1 << i)))
10030                                 continue;
10031                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10032                         dcb_info->tc_queue.tc_rxq[j][i].base =
10033                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10034                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10035                         dcb_info->tc_queue.tc_txq[j][i].base =
10036                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10037                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10038                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10039                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10040                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10041                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10042                 }
10043                 j++;
10044         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10045         return 0;
10046 }
10047
10048 static int
10049 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10050 {
10051         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10052         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10054         uint16_t interval =
10055                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10056         uint16_t msix_intr;
10057
10058         msix_intr = intr_handle->intr_vec[queue_id];
10059         if (msix_intr == I40E_MISC_VEC_ID)
10060                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10061                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10062                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10063                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10064                                (interval <<
10065                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10066         else
10067                 I40E_WRITE_REG(hw,
10068                                I40E_PFINT_DYN_CTLN(msix_intr -
10069                                                    I40E_RX_VEC_START),
10070                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10071                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10072                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10073                                (interval <<
10074                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10075
10076         I40E_WRITE_FLUSH(hw);
10077         rte_intr_enable(&pci_dev->intr_handle);
10078
10079         return 0;
10080 }
10081
10082 static int
10083 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10084 {
10085         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10086         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10087         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10088         uint16_t msix_intr;
10089
10090         msix_intr = intr_handle->intr_vec[queue_id];
10091         if (msix_intr == I40E_MISC_VEC_ID)
10092                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10093         else
10094                 I40E_WRITE_REG(hw,
10095                                I40E_PFINT_DYN_CTLN(msix_intr -
10096                                                    I40E_RX_VEC_START),
10097                                0);
10098         I40E_WRITE_FLUSH(hw);
10099
10100         return 0;
10101 }
10102
10103 static int i40e_get_regs(struct rte_eth_dev *dev,
10104                          struct rte_dev_reg_info *regs)
10105 {
10106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10107         uint32_t *ptr_data = regs->data;
10108         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10109         const struct i40e_reg_info *reg_info;
10110
10111         if (ptr_data == NULL) {
10112                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10113                 regs->width = sizeof(uint32_t);
10114                 return 0;
10115         }
10116
10117         /* The first few registers have to be read using AQ operations */
10118         reg_idx = 0;
10119         while (i40e_regs_adminq[reg_idx].name) {
10120                 reg_info = &i40e_regs_adminq[reg_idx++];
10121                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10122                         for (arr_idx2 = 0;
10123                                         arr_idx2 <= reg_info->count2;
10124                                         arr_idx2++) {
10125                                 reg_offset = arr_idx * reg_info->stride1 +
10126                                         arr_idx2 * reg_info->stride2;
10127                                 reg_offset += reg_info->base_addr;
10128                                 ptr_data[reg_offset >> 2] =
10129                                         i40e_read_rx_ctl(hw, reg_offset);
10130                         }
10131         }
10132
10133         /* The remaining registers can be read using primitives */
10134         reg_idx = 0;
10135         while (i40e_regs_others[reg_idx].name) {
10136                 reg_info = &i40e_regs_others[reg_idx++];
10137                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10138                         for (arr_idx2 = 0;
10139                                         arr_idx2 <= reg_info->count2;
10140                                         arr_idx2++) {
10141                                 reg_offset = arr_idx * reg_info->stride1 +
10142                                         arr_idx2 * reg_info->stride2;
10143                                 reg_offset += reg_info->base_addr;
10144                                 ptr_data[reg_offset >> 2] =
10145                                         I40E_READ_REG(hw, reg_offset);
10146                         }
10147         }
10148
10149         return 0;
10150 }
10151
10152 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10153 {
10154         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10155
10156         /* Convert word count to byte count */
10157         return hw->nvm.sr_size << 1;
10158 }
10159
10160 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10161                            struct rte_dev_eeprom_info *eeprom)
10162 {
10163         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10164         uint16_t *data = eeprom->data;
10165         uint16_t offset, length, cnt_words;
10166         int ret_code;
10167
10168         offset = eeprom->offset >> 1;
10169         length = eeprom->length >> 1;
10170         cnt_words = length;
10171
10172         if (offset > hw->nvm.sr_size ||
10173                 offset + length > hw->nvm.sr_size) {
10174                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10175                 return -EINVAL;
10176         }
10177
10178         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10179
10180         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10181         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10182                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10183                 return -EIO;
10184         }
10185
10186         return 0;
10187 }
10188
10189 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10190                                       struct ether_addr *mac_addr)
10191 {
10192         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10193
10194         if (!is_valid_assigned_ether_addr(mac_addr)) {
10195                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10196                 return;
10197         }
10198
10199         /* Flags: 0x3 updates port address */
10200         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10201 }
10202
10203 static int
10204 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10205 {
10206         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10207         struct rte_eth_dev_data *dev_data = pf->dev_data;
10208         uint32_t frame_size = mtu + ETHER_HDR_LEN
10209                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10210         int ret = 0;
10211
10212         /* check if mtu is within the allowed range */
10213         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10214                 return -EINVAL;
10215
10216         /* mtu setting is forbidden if port is start */
10217         if (dev_data->dev_started) {
10218                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10219                             dev_data->port_id);
10220                 return -EBUSY;
10221         }
10222
10223         if (frame_size > ETHER_MAX_LEN)
10224                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10225         else
10226                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10227
10228         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10229
10230         return ret;
10231 }
10232
10233 /* Restore ethertype filter */
10234 static void
10235 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10236 {
10237         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10238         struct i40e_ethertype_filter_list
10239                 *ethertype_list = &pf->ethertype.ethertype_list;
10240         struct i40e_ethertype_filter *f;
10241         struct i40e_control_filter_stats stats;
10242         uint16_t flags;
10243
10244         TAILQ_FOREACH(f, ethertype_list, rules) {
10245                 flags = 0;
10246                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10247                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10248                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10249                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10250                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10251
10252                 memset(&stats, 0, sizeof(stats));
10253                 i40e_aq_add_rem_control_packet_filter(hw,
10254                                             f->input.mac_addr.addr_bytes,
10255                                             f->input.ether_type,
10256                                             flags, pf->main_vsi->seid,
10257                                             f->queue, 1, &stats, NULL);
10258         }
10259         PMD_DRV_LOG(INFO, "Ethertype filter:"
10260                     " mac_etype_used = %u, etype_used = %u,"
10261                     " mac_etype_free = %u, etype_free = %u",
10262                     stats.mac_etype_used, stats.etype_used,
10263                     stats.mac_etype_free, stats.etype_free);
10264 }
10265
10266 /* Restore tunnel filter */
10267 static void
10268 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10269 {
10270         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10271         struct i40e_vsi *vsi = pf->main_vsi;
10272         struct i40e_tunnel_filter_list
10273                 *tunnel_list = &pf->tunnel.tunnel_list;
10274         struct i40e_tunnel_filter *f;
10275         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10276
10277         TAILQ_FOREACH(f, tunnel_list, rules) {
10278                 memset(&cld_filter, 0, sizeof(cld_filter));
10279                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10280                 cld_filter.queue_number = f->queue;
10281                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10282         }
10283 }
10284
10285 static void
10286 i40e_filter_restore(struct i40e_pf *pf)
10287 {
10288         i40e_ethertype_filter_restore(pf);
10289         i40e_tunnel_filter_restore(pf);
10290         i40e_fdir_filter_restore(pf);
10291 }
10292
10293 static bool
10294 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10295 {
10296         if (strcmp(dev->driver->pci_drv.driver.name,
10297                    drv->pci_drv.driver.name))
10298                 return false;
10299
10300         return true;
10301 }
10302
10303 int
10304 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10305 {
10306         struct rte_eth_dev *dev;
10307         struct i40e_pf *pf;
10308
10309         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10310
10311         dev = &rte_eth_devices[port];
10312
10313         if (!is_device_supported(dev, &rte_i40e_pmd))
10314                 return -ENOTSUP;
10315
10316         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10317
10318         if (vf >= pf->vf_num || !pf->vfs) {
10319                 PMD_DRV_LOG(ERR, "Invalid argument.");
10320                 return -EINVAL;
10321         }
10322
10323         i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10324
10325         return 0;
10326 }
10327
10328 int
10329 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10330 {
10331         struct rte_eth_dev *dev;
10332         struct i40e_pf *pf;
10333         struct i40e_vsi *vsi;
10334         struct i40e_hw *hw;
10335         struct i40e_vsi_context ctxt;
10336         int ret;
10337
10338         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10339
10340         dev = &rte_eth_devices[port];
10341
10342         if (!is_device_supported(dev, &rte_i40e_pmd))
10343                 return -ENOTSUP;
10344
10345         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10346
10347         if (vf_id >= pf->vf_num || !pf->vfs) {
10348                 PMD_DRV_LOG(ERR, "Invalid argument.");
10349                 return -EINVAL;
10350         }
10351
10352         vsi = pf->vfs[vf_id].vsi;
10353         if (!vsi) {
10354                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10355                 return -EINVAL;
10356         }
10357
10358         /* Check if it has been already on or off */
10359         if (vsi->info.valid_sections &
10360                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10361                 if (on) {
10362                         if ((vsi->info.sec_flags &
10363                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10364                             I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10365                                 return 0; /* already on */
10366                 } else {
10367                         if ((vsi->info.sec_flags &
10368                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10369                                 return 0; /* already off */
10370                 }
10371         }
10372
10373         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10374         if (on)
10375                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10376         else
10377                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10378
10379         memset(&ctxt, 0, sizeof(ctxt));
10380         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10381         ctxt.seid = vsi->seid;
10382
10383         hw = I40E_VSI_TO_HW(vsi);
10384         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10385         if (ret != I40E_SUCCESS) {
10386                 ret = -ENOTSUP;
10387                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10388         }
10389
10390         return ret;
10391 }
10392
10393 static int
10394 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10395 {
10396         uint32_t j, k;
10397         uint16_t vlan_id;
10398         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10399         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10400         int ret;
10401
10402         for (j = 0; j < I40E_VFTA_SIZE; j++) {
10403                 if (!vsi->vfta[j])
10404                         continue;
10405
10406                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10407                         if (!(vsi->vfta[j] & (1 << k)))
10408                                 continue;
10409
10410                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10411                         if (!vlan_id)
10412                                 continue;
10413
10414                         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10415                         if (add)
10416                                 ret = i40e_aq_add_vlan(hw, vsi->seid,
10417                                                        &vlan_data, 1, NULL);
10418                         else
10419                                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10420                                                           &vlan_data, 1, NULL);
10421                         if (ret != I40E_SUCCESS) {
10422                                 PMD_DRV_LOG(ERR,
10423                                             "Failed to add/rm vlan filter");
10424                                 return ret;
10425                         }
10426                 }
10427         }
10428
10429         return I40E_SUCCESS;
10430 }
10431
10432 int
10433 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10434 {
10435         struct rte_eth_dev *dev;
10436         struct i40e_pf *pf;
10437         struct i40e_vsi *vsi;
10438         struct i40e_hw *hw;
10439         struct i40e_vsi_context ctxt;
10440         int ret;
10441
10442         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10443
10444         dev = &rte_eth_devices[port];
10445
10446         if (!is_device_supported(dev, &rte_i40e_pmd))
10447                 return -ENOTSUP;
10448
10449         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10450
10451         if (vf_id >= pf->vf_num || !pf->vfs) {
10452                 PMD_DRV_LOG(ERR, "Invalid argument.");
10453                 return -EINVAL;
10454         }
10455
10456         vsi = pf->vfs[vf_id].vsi;
10457         if (!vsi) {
10458                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10459                 return -EINVAL;
10460         }
10461
10462         /* Check if it has been already on or off */
10463         if (vsi->vlan_anti_spoof_on == on)
10464                 return 0; /* already on or off */
10465
10466         vsi->vlan_anti_spoof_on = on;
10467         ret = i40e_add_rm_all_vlan_filter(vsi, on);
10468         if (ret) {
10469                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filters.");
10470                 return -ENOTSUP;
10471         }
10472
10473         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10474         if (on)
10475                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10476         else
10477                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10478
10479         memset(&ctxt, 0, sizeof(ctxt));
10480         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10481         ctxt.seid = vsi->seid;
10482
10483         hw = I40E_VSI_TO_HW(vsi);
10484         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10485         if (ret != I40E_SUCCESS) {
10486                 ret = -ENOTSUP;
10487                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10488         }
10489
10490         return ret;
10491 }
10492
10493 static int
10494 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10495 {
10496         struct i40e_mac_filter *f;
10497         struct i40e_macvlan_filter *mv_f;
10498         int i, vlan_num;
10499         enum rte_mac_filter_type filter_type;
10500         int ret = I40E_SUCCESS;
10501         void *temp;
10502
10503         /* remove all the MACs */
10504         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10505                 vlan_num = vsi->vlan_num;
10506                 filter_type = f->mac_info.filter_type;
10507                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10508                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10509                         if (vlan_num == 0) {
10510                                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10511                                 return I40E_ERR_PARAM;
10512                         }
10513                 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10514                            filter_type == RTE_MAC_HASH_MATCH)
10515                         vlan_num = 1;
10516
10517                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10518                 if (!mv_f) {
10519                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10520                         return I40E_ERR_NO_MEMORY;
10521                 }
10522
10523                 for (i = 0; i < vlan_num; i++) {
10524                         mv_f[i].filter_type = filter_type;
10525                         (void)rte_memcpy(&mv_f[i].macaddr,
10526                                          &f->mac_info.mac_addr,
10527                                          ETH_ADDR_LEN);
10528                 }
10529                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10530                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10531                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10532                                                          &f->mac_info.mac_addr);
10533                         if (ret != I40E_SUCCESS) {
10534                                 rte_free(mv_f);
10535                                 return ret;
10536                         }
10537                 }
10538
10539                 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10540                 if (ret != I40E_SUCCESS) {
10541                         rte_free(mv_f);
10542                         return ret;
10543                 }
10544
10545                 rte_free(mv_f);
10546                 ret = I40E_SUCCESS;
10547         }
10548
10549         return ret;
10550 }
10551
10552 static int
10553 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10554 {
10555         struct i40e_mac_filter *f;
10556         struct i40e_macvlan_filter *mv_f;
10557         int i, vlan_num = 0;
10558         int ret = I40E_SUCCESS;
10559         void *temp;
10560
10561         /* restore all the MACs */
10562         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10563                 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10564                     (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10565                         /**
10566                          * If vlan_num is 0, that's the first time to add mac,
10567                          * set mask for vlan_id 0.
10568                          */
10569                         if (vsi->vlan_num == 0) {
10570                                 i40e_set_vlan_filter(vsi, 0, 1);
10571                                 vsi->vlan_num = 1;
10572                         }
10573                         vlan_num = vsi->vlan_num;
10574                 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10575                            (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10576                         vlan_num = 1;
10577
10578                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10579                 if (!mv_f) {
10580                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10581                         return I40E_ERR_NO_MEMORY;
10582                 }
10583
10584                 for (i = 0; i < vlan_num; i++) {
10585                         mv_f[i].filter_type = f->mac_info.filter_type;
10586                         (void)rte_memcpy(&mv_f[i].macaddr,
10587                                          &f->mac_info.mac_addr,
10588                                          ETH_ADDR_LEN);
10589                 }
10590
10591                 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10592                     f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10593                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10594                                                          &f->mac_info.mac_addr);
10595                         if (ret != I40E_SUCCESS) {
10596                                 rte_free(mv_f);
10597                                 return ret;
10598                         }
10599                 }
10600
10601                 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10602                 if (ret != I40E_SUCCESS) {
10603                         rte_free(mv_f);
10604                         return ret;
10605                 }
10606
10607                 rte_free(mv_f);
10608                 ret = I40E_SUCCESS;
10609         }
10610
10611         return ret;
10612 }
10613
10614 static int
10615 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10616 {
10617         struct i40e_vsi_context ctxt;
10618         struct i40e_hw *hw;
10619         int ret;
10620
10621         if (!vsi)
10622                 return -EINVAL;
10623
10624         hw = I40E_VSI_TO_HW(vsi);
10625
10626         /* Use the FW API if FW >= v5.0 */
10627         if (hw->aq.fw_maj_ver < 5) {
10628                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10629                 return -ENOTSUP;
10630         }
10631
10632         /* Check if it has been already on or off */
10633         if (vsi->info.valid_sections &
10634                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10635                 if (on) {
10636                         if ((vsi->info.switch_id &
10637                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10638                             I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10639                                 return 0; /* already on */
10640                 } else {
10641                         if ((vsi->info.switch_id &
10642                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10643                                 return 0; /* already off */
10644                 }
10645         }
10646
10647         /* remove all the MAC and VLAN first */
10648         ret = i40e_vsi_rm_mac_filter(vsi);
10649         if (ret) {
10650                 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10651                 return ret;
10652         }
10653         if (vsi->vlan_anti_spoof_on) {
10654                 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10655                 if (ret) {
10656                         PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10657                         return ret;
10658                 }
10659         }
10660
10661         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10662         if (on)
10663                 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10664         else
10665                 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10666
10667         memset(&ctxt, 0, sizeof(ctxt));
10668         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10669         ctxt.seid = vsi->seid;
10670
10671         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10672         if (ret != I40E_SUCCESS) {
10673                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10674                 return ret;
10675         }
10676
10677         /* add all the MAC and VLAN back */
10678         ret = i40e_vsi_restore_mac_filter(vsi);
10679         if (ret)
10680                 return ret;
10681         if (vsi->vlan_anti_spoof_on) {
10682                 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10683                 if (ret)
10684                         return ret;
10685         }
10686
10687         return ret;
10688 }
10689
10690 int
10691 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10692 {
10693         struct rte_eth_dev *dev;
10694         struct i40e_pf *pf;
10695         struct i40e_pf_vf *vf;
10696         struct i40e_vsi *vsi;
10697         uint16_t vf_id;
10698         int ret;
10699
10700         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10701
10702         dev = &rte_eth_devices[port];
10703
10704         if (!is_device_supported(dev, &rte_i40e_pmd))
10705                 return -ENOTSUP;
10706
10707         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10708
10709         /* setup PF TX loopback */
10710         vsi = pf->main_vsi;
10711         ret = i40e_vsi_set_tx_loopback(vsi, on);
10712         if (ret)
10713                 return -ENOTSUP;
10714
10715         /* setup TX loopback for all the VFs */
10716         if (!pf->vfs) {
10717                 /* if no VF, do nothing. */
10718                 return 0;
10719         }
10720
10721         for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10722                 vf = &pf->vfs[vf_id];
10723                 vsi = vf->vsi;
10724
10725                 ret = i40e_vsi_set_tx_loopback(vsi, on);
10726                 if (ret)
10727                         return -ENOTSUP;
10728         }
10729
10730         return ret;
10731 }
10732
10733 int
10734 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10735 {
10736         struct rte_eth_dev *dev;
10737         struct i40e_pf *pf;
10738         struct i40e_vsi *vsi;
10739         struct i40e_hw *hw;
10740         int ret;
10741
10742         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10743
10744         dev = &rte_eth_devices[port];
10745
10746         if (!is_device_supported(dev, &rte_i40e_pmd))
10747                 return -ENOTSUP;
10748
10749         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10750
10751         if (vf_id >= pf->vf_num || !pf->vfs) {
10752                 PMD_DRV_LOG(ERR, "Invalid argument.");
10753                 return -EINVAL;
10754         }
10755
10756         vsi = pf->vfs[vf_id].vsi;
10757         if (!vsi) {
10758                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10759                 return -EINVAL;
10760         }
10761
10762         hw = I40E_VSI_TO_HW(vsi);
10763
10764         ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10765                                                   on, NULL, true);
10766         if (ret != I40E_SUCCESS) {
10767                 ret = -ENOTSUP;
10768                 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10769         }
10770
10771         return ret;
10772 }
10773
10774 int
10775 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10776 {
10777         struct rte_eth_dev *dev;
10778         struct i40e_pf *pf;
10779         struct i40e_vsi *vsi;
10780         struct i40e_hw *hw;
10781         int ret;
10782
10783         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10784
10785         dev = &rte_eth_devices[port];
10786
10787         if (!is_device_supported(dev, &rte_i40e_pmd))
10788                 return -ENOTSUP;
10789
10790         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10791
10792         if (vf_id >= pf->vf_num || !pf->vfs) {
10793                 PMD_DRV_LOG(ERR, "Invalid argument.");
10794                 return -EINVAL;
10795         }
10796
10797         vsi = pf->vfs[vf_id].vsi;
10798         if (!vsi) {
10799                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10800                 return -EINVAL;
10801         }
10802
10803         hw = I40E_VSI_TO_HW(vsi);
10804
10805         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10806                                                     on, NULL);
10807         if (ret != I40E_SUCCESS) {
10808                 ret = -ENOTSUP;
10809                 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10810         }
10811
10812         return ret;
10813 }
10814
10815 int
10816 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
10817                              struct ether_addr *mac_addr)
10818 {
10819         struct i40e_mac_filter *f;
10820         struct rte_eth_dev *dev;
10821         struct i40e_pf_vf *vf;
10822         struct i40e_vsi *vsi;
10823         struct i40e_pf *pf;
10824         void *temp;
10825
10826         if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
10827                 return -EINVAL;
10828
10829         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10830
10831         dev = &rte_eth_devices[port];
10832
10833         if (!is_device_supported(dev, &rte_i40e_pmd))
10834                 return -ENOTSUP;
10835
10836         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10837
10838         if (vf_id >= pf->vf_num || !pf->vfs)
10839                 return -EINVAL;
10840
10841         vf = &pf->vfs[vf_id];
10842         vsi = vf->vsi;
10843         if (!vsi) {
10844                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10845                 return -EINVAL;
10846         }
10847
10848         ether_addr_copy(mac_addr, &vf->mac_addr);
10849
10850         /* Remove all existing mac */
10851         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
10852                 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
10853
10854         return 0;
10855 }
10856
10857 /* Set vlan strip on/off for specific VF from host */
10858 int
10859 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
10860 {
10861         struct rte_eth_dev *dev;
10862         struct i40e_pf *pf;
10863         struct i40e_vsi *vsi;
10864         int ret;
10865
10866         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10867
10868         dev = &rte_eth_devices[port];
10869
10870         if (!is_device_supported(dev, &rte_i40e_pmd))
10871                 return -ENOTSUP;
10872
10873         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10874
10875         if (vf_id >= pf->vf_num || !pf->vfs) {
10876                 PMD_DRV_LOG(ERR, "Invalid argument.");
10877                 return -EINVAL;
10878         }
10879
10880         vsi = pf->vfs[vf_id].vsi;
10881
10882         if (!vsi)
10883                 return -EINVAL;
10884
10885         ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
10886         if (ret != I40E_SUCCESS) {
10887                 ret = -ENOTSUP;
10888                 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
10889         }
10890
10891         return ret;
10892 }
10893
10894 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
10895                                     uint16_t vlan_id)
10896 {
10897         struct rte_eth_dev *dev;
10898         struct i40e_pf *pf;
10899         struct i40e_hw *hw;
10900         struct i40e_vsi *vsi;
10901         struct i40e_vsi_context ctxt;
10902         int ret;
10903
10904         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10905
10906         if (vlan_id > ETHER_MAX_VLAN_ID) {
10907                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
10908                 return -EINVAL;
10909         }
10910
10911         dev = &rte_eth_devices[port];
10912
10913         if (!is_device_supported(dev, &rte_i40e_pmd))
10914                 return -ENOTSUP;
10915
10916         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10917         hw = I40E_PF_TO_HW(pf);
10918
10919         /**
10920          * return -ENODEV if SRIOV not enabled, VF number not configured
10921          * or no queue assigned.
10922          */
10923         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10924             pf->vf_nb_qps == 0)
10925                 return -ENODEV;
10926
10927         if (vf_id >= pf->vf_num || !pf->vfs) {
10928                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10929                 return -EINVAL;
10930         }
10931
10932         vsi = pf->vfs[vf_id].vsi;
10933         if (!vsi) {
10934                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10935                 return -EINVAL;
10936         }
10937
10938         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
10939         vsi->info.pvid = vlan_id;
10940         if (vlan_id > 0)
10941                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
10942         else
10943                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
10944
10945         memset(&ctxt, 0, sizeof(ctxt));
10946         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10947         ctxt.seid = vsi->seid;
10948
10949         hw = I40E_VSI_TO_HW(vsi);
10950         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10951         if (ret != I40E_SUCCESS) {
10952                 ret = -ENOTSUP;
10953                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10954         }
10955
10956         return ret;
10957 }
10958
10959 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
10960                                   uint8_t on)
10961 {
10962         struct rte_eth_dev *dev;
10963         struct i40e_pf *pf;
10964         struct i40e_vsi *vsi;
10965         struct i40e_hw *hw;
10966         int ret;
10967
10968         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10969
10970         if (on > 1) {
10971                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
10972                 return -EINVAL;
10973         }
10974
10975         dev = &rte_eth_devices[port];
10976
10977         if (!is_device_supported(dev, &rte_i40e_pmd))
10978                 return -ENOTSUP;
10979
10980         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10981         hw = I40E_PF_TO_HW(pf);
10982
10983         if (vf_id >= pf->vf_num || !pf->vfs) {
10984                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10985                 return -EINVAL;
10986         }
10987
10988         /**
10989          * return -ENODEV if SRIOV not enabled, VF number not configured
10990          * or no queue assigned.
10991          */
10992         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10993             pf->vf_nb_qps == 0) {
10994                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
10995                 return -ENODEV;
10996         }
10997
10998         vsi = pf->vfs[vf_id].vsi;
10999         if (!vsi) {
11000                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11001                 return -EINVAL;
11002         }
11003
11004         hw = I40E_VSI_TO_HW(vsi);
11005
11006         ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, on, NULL);
11007         if (ret != I40E_SUCCESS) {
11008                 ret = -ENOTSUP;
11009                 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11010         }
11011
11012         return ret;
11013 }
11014
11015 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11016 {
11017         struct rte_eth_dev *dev;
11018         struct i40e_pf *pf;
11019         struct i40e_hw *hw;
11020         struct i40e_vsi *vsi;
11021         struct i40e_vsi_context ctxt;
11022         int ret;
11023
11024         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11025
11026         if (on > 1) {
11027                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11028                 return -EINVAL;
11029         }
11030
11031         dev = &rte_eth_devices[port];
11032
11033         if (!is_device_supported(dev, &rte_i40e_pmd))
11034                 return -ENOTSUP;
11035
11036         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11037         hw = I40E_PF_TO_HW(pf);
11038
11039         /**
11040          * return -ENODEV if SRIOV not enabled, VF number not configured
11041          * or no queue assigned.
11042          */
11043         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11044             pf->vf_nb_qps == 0) {
11045                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11046                 return -ENODEV;
11047         }
11048
11049         if (vf_id >= pf->vf_num || !pf->vfs) {
11050                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11051                 return -EINVAL;
11052         }
11053
11054         vsi = pf->vfs[vf_id].vsi;
11055         if (!vsi) {
11056                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11057                 return -EINVAL;
11058         }
11059
11060         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11061         if (on) {
11062                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11063                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11064         } else {
11065                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11066                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11067         }
11068
11069         memset(&ctxt, 0, sizeof(ctxt));
11070         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11071         ctxt.seid = vsi->seid;
11072
11073         hw = I40E_VSI_TO_HW(vsi);
11074         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11075         if (ret != I40E_SUCCESS) {
11076                 ret = -ENOTSUP;
11077                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11078         }
11079
11080         return ret;
11081 }
11082
11083 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11084                                     uint64_t vf_mask, uint8_t on)
11085 {
11086         struct rte_eth_dev *dev;
11087         struct i40e_pf *pf;
11088         struct i40e_hw *hw;
11089         uint16_t vf_idx;
11090         int ret = I40E_SUCCESS;
11091
11092         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11093
11094         dev = &rte_eth_devices[port];
11095
11096         if (!is_device_supported(dev, &rte_i40e_pmd))
11097                 return -ENOTSUP;
11098
11099         if (vlan_id > ETHER_MAX_VLAN_ID) {
11100                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11101                 return -EINVAL;
11102         }
11103
11104         if (vf_mask == 0) {
11105                 PMD_DRV_LOG(ERR, "No VF.");
11106                 return -EINVAL;
11107         }
11108
11109         if (on > 1) {
11110                 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11111                 return -EINVAL;
11112         }
11113
11114         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11115         hw = I40E_PF_TO_HW(pf);
11116
11117         /**
11118          * return -ENODEV if SRIOV not enabled, VF number not configured
11119          * or no queue assigned.
11120          */
11121         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11122             pf->vf_nb_qps == 0) {
11123                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11124                 return -ENODEV;
11125         }
11126
11127         for (vf_idx = 0; vf_idx < 64 && ret == I40E_SUCCESS; vf_idx++) {
11128                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11129                         if (on)
11130                                 ret = i40e_vsi_add_vlan(pf->vfs[vf_idx].vsi,
11131                                                         vlan_id);
11132                         else
11133                                 ret = i40e_vsi_delete_vlan(pf->vfs[vf_idx].vsi,
11134                                                            vlan_id);
11135                 }
11136         }
11137
11138         if (ret != I40E_SUCCESS) {
11139                 ret = -ENOTSUP;
11140                 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11141         }
11142
11143         return ret;
11144 }
11145
11146 int
11147 rte_pmd_i40e_get_vf_stats(uint8_t port,
11148                           uint16_t vf_id,
11149                           struct rte_eth_stats *stats)
11150 {
11151         struct rte_eth_dev *dev;
11152         struct i40e_pf *pf;
11153         struct i40e_vsi *vsi;
11154
11155         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11156
11157         dev = &rte_eth_devices[port];
11158
11159         if (!is_device_supported(dev, &rte_i40e_pmd))
11160                 return -ENOTSUP;
11161
11162         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11163
11164         if (vf_id >= pf->vf_num || !pf->vfs) {
11165                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11166                 return -EINVAL;
11167         }
11168
11169         vsi = pf->vfs[vf_id].vsi;
11170         if (!vsi) {
11171                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11172                 return -EINVAL;
11173         }
11174
11175         i40e_update_vsi_stats(vsi);
11176
11177         stats->ipackets = vsi->eth_stats.rx_unicast +
11178                         vsi->eth_stats.rx_multicast +
11179                         vsi->eth_stats.rx_broadcast;
11180         stats->opackets = vsi->eth_stats.tx_unicast +
11181                         vsi->eth_stats.tx_multicast +
11182                         vsi->eth_stats.tx_broadcast;
11183         stats->ibytes   = vsi->eth_stats.rx_bytes;
11184         stats->obytes   = vsi->eth_stats.tx_bytes;
11185         stats->ierrors  = vsi->eth_stats.rx_discards;
11186         stats->oerrors  = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11187
11188         return 0;
11189 }
11190
11191 int
11192 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11193                             uint16_t vf_id)
11194 {
11195         struct rte_eth_dev *dev;
11196         struct i40e_pf *pf;
11197         struct i40e_vsi *vsi;
11198
11199         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11200
11201         dev = &rte_eth_devices[port];
11202
11203         if (!is_device_supported(dev, &rte_i40e_pmd))
11204                 return -ENOTSUP;
11205
11206         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11207
11208         if (vf_id >= pf->vf_num || !pf->vfs) {
11209                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11210                 return -EINVAL;
11211         }
11212
11213         vsi = pf->vfs[vf_id].vsi;
11214         if (!vsi) {
11215                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11216                 return -EINVAL;
11217         }
11218
11219         vsi->offset_loaded = false;
11220         i40e_update_vsi_stats(vsi);
11221
11222         return 0;
11223 }