1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
46 #define I40E_CLEAR_PXE_WAIT_MS 200
48 /* Maximun number of capability elements */
49 #define I40E_MAX_CAP_ELE_NUM 128
51 /* Wait count and interval */
52 #define I40E_CHK_Q_ENA_COUNT 1000
53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
55 /* Maximun number of VSI */
56 #define I40E_MAX_NUM_VSIS (384UL)
58 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
60 /* Flow control default timer */
61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
63 /* Flow control enable fwd bit */
64 #define I40E_PRTMAC_FWD_CTRL 0x00000001
66 /* Receive Packet Buffer size */
67 #define I40E_RXPBSIZE (968 * 1024)
70 #define I40E_KILOSHIFT 10
72 /* Flow control default high water */
73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
75 /* Flow control default low water */
76 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Receive Average Packet Size in Byte*/
79 #define I40E_PACKET_AVERAGE_SIZE 128
81 /* Mask of PF interrupt causes */
82 #define I40E_PFINT_ICR0_ENA_MASK ( \
83 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
84 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
85 I40E_PFINT_ICR0_ENA_GRST_MASK | \
86 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
87 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
89 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
90 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
91 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
93 #define I40E_FLOW_TYPES ( \
94 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
95 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
96 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
99 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
104 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
106 /* Additional timesync values. */
107 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
108 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
109 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
110 #define I40E_PRTTSYN_TSYNENA 0x80000000
111 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
112 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 * Below are values for writing un-exposed registers suggested
118 /* Destination MAC address */
119 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
120 /* Source MAC address */
121 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
123 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
126 /* Single VLAN tag in the inner L2 header */
127 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
128 /* Source IPv4 address */
129 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
130 /* Destination IPv4 address */
131 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
132 /* Source IPv4 address for X722 */
133 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
134 /* Destination IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
136 /* IPv4 Protocol for X722 */
137 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
138 /* IPv4 Time to Live for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
140 /* IPv4 Type of Service (TOS) */
141 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
143 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
144 /* IPv4 Time to Live */
145 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
146 /* Source IPv6 address */
147 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
148 /* Destination IPv6 address */
149 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
150 /* IPv6 Traffic Class (TC) */
151 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
152 /* IPv6 Next Header */
153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
157 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
158 /* Destination L4 port */
159 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
160 /* SCTP verification tag */
161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
164 /* Source port of tunneling UDP */
165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
166 /* Destination port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
168 /* UDP Tunneling ID, NVGRE/GRE key */
169 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
170 /* Last ether type */
171 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
172 /* Tunneling outer destination IPv4 address */
173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
174 /* Tunneling outer destination IPv6 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
176 /* 1st word of flex payload */
177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
178 /* 2nd word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
180 /* 3rd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
182 /* 4th word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
184 /* 5th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
186 /* 6th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
188 /* 7th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
190 /* 8th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
192 /* all 8 words flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
194 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
196 #define I40E_TRANSLATE_INSET 0
197 #define I40E_TRANSLATE_REG 1
199 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
200 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
201 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
202 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
204 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
206 /* PCI offset for querying capability */
207 #define PCI_DEV_CAP_REG 0xA4
208 /* PCI offset for enabling/disabling Extended Tag */
209 #define PCI_DEV_CTRL_REG 0xA8
210 /* Bit mask of Extended Tag capability */
211 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
212 /* Bit shift of Extended Tag enable/disable */
213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
214 /* Bit mask of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
219 static int i40e_dev_configure(struct rte_eth_dev *dev);
220 static int i40e_dev_start(struct rte_eth_dev *dev);
221 static void i40e_dev_stop(struct rte_eth_dev *dev);
222 static void i40e_dev_close(struct rte_eth_dev *dev);
223 static int i40e_dev_reset(struct rte_eth_dev *dev);
224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
231 struct rte_eth_stats *stats);
232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
233 struct rte_eth_xstat *xstats, unsigned n);
234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
235 struct rte_eth_xstat_name *xstats_names,
237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
243 char *fw_version, size_t fw_size);
244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
245 struct rte_eth_dev_info *dev_info);
246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
250 enum rte_vlan_type vlan_type,
252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_pfc_conf *pfc_conf);
265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
266 struct ether_addr *mac_addr,
269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
271 struct rte_eth_rss_reta_entry64 *reta_conf,
273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
277 static int i40e_get_cap(struct i40e_hw *hw);
278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
279 static int i40e_pf_setup(struct i40e_pf *pf);
280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
284 bool offset_loaded, uint64_t *offset, uint64_t *stat);
285 static void i40e_stat_update_48(struct i40e_hw *hw,
291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
292 static void i40e_dev_interrupt_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 int i40e_logtype_init;
402 int i40e_logtype_driver;
404 static const struct rte_pci_id pci_id_i40e_map[] = {
405 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
406 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
407 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
408 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
409 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
410 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
425 { .vendor_id = 0, /* sentinel */ },
428 static const struct eth_dev_ops i40e_eth_dev_ops = {
429 .dev_configure = i40e_dev_configure,
430 .dev_start = i40e_dev_start,
431 .dev_stop = i40e_dev_stop,
432 .dev_close = i40e_dev_close,
433 .dev_reset = i40e_dev_reset,
434 .promiscuous_enable = i40e_dev_promiscuous_enable,
435 .promiscuous_disable = i40e_dev_promiscuous_disable,
436 .allmulticast_enable = i40e_dev_allmulticast_enable,
437 .allmulticast_disable = i40e_dev_allmulticast_disable,
438 .dev_set_link_up = i40e_dev_set_link_up,
439 .dev_set_link_down = i40e_dev_set_link_down,
440 .link_update = i40e_dev_link_update,
441 .stats_get = i40e_dev_stats_get,
442 .xstats_get = i40e_dev_xstats_get,
443 .xstats_get_names = i40e_dev_xstats_get_names,
444 .stats_reset = i40e_dev_stats_reset,
445 .xstats_reset = i40e_dev_stats_reset,
446 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
447 .fw_version_get = i40e_fw_version_get,
448 .dev_infos_get = i40e_dev_info_get,
449 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
450 .vlan_filter_set = i40e_vlan_filter_set,
451 .vlan_tpid_set = i40e_vlan_tpid_set,
452 .vlan_offload_set = i40e_vlan_offload_set,
453 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
454 .vlan_pvid_set = i40e_vlan_pvid_set,
455 .rx_queue_start = i40e_dev_rx_queue_start,
456 .rx_queue_stop = i40e_dev_rx_queue_stop,
457 .tx_queue_start = i40e_dev_tx_queue_start,
458 .tx_queue_stop = i40e_dev_tx_queue_stop,
459 .rx_queue_setup = i40e_dev_rx_queue_setup,
460 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
461 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
462 .rx_queue_release = i40e_dev_rx_queue_release,
463 .rx_queue_count = i40e_dev_rx_queue_count,
464 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
465 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
466 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
467 .tx_queue_setup = i40e_dev_tx_queue_setup,
468 .tx_queue_release = i40e_dev_tx_queue_release,
469 .dev_led_on = i40e_dev_led_on,
470 .dev_led_off = i40e_dev_led_off,
471 .flow_ctrl_get = i40e_flow_ctrl_get,
472 .flow_ctrl_set = i40e_flow_ctrl_set,
473 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
474 .mac_addr_add = i40e_macaddr_add,
475 .mac_addr_remove = i40e_macaddr_remove,
476 .reta_update = i40e_dev_rss_reta_update,
477 .reta_query = i40e_dev_rss_reta_query,
478 .rss_hash_update = i40e_dev_rss_hash_update,
479 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
480 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
481 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
482 .filter_ctrl = i40e_dev_filter_ctrl,
483 .rxq_info_get = i40e_rxq_info_get,
484 .txq_info_get = i40e_txq_info_get,
485 .mirror_rule_set = i40e_mirror_rule_set,
486 .mirror_rule_reset = i40e_mirror_rule_reset,
487 .timesync_enable = i40e_timesync_enable,
488 .timesync_disable = i40e_timesync_disable,
489 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
490 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
491 .get_dcb_info = i40e_dev_get_dcb_info,
492 .timesync_adjust_time = i40e_timesync_adjust_time,
493 .timesync_read_time = i40e_timesync_read_time,
494 .timesync_write_time = i40e_timesync_write_time,
495 .get_reg = i40e_get_regs,
496 .get_eeprom_length = i40e_get_eeprom_length,
497 .get_eeprom = i40e_get_eeprom,
498 .get_module_info = i40e_get_module_info,
499 .get_module_eeprom = i40e_get_module_eeprom,
500 .mac_addr_set = i40e_set_default_mac_addr,
501 .mtu_set = i40e_dev_mtu_set,
502 .tm_ops_get = i40e_tm_ops_get,
505 /* store statistics names and its offset in stats structure */
506 struct rte_i40e_xstats_name_off {
507 char name[RTE_ETH_XSTATS_NAME_SIZE];
511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
512 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
513 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
514 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
515 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
516 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
517 rx_unknown_protocol)},
518 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
519 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
520 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
521 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
525 sizeof(rte_i40e_stats_strings[0]))
527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
528 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
529 tx_dropped_link_down)},
530 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
531 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
533 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
534 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
536 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
538 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
540 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
541 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
542 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
543 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
544 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
545 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
547 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
549 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
551 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
553 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
555 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
557 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
559 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
561 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
562 mac_short_packet_dropped)},
563 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
566 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
567 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
569 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
571 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
573 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
575 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
577 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_flow_director_atr_match_packets",
580 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
581 {"rx_flow_director_sb_match_packets",
582 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
583 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
585 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
587 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
589 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
594 sizeof(rte_i40e_hw_port_strings[0]))
596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
597 {"xon_packets", offsetof(struct i40e_hw_port_stats,
599 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
604 sizeof(rte_i40e_rxq_prio_strings[0]))
606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
607 {"xon_packets", offsetof(struct i40e_hw_port_stats,
609 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
611 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
612 priority_xon_2_xoff)},
615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
616 sizeof(rte_i40e_txq_prio_strings[0]))
619 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
620 struct rte_pci_device *pci_dev)
622 char name[RTE_ETH_NAME_MAX_LEN];
623 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
626 if (pci_dev->device.devargs) {
627 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
633 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
634 sizeof(struct i40e_adapter),
635 eth_dev_pci_specific_init, pci_dev,
636 eth_i40e_dev_init, NULL);
638 if (retval || eth_da.nb_representor_ports < 1)
641 /* probe VF representor ports */
642 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
643 pci_dev->device.name);
645 if (pf_ethdev == NULL)
648 for (i = 0; i < eth_da.nb_representor_ports; i++) {
649 struct i40e_vf_representor representor = {
650 .vf_id = eth_da.representor_ports[i],
651 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
652 pf_ethdev->data->dev_private)->switch_domain_id,
653 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
654 pf_ethdev->data->dev_private)
657 /* representor port net_bdf_port */
658 snprintf(name, sizeof(name), "net_%s_representor_%d",
659 pci_dev->device.name, eth_da.representor_ports[i]);
661 retval = rte_eth_dev_create(&pci_dev->device, name,
662 sizeof(struct i40e_vf_representor), NULL, NULL,
663 i40e_vf_representor_init, &representor);
666 PMD_DRV_LOG(ERR, "failed to create i40e vf "
667 "representor %s.", name);
673 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
675 struct rte_eth_dev *ethdev;
677 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
682 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
683 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
685 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
688 static struct rte_pci_driver rte_i40e_pmd = {
689 .id_table = pci_id_i40e_map,
690 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
691 RTE_PCI_DRV_IOVA_AS_VA,
692 .probe = eth_i40e_pci_probe,
693 .remove = eth_i40e_pci_remove,
697 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
700 uint32_t ori_reg_val;
702 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
703 i40e_write_rx_ctl(hw, reg_addr, reg_val);
705 "Global register [0x%08x] original: 0x%08x, after: 0x%08x",
706 reg_addr, ori_reg_val, reg_val);
709 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
710 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
711 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
713 #ifndef I40E_GLQF_ORT
714 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
716 #ifndef I40E_GLQF_PIT
717 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
719 #ifndef I40E_GLQF_L3_MAP
720 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
723 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
726 * Initialize registers for parsing packet type of QinQ
727 * This should be removed from code once proper
728 * configuration API is added to avoid configuration conflicts
729 * between ports of the same device.
731 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
732 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
733 i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
736 static inline void i40e_config_automask(struct i40e_pf *pf)
738 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
741 /* INTENA flag is not auto-cleared for interrupt */
742 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
743 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
744 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
746 /* If support multi-driver, PF will use INT0. */
747 if (!pf->support_multi_driver)
748 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
750 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
753 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
756 * Add a ethertype filter to drop all flow control frames transmitted
760 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
762 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
763 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
764 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
765 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
768 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
769 I40E_FLOW_CONTROL_ETHERTYPE, flags,
770 pf->main_vsi_seid, 0,
774 "Failed to add filter to drop flow control frames from VSIs.");
778 floating_veb_list_handler(__rte_unused const char *key,
779 const char *floating_veb_value,
783 unsigned int count = 0;
786 bool *vf_floating_veb = opaque;
788 while (isblank(*floating_veb_value))
789 floating_veb_value++;
791 /* Reset floating VEB configuration for VFs */
792 for (idx = 0; idx < I40E_MAX_VF; idx++)
793 vf_floating_veb[idx] = false;
797 while (isblank(*floating_veb_value))
798 floating_veb_value++;
799 if (*floating_veb_value == '\0')
802 idx = strtoul(floating_veb_value, &end, 10);
803 if (errno || end == NULL)
805 while (isblank(*end))
809 } else if ((*end == ';') || (*end == '\0')) {
811 if (min == I40E_MAX_VF)
813 if (max >= I40E_MAX_VF)
814 max = I40E_MAX_VF - 1;
815 for (idx = min; idx <= max; idx++) {
816 vf_floating_veb[idx] = true;
823 floating_veb_value = end + 1;
824 } while (*end != '\0');
833 config_vf_floating_veb(struct rte_devargs *devargs,
834 uint16_t floating_veb,
835 bool *vf_floating_veb)
837 struct rte_kvargs *kvlist;
839 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
843 /* All the VFs attach to the floating VEB by default
844 * when the floating VEB is enabled.
846 for (i = 0; i < I40E_MAX_VF; i++)
847 vf_floating_veb[i] = true;
852 kvlist = rte_kvargs_parse(devargs->args, NULL);
856 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
857 rte_kvargs_free(kvlist);
860 /* When the floating_veb_list parameter exists, all the VFs
861 * will attach to the legacy VEB firstly, then configure VFs
862 * to the floating VEB according to the floating_veb_list.
864 if (rte_kvargs_process(kvlist, floating_veb_list,
865 floating_veb_list_handler,
866 vf_floating_veb) < 0) {
867 rte_kvargs_free(kvlist);
870 rte_kvargs_free(kvlist);
874 i40e_check_floating_handler(__rte_unused const char *key,
876 __rte_unused void *opaque)
878 if (strcmp(value, "1"))
885 is_floating_veb_supported(struct rte_devargs *devargs)
887 struct rte_kvargs *kvlist;
888 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
893 kvlist = rte_kvargs_parse(devargs->args, NULL);
897 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
898 rte_kvargs_free(kvlist);
901 /* Floating VEB is enabled when there's key-value:
902 * enable_floating_veb=1
904 if (rte_kvargs_process(kvlist, floating_veb_key,
905 i40e_check_floating_handler, NULL) < 0) {
906 rte_kvargs_free(kvlist);
909 rte_kvargs_free(kvlist);
915 config_floating_veb(struct rte_eth_dev *dev)
917 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
918 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
919 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
921 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
923 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
925 is_floating_veb_supported(pci_dev->device.devargs);
926 config_vf_floating_veb(pci_dev->device.devargs,
928 pf->floating_veb_list);
930 pf->floating_veb = false;
934 #define I40E_L2_TAGS_S_TAG_SHIFT 1
935 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
938 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
941 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
942 char ethertype_hash_name[RTE_HASH_NAMESIZE];
945 struct rte_hash_parameters ethertype_hash_params = {
946 .name = ethertype_hash_name,
947 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
948 .key_len = sizeof(struct i40e_ethertype_filter_input),
949 .hash_func = rte_hash_crc,
950 .hash_func_init_val = 0,
951 .socket_id = rte_socket_id(),
954 /* Initialize ethertype filter rule list and hash */
955 TAILQ_INIT(ðertype_rule->ethertype_list);
956 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
957 "ethertype_%s", dev->device->name);
958 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
959 if (!ethertype_rule->hash_table) {
960 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
963 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
964 sizeof(struct i40e_ethertype_filter *) *
965 I40E_MAX_ETHERTYPE_FILTER_NUM,
967 if (!ethertype_rule->hash_map) {
969 "Failed to allocate memory for ethertype hash map!");
971 goto err_ethertype_hash_map_alloc;
976 err_ethertype_hash_map_alloc:
977 rte_hash_free(ethertype_rule->hash_table);
983 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
985 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
986 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
987 char tunnel_hash_name[RTE_HASH_NAMESIZE];
990 struct rte_hash_parameters tunnel_hash_params = {
991 .name = tunnel_hash_name,
992 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
993 .key_len = sizeof(struct i40e_tunnel_filter_input),
994 .hash_func = rte_hash_crc,
995 .hash_func_init_val = 0,
996 .socket_id = rte_socket_id(),
999 /* Initialize tunnel filter rule list and hash */
1000 TAILQ_INIT(&tunnel_rule->tunnel_list);
1001 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1002 "tunnel_%s", dev->device->name);
1003 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1004 if (!tunnel_rule->hash_table) {
1005 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1008 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1009 sizeof(struct i40e_tunnel_filter *) *
1010 I40E_MAX_TUNNEL_FILTER_NUM,
1012 if (!tunnel_rule->hash_map) {
1014 "Failed to allocate memory for tunnel hash map!");
1016 goto err_tunnel_hash_map_alloc;
1021 err_tunnel_hash_map_alloc:
1022 rte_hash_free(tunnel_rule->hash_table);
1028 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1030 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031 struct i40e_fdir_info *fdir_info = &pf->fdir;
1032 char fdir_hash_name[RTE_HASH_NAMESIZE];
1035 struct rte_hash_parameters fdir_hash_params = {
1036 .name = fdir_hash_name,
1037 .entries = I40E_MAX_FDIR_FILTER_NUM,
1038 .key_len = sizeof(struct i40e_fdir_input),
1039 .hash_func = rte_hash_crc,
1040 .hash_func_init_val = 0,
1041 .socket_id = rte_socket_id(),
1044 /* Initialize flow director filter rule list and hash */
1045 TAILQ_INIT(&fdir_info->fdir_list);
1046 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1047 "fdir_%s", dev->device->name);
1048 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1049 if (!fdir_info->hash_table) {
1050 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1053 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1054 sizeof(struct i40e_fdir_filter *) *
1055 I40E_MAX_FDIR_FILTER_NUM,
1057 if (!fdir_info->hash_map) {
1059 "Failed to allocate memory for fdir hash map!");
1061 goto err_fdir_hash_map_alloc;
1065 err_fdir_hash_map_alloc:
1066 rte_hash_free(fdir_info->hash_table);
1072 i40e_init_customized_info(struct i40e_pf *pf)
1076 /* Initialize customized pctype */
1077 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1078 pf->customized_pctype[i].index = i;
1079 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1080 pf->customized_pctype[i].valid = false;
1083 pf->gtp_support = false;
1087 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1089 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1090 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1091 struct i40e_queue_regions *info = &pf->queue_region;
1094 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1095 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1097 memset(info, 0, sizeof(struct i40e_queue_regions));
1100 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
1103 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1108 unsigned long support_multi_driver;
1111 pf = (struct i40e_pf *)opaque;
1114 support_multi_driver = strtoul(value, &end, 10);
1115 if (errno != 0 || end == value || *end != 0) {
1116 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1120 if (support_multi_driver == 1 || support_multi_driver == 0)
1121 pf->support_multi_driver = (bool)support_multi_driver;
1123 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1124 "enable global configuration by default."
1125 ETH_I40E_SUPPORT_MULTI_DRIVER);
1130 i40e_support_multi_driver(struct rte_eth_dev *dev)
1132 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1133 static const char *const valid_keys[] = {
1134 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1135 struct rte_kvargs *kvlist;
1137 /* Enable global configuration by default */
1138 pf->support_multi_driver = false;
1140 if (!dev->device->devargs)
1143 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1147 if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1148 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1149 "the first invalid or last valid one is used !",
1150 ETH_I40E_SUPPORT_MULTI_DRIVER);
1152 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1153 i40e_parse_multi_drv_handler, pf) < 0) {
1154 rte_kvargs_free(kvlist);
1158 rte_kvargs_free(kvlist);
1163 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1164 uint32_t reg_addr, uint64_t reg_val,
1165 struct i40e_asq_cmd_details *cmd_details)
1167 uint64_t ori_reg_val;
1170 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1171 if (ret != I40E_SUCCESS) {
1173 "Fail to debug read from 0x%08x",
1179 "Global register [0x%08x] original: 0x%"PRIx64
1180 ", after: 0x%"PRIx64,
1181 reg_addr, ori_reg_val, reg_val);
1183 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1187 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1189 struct rte_pci_device *pci_dev;
1190 struct rte_intr_handle *intr_handle;
1191 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1192 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1193 struct i40e_vsi *vsi;
1196 uint8_t aq_fail = 0;
1198 PMD_INIT_FUNC_TRACE();
1200 dev->dev_ops = &i40e_eth_dev_ops;
1201 dev->rx_pkt_burst = i40e_recv_pkts;
1202 dev->tx_pkt_burst = i40e_xmit_pkts;
1203 dev->tx_pkt_prepare = i40e_prep_pkts;
1205 /* for secondary processes, we don't initialise any further as primary
1206 * has already done this work. Only check we don't need a different
1208 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1209 i40e_set_rx_function(dev);
1210 i40e_set_tx_function(dev);
1213 i40e_set_default_ptype_table(dev);
1214 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1215 intr_handle = &pci_dev->intr_handle;
1217 rte_eth_copy_pci_info(dev, pci_dev);
1219 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1220 pf->adapter->eth_dev = dev;
1221 pf->dev_data = dev->data;
1223 hw->back = I40E_PF_TO_ADAPTER(pf);
1224 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1227 "Hardware is not available, as address is NULL");
1231 hw->vendor_id = pci_dev->id.vendor_id;
1232 hw->device_id = pci_dev->id.device_id;
1233 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1234 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1235 hw->bus.device = pci_dev->addr.devid;
1236 hw->bus.func = pci_dev->addr.function;
1237 hw->adapter_stopped = 0;
1239 /* Check if need to support multi-driver */
1240 i40e_support_multi_driver(dev);
1242 /* Make sure all is clean before doing PF reset */
1245 /* Initialize the hardware */
1248 /* Reset here to make sure all is clean for each PF */
1249 ret = i40e_pf_reset(hw);
1251 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1255 /* Initialize the shared code (base driver) */
1256 ret = i40e_init_shared_code(hw);
1258 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1262 i40e_config_automask(pf);
1264 i40e_set_default_pctype_table(dev);
1267 * To work around the NVM issue, initialize registers
1268 * for packet type of QinQ by software.
1269 * It should be removed once issues are fixed in NVM.
1271 if (!pf->support_multi_driver)
1272 i40e_GLQF_reg_init(hw);
1274 /* Initialize the input set for filters (hash and fd) to default value */
1275 i40e_filter_input_set_init(pf);
1277 /* Initialize the parameters for adminq */
1278 i40e_init_adminq_parameter(hw);
1279 ret = i40e_init_adminq(hw);
1280 if (ret != I40E_SUCCESS) {
1281 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1284 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1285 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1286 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1287 ((hw->nvm.version >> 12) & 0xf),
1288 ((hw->nvm.version >> 4) & 0xff),
1289 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1291 /* initialise the L3_MAP register */
1292 if (!pf->support_multi_driver) {
1293 ret = i40e_aq_debug_write_global_register(hw,
1294 I40E_GLQF_L3_MAP(40),
1297 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1300 "Global register 0x%08x is changed with 0x28",
1301 I40E_GLQF_L3_MAP(40));
1302 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1305 /* Need the special FW version to support floating VEB */
1306 config_floating_veb(dev);
1307 /* Clear PXE mode */
1308 i40e_clear_pxe_mode(hw);
1309 i40e_dev_sync_phy_type(hw);
1312 * On X710, performance number is far from the expectation on recent
1313 * firmware versions. The fix for this issue may not be integrated in
1314 * the following firmware version. So the workaround in software driver
1315 * is needed. It needs to modify the initial values of 3 internal only
1316 * registers. Note that the workaround can be removed when it is fixed
1317 * in firmware in the future.
1319 i40e_configure_registers(hw);
1321 /* Get hw capabilities */
1322 ret = i40e_get_cap(hw);
1323 if (ret != I40E_SUCCESS) {
1324 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1325 goto err_get_capabilities;
1328 /* Initialize parameters for PF */
1329 ret = i40e_pf_parameter_init(dev);
1331 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1332 goto err_parameter_init;
1335 /* Initialize the queue management */
1336 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1338 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1339 goto err_qp_pool_init;
1341 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1342 hw->func_caps.num_msix_vectors - 1);
1344 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1345 goto err_msix_pool_init;
1348 /* Initialize lan hmc */
1349 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1350 hw->func_caps.num_rx_qp, 0, 0);
1351 if (ret != I40E_SUCCESS) {
1352 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1353 goto err_init_lan_hmc;
1356 /* Configure lan hmc */
1357 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1358 if (ret != I40E_SUCCESS) {
1359 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1360 goto err_configure_lan_hmc;
1363 /* Get and check the mac address */
1364 i40e_get_mac_addr(hw, hw->mac.addr);
1365 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1366 PMD_INIT_LOG(ERR, "mac address is not valid");
1368 goto err_get_mac_addr;
1370 /* Copy the permanent MAC address */
1371 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1372 (struct ether_addr *) hw->mac.perm_addr);
1374 /* Disable flow control */
1375 hw->fc.requested_mode = I40E_FC_NONE;
1376 i40e_set_fc(hw, &aq_fail, TRUE);
1378 /* Set the global registers with default ether type value */
1379 if (!pf->support_multi_driver) {
1380 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1382 if (ret != I40E_SUCCESS) {
1384 "Failed to set the default outer "
1386 goto err_setup_pf_switch;
1390 /* PF setup, which includes VSI setup */
1391 ret = i40e_pf_setup(pf);
1393 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1394 goto err_setup_pf_switch;
1397 /* reset all stats of the device, including pf and main vsi */
1398 i40e_dev_stats_reset(dev);
1402 /* Disable double vlan by default */
1403 i40e_vsi_config_double_vlan(vsi, FALSE);
1405 /* Disable S-TAG identification when floating_veb is disabled */
1406 if (!pf->floating_veb) {
1407 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1408 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1409 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1410 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1414 if (!vsi->max_macaddrs)
1415 len = ETHER_ADDR_LEN;
1417 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1419 /* Should be after VSI initialized */
1420 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1421 if (!dev->data->mac_addrs) {
1423 "Failed to allocated memory for storing mac address");
1426 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1427 &dev->data->mac_addrs[0]);
1429 /* Init dcb to sw mode by default */
1430 ret = i40e_dcb_init_configure(dev, TRUE);
1431 if (ret != I40E_SUCCESS) {
1432 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1433 pf->flags &= ~I40E_FLAG_DCB;
1435 /* Update HW struct after DCB configuration */
1438 /* initialize pf host driver to setup SRIOV resource if applicable */
1439 i40e_pf_host_init(dev);
1441 /* register callback func to eal lib */
1442 rte_intr_callback_register(intr_handle,
1443 i40e_dev_interrupt_handler, dev);
1445 /* configure and enable device interrupt */
1446 i40e_pf_config_irq0(hw, TRUE);
1447 i40e_pf_enable_irq0(hw);
1449 /* enable uio intr after callback register */
1450 rte_intr_enable(intr_handle);
1452 /* By default disable flexible payload in global configuration */
1453 if (!pf->support_multi_driver)
1454 i40e_flex_payload_reg_set_default(hw);
1457 * Add an ethertype filter to drop all flow control frames transmitted
1458 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1461 i40e_add_tx_flow_control_drop_filter(pf);
1463 /* Set the max frame size to 0x2600 by default,
1464 * in case other drivers changed the default value.
1466 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1468 /* initialize mirror rule list */
1469 TAILQ_INIT(&pf->mirror_list);
1471 /* initialize Traffic Manager configuration */
1472 i40e_tm_conf_init(dev);
1474 /* Initialize customized information */
1475 i40e_init_customized_info(pf);
1477 ret = i40e_init_ethtype_filter_list(dev);
1479 goto err_init_ethtype_filter_list;
1480 ret = i40e_init_tunnel_filter_list(dev);
1482 goto err_init_tunnel_filter_list;
1483 ret = i40e_init_fdir_filter_list(dev);
1485 goto err_init_fdir_filter_list;
1487 /* initialize queue region configuration */
1488 i40e_init_queue_region_conf(dev);
1490 /* initialize rss configuration from rte_flow */
1491 memset(&pf->rss_info, 0,
1492 sizeof(struct i40e_rte_flow_rss_conf));
1496 err_init_fdir_filter_list:
1497 rte_free(pf->tunnel.hash_table);
1498 rte_free(pf->tunnel.hash_map);
1499 err_init_tunnel_filter_list:
1500 rte_free(pf->ethertype.hash_table);
1501 rte_free(pf->ethertype.hash_map);
1502 err_init_ethtype_filter_list:
1503 rte_free(dev->data->mac_addrs);
1505 i40e_vsi_release(pf->main_vsi);
1506 err_setup_pf_switch:
1508 err_configure_lan_hmc:
1509 (void)i40e_shutdown_lan_hmc(hw);
1511 i40e_res_pool_destroy(&pf->msix_pool);
1513 i40e_res_pool_destroy(&pf->qp_pool);
1516 err_get_capabilities:
1517 (void)i40e_shutdown_adminq(hw);
1523 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1525 struct i40e_ethertype_filter *p_ethertype;
1526 struct i40e_ethertype_rule *ethertype_rule;
1528 ethertype_rule = &pf->ethertype;
1529 /* Remove all ethertype filter rules and hash */
1530 if (ethertype_rule->hash_map)
1531 rte_free(ethertype_rule->hash_map);
1532 if (ethertype_rule->hash_table)
1533 rte_hash_free(ethertype_rule->hash_table);
1535 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1536 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1537 p_ethertype, rules);
1538 rte_free(p_ethertype);
1543 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1545 struct i40e_tunnel_filter *p_tunnel;
1546 struct i40e_tunnel_rule *tunnel_rule;
1548 tunnel_rule = &pf->tunnel;
1549 /* Remove all tunnel director rules and hash */
1550 if (tunnel_rule->hash_map)
1551 rte_free(tunnel_rule->hash_map);
1552 if (tunnel_rule->hash_table)
1553 rte_hash_free(tunnel_rule->hash_table);
1555 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1556 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1562 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1564 struct i40e_fdir_filter *p_fdir;
1565 struct i40e_fdir_info *fdir_info;
1567 fdir_info = &pf->fdir;
1568 /* Remove all flow director rules and hash */
1569 if (fdir_info->hash_map)
1570 rte_free(fdir_info->hash_map);
1571 if (fdir_info->hash_table)
1572 rte_hash_free(fdir_info->hash_table);
1574 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1575 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1580 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1583 * Disable by default flexible payload
1584 * for corresponding L2/L3/L4 layers.
1586 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1587 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1588 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1589 i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1593 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1596 struct rte_pci_device *pci_dev;
1597 struct rte_intr_handle *intr_handle;
1599 struct i40e_filter_control_settings settings;
1600 struct rte_flow *p_flow;
1602 uint8_t aq_fail = 0;
1605 PMD_INIT_FUNC_TRACE();
1607 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1610 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1611 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1613 intr_handle = &pci_dev->intr_handle;
1615 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1617 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1619 if (hw->adapter_stopped == 0)
1620 i40e_dev_close(dev);
1622 dev->dev_ops = NULL;
1623 dev->rx_pkt_burst = NULL;
1624 dev->tx_pkt_burst = NULL;
1626 /* Clear PXE mode */
1627 i40e_clear_pxe_mode(hw);
1629 /* Unconfigure filter control */
1630 memset(&settings, 0, sizeof(settings));
1631 ret = i40e_set_filter_control(hw, &settings);
1633 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1636 /* Disable flow control */
1637 hw->fc.requested_mode = I40E_FC_NONE;
1638 i40e_set_fc(hw, &aq_fail, TRUE);
1640 /* uninitialize pf host driver */
1641 i40e_pf_host_uninit(dev);
1643 rte_free(dev->data->mac_addrs);
1644 dev->data->mac_addrs = NULL;
1646 /* disable uio intr before callback unregister */
1647 rte_intr_disable(intr_handle);
1649 /* unregister callback func to eal lib */
1651 ret = rte_intr_callback_unregister(intr_handle,
1652 i40e_dev_interrupt_handler, dev);
1655 } else if (ret != -EAGAIN) {
1657 "intr callback unregister failed: %d",
1661 i40e_msec_delay(500);
1662 } while (retries++ < 5);
1664 i40e_rm_ethtype_filter_list(pf);
1665 i40e_rm_tunnel_filter_list(pf);
1666 i40e_rm_fdir_filter_list(pf);
1668 /* Remove all flows */
1669 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1670 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1674 /* Remove all Traffic Manager configuration */
1675 i40e_tm_conf_uninit(dev);
1681 i40e_dev_configure(struct rte_eth_dev *dev)
1683 struct i40e_adapter *ad =
1684 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1685 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1686 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1690 ret = i40e_dev_sync_phy_type(hw);
1694 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1695 * bulk allocation or vector Rx preconditions we will reset it.
1697 ad->rx_bulk_alloc_allowed = true;
1698 ad->rx_vec_allowed = true;
1699 ad->tx_simple_allowed = true;
1700 ad->tx_vec_allowed = true;
1702 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1703 ret = i40e_fdir_setup(pf);
1704 if (ret != I40E_SUCCESS) {
1705 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1708 ret = i40e_fdir_configure(dev);
1710 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1714 i40e_fdir_teardown(pf);
1716 ret = i40e_dev_init_vlan(dev);
1721 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1722 * RSS setting have different requirements.
1723 * General PMD driver call sequence are NIC init, configure,
1724 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1725 * will try to lookup the VSI that specific queue belongs to if VMDQ
1726 * applicable. So, VMDQ setting has to be done before
1727 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1728 * For RSS setting, it will try to calculate actual configured RX queue
1729 * number, which will be available after rx_queue_setup(). dev_start()
1730 * function is good to place RSS setup.
1732 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1733 ret = i40e_vmdq_setup(dev);
1738 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1739 ret = i40e_dcb_setup(dev);
1741 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1746 TAILQ_INIT(&pf->flow_list);
1751 /* need to release vmdq resource if exists */
1752 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1753 i40e_vsi_release(pf->vmdq[i].vsi);
1754 pf->vmdq[i].vsi = NULL;
1759 /* need to release fdir resource if exists */
1760 i40e_fdir_teardown(pf);
1765 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1767 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1769 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771 uint16_t msix_vect = vsi->msix_intr;
1774 for (i = 0; i < vsi->nb_qps; i++) {
1775 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1776 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1780 if (vsi->type != I40E_VSI_SRIOV) {
1781 if (!rte_intr_allow_others(intr_handle)) {
1782 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1783 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1785 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1788 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1789 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1791 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1796 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1797 vsi->user_param + (msix_vect - 1);
1799 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1800 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1802 I40E_WRITE_FLUSH(hw);
1806 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1807 int base_queue, int nb_queue,
1812 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1813 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1815 /* Bind all RX queues to allocated MSIX interrupt */
1816 for (i = 0; i < nb_queue; i++) {
1817 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1818 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1819 ((base_queue + i + 1) <<
1820 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1821 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1822 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1824 if (i == nb_queue - 1)
1825 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1826 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1829 /* Write first RX queue to Link list register as the head element */
1830 if (vsi->type != I40E_VSI_SRIOV) {
1832 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1833 pf->support_multi_driver);
1835 if (msix_vect == I40E_MISC_VEC_ID) {
1836 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1838 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1840 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1842 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1845 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1847 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1849 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1851 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1858 if (msix_vect == I40E_MISC_VEC_ID) {
1860 I40E_VPINT_LNKLST0(vsi->user_param),
1862 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1864 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1866 /* num_msix_vectors_vf needs to minus irq0 */
1867 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1868 vsi->user_param + (msix_vect - 1);
1870 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1872 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1874 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1878 I40E_WRITE_FLUSH(hw);
1882 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1884 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1885 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1886 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1887 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1888 uint16_t msix_vect = vsi->msix_intr;
1889 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1890 uint16_t queue_idx = 0;
1894 for (i = 0; i < vsi->nb_qps; i++) {
1895 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1896 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1899 /* VF bind interrupt */
1900 if (vsi->type == I40E_VSI_SRIOV) {
1901 __vsi_queues_bind_intr(vsi, msix_vect,
1902 vsi->base_queue, vsi->nb_qps,
1907 /* PF & VMDq bind interrupt */
1908 if (rte_intr_dp_is_en(intr_handle)) {
1909 if (vsi->type == I40E_VSI_MAIN) {
1912 } else if (vsi->type == I40E_VSI_VMDQ2) {
1913 struct i40e_vsi *main_vsi =
1914 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1915 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1920 for (i = 0; i < vsi->nb_used_qps; i++) {
1922 if (!rte_intr_allow_others(intr_handle))
1923 /* allow to share MISC_VEC_ID */
1924 msix_vect = I40E_MISC_VEC_ID;
1926 /* no enough msix_vect, map all to one */
1927 __vsi_queues_bind_intr(vsi, msix_vect,
1928 vsi->base_queue + i,
1929 vsi->nb_used_qps - i,
1931 for (; !!record && i < vsi->nb_used_qps; i++)
1932 intr_handle->intr_vec[queue_idx + i] =
1936 /* 1:1 queue/msix_vect mapping */
1937 __vsi_queues_bind_intr(vsi, msix_vect,
1938 vsi->base_queue + i, 1,
1941 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1949 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1951 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1952 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1953 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1954 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1955 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1956 uint16_t msix_intr, i;
1958 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1959 for (i = 0; i < vsi->nb_msix; i++) {
1960 msix_intr = vsi->msix_intr + i;
1961 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1962 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1963 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1964 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1967 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1968 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1969 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1970 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1972 I40E_WRITE_FLUSH(hw);
1976 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1978 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1979 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1980 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1981 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1982 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1983 uint16_t msix_intr, i;
1985 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1986 for (i = 0; i < vsi->nb_msix; i++) {
1987 msix_intr = vsi->msix_intr + i;
1988 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1989 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1992 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1993 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1995 I40E_WRITE_FLUSH(hw);
1998 static inline uint8_t
1999 i40e_parse_link_speeds(uint16_t link_speeds)
2001 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2003 if (link_speeds & ETH_LINK_SPEED_40G)
2004 link_speed |= I40E_LINK_SPEED_40GB;
2005 if (link_speeds & ETH_LINK_SPEED_25G)
2006 link_speed |= I40E_LINK_SPEED_25GB;
2007 if (link_speeds & ETH_LINK_SPEED_20G)
2008 link_speed |= I40E_LINK_SPEED_20GB;
2009 if (link_speeds & ETH_LINK_SPEED_10G)
2010 link_speed |= I40E_LINK_SPEED_10GB;
2011 if (link_speeds & ETH_LINK_SPEED_1G)
2012 link_speed |= I40E_LINK_SPEED_1GB;
2013 if (link_speeds & ETH_LINK_SPEED_100M)
2014 link_speed |= I40E_LINK_SPEED_100MB;
2020 i40e_phy_conf_link(struct i40e_hw *hw,
2022 uint8_t force_speed,
2025 enum i40e_status_code status;
2026 struct i40e_aq_get_phy_abilities_resp phy_ab;
2027 struct i40e_aq_set_phy_config phy_conf;
2028 enum i40e_aq_phy_type cnt;
2029 uint32_t phy_type_mask = 0;
2031 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2032 I40E_AQ_PHY_FLAG_PAUSE_RX |
2033 I40E_AQ_PHY_FLAG_PAUSE_RX |
2034 I40E_AQ_PHY_FLAG_LOW_POWER;
2035 const uint8_t advt = I40E_LINK_SPEED_40GB |
2036 I40E_LINK_SPEED_25GB |
2037 I40E_LINK_SPEED_10GB |
2038 I40E_LINK_SPEED_1GB |
2039 I40E_LINK_SPEED_100MB;
2043 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2048 /* If link already up, no need to set up again */
2049 if (is_up && phy_ab.phy_type != 0)
2050 return I40E_SUCCESS;
2052 memset(&phy_conf, 0, sizeof(phy_conf));
2054 /* bits 0-2 use the values from get_phy_abilities_resp */
2056 abilities |= phy_ab.abilities & mask;
2058 /* update ablities and speed */
2059 if (abilities & I40E_AQ_PHY_AN_ENABLED)
2060 phy_conf.link_speed = advt;
2062 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
2064 phy_conf.abilities = abilities;
2068 /* To enable link, phy_type mask needs to include each type */
2069 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
2070 phy_type_mask |= 1 << cnt;
2072 /* use get_phy_abilities_resp value for the rest */
2073 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2074 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2075 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2076 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2077 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2078 phy_conf.eee_capability = phy_ab.eee_capability;
2079 phy_conf.eeer = phy_ab.eeer_val;
2080 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2082 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2083 phy_ab.abilities, phy_ab.link_speed);
2084 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2085 phy_conf.abilities, phy_conf.link_speed);
2087 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2091 return I40E_SUCCESS;
2095 i40e_apply_link_speed(struct rte_eth_dev *dev)
2098 uint8_t abilities = 0;
2099 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2100 struct rte_eth_conf *conf = &dev->data->dev_conf;
2102 speed = i40e_parse_link_speeds(conf->link_speeds);
2103 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2104 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2105 abilities |= I40E_AQ_PHY_AN_ENABLED;
2106 abilities |= I40E_AQ_PHY_LINK_ENABLED;
2108 return i40e_phy_conf_link(hw, abilities, speed, true);
2112 i40e_dev_start(struct rte_eth_dev *dev)
2114 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2115 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2116 struct i40e_vsi *main_vsi = pf->main_vsi;
2118 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2119 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2120 uint32_t intr_vector = 0;
2121 struct i40e_vsi *vsi;
2123 hw->adapter_stopped = 0;
2125 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2127 "Invalid link_speeds for port %u, autonegotiation disabled",
2128 dev->data->port_id);
2132 rte_intr_disable(intr_handle);
2134 if ((rte_intr_cap_multiple(intr_handle) ||
2135 !RTE_ETH_DEV_SRIOV(dev).active) &&
2136 dev->data->dev_conf.intr_conf.rxq != 0) {
2137 intr_vector = dev->data->nb_rx_queues;
2138 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2143 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2144 intr_handle->intr_vec =
2145 rte_zmalloc("intr_vec",
2146 dev->data->nb_rx_queues * sizeof(int),
2148 if (!intr_handle->intr_vec) {
2150 "Failed to allocate %d rx_queues intr_vec",
2151 dev->data->nb_rx_queues);
2156 /* Initialize VSI */
2157 ret = i40e_dev_rxtx_init(pf);
2158 if (ret != I40E_SUCCESS) {
2159 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2163 /* Map queues with MSIX interrupt */
2164 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2165 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2166 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2167 i40e_vsi_enable_queues_intr(main_vsi);
2169 /* Map VMDQ VSI queues with MSIX interrupt */
2170 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2171 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2172 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2173 I40E_ITR_INDEX_DEFAULT);
2174 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2177 /* enable FDIR MSIX interrupt */
2178 if (pf->fdir.fdir_vsi) {
2179 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2180 I40E_ITR_INDEX_NONE);
2181 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2184 /* Enable all queues which have been configured */
2185 ret = i40e_dev_switch_queues(pf, TRUE);
2186 if (ret != I40E_SUCCESS) {
2187 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2191 /* Enable receiving broadcast packets */
2192 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2193 if (ret != I40E_SUCCESS)
2194 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2196 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2197 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2199 if (ret != I40E_SUCCESS)
2200 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2203 /* Enable the VLAN promiscuous mode. */
2205 for (i = 0; i < pf->vf_num; i++) {
2206 vsi = pf->vfs[i].vsi;
2207 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2212 /* Enable mac loopback mode */
2213 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2214 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2215 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2216 if (ret != I40E_SUCCESS) {
2217 PMD_DRV_LOG(ERR, "fail to set loopback link");
2222 /* Apply link configure */
2223 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2224 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2225 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2226 ETH_LINK_SPEED_40G)) {
2227 PMD_DRV_LOG(ERR, "Invalid link setting");
2230 ret = i40e_apply_link_speed(dev);
2231 if (I40E_SUCCESS != ret) {
2232 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2236 if (!rte_intr_allow_others(intr_handle)) {
2237 rte_intr_callback_unregister(intr_handle,
2238 i40e_dev_interrupt_handler,
2240 /* configure and enable device interrupt */
2241 i40e_pf_config_irq0(hw, FALSE);
2242 i40e_pf_enable_irq0(hw);
2244 if (dev->data->dev_conf.intr_conf.lsc != 0)
2246 "lsc won't enable because of no intr multiplex");
2248 ret = i40e_aq_set_phy_int_mask(hw,
2249 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2250 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2251 I40E_AQ_EVENT_MEDIA_NA), NULL);
2252 if (ret != I40E_SUCCESS)
2253 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2255 /* Call get_link_info aq commond to enable/disable LSE */
2256 i40e_dev_link_update(dev, 0);
2259 /* enable uio intr after callback register */
2260 rte_intr_enable(intr_handle);
2262 i40e_filter_restore(pf);
2264 if (pf->tm_conf.root && !pf->tm_conf.committed)
2265 PMD_DRV_LOG(WARNING,
2266 "please call hierarchy_commit() "
2267 "before starting the port");
2269 return I40E_SUCCESS;
2272 i40e_dev_switch_queues(pf, FALSE);
2273 i40e_dev_clear_queues(dev);
2279 i40e_dev_stop(struct rte_eth_dev *dev)
2281 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2282 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283 struct i40e_vsi *main_vsi = pf->main_vsi;
2284 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2285 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2288 if (hw->adapter_stopped == 1)
2290 /* Disable all queues */
2291 i40e_dev_switch_queues(pf, FALSE);
2293 /* un-map queues with interrupt registers */
2294 i40e_vsi_disable_queues_intr(main_vsi);
2295 i40e_vsi_queues_unbind_intr(main_vsi);
2297 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2298 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2299 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2302 if (pf->fdir.fdir_vsi) {
2303 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2304 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2306 /* Clear all queues and release memory */
2307 i40e_dev_clear_queues(dev);
2310 i40e_dev_set_link_down(dev);
2312 if (!rte_intr_allow_others(intr_handle))
2313 /* resume to the default handler */
2314 rte_intr_callback_register(intr_handle,
2315 i40e_dev_interrupt_handler,
2318 /* Clean datapath event and queue/vec mapping */
2319 rte_intr_efd_disable(intr_handle);
2320 if (intr_handle->intr_vec) {
2321 rte_free(intr_handle->intr_vec);
2322 intr_handle->intr_vec = NULL;
2325 /* reset hierarchy commit */
2326 pf->tm_conf.committed = false;
2328 hw->adapter_stopped = 1;
2332 i40e_dev_close(struct rte_eth_dev *dev)
2334 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2335 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2337 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2338 struct i40e_mirror_rule *p_mirror;
2343 PMD_INIT_FUNC_TRACE();
2347 /* Remove all mirror rules */
2348 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2349 ret = i40e_aq_del_mirror_rule(hw,
2350 pf->main_vsi->veb->seid,
2351 p_mirror->rule_type,
2353 p_mirror->num_entries,
2356 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2357 "status = %d, aq_err = %d.", ret,
2358 hw->aq.asq_last_status);
2360 /* remove mirror software resource anyway */
2361 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2363 pf->nb_mirror_rule--;
2366 i40e_dev_free_queues(dev);
2368 /* Disable interrupt */
2369 i40e_pf_disable_irq0(hw);
2370 rte_intr_disable(intr_handle);
2372 i40e_fdir_teardown(pf);
2374 /* shutdown and destroy the HMC */
2375 i40e_shutdown_lan_hmc(hw);
2377 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2378 i40e_vsi_release(pf->vmdq[i].vsi);
2379 pf->vmdq[i].vsi = NULL;
2384 /* release all the existing VSIs and VEBs */
2385 i40e_vsi_release(pf->main_vsi);
2387 /* shutdown the adminq */
2388 i40e_aq_queue_shutdown(hw, true);
2389 i40e_shutdown_adminq(hw);
2391 i40e_res_pool_destroy(&pf->qp_pool);
2392 i40e_res_pool_destroy(&pf->msix_pool);
2394 /* Disable flexible payload in global configuration */
2395 if (!pf->support_multi_driver)
2396 i40e_flex_payload_reg_set_default(hw);
2398 /* force a PF reset to clean anything leftover */
2399 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2400 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2401 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2402 I40E_WRITE_FLUSH(hw);
2406 * Reset PF device only to re-initialize resources in PMD layer
2409 i40e_dev_reset(struct rte_eth_dev *dev)
2413 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2414 * its VF to make them align with it. The detailed notification
2415 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2416 * To avoid unexpected behavior in VF, currently reset of PF with
2417 * SR-IOV activation is not supported. It might be supported later.
2419 if (dev->data->sriov.active)
2422 ret = eth_i40e_dev_uninit(dev);
2426 ret = eth_i40e_dev_init(dev, NULL);
2432 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2434 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2435 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2436 struct i40e_vsi *vsi = pf->main_vsi;
2439 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2441 if (status != I40E_SUCCESS)
2442 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2444 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2446 if (status != I40E_SUCCESS)
2447 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2452 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2454 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2455 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456 struct i40e_vsi *vsi = pf->main_vsi;
2459 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2461 if (status != I40E_SUCCESS)
2462 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2464 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2466 if (status != I40E_SUCCESS)
2467 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2471 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2473 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2474 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475 struct i40e_vsi *vsi = pf->main_vsi;
2478 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2479 if (ret != I40E_SUCCESS)
2480 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2484 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2486 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2487 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2488 struct i40e_vsi *vsi = pf->main_vsi;
2491 if (dev->data->promiscuous == 1)
2492 return; /* must remain in all_multicast mode */
2494 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2495 vsi->seid, FALSE, NULL);
2496 if (ret != I40E_SUCCESS)
2497 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2501 * Set device link up.
2504 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2506 /* re-apply link speed setting */
2507 return i40e_apply_link_speed(dev);
2511 * Set device link down.
2514 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2516 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2517 uint8_t abilities = 0;
2518 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2520 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2521 return i40e_phy_conf_link(hw, abilities, speed, false);
2524 static __rte_always_inline void
2525 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2527 /* Link status registers and values*/
2528 #define I40E_PRTMAC_LINKSTA 0x001E2420
2529 #define I40E_REG_LINK_UP 0x40000080
2530 #define I40E_PRTMAC_MACC 0x001E24E0
2531 #define I40E_REG_MACC_25GB 0x00020000
2532 #define I40E_REG_SPEED_MASK 0x38000000
2533 #define I40E_REG_SPEED_100MB 0x00000000
2534 #define I40E_REG_SPEED_1GB 0x08000000
2535 #define I40E_REG_SPEED_10GB 0x10000000
2536 #define I40E_REG_SPEED_20GB 0x20000000
2537 #define I40E_REG_SPEED_25_40GB 0x18000000
2538 uint32_t link_speed;
2541 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2542 link_speed = reg_val & I40E_REG_SPEED_MASK;
2543 reg_val &= I40E_REG_LINK_UP;
2544 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2546 if (unlikely(link->link_status == 0))
2549 /* Parse the link status */
2550 switch (link_speed) {
2551 case I40E_REG_SPEED_100MB:
2552 link->link_speed = ETH_SPEED_NUM_100M;
2554 case I40E_REG_SPEED_1GB:
2555 link->link_speed = ETH_SPEED_NUM_1G;
2557 case I40E_REG_SPEED_10GB:
2558 link->link_speed = ETH_SPEED_NUM_10G;
2560 case I40E_REG_SPEED_20GB:
2561 link->link_speed = ETH_SPEED_NUM_20G;
2563 case I40E_REG_SPEED_25_40GB:
2564 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2566 if (reg_val & I40E_REG_MACC_25GB)
2567 link->link_speed = ETH_SPEED_NUM_25G;
2569 link->link_speed = ETH_SPEED_NUM_40G;
2573 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2578 static __rte_always_inline void
2579 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2582 #define CHECK_INTERVAL 100 /* 100ms */
2583 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2584 uint32_t rep_cnt = MAX_REPEAT_TIME;
2585 struct i40e_link_status link_status;
2588 memset(&link_status, 0, sizeof(link_status));
2591 memset(&link_status, 0, sizeof(link_status));
2593 /* Get link status information from hardware */
2594 status = i40e_aq_get_link_info(hw, enable_lse,
2595 &link_status, NULL);
2596 if (unlikely(status != I40E_SUCCESS)) {
2597 link->link_speed = ETH_SPEED_NUM_100M;
2598 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2599 PMD_DRV_LOG(ERR, "Failed to get link info");
2603 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2604 if (unlikely(link->link_status != 0))
2607 rte_delay_ms(CHECK_INTERVAL);
2608 } while (--rep_cnt);
2610 /* Parse the link status */
2611 switch (link_status.link_speed) {
2612 case I40E_LINK_SPEED_100MB:
2613 link->link_speed = ETH_SPEED_NUM_100M;
2615 case I40E_LINK_SPEED_1GB:
2616 link->link_speed = ETH_SPEED_NUM_1G;
2618 case I40E_LINK_SPEED_10GB:
2619 link->link_speed = ETH_SPEED_NUM_10G;
2621 case I40E_LINK_SPEED_20GB:
2622 link->link_speed = ETH_SPEED_NUM_20G;
2624 case I40E_LINK_SPEED_25GB:
2625 link->link_speed = ETH_SPEED_NUM_25G;
2627 case I40E_LINK_SPEED_40GB:
2628 link->link_speed = ETH_SPEED_NUM_40G;
2631 link->link_speed = ETH_SPEED_NUM_100M;
2637 i40e_dev_link_update(struct rte_eth_dev *dev,
2638 int wait_to_complete)
2640 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2641 struct rte_eth_link link;
2642 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2645 memset(&link, 0, sizeof(link));
2647 /* i40e uses full duplex only */
2648 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2649 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2650 ETH_LINK_SPEED_FIXED);
2652 if (!wait_to_complete)
2653 update_link_no_wait(hw, &link);
2655 update_link_wait(hw, &link, enable_lse);
2657 ret = rte_eth_linkstatus_set(dev, &link);
2658 i40e_notify_all_vfs_link_status(dev);
2663 /* Get all the statistics of a VSI */
2665 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2667 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2668 struct i40e_eth_stats *nes = &vsi->eth_stats;
2669 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2670 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2672 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2673 vsi->offset_loaded, &oes->rx_bytes,
2675 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2676 vsi->offset_loaded, &oes->rx_unicast,
2678 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2679 vsi->offset_loaded, &oes->rx_multicast,
2680 &nes->rx_multicast);
2681 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2682 vsi->offset_loaded, &oes->rx_broadcast,
2683 &nes->rx_broadcast);
2684 /* exclude CRC bytes */
2685 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2686 nes->rx_broadcast) * ETHER_CRC_LEN;
2688 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2689 &oes->rx_discards, &nes->rx_discards);
2690 /* GLV_REPC not supported */
2691 /* GLV_RMPC not supported */
2692 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2693 &oes->rx_unknown_protocol,
2694 &nes->rx_unknown_protocol);
2695 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2696 vsi->offset_loaded, &oes->tx_bytes,
2698 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2699 vsi->offset_loaded, &oes->tx_unicast,
2701 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2702 vsi->offset_loaded, &oes->tx_multicast,
2703 &nes->tx_multicast);
2704 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2705 vsi->offset_loaded, &oes->tx_broadcast,
2706 &nes->tx_broadcast);
2707 /* GLV_TDPC not supported */
2708 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2709 &oes->tx_errors, &nes->tx_errors);
2710 vsi->offset_loaded = true;
2712 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2714 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2715 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2716 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2717 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2718 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2719 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2720 nes->rx_unknown_protocol);
2721 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2722 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2723 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2724 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2725 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2726 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2727 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2732 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2735 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2736 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2738 /* Get rx/tx bytes of internal transfer packets */
2739 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2740 I40E_GLV_GORCL(hw->port),
2742 &pf->internal_stats_offset.rx_bytes,
2743 &pf->internal_stats.rx_bytes);
2745 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2746 I40E_GLV_GOTCL(hw->port),
2748 &pf->internal_stats_offset.tx_bytes,
2749 &pf->internal_stats.tx_bytes);
2750 /* Get total internal rx packet count */
2751 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2752 I40E_GLV_UPRCL(hw->port),
2754 &pf->internal_stats_offset.rx_unicast,
2755 &pf->internal_stats.rx_unicast);
2756 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2757 I40E_GLV_MPRCL(hw->port),
2759 &pf->internal_stats_offset.rx_multicast,
2760 &pf->internal_stats.rx_multicast);
2761 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2762 I40E_GLV_BPRCL(hw->port),
2764 &pf->internal_stats_offset.rx_broadcast,
2765 &pf->internal_stats.rx_broadcast);
2766 /* Get total internal tx packet count */
2767 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2768 I40E_GLV_UPTCL(hw->port),
2770 &pf->internal_stats_offset.tx_unicast,
2771 &pf->internal_stats.tx_unicast);
2772 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2773 I40E_GLV_MPTCL(hw->port),
2775 &pf->internal_stats_offset.tx_multicast,
2776 &pf->internal_stats.tx_multicast);
2777 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2778 I40E_GLV_BPTCL(hw->port),
2780 &pf->internal_stats_offset.tx_broadcast,
2781 &pf->internal_stats.tx_broadcast);
2783 /* exclude CRC size */
2784 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2785 pf->internal_stats.rx_multicast +
2786 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2788 /* Get statistics of struct i40e_eth_stats */
2789 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2790 I40E_GLPRT_GORCL(hw->port),
2791 pf->offset_loaded, &os->eth.rx_bytes,
2793 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2794 I40E_GLPRT_UPRCL(hw->port),
2795 pf->offset_loaded, &os->eth.rx_unicast,
2796 &ns->eth.rx_unicast);
2797 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2798 I40E_GLPRT_MPRCL(hw->port),
2799 pf->offset_loaded, &os->eth.rx_multicast,
2800 &ns->eth.rx_multicast);
2801 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2802 I40E_GLPRT_BPRCL(hw->port),
2803 pf->offset_loaded, &os->eth.rx_broadcast,
2804 &ns->eth.rx_broadcast);
2805 /* Workaround: CRC size should not be included in byte statistics,
2806 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2808 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2809 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2811 /* exclude internal rx bytes
2812 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2813 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2815 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2817 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2818 ns->eth.rx_bytes = 0;
2820 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2822 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2823 ns->eth.rx_unicast = 0;
2825 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2827 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2828 ns->eth.rx_multicast = 0;
2830 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2832 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2833 ns->eth.rx_broadcast = 0;
2835 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2837 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2838 pf->offset_loaded, &os->eth.rx_discards,
2839 &ns->eth.rx_discards);
2840 /* GLPRT_REPC not supported */
2841 /* GLPRT_RMPC not supported */
2842 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2844 &os->eth.rx_unknown_protocol,
2845 &ns->eth.rx_unknown_protocol);
2846 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2847 I40E_GLPRT_GOTCL(hw->port),
2848 pf->offset_loaded, &os->eth.tx_bytes,
2850 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2851 I40E_GLPRT_UPTCL(hw->port),
2852 pf->offset_loaded, &os->eth.tx_unicast,
2853 &ns->eth.tx_unicast);
2854 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2855 I40E_GLPRT_MPTCL(hw->port),
2856 pf->offset_loaded, &os->eth.tx_multicast,
2857 &ns->eth.tx_multicast);
2858 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2859 I40E_GLPRT_BPTCL(hw->port),
2860 pf->offset_loaded, &os->eth.tx_broadcast,
2861 &ns->eth.tx_broadcast);
2862 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2863 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2865 /* exclude internal tx bytes
2866 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2867 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2869 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2871 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2872 ns->eth.tx_bytes = 0;
2874 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2876 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2877 ns->eth.tx_unicast = 0;
2879 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2881 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2882 ns->eth.tx_multicast = 0;
2884 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2886 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2887 ns->eth.tx_broadcast = 0;
2889 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2891 /* GLPRT_TEPC not supported */
2893 /* additional port specific stats */
2894 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2895 pf->offset_loaded, &os->tx_dropped_link_down,
2896 &ns->tx_dropped_link_down);
2897 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2898 pf->offset_loaded, &os->crc_errors,
2900 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2901 pf->offset_loaded, &os->illegal_bytes,
2902 &ns->illegal_bytes);
2903 /* GLPRT_ERRBC not supported */
2904 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2905 pf->offset_loaded, &os->mac_local_faults,
2906 &ns->mac_local_faults);
2907 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2908 pf->offset_loaded, &os->mac_remote_faults,
2909 &ns->mac_remote_faults);
2910 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2911 pf->offset_loaded, &os->rx_length_errors,
2912 &ns->rx_length_errors);
2913 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2914 pf->offset_loaded, &os->link_xon_rx,
2916 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2917 pf->offset_loaded, &os->link_xoff_rx,
2919 for (i = 0; i < 8; i++) {
2920 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2922 &os->priority_xon_rx[i],
2923 &ns->priority_xon_rx[i]);
2924 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2926 &os->priority_xoff_rx[i],
2927 &ns->priority_xoff_rx[i]);
2929 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2930 pf->offset_loaded, &os->link_xon_tx,
2932 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2933 pf->offset_loaded, &os->link_xoff_tx,
2935 for (i = 0; i < 8; i++) {
2936 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2938 &os->priority_xon_tx[i],
2939 &ns->priority_xon_tx[i]);
2940 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2942 &os->priority_xoff_tx[i],
2943 &ns->priority_xoff_tx[i]);
2944 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2946 &os->priority_xon_2_xoff[i],
2947 &ns->priority_xon_2_xoff[i]);
2949 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2950 I40E_GLPRT_PRC64L(hw->port),
2951 pf->offset_loaded, &os->rx_size_64,
2953 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2954 I40E_GLPRT_PRC127L(hw->port),
2955 pf->offset_loaded, &os->rx_size_127,
2957 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2958 I40E_GLPRT_PRC255L(hw->port),
2959 pf->offset_loaded, &os->rx_size_255,
2961 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2962 I40E_GLPRT_PRC511L(hw->port),
2963 pf->offset_loaded, &os->rx_size_511,
2965 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2966 I40E_GLPRT_PRC1023L(hw->port),
2967 pf->offset_loaded, &os->rx_size_1023,
2969 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2970 I40E_GLPRT_PRC1522L(hw->port),
2971 pf->offset_loaded, &os->rx_size_1522,
2973 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2974 I40E_GLPRT_PRC9522L(hw->port),
2975 pf->offset_loaded, &os->rx_size_big,
2977 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2978 pf->offset_loaded, &os->rx_undersize,
2980 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2981 pf->offset_loaded, &os->rx_fragments,
2983 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2984 pf->offset_loaded, &os->rx_oversize,
2986 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2987 pf->offset_loaded, &os->rx_jabber,
2989 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2990 I40E_GLPRT_PTC64L(hw->port),
2991 pf->offset_loaded, &os->tx_size_64,
2993 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2994 I40E_GLPRT_PTC127L(hw->port),
2995 pf->offset_loaded, &os->tx_size_127,
2997 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2998 I40E_GLPRT_PTC255L(hw->port),
2999 pf->offset_loaded, &os->tx_size_255,
3001 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3002 I40E_GLPRT_PTC511L(hw->port),
3003 pf->offset_loaded, &os->tx_size_511,
3005 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3006 I40E_GLPRT_PTC1023L(hw->port),
3007 pf->offset_loaded, &os->tx_size_1023,
3009 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3010 I40E_GLPRT_PTC1522L(hw->port),
3011 pf->offset_loaded, &os->tx_size_1522,
3013 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3014 I40E_GLPRT_PTC9522L(hw->port),
3015 pf->offset_loaded, &os->tx_size_big,
3017 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3019 &os->fd_sb_match, &ns->fd_sb_match);
3020 /* GLPRT_MSPDC not supported */
3021 /* GLPRT_XEC not supported */
3023 pf->offset_loaded = true;
3026 i40e_update_vsi_stats(pf->main_vsi);
3029 /* Get all statistics of a port */
3031 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3033 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3034 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3035 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3038 /* call read registers - updates values, now write them to struct */
3039 i40e_read_stats_registers(pf, hw);
3041 stats->ipackets = ns->eth.rx_unicast +
3042 ns->eth.rx_multicast +
3043 ns->eth.rx_broadcast -
3044 ns->eth.rx_discards -
3045 pf->main_vsi->eth_stats.rx_discards;
3046 stats->opackets = ns->eth.tx_unicast +
3047 ns->eth.tx_multicast +
3048 ns->eth.tx_broadcast;
3049 stats->ibytes = ns->eth.rx_bytes;
3050 stats->obytes = ns->eth.tx_bytes;
3051 stats->oerrors = ns->eth.tx_errors +
3052 pf->main_vsi->eth_stats.tx_errors;
3055 stats->imissed = ns->eth.rx_discards +
3056 pf->main_vsi->eth_stats.rx_discards;
3057 stats->ierrors = ns->crc_errors +
3058 ns->rx_length_errors + ns->rx_undersize +
3059 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3061 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3062 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3063 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3064 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3065 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3066 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3067 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3068 ns->eth.rx_unknown_protocol);
3069 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3070 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3071 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3072 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3073 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3074 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3076 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3077 ns->tx_dropped_link_down);
3078 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3079 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3081 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3082 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3083 ns->mac_local_faults);
3084 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3085 ns->mac_remote_faults);
3086 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3087 ns->rx_length_errors);
3088 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3089 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3090 for (i = 0; i < 8; i++) {
3091 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3092 i, ns->priority_xon_rx[i]);
3093 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3094 i, ns->priority_xoff_rx[i]);
3096 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3097 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3098 for (i = 0; i < 8; i++) {
3099 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3100 i, ns->priority_xon_tx[i]);
3101 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3102 i, ns->priority_xoff_tx[i]);
3103 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3104 i, ns->priority_xon_2_xoff[i]);
3106 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3107 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3108 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3109 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3110 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3111 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3112 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3113 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3114 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3115 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3116 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3117 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3118 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3119 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3120 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3121 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3122 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3123 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3124 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3125 ns->mac_short_packet_dropped);
3126 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3127 ns->checksum_error);
3128 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3129 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3133 /* Reset the statistics */
3135 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3137 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3138 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3140 /* Mark PF and VSI stats to update the offset, aka "reset" */
3141 pf->offset_loaded = false;
3143 pf->main_vsi->offset_loaded = false;
3145 /* read the stats, reading current register values into offset */
3146 i40e_read_stats_registers(pf, hw);
3150 i40e_xstats_calc_num(void)
3152 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3153 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3154 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3157 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3158 struct rte_eth_xstat_name *xstats_names,
3159 __rte_unused unsigned limit)
3164 if (xstats_names == NULL)
3165 return i40e_xstats_calc_num();
3167 /* Note: limit checked in rte_eth_xstats_names() */
3169 /* Get stats from i40e_eth_stats struct */
3170 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3171 snprintf(xstats_names[count].name,
3172 sizeof(xstats_names[count].name),
3173 "%s", rte_i40e_stats_strings[i].name);
3177 /* Get individiual stats from i40e_hw_port struct */
3178 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3179 snprintf(xstats_names[count].name,
3180 sizeof(xstats_names[count].name),
3181 "%s", rte_i40e_hw_port_strings[i].name);
3185 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3186 for (prio = 0; prio < 8; prio++) {
3187 snprintf(xstats_names[count].name,
3188 sizeof(xstats_names[count].name),
3189 "rx_priority%u_%s", prio,
3190 rte_i40e_rxq_prio_strings[i].name);
3195 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3196 for (prio = 0; prio < 8; prio++) {
3197 snprintf(xstats_names[count].name,
3198 sizeof(xstats_names[count].name),
3199 "tx_priority%u_%s", prio,
3200 rte_i40e_txq_prio_strings[i].name);
3208 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3211 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3212 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3213 unsigned i, count, prio;
3214 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3216 count = i40e_xstats_calc_num();
3220 i40e_read_stats_registers(pf, hw);
3227 /* Get stats from i40e_eth_stats struct */
3228 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3229 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3230 rte_i40e_stats_strings[i].offset);
3231 xstats[count].id = count;
3235 /* Get individiual stats from i40e_hw_port struct */
3236 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3237 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3238 rte_i40e_hw_port_strings[i].offset);
3239 xstats[count].id = count;
3243 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3244 for (prio = 0; prio < 8; prio++) {
3245 xstats[count].value =
3246 *(uint64_t *)(((char *)hw_stats) +
3247 rte_i40e_rxq_prio_strings[i].offset +
3248 (sizeof(uint64_t) * prio));
3249 xstats[count].id = count;
3254 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3255 for (prio = 0; prio < 8; prio++) {
3256 xstats[count].value =
3257 *(uint64_t *)(((char *)hw_stats) +
3258 rte_i40e_txq_prio_strings[i].offset +
3259 (sizeof(uint64_t) * prio));
3260 xstats[count].id = count;
3269 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3270 __rte_unused uint16_t queue_id,
3271 __rte_unused uint8_t stat_idx,
3272 __rte_unused uint8_t is_rx)
3274 PMD_INIT_FUNC_TRACE();
3280 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3282 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288 full_ver = hw->nvm.oem_ver;
3289 ver = (u8)(full_ver >> 24);
3290 build = (u16)((full_ver >> 8) & 0xffff);
3291 patch = (u8)(full_ver & 0xff);
3293 ret = snprintf(fw_version, fw_size,
3294 "%d.%d%d 0x%08x %d.%d.%d",
3295 ((hw->nvm.version >> 12) & 0xf),
3296 ((hw->nvm.version >> 4) & 0xff),
3297 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3300 ret += 1; /* add the size of '\0' */
3301 if (fw_size < (u32)ret)
3308 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3310 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3311 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312 struct i40e_vsi *vsi = pf->main_vsi;
3313 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3315 dev_info->max_rx_queues = vsi->nb_qps;
3316 dev_info->max_tx_queues = vsi->nb_qps;
3317 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3318 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3319 dev_info->max_mac_addrs = vsi->max_macaddrs;
3320 dev_info->max_vfs = pci_dev->max_vfs;
3321 dev_info->rx_queue_offload_capa = 0;
3322 dev_info->rx_offload_capa =
3323 DEV_RX_OFFLOAD_VLAN_STRIP |
3324 DEV_RX_OFFLOAD_QINQ_STRIP |
3325 DEV_RX_OFFLOAD_IPV4_CKSUM |
3326 DEV_RX_OFFLOAD_UDP_CKSUM |
3327 DEV_RX_OFFLOAD_TCP_CKSUM |
3328 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3329 DEV_RX_OFFLOAD_CRC_STRIP |
3330 DEV_RX_OFFLOAD_VLAN_EXTEND |
3331 DEV_RX_OFFLOAD_VLAN_FILTER |
3332 DEV_RX_OFFLOAD_JUMBO_FRAME;
3334 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3335 dev_info->tx_offload_capa =
3336 DEV_TX_OFFLOAD_VLAN_INSERT |
3337 DEV_TX_OFFLOAD_QINQ_INSERT |
3338 DEV_TX_OFFLOAD_IPV4_CKSUM |
3339 DEV_TX_OFFLOAD_UDP_CKSUM |
3340 DEV_TX_OFFLOAD_TCP_CKSUM |
3341 DEV_TX_OFFLOAD_SCTP_CKSUM |
3342 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3343 DEV_TX_OFFLOAD_TCP_TSO |
3344 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3345 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3346 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3347 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3348 DEV_TX_OFFLOAD_MULTI_SEGS |
3349 dev_info->tx_queue_offload_capa;
3350 dev_info->dev_capa =
3351 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3352 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3354 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3356 dev_info->reta_size = pf->hash_lut_size;
3357 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3359 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3361 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3362 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3363 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3365 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3370 dev_info->default_txconf = (struct rte_eth_txconf) {
3372 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3373 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3374 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3376 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3377 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3381 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3382 .nb_max = I40E_MAX_RING_DESC,
3383 .nb_min = I40E_MIN_RING_DESC,
3384 .nb_align = I40E_ALIGN_RING_DESC,
3387 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3388 .nb_max = I40E_MAX_RING_DESC,
3389 .nb_min = I40E_MIN_RING_DESC,
3390 .nb_align = I40E_ALIGN_RING_DESC,
3391 .nb_seg_max = I40E_TX_MAX_SEG,
3392 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3395 if (pf->flags & I40E_FLAG_VMDQ) {
3396 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3397 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3398 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3399 pf->max_nb_vmdq_vsi;
3400 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3401 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3402 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3405 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3407 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3408 dev_info->default_rxportconf.nb_queues = 2;
3409 dev_info->default_txportconf.nb_queues = 2;
3410 if (dev->data->nb_rx_queues == 1)
3411 dev_info->default_rxportconf.ring_size = 2048;
3413 dev_info->default_rxportconf.ring_size = 1024;
3414 if (dev->data->nb_tx_queues == 1)
3415 dev_info->default_txportconf.ring_size = 1024;
3417 dev_info->default_txportconf.ring_size = 512;
3419 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3421 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3422 dev_info->default_rxportconf.nb_queues = 1;
3423 dev_info->default_txportconf.nb_queues = 1;
3424 dev_info->default_rxportconf.ring_size = 256;
3425 dev_info->default_txportconf.ring_size = 256;
3428 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3429 dev_info->default_rxportconf.nb_queues = 1;
3430 dev_info->default_txportconf.nb_queues = 1;
3431 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3432 dev_info->default_rxportconf.ring_size = 512;
3433 dev_info->default_txportconf.ring_size = 256;
3435 dev_info->default_rxportconf.ring_size = 256;
3436 dev_info->default_txportconf.ring_size = 256;
3439 dev_info->default_rxportconf.burst_size = 32;
3440 dev_info->default_txportconf.burst_size = 32;
3444 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3446 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3447 struct i40e_vsi *vsi = pf->main_vsi;
3448 PMD_INIT_FUNC_TRACE();
3451 return i40e_vsi_add_vlan(vsi, vlan_id);
3453 return i40e_vsi_delete_vlan(vsi, vlan_id);
3457 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3458 enum rte_vlan_type vlan_type,
3459 uint16_t tpid, int qinq)
3461 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3464 uint16_t reg_id = 3;
3468 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3472 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3474 if (ret != I40E_SUCCESS) {
3476 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3481 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3484 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3485 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3486 if (reg_r == reg_w) {
3487 PMD_DRV_LOG(DEBUG, "No need to write");
3491 ret = i40e_aq_debug_write_global_register(hw,
3492 I40E_GL_SWT_L2TAGCTRL(reg_id),
3494 if (ret != I40E_SUCCESS) {
3496 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3501 "Global register 0x%08x is changed with value 0x%08x",
3502 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3504 i40e_global_cfg_warning(I40E_WARNING_TPID);
3510 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3511 enum rte_vlan_type vlan_type,
3514 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3515 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3516 int qinq = dev->data->dev_conf.rxmode.offloads &
3517 DEV_RX_OFFLOAD_VLAN_EXTEND;
3520 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3521 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3522 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3524 "Unsupported vlan type.");
3528 if (pf->support_multi_driver) {
3529 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3533 /* 802.1ad frames ability is added in NVM API 1.7*/
3534 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3536 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3537 hw->first_tag = rte_cpu_to_le_16(tpid);
3538 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3539 hw->second_tag = rte_cpu_to_le_16(tpid);
3541 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3542 hw->second_tag = rte_cpu_to_le_16(tpid);
3544 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3545 if (ret != I40E_SUCCESS) {
3547 "Set switch config failed aq_err: %d",
3548 hw->aq.asq_last_status);
3552 /* If NVM API < 1.7, keep the register setting */
3553 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3560 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3562 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3563 struct i40e_vsi *vsi = pf->main_vsi;
3564 struct rte_eth_rxmode *rxmode;
3566 rxmode = &dev->data->dev_conf.rxmode;
3567 if (mask & ETH_VLAN_FILTER_MASK) {
3568 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3569 i40e_vsi_config_vlan_filter(vsi, TRUE);
3571 i40e_vsi_config_vlan_filter(vsi, FALSE);
3574 if (mask & ETH_VLAN_STRIP_MASK) {
3575 /* Enable or disable VLAN stripping */
3576 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3577 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3579 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3582 if (mask & ETH_VLAN_EXTEND_MASK) {
3583 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3584 i40e_vsi_config_double_vlan(vsi, TRUE);
3585 /* Set global registers with default ethertype. */
3586 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3588 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3592 i40e_vsi_config_double_vlan(vsi, FALSE);
3599 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3600 __rte_unused uint16_t queue,
3601 __rte_unused int on)
3603 PMD_INIT_FUNC_TRACE();
3607 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3609 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3610 struct i40e_vsi *vsi = pf->main_vsi;
3611 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3612 struct i40e_vsi_vlan_pvid_info info;
3614 memset(&info, 0, sizeof(info));
3617 info.config.pvid = pvid;
3619 info.config.reject.tagged =
3620 data->dev_conf.txmode.hw_vlan_reject_tagged;
3621 info.config.reject.untagged =
3622 data->dev_conf.txmode.hw_vlan_reject_untagged;
3625 return i40e_vsi_vlan_pvid_set(vsi, &info);
3629 i40e_dev_led_on(struct rte_eth_dev *dev)
3631 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3632 uint32_t mode = i40e_led_get(hw);
3635 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3641 i40e_dev_led_off(struct rte_eth_dev *dev)
3643 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3644 uint32_t mode = i40e_led_get(hw);
3647 i40e_led_set(hw, 0, false);
3653 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3655 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3656 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3658 fc_conf->pause_time = pf->fc_conf.pause_time;
3660 /* read out from register, in case they are modified by other port */
3661 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3662 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3663 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3664 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3666 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3667 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3669 /* Return current mode according to actual setting*/
3670 switch (hw->fc.current_mode) {
3672 fc_conf->mode = RTE_FC_FULL;
3674 case I40E_FC_TX_PAUSE:
3675 fc_conf->mode = RTE_FC_TX_PAUSE;
3677 case I40E_FC_RX_PAUSE:
3678 fc_conf->mode = RTE_FC_RX_PAUSE;
3682 fc_conf->mode = RTE_FC_NONE;
3689 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3691 uint32_t mflcn_reg, fctrl_reg, reg;
3692 uint32_t max_high_water;
3693 uint8_t i, aq_failure;
3697 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3698 [RTE_FC_NONE] = I40E_FC_NONE,
3699 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3700 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3701 [RTE_FC_FULL] = I40E_FC_FULL
3704 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3706 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3707 if ((fc_conf->high_water > max_high_water) ||
3708 (fc_conf->high_water < fc_conf->low_water)) {
3710 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3715 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3717 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3719 pf->fc_conf.pause_time = fc_conf->pause_time;
3720 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3721 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3723 PMD_INIT_FUNC_TRACE();
3725 /* All the link flow control related enable/disable register
3726 * configuration is handle by the F/W
3728 err = i40e_set_fc(hw, &aq_failure, true);
3732 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3733 /* Configure flow control refresh threshold,
3734 * the value for stat_tx_pause_refresh_timer[8]
3735 * is used for global pause operation.
3739 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3740 pf->fc_conf.pause_time);
3742 /* configure the timer value included in transmitted pause
3744 * the value for stat_tx_pause_quanta[8] is used for global
3747 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3748 pf->fc_conf.pause_time);
3750 fctrl_reg = I40E_READ_REG(hw,
3751 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3753 if (fc_conf->mac_ctrl_frame_fwd != 0)
3754 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3756 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3758 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3761 /* Configure pause time (2 TCs per register) */
3762 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3763 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3764 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3766 /* Configure flow control refresh threshold value */
3767 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3768 pf->fc_conf.pause_time / 2);
3770 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3772 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3773 *depending on configuration
3775 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3776 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3777 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3779 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3780 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3783 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3786 if (!pf->support_multi_driver) {
3787 /* config water marker both based on the packets and bytes */
3788 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3789 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3790 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3791 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3792 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3793 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3794 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3795 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3797 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3798 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3800 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3803 "Water marker configuration is not supported.");
3806 I40E_WRITE_FLUSH(hw);
3812 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3813 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3815 PMD_INIT_FUNC_TRACE();
3820 /* Add a MAC address, and update filters */
3822 i40e_macaddr_add(struct rte_eth_dev *dev,
3823 struct ether_addr *mac_addr,
3824 __rte_unused uint32_t index,
3827 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3828 struct i40e_mac_filter_info mac_filter;
3829 struct i40e_vsi *vsi;
3830 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3833 /* If VMDQ not enabled or configured, return */
3834 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3835 !pf->nb_cfg_vmdq_vsi)) {
3836 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3837 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3842 if (pool > pf->nb_cfg_vmdq_vsi) {
3843 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3844 pool, pf->nb_cfg_vmdq_vsi);
3848 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3849 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3850 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3852 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3857 vsi = pf->vmdq[pool - 1].vsi;
3859 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3860 if (ret != I40E_SUCCESS) {
3861 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3867 /* Remove a MAC address, and update filters */
3869 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3871 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3872 struct i40e_vsi *vsi;
3873 struct rte_eth_dev_data *data = dev->data;
3874 struct ether_addr *macaddr;
3879 macaddr = &(data->mac_addrs[index]);
3881 pool_sel = dev->data->mac_pool_sel[index];
3883 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3884 if (pool_sel & (1ULL << i)) {
3888 /* No VMDQ pool enabled or configured */
3889 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3890 (i > pf->nb_cfg_vmdq_vsi)) {
3892 "No VMDQ pool enabled/configured");
3895 vsi = pf->vmdq[i - 1].vsi;
3897 ret = i40e_vsi_delete_mac(vsi, macaddr);
3900 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3907 /* Set perfect match or hash match of MAC and VLAN for a VF */
3909 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3910 struct rte_eth_mac_filter *filter,
3914 struct i40e_mac_filter_info mac_filter;
3915 struct ether_addr old_mac;
3916 struct ether_addr *new_mac;
3917 struct i40e_pf_vf *vf = NULL;
3922 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3925 hw = I40E_PF_TO_HW(pf);
3927 if (filter == NULL) {
3928 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3932 new_mac = &filter->mac_addr;
3934 if (is_zero_ether_addr(new_mac)) {
3935 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3939 vf_id = filter->dst_id;
3941 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3942 PMD_DRV_LOG(ERR, "Invalid argument.");
3945 vf = &pf->vfs[vf_id];
3947 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3948 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3953 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3954 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3956 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3959 mac_filter.filter_type = filter->filter_type;
3960 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3961 if (ret != I40E_SUCCESS) {
3962 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3965 ether_addr_copy(new_mac, &pf->dev_addr);
3967 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3969 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3970 if (ret != I40E_SUCCESS) {
3971 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3975 /* Clear device address as it has been removed */
3976 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3977 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3983 /* MAC filter handle */
3985 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3988 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3989 struct rte_eth_mac_filter *filter;
3990 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3991 int ret = I40E_NOT_SUPPORTED;
3993 filter = (struct rte_eth_mac_filter *)(arg);
3995 switch (filter_op) {
3996 case RTE_ETH_FILTER_NOP:
3999 case RTE_ETH_FILTER_ADD:
4000 i40e_pf_disable_irq0(hw);
4002 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4003 i40e_pf_enable_irq0(hw);
4005 case RTE_ETH_FILTER_DELETE:
4006 i40e_pf_disable_irq0(hw);
4008 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4009 i40e_pf_enable_irq0(hw);
4012 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4013 ret = I40E_ERR_PARAM;
4021 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4023 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4024 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4031 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4032 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4035 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4039 uint32_t *lut_dw = (uint32_t *)lut;
4040 uint16_t i, lut_size_dw = lut_size / 4;
4042 if (vsi->type == I40E_VSI_SRIOV) {
4043 for (i = 0; i <= lut_size_dw; i++) {
4044 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4045 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4048 for (i = 0; i < lut_size_dw; i++)
4049 lut_dw[i] = I40E_READ_REG(hw,
4058 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4067 pf = I40E_VSI_TO_PF(vsi);
4068 hw = I40E_VSI_TO_HW(vsi);
4070 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4071 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4074 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4078 uint32_t *lut_dw = (uint32_t *)lut;
4079 uint16_t i, lut_size_dw = lut_size / 4;
4081 if (vsi->type == I40E_VSI_SRIOV) {
4082 for (i = 0; i < lut_size_dw; i++)
4085 I40E_VFQF_HLUT1(i, vsi->user_param),
4088 for (i = 0; i < lut_size_dw; i++)
4089 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4092 I40E_WRITE_FLUSH(hw);
4099 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4100 struct rte_eth_rss_reta_entry64 *reta_conf,
4103 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4104 uint16_t i, lut_size = pf->hash_lut_size;
4105 uint16_t idx, shift;
4109 if (reta_size != lut_size ||
4110 reta_size > ETH_RSS_RETA_SIZE_512) {
4112 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4113 reta_size, lut_size);
4117 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4119 PMD_DRV_LOG(ERR, "No memory can be allocated");
4122 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4125 for (i = 0; i < reta_size; i++) {
4126 idx = i / RTE_RETA_GROUP_SIZE;
4127 shift = i % RTE_RETA_GROUP_SIZE;
4128 if (reta_conf[idx].mask & (1ULL << shift))
4129 lut[i] = reta_conf[idx].reta[shift];
4131 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4140 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4141 struct rte_eth_rss_reta_entry64 *reta_conf,
4144 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4145 uint16_t i, lut_size = pf->hash_lut_size;
4146 uint16_t idx, shift;
4150 if (reta_size != lut_size ||
4151 reta_size > ETH_RSS_RETA_SIZE_512) {
4153 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4154 reta_size, lut_size);
4158 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4160 PMD_DRV_LOG(ERR, "No memory can be allocated");
4164 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4167 for (i = 0; i < reta_size; i++) {
4168 idx = i / RTE_RETA_GROUP_SIZE;
4169 shift = i % RTE_RETA_GROUP_SIZE;
4170 if (reta_conf[idx].mask & (1ULL << shift))
4171 reta_conf[idx].reta[shift] = lut[i];
4181 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4182 * @hw: pointer to the HW structure
4183 * @mem: pointer to mem struct to fill out
4184 * @size: size of memory requested
4185 * @alignment: what to align the allocation to
4187 enum i40e_status_code
4188 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4189 struct i40e_dma_mem *mem,
4193 const struct rte_memzone *mz = NULL;
4194 char z_name[RTE_MEMZONE_NAMESIZE];
4197 return I40E_ERR_PARAM;
4199 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4200 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4201 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4203 return I40E_ERR_NO_MEMORY;
4208 mem->zone = (const void *)mz;
4210 "memzone %s allocated with physical address: %"PRIu64,
4213 return I40E_SUCCESS;
4217 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4218 * @hw: pointer to the HW structure
4219 * @mem: ptr to mem struct to free
4221 enum i40e_status_code
4222 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4223 struct i40e_dma_mem *mem)
4226 return I40E_ERR_PARAM;
4229 "memzone %s to be freed with physical address: %"PRIu64,
4230 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4231 rte_memzone_free((const struct rte_memzone *)mem->zone);
4236 return I40E_SUCCESS;
4240 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4241 * @hw: pointer to the HW structure
4242 * @mem: pointer to mem struct to fill out
4243 * @size: size of memory requested
4245 enum i40e_status_code
4246 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4247 struct i40e_virt_mem *mem,
4251 return I40E_ERR_PARAM;
4254 mem->va = rte_zmalloc("i40e", size, 0);
4257 return I40E_SUCCESS;
4259 return I40E_ERR_NO_MEMORY;
4263 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4264 * @hw: pointer to the HW structure
4265 * @mem: pointer to mem struct to free
4267 enum i40e_status_code
4268 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4269 struct i40e_virt_mem *mem)
4272 return I40E_ERR_PARAM;
4277 return I40E_SUCCESS;
4281 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4283 rte_spinlock_init(&sp->spinlock);
4287 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4289 rte_spinlock_lock(&sp->spinlock);
4293 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4295 rte_spinlock_unlock(&sp->spinlock);
4299 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4305 * Get the hardware capabilities, which will be parsed
4306 * and saved into struct i40e_hw.
4309 i40e_get_cap(struct i40e_hw *hw)
4311 struct i40e_aqc_list_capabilities_element_resp *buf;
4312 uint16_t len, size = 0;
4315 /* Calculate a huge enough buff for saving response data temporarily */
4316 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4317 I40E_MAX_CAP_ELE_NUM;
4318 buf = rte_zmalloc("i40e", len, 0);
4320 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4321 return I40E_ERR_NO_MEMORY;
4324 /* Get, parse the capabilities and save it to hw */
4325 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4326 i40e_aqc_opc_list_func_capabilities, NULL);
4327 if (ret != I40E_SUCCESS)
4328 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4330 /* Free the temporary buffer after being used */
4336 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4337 #define QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
4339 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4347 pf = (struct i40e_pf *)opaque;
4351 num = strtoul(value, &end, 0);
4352 if (errno != 0 || end == value || *end != 0) {
4353 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4354 "kept the value = %hu", value, pf->vf_nb_qp_max);
4358 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4359 pf->vf_nb_qp_max = (uint16_t)num;
4361 /* here return 0 to make next valid same argument work */
4362 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4363 "power of 2 and equal or less than 16 !, Now it is "
4364 "kept the value = %hu", num, pf->vf_nb_qp_max);
4369 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4371 static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4372 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4373 struct rte_kvargs *kvlist;
4375 /* set default queue number per VF as 4 */
4376 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4378 if (dev->device->devargs == NULL)
4381 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4385 if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4386 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4387 "the first invalid or last valid one is used !",
4388 QUEUE_NUM_PER_VF_ARG);
4390 rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4391 i40e_pf_parse_vf_queue_number_handler, pf);
4393 rte_kvargs_free(kvlist);
4399 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4401 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4402 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4403 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4404 uint16_t qp_count = 0, vsi_count = 0;
4406 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4407 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4411 i40e_pf_config_vf_rxq_number(dev);
4413 /* Add the parameter init for LFC */
4414 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4415 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4416 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4418 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4419 pf->max_num_vsi = hw->func_caps.num_vsis;
4420 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4421 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4423 /* FDir queue/VSI allocation */
4424 pf->fdir_qp_offset = 0;
4425 if (hw->func_caps.fd) {
4426 pf->flags |= I40E_FLAG_FDIR;
4427 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4429 pf->fdir_nb_qps = 0;
4431 qp_count += pf->fdir_nb_qps;
4434 /* LAN queue/VSI allocation */
4435 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4436 if (!hw->func_caps.rss) {
4439 pf->flags |= I40E_FLAG_RSS;
4440 if (hw->mac.type == I40E_MAC_X722)
4441 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4442 pf->lan_nb_qps = pf->lan_nb_qp_max;
4444 qp_count += pf->lan_nb_qps;
4447 /* VF queue/VSI allocation */
4448 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4449 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4450 pf->flags |= I40E_FLAG_SRIOV;
4451 pf->vf_nb_qps = pf->vf_nb_qp_max;
4452 pf->vf_num = pci_dev->max_vfs;
4454 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4455 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4460 qp_count += pf->vf_nb_qps * pf->vf_num;
4461 vsi_count += pf->vf_num;
4463 /* VMDq queue/VSI allocation */
4464 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4465 pf->vmdq_nb_qps = 0;
4466 pf->max_nb_vmdq_vsi = 0;
4467 if (hw->func_caps.vmdq) {
4468 if (qp_count < hw->func_caps.num_tx_qp &&
4469 vsi_count < hw->func_caps.num_vsis) {
4470 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4471 qp_count) / pf->vmdq_nb_qp_max;
4473 /* Limit the maximum number of VMDq vsi to the maximum
4474 * ethdev can support
4476 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4477 hw->func_caps.num_vsis - vsi_count);
4478 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4480 if (pf->max_nb_vmdq_vsi) {
4481 pf->flags |= I40E_FLAG_VMDQ;
4482 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4484 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4485 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4486 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4489 "No enough queues left for VMDq");
4492 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4495 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4496 vsi_count += pf->max_nb_vmdq_vsi;
4498 if (hw->func_caps.dcb)
4499 pf->flags |= I40E_FLAG_DCB;
4501 if (qp_count > hw->func_caps.num_tx_qp) {
4503 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4504 qp_count, hw->func_caps.num_tx_qp);
4507 if (vsi_count > hw->func_caps.num_vsis) {
4509 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4510 vsi_count, hw->func_caps.num_vsis);
4518 i40e_pf_get_switch_config(struct i40e_pf *pf)
4520 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4521 struct i40e_aqc_get_switch_config_resp *switch_config;
4522 struct i40e_aqc_switch_config_element_resp *element;
4523 uint16_t start_seid = 0, num_reported;
4526 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4527 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4528 if (!switch_config) {
4529 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4533 /* Get the switch configurations */
4534 ret = i40e_aq_get_switch_config(hw, switch_config,
4535 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4536 if (ret != I40E_SUCCESS) {
4537 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4540 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4541 if (num_reported != 1) { /* The number should be 1 */
4542 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4546 /* Parse the switch configuration elements */
4547 element = &(switch_config->element[0]);
4548 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4549 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4550 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4552 PMD_DRV_LOG(INFO, "Unknown element type");
4555 rte_free(switch_config);
4561 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4564 struct pool_entry *entry;
4566 if (pool == NULL || num == 0)
4569 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4570 if (entry == NULL) {
4571 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4575 /* queue heap initialize */
4576 pool->num_free = num;
4577 pool->num_alloc = 0;
4579 LIST_INIT(&pool->alloc_list);
4580 LIST_INIT(&pool->free_list);
4582 /* Initialize element */
4586 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4591 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4593 struct pool_entry *entry, *next_entry;
4598 for (entry = LIST_FIRST(&pool->alloc_list);
4599 entry && (next_entry = LIST_NEXT(entry, next), 1);
4600 entry = next_entry) {
4601 LIST_REMOVE(entry, next);
4605 for (entry = LIST_FIRST(&pool->free_list);
4606 entry && (next_entry = LIST_NEXT(entry, next), 1);
4607 entry = next_entry) {
4608 LIST_REMOVE(entry, next);
4613 pool->num_alloc = 0;
4615 LIST_INIT(&pool->alloc_list);
4616 LIST_INIT(&pool->free_list);
4620 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4623 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4624 uint32_t pool_offset;
4628 PMD_DRV_LOG(ERR, "Invalid parameter");
4632 pool_offset = base - pool->base;
4633 /* Lookup in alloc list */
4634 LIST_FOREACH(entry, &pool->alloc_list, next) {
4635 if (entry->base == pool_offset) {
4636 valid_entry = entry;
4637 LIST_REMOVE(entry, next);
4642 /* Not find, return */
4643 if (valid_entry == NULL) {
4644 PMD_DRV_LOG(ERR, "Failed to find entry");
4649 * Found it, move it to free list and try to merge.
4650 * In order to make merge easier, always sort it by qbase.
4651 * Find adjacent prev and last entries.
4654 LIST_FOREACH(entry, &pool->free_list, next) {
4655 if (entry->base > valid_entry->base) {
4663 /* Try to merge with next one*/
4665 /* Merge with next one */
4666 if (valid_entry->base + valid_entry->len == next->base) {
4667 next->base = valid_entry->base;
4668 next->len += valid_entry->len;
4669 rte_free(valid_entry);
4676 /* Merge with previous one */
4677 if (prev->base + prev->len == valid_entry->base) {
4678 prev->len += valid_entry->len;
4679 /* If it merge with next one, remove next node */
4681 LIST_REMOVE(valid_entry, next);
4682 rte_free(valid_entry);
4684 rte_free(valid_entry);
4690 /* Not find any entry to merge, insert */
4693 LIST_INSERT_AFTER(prev, valid_entry, next);
4694 else if (next != NULL)
4695 LIST_INSERT_BEFORE(next, valid_entry, next);
4696 else /* It's empty list, insert to head */
4697 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4700 pool->num_free += valid_entry->len;
4701 pool->num_alloc -= valid_entry->len;
4707 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4710 struct pool_entry *entry, *valid_entry;
4712 if (pool == NULL || num == 0) {
4713 PMD_DRV_LOG(ERR, "Invalid parameter");
4717 if (pool->num_free < num) {
4718 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4719 num, pool->num_free);
4724 /* Lookup in free list and find most fit one */
4725 LIST_FOREACH(entry, &pool->free_list, next) {
4726 if (entry->len >= num) {
4728 if (entry->len == num) {
4729 valid_entry = entry;
4732 if (valid_entry == NULL || valid_entry->len > entry->len)
4733 valid_entry = entry;
4737 /* Not find one to satisfy the request, return */
4738 if (valid_entry == NULL) {
4739 PMD_DRV_LOG(ERR, "No valid entry found");
4743 * The entry have equal queue number as requested,
4744 * remove it from alloc_list.
4746 if (valid_entry->len == num) {
4747 LIST_REMOVE(valid_entry, next);
4750 * The entry have more numbers than requested,
4751 * create a new entry for alloc_list and minus its
4752 * queue base and number in free_list.
4754 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4755 if (entry == NULL) {
4757 "Failed to allocate memory for resource pool");
4760 entry->base = valid_entry->base;
4762 valid_entry->base += num;
4763 valid_entry->len -= num;
4764 valid_entry = entry;
4767 /* Insert it into alloc list, not sorted */
4768 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4770 pool->num_free -= valid_entry->len;
4771 pool->num_alloc += valid_entry->len;
4773 return valid_entry->base + pool->base;
4777 * bitmap_is_subset - Check whether src2 is subset of src1
4780 bitmap_is_subset(uint8_t src1, uint8_t src2)
4782 return !((src1 ^ src2) & src2);
4785 static enum i40e_status_code
4786 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4788 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4790 /* If DCB is not supported, only default TC is supported */
4791 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4792 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4793 return I40E_NOT_SUPPORTED;
4796 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4798 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4799 hw->func_caps.enabled_tcmap, enabled_tcmap);
4800 return I40E_NOT_SUPPORTED;
4802 return I40E_SUCCESS;
4806 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4807 struct i40e_vsi_vlan_pvid_info *info)
4810 struct i40e_vsi_context ctxt;
4811 uint8_t vlan_flags = 0;
4814 if (vsi == NULL || info == NULL) {
4815 PMD_DRV_LOG(ERR, "invalid parameters");
4816 return I40E_ERR_PARAM;
4820 vsi->info.pvid = info->config.pvid;
4822 * If insert pvid is enabled, only tagged pkts are
4823 * allowed to be sent out.
4825 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4826 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4829 if (info->config.reject.tagged == 0)
4830 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4832 if (info->config.reject.untagged == 0)
4833 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4835 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4836 I40E_AQ_VSI_PVLAN_MODE_MASK);
4837 vsi->info.port_vlan_flags |= vlan_flags;
4838 vsi->info.valid_sections =
4839 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4840 memset(&ctxt, 0, sizeof(ctxt));
4841 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4842 ctxt.seid = vsi->seid;
4844 hw = I40E_VSI_TO_HW(vsi);
4845 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4846 if (ret != I40E_SUCCESS)
4847 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4853 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4855 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4857 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4859 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4860 if (ret != I40E_SUCCESS)
4864 PMD_DRV_LOG(ERR, "seid not valid");
4868 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4869 tc_bw_data.tc_valid_bits = enabled_tcmap;
4870 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4871 tc_bw_data.tc_bw_credits[i] =
4872 (enabled_tcmap & (1 << i)) ? 1 : 0;
4874 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4875 if (ret != I40E_SUCCESS) {
4876 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4880 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4881 sizeof(vsi->info.qs_handle));
4882 return I40E_SUCCESS;
4885 static enum i40e_status_code
4886 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4887 struct i40e_aqc_vsi_properties_data *info,
4888 uint8_t enabled_tcmap)
4890 enum i40e_status_code ret;
4891 int i, total_tc = 0;
4892 uint16_t qpnum_per_tc, bsf, qp_idx;
4894 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4895 if (ret != I40E_SUCCESS)
4898 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4899 if (enabled_tcmap & (1 << i))
4903 vsi->enabled_tc = enabled_tcmap;
4905 /* Number of queues per enabled TC */
4906 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4907 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4908 bsf = rte_bsf32(qpnum_per_tc);
4910 /* Adjust the queue number to actual queues that can be applied */
4911 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4912 vsi->nb_qps = qpnum_per_tc * total_tc;
4915 * Configure TC and queue mapping parameters, for enabled TC,
4916 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4917 * default queue will serve it.
4920 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4921 if (vsi->enabled_tc & (1 << i)) {
4922 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4923 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4924 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4925 qp_idx += qpnum_per_tc;
4927 info->tc_mapping[i] = 0;
4930 /* Associate queue number with VSI */
4931 if (vsi->type == I40E_VSI_SRIOV) {
4932 info->mapping_flags |=
4933 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4934 for (i = 0; i < vsi->nb_qps; i++)
4935 info->queue_mapping[i] =
4936 rte_cpu_to_le_16(vsi->base_queue + i);
4938 info->mapping_flags |=
4939 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4940 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4942 info->valid_sections |=
4943 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4945 return I40E_SUCCESS;
4949 i40e_veb_release(struct i40e_veb *veb)
4951 struct i40e_vsi *vsi;
4957 if (!TAILQ_EMPTY(&veb->head)) {
4958 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4961 /* associate_vsi field is NULL for floating VEB */
4962 if (veb->associate_vsi != NULL) {
4963 vsi = veb->associate_vsi;
4964 hw = I40E_VSI_TO_HW(vsi);
4966 vsi->uplink_seid = veb->uplink_seid;
4969 veb->associate_pf->main_vsi->floating_veb = NULL;
4970 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4973 i40e_aq_delete_element(hw, veb->seid, NULL);
4975 return I40E_SUCCESS;
4979 static struct i40e_veb *
4980 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4982 struct i40e_veb *veb;
4988 "veb setup failed, associated PF shouldn't null");
4991 hw = I40E_PF_TO_HW(pf);
4993 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4995 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4999 veb->associate_vsi = vsi;
5000 veb->associate_pf = pf;
5001 TAILQ_INIT(&veb->head);
5002 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5004 /* create floating veb if vsi is NULL */
5006 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5007 I40E_DEFAULT_TCMAP, false,
5008 &veb->seid, false, NULL);
5010 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5011 true, &veb->seid, false, NULL);
5014 if (ret != I40E_SUCCESS) {
5015 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5016 hw->aq.asq_last_status);
5019 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5021 /* get statistics index */
5022 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5023 &veb->stats_idx, NULL, NULL, NULL);
5024 if (ret != I40E_SUCCESS) {
5025 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5026 hw->aq.asq_last_status);
5029 /* Get VEB bandwidth, to be implemented */
5030 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5032 vsi->uplink_seid = veb->seid;
5041 i40e_vsi_release(struct i40e_vsi *vsi)
5045 struct i40e_vsi_list *vsi_list;
5048 struct i40e_mac_filter *f;
5049 uint16_t user_param;
5052 return I40E_SUCCESS;
5057 user_param = vsi->user_param;
5059 pf = I40E_VSI_TO_PF(vsi);
5060 hw = I40E_VSI_TO_HW(vsi);
5062 /* VSI has child to attach, release child first */
5064 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5065 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5068 i40e_veb_release(vsi->veb);
5071 if (vsi->floating_veb) {
5072 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5073 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5078 /* Remove all macvlan filters of the VSI */
5079 i40e_vsi_remove_all_macvlan_filter(vsi);
5080 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5083 if (vsi->type != I40E_VSI_MAIN &&
5084 ((vsi->type != I40E_VSI_SRIOV) ||
5085 !pf->floating_veb_list[user_param])) {
5086 /* Remove vsi from parent's sibling list */
5087 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5088 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5089 return I40E_ERR_PARAM;
5091 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5092 &vsi->sib_vsi_list, list);
5094 /* Remove all switch element of the VSI */
5095 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5096 if (ret != I40E_SUCCESS)
5097 PMD_DRV_LOG(ERR, "Failed to delete element");
5100 if ((vsi->type == I40E_VSI_SRIOV) &&
5101 pf->floating_veb_list[user_param]) {
5102 /* Remove vsi from parent's sibling list */
5103 if (vsi->parent_vsi == NULL ||
5104 vsi->parent_vsi->floating_veb == NULL) {
5105 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5106 return I40E_ERR_PARAM;
5108 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5109 &vsi->sib_vsi_list, list);
5111 /* Remove all switch element of the VSI */
5112 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5113 if (ret != I40E_SUCCESS)
5114 PMD_DRV_LOG(ERR, "Failed to delete element");
5117 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5119 if (vsi->type != I40E_VSI_SRIOV)
5120 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5123 return I40E_SUCCESS;
5127 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5129 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5130 struct i40e_aqc_remove_macvlan_element_data def_filter;
5131 struct i40e_mac_filter_info filter;
5134 if (vsi->type != I40E_VSI_MAIN)
5135 return I40E_ERR_CONFIG;
5136 memset(&def_filter, 0, sizeof(def_filter));
5137 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5139 def_filter.vlan_tag = 0;
5140 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5141 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5142 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5143 if (ret != I40E_SUCCESS) {
5144 struct i40e_mac_filter *f;
5145 struct ether_addr *mac;
5148 "Cannot remove the default macvlan filter");
5149 /* It needs to add the permanent mac into mac list */
5150 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5152 PMD_DRV_LOG(ERR, "failed to allocate memory");
5153 return I40E_ERR_NO_MEMORY;
5155 mac = &f->mac_info.mac_addr;
5156 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5158 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5159 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5164 rte_memcpy(&filter.mac_addr,
5165 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5166 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5167 return i40e_vsi_add_mac(vsi, &filter);
5171 * i40e_vsi_get_bw_config - Query VSI BW Information
5172 * @vsi: the VSI to be queried
5174 * Returns 0 on success, negative value on failure
5176 static enum i40e_status_code
5177 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5179 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5180 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5181 struct i40e_hw *hw = &vsi->adapter->hw;
5186 memset(&bw_config, 0, sizeof(bw_config));
5187 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5188 if (ret != I40E_SUCCESS) {
5189 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5190 hw->aq.asq_last_status);
5194 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5195 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5196 &ets_sla_config, NULL);
5197 if (ret != I40E_SUCCESS) {
5199 "VSI failed to get TC bandwdith configuration %u",
5200 hw->aq.asq_last_status);
5204 /* store and print out BW info */
5205 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5206 vsi->bw_info.bw_max = bw_config.max_bw;
5207 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5208 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5209 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5210 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5212 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5213 vsi->bw_info.bw_ets_share_credits[i] =
5214 ets_sla_config.share_credits[i];
5215 vsi->bw_info.bw_ets_credits[i] =
5216 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5217 /* 4 bits per TC, 4th bit is reserved */
5218 vsi->bw_info.bw_ets_max[i] =
5219 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5220 RTE_LEN2MASK(3, uint8_t));
5221 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5222 vsi->bw_info.bw_ets_share_credits[i]);
5223 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5224 vsi->bw_info.bw_ets_credits[i]);
5225 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5226 vsi->bw_info.bw_ets_max[i]);
5229 return I40E_SUCCESS;
5232 /* i40e_enable_pf_lb
5233 * @pf: pointer to the pf structure
5235 * allow loopback on pf
5238 i40e_enable_pf_lb(struct i40e_pf *pf)
5240 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5241 struct i40e_vsi_context ctxt;
5244 /* Use the FW API if FW >= v5.0 */
5245 if (hw->aq.fw_maj_ver < 5) {
5246 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5250 memset(&ctxt, 0, sizeof(ctxt));
5251 ctxt.seid = pf->main_vsi_seid;
5252 ctxt.pf_num = hw->pf_id;
5253 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5255 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5256 ret, hw->aq.asq_last_status);
5259 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5260 ctxt.info.valid_sections =
5261 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5262 ctxt.info.switch_id |=
5263 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5265 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5267 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5268 hw->aq.asq_last_status);
5273 i40e_vsi_setup(struct i40e_pf *pf,
5274 enum i40e_vsi_type type,
5275 struct i40e_vsi *uplink_vsi,
5276 uint16_t user_param)
5278 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5279 struct i40e_vsi *vsi;
5280 struct i40e_mac_filter_info filter;
5282 struct i40e_vsi_context ctxt;
5283 struct ether_addr broadcast =
5284 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5286 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5287 uplink_vsi == NULL) {
5289 "VSI setup failed, VSI link shouldn't be NULL");
5293 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5295 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5300 * 1.type is not MAIN and uplink vsi is not NULL
5301 * If uplink vsi didn't setup VEB, create one first under veb field
5302 * 2.type is SRIOV and the uplink is NULL
5303 * If floating VEB is NULL, create one veb under floating veb field
5306 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5307 uplink_vsi->veb == NULL) {
5308 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5310 if (uplink_vsi->veb == NULL) {
5311 PMD_DRV_LOG(ERR, "VEB setup failed");
5314 /* set ALLOWLOOPBACk on pf, when veb is created */
5315 i40e_enable_pf_lb(pf);
5318 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5319 pf->main_vsi->floating_veb == NULL) {
5320 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5322 if (pf->main_vsi->floating_veb == NULL) {
5323 PMD_DRV_LOG(ERR, "VEB setup failed");
5328 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5330 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5333 TAILQ_INIT(&vsi->mac_list);
5335 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5336 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5337 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5338 vsi->user_param = user_param;
5339 vsi->vlan_anti_spoof_on = 0;
5340 vsi->vlan_filter_on = 0;
5341 /* Allocate queues */
5342 switch (vsi->type) {
5343 case I40E_VSI_MAIN :
5344 vsi->nb_qps = pf->lan_nb_qps;
5346 case I40E_VSI_SRIOV :
5347 vsi->nb_qps = pf->vf_nb_qps;
5349 case I40E_VSI_VMDQ2:
5350 vsi->nb_qps = pf->vmdq_nb_qps;
5353 vsi->nb_qps = pf->fdir_nb_qps;
5359 * The filter status descriptor is reported in rx queue 0,
5360 * while the tx queue for fdir filter programming has no
5361 * such constraints, can be non-zero queues.
5362 * To simplify it, choose FDIR vsi use queue 0 pair.
5363 * To make sure it will use queue 0 pair, queue allocation
5364 * need be done before this function is called
5366 if (type != I40E_VSI_FDIR) {
5367 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5369 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5373 vsi->base_queue = ret;
5375 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5377 /* VF has MSIX interrupt in VF range, don't allocate here */
5378 if (type == I40E_VSI_MAIN) {
5379 if (pf->support_multi_driver) {
5380 /* If support multi-driver, need to use INT0 instead of
5381 * allocating from msix pool. The Msix pool is init from
5382 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5383 * to 1 without calling i40e_res_pool_alloc.
5388 ret = i40e_res_pool_alloc(&pf->msix_pool,
5389 RTE_MIN(vsi->nb_qps,
5390 RTE_MAX_RXTX_INTR_VEC_ID));
5393 "VSI MAIN %d get heap failed %d",
5395 goto fail_queue_alloc;
5397 vsi->msix_intr = ret;
5398 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5399 RTE_MAX_RXTX_INTR_VEC_ID);
5401 } else if (type != I40E_VSI_SRIOV) {
5402 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5404 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5405 goto fail_queue_alloc;
5407 vsi->msix_intr = ret;
5415 if (type == I40E_VSI_MAIN) {
5416 /* For main VSI, no need to add since it's default one */
5417 vsi->uplink_seid = pf->mac_seid;
5418 vsi->seid = pf->main_vsi_seid;
5419 /* Bind queues with specific MSIX interrupt */
5421 * Needs 2 interrupt at least, one for misc cause which will
5422 * enabled from OS side, Another for queues binding the
5423 * interrupt from device side only.
5426 /* Get default VSI parameters from hardware */
5427 memset(&ctxt, 0, sizeof(ctxt));
5428 ctxt.seid = vsi->seid;
5429 ctxt.pf_num = hw->pf_id;
5430 ctxt.uplink_seid = vsi->uplink_seid;
5432 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5433 if (ret != I40E_SUCCESS) {
5434 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5435 goto fail_msix_alloc;
5437 rte_memcpy(&vsi->info, &ctxt.info,
5438 sizeof(struct i40e_aqc_vsi_properties_data));
5439 vsi->vsi_id = ctxt.vsi_number;
5440 vsi->info.valid_sections = 0;
5442 /* Configure tc, enabled TC0 only */
5443 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5445 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5446 goto fail_msix_alloc;
5449 /* TC, queue mapping */
5450 memset(&ctxt, 0, sizeof(ctxt));
5451 vsi->info.valid_sections |=
5452 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5453 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5454 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5455 rte_memcpy(&ctxt.info, &vsi->info,
5456 sizeof(struct i40e_aqc_vsi_properties_data));
5457 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5458 I40E_DEFAULT_TCMAP);
5459 if (ret != I40E_SUCCESS) {
5461 "Failed to configure TC queue mapping");
5462 goto fail_msix_alloc;
5464 ctxt.seid = vsi->seid;
5465 ctxt.pf_num = hw->pf_id;
5466 ctxt.uplink_seid = vsi->uplink_seid;
5469 /* Update VSI parameters */
5470 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5471 if (ret != I40E_SUCCESS) {
5472 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5473 goto fail_msix_alloc;
5476 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5477 sizeof(vsi->info.tc_mapping));
5478 rte_memcpy(&vsi->info.queue_mapping,
5479 &ctxt.info.queue_mapping,
5480 sizeof(vsi->info.queue_mapping));
5481 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5482 vsi->info.valid_sections = 0;
5484 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5488 * Updating default filter settings are necessary to prevent
5489 * reception of tagged packets.
5490 * Some old firmware configurations load a default macvlan
5491 * filter which accepts both tagged and untagged packets.
5492 * The updating is to use a normal filter instead if needed.
5493 * For NVM 4.2.2 or after, the updating is not needed anymore.
5494 * The firmware with correct configurations load the default
5495 * macvlan filter which is expected and cannot be removed.
5497 i40e_update_default_filter_setting(vsi);
5498 i40e_config_qinq(hw, vsi);
5499 } else if (type == I40E_VSI_SRIOV) {
5500 memset(&ctxt, 0, sizeof(ctxt));
5502 * For other VSI, the uplink_seid equals to uplink VSI's
5503 * uplink_seid since they share same VEB
5505 if (uplink_vsi == NULL)
5506 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5508 vsi->uplink_seid = uplink_vsi->uplink_seid;
5509 ctxt.pf_num = hw->pf_id;
5510 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5511 ctxt.uplink_seid = vsi->uplink_seid;
5512 ctxt.connection_type = 0x1;
5513 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5515 /* Use the VEB configuration if FW >= v5.0 */
5516 if (hw->aq.fw_maj_ver >= 5) {
5517 /* Configure switch ID */
5518 ctxt.info.valid_sections |=
5519 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5520 ctxt.info.switch_id =
5521 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5524 /* Configure port/vlan */
5525 ctxt.info.valid_sections |=
5526 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5527 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5528 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5529 hw->func_caps.enabled_tcmap);
5530 if (ret != I40E_SUCCESS) {
5532 "Failed to configure TC queue mapping");
5533 goto fail_msix_alloc;
5536 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5537 ctxt.info.valid_sections |=
5538 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5540 * Since VSI is not created yet, only configure parameter,
5541 * will add vsi below.
5544 i40e_config_qinq(hw, vsi);
5545 } else if (type == I40E_VSI_VMDQ2) {
5546 memset(&ctxt, 0, sizeof(ctxt));
5548 * For other VSI, the uplink_seid equals to uplink VSI's
5549 * uplink_seid since they share same VEB
5551 vsi->uplink_seid = uplink_vsi->uplink_seid;
5552 ctxt.pf_num = hw->pf_id;
5554 ctxt.uplink_seid = vsi->uplink_seid;
5555 ctxt.connection_type = 0x1;
5556 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5558 ctxt.info.valid_sections |=
5559 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5560 /* user_param carries flag to enable loop back */
5562 ctxt.info.switch_id =
5563 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5564 ctxt.info.switch_id |=
5565 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5568 /* Configure port/vlan */
5569 ctxt.info.valid_sections |=
5570 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5571 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5572 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5573 I40E_DEFAULT_TCMAP);
5574 if (ret != I40E_SUCCESS) {
5576 "Failed to configure TC queue mapping");
5577 goto fail_msix_alloc;
5579 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5580 ctxt.info.valid_sections |=
5581 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5582 } else if (type == I40E_VSI_FDIR) {
5583 memset(&ctxt, 0, sizeof(ctxt));
5584 vsi->uplink_seid = uplink_vsi->uplink_seid;
5585 ctxt.pf_num = hw->pf_id;
5587 ctxt.uplink_seid = vsi->uplink_seid;
5588 ctxt.connection_type = 0x1; /* regular data port */
5589 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5590 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5591 I40E_DEFAULT_TCMAP);
5592 if (ret != I40E_SUCCESS) {
5594 "Failed to configure TC queue mapping.");
5595 goto fail_msix_alloc;
5597 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5598 ctxt.info.valid_sections |=
5599 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5601 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5602 goto fail_msix_alloc;
5605 if (vsi->type != I40E_VSI_MAIN) {
5606 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5607 if (ret != I40E_SUCCESS) {
5608 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5609 hw->aq.asq_last_status);
5610 goto fail_msix_alloc;
5612 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5613 vsi->info.valid_sections = 0;
5614 vsi->seid = ctxt.seid;
5615 vsi->vsi_id = ctxt.vsi_number;
5616 vsi->sib_vsi_list.vsi = vsi;
5617 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5618 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5619 &vsi->sib_vsi_list, list);
5621 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5622 &vsi->sib_vsi_list, list);
5626 /* MAC/VLAN configuration */
5627 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5628 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5630 ret = i40e_vsi_add_mac(vsi, &filter);
5631 if (ret != I40E_SUCCESS) {
5632 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5633 goto fail_msix_alloc;
5636 /* Get VSI BW information */
5637 i40e_vsi_get_bw_config(vsi);
5640 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5642 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5648 /* Configure vlan filter on or off */
5650 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5653 struct i40e_mac_filter *f;
5655 struct i40e_mac_filter_info *mac_filter;
5656 enum rte_mac_filter_type desired_filter;
5657 int ret = I40E_SUCCESS;
5660 /* Filter to match MAC and VLAN */
5661 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5663 /* Filter to match only MAC */
5664 desired_filter = RTE_MAC_PERFECT_MATCH;
5669 mac_filter = rte_zmalloc("mac_filter_info_data",
5670 num * sizeof(*mac_filter), 0);
5671 if (mac_filter == NULL) {
5672 PMD_DRV_LOG(ERR, "failed to allocate memory");
5673 return I40E_ERR_NO_MEMORY;
5678 /* Remove all existing mac */
5679 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5680 mac_filter[i] = f->mac_info;
5681 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5683 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5684 on ? "enable" : "disable");
5690 /* Override with new filter */
5691 for (i = 0; i < num; i++) {
5692 mac_filter[i].filter_type = desired_filter;
5693 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5695 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5696 on ? "enable" : "disable");
5702 rte_free(mac_filter);
5706 /* Configure vlan stripping on or off */
5708 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5710 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5711 struct i40e_vsi_context ctxt;
5713 int ret = I40E_SUCCESS;
5715 /* Check if it has been already on or off */
5716 if (vsi->info.valid_sections &
5717 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5719 if ((vsi->info.port_vlan_flags &
5720 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5721 return 0; /* already on */
5723 if ((vsi->info.port_vlan_flags &
5724 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5725 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5726 return 0; /* already off */
5731 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5733 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5734 vsi->info.valid_sections =
5735 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5736 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5737 vsi->info.port_vlan_flags |= vlan_flags;
5738 ctxt.seid = vsi->seid;
5739 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5740 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5742 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5743 on ? "enable" : "disable");
5749 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5751 struct rte_eth_dev_data *data = dev->data;
5755 /* Apply vlan offload setting */
5756 mask = ETH_VLAN_STRIP_MASK |
5757 ETH_VLAN_FILTER_MASK |
5758 ETH_VLAN_EXTEND_MASK;
5759 ret = i40e_vlan_offload_set(dev, mask);
5761 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5765 /* Apply pvid setting */
5766 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5767 data->dev_conf.txmode.hw_vlan_insert_pvid);
5769 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5775 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5777 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5779 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5783 i40e_update_flow_control(struct i40e_hw *hw)
5785 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5786 struct i40e_link_status link_status;
5787 uint32_t rxfc = 0, txfc = 0, reg;
5791 memset(&link_status, 0, sizeof(link_status));
5792 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5793 if (ret != I40E_SUCCESS) {
5794 PMD_DRV_LOG(ERR, "Failed to get link status information");
5795 goto write_reg; /* Disable flow control */
5798 an_info = hw->phy.link_info.an_info;
5799 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5800 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5801 ret = I40E_ERR_NOT_READY;
5802 goto write_reg; /* Disable flow control */
5805 * If link auto negotiation is enabled, flow control needs to
5806 * be configured according to it
5808 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5809 case I40E_LINK_PAUSE_RXTX:
5812 hw->fc.current_mode = I40E_FC_FULL;
5814 case I40E_AQ_LINK_PAUSE_RX:
5816 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5818 case I40E_AQ_LINK_PAUSE_TX:
5820 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5823 hw->fc.current_mode = I40E_FC_NONE;
5828 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5829 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5830 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5831 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5832 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5833 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5840 i40e_pf_setup(struct i40e_pf *pf)
5842 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5843 struct i40e_filter_control_settings settings;
5844 struct i40e_vsi *vsi;
5847 /* Clear all stats counters */
5848 pf->offset_loaded = FALSE;
5849 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5850 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5851 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5852 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5854 ret = i40e_pf_get_switch_config(pf);
5855 if (ret != I40E_SUCCESS) {
5856 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5860 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5862 PMD_INIT_LOG(WARNING,
5863 "failed to allocate switch domain for device %d", ret);
5865 if (pf->flags & I40E_FLAG_FDIR) {
5866 /* make queue allocated first, let FDIR use queue pair 0*/
5867 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5868 if (ret != I40E_FDIR_QUEUE_ID) {
5870 "queue allocation fails for FDIR: ret =%d",
5872 pf->flags &= ~I40E_FLAG_FDIR;
5875 /* main VSI setup */
5876 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5878 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5879 return I40E_ERR_NOT_READY;
5883 /* Configure filter control */
5884 memset(&settings, 0, sizeof(settings));
5885 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5886 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5887 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5888 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5890 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5891 hw->func_caps.rss_table_size);
5892 return I40E_ERR_PARAM;
5894 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5895 hw->func_caps.rss_table_size);
5896 pf->hash_lut_size = hw->func_caps.rss_table_size;
5898 /* Enable ethtype and macvlan filters */
5899 settings.enable_ethtype = TRUE;
5900 settings.enable_macvlan = TRUE;
5901 ret = i40e_set_filter_control(hw, &settings);
5903 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5906 /* Update flow control according to the auto negotiation */
5907 i40e_update_flow_control(hw);
5909 return I40E_SUCCESS;
5913 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5919 * Set or clear TX Queue Disable flags,
5920 * which is required by hardware.
5922 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5923 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5925 /* Wait until the request is finished */
5926 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5927 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5928 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5929 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5930 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5936 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5937 return I40E_SUCCESS; /* already on, skip next steps */
5939 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5940 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5942 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5943 return I40E_SUCCESS; /* already off, skip next steps */
5944 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5946 /* Write the register */
5947 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5948 /* Check the result */
5949 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5950 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5951 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5953 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5954 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5957 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5958 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5962 /* Check if it is timeout */
5963 if (j >= I40E_CHK_Q_ENA_COUNT) {
5964 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5965 (on ? "enable" : "disable"), q_idx);
5966 return I40E_ERR_TIMEOUT;
5969 return I40E_SUCCESS;
5972 /* Swith on or off the tx queues */
5974 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5976 struct rte_eth_dev_data *dev_data = pf->dev_data;
5977 struct i40e_tx_queue *txq;
5978 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5982 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5983 txq = dev_data->tx_queues[i];
5984 /* Don't operate the queue if not configured or
5985 * if starting only per queue */
5986 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5989 ret = i40e_dev_tx_queue_start(dev, i);
5991 ret = i40e_dev_tx_queue_stop(dev, i);
5992 if ( ret != I40E_SUCCESS)
5996 return I40E_SUCCESS;
6000 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6005 /* Wait until the request is finished */
6006 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6007 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6008 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6009 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6010 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6015 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6016 return I40E_SUCCESS; /* Already on, skip next steps */
6017 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6019 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6020 return I40E_SUCCESS; /* Already off, skip next steps */
6021 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6024 /* Write the register */
6025 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6026 /* Check the result */
6027 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6028 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6029 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6031 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6032 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6035 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6036 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6041 /* Check if it is timeout */
6042 if (j >= I40E_CHK_Q_ENA_COUNT) {
6043 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6044 (on ? "enable" : "disable"), q_idx);
6045 return I40E_ERR_TIMEOUT;
6048 return I40E_SUCCESS;
6050 /* Switch on or off the rx queues */
6052 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6054 struct rte_eth_dev_data *dev_data = pf->dev_data;
6055 struct i40e_rx_queue *rxq;
6056 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6060 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6061 rxq = dev_data->rx_queues[i];
6062 /* Don't operate the queue if not configured or
6063 * if starting only per queue */
6064 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6067 ret = i40e_dev_rx_queue_start(dev, i);
6069 ret = i40e_dev_rx_queue_stop(dev, i);
6070 if (ret != I40E_SUCCESS)
6074 return I40E_SUCCESS;
6077 /* Switch on or off all the rx/tx queues */
6079 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6084 /* enable rx queues before enabling tx queues */
6085 ret = i40e_dev_switch_rx_queues(pf, on);
6087 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6090 ret = i40e_dev_switch_tx_queues(pf, on);
6092 /* Stop tx queues before stopping rx queues */
6093 ret = i40e_dev_switch_tx_queues(pf, on);
6095 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6098 ret = i40e_dev_switch_rx_queues(pf, on);
6104 /* Initialize VSI for TX */
6106 i40e_dev_tx_init(struct i40e_pf *pf)
6108 struct rte_eth_dev_data *data = pf->dev_data;
6110 uint32_t ret = I40E_SUCCESS;
6111 struct i40e_tx_queue *txq;
6113 for (i = 0; i < data->nb_tx_queues; i++) {
6114 txq = data->tx_queues[i];
6115 if (!txq || !txq->q_set)
6117 ret = i40e_tx_queue_init(txq);
6118 if (ret != I40E_SUCCESS)
6121 if (ret == I40E_SUCCESS)
6122 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6128 /* Initialize VSI for RX */
6130 i40e_dev_rx_init(struct i40e_pf *pf)
6132 struct rte_eth_dev_data *data = pf->dev_data;
6133 int ret = I40E_SUCCESS;
6135 struct i40e_rx_queue *rxq;
6137 i40e_pf_config_mq_rx(pf);
6138 for (i = 0; i < data->nb_rx_queues; i++) {
6139 rxq = data->rx_queues[i];
6140 if (!rxq || !rxq->q_set)
6143 ret = i40e_rx_queue_init(rxq);
6144 if (ret != I40E_SUCCESS) {
6146 "Failed to do RX queue initialization");
6150 if (ret == I40E_SUCCESS)
6151 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6158 i40e_dev_rxtx_init(struct i40e_pf *pf)
6162 err = i40e_dev_tx_init(pf);
6164 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6167 err = i40e_dev_rx_init(pf);
6169 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6177 i40e_vmdq_setup(struct rte_eth_dev *dev)
6179 struct rte_eth_conf *conf = &dev->data->dev_conf;
6180 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6181 int i, err, conf_vsis, j, loop;
6182 struct i40e_vsi *vsi;
6183 struct i40e_vmdq_info *vmdq_info;
6184 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6185 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6188 * Disable interrupt to avoid message from VF. Furthermore, it will
6189 * avoid race condition in VSI creation/destroy.
6191 i40e_pf_disable_irq0(hw);
6193 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6194 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6198 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6199 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6200 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6201 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6202 pf->max_nb_vmdq_vsi);
6206 if (pf->vmdq != NULL) {
6207 PMD_INIT_LOG(INFO, "VMDQ already configured");
6211 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6212 sizeof(*vmdq_info) * conf_vsis, 0);
6214 if (pf->vmdq == NULL) {
6215 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6219 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6221 /* Create VMDQ VSI */
6222 for (i = 0; i < conf_vsis; i++) {
6223 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6224 vmdq_conf->enable_loop_back);
6226 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6230 vmdq_info = &pf->vmdq[i];
6232 vmdq_info->vsi = vsi;
6234 pf->nb_cfg_vmdq_vsi = conf_vsis;
6236 /* Configure Vlan */
6237 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6238 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6239 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6240 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6241 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6242 vmdq_conf->pool_map[i].vlan_id, j);
6244 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6245 vmdq_conf->pool_map[i].vlan_id);
6247 PMD_INIT_LOG(ERR, "Failed to add vlan");
6255 i40e_pf_enable_irq0(hw);
6260 for (i = 0; i < conf_vsis; i++)
6261 if (pf->vmdq[i].vsi == NULL)
6264 i40e_vsi_release(pf->vmdq[i].vsi);
6268 i40e_pf_enable_irq0(hw);
6273 i40e_stat_update_32(struct i40e_hw *hw,
6281 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6285 if (new_data >= *offset)
6286 *stat = (uint64_t)(new_data - *offset);
6288 *stat = (uint64_t)((new_data +
6289 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6293 i40e_stat_update_48(struct i40e_hw *hw,
6302 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6303 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6304 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6309 if (new_data >= *offset)
6310 *stat = new_data - *offset;
6312 *stat = (uint64_t)((new_data +
6313 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6315 *stat &= I40E_48_BIT_MASK;
6320 i40e_pf_disable_irq0(struct i40e_hw *hw)
6322 /* Disable all interrupt types */
6323 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6324 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6325 I40E_WRITE_FLUSH(hw);
6330 i40e_pf_enable_irq0(struct i40e_hw *hw)
6332 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6333 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6334 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6335 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6336 I40E_WRITE_FLUSH(hw);
6340 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6342 /* read pending request and disable first */
6343 i40e_pf_disable_irq0(hw);
6344 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6345 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6346 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6349 /* Link no queues with irq0 */
6350 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6351 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6355 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6357 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6358 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6361 uint32_t index, offset, val;
6366 * Try to find which VF trigger a reset, use absolute VF id to access
6367 * since the reg is global register.
6369 for (i = 0; i < pf->vf_num; i++) {
6370 abs_vf_id = hw->func_caps.vf_base_id + i;
6371 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6372 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6373 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6374 /* VFR event occurred */
6375 if (val & (0x1 << offset)) {
6378 /* Clear the event first */
6379 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6381 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6383 * Only notify a VF reset event occurred,
6384 * don't trigger another SW reset
6386 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6387 if (ret != I40E_SUCCESS)
6388 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6394 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6399 for (i = 0; i < pf->vf_num; i++)
6400 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6404 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6406 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6407 struct i40e_arq_event_info info;
6408 uint16_t pending, opcode;
6411 info.buf_len = I40E_AQ_BUF_SZ;
6412 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6413 if (!info.msg_buf) {
6414 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6420 ret = i40e_clean_arq_element(hw, &info, &pending);
6422 if (ret != I40E_SUCCESS) {
6424 "Failed to read msg from AdminQ, aq_err: %u",
6425 hw->aq.asq_last_status);
6428 opcode = rte_le_to_cpu_16(info.desc.opcode);
6431 case i40e_aqc_opc_send_msg_to_pf:
6432 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6433 i40e_pf_host_handle_vf_msg(dev,
6434 rte_le_to_cpu_16(info.desc.retval),
6435 rte_le_to_cpu_32(info.desc.cookie_high),
6436 rte_le_to_cpu_32(info.desc.cookie_low),
6440 case i40e_aqc_opc_get_link_status:
6441 ret = i40e_dev_link_update(dev, 0);
6443 _rte_eth_dev_callback_process(dev,
6444 RTE_ETH_EVENT_INTR_LSC, NULL);
6447 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6452 rte_free(info.msg_buf);
6456 * Interrupt handler triggered by NIC for handling
6457 * specific interrupt.
6460 * Pointer to interrupt handle.
6462 * The address of parameter (struct rte_eth_dev *) regsitered before.
6468 i40e_dev_interrupt_handler(void *param)
6470 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6471 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6474 /* Disable interrupt */
6475 i40e_pf_disable_irq0(hw);
6477 /* read out interrupt causes */
6478 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6480 /* No interrupt event indicated */
6481 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6482 PMD_DRV_LOG(INFO, "No interrupt event");
6485 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6486 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6487 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6488 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6489 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6490 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6491 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6492 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6493 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6494 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6495 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6496 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6497 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6498 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6500 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6501 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6502 i40e_dev_handle_vfr_event(dev);
6504 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6505 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6506 i40e_dev_handle_aq_msg(dev);
6510 /* Enable interrupt */
6511 i40e_pf_enable_irq0(hw);
6512 rte_intr_enable(dev->intr_handle);
6516 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6517 struct i40e_macvlan_filter *filter,
6520 int ele_num, ele_buff_size;
6521 int num, actual_num, i;
6523 int ret = I40E_SUCCESS;
6524 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6525 struct i40e_aqc_add_macvlan_element_data *req_list;
6527 if (filter == NULL || total == 0)
6528 return I40E_ERR_PARAM;
6529 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6530 ele_buff_size = hw->aq.asq_buf_size;
6532 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6533 if (req_list == NULL) {
6534 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6535 return I40E_ERR_NO_MEMORY;
6540 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6541 memset(req_list, 0, ele_buff_size);
6543 for (i = 0; i < actual_num; i++) {
6544 rte_memcpy(req_list[i].mac_addr,
6545 &filter[num + i].macaddr, ETH_ADDR_LEN);
6546 req_list[i].vlan_tag =
6547 rte_cpu_to_le_16(filter[num + i].vlan_id);
6549 switch (filter[num + i].filter_type) {
6550 case RTE_MAC_PERFECT_MATCH:
6551 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6552 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6554 case RTE_MACVLAN_PERFECT_MATCH:
6555 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6557 case RTE_MAC_HASH_MATCH:
6558 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6559 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6561 case RTE_MACVLAN_HASH_MATCH:
6562 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6565 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6566 ret = I40E_ERR_PARAM;
6570 req_list[i].queue_number = 0;
6572 req_list[i].flags = rte_cpu_to_le_16(flags);
6575 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6577 if (ret != I40E_SUCCESS) {
6578 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6582 } while (num < total);
6590 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6591 struct i40e_macvlan_filter *filter,
6594 int ele_num, ele_buff_size;
6595 int num, actual_num, i;
6597 int ret = I40E_SUCCESS;
6598 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6599 struct i40e_aqc_remove_macvlan_element_data *req_list;
6601 if (filter == NULL || total == 0)
6602 return I40E_ERR_PARAM;
6604 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6605 ele_buff_size = hw->aq.asq_buf_size;
6607 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6608 if (req_list == NULL) {
6609 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6610 return I40E_ERR_NO_MEMORY;
6615 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6616 memset(req_list, 0, ele_buff_size);
6618 for (i = 0; i < actual_num; i++) {
6619 rte_memcpy(req_list[i].mac_addr,
6620 &filter[num + i].macaddr, ETH_ADDR_LEN);
6621 req_list[i].vlan_tag =
6622 rte_cpu_to_le_16(filter[num + i].vlan_id);
6624 switch (filter[num + i].filter_type) {
6625 case RTE_MAC_PERFECT_MATCH:
6626 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6627 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6629 case RTE_MACVLAN_PERFECT_MATCH:
6630 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6632 case RTE_MAC_HASH_MATCH:
6633 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6634 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6636 case RTE_MACVLAN_HASH_MATCH:
6637 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6640 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6641 ret = I40E_ERR_PARAM;
6644 req_list[i].flags = rte_cpu_to_le_16(flags);
6647 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6649 if (ret != I40E_SUCCESS) {
6650 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6654 } while (num < total);
6661 /* Find out specific MAC filter */
6662 static struct i40e_mac_filter *
6663 i40e_find_mac_filter(struct i40e_vsi *vsi,
6664 struct ether_addr *macaddr)
6666 struct i40e_mac_filter *f;
6668 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6669 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6677 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6680 uint32_t vid_idx, vid_bit;
6682 if (vlan_id > ETH_VLAN_ID_MAX)
6685 vid_idx = I40E_VFTA_IDX(vlan_id);
6686 vid_bit = I40E_VFTA_BIT(vlan_id);
6688 if (vsi->vfta[vid_idx] & vid_bit)
6695 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6696 uint16_t vlan_id, bool on)
6698 uint32_t vid_idx, vid_bit;
6700 vid_idx = I40E_VFTA_IDX(vlan_id);
6701 vid_bit = I40E_VFTA_BIT(vlan_id);
6704 vsi->vfta[vid_idx] |= vid_bit;
6706 vsi->vfta[vid_idx] &= ~vid_bit;
6710 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6711 uint16_t vlan_id, bool on)
6713 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6714 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6717 if (vlan_id > ETH_VLAN_ID_MAX)
6720 i40e_store_vlan_filter(vsi, vlan_id, on);
6722 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6725 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6728 ret = i40e_aq_add_vlan(hw, vsi->seid,
6729 &vlan_data, 1, NULL);
6730 if (ret != I40E_SUCCESS)
6731 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6733 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6734 &vlan_data, 1, NULL);
6735 if (ret != I40E_SUCCESS)
6737 "Failed to remove vlan filter");
6742 * Find all vlan options for specific mac addr,
6743 * return with actual vlan found.
6746 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6747 struct i40e_macvlan_filter *mv_f,
6748 int num, struct ether_addr *addr)
6754 * Not to use i40e_find_vlan_filter to decrease the loop time,
6755 * although the code looks complex.
6757 if (num < vsi->vlan_num)
6758 return I40E_ERR_PARAM;
6761 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6763 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6764 if (vsi->vfta[j] & (1 << k)) {
6767 "vlan number doesn't match");
6768 return I40E_ERR_PARAM;
6770 rte_memcpy(&mv_f[i].macaddr,
6771 addr, ETH_ADDR_LEN);
6773 j * I40E_UINT32_BIT_SIZE + k;
6779 return I40E_SUCCESS;
6783 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6784 struct i40e_macvlan_filter *mv_f,
6789 struct i40e_mac_filter *f;
6791 if (num < vsi->mac_num)
6792 return I40E_ERR_PARAM;
6794 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6796 PMD_DRV_LOG(ERR, "buffer number not match");
6797 return I40E_ERR_PARAM;
6799 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6801 mv_f[i].vlan_id = vlan;
6802 mv_f[i].filter_type = f->mac_info.filter_type;
6806 return I40E_SUCCESS;
6810 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6813 struct i40e_mac_filter *f;
6814 struct i40e_macvlan_filter *mv_f;
6815 int ret = I40E_SUCCESS;
6817 if (vsi == NULL || vsi->mac_num == 0)
6818 return I40E_ERR_PARAM;
6820 /* Case that no vlan is set */
6821 if (vsi->vlan_num == 0)
6824 num = vsi->mac_num * vsi->vlan_num;
6826 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6828 PMD_DRV_LOG(ERR, "failed to allocate memory");
6829 return I40E_ERR_NO_MEMORY;
6833 if (vsi->vlan_num == 0) {
6834 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6835 rte_memcpy(&mv_f[i].macaddr,
6836 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6837 mv_f[i].filter_type = f->mac_info.filter_type;
6838 mv_f[i].vlan_id = 0;
6842 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6843 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6844 vsi->vlan_num, &f->mac_info.mac_addr);
6845 if (ret != I40E_SUCCESS)
6847 for (j = i; j < i + vsi->vlan_num; j++)
6848 mv_f[j].filter_type = f->mac_info.filter_type;
6853 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6861 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6863 struct i40e_macvlan_filter *mv_f;
6865 int ret = I40E_SUCCESS;
6867 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6868 return I40E_ERR_PARAM;
6870 /* If it's already set, just return */
6871 if (i40e_find_vlan_filter(vsi,vlan))
6872 return I40E_SUCCESS;
6874 mac_num = vsi->mac_num;
6877 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6878 return I40E_ERR_PARAM;
6881 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6884 PMD_DRV_LOG(ERR, "failed to allocate memory");
6885 return I40E_ERR_NO_MEMORY;
6888 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6890 if (ret != I40E_SUCCESS)
6893 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6895 if (ret != I40E_SUCCESS)
6898 i40e_set_vlan_filter(vsi, vlan, 1);
6908 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6910 struct i40e_macvlan_filter *mv_f;
6912 int ret = I40E_SUCCESS;
6915 * Vlan 0 is the generic filter for untagged packets
6916 * and can't be removed.
6918 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6919 return I40E_ERR_PARAM;
6921 /* If can't find it, just return */
6922 if (!i40e_find_vlan_filter(vsi, vlan))
6923 return I40E_ERR_PARAM;
6925 mac_num = vsi->mac_num;
6928 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6929 return I40E_ERR_PARAM;
6932 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6935 PMD_DRV_LOG(ERR, "failed to allocate memory");
6936 return I40E_ERR_NO_MEMORY;
6939 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6941 if (ret != I40E_SUCCESS)
6944 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6946 if (ret != I40E_SUCCESS)
6949 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6950 if (vsi->vlan_num == 1) {
6951 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6952 if (ret != I40E_SUCCESS)
6955 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6956 if (ret != I40E_SUCCESS)
6960 i40e_set_vlan_filter(vsi, vlan, 0);
6970 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6972 struct i40e_mac_filter *f;
6973 struct i40e_macvlan_filter *mv_f;
6974 int i, vlan_num = 0;
6975 int ret = I40E_SUCCESS;
6977 /* If it's add and we've config it, return */
6978 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6980 return I40E_SUCCESS;
6981 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6982 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6985 * If vlan_num is 0, that's the first time to add mac,
6986 * set mask for vlan_id 0.
6988 if (vsi->vlan_num == 0) {
6989 i40e_set_vlan_filter(vsi, 0, 1);
6992 vlan_num = vsi->vlan_num;
6993 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6994 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6997 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6999 PMD_DRV_LOG(ERR, "failed to allocate memory");
7000 return I40E_ERR_NO_MEMORY;
7003 for (i = 0; i < vlan_num; i++) {
7004 mv_f[i].filter_type = mac_filter->filter_type;
7005 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7009 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7010 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7011 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7012 &mac_filter->mac_addr);
7013 if (ret != I40E_SUCCESS)
7017 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7018 if (ret != I40E_SUCCESS)
7021 /* Add the mac addr into mac list */
7022 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7024 PMD_DRV_LOG(ERR, "failed to allocate memory");
7025 ret = I40E_ERR_NO_MEMORY;
7028 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7030 f->mac_info.filter_type = mac_filter->filter_type;
7031 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7042 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7044 struct i40e_mac_filter *f;
7045 struct i40e_macvlan_filter *mv_f;
7047 enum rte_mac_filter_type filter_type;
7048 int ret = I40E_SUCCESS;
7050 /* Can't find it, return an error */
7051 f = i40e_find_mac_filter(vsi, addr);
7053 return I40E_ERR_PARAM;
7055 vlan_num = vsi->vlan_num;
7056 filter_type = f->mac_info.filter_type;
7057 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7058 filter_type == RTE_MACVLAN_HASH_MATCH) {
7059 if (vlan_num == 0) {
7060 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7061 return I40E_ERR_PARAM;
7063 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7064 filter_type == RTE_MAC_HASH_MATCH)
7067 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7069 PMD_DRV_LOG(ERR, "failed to allocate memory");
7070 return I40E_ERR_NO_MEMORY;
7073 for (i = 0; i < vlan_num; i++) {
7074 mv_f[i].filter_type = filter_type;
7075 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7078 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7079 filter_type == RTE_MACVLAN_HASH_MATCH) {
7080 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7081 if (ret != I40E_SUCCESS)
7085 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7086 if (ret != I40E_SUCCESS)
7089 /* Remove the mac addr into mac list */
7090 TAILQ_REMOVE(&vsi->mac_list, f, next);
7100 /* Configure hash enable flags for RSS */
7102 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7110 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7111 if (flags & (1ULL << i))
7112 hena |= adapter->pctypes_tbl[i];
7118 /* Parse the hash enable flags */
7120 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7122 uint64_t rss_hf = 0;
7128 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7129 if (flags & adapter->pctypes_tbl[i])
7130 rss_hf |= (1ULL << i);
7137 i40e_pf_disable_rss(struct i40e_pf *pf)
7139 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7141 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7142 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7143 I40E_WRITE_FLUSH(hw);
7147 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7149 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7150 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7151 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7152 I40E_VFQF_HKEY_MAX_INDEX :
7153 I40E_PFQF_HKEY_MAX_INDEX;
7156 if (!key || key_len == 0) {
7157 PMD_DRV_LOG(DEBUG, "No key to be configured");
7159 } else if (key_len != (key_idx + 1) *
7161 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7165 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7166 struct i40e_aqc_get_set_rss_key_data *key_dw =
7167 (struct i40e_aqc_get_set_rss_key_data *)key;
7169 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7171 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7173 uint32_t *hash_key = (uint32_t *)key;
7176 if (vsi->type == I40E_VSI_SRIOV) {
7177 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7180 I40E_VFQF_HKEY1(i, vsi->user_param),
7184 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7185 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7188 I40E_WRITE_FLUSH(hw);
7195 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7197 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7198 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7202 if (!key || !key_len)
7205 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7206 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7207 (struct i40e_aqc_get_set_rss_key_data *)key);
7209 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7213 uint32_t *key_dw = (uint32_t *)key;
7216 if (vsi->type == I40E_VSI_SRIOV) {
7217 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7218 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7219 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7221 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7224 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7225 reg = I40E_PFQF_HKEY(i);
7226 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7228 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7236 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7238 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7242 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7243 rss_conf->rss_key_len);
7247 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7248 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7249 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7250 I40E_WRITE_FLUSH(hw);
7256 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7257 struct rte_eth_rss_conf *rss_conf)
7259 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7260 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7261 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7264 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7265 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7267 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7268 if (rss_hf != 0) /* Enable RSS */
7270 return 0; /* Nothing to do */
7273 if (rss_hf == 0) /* Disable RSS */
7276 return i40e_hw_rss_hash_set(pf, rss_conf);
7280 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7281 struct rte_eth_rss_conf *rss_conf)
7283 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7284 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7287 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7288 &rss_conf->rss_key_len);
7290 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7291 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7292 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7298 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7300 switch (filter_type) {
7301 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7302 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7304 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7305 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7307 case RTE_TUNNEL_FILTER_IMAC_TENID:
7308 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7310 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7311 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7313 case ETH_TUNNEL_FILTER_IMAC:
7314 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7316 case ETH_TUNNEL_FILTER_OIP:
7317 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7319 case ETH_TUNNEL_FILTER_IIP:
7320 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7323 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7330 /* Convert tunnel filter structure */
7332 i40e_tunnel_filter_convert(
7333 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7334 struct i40e_tunnel_filter *tunnel_filter)
7336 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7337 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7338 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7339 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7340 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7341 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7342 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7343 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7344 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7346 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7347 tunnel_filter->input.flags = cld_filter->element.flags;
7348 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7349 tunnel_filter->queue = cld_filter->element.queue_number;
7350 rte_memcpy(tunnel_filter->input.general_fields,
7351 cld_filter->general_fields,
7352 sizeof(cld_filter->general_fields));
7357 /* Check if there exists the tunnel filter */
7358 struct i40e_tunnel_filter *
7359 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7360 const struct i40e_tunnel_filter_input *input)
7364 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7368 return tunnel_rule->hash_map[ret];
7371 /* Add a tunnel filter into the SW list */
7373 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7374 struct i40e_tunnel_filter *tunnel_filter)
7376 struct i40e_tunnel_rule *rule = &pf->tunnel;
7379 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7382 "Failed to insert tunnel filter to hash table %d!",
7386 rule->hash_map[ret] = tunnel_filter;
7388 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7393 /* Delete a tunnel filter from the SW list */
7395 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7396 struct i40e_tunnel_filter_input *input)
7398 struct i40e_tunnel_rule *rule = &pf->tunnel;
7399 struct i40e_tunnel_filter *tunnel_filter;
7402 ret = rte_hash_del_key(rule->hash_table, input);
7405 "Failed to delete tunnel filter to hash table %d!",
7409 tunnel_filter = rule->hash_map[ret];
7410 rule->hash_map[ret] = NULL;
7412 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7413 rte_free(tunnel_filter);
7419 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7420 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7424 uint32_t ipv4_addr, ipv4_addr_le;
7425 uint8_t i, tun_type = 0;
7426 /* internal varialbe to convert ipv6 byte order */
7427 uint32_t convert_ipv6[4];
7429 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7430 struct i40e_vsi *vsi = pf->main_vsi;
7431 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7432 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7433 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7434 struct i40e_tunnel_filter *tunnel, *node;
7435 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7437 cld_filter = rte_zmalloc("tunnel_filter",
7438 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7441 if (NULL == cld_filter) {
7442 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7445 pfilter = cld_filter;
7447 ether_addr_copy(&tunnel_filter->outer_mac,
7448 (struct ether_addr *)&pfilter->element.outer_mac);
7449 ether_addr_copy(&tunnel_filter->inner_mac,
7450 (struct ether_addr *)&pfilter->element.inner_mac);
7452 pfilter->element.inner_vlan =
7453 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7454 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7455 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7456 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7457 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7458 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7460 sizeof(pfilter->element.ipaddr.v4.data));
7462 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7463 for (i = 0; i < 4; i++) {
7465 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7467 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7469 sizeof(pfilter->element.ipaddr.v6.data));
7472 /* check tunneled type */
7473 switch (tunnel_filter->tunnel_type) {
7474 case RTE_TUNNEL_TYPE_VXLAN:
7475 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7477 case RTE_TUNNEL_TYPE_NVGRE:
7478 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7480 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7481 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7484 /* Other tunnel types is not supported. */
7485 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7486 rte_free(cld_filter);
7490 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7491 &pfilter->element.flags);
7493 rte_free(cld_filter);
7497 pfilter->element.flags |= rte_cpu_to_le_16(
7498 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7499 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7500 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7501 pfilter->element.queue_number =
7502 rte_cpu_to_le_16(tunnel_filter->queue_id);
7504 /* Check if there is the filter in SW list */
7505 memset(&check_filter, 0, sizeof(check_filter));
7506 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7507 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7509 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7510 rte_free(cld_filter);
7514 if (!add && !node) {
7515 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7516 rte_free(cld_filter);
7521 ret = i40e_aq_add_cloud_filters(hw,
7522 vsi->seid, &cld_filter->element, 1);
7524 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7525 rte_free(cld_filter);
7528 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7529 if (tunnel == NULL) {
7530 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7531 rte_free(cld_filter);
7535 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7536 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7540 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7541 &cld_filter->element, 1);
7543 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7544 rte_free(cld_filter);
7547 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7550 rte_free(cld_filter);
7554 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7555 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7556 #define I40E_TR_GENEVE_KEY_MASK 0x8
7557 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7558 #define I40E_TR_GRE_KEY_MASK 0x400
7559 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7560 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7563 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7565 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7566 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7567 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7568 enum i40e_status_code status = I40E_SUCCESS;
7570 if (pf->support_multi_driver) {
7571 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7572 return I40E_NOT_SUPPORTED;
7575 memset(&filter_replace, 0,
7576 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7577 memset(&filter_replace_buf, 0,
7578 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7580 /* create L1 filter */
7581 filter_replace.old_filter_type =
7582 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7583 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7584 filter_replace.tr_bit = 0;
7586 /* Prepare the buffer, 3 entries */
7587 filter_replace_buf.data[0] =
7588 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7589 filter_replace_buf.data[0] |=
7590 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7591 filter_replace_buf.data[2] = 0xFF;
7592 filter_replace_buf.data[3] = 0xFF;
7593 filter_replace_buf.data[4] =
7594 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7595 filter_replace_buf.data[4] |=
7596 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7597 filter_replace_buf.data[7] = 0xF0;
7598 filter_replace_buf.data[8]
7599 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7600 filter_replace_buf.data[8] |=
7601 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7602 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7603 I40E_TR_GENEVE_KEY_MASK |
7604 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7605 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7606 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7607 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7609 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7610 &filter_replace_buf);
7612 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7613 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7614 "cloud l1 type is changed from 0x%x to 0x%x",
7615 filter_replace.old_filter_type,
7616 filter_replace.new_filter_type);
7622 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7624 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7625 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7626 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7627 enum i40e_status_code status = I40E_SUCCESS;
7629 if (pf->support_multi_driver) {
7630 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7631 return I40E_NOT_SUPPORTED;
7635 memset(&filter_replace, 0,
7636 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7637 memset(&filter_replace_buf, 0,
7638 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7639 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7640 I40E_AQC_MIRROR_CLOUD_FILTER;
7641 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7642 filter_replace.new_filter_type =
7643 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7644 /* Prepare the buffer, 2 entries */
7645 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7646 filter_replace_buf.data[0] |=
7647 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7648 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7649 filter_replace_buf.data[4] |=
7650 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7651 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7652 &filter_replace_buf);
7655 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7656 "cloud filter type is changed from 0x%x to 0x%x",
7657 filter_replace.old_filter_type,
7658 filter_replace.new_filter_type);
7661 memset(&filter_replace, 0,
7662 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7663 memset(&filter_replace_buf, 0,
7664 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7666 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7667 I40E_AQC_MIRROR_CLOUD_FILTER;
7668 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7669 filter_replace.new_filter_type =
7670 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7671 /* Prepare the buffer, 2 entries */
7672 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7673 filter_replace_buf.data[0] |=
7674 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7675 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7676 filter_replace_buf.data[4] |=
7677 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7679 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7680 &filter_replace_buf);
7682 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7683 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7684 "cloud filter type is changed from 0x%x to 0x%x",
7685 filter_replace.old_filter_type,
7686 filter_replace.new_filter_type);
7691 static enum i40e_status_code
7692 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7694 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7695 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7696 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7697 enum i40e_status_code status = I40E_SUCCESS;
7699 if (pf->support_multi_driver) {
7700 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7701 return I40E_NOT_SUPPORTED;
7705 memset(&filter_replace, 0,
7706 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7707 memset(&filter_replace_buf, 0,
7708 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7709 /* create L1 filter */
7710 filter_replace.old_filter_type =
7711 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7712 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7713 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7714 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7715 /* Prepare the buffer, 2 entries */
7716 filter_replace_buf.data[0] =
7717 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7718 filter_replace_buf.data[0] |=
7719 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7720 filter_replace_buf.data[2] = 0xFF;
7721 filter_replace_buf.data[3] = 0xFF;
7722 filter_replace_buf.data[4] =
7723 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7724 filter_replace_buf.data[4] |=
7725 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7726 filter_replace_buf.data[6] = 0xFF;
7727 filter_replace_buf.data[7] = 0xFF;
7728 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7729 &filter_replace_buf);
7732 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7733 "cloud l1 type is changed from 0x%x to 0x%x",
7734 filter_replace.old_filter_type,
7735 filter_replace.new_filter_type);
7738 memset(&filter_replace, 0,
7739 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7740 memset(&filter_replace_buf, 0,
7741 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7742 /* create L1 filter */
7743 filter_replace.old_filter_type =
7744 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7745 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7746 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7747 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7748 /* Prepare the buffer, 2 entries */
7749 filter_replace_buf.data[0] =
7750 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7751 filter_replace_buf.data[0] |=
7752 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7753 filter_replace_buf.data[2] = 0xFF;
7754 filter_replace_buf.data[3] = 0xFF;
7755 filter_replace_buf.data[4] =
7756 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7757 filter_replace_buf.data[4] |=
7758 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7759 filter_replace_buf.data[6] = 0xFF;
7760 filter_replace_buf.data[7] = 0xFF;
7762 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7763 &filter_replace_buf);
7765 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7766 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7767 "cloud l1 type is changed from 0x%x to 0x%x",
7768 filter_replace.old_filter_type,
7769 filter_replace.new_filter_type);
7775 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7777 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7778 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7779 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7780 enum i40e_status_code status = I40E_SUCCESS;
7782 if (pf->support_multi_driver) {
7783 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7784 return I40E_NOT_SUPPORTED;
7788 memset(&filter_replace, 0,
7789 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7790 memset(&filter_replace_buf, 0,
7791 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7792 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7793 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7794 filter_replace.new_filter_type =
7795 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7796 /* Prepare the buffer, 2 entries */
7797 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7798 filter_replace_buf.data[0] |=
7799 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7800 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7801 filter_replace_buf.data[4] |=
7802 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7803 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7804 &filter_replace_buf);
7807 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7808 "cloud filter type is changed from 0x%x to 0x%x",
7809 filter_replace.old_filter_type,
7810 filter_replace.new_filter_type);
7813 memset(&filter_replace, 0,
7814 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7815 memset(&filter_replace_buf, 0,
7816 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7817 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7818 filter_replace.old_filter_type =
7819 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7820 filter_replace.new_filter_type =
7821 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7822 /* Prepare the buffer, 2 entries */
7823 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7824 filter_replace_buf.data[0] |=
7825 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7826 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7827 filter_replace_buf.data[4] |=
7828 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7830 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7831 &filter_replace_buf);
7833 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7834 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7835 "cloud filter type is changed from 0x%x to 0x%x",
7836 filter_replace.old_filter_type,
7837 filter_replace.new_filter_type);
7843 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7844 struct i40e_tunnel_filter_conf *tunnel_filter,
7848 uint32_t ipv4_addr, ipv4_addr_le;
7849 uint8_t i, tun_type = 0;
7850 /* internal variable to convert ipv6 byte order */
7851 uint32_t convert_ipv6[4];
7853 struct i40e_pf_vf *vf = NULL;
7854 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7855 struct i40e_vsi *vsi;
7856 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7857 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7858 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7859 struct i40e_tunnel_filter *tunnel, *node;
7860 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7862 bool big_buffer = 0;
7864 cld_filter = rte_zmalloc("tunnel_filter",
7865 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7868 if (cld_filter == NULL) {
7869 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7872 pfilter = cld_filter;
7874 ether_addr_copy(&tunnel_filter->outer_mac,
7875 (struct ether_addr *)&pfilter->element.outer_mac);
7876 ether_addr_copy(&tunnel_filter->inner_mac,
7877 (struct ether_addr *)&pfilter->element.inner_mac);
7879 pfilter->element.inner_vlan =
7880 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7881 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7882 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7883 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7884 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7885 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7887 sizeof(pfilter->element.ipaddr.v4.data));
7889 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7890 for (i = 0; i < 4; i++) {
7892 rte_cpu_to_le_32(rte_be_to_cpu_32(
7893 tunnel_filter->ip_addr.ipv6_addr[i]));
7895 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7897 sizeof(pfilter->element.ipaddr.v6.data));
7900 /* check tunneled type */
7901 switch (tunnel_filter->tunnel_type) {
7902 case I40E_TUNNEL_TYPE_VXLAN:
7903 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7905 case I40E_TUNNEL_TYPE_NVGRE:
7906 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7908 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7909 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7911 case I40E_TUNNEL_TYPE_MPLSoUDP:
7912 if (!pf->mpls_replace_flag) {
7913 i40e_replace_mpls_l1_filter(pf);
7914 i40e_replace_mpls_cloud_filter(pf);
7915 pf->mpls_replace_flag = 1;
7917 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7918 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7920 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7921 (teid_le & 0xF) << 12;
7922 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7925 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7927 case I40E_TUNNEL_TYPE_MPLSoGRE:
7928 if (!pf->mpls_replace_flag) {
7929 i40e_replace_mpls_l1_filter(pf);
7930 i40e_replace_mpls_cloud_filter(pf);
7931 pf->mpls_replace_flag = 1;
7933 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7934 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7936 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7937 (teid_le & 0xF) << 12;
7938 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7941 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7943 case I40E_TUNNEL_TYPE_GTPC:
7944 if (!pf->gtp_replace_flag) {
7945 i40e_replace_gtp_l1_filter(pf);
7946 i40e_replace_gtp_cloud_filter(pf);
7947 pf->gtp_replace_flag = 1;
7949 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7950 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7951 (teid_le >> 16) & 0xFFFF;
7952 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7954 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7958 case I40E_TUNNEL_TYPE_GTPU:
7959 if (!pf->gtp_replace_flag) {
7960 i40e_replace_gtp_l1_filter(pf);
7961 i40e_replace_gtp_cloud_filter(pf);
7962 pf->gtp_replace_flag = 1;
7964 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7965 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7966 (teid_le >> 16) & 0xFFFF;
7967 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7969 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7973 case I40E_TUNNEL_TYPE_QINQ:
7974 if (!pf->qinq_replace_flag) {
7975 ret = i40e_cloud_filter_qinq_create(pf);
7978 "QinQ tunnel filter already created.");
7979 pf->qinq_replace_flag = 1;
7981 /* Add in the General fields the values of
7982 * the Outer and Inner VLAN
7983 * Big Buffer should be set, see changes in
7984 * i40e_aq_add_cloud_filters
7986 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7987 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7991 /* Other tunnel types is not supported. */
7992 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7993 rte_free(cld_filter);
7997 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7998 pfilter->element.flags =
7999 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8000 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8001 pfilter->element.flags =
8002 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8003 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8004 pfilter->element.flags =
8005 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8006 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8007 pfilter->element.flags =
8008 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8009 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8010 pfilter->element.flags |=
8011 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8013 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8014 &pfilter->element.flags);
8016 rte_free(cld_filter);
8021 pfilter->element.flags |= rte_cpu_to_le_16(
8022 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8023 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8024 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8025 pfilter->element.queue_number =
8026 rte_cpu_to_le_16(tunnel_filter->queue_id);
8028 if (!tunnel_filter->is_to_vf)
8031 if (tunnel_filter->vf_id >= pf->vf_num) {
8032 PMD_DRV_LOG(ERR, "Invalid argument.");
8033 rte_free(cld_filter);
8036 vf = &pf->vfs[tunnel_filter->vf_id];
8040 /* Check if there is the filter in SW list */
8041 memset(&check_filter, 0, sizeof(check_filter));
8042 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8043 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8044 check_filter.vf_id = tunnel_filter->vf_id;
8045 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8047 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8048 rte_free(cld_filter);
8052 if (!add && !node) {
8053 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8054 rte_free(cld_filter);
8060 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8061 vsi->seid, cld_filter, 1);
8063 ret = i40e_aq_add_cloud_filters(hw,
8064 vsi->seid, &cld_filter->element, 1);
8066 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8067 rte_free(cld_filter);
8070 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8071 if (tunnel == NULL) {
8072 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8073 rte_free(cld_filter);
8077 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8078 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8083 ret = i40e_aq_remove_cloud_filters_big_buffer(
8084 hw, vsi->seid, cld_filter, 1);
8086 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8087 &cld_filter->element, 1);
8089 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8090 rte_free(cld_filter);
8093 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8096 rte_free(cld_filter);
8101 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8105 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8106 if (pf->vxlan_ports[i] == port)
8114 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8118 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8120 idx = i40e_get_vxlan_port_idx(pf, port);
8122 /* Check if port already exists */
8124 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8128 /* Now check if there is space to add the new port */
8129 idx = i40e_get_vxlan_port_idx(pf, 0);
8132 "Maximum number of UDP ports reached, not adding port %d",
8137 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8140 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8144 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8147 /* New port: add it and mark its index in the bitmap */
8148 pf->vxlan_ports[idx] = port;
8149 pf->vxlan_bitmap |= (1 << idx);
8151 if (!(pf->flags & I40E_FLAG_VXLAN))
8152 pf->flags |= I40E_FLAG_VXLAN;
8158 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8161 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8163 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8164 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8168 idx = i40e_get_vxlan_port_idx(pf, port);
8171 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8175 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8176 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8180 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8183 pf->vxlan_ports[idx] = 0;
8184 pf->vxlan_bitmap &= ~(1 << idx);
8186 if (!pf->vxlan_bitmap)
8187 pf->flags &= ~I40E_FLAG_VXLAN;
8192 /* Add UDP tunneling port */
8194 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8195 struct rte_eth_udp_tunnel *udp_tunnel)
8198 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8200 if (udp_tunnel == NULL)
8203 switch (udp_tunnel->prot_type) {
8204 case RTE_TUNNEL_TYPE_VXLAN:
8205 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8208 case RTE_TUNNEL_TYPE_GENEVE:
8209 case RTE_TUNNEL_TYPE_TEREDO:
8210 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8215 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8223 /* Remove UDP tunneling port */
8225 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8226 struct rte_eth_udp_tunnel *udp_tunnel)
8229 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8231 if (udp_tunnel == NULL)
8234 switch (udp_tunnel->prot_type) {
8235 case RTE_TUNNEL_TYPE_VXLAN:
8236 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8238 case RTE_TUNNEL_TYPE_GENEVE:
8239 case RTE_TUNNEL_TYPE_TEREDO:
8240 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8244 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8252 /* Calculate the maximum number of contiguous PF queues that are configured */
8254 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8256 struct rte_eth_dev_data *data = pf->dev_data;
8258 struct i40e_rx_queue *rxq;
8261 for (i = 0; i < pf->lan_nb_qps; i++) {
8262 rxq = data->rx_queues[i];
8263 if (rxq && rxq->q_set)
8274 i40e_pf_config_rss(struct i40e_pf *pf)
8276 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8277 struct rte_eth_rss_conf rss_conf;
8278 uint32_t i, lut = 0;
8282 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8283 * It's necessary to calculate the actual PF queues that are configured.
8285 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8286 num = i40e_pf_calc_configured_queues_num(pf);
8288 num = pf->dev_data->nb_rx_queues;
8290 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8291 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8295 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8299 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8302 lut = (lut << 8) | (j & ((0x1 <<
8303 hw->func_caps.rss_table_entry_width) - 1));
8305 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8308 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8309 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8310 i40e_pf_disable_rss(pf);
8313 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8314 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8315 /* Random default keys */
8316 static uint32_t rss_key_default[] = {0x6b793944,
8317 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8318 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8319 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8321 rss_conf.rss_key = (uint8_t *)rss_key_default;
8322 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8326 return i40e_hw_rss_hash_set(pf, &rss_conf);
8330 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8331 struct rte_eth_tunnel_filter_conf *filter)
8333 if (pf == NULL || filter == NULL) {
8334 PMD_DRV_LOG(ERR, "Invalid parameter");
8338 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8339 PMD_DRV_LOG(ERR, "Invalid queue ID");
8343 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8344 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8348 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8349 (is_zero_ether_addr(&filter->outer_mac))) {
8350 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8354 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8355 (is_zero_ether_addr(&filter->inner_mac))) {
8356 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8363 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8364 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8366 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8368 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8372 if (pf->support_multi_driver) {
8373 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8377 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8378 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8381 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8382 } else if (len == 4) {
8383 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8385 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8390 ret = i40e_aq_debug_write_global_register(hw,
8391 I40E_GL_PRS_FVBM(2),
8395 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8396 "with value 0x%08x",
8397 I40E_GL_PRS_FVBM(2), reg);
8398 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8402 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8403 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8409 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8416 switch (cfg->cfg_type) {
8417 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8418 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8421 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8429 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8430 enum rte_filter_op filter_op,
8433 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8434 int ret = I40E_ERR_PARAM;
8436 switch (filter_op) {
8437 case RTE_ETH_FILTER_SET:
8438 ret = i40e_dev_global_config_set(hw,
8439 (struct rte_eth_global_cfg *)arg);
8442 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8450 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8451 enum rte_filter_op filter_op,
8454 struct rte_eth_tunnel_filter_conf *filter;
8455 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8456 int ret = I40E_SUCCESS;
8458 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8460 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8461 return I40E_ERR_PARAM;
8463 switch (filter_op) {
8464 case RTE_ETH_FILTER_NOP:
8465 if (!(pf->flags & I40E_FLAG_VXLAN))
8466 ret = I40E_NOT_SUPPORTED;
8468 case RTE_ETH_FILTER_ADD:
8469 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8471 case RTE_ETH_FILTER_DELETE:
8472 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8475 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8476 ret = I40E_ERR_PARAM;
8484 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8487 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8490 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8491 ret = i40e_pf_config_rss(pf);
8493 i40e_pf_disable_rss(pf);
8498 /* Get the symmetric hash enable configurations per port */
8500 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8502 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8504 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8507 /* Set the symmetric hash enable configurations per port */
8509 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8511 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8514 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8516 "Symmetric hash has already been enabled");
8519 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8521 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8523 "Symmetric hash has already been disabled");
8526 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8528 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8529 I40E_WRITE_FLUSH(hw);
8533 * Get global configurations of hash function type and symmetric hash enable
8534 * per flow type (pctype). Note that global configuration means it affects all
8535 * the ports on the same NIC.
8538 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8539 struct rte_eth_hash_global_conf *g_cfg)
8541 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8545 memset(g_cfg, 0, sizeof(*g_cfg));
8546 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8547 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8548 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8550 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8551 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8552 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8555 * As i40e supports less than 64 flow types, only first 64 bits need to
8558 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8559 g_cfg->valid_bit_mask[i] = 0ULL;
8560 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8563 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8565 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8566 if (!adapter->pctypes_tbl[i])
8568 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8569 j < I40E_FILTER_PCTYPE_MAX; j++) {
8570 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8571 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8572 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8573 g_cfg->sym_hash_enable_mask[0] |=
8584 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8585 const struct rte_eth_hash_global_conf *g_cfg)
8588 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8590 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8591 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8592 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8593 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8599 * As i40e supports less than 64 flow types, only first 64 bits need to
8602 mask0 = g_cfg->valid_bit_mask[0];
8603 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8605 /* Check if any unsupported flow type configured */
8606 if ((mask0 | i40e_mask) ^ i40e_mask)
8609 if (g_cfg->valid_bit_mask[i])
8617 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8623 * Set global configurations of hash function type and symmetric hash enable
8624 * per flow type (pctype). Note any modifying global configuration will affect
8625 * all the ports on the same NIC.
8628 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8629 struct rte_eth_hash_global_conf *g_cfg)
8631 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8632 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8636 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8638 if (pf->support_multi_driver) {
8639 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8643 /* Check the input parameters */
8644 ret = i40e_hash_global_config_check(adapter, g_cfg);
8649 * As i40e supports less than 64 flow types, only first 64 bits need to
8652 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8653 if (mask0 & (1UL << i)) {
8654 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8655 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8657 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8658 j < I40E_FILTER_PCTYPE_MAX; j++) {
8659 if (adapter->pctypes_tbl[i] & (1ULL << j))
8660 i40e_write_global_rx_ctl(hw,
8664 i40e_global_cfg_warning(I40E_WARNING_HSYM);
8668 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8669 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8671 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8673 "Hash function already set to Toeplitz");
8676 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8677 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8679 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8681 "Hash function already set to Simple XOR");
8684 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8686 /* Use the default, and keep it as it is */
8689 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8690 i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8693 I40E_WRITE_FLUSH(hw);
8699 * Valid input sets for hash and flow director filters per PCTYPE
8702 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8703 enum rte_filter_type filter)
8707 static const uint64_t valid_hash_inset_table[] = {
8708 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8709 I40E_INSET_DMAC | I40E_INSET_SMAC |
8710 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8711 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8712 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8713 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8714 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8715 I40E_INSET_FLEX_PAYLOAD,
8716 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8717 I40E_INSET_DMAC | I40E_INSET_SMAC |
8718 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8719 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8720 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8721 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8722 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8723 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8724 I40E_INSET_FLEX_PAYLOAD,
8725 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8726 I40E_INSET_DMAC | I40E_INSET_SMAC |
8727 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8728 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8729 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8730 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8731 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8732 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8733 I40E_INSET_FLEX_PAYLOAD,
8734 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8735 I40E_INSET_DMAC | I40E_INSET_SMAC |
8736 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8737 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8738 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8739 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8740 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8741 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8742 I40E_INSET_FLEX_PAYLOAD,
8743 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8744 I40E_INSET_DMAC | I40E_INSET_SMAC |
8745 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8746 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8747 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8748 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8749 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8750 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8751 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8752 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8753 I40E_INSET_DMAC | I40E_INSET_SMAC |
8754 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8755 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8756 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8757 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8758 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8759 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8760 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8761 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8762 I40E_INSET_DMAC | I40E_INSET_SMAC |
8763 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8764 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8765 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8766 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8767 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8768 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8769 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8770 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8771 I40E_INSET_DMAC | I40E_INSET_SMAC |
8772 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8773 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8774 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8775 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8776 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8777 I40E_INSET_FLEX_PAYLOAD,
8778 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8779 I40E_INSET_DMAC | I40E_INSET_SMAC |
8780 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8781 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8782 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8783 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8784 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8785 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8786 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8787 I40E_INSET_DMAC | I40E_INSET_SMAC |
8788 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8789 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8790 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8791 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8792 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8793 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8794 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8795 I40E_INSET_DMAC | I40E_INSET_SMAC |
8796 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8797 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8798 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8799 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8800 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8801 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8802 I40E_INSET_FLEX_PAYLOAD,
8803 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8804 I40E_INSET_DMAC | I40E_INSET_SMAC |
8805 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8806 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8807 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8808 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8809 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8810 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8811 I40E_INSET_FLEX_PAYLOAD,
8812 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8813 I40E_INSET_DMAC | I40E_INSET_SMAC |
8814 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8815 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8816 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8817 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8818 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8819 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8820 I40E_INSET_FLEX_PAYLOAD,
8821 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8822 I40E_INSET_DMAC | I40E_INSET_SMAC |
8823 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8824 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8825 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8826 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8827 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8828 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8829 I40E_INSET_FLEX_PAYLOAD,
8830 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8831 I40E_INSET_DMAC | I40E_INSET_SMAC |
8832 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8833 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8834 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8835 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8836 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8837 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8838 I40E_INSET_FLEX_PAYLOAD,
8839 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8840 I40E_INSET_DMAC | I40E_INSET_SMAC |
8841 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8842 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8843 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8844 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8845 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8846 I40E_INSET_FLEX_PAYLOAD,
8847 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8848 I40E_INSET_DMAC | I40E_INSET_SMAC |
8849 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8850 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8851 I40E_INSET_FLEX_PAYLOAD,
8855 * Flow director supports only fields defined in
8856 * union rte_eth_fdir_flow.
8858 static const uint64_t valid_fdir_inset_table[] = {
8859 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8860 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8861 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8862 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8863 I40E_INSET_IPV4_TTL,
8864 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8865 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8866 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8867 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8868 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8869 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8870 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8871 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8872 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8873 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8874 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8875 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8876 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8877 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8878 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8879 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8880 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8881 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8882 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8883 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8884 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8885 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8886 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8887 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8888 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8889 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8890 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8891 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8892 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8893 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8895 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8896 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8897 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8898 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8899 I40E_INSET_IPV4_TTL,
8900 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8901 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8902 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8903 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8904 I40E_INSET_IPV6_HOP_LIMIT,
8905 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8906 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8907 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8908 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8909 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8910 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8911 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8912 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8913 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8914 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8915 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8916 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8917 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8918 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8919 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8920 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8921 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8922 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8923 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8924 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8925 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8926 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8927 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8928 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8929 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8930 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8931 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8932 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8933 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8934 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8936 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8937 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8938 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8939 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8940 I40E_INSET_IPV6_HOP_LIMIT,
8941 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8942 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8943 I40E_INSET_LAST_ETHER_TYPE,
8946 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8948 if (filter == RTE_ETH_FILTER_HASH)
8949 valid = valid_hash_inset_table[pctype];
8951 valid = valid_fdir_inset_table[pctype];
8957 * Validate if the input set is allowed for a specific PCTYPE
8960 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8961 enum rte_filter_type filter, uint64_t inset)
8965 valid = i40e_get_valid_input_set(pctype, filter);
8966 if (inset & (~valid))
8972 /* default input set fields combination per pctype */
8974 i40e_get_default_input_set(uint16_t pctype)
8976 static const uint64_t default_inset_table[] = {
8977 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8978 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8979 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8980 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8981 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8982 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8983 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8984 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8985 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8986 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8987 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8988 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8989 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8990 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8991 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8992 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8993 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8994 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8995 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8996 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8998 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8999 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9000 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9001 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9002 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9003 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9004 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9005 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9006 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9007 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9008 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9009 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9010 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9011 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9012 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9013 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9014 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9015 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9016 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9017 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9018 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9019 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9021 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9022 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9023 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9024 I40E_INSET_LAST_ETHER_TYPE,
9027 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9030 return default_inset_table[pctype];
9034 * Parse the input set from index to logical bit masks
9037 i40e_parse_input_set(uint64_t *inset,
9038 enum i40e_filter_pctype pctype,
9039 enum rte_eth_input_set_field *field,
9045 static const struct {
9046 enum rte_eth_input_set_field field;
9048 } inset_convert_table[] = {
9049 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9050 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9051 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9052 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9053 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9054 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9055 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9056 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9057 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9058 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9059 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9060 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9061 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9062 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9063 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9064 I40E_INSET_IPV6_NEXT_HDR},
9065 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9066 I40E_INSET_IPV6_HOP_LIMIT},
9067 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9068 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9069 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9070 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9071 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9072 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9073 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9074 I40E_INSET_SCTP_VT},
9075 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9076 I40E_INSET_TUNNEL_DMAC},
9077 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9078 I40E_INSET_VLAN_TUNNEL},
9079 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9080 I40E_INSET_TUNNEL_ID},
9081 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9082 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9083 I40E_INSET_FLEX_PAYLOAD_W1},
9084 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9085 I40E_INSET_FLEX_PAYLOAD_W2},
9086 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9087 I40E_INSET_FLEX_PAYLOAD_W3},
9088 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9089 I40E_INSET_FLEX_PAYLOAD_W4},
9090 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9091 I40E_INSET_FLEX_PAYLOAD_W5},
9092 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9093 I40E_INSET_FLEX_PAYLOAD_W6},
9094 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9095 I40E_INSET_FLEX_PAYLOAD_W7},
9096 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9097 I40E_INSET_FLEX_PAYLOAD_W8},
9100 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9103 /* Only one item allowed for default or all */
9105 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9106 *inset = i40e_get_default_input_set(pctype);
9108 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9109 *inset = I40E_INSET_NONE;
9114 for (i = 0, *inset = 0; i < size; i++) {
9115 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9116 if (field[i] == inset_convert_table[j].field) {
9117 *inset |= inset_convert_table[j].inset;
9122 /* It contains unsupported input set, return immediately */
9123 if (j == RTE_DIM(inset_convert_table))
9131 * Translate the input set from bit masks to register aware bit masks
9135 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9145 static const struct inset_map inset_map_common[] = {
9146 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9147 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9148 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9149 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9150 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9151 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9152 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9153 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9154 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9155 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9156 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9157 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9158 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9159 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9160 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9161 {I40E_INSET_TUNNEL_DMAC,
9162 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9163 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9164 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9165 {I40E_INSET_TUNNEL_SRC_PORT,
9166 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9167 {I40E_INSET_TUNNEL_DST_PORT,
9168 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9169 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9170 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9171 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9172 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9173 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9174 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9175 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9176 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9177 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9180 /* some different registers map in x722*/
9181 static const struct inset_map inset_map_diff_x722[] = {
9182 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9183 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9184 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9185 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9188 static const struct inset_map inset_map_diff_not_x722[] = {
9189 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9190 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9191 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9192 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9198 /* Translate input set to register aware inset */
9199 if (type == I40E_MAC_X722) {
9200 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9201 if (input & inset_map_diff_x722[i].inset)
9202 val |= inset_map_diff_x722[i].inset_reg;
9205 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9206 if (input & inset_map_diff_not_x722[i].inset)
9207 val |= inset_map_diff_not_x722[i].inset_reg;
9211 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9212 if (input & inset_map_common[i].inset)
9213 val |= inset_map_common[i].inset_reg;
9220 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9223 uint64_t inset_need_mask = inset;
9225 static const struct {
9228 } inset_mask_map[] = {
9229 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9230 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9231 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9232 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9233 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9234 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9235 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9236 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9239 if (!inset || !mask || !nb_elem)
9242 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9243 /* Clear the inset bit, if no MASK is required,
9244 * for example proto + ttl
9246 if ((inset & inset_mask_map[i].inset) ==
9247 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9248 inset_need_mask &= ~inset_mask_map[i].inset;
9249 if (!inset_need_mask)
9252 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9253 if ((inset_need_mask & inset_mask_map[i].inset) ==
9254 inset_mask_map[i].inset) {
9255 if (idx >= nb_elem) {
9256 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9259 mask[idx] = inset_mask_map[i].mask;
9268 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9270 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9272 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9274 i40e_write_rx_ctl(hw, addr, val);
9275 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9276 (uint32_t)i40e_read_rx_ctl(hw, addr));
9280 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9282 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9285 i40e_write_rx_ctl(hw, addr, val);
9287 "Global register [0x%08x] original: 0x%08x, after: 0x%08x",
9288 addr, reg, (uint32_t)i40e_read_rx_ctl(hw, addr));
9292 i40e_filter_input_set_init(struct i40e_pf *pf)
9294 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9295 enum i40e_filter_pctype pctype;
9296 uint64_t input_set, inset_reg;
9297 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9301 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9302 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9303 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9305 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9308 input_set = i40e_get_default_input_set(pctype);
9310 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9311 I40E_INSET_MASK_NUM_REG);
9314 if (pf->support_multi_driver && num > 0) {
9315 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9318 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9321 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9322 (uint32_t)(inset_reg & UINT32_MAX));
9323 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9324 (uint32_t)((inset_reg >>
9325 I40E_32_BIT_WIDTH) & UINT32_MAX));
9326 if (!pf->support_multi_driver) {
9327 i40e_check_write_global_reg(hw,
9328 I40E_GLQF_HASH_INSET(0, pctype),
9329 (uint32_t)(inset_reg & UINT32_MAX));
9330 i40e_check_write_global_reg(hw,
9331 I40E_GLQF_HASH_INSET(1, pctype),
9332 (uint32_t)((inset_reg >>
9333 I40E_32_BIT_WIDTH) & UINT32_MAX));
9335 for (i = 0; i < num; i++) {
9336 i40e_check_write_global_reg(hw,
9337 I40E_GLQF_FD_MSK(i, pctype),
9339 i40e_check_write_global_reg(hw,
9340 I40E_GLQF_HASH_MSK(i, pctype),
9343 /*clear unused mask registers of the pctype */
9344 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9345 i40e_check_write_global_reg(hw,
9346 I40E_GLQF_FD_MSK(i, pctype),
9348 i40e_check_write_global_reg(hw,
9349 I40E_GLQF_HASH_MSK(i, pctype),
9353 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9355 I40E_WRITE_FLUSH(hw);
9357 /* store the default input set */
9358 if (!pf->support_multi_driver)
9359 pf->hash_input_set[pctype] = input_set;
9360 pf->fdir.input_set[pctype] = input_set;
9363 if (!pf->support_multi_driver) {
9364 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9365 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9366 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9371 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9372 struct rte_eth_input_set_conf *conf)
9374 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9375 enum i40e_filter_pctype pctype;
9376 uint64_t input_set, inset_reg = 0;
9377 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9381 PMD_DRV_LOG(ERR, "Invalid pointer");
9384 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9385 conf->op != RTE_ETH_INPUT_SET_ADD) {
9386 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9390 if (pf->support_multi_driver) {
9391 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9395 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9396 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9397 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9401 if (hw->mac.type == I40E_MAC_X722) {
9402 /* get translated pctype value in fd pctype register */
9403 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9404 I40E_GLQF_FD_PCTYPES((int)pctype));
9407 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9410 PMD_DRV_LOG(ERR, "Failed to parse input set");
9414 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9415 /* get inset value in register */
9416 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9417 inset_reg <<= I40E_32_BIT_WIDTH;
9418 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9419 input_set |= pf->hash_input_set[pctype];
9421 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9422 I40E_INSET_MASK_NUM_REG);
9426 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9428 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9429 (uint32_t)(inset_reg & UINT32_MAX));
9430 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9431 (uint32_t)((inset_reg >>
9432 I40E_32_BIT_WIDTH) & UINT32_MAX));
9433 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9435 for (i = 0; i < num; i++)
9436 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9438 /*clear unused mask registers of the pctype */
9439 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9440 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9442 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9443 I40E_WRITE_FLUSH(hw);
9445 pf->hash_input_set[pctype] = input_set;
9450 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9451 struct rte_eth_input_set_conf *conf)
9453 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9454 enum i40e_filter_pctype pctype;
9455 uint64_t input_set, inset_reg = 0;
9456 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9460 PMD_DRV_LOG(ERR, "Invalid pointer");
9463 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9464 conf->op != RTE_ETH_INPUT_SET_ADD) {
9465 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9469 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9471 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9472 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9476 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9479 PMD_DRV_LOG(ERR, "Failed to parse input set");
9483 /* get inset value in register */
9484 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9485 inset_reg <<= I40E_32_BIT_WIDTH;
9486 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9488 /* Can not change the inset reg for flex payload for fdir,
9489 * it is done by writing I40E_PRTQF_FD_FLXINSET
9490 * in i40e_set_flex_mask_on_pctype.
9492 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9493 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9495 input_set |= pf->fdir.input_set[pctype];
9496 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9497 I40E_INSET_MASK_NUM_REG);
9500 if (pf->support_multi_driver && num > 0) {
9501 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9505 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9507 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9508 (uint32_t)(inset_reg & UINT32_MAX));
9509 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9510 (uint32_t)((inset_reg >>
9511 I40E_32_BIT_WIDTH) & UINT32_MAX));
9513 if (!pf->support_multi_driver) {
9514 for (i = 0; i < num; i++)
9515 i40e_check_write_global_reg(hw,
9516 I40E_GLQF_FD_MSK(i, pctype),
9518 /*clear unused mask registers of the pctype */
9519 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9520 i40e_check_write_global_reg(hw,
9521 I40E_GLQF_FD_MSK(i, pctype),
9523 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9525 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9527 I40E_WRITE_FLUSH(hw);
9529 pf->fdir.input_set[pctype] = input_set;
9534 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9539 PMD_DRV_LOG(ERR, "Invalid pointer");
9543 switch (info->info_type) {
9544 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9545 i40e_get_symmetric_hash_enable_per_port(hw,
9546 &(info->info.enable));
9548 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9549 ret = i40e_get_hash_filter_global_config(hw,
9550 &(info->info.global_conf));
9553 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9563 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9568 PMD_DRV_LOG(ERR, "Invalid pointer");
9572 switch (info->info_type) {
9573 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9574 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9576 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9577 ret = i40e_set_hash_filter_global_config(hw,
9578 &(info->info.global_conf));
9580 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9581 ret = i40e_hash_filter_inset_select(hw,
9582 &(info->info.input_set_conf));
9586 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9595 /* Operations for hash function */
9597 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9598 enum rte_filter_op filter_op,
9601 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9604 switch (filter_op) {
9605 case RTE_ETH_FILTER_NOP:
9607 case RTE_ETH_FILTER_GET:
9608 ret = i40e_hash_filter_get(hw,
9609 (struct rte_eth_hash_filter_info *)arg);
9611 case RTE_ETH_FILTER_SET:
9612 ret = i40e_hash_filter_set(hw,
9613 (struct rte_eth_hash_filter_info *)arg);
9616 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9625 /* Convert ethertype filter structure */
9627 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9628 struct i40e_ethertype_filter *filter)
9630 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9631 filter->input.ether_type = input->ether_type;
9632 filter->flags = input->flags;
9633 filter->queue = input->queue;
9638 /* Check if there exists the ehtertype filter */
9639 struct i40e_ethertype_filter *
9640 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9641 const struct i40e_ethertype_filter_input *input)
9645 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9649 return ethertype_rule->hash_map[ret];
9652 /* Add ethertype filter in SW list */
9654 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9655 struct i40e_ethertype_filter *filter)
9657 struct i40e_ethertype_rule *rule = &pf->ethertype;
9660 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9663 "Failed to insert ethertype filter"
9664 " to hash table %d!",
9668 rule->hash_map[ret] = filter;
9670 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9675 /* Delete ethertype filter in SW list */
9677 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9678 struct i40e_ethertype_filter_input *input)
9680 struct i40e_ethertype_rule *rule = &pf->ethertype;
9681 struct i40e_ethertype_filter *filter;
9684 ret = rte_hash_del_key(rule->hash_table, input);
9687 "Failed to delete ethertype filter"
9688 " to hash table %d!",
9692 filter = rule->hash_map[ret];
9693 rule->hash_map[ret] = NULL;
9695 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9702 * Configure ethertype filter, which can director packet by filtering
9703 * with mac address and ether_type or only ether_type
9706 i40e_ethertype_filter_set(struct i40e_pf *pf,
9707 struct rte_eth_ethertype_filter *filter,
9710 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9711 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9712 struct i40e_ethertype_filter *ethertype_filter, *node;
9713 struct i40e_ethertype_filter check_filter;
9714 struct i40e_control_filter_stats stats;
9718 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9719 PMD_DRV_LOG(ERR, "Invalid queue ID");
9722 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9723 filter->ether_type == ETHER_TYPE_IPv6) {
9725 "unsupported ether_type(0x%04x) in control packet filter.",
9726 filter->ether_type);
9729 if (filter->ether_type == ETHER_TYPE_VLAN)
9730 PMD_DRV_LOG(WARNING,
9731 "filter vlan ether_type in first tag is not supported.");
9733 /* Check if there is the filter in SW list */
9734 memset(&check_filter, 0, sizeof(check_filter));
9735 i40e_ethertype_filter_convert(filter, &check_filter);
9736 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9737 &check_filter.input);
9739 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9743 if (!add && !node) {
9744 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9748 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9749 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9750 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9751 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9752 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9754 memset(&stats, 0, sizeof(stats));
9755 ret = i40e_aq_add_rem_control_packet_filter(hw,
9756 filter->mac_addr.addr_bytes,
9757 filter->ether_type, flags,
9759 filter->queue, add, &stats, NULL);
9762 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9763 ret, stats.mac_etype_used, stats.etype_used,
9764 stats.mac_etype_free, stats.etype_free);
9768 /* Add or delete a filter in SW list */
9770 ethertype_filter = rte_zmalloc("ethertype_filter",
9771 sizeof(*ethertype_filter), 0);
9772 if (ethertype_filter == NULL) {
9773 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9777 rte_memcpy(ethertype_filter, &check_filter,
9778 sizeof(check_filter));
9779 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9781 rte_free(ethertype_filter);
9783 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9790 * Handle operations for ethertype filter.
9793 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9794 enum rte_filter_op filter_op,
9797 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9800 if (filter_op == RTE_ETH_FILTER_NOP)
9804 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9809 switch (filter_op) {
9810 case RTE_ETH_FILTER_ADD:
9811 ret = i40e_ethertype_filter_set(pf,
9812 (struct rte_eth_ethertype_filter *)arg,
9815 case RTE_ETH_FILTER_DELETE:
9816 ret = i40e_ethertype_filter_set(pf,
9817 (struct rte_eth_ethertype_filter *)arg,
9821 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9829 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9830 enum rte_filter_type filter_type,
9831 enum rte_filter_op filter_op,
9839 switch (filter_type) {
9840 case RTE_ETH_FILTER_NONE:
9841 /* For global configuration */
9842 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9844 case RTE_ETH_FILTER_HASH:
9845 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9847 case RTE_ETH_FILTER_MACVLAN:
9848 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9850 case RTE_ETH_FILTER_ETHERTYPE:
9851 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9853 case RTE_ETH_FILTER_TUNNEL:
9854 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9856 case RTE_ETH_FILTER_FDIR:
9857 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9859 case RTE_ETH_FILTER_GENERIC:
9860 if (filter_op != RTE_ETH_FILTER_GET)
9862 *(const void **)arg = &i40e_flow_ops;
9865 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9875 * Check and enable Extended Tag.
9876 * Enabling Extended Tag is important for 40G performance.
9879 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9881 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9885 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9888 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9892 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9893 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9898 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9901 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9905 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9906 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9909 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9910 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9913 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9920 * As some registers wouldn't be reset unless a global hardware reset,
9921 * hardware initialization is needed to put those registers into an
9922 * expected initial state.
9925 i40e_hw_init(struct rte_eth_dev *dev)
9927 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9929 i40e_enable_extended_tag(dev);
9931 /* clear the PF Queue Filter control register */
9932 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9934 /* Disable symmetric hash per port */
9935 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9939 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9940 * however this function will return only one highest pctype index,
9941 * which is not quite correct. This is known problem of i40e driver
9942 * and needs to be fixed later.
9944 enum i40e_filter_pctype
9945 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9948 uint64_t pctype_mask;
9950 if (flow_type < I40E_FLOW_TYPE_MAX) {
9951 pctype_mask = adapter->pctypes_tbl[flow_type];
9952 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9953 if (pctype_mask & (1ULL << i))
9954 return (enum i40e_filter_pctype)i;
9957 return I40E_FILTER_PCTYPE_INVALID;
9961 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9962 enum i40e_filter_pctype pctype)
9965 uint64_t pctype_mask = 1ULL << pctype;
9967 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9969 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9973 return RTE_ETH_FLOW_UNKNOWN;
9977 * On X710, performance number is far from the expectation on recent firmware
9978 * versions; on XL710, performance number is also far from the expectation on
9979 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9980 * mode is enabled and port MAC address is equal to the packet destination MAC
9981 * address. The fix for this issue may not be integrated in the following
9982 * firmware version. So the workaround in software driver is needed. It needs
9983 * to modify the initial values of 3 internal only registers for both X710 and
9984 * XL710. Note that the values for X710 or XL710 could be different, and the
9985 * workaround can be removed when it is fixed in firmware in the future.
9988 /* For both X710 and XL710 */
9989 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9990 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
9991 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9993 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9994 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9997 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9998 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10001 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10003 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10004 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10007 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10009 enum i40e_status_code status;
10010 struct i40e_aq_get_phy_abilities_resp phy_ab;
10011 int ret = -ENOTSUP;
10014 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10018 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10021 rte_delay_us(100000);
10023 status = i40e_aq_get_phy_capabilities(hw, false,
10024 true, &phy_ab, NULL);
10032 i40e_configure_registers(struct i40e_hw *hw)
10038 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10039 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10040 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10046 for (i = 0; i < RTE_DIM(reg_table); i++) {
10047 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10048 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10050 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10051 else /* For X710/XL710/XXV710 */
10052 if (hw->aq.fw_maj_ver < 6)
10054 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10057 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10060 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10061 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10063 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10064 else /* For X710/XL710/XXV710 */
10066 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10069 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10070 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
10071 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
10073 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
10074 else /* For X710 */
10076 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
10079 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10082 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10083 reg_table[i].addr);
10086 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10087 reg_table[i].addr, reg);
10088 if (reg == reg_table[i].val)
10091 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10092 reg_table[i].val, NULL);
10095 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10096 reg_table[i].val, reg_table[i].addr);
10099 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10100 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10104 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10105 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10106 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10107 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10109 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10114 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10115 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10119 /* Configure for double VLAN RX stripping */
10120 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10121 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10122 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10123 ret = i40e_aq_debug_write_register(hw,
10124 I40E_VSI_TSR(vsi->vsi_id),
10127 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10129 return I40E_ERR_CONFIG;
10133 /* Configure for double VLAN TX insertion */
10134 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10135 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10136 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10137 ret = i40e_aq_debug_write_register(hw,
10138 I40E_VSI_L2TAGSTXVALID(
10139 vsi->vsi_id), reg, NULL);
10142 "Failed to update VSI_L2TAGSTXVALID[%d]",
10144 return I40E_ERR_CONFIG;
10152 * i40e_aq_add_mirror_rule
10153 * @hw: pointer to the hardware structure
10154 * @seid: VEB seid to add mirror rule to
10155 * @dst_id: destination vsi seid
10156 * @entries: Buffer which contains the entities to be mirrored
10157 * @count: number of entities contained in the buffer
10158 * @rule_id:the rule_id of the rule to be added
10160 * Add a mirror rule for a given veb.
10163 static enum i40e_status_code
10164 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10165 uint16_t seid, uint16_t dst_id,
10166 uint16_t rule_type, uint16_t *entries,
10167 uint16_t count, uint16_t *rule_id)
10169 struct i40e_aq_desc desc;
10170 struct i40e_aqc_add_delete_mirror_rule cmd;
10171 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10172 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10175 enum i40e_status_code status;
10177 i40e_fill_default_direct_cmd_desc(&desc,
10178 i40e_aqc_opc_add_mirror_rule);
10179 memset(&cmd, 0, sizeof(cmd));
10181 buff_len = sizeof(uint16_t) * count;
10182 desc.datalen = rte_cpu_to_le_16(buff_len);
10184 desc.flags |= rte_cpu_to_le_16(
10185 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10186 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10187 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10188 cmd.num_entries = rte_cpu_to_le_16(count);
10189 cmd.seid = rte_cpu_to_le_16(seid);
10190 cmd.destination = rte_cpu_to_le_16(dst_id);
10192 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10193 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10195 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10196 hw->aq.asq_last_status, resp->rule_id,
10197 resp->mirror_rules_used, resp->mirror_rules_free);
10198 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10204 * i40e_aq_del_mirror_rule
10205 * @hw: pointer to the hardware structure
10206 * @seid: VEB seid to add mirror rule to
10207 * @entries: Buffer which contains the entities to be mirrored
10208 * @count: number of entities contained in the buffer
10209 * @rule_id:the rule_id of the rule to be delete
10211 * Delete a mirror rule for a given veb.
10214 static enum i40e_status_code
10215 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10216 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10217 uint16_t count, uint16_t rule_id)
10219 struct i40e_aq_desc desc;
10220 struct i40e_aqc_add_delete_mirror_rule cmd;
10221 uint16_t buff_len = 0;
10222 enum i40e_status_code status;
10225 i40e_fill_default_direct_cmd_desc(&desc,
10226 i40e_aqc_opc_delete_mirror_rule);
10227 memset(&cmd, 0, sizeof(cmd));
10228 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10229 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10231 cmd.num_entries = count;
10232 buff_len = sizeof(uint16_t) * count;
10233 desc.datalen = rte_cpu_to_le_16(buff_len);
10234 buff = (void *)entries;
10236 /* rule id is filled in destination field for deleting mirror rule */
10237 cmd.destination = rte_cpu_to_le_16(rule_id);
10239 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10240 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10241 cmd.seid = rte_cpu_to_le_16(seid);
10243 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10244 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10250 * i40e_mirror_rule_set
10251 * @dev: pointer to the hardware structure
10252 * @mirror_conf: mirror rule info
10253 * @sw_id: mirror rule's sw_id
10254 * @on: enable/disable
10256 * set a mirror rule.
10260 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10261 struct rte_eth_mirror_conf *mirror_conf,
10262 uint8_t sw_id, uint8_t on)
10264 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10265 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10266 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10267 struct i40e_mirror_rule *parent = NULL;
10268 uint16_t seid, dst_seid, rule_id;
10272 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10274 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10276 "mirror rule can not be configured without veb or vfs.");
10279 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10280 PMD_DRV_LOG(ERR, "mirror table is full.");
10283 if (mirror_conf->dst_pool > pf->vf_num) {
10284 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10285 mirror_conf->dst_pool);
10289 seid = pf->main_vsi->veb->seid;
10291 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10292 if (sw_id <= it->index) {
10298 if (mirr_rule && sw_id == mirr_rule->index) {
10300 PMD_DRV_LOG(ERR, "mirror rule exists.");
10303 ret = i40e_aq_del_mirror_rule(hw, seid,
10304 mirr_rule->rule_type,
10305 mirr_rule->entries,
10306 mirr_rule->num_entries, mirr_rule->id);
10309 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10310 ret, hw->aq.asq_last_status);
10313 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10314 rte_free(mirr_rule);
10315 pf->nb_mirror_rule--;
10319 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10323 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10324 sizeof(struct i40e_mirror_rule) , 0);
10326 PMD_DRV_LOG(ERR, "failed to allocate memory");
10327 return I40E_ERR_NO_MEMORY;
10329 switch (mirror_conf->rule_type) {
10330 case ETH_MIRROR_VLAN:
10331 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10332 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10333 mirr_rule->entries[j] =
10334 mirror_conf->vlan.vlan_id[i];
10339 PMD_DRV_LOG(ERR, "vlan is not specified.");
10340 rte_free(mirr_rule);
10343 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10345 case ETH_MIRROR_VIRTUAL_POOL_UP:
10346 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10347 /* check if the specified pool bit is out of range */
10348 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10349 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10350 rte_free(mirr_rule);
10353 for (i = 0, j = 0; i < pf->vf_num; i++) {
10354 if (mirror_conf->pool_mask & (1ULL << i)) {
10355 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10359 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10360 /* add pf vsi to entries */
10361 mirr_rule->entries[j] = pf->main_vsi_seid;
10365 PMD_DRV_LOG(ERR, "pool is not specified.");
10366 rte_free(mirr_rule);
10369 /* egress and ingress in aq commands means from switch but not port */
10370 mirr_rule->rule_type =
10371 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10372 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10373 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10375 case ETH_MIRROR_UPLINK_PORT:
10376 /* egress and ingress in aq commands means from switch but not port*/
10377 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10379 case ETH_MIRROR_DOWNLINK_PORT:
10380 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10383 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10384 mirror_conf->rule_type);
10385 rte_free(mirr_rule);
10389 /* If the dst_pool is equal to vf_num, consider it as PF */
10390 if (mirror_conf->dst_pool == pf->vf_num)
10391 dst_seid = pf->main_vsi_seid;
10393 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10395 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10396 mirr_rule->rule_type, mirr_rule->entries,
10400 "failed to add mirror rule: ret = %d, aq_err = %d.",
10401 ret, hw->aq.asq_last_status);
10402 rte_free(mirr_rule);
10406 mirr_rule->index = sw_id;
10407 mirr_rule->num_entries = j;
10408 mirr_rule->id = rule_id;
10409 mirr_rule->dst_vsi_seid = dst_seid;
10412 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10414 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10416 pf->nb_mirror_rule++;
10421 * i40e_mirror_rule_reset
10422 * @dev: pointer to the device
10423 * @sw_id: mirror rule's sw_id
10425 * reset a mirror rule.
10429 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10431 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10432 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10433 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10437 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10439 seid = pf->main_vsi->veb->seid;
10441 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10442 if (sw_id == it->index) {
10448 ret = i40e_aq_del_mirror_rule(hw, seid,
10449 mirr_rule->rule_type,
10450 mirr_rule->entries,
10451 mirr_rule->num_entries, mirr_rule->id);
10454 "failed to remove mirror rule: status = %d, aq_err = %d.",
10455 ret, hw->aq.asq_last_status);
10458 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10459 rte_free(mirr_rule);
10460 pf->nb_mirror_rule--;
10462 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10469 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10471 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10472 uint64_t systim_cycles;
10474 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10475 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10478 return systim_cycles;
10482 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10484 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10485 uint64_t rx_tstamp;
10487 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10488 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10495 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10497 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10498 uint64_t tx_tstamp;
10500 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10501 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10508 i40e_start_timecounters(struct rte_eth_dev *dev)
10510 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10511 struct i40e_adapter *adapter =
10512 (struct i40e_adapter *)dev->data->dev_private;
10513 struct rte_eth_link link;
10514 uint32_t tsync_inc_l;
10515 uint32_t tsync_inc_h;
10517 /* Get current link speed. */
10518 i40e_dev_link_update(dev, 1);
10519 rte_eth_linkstatus_get(dev, &link);
10521 switch (link.link_speed) {
10522 case ETH_SPEED_NUM_40G:
10523 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10524 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10526 case ETH_SPEED_NUM_10G:
10527 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10528 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10530 case ETH_SPEED_NUM_1G:
10531 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10532 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10539 /* Set the timesync increment value. */
10540 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10541 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10543 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10544 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10545 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10547 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10548 adapter->systime_tc.cc_shift = 0;
10549 adapter->systime_tc.nsec_mask = 0;
10551 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10552 adapter->rx_tstamp_tc.cc_shift = 0;
10553 adapter->rx_tstamp_tc.nsec_mask = 0;
10555 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10556 adapter->tx_tstamp_tc.cc_shift = 0;
10557 adapter->tx_tstamp_tc.nsec_mask = 0;
10561 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10563 struct i40e_adapter *adapter =
10564 (struct i40e_adapter *)dev->data->dev_private;
10566 adapter->systime_tc.nsec += delta;
10567 adapter->rx_tstamp_tc.nsec += delta;
10568 adapter->tx_tstamp_tc.nsec += delta;
10574 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10577 struct i40e_adapter *adapter =
10578 (struct i40e_adapter *)dev->data->dev_private;
10580 ns = rte_timespec_to_ns(ts);
10582 /* Set the timecounters to a new value. */
10583 adapter->systime_tc.nsec = ns;
10584 adapter->rx_tstamp_tc.nsec = ns;
10585 adapter->tx_tstamp_tc.nsec = ns;
10591 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10593 uint64_t ns, systime_cycles;
10594 struct i40e_adapter *adapter =
10595 (struct i40e_adapter *)dev->data->dev_private;
10597 systime_cycles = i40e_read_systime_cyclecounter(dev);
10598 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10599 *ts = rte_ns_to_timespec(ns);
10605 i40e_timesync_enable(struct rte_eth_dev *dev)
10607 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10608 uint32_t tsync_ctl_l;
10609 uint32_t tsync_ctl_h;
10611 /* Stop the timesync system time. */
10612 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10613 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10614 /* Reset the timesync system time value. */
10615 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10616 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10618 i40e_start_timecounters(dev);
10620 /* Clear timesync registers. */
10621 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10622 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10623 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10624 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10625 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10626 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10628 /* Enable timestamping of PTP packets. */
10629 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10630 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10632 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10633 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10634 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10636 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10637 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10643 i40e_timesync_disable(struct rte_eth_dev *dev)
10645 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10646 uint32_t tsync_ctl_l;
10647 uint32_t tsync_ctl_h;
10649 /* Disable timestamping of transmitted PTP packets. */
10650 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10651 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10653 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10654 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10656 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10657 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10659 /* Reset the timesync increment value. */
10660 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10661 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10667 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10668 struct timespec *timestamp, uint32_t flags)
10670 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10671 struct i40e_adapter *adapter =
10672 (struct i40e_adapter *)dev->data->dev_private;
10674 uint32_t sync_status;
10675 uint32_t index = flags & 0x03;
10676 uint64_t rx_tstamp_cycles;
10679 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10680 if ((sync_status & (1 << index)) == 0)
10683 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10684 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10685 *timestamp = rte_ns_to_timespec(ns);
10691 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10692 struct timespec *timestamp)
10694 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10695 struct i40e_adapter *adapter =
10696 (struct i40e_adapter *)dev->data->dev_private;
10698 uint32_t sync_status;
10699 uint64_t tx_tstamp_cycles;
10702 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10703 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10706 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10707 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10708 *timestamp = rte_ns_to_timespec(ns);
10714 * i40e_parse_dcb_configure - parse dcb configure from user
10715 * @dev: the device being configured
10716 * @dcb_cfg: pointer of the result of parse
10717 * @*tc_map: bit map of enabled traffic classes
10719 * Returns 0 on success, negative value on failure
10722 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10723 struct i40e_dcbx_config *dcb_cfg,
10726 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10727 uint8_t i, tc_bw, bw_lf;
10729 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10731 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10732 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10733 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10737 /* assume each tc has the same bw */
10738 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10739 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10740 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10741 /* to ensure the sum of tcbw is equal to 100 */
10742 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10743 for (i = 0; i < bw_lf; i++)
10744 dcb_cfg->etscfg.tcbwtable[i]++;
10746 /* assume each tc has the same Transmission Selection Algorithm */
10747 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10748 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10750 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10751 dcb_cfg->etscfg.prioritytable[i] =
10752 dcb_rx_conf->dcb_tc[i];
10754 /* FW needs one App to configure HW */
10755 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10756 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10757 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10758 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10760 if (dcb_rx_conf->nb_tcs == 0)
10761 *tc_map = 1; /* tc0 only */
10763 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10765 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10766 dcb_cfg->pfc.willing = 0;
10767 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10768 dcb_cfg->pfc.pfcenable = *tc_map;
10774 static enum i40e_status_code
10775 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10776 struct i40e_aqc_vsi_properties_data *info,
10777 uint8_t enabled_tcmap)
10779 enum i40e_status_code ret;
10780 int i, total_tc = 0;
10781 uint16_t qpnum_per_tc, bsf, qp_idx;
10782 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10783 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10784 uint16_t used_queues;
10786 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10787 if (ret != I40E_SUCCESS)
10790 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10791 if (enabled_tcmap & (1 << i))
10796 vsi->enabled_tc = enabled_tcmap;
10798 /* different VSI has different queues assigned */
10799 if (vsi->type == I40E_VSI_MAIN)
10800 used_queues = dev_data->nb_rx_queues -
10801 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10802 else if (vsi->type == I40E_VSI_VMDQ2)
10803 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10805 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10806 return I40E_ERR_NO_AVAILABLE_VSI;
10809 qpnum_per_tc = used_queues / total_tc;
10810 /* Number of queues per enabled TC */
10811 if (qpnum_per_tc == 0) {
10812 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10813 return I40E_ERR_INVALID_QP_ID;
10815 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10816 I40E_MAX_Q_PER_TC);
10817 bsf = rte_bsf32(qpnum_per_tc);
10820 * Configure TC and queue mapping parameters, for enabled TC,
10821 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10822 * default queue will serve it.
10825 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10826 if (vsi->enabled_tc & (1 << i)) {
10827 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10828 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10829 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10830 qp_idx += qpnum_per_tc;
10832 info->tc_mapping[i] = 0;
10835 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10836 if (vsi->type == I40E_VSI_SRIOV) {
10837 info->mapping_flags |=
10838 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10839 for (i = 0; i < vsi->nb_qps; i++)
10840 info->queue_mapping[i] =
10841 rte_cpu_to_le_16(vsi->base_queue + i);
10843 info->mapping_flags |=
10844 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10845 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10847 info->valid_sections |=
10848 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10850 return I40E_SUCCESS;
10854 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10855 * @veb: VEB to be configured
10856 * @tc_map: enabled TC bitmap
10858 * Returns 0 on success, negative value on failure
10860 static enum i40e_status_code
10861 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10863 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10864 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10865 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10866 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10867 enum i40e_status_code ret = I40E_SUCCESS;
10871 /* Check if enabled_tc is same as existing or new TCs */
10872 if (veb->enabled_tc == tc_map)
10875 /* configure tc bandwidth */
10876 memset(&veb_bw, 0, sizeof(veb_bw));
10877 veb_bw.tc_valid_bits = tc_map;
10878 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10879 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10880 if (tc_map & BIT_ULL(i))
10881 veb_bw.tc_bw_share_credits[i] = 1;
10883 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10887 "AQ command Config switch_comp BW allocation per TC failed = %d",
10888 hw->aq.asq_last_status);
10892 memset(&ets_query, 0, sizeof(ets_query));
10893 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10895 if (ret != I40E_SUCCESS) {
10897 "Failed to get switch_comp ETS configuration %u",
10898 hw->aq.asq_last_status);
10901 memset(&bw_query, 0, sizeof(bw_query));
10902 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10904 if (ret != I40E_SUCCESS) {
10906 "Failed to get switch_comp bandwidth configuration %u",
10907 hw->aq.asq_last_status);
10911 /* store and print out BW info */
10912 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10913 veb->bw_info.bw_max = ets_query.tc_bw_max;
10914 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10915 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10916 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10917 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10918 I40E_16_BIT_WIDTH);
10919 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10920 veb->bw_info.bw_ets_share_credits[i] =
10921 bw_query.tc_bw_share_credits[i];
10922 veb->bw_info.bw_ets_credits[i] =
10923 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10924 /* 4 bits per TC, 4th bit is reserved */
10925 veb->bw_info.bw_ets_max[i] =
10926 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10927 RTE_LEN2MASK(3, uint8_t));
10928 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10929 veb->bw_info.bw_ets_share_credits[i]);
10930 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10931 veb->bw_info.bw_ets_credits[i]);
10932 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10933 veb->bw_info.bw_ets_max[i]);
10936 veb->enabled_tc = tc_map;
10943 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10944 * @vsi: VSI to be configured
10945 * @tc_map: enabled TC bitmap
10947 * Returns 0 on success, negative value on failure
10949 static enum i40e_status_code
10950 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10952 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10953 struct i40e_vsi_context ctxt;
10954 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10955 enum i40e_status_code ret = I40E_SUCCESS;
10958 /* Check if enabled_tc is same as existing or new TCs */
10959 if (vsi->enabled_tc == tc_map)
10962 /* configure tc bandwidth */
10963 memset(&bw_data, 0, sizeof(bw_data));
10964 bw_data.tc_valid_bits = tc_map;
10965 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10966 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10967 if (tc_map & BIT_ULL(i))
10968 bw_data.tc_bw_credits[i] = 1;
10970 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10973 "AQ command Config VSI BW allocation per TC failed = %d",
10974 hw->aq.asq_last_status);
10977 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10978 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10980 /* Update Queue Pairs Mapping for currently enabled UPs */
10981 ctxt.seid = vsi->seid;
10982 ctxt.pf_num = hw->pf_id;
10984 ctxt.uplink_seid = vsi->uplink_seid;
10985 ctxt.info = vsi->info;
10987 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10991 /* Update the VSI after updating the VSI queue-mapping information */
10992 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10994 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10995 hw->aq.asq_last_status);
10998 /* update the local VSI info with updated queue map */
10999 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11000 sizeof(vsi->info.tc_mapping));
11001 rte_memcpy(&vsi->info.queue_mapping,
11002 &ctxt.info.queue_mapping,
11003 sizeof(vsi->info.queue_mapping));
11004 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11005 vsi->info.valid_sections = 0;
11007 /* query and update current VSI BW information */
11008 ret = i40e_vsi_get_bw_config(vsi);
11011 "Failed updating vsi bw info, err %s aq_err %s",
11012 i40e_stat_str(hw, ret),
11013 i40e_aq_str(hw, hw->aq.asq_last_status));
11017 vsi->enabled_tc = tc_map;
11024 * i40e_dcb_hw_configure - program the dcb setting to hw
11025 * @pf: pf the configuration is taken on
11026 * @new_cfg: new configuration
11027 * @tc_map: enabled TC bitmap
11029 * Returns 0 on success, negative value on failure
11031 static enum i40e_status_code
11032 i40e_dcb_hw_configure(struct i40e_pf *pf,
11033 struct i40e_dcbx_config *new_cfg,
11036 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11037 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11038 struct i40e_vsi *main_vsi = pf->main_vsi;
11039 struct i40e_vsi_list *vsi_list;
11040 enum i40e_status_code ret;
11044 /* Use the FW API if FW > v4.4*/
11045 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11046 (hw->aq.fw_maj_ver >= 5))) {
11048 "FW < v4.4, can not use FW LLDP API to configure DCB");
11049 return I40E_ERR_FIRMWARE_API_VERSION;
11052 /* Check if need reconfiguration */
11053 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11054 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11055 return I40E_SUCCESS;
11058 /* Copy the new config to the current config */
11059 *old_cfg = *new_cfg;
11060 old_cfg->etsrec = old_cfg->etscfg;
11061 ret = i40e_set_dcb_config(hw);
11063 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11064 i40e_stat_str(hw, ret),
11065 i40e_aq_str(hw, hw->aq.asq_last_status));
11068 /* set receive Arbiter to RR mode and ETS scheme by default */
11069 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11070 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11071 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11072 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11073 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11074 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11075 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11076 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11077 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11078 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11079 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11080 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11081 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11083 /* get local mib to check whether it is configured correctly */
11085 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11086 /* Get Local DCB Config */
11087 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11088 &hw->local_dcbx_config);
11090 /* if Veb is created, need to update TC of it at first */
11091 if (main_vsi->veb) {
11092 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11094 PMD_INIT_LOG(WARNING,
11095 "Failed configuring TC for VEB seid=%d",
11096 main_vsi->veb->seid);
11098 /* Update each VSI */
11099 i40e_vsi_config_tc(main_vsi, tc_map);
11100 if (main_vsi->veb) {
11101 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11102 /* Beside main VSI and VMDQ VSIs, only enable default
11103 * TC for other VSIs
11105 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11106 ret = i40e_vsi_config_tc(vsi_list->vsi,
11109 ret = i40e_vsi_config_tc(vsi_list->vsi,
11110 I40E_DEFAULT_TCMAP);
11112 PMD_INIT_LOG(WARNING,
11113 "Failed configuring TC for VSI seid=%d",
11114 vsi_list->vsi->seid);
11118 return I40E_SUCCESS;
11122 * i40e_dcb_init_configure - initial dcb config
11123 * @dev: device being configured
11124 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11126 * Returns 0 on success, negative value on failure
11129 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11131 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11132 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11135 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11136 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11140 /* DCB initialization:
11141 * Update DCB configuration from the Firmware and configure
11142 * LLDP MIB change event.
11144 if (sw_dcb == TRUE) {
11145 ret = i40e_init_dcb(hw);
11146 /* If lldp agent is stopped, the return value from
11147 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11148 * adminq status. Otherwise, it should return success.
11150 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11151 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11152 memset(&hw->local_dcbx_config, 0,
11153 sizeof(struct i40e_dcbx_config));
11154 /* set dcb default configuration */
11155 hw->local_dcbx_config.etscfg.willing = 0;
11156 hw->local_dcbx_config.etscfg.maxtcs = 0;
11157 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11158 hw->local_dcbx_config.etscfg.tsatable[0] =
11160 /* all UPs mapping to TC0 */
11161 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11162 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11163 hw->local_dcbx_config.etsrec =
11164 hw->local_dcbx_config.etscfg;
11165 hw->local_dcbx_config.pfc.willing = 0;
11166 hw->local_dcbx_config.pfc.pfccap =
11167 I40E_MAX_TRAFFIC_CLASS;
11168 /* FW needs one App to configure HW */
11169 hw->local_dcbx_config.numapps = 1;
11170 hw->local_dcbx_config.app[0].selector =
11171 I40E_APP_SEL_ETHTYPE;
11172 hw->local_dcbx_config.app[0].priority = 3;
11173 hw->local_dcbx_config.app[0].protocolid =
11174 I40E_APP_PROTOID_FCOE;
11175 ret = i40e_set_dcb_config(hw);
11178 "default dcb config fails. err = %d, aq_err = %d.",
11179 ret, hw->aq.asq_last_status);
11184 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11185 ret, hw->aq.asq_last_status);
11189 ret = i40e_aq_start_lldp(hw, NULL);
11190 if (ret != I40E_SUCCESS)
11191 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11193 ret = i40e_init_dcb(hw);
11195 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11197 "HW doesn't support DCBX offload.");
11202 "DCBX configuration failed, err = %d, aq_err = %d.",
11203 ret, hw->aq.asq_last_status);
11211 * i40e_dcb_setup - setup dcb related config
11212 * @dev: device being configured
11214 * Returns 0 on success, negative value on failure
11217 i40e_dcb_setup(struct rte_eth_dev *dev)
11219 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11220 struct i40e_dcbx_config dcb_cfg;
11221 uint8_t tc_map = 0;
11224 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11225 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11229 if (pf->vf_num != 0)
11230 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11232 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11234 PMD_INIT_LOG(ERR, "invalid dcb config");
11237 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11239 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11247 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11248 struct rte_eth_dcb_info *dcb_info)
11250 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11251 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11252 struct i40e_vsi *vsi = pf->main_vsi;
11253 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11254 uint16_t bsf, tc_mapping;
11257 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11258 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11260 dcb_info->nb_tcs = 1;
11261 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11262 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11263 for (i = 0; i < dcb_info->nb_tcs; i++)
11264 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11266 /* get queue mapping if vmdq is disabled */
11267 if (!pf->nb_cfg_vmdq_vsi) {
11268 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11269 if (!(vsi->enabled_tc & (1 << i)))
11271 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11272 dcb_info->tc_queue.tc_rxq[j][i].base =
11273 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11274 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11275 dcb_info->tc_queue.tc_txq[j][i].base =
11276 dcb_info->tc_queue.tc_rxq[j][i].base;
11277 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11278 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11279 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11280 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11281 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11286 /* get queue mapping if vmdq is enabled */
11288 vsi = pf->vmdq[j].vsi;
11289 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11290 if (!(vsi->enabled_tc & (1 << i)))
11292 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11293 dcb_info->tc_queue.tc_rxq[j][i].base =
11294 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11295 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11296 dcb_info->tc_queue.tc_txq[j][i].base =
11297 dcb_info->tc_queue.tc_rxq[j][i].base;
11298 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11299 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11300 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11301 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11302 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11305 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11310 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11312 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11313 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11314 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11315 uint16_t msix_intr;
11317 msix_intr = intr_handle->intr_vec[queue_id];
11318 if (msix_intr == I40E_MISC_VEC_ID)
11319 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11320 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11321 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11322 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11325 I40E_PFINT_DYN_CTLN(msix_intr -
11326 I40E_RX_VEC_START),
11327 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11328 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11329 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11331 I40E_WRITE_FLUSH(hw);
11332 rte_intr_enable(&pci_dev->intr_handle);
11338 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11340 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11341 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11342 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11343 uint16_t msix_intr;
11345 msix_intr = intr_handle->intr_vec[queue_id];
11346 if (msix_intr == I40E_MISC_VEC_ID)
11347 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11348 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11351 I40E_PFINT_DYN_CTLN(msix_intr -
11352 I40E_RX_VEC_START),
11353 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11354 I40E_WRITE_FLUSH(hw);
11359 static int i40e_get_regs(struct rte_eth_dev *dev,
11360 struct rte_dev_reg_info *regs)
11362 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11363 uint32_t *ptr_data = regs->data;
11364 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11365 const struct i40e_reg_info *reg_info;
11367 if (ptr_data == NULL) {
11368 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11369 regs->width = sizeof(uint32_t);
11373 /* The first few registers have to be read using AQ operations */
11375 while (i40e_regs_adminq[reg_idx].name) {
11376 reg_info = &i40e_regs_adminq[reg_idx++];
11377 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11379 arr_idx2 <= reg_info->count2;
11381 reg_offset = arr_idx * reg_info->stride1 +
11382 arr_idx2 * reg_info->stride2;
11383 reg_offset += reg_info->base_addr;
11384 ptr_data[reg_offset >> 2] =
11385 i40e_read_rx_ctl(hw, reg_offset);
11389 /* The remaining registers can be read using primitives */
11391 while (i40e_regs_others[reg_idx].name) {
11392 reg_info = &i40e_regs_others[reg_idx++];
11393 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11395 arr_idx2 <= reg_info->count2;
11397 reg_offset = arr_idx * reg_info->stride1 +
11398 arr_idx2 * reg_info->stride2;
11399 reg_offset += reg_info->base_addr;
11400 ptr_data[reg_offset >> 2] =
11401 I40E_READ_REG(hw, reg_offset);
11408 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11410 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11412 /* Convert word count to byte count */
11413 return hw->nvm.sr_size << 1;
11416 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11417 struct rte_dev_eeprom_info *eeprom)
11419 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11420 uint16_t *data = eeprom->data;
11421 uint16_t offset, length, cnt_words;
11424 offset = eeprom->offset >> 1;
11425 length = eeprom->length >> 1;
11426 cnt_words = length;
11428 if (offset > hw->nvm.sr_size ||
11429 offset + length > hw->nvm.sr_size) {
11430 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11434 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11436 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11437 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11438 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11445 static int i40e_get_module_info(struct rte_eth_dev *dev,
11446 struct rte_eth_dev_module_info *modinfo)
11448 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11449 uint32_t sff8472_comp = 0;
11450 uint32_t sff8472_swap = 0;
11451 uint32_t sff8636_rev = 0;
11452 i40e_status status;
11455 /* Check if firmware supports reading module EEPROM. */
11456 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11458 "Module EEPROM memory read not supported. "
11459 "Please update the NVM image.\n");
11463 status = i40e_update_link_info(hw);
11467 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11469 "Cannot read module EEPROM memory. "
11470 "No module connected.\n");
11474 type = hw->phy.link_info.module_type[0];
11477 case I40E_MODULE_TYPE_SFP:
11478 status = i40e_aq_get_phy_register(hw,
11479 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11480 I40E_I2C_EEPROM_DEV_ADDR,
11481 I40E_MODULE_SFF_8472_COMP,
11482 &sff8472_comp, NULL);
11486 status = i40e_aq_get_phy_register(hw,
11487 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11488 I40E_I2C_EEPROM_DEV_ADDR,
11489 I40E_MODULE_SFF_8472_SWAP,
11490 &sff8472_swap, NULL);
11494 /* Check if the module requires address swap to access
11495 * the other EEPROM memory page.
11497 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11498 PMD_DRV_LOG(WARNING,
11499 "Module address swap to access "
11500 "page 0xA2 is not supported.\n");
11501 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11502 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11503 } else if (sff8472_comp == 0x00) {
11504 /* Module is not SFF-8472 compliant */
11505 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11506 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11508 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11509 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11512 case I40E_MODULE_TYPE_QSFP_PLUS:
11513 /* Read from memory page 0. */
11514 status = i40e_aq_get_phy_register(hw,
11515 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11517 I40E_MODULE_REVISION_ADDR,
11518 &sff8636_rev, NULL);
11521 /* Determine revision compliance byte */
11522 if (sff8636_rev > 0x02) {
11523 /* Module is SFF-8636 compliant */
11524 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11525 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11527 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11528 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11531 case I40E_MODULE_TYPE_QSFP28:
11532 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11533 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11536 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11542 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11543 struct rte_dev_eeprom_info *info)
11545 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11546 bool is_sfp = false;
11547 i40e_status status;
11548 uint8_t *data = info->data;
11549 uint32_t value = 0;
11552 if (!info || !info->length || !data)
11555 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11558 for (i = 0; i < info->length; i++) {
11559 u32 offset = i + info->offset;
11560 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11562 /* Check if we need to access the other memory page */
11564 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11565 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11566 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11569 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11570 /* Compute memory page number and offset. */
11571 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11575 status = i40e_aq_get_phy_register(hw,
11576 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11577 addr, offset, &value, NULL);
11580 data[i] = (uint8_t)value;
11585 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11586 struct ether_addr *mac_addr)
11588 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11589 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11590 struct i40e_vsi *vsi = pf->main_vsi;
11591 struct i40e_mac_filter_info mac_filter;
11592 struct i40e_mac_filter *f;
11595 if (!is_valid_assigned_ether_addr(mac_addr)) {
11596 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11600 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11601 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11606 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11610 mac_filter = f->mac_info;
11611 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11612 if (ret != I40E_SUCCESS) {
11613 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11616 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11617 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11618 if (ret != I40E_SUCCESS) {
11619 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11622 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11624 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11625 mac_addr->addr_bytes, NULL);
11626 if (ret != I40E_SUCCESS) {
11627 PMD_DRV_LOG(ERR, "Failed to change mac");
11635 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11637 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11638 struct rte_eth_dev_data *dev_data = pf->dev_data;
11639 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11642 /* check if mtu is within the allowed range */
11643 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11646 /* mtu setting is forbidden if port is start */
11647 if (dev_data->dev_started) {
11648 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11649 dev_data->port_id);
11653 if (frame_size > ETHER_MAX_LEN)
11654 dev_data->dev_conf.rxmode.offloads |=
11655 DEV_RX_OFFLOAD_JUMBO_FRAME;
11657 dev_data->dev_conf.rxmode.offloads &=
11658 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11660 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11665 /* Restore ethertype filter */
11667 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11669 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11670 struct i40e_ethertype_filter_list
11671 *ethertype_list = &pf->ethertype.ethertype_list;
11672 struct i40e_ethertype_filter *f;
11673 struct i40e_control_filter_stats stats;
11676 TAILQ_FOREACH(f, ethertype_list, rules) {
11678 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11679 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11680 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11681 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11682 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11684 memset(&stats, 0, sizeof(stats));
11685 i40e_aq_add_rem_control_packet_filter(hw,
11686 f->input.mac_addr.addr_bytes,
11687 f->input.ether_type,
11688 flags, pf->main_vsi->seid,
11689 f->queue, 1, &stats, NULL);
11691 PMD_DRV_LOG(INFO, "Ethertype filter:"
11692 " mac_etype_used = %u, etype_used = %u,"
11693 " mac_etype_free = %u, etype_free = %u",
11694 stats.mac_etype_used, stats.etype_used,
11695 stats.mac_etype_free, stats.etype_free);
11698 /* Restore tunnel filter */
11700 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11702 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11703 struct i40e_vsi *vsi;
11704 struct i40e_pf_vf *vf;
11705 struct i40e_tunnel_filter_list
11706 *tunnel_list = &pf->tunnel.tunnel_list;
11707 struct i40e_tunnel_filter *f;
11708 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11709 bool big_buffer = 0;
11711 TAILQ_FOREACH(f, tunnel_list, rules) {
11713 vsi = pf->main_vsi;
11715 vf = &pf->vfs[f->vf_id];
11718 memset(&cld_filter, 0, sizeof(cld_filter));
11719 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11720 (struct ether_addr *)&cld_filter.element.outer_mac);
11721 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11722 (struct ether_addr *)&cld_filter.element.inner_mac);
11723 cld_filter.element.inner_vlan = f->input.inner_vlan;
11724 cld_filter.element.flags = f->input.flags;
11725 cld_filter.element.tenant_id = f->input.tenant_id;
11726 cld_filter.element.queue_number = f->queue;
11727 rte_memcpy(cld_filter.general_fields,
11728 f->input.general_fields,
11729 sizeof(f->input.general_fields));
11731 if (((f->input.flags &
11732 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11733 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11735 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11736 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11738 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11739 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11743 i40e_aq_add_cloud_filters_big_buffer(hw,
11744 vsi->seid, &cld_filter, 1);
11746 i40e_aq_add_cloud_filters(hw, vsi->seid,
11747 &cld_filter.element, 1);
11751 /* Restore rss filter */
11753 i40e_rss_filter_restore(struct i40e_pf *pf)
11755 struct i40e_rte_flow_rss_conf *conf =
11757 if (conf->conf.queue_num)
11758 i40e_config_rss_filter(pf, conf, TRUE);
11762 i40e_filter_restore(struct i40e_pf *pf)
11764 i40e_ethertype_filter_restore(pf);
11765 i40e_tunnel_filter_restore(pf);
11766 i40e_fdir_filter_restore(pf);
11767 i40e_rss_filter_restore(pf);
11771 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11773 if (strcmp(dev->device->driver->name, drv->driver.name))
11780 is_i40e_supported(struct rte_eth_dev *dev)
11782 return is_device_supported(dev, &rte_i40e_pmd);
11785 struct i40e_customized_pctype*
11786 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11790 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11791 if (pf->customized_pctype[i].index == index)
11792 return &pf->customized_pctype[i];
11798 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11799 uint32_t pkg_size, uint32_t proto_num,
11800 struct rte_pmd_i40e_proto_info *proto,
11801 enum rte_pmd_i40e_package_op op)
11803 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11804 uint32_t pctype_num;
11805 struct rte_pmd_i40e_ptype_info *pctype;
11806 uint32_t buff_size;
11807 struct i40e_customized_pctype *new_pctype = NULL;
11809 uint8_t pctype_value;
11814 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11815 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11816 PMD_DRV_LOG(ERR, "Unsupported operation.");
11820 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11821 (uint8_t *)&pctype_num, sizeof(pctype_num),
11822 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11824 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11828 PMD_DRV_LOG(INFO, "No new pctype added");
11832 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11833 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11835 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11838 /* get information about new pctype list */
11839 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11840 (uint8_t *)pctype, buff_size,
11841 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11843 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11848 /* Update customized pctype. */
11849 for (i = 0; i < pctype_num; i++) {
11850 pctype_value = pctype[i].ptype_id;
11851 memset(name, 0, sizeof(name));
11852 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11853 proto_id = pctype[i].protocols[j];
11854 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11856 for (n = 0; n < proto_num; n++) {
11857 if (proto[n].proto_id != proto_id)
11859 strcat(name, proto[n].name);
11864 name[strlen(name) - 1] = '\0';
11865 if (!strcmp(name, "GTPC"))
11867 i40e_find_customized_pctype(pf,
11868 I40E_CUSTOMIZED_GTPC);
11869 else if (!strcmp(name, "GTPU_IPV4"))
11871 i40e_find_customized_pctype(pf,
11872 I40E_CUSTOMIZED_GTPU_IPV4);
11873 else if (!strcmp(name, "GTPU_IPV6"))
11875 i40e_find_customized_pctype(pf,
11876 I40E_CUSTOMIZED_GTPU_IPV6);
11877 else if (!strcmp(name, "GTPU"))
11879 i40e_find_customized_pctype(pf,
11880 I40E_CUSTOMIZED_GTPU);
11882 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11883 new_pctype->pctype = pctype_value;
11884 new_pctype->valid = true;
11886 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11887 new_pctype->valid = false;
11897 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11898 uint32_t pkg_size, uint32_t proto_num,
11899 struct rte_pmd_i40e_proto_info *proto,
11900 enum rte_pmd_i40e_package_op op)
11902 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11903 uint16_t port_id = dev->data->port_id;
11904 uint32_t ptype_num;
11905 struct rte_pmd_i40e_ptype_info *ptype;
11906 uint32_t buff_size;
11908 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11913 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11914 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11915 PMD_DRV_LOG(ERR, "Unsupported operation.");
11919 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11920 rte_pmd_i40e_ptype_mapping_reset(port_id);
11924 /* get information about new ptype num */
11925 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11926 (uint8_t *)&ptype_num, sizeof(ptype_num),
11927 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11929 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11933 PMD_DRV_LOG(INFO, "No new ptype added");
11937 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11938 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11940 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11944 /* get information about new ptype list */
11945 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11946 (uint8_t *)ptype, buff_size,
11947 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11949 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11954 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11955 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11956 if (!ptype_mapping) {
11957 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11962 /* Update ptype mapping table. */
11963 for (i = 0; i < ptype_num; i++) {
11964 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11965 ptype_mapping[i].sw_ptype = 0;
11967 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11968 proto_id = ptype[i].protocols[j];
11969 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11971 for (n = 0; n < proto_num; n++) {
11972 if (proto[n].proto_id != proto_id)
11974 memset(name, 0, sizeof(name));
11975 strcpy(name, proto[n].name);
11976 if (!strncasecmp(name, "PPPOE", 5))
11977 ptype_mapping[i].sw_ptype |=
11978 RTE_PTYPE_L2_ETHER_PPPOE;
11979 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11981 ptype_mapping[i].sw_ptype |=
11982 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11983 ptype_mapping[i].sw_ptype |=
11985 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11987 ptype_mapping[i].sw_ptype |=
11988 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11989 ptype_mapping[i].sw_ptype |=
11990 RTE_PTYPE_INNER_L4_FRAG;
11991 } else if (!strncasecmp(name, "OIPV4", 5)) {
11992 ptype_mapping[i].sw_ptype |=
11993 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11995 } else if (!strncasecmp(name, "IPV4", 4) &&
11997 ptype_mapping[i].sw_ptype |=
11998 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11999 else if (!strncasecmp(name, "IPV4", 4) &&
12001 ptype_mapping[i].sw_ptype |=
12002 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12003 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12005 ptype_mapping[i].sw_ptype |=
12006 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12007 ptype_mapping[i].sw_ptype |=
12009 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12011 ptype_mapping[i].sw_ptype |=
12012 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12013 ptype_mapping[i].sw_ptype |=
12014 RTE_PTYPE_INNER_L4_FRAG;
12015 } else if (!strncasecmp(name, "OIPV6", 5)) {
12016 ptype_mapping[i].sw_ptype |=
12017 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12019 } else if (!strncasecmp(name, "IPV6", 4) &&
12021 ptype_mapping[i].sw_ptype |=
12022 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12023 else if (!strncasecmp(name, "IPV6", 4) &&
12025 ptype_mapping[i].sw_ptype |=
12026 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12027 else if (!strncasecmp(name, "UDP", 3) &&
12029 ptype_mapping[i].sw_ptype |=
12031 else if (!strncasecmp(name, "UDP", 3) &&
12033 ptype_mapping[i].sw_ptype |=
12034 RTE_PTYPE_INNER_L4_UDP;
12035 else if (!strncasecmp(name, "TCP", 3) &&
12037 ptype_mapping[i].sw_ptype |=
12039 else if (!strncasecmp(name, "TCP", 3) &&
12041 ptype_mapping[i].sw_ptype |=
12042 RTE_PTYPE_INNER_L4_TCP;
12043 else if (!strncasecmp(name, "SCTP", 4) &&
12045 ptype_mapping[i].sw_ptype |=
12047 else if (!strncasecmp(name, "SCTP", 4) &&
12049 ptype_mapping[i].sw_ptype |=
12050 RTE_PTYPE_INNER_L4_SCTP;
12051 else if ((!strncasecmp(name, "ICMP", 4) ||
12052 !strncasecmp(name, "ICMPV6", 6)) &&
12054 ptype_mapping[i].sw_ptype |=
12056 else if ((!strncasecmp(name, "ICMP", 4) ||
12057 !strncasecmp(name, "ICMPV6", 6)) &&
12059 ptype_mapping[i].sw_ptype |=
12060 RTE_PTYPE_INNER_L4_ICMP;
12061 else if (!strncasecmp(name, "GTPC", 4)) {
12062 ptype_mapping[i].sw_ptype |=
12063 RTE_PTYPE_TUNNEL_GTPC;
12065 } else if (!strncasecmp(name, "GTPU", 4)) {
12066 ptype_mapping[i].sw_ptype |=
12067 RTE_PTYPE_TUNNEL_GTPU;
12069 } else if (!strncasecmp(name, "GRENAT", 6)) {
12070 ptype_mapping[i].sw_ptype |=
12071 RTE_PTYPE_TUNNEL_GRENAT;
12073 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
12074 ptype_mapping[i].sw_ptype |=
12075 RTE_PTYPE_TUNNEL_L2TP;
12084 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12087 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12089 rte_free(ptype_mapping);
12095 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12096 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12098 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12099 uint32_t proto_num;
12100 struct rte_pmd_i40e_proto_info *proto;
12101 uint32_t buff_size;
12105 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12106 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12107 PMD_DRV_LOG(ERR, "Unsupported operation.");
12111 /* get information about protocol number */
12112 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12113 (uint8_t *)&proto_num, sizeof(proto_num),
12114 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12116 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12120 PMD_DRV_LOG(INFO, "No new protocol added");
12124 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12125 proto = rte_zmalloc("new_proto", buff_size, 0);
12127 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12131 /* get information about protocol list */
12132 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12133 (uint8_t *)proto, buff_size,
12134 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12136 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12141 /* Check if GTP is supported. */
12142 for (i = 0; i < proto_num; i++) {
12143 if (!strncmp(proto[i].name, "GTP", 3)) {
12144 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12145 pf->gtp_support = true;
12147 pf->gtp_support = false;
12152 /* Update customized pctype info */
12153 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12154 proto_num, proto, op);
12156 PMD_DRV_LOG(INFO, "No pctype is updated.");
12158 /* Update customized ptype info */
12159 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12160 proto_num, proto, op);
12162 PMD_DRV_LOG(INFO, "No ptype is updated.");
12167 /* Create a QinQ cloud filter
12169 * The Fortville NIC has limited resources for tunnel filters,
12170 * so we can only reuse existing filters.
12172 * In step 1 we define which Field Vector fields can be used for
12174 * As we do not have the inner tag defined as a field,
12175 * we have to define it first, by reusing one of L1 entries.
12177 * In step 2 we are replacing one of existing filter types with
12178 * a new one for QinQ.
12179 * As we reusing L1 and replacing L2, some of the default filter
12180 * types will disappear,which depends on L1 and L2 entries we reuse.
12182 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12184 * 1. Create L1 filter of outer vlan (12b) which will be in use
12185 * later when we define the cloud filter.
12186 * a. Valid_flags.replace_cloud = 0
12187 * b. Old_filter = 10 (Stag_Inner_Vlan)
12188 * c. New_filter = 0x10
12189 * d. TR bit = 0xff (optional, not used here)
12190 * e. Buffer – 2 entries:
12191 * i. Byte 0 = 8 (outer vlan FV index).
12193 * Byte 2-3 = 0x0fff
12194 * ii. Byte 0 = 37 (inner vlan FV index).
12196 * Byte 2-3 = 0x0fff
12199 * 2. Create cloud filter using two L1 filters entries: stag and
12200 * new filter(outer vlan+ inner vlan)
12201 * a. Valid_flags.replace_cloud = 1
12202 * b. Old_filter = 1 (instead of outer IP)
12203 * c. New_filter = 0x10
12204 * d. Buffer – 2 entries:
12205 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12206 * Byte 1-3 = 0 (rsv)
12207 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12208 * Byte 9-11 = 0 (rsv)
12211 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12213 int ret = -ENOTSUP;
12214 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12215 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12216 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12218 if (pf->support_multi_driver) {
12219 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12224 memset(&filter_replace, 0,
12225 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12226 memset(&filter_replace_buf, 0,
12227 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12229 /* create L1 filter */
12230 filter_replace.old_filter_type =
12231 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12232 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12233 filter_replace.tr_bit = 0;
12235 /* Prepare the buffer, 2 entries */
12236 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12237 filter_replace_buf.data[0] |=
12238 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12239 /* Field Vector 12b mask */
12240 filter_replace_buf.data[2] = 0xff;
12241 filter_replace_buf.data[3] = 0x0f;
12242 filter_replace_buf.data[4] =
12243 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12244 filter_replace_buf.data[4] |=
12245 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12246 /* Field Vector 12b mask */
12247 filter_replace_buf.data[6] = 0xff;
12248 filter_replace_buf.data[7] = 0x0f;
12249 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12250 &filter_replace_buf);
12251 if (ret != I40E_SUCCESS)
12253 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12254 "cloud l1 type is changed from 0x%x to 0x%x",
12255 filter_replace.old_filter_type,
12256 filter_replace.new_filter_type);
12258 /* Apply the second L2 cloud filter */
12259 memset(&filter_replace, 0,
12260 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12261 memset(&filter_replace_buf, 0,
12262 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12264 /* create L2 filter, input for L2 filter will be L1 filter */
12265 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12266 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12267 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12269 /* Prepare the buffer, 2 entries */
12270 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12271 filter_replace_buf.data[0] |=
12272 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12273 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12274 filter_replace_buf.data[4] |=
12275 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12276 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12277 &filter_replace_buf);
12279 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
12280 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12281 "cloud filter type is changed from 0x%x to 0x%x",
12282 filter_replace.old_filter_type,
12283 filter_replace.new_filter_type);
12289 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12290 const struct rte_flow_action_rss *in)
12292 if (in->key_len > RTE_DIM(out->key) ||
12293 in->queue_num > RTE_DIM(out->queue))
12295 out->conf = (struct rte_flow_action_rss){
12297 .level = in->level,
12298 .types = in->types,
12299 .key_len = in->key_len,
12300 .queue_num = in->queue_num,
12301 .key = memcpy(out->key, in->key, in->key_len),
12302 .queue = memcpy(out->queue, in->queue,
12303 sizeof(*in->queue) * in->queue_num),
12309 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12310 const struct rte_flow_action_rss *with)
12312 return (comp->func == with->func &&
12313 comp->level == with->level &&
12314 comp->types == with->types &&
12315 comp->key_len == with->key_len &&
12316 comp->queue_num == with->queue_num &&
12317 !memcmp(comp->key, with->key, with->key_len) &&
12318 !memcmp(comp->queue, with->queue,
12319 sizeof(*with->queue) * with->queue_num));
12323 i40e_config_rss_filter(struct i40e_pf *pf,
12324 struct i40e_rte_flow_rss_conf *conf, bool add)
12326 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12327 uint32_t i, lut = 0;
12329 struct rte_eth_rss_conf rss_conf = {
12330 .rss_key = conf->conf.key_len ?
12331 (void *)(uintptr_t)conf->conf.key : NULL,
12332 .rss_key_len = conf->conf.key_len,
12333 .rss_hf = conf->conf.types,
12335 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12338 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12339 i40e_pf_disable_rss(pf);
12340 memset(rss_info, 0,
12341 sizeof(struct i40e_rte_flow_rss_conf));
12347 if (rss_info->conf.queue_num)
12350 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12351 * It's necessary to calculate the actual PF queues that are configured.
12353 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12354 num = i40e_pf_calc_configured_queues_num(pf);
12356 num = pf->dev_data->nb_rx_queues;
12358 num = RTE_MIN(num, conf->conf.queue_num);
12359 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12363 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12367 /* Fill in redirection table */
12368 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12371 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12372 hw->func_caps.rss_table_entry_width) - 1));
12374 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12377 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12378 i40e_pf_disable_rss(pf);
12381 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12382 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12383 /* Random default keys */
12384 static uint32_t rss_key_default[] = {0x6b793944,
12385 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12386 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12387 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12389 rss_conf.rss_key = (uint8_t *)rss_key_default;
12390 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12394 i40e_hw_rss_hash_set(pf, &rss_conf);
12396 if (i40e_rss_conf_init(rss_info, &conf->conf))
12402 RTE_INIT(i40e_init_log);
12404 i40e_init_log(void)
12406 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12407 if (i40e_logtype_init >= 0)
12408 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12409 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12410 if (i40e_logtype_driver >= 0)
12411 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12414 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12415 QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12416 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");