1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define I40E_CLEAR_PXE_WAIT_MS 200
50 /* Maximun number of capability elements */
51 #define I40E_MAX_CAP_ELE_NUM 128
53 /* Wait count and interval */
54 #define I40E_CHK_Q_ENA_COUNT 1000
55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
57 /* Maximun number of VSI */
58 #define I40E_MAX_NUM_VSIS (384UL)
60 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
62 /* Flow control default timer */
63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
65 /* Flow control enable fwd bit */
66 #define I40E_PRTMAC_FWD_CTRL 0x00000001
68 /* Receive Packet Buffer size */
69 #define I40E_RXPBSIZE (968 * 1024)
72 #define I40E_KILOSHIFT 10
74 /* Flow control default high water */
75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
77 /* Flow control default low water */
78 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
80 /* Receive Average Packet Size in Byte*/
81 #define I40E_PACKET_AVERAGE_SIZE 128
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
91 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
92 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
93 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
95 #define I40E_FLOW_TYPES ( \
96 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
101 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
106 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
108 /* Additional timesync values. */
109 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
110 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
111 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
112 #define I40E_PRTTSYN_TSYNENA 0x80000000
113 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
114 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
117 * Below are values for writing un-exposed registers suggested
120 /* Destination MAC address */
121 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
122 /* Source MAC address */
123 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
127 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
128 /* Single VLAN tag in the inner L2 header */
129 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
130 /* Source IPv4 address */
131 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
132 /* Destination IPv4 address */
133 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
134 /* Source IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
136 /* Destination IPv4 address for X722 */
137 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
138 /* IPv4 Protocol for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
140 /* IPv4 Time to Live for X722 */
141 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
142 /* IPv4 Type of Service (TOS) */
143 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
145 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
146 /* IPv4 Time to Live */
147 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
148 /* Source IPv6 address */
149 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
150 /* Destination IPv6 address */
151 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
152 /* IPv6 Traffic Class (TC) */
153 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
154 /* IPv6 Next Header */
155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
159 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
160 /* Destination L4 port */
161 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
162 /* SCTP verification tag */
163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
166 /* Source port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
168 /* Destination port of tunneling UDP */
169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
170 /* UDP Tunneling ID, NVGRE/GRE key */
171 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
172 /* Last ether type */
173 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
174 /* Tunneling outer destination IPv4 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
176 /* Tunneling outer destination IPv6 address */
177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
178 /* 1st word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
180 /* 2nd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
182 /* 3rd word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
184 /* 4th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
186 /* 5th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
188 /* 6th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
190 /* 7th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
192 /* 8th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
194 /* all 8 words flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
196 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
198 #define I40E_TRANSLATE_INSET 0
199 #define I40E_TRANSLATE_REG 1
201 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
202 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
203 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
204 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
206 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
208 /* PCI offset for querying capability */
209 #define PCI_DEV_CAP_REG 0xA4
210 /* PCI offset for enabling/disabling Extended Tag */
211 #define PCI_DEV_CTRL_REG 0xA8
212 /* Bit mask of Extended Tag capability */
213 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
214 /* Bit shift of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
216 /* Bit mask of Extended Tag enable/disable */
217 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
221 static int i40e_dev_configure(struct rte_eth_dev *dev);
222 static int i40e_dev_start(struct rte_eth_dev *dev);
223 static void i40e_dev_stop(struct rte_eth_dev *dev);
224 static void i40e_dev_close(struct rte_eth_dev *dev);
225 static int i40e_dev_reset(struct rte_eth_dev *dev);
226 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
233 struct rte_eth_stats *stats);
234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
235 struct rte_eth_xstat *xstats, unsigned n);
236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
237 struct rte_eth_xstat_name *xstats_names,
239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
240 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
245 char *fw_version, size_t fw_size);
246 static void i40e_dev_info_get(struct rte_eth_dev *dev,
247 struct rte_eth_dev_info *dev_info);
248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
252 enum rte_vlan_type vlan_type,
254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_fc_conf *fc_conf);
265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
266 struct rte_eth_pfc_conf *pfc_conf);
267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
268 struct rte_ether_addr *mac_addr,
271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
276 struct rte_eth_rss_reta_entry64 *reta_conf,
279 static int i40e_get_cap(struct i40e_hw *hw);
280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
281 static int i40e_pf_setup(struct i40e_pf *pf);
282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
286 bool offset_loaded, uint64_t *offset, uint64_t *stat);
287 static void i40e_stat_update_48(struct i40e_hw *hw,
293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
294 static void i40e_dev_interrupt_handler(void *param);
295 static void i40e_dev_alarm_handler(void *param);
296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
297 uint32_t base, uint32_t num);
298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
304 static int i40e_veb_release(struct i40e_veb *veb);
305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
306 struct i40e_vsi *vsi);
307 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
308 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
309 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
310 struct i40e_macvlan_filter *mv_f,
313 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
314 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
315 struct rte_eth_rss_conf *rss_conf);
316 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
317 struct rte_eth_rss_conf *rss_conf);
318 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
319 struct rte_eth_udp_tunnel *udp_tunnel);
320 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
321 struct rte_eth_udp_tunnel *udp_tunnel);
322 static void i40e_filter_input_set_init(struct i40e_pf *pf);
323 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
324 enum rte_filter_op filter_op,
326 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
327 enum rte_filter_type filter_type,
328 enum rte_filter_op filter_op,
330 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
331 struct rte_eth_dcb_info *dcb_info);
332 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
333 static void i40e_configure_registers(struct i40e_hw *hw);
334 static void i40e_hw_init(struct rte_eth_dev *dev);
335 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
336 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
342 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
343 struct rte_eth_mirror_conf *mirror_conf,
344 uint8_t sw_id, uint8_t on);
345 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
347 static int i40e_timesync_enable(struct rte_eth_dev *dev);
348 static int i40e_timesync_disable(struct rte_eth_dev *dev);
349 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp,
352 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
353 struct timespec *timestamp);
354 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
356 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
358 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
359 struct timespec *timestamp);
360 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
361 const struct timespec *timestamp);
363 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
365 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
368 static int i40e_get_regs(struct rte_eth_dev *dev,
369 struct rte_dev_reg_info *regs);
371 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
373 static int i40e_get_eeprom(struct rte_eth_dev *dev,
374 struct rte_dev_eeprom_info *eeprom);
376 static int i40e_get_module_info(struct rte_eth_dev *dev,
377 struct rte_eth_dev_module_info *modinfo);
378 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
379 struct rte_dev_eeprom_info *info);
381 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
382 struct rte_ether_addr *mac_addr);
384 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
386 static int i40e_ethertype_filter_convert(
387 const struct rte_eth_ethertype_filter *input,
388 struct i40e_ethertype_filter *filter);
389 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
390 struct i40e_ethertype_filter *filter);
392 static int i40e_tunnel_filter_convert(
393 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
394 struct i40e_tunnel_filter *tunnel_filter);
395 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
396 struct i40e_tunnel_filter *tunnel_filter);
397 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
399 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
400 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
401 static void i40e_filter_restore(struct i40e_pf *pf);
402 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
404 int i40e_logtype_init;
405 int i40e_logtype_driver;
407 static const char *const valid_keys[] = {
408 ETH_I40E_FLOATING_VEB_ARG,
409 ETH_I40E_FLOATING_VEB_LIST_ARG,
410 ETH_I40E_SUPPORT_MULTI_DRIVER,
411 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
412 ETH_I40E_USE_LATEST_VEC,
415 static const struct rte_pci_id pci_id_i40e_map[] = {
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
439 { .vendor_id = 0, /* sentinel */ },
442 static const struct eth_dev_ops i40e_eth_dev_ops = {
443 .dev_configure = i40e_dev_configure,
444 .dev_start = i40e_dev_start,
445 .dev_stop = i40e_dev_stop,
446 .dev_close = i40e_dev_close,
447 .dev_reset = i40e_dev_reset,
448 .promiscuous_enable = i40e_dev_promiscuous_enable,
449 .promiscuous_disable = i40e_dev_promiscuous_disable,
450 .allmulticast_enable = i40e_dev_allmulticast_enable,
451 .allmulticast_disable = i40e_dev_allmulticast_disable,
452 .dev_set_link_up = i40e_dev_set_link_up,
453 .dev_set_link_down = i40e_dev_set_link_down,
454 .link_update = i40e_dev_link_update,
455 .stats_get = i40e_dev_stats_get,
456 .xstats_get = i40e_dev_xstats_get,
457 .xstats_get_names = i40e_dev_xstats_get_names,
458 .stats_reset = i40e_dev_stats_reset,
459 .xstats_reset = i40e_dev_stats_reset,
460 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
461 .fw_version_get = i40e_fw_version_get,
462 .dev_infos_get = i40e_dev_info_get,
463 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
464 .vlan_filter_set = i40e_vlan_filter_set,
465 .vlan_tpid_set = i40e_vlan_tpid_set,
466 .vlan_offload_set = i40e_vlan_offload_set,
467 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
468 .vlan_pvid_set = i40e_vlan_pvid_set,
469 .rx_queue_start = i40e_dev_rx_queue_start,
470 .rx_queue_stop = i40e_dev_rx_queue_stop,
471 .tx_queue_start = i40e_dev_tx_queue_start,
472 .tx_queue_stop = i40e_dev_tx_queue_stop,
473 .rx_queue_setup = i40e_dev_rx_queue_setup,
474 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
475 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
476 .rx_queue_release = i40e_dev_rx_queue_release,
477 .rx_queue_count = i40e_dev_rx_queue_count,
478 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
479 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
480 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
481 .tx_queue_setup = i40e_dev_tx_queue_setup,
482 .tx_queue_release = i40e_dev_tx_queue_release,
483 .dev_led_on = i40e_dev_led_on,
484 .dev_led_off = i40e_dev_led_off,
485 .flow_ctrl_get = i40e_flow_ctrl_get,
486 .flow_ctrl_set = i40e_flow_ctrl_set,
487 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
488 .mac_addr_add = i40e_macaddr_add,
489 .mac_addr_remove = i40e_macaddr_remove,
490 .reta_update = i40e_dev_rss_reta_update,
491 .reta_query = i40e_dev_rss_reta_query,
492 .rss_hash_update = i40e_dev_rss_hash_update,
493 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
494 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
495 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
496 .filter_ctrl = i40e_dev_filter_ctrl,
497 .rxq_info_get = i40e_rxq_info_get,
498 .txq_info_get = i40e_txq_info_get,
499 .mirror_rule_set = i40e_mirror_rule_set,
500 .mirror_rule_reset = i40e_mirror_rule_reset,
501 .timesync_enable = i40e_timesync_enable,
502 .timesync_disable = i40e_timesync_disable,
503 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
504 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
505 .get_dcb_info = i40e_dev_get_dcb_info,
506 .timesync_adjust_time = i40e_timesync_adjust_time,
507 .timesync_read_time = i40e_timesync_read_time,
508 .timesync_write_time = i40e_timesync_write_time,
509 .get_reg = i40e_get_regs,
510 .get_eeprom_length = i40e_get_eeprom_length,
511 .get_eeprom = i40e_get_eeprom,
512 .get_module_info = i40e_get_module_info,
513 .get_module_eeprom = i40e_get_module_eeprom,
514 .mac_addr_set = i40e_set_default_mac_addr,
515 .mtu_set = i40e_dev_mtu_set,
516 .tm_ops_get = i40e_tm_ops_get,
519 /* store statistics names and its offset in stats structure */
520 struct rte_i40e_xstats_name_off {
521 char name[RTE_ETH_XSTATS_NAME_SIZE];
525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
526 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
527 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
528 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
529 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
530 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
531 rx_unknown_protocol)},
532 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
533 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
534 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
535 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
539 sizeof(rte_i40e_stats_strings[0]))
541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
542 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
543 tx_dropped_link_down)},
544 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
545 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
547 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
548 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
550 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
552 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
554 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
555 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
556 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
557 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
558 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
559 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
575 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
576 mac_short_packet_dropped)},
577 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
580 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
581 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
593 {"rx_flow_director_atr_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
595 {"rx_flow_director_sb_match_packets",
596 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
597 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
601 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
603 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
608 sizeof(rte_i40e_hw_port_strings[0]))
610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
611 {"xon_packets", offsetof(struct i40e_hw_port_stats,
613 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
618 sizeof(rte_i40e_rxq_prio_strings[0]))
620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
621 {"xon_packets", offsetof(struct i40e_hw_port_stats,
623 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
625 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
626 priority_xon_2_xoff)},
629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
630 sizeof(rte_i40e_txq_prio_strings[0]))
633 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
634 struct rte_pci_device *pci_dev)
636 char name[RTE_ETH_NAME_MAX_LEN];
637 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
640 if (pci_dev->device.devargs) {
641 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
647 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
648 sizeof(struct i40e_adapter),
649 eth_dev_pci_specific_init, pci_dev,
650 eth_i40e_dev_init, NULL);
652 if (retval || eth_da.nb_representor_ports < 1)
655 /* probe VF representor ports */
656 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
657 pci_dev->device.name);
659 if (pf_ethdev == NULL)
662 for (i = 0; i < eth_da.nb_representor_ports; i++) {
663 struct i40e_vf_representor representor = {
664 .vf_id = eth_da.representor_ports[i],
665 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
666 pf_ethdev->data->dev_private)->switch_domain_id,
667 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
668 pf_ethdev->data->dev_private)
671 /* representor port net_bdf_port */
672 snprintf(name, sizeof(name), "net_%s_representor_%d",
673 pci_dev->device.name, eth_da.representor_ports[i]);
675 retval = rte_eth_dev_create(&pci_dev->device, name,
676 sizeof(struct i40e_vf_representor), NULL, NULL,
677 i40e_vf_representor_init, &representor);
680 PMD_DRV_LOG(ERR, "failed to create i40e vf "
681 "representor %s.", name);
687 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
689 struct rte_eth_dev *ethdev;
691 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
696 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
697 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
699 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
702 static struct rte_pci_driver rte_i40e_pmd = {
703 .id_table = pci_id_i40e_map,
704 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
705 RTE_PCI_DRV_IOVA_AS_VA,
706 .probe = eth_i40e_pci_probe,
707 .remove = eth_i40e_pci_remove,
711 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
714 uint32_t ori_reg_val;
715 struct rte_eth_dev *dev;
717 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
718 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
719 i40e_write_rx_ctl(hw, reg_addr, reg_val);
720 if (ori_reg_val != reg_val)
722 "i40e device %s changed global register [0x%08x]."
723 " original: 0x%08x, new: 0x%08x",
724 dev->device->name, reg_addr, ori_reg_val, reg_val);
727 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
728 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
729 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
731 #ifndef I40E_GLQF_ORT
732 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
734 #ifndef I40E_GLQF_PIT
735 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
737 #ifndef I40E_GLQF_L3_MAP
738 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
741 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
744 * Initialize registers for parsing packet type of QinQ
745 * This should be removed from code once proper
746 * configuration API is added to avoid configuration conflicts
747 * between ports of the same device.
749 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
750 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
753 static inline void i40e_config_automask(struct i40e_pf *pf)
755 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
758 /* INTENA flag is not auto-cleared for interrupt */
759 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
760 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
761 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
763 /* If support multi-driver, PF will use INT0. */
764 if (!pf->support_multi_driver)
765 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
767 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
770 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
773 * Add a ethertype filter to drop all flow control frames transmitted
777 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
779 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
780 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
781 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
782 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
785 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
786 I40E_FLOW_CONTROL_ETHERTYPE, flags,
787 pf->main_vsi_seid, 0,
791 "Failed to add filter to drop flow control frames from VSIs.");
795 floating_veb_list_handler(__rte_unused const char *key,
796 const char *floating_veb_value,
800 unsigned int count = 0;
803 bool *vf_floating_veb = opaque;
805 while (isblank(*floating_veb_value))
806 floating_veb_value++;
808 /* Reset floating VEB configuration for VFs */
809 for (idx = 0; idx < I40E_MAX_VF; idx++)
810 vf_floating_veb[idx] = false;
814 while (isblank(*floating_veb_value))
815 floating_veb_value++;
816 if (*floating_veb_value == '\0')
819 idx = strtoul(floating_veb_value, &end, 10);
820 if (errno || end == NULL)
822 while (isblank(*end))
826 } else if ((*end == ';') || (*end == '\0')) {
828 if (min == I40E_MAX_VF)
830 if (max >= I40E_MAX_VF)
831 max = I40E_MAX_VF - 1;
832 for (idx = min; idx <= max; idx++) {
833 vf_floating_veb[idx] = true;
840 floating_veb_value = end + 1;
841 } while (*end != '\0');
850 config_vf_floating_veb(struct rte_devargs *devargs,
851 uint16_t floating_veb,
852 bool *vf_floating_veb)
854 struct rte_kvargs *kvlist;
856 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
860 /* All the VFs attach to the floating VEB by default
861 * when the floating VEB is enabled.
863 for (i = 0; i < I40E_MAX_VF; i++)
864 vf_floating_veb[i] = true;
869 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
873 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
874 rte_kvargs_free(kvlist);
877 /* When the floating_veb_list parameter exists, all the VFs
878 * will attach to the legacy VEB firstly, then configure VFs
879 * to the floating VEB according to the floating_veb_list.
881 if (rte_kvargs_process(kvlist, floating_veb_list,
882 floating_veb_list_handler,
883 vf_floating_veb) < 0) {
884 rte_kvargs_free(kvlist);
887 rte_kvargs_free(kvlist);
891 i40e_check_floating_handler(__rte_unused const char *key,
893 __rte_unused void *opaque)
895 if (strcmp(value, "1"))
902 is_floating_veb_supported(struct rte_devargs *devargs)
904 struct rte_kvargs *kvlist;
905 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
910 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
914 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
915 rte_kvargs_free(kvlist);
918 /* Floating VEB is enabled when there's key-value:
919 * enable_floating_veb=1
921 if (rte_kvargs_process(kvlist, floating_veb_key,
922 i40e_check_floating_handler, NULL) < 0) {
923 rte_kvargs_free(kvlist);
926 rte_kvargs_free(kvlist);
932 config_floating_veb(struct rte_eth_dev *dev)
934 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
938 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
940 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
942 is_floating_veb_supported(pci_dev->device.devargs);
943 config_vf_floating_veb(pci_dev->device.devargs,
945 pf->floating_veb_list);
947 pf->floating_veb = false;
951 #define I40E_L2_TAGS_S_TAG_SHIFT 1
952 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
955 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
958 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
959 char ethertype_hash_name[RTE_HASH_NAMESIZE];
962 struct rte_hash_parameters ethertype_hash_params = {
963 .name = ethertype_hash_name,
964 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
965 .key_len = sizeof(struct i40e_ethertype_filter_input),
966 .hash_func = rte_hash_crc,
967 .hash_func_init_val = 0,
968 .socket_id = rte_socket_id(),
971 /* Initialize ethertype filter rule list and hash */
972 TAILQ_INIT(ðertype_rule->ethertype_list);
973 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
974 "ethertype_%s", dev->device->name);
975 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
976 if (!ethertype_rule->hash_table) {
977 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
980 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
981 sizeof(struct i40e_ethertype_filter *) *
982 I40E_MAX_ETHERTYPE_FILTER_NUM,
984 if (!ethertype_rule->hash_map) {
986 "Failed to allocate memory for ethertype hash map!");
988 goto err_ethertype_hash_map_alloc;
993 err_ethertype_hash_map_alloc:
994 rte_hash_free(ethertype_rule->hash_table);
1000 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1002 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1004 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1007 struct rte_hash_parameters tunnel_hash_params = {
1008 .name = tunnel_hash_name,
1009 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1010 .key_len = sizeof(struct i40e_tunnel_filter_input),
1011 .hash_func = rte_hash_crc,
1012 .hash_func_init_val = 0,
1013 .socket_id = rte_socket_id(),
1016 /* Initialize tunnel filter rule list and hash */
1017 TAILQ_INIT(&tunnel_rule->tunnel_list);
1018 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1019 "tunnel_%s", dev->device->name);
1020 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1021 if (!tunnel_rule->hash_table) {
1022 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1025 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1026 sizeof(struct i40e_tunnel_filter *) *
1027 I40E_MAX_TUNNEL_FILTER_NUM,
1029 if (!tunnel_rule->hash_map) {
1031 "Failed to allocate memory for tunnel hash map!");
1033 goto err_tunnel_hash_map_alloc;
1038 err_tunnel_hash_map_alloc:
1039 rte_hash_free(tunnel_rule->hash_table);
1045 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1047 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048 struct i40e_fdir_info *fdir_info = &pf->fdir;
1049 char fdir_hash_name[RTE_HASH_NAMESIZE];
1052 struct rte_hash_parameters fdir_hash_params = {
1053 .name = fdir_hash_name,
1054 .entries = I40E_MAX_FDIR_FILTER_NUM,
1055 .key_len = sizeof(struct i40e_fdir_input),
1056 .hash_func = rte_hash_crc,
1057 .hash_func_init_val = 0,
1058 .socket_id = rte_socket_id(),
1061 /* Initialize flow director filter rule list and hash */
1062 TAILQ_INIT(&fdir_info->fdir_list);
1063 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1064 "fdir_%s", dev->device->name);
1065 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1066 if (!fdir_info->hash_table) {
1067 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1070 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1071 sizeof(struct i40e_fdir_filter *) *
1072 I40E_MAX_FDIR_FILTER_NUM,
1074 if (!fdir_info->hash_map) {
1076 "Failed to allocate memory for fdir hash map!");
1078 goto err_fdir_hash_map_alloc;
1082 err_fdir_hash_map_alloc:
1083 rte_hash_free(fdir_info->hash_table);
1089 i40e_init_customized_info(struct i40e_pf *pf)
1093 /* Initialize customized pctype */
1094 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1095 pf->customized_pctype[i].index = i;
1096 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1097 pf->customized_pctype[i].valid = false;
1100 pf->gtp_support = false;
1104 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1106 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1107 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1108 struct i40e_queue_regions *info = &pf->queue_region;
1111 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1112 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1114 memset(info, 0, sizeof(struct i40e_queue_regions));
1118 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1123 unsigned long support_multi_driver;
1126 pf = (struct i40e_pf *)opaque;
1129 support_multi_driver = strtoul(value, &end, 10);
1130 if (errno != 0 || end == value || *end != 0) {
1131 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1135 if (support_multi_driver == 1 || support_multi_driver == 0)
1136 pf->support_multi_driver = (bool)support_multi_driver;
1138 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1139 "enable global configuration by default."
1140 ETH_I40E_SUPPORT_MULTI_DRIVER);
1145 i40e_support_multi_driver(struct rte_eth_dev *dev)
1147 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1148 struct rte_kvargs *kvlist;
1151 /* Enable global configuration by default */
1152 pf->support_multi_driver = false;
1154 if (!dev->device->devargs)
1157 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1161 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1162 if (!kvargs_count) {
1163 rte_kvargs_free(kvlist);
1167 if (kvargs_count > 1)
1168 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1169 "the first invalid or last valid one is used !",
1170 ETH_I40E_SUPPORT_MULTI_DRIVER);
1172 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1173 i40e_parse_multi_drv_handler, pf) < 0) {
1174 rte_kvargs_free(kvlist);
1178 rte_kvargs_free(kvlist);
1183 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1184 uint32_t reg_addr, uint64_t reg_val,
1185 struct i40e_asq_cmd_details *cmd_details)
1187 uint64_t ori_reg_val;
1188 struct rte_eth_dev *dev;
1191 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1192 if (ret != I40E_SUCCESS) {
1194 "Fail to debug read from 0x%08x",
1198 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1200 if (ori_reg_val != reg_val)
1201 PMD_DRV_LOG(WARNING,
1202 "i40e device %s changed global register [0x%08x]."
1203 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1204 dev->device->name, reg_addr, ori_reg_val, reg_val);
1206 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1210 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1214 struct i40e_adapter *ad;
1217 ad = (struct i40e_adapter *)opaque;
1219 use_latest_vec = atoi(value);
1221 if (use_latest_vec != 0 && use_latest_vec != 1)
1222 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1224 ad->use_latest_vec = (uint8_t)use_latest_vec;
1230 i40e_use_latest_vec(struct rte_eth_dev *dev)
1232 struct i40e_adapter *ad =
1233 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1234 struct rte_kvargs *kvlist;
1237 ad->use_latest_vec = false;
1239 if (!dev->device->devargs)
1242 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1246 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1247 if (!kvargs_count) {
1248 rte_kvargs_free(kvlist);
1252 if (kvargs_count > 1)
1253 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1254 "the first invalid or last valid one is used !",
1255 ETH_I40E_USE_LATEST_VEC);
1257 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1258 i40e_parse_latest_vec_handler, ad) < 0) {
1259 rte_kvargs_free(kvlist);
1263 rte_kvargs_free(kvlist);
1267 #define I40E_ALARM_INTERVAL 50000 /* us */
1270 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1272 struct rte_pci_device *pci_dev;
1273 struct rte_intr_handle *intr_handle;
1274 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1275 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276 struct i40e_vsi *vsi;
1279 uint8_t aq_fail = 0;
1281 PMD_INIT_FUNC_TRACE();
1283 dev->dev_ops = &i40e_eth_dev_ops;
1284 dev->rx_pkt_burst = i40e_recv_pkts;
1285 dev->tx_pkt_burst = i40e_xmit_pkts;
1286 dev->tx_pkt_prepare = i40e_prep_pkts;
1288 /* for secondary processes, we don't initialise any further as primary
1289 * has already done this work. Only check we don't need a different
1291 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1292 i40e_set_rx_function(dev);
1293 i40e_set_tx_function(dev);
1296 i40e_set_default_ptype_table(dev);
1297 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1298 intr_handle = &pci_dev->intr_handle;
1300 rte_eth_copy_pci_info(dev, pci_dev);
1302 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1303 pf->adapter->eth_dev = dev;
1304 pf->dev_data = dev->data;
1306 hw->back = I40E_PF_TO_ADAPTER(pf);
1307 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1310 "Hardware is not available, as address is NULL");
1314 hw->vendor_id = pci_dev->id.vendor_id;
1315 hw->device_id = pci_dev->id.device_id;
1316 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1317 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1318 hw->bus.device = pci_dev->addr.devid;
1319 hw->bus.func = pci_dev->addr.function;
1320 hw->adapter_stopped = 0;
1321 hw->adapter_closed = 0;
1324 * Switch Tag value should not be identical to either the First Tag
1325 * or Second Tag values. So set something other than common Ethertype
1326 * for internal switching.
1328 hw->switch_tag = 0xffff;
1330 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1331 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1332 PMD_INIT_LOG(ERR, "\nERROR: "
1333 "Firmware recovery mode detected. Limiting functionality.\n"
1334 "Refer to the Intel(R) Ethernet Adapters and Devices "
1335 "User Guide for details on firmware recovery mode.");
1339 /* Check if need to support multi-driver */
1340 i40e_support_multi_driver(dev);
1341 /* Check if users want the latest supported vec path */
1342 i40e_use_latest_vec(dev);
1344 /* Make sure all is clean before doing PF reset */
1347 /* Reset here to make sure all is clean for each PF */
1348 ret = i40e_pf_reset(hw);
1350 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1354 /* Initialize the shared code (base driver) */
1355 ret = i40e_init_shared_code(hw);
1357 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1361 /* Initialize the parameters for adminq */
1362 i40e_init_adminq_parameter(hw);
1363 ret = i40e_init_adminq(hw);
1364 if (ret != I40E_SUCCESS) {
1365 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1368 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1369 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1370 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1371 ((hw->nvm.version >> 12) & 0xf),
1372 ((hw->nvm.version >> 4) & 0xff),
1373 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1375 /* Initialize the hardware */
1378 i40e_config_automask(pf);
1380 i40e_set_default_pctype_table(dev);
1383 * To work around the NVM issue, initialize registers
1384 * for packet type of QinQ by software.
1385 * It should be removed once issues are fixed in NVM.
1387 if (!pf->support_multi_driver)
1388 i40e_GLQF_reg_init(hw);
1390 /* Initialize the input set for filters (hash and fd) to default value */
1391 i40e_filter_input_set_init(pf);
1393 /* initialise the L3_MAP register */
1394 if (!pf->support_multi_driver) {
1395 ret = i40e_aq_debug_write_global_register(hw,
1396 I40E_GLQF_L3_MAP(40),
1399 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1402 "Global register 0x%08x is changed with 0x28",
1403 I40E_GLQF_L3_MAP(40));
1406 /* Need the special FW version to support floating VEB */
1407 config_floating_veb(dev);
1408 /* Clear PXE mode */
1409 i40e_clear_pxe_mode(hw);
1410 i40e_dev_sync_phy_type(hw);
1413 * On X710, performance number is far from the expectation on recent
1414 * firmware versions. The fix for this issue may not be integrated in
1415 * the following firmware version. So the workaround in software driver
1416 * is needed. It needs to modify the initial values of 3 internal only
1417 * registers. Note that the workaround can be removed when it is fixed
1418 * in firmware in the future.
1420 i40e_configure_registers(hw);
1422 /* Get hw capabilities */
1423 ret = i40e_get_cap(hw);
1424 if (ret != I40E_SUCCESS) {
1425 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1426 goto err_get_capabilities;
1429 /* Initialize parameters for PF */
1430 ret = i40e_pf_parameter_init(dev);
1432 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1433 goto err_parameter_init;
1436 /* Initialize the queue management */
1437 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1439 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1440 goto err_qp_pool_init;
1442 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1443 hw->func_caps.num_msix_vectors - 1);
1445 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1446 goto err_msix_pool_init;
1449 /* Initialize lan hmc */
1450 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1451 hw->func_caps.num_rx_qp, 0, 0);
1452 if (ret != I40E_SUCCESS) {
1453 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1454 goto err_init_lan_hmc;
1457 /* Configure lan hmc */
1458 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1459 if (ret != I40E_SUCCESS) {
1460 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1461 goto err_configure_lan_hmc;
1464 /* Get and check the mac address */
1465 i40e_get_mac_addr(hw, hw->mac.addr);
1466 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1467 PMD_INIT_LOG(ERR, "mac address is not valid");
1469 goto err_get_mac_addr;
1471 /* Copy the permanent MAC address */
1472 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1473 (struct rte_ether_addr *)hw->mac.perm_addr);
1475 /* Disable flow control */
1476 hw->fc.requested_mode = I40E_FC_NONE;
1477 i40e_set_fc(hw, &aq_fail, TRUE);
1479 /* Set the global registers with default ether type value */
1480 if (!pf->support_multi_driver) {
1481 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1482 RTE_ETHER_TYPE_VLAN);
1483 if (ret != I40E_SUCCESS) {
1485 "Failed to set the default outer "
1487 goto err_setup_pf_switch;
1491 /* PF setup, which includes VSI setup */
1492 ret = i40e_pf_setup(pf);
1494 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1495 goto err_setup_pf_switch;
1500 /* Disable double vlan by default */
1501 i40e_vsi_config_double_vlan(vsi, FALSE);
1503 /* Disable S-TAG identification when floating_veb is disabled */
1504 if (!pf->floating_veb) {
1505 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1506 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1507 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1508 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1512 if (!vsi->max_macaddrs)
1513 len = RTE_ETHER_ADDR_LEN;
1515 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1517 /* Should be after VSI initialized */
1518 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1519 if (!dev->data->mac_addrs) {
1521 "Failed to allocated memory for storing mac address");
1524 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1525 &dev->data->mac_addrs[0]);
1527 /* Init dcb to sw mode by default */
1528 ret = i40e_dcb_init_configure(dev, TRUE);
1529 if (ret != I40E_SUCCESS) {
1530 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1531 pf->flags &= ~I40E_FLAG_DCB;
1533 /* Update HW struct after DCB configuration */
1536 /* initialize pf host driver to setup SRIOV resource if applicable */
1537 i40e_pf_host_init(dev);
1539 /* register callback func to eal lib */
1540 rte_intr_callback_register(intr_handle,
1541 i40e_dev_interrupt_handler, dev);
1543 /* configure and enable device interrupt */
1544 i40e_pf_config_irq0(hw, TRUE);
1545 i40e_pf_enable_irq0(hw);
1547 /* enable uio intr after callback register */
1548 rte_intr_enable(intr_handle);
1550 /* By default disable flexible payload in global configuration */
1551 if (!pf->support_multi_driver)
1552 i40e_flex_payload_reg_set_default(hw);
1555 * Add an ethertype filter to drop all flow control frames transmitted
1556 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1559 i40e_add_tx_flow_control_drop_filter(pf);
1561 /* Set the max frame size to 0x2600 by default,
1562 * in case other drivers changed the default value.
1564 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1566 /* initialize mirror rule list */
1567 TAILQ_INIT(&pf->mirror_list);
1569 /* initialize Traffic Manager configuration */
1570 i40e_tm_conf_init(dev);
1572 /* Initialize customized information */
1573 i40e_init_customized_info(pf);
1575 ret = i40e_init_ethtype_filter_list(dev);
1577 goto err_init_ethtype_filter_list;
1578 ret = i40e_init_tunnel_filter_list(dev);
1580 goto err_init_tunnel_filter_list;
1581 ret = i40e_init_fdir_filter_list(dev);
1583 goto err_init_fdir_filter_list;
1585 /* initialize queue region configuration */
1586 i40e_init_queue_region_conf(dev);
1588 /* initialize rss configuration from rte_flow */
1589 memset(&pf->rss_info, 0,
1590 sizeof(struct i40e_rte_flow_rss_conf));
1592 /* reset all stats of the device, including pf and main vsi */
1593 i40e_dev_stats_reset(dev);
1597 err_init_fdir_filter_list:
1598 rte_free(pf->tunnel.hash_table);
1599 rte_free(pf->tunnel.hash_map);
1600 err_init_tunnel_filter_list:
1601 rte_free(pf->ethertype.hash_table);
1602 rte_free(pf->ethertype.hash_map);
1603 err_init_ethtype_filter_list:
1604 rte_free(dev->data->mac_addrs);
1606 i40e_vsi_release(pf->main_vsi);
1607 err_setup_pf_switch:
1609 err_configure_lan_hmc:
1610 (void)i40e_shutdown_lan_hmc(hw);
1612 i40e_res_pool_destroy(&pf->msix_pool);
1614 i40e_res_pool_destroy(&pf->qp_pool);
1617 err_get_capabilities:
1618 (void)i40e_shutdown_adminq(hw);
1624 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1626 struct i40e_ethertype_filter *p_ethertype;
1627 struct i40e_ethertype_rule *ethertype_rule;
1629 ethertype_rule = &pf->ethertype;
1630 /* Remove all ethertype filter rules and hash */
1631 if (ethertype_rule->hash_map)
1632 rte_free(ethertype_rule->hash_map);
1633 if (ethertype_rule->hash_table)
1634 rte_hash_free(ethertype_rule->hash_table);
1636 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1637 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1638 p_ethertype, rules);
1639 rte_free(p_ethertype);
1644 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1646 struct i40e_tunnel_filter *p_tunnel;
1647 struct i40e_tunnel_rule *tunnel_rule;
1649 tunnel_rule = &pf->tunnel;
1650 /* Remove all tunnel director rules and hash */
1651 if (tunnel_rule->hash_map)
1652 rte_free(tunnel_rule->hash_map);
1653 if (tunnel_rule->hash_table)
1654 rte_hash_free(tunnel_rule->hash_table);
1656 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1657 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1663 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1665 struct i40e_fdir_filter *p_fdir;
1666 struct i40e_fdir_info *fdir_info;
1668 fdir_info = &pf->fdir;
1669 /* Remove all flow director rules and hash */
1670 if (fdir_info->hash_map)
1671 rte_free(fdir_info->hash_map);
1672 if (fdir_info->hash_table)
1673 rte_hash_free(fdir_info->hash_table);
1675 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1676 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1681 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1684 * Disable by default flexible payload
1685 * for corresponding L2/L3/L4 layers.
1687 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1688 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1689 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1693 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1696 struct rte_pci_device *pci_dev;
1697 struct rte_intr_handle *intr_handle;
1699 struct i40e_filter_control_settings settings;
1700 struct rte_flow *p_flow;
1702 uint8_t aq_fail = 0;
1705 PMD_INIT_FUNC_TRACE();
1707 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1710 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1711 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1713 intr_handle = &pci_dev->intr_handle;
1715 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1717 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1719 if (hw->adapter_closed == 0)
1720 i40e_dev_close(dev);
1722 dev->dev_ops = NULL;
1723 dev->rx_pkt_burst = NULL;
1724 dev->tx_pkt_burst = NULL;
1726 /* Clear PXE mode */
1727 i40e_clear_pxe_mode(hw);
1729 /* Unconfigure filter control */
1730 memset(&settings, 0, sizeof(settings));
1731 ret = i40e_set_filter_control(hw, &settings);
1733 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1736 /* Disable flow control */
1737 hw->fc.requested_mode = I40E_FC_NONE;
1738 i40e_set_fc(hw, &aq_fail, TRUE);
1740 /* uninitialize pf host driver */
1741 i40e_pf_host_uninit(dev);
1743 /* disable uio intr before callback unregister */
1744 rte_intr_disable(intr_handle);
1746 /* unregister callback func to eal lib */
1748 ret = rte_intr_callback_unregister(intr_handle,
1749 i40e_dev_interrupt_handler, dev);
1752 } else if (ret != -EAGAIN) {
1754 "intr callback unregister failed: %d",
1758 i40e_msec_delay(500);
1759 } while (retries++ < 5);
1761 i40e_rm_ethtype_filter_list(pf);
1762 i40e_rm_tunnel_filter_list(pf);
1763 i40e_rm_fdir_filter_list(pf);
1765 /* Remove all flows */
1766 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1767 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1771 /* Remove all Traffic Manager configuration */
1772 i40e_tm_conf_uninit(dev);
1778 i40e_dev_configure(struct rte_eth_dev *dev)
1780 struct i40e_adapter *ad =
1781 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1782 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1787 ret = i40e_dev_sync_phy_type(hw);
1791 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1792 * bulk allocation or vector Rx preconditions we will reset it.
1794 ad->rx_bulk_alloc_allowed = true;
1795 ad->rx_vec_allowed = true;
1796 ad->tx_simple_allowed = true;
1797 ad->tx_vec_allowed = true;
1799 /* Only legacy filter API needs the following fdir config. So when the
1800 * legacy filter API is deprecated, the following codes should also be
1803 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1804 ret = i40e_fdir_setup(pf);
1805 if (ret != I40E_SUCCESS) {
1806 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1809 ret = i40e_fdir_configure(dev);
1811 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1815 i40e_fdir_teardown(pf);
1817 ret = i40e_dev_init_vlan(dev);
1822 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1823 * RSS setting have different requirements.
1824 * General PMD driver call sequence are NIC init, configure,
1825 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1826 * will try to lookup the VSI that specific queue belongs to if VMDQ
1827 * applicable. So, VMDQ setting has to be done before
1828 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1829 * For RSS setting, it will try to calculate actual configured RX queue
1830 * number, which will be available after rx_queue_setup(). dev_start()
1831 * function is good to place RSS setup.
1833 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1834 ret = i40e_vmdq_setup(dev);
1839 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1840 ret = i40e_dcb_setup(dev);
1842 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1847 TAILQ_INIT(&pf->flow_list);
1852 /* need to release vmdq resource if exists */
1853 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1854 i40e_vsi_release(pf->vmdq[i].vsi);
1855 pf->vmdq[i].vsi = NULL;
1860 /* Need to release fdir resource if exists.
1861 * Only legacy filter API needs the following fdir config. So when the
1862 * legacy filter API is deprecated, the following code should also be
1865 i40e_fdir_teardown(pf);
1870 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1872 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1873 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1874 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1875 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1876 uint16_t msix_vect = vsi->msix_intr;
1879 for (i = 0; i < vsi->nb_qps; i++) {
1880 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1881 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1885 if (vsi->type != I40E_VSI_SRIOV) {
1886 if (!rte_intr_allow_others(intr_handle)) {
1887 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1888 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1890 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1893 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1894 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1896 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1901 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1902 vsi->user_param + (msix_vect - 1);
1904 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1905 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1907 I40E_WRITE_FLUSH(hw);
1911 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1912 int base_queue, int nb_queue,
1917 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1918 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1920 /* Bind all RX queues to allocated MSIX interrupt */
1921 for (i = 0; i < nb_queue; i++) {
1922 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1923 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1924 ((base_queue + i + 1) <<
1925 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1926 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1927 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1929 if (i == nb_queue - 1)
1930 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1931 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1934 /* Write first RX queue to Link list register as the head element */
1935 if (vsi->type != I40E_VSI_SRIOV) {
1937 i40e_calc_itr_interval(1, pf->support_multi_driver);
1939 if (msix_vect == I40E_MISC_VEC_ID) {
1940 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1942 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1944 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1946 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1949 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1951 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1953 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1955 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1962 if (msix_vect == I40E_MISC_VEC_ID) {
1964 I40E_VPINT_LNKLST0(vsi->user_param),
1966 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1968 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1970 /* num_msix_vectors_vf needs to minus irq0 */
1971 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1972 vsi->user_param + (msix_vect - 1);
1974 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1976 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1978 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1982 I40E_WRITE_FLUSH(hw);
1986 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1988 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1989 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1990 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1991 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1992 uint16_t msix_vect = vsi->msix_intr;
1993 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1994 uint16_t queue_idx = 0;
1998 for (i = 0; i < vsi->nb_qps; i++) {
1999 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2000 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2003 /* VF bind interrupt */
2004 if (vsi->type == I40E_VSI_SRIOV) {
2005 __vsi_queues_bind_intr(vsi, msix_vect,
2006 vsi->base_queue, vsi->nb_qps,
2011 /* PF & VMDq bind interrupt */
2012 if (rte_intr_dp_is_en(intr_handle)) {
2013 if (vsi->type == I40E_VSI_MAIN) {
2016 } else if (vsi->type == I40E_VSI_VMDQ2) {
2017 struct i40e_vsi *main_vsi =
2018 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2019 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2024 for (i = 0; i < vsi->nb_used_qps; i++) {
2026 if (!rte_intr_allow_others(intr_handle))
2027 /* allow to share MISC_VEC_ID */
2028 msix_vect = I40E_MISC_VEC_ID;
2030 /* no enough msix_vect, map all to one */
2031 __vsi_queues_bind_intr(vsi, msix_vect,
2032 vsi->base_queue + i,
2033 vsi->nb_used_qps - i,
2035 for (; !!record && i < vsi->nb_used_qps; i++)
2036 intr_handle->intr_vec[queue_idx + i] =
2040 /* 1:1 queue/msix_vect mapping */
2041 __vsi_queues_bind_intr(vsi, msix_vect,
2042 vsi->base_queue + i, 1,
2045 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2053 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2055 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2056 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2059 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2060 uint16_t msix_intr, i;
2062 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2063 for (i = 0; i < vsi->nb_msix; i++) {
2064 msix_intr = vsi->msix_intr + i;
2065 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2066 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2067 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2068 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2071 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2072 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2073 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2074 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2076 I40E_WRITE_FLUSH(hw);
2080 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2082 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2083 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2084 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2085 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2086 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2087 uint16_t msix_intr, i;
2089 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2090 for (i = 0; i < vsi->nb_msix; i++) {
2091 msix_intr = vsi->msix_intr + i;
2092 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2093 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2096 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2097 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2099 I40E_WRITE_FLUSH(hw);
2102 static inline uint8_t
2103 i40e_parse_link_speeds(uint16_t link_speeds)
2105 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2107 if (link_speeds & ETH_LINK_SPEED_40G)
2108 link_speed |= I40E_LINK_SPEED_40GB;
2109 if (link_speeds & ETH_LINK_SPEED_25G)
2110 link_speed |= I40E_LINK_SPEED_25GB;
2111 if (link_speeds & ETH_LINK_SPEED_20G)
2112 link_speed |= I40E_LINK_SPEED_20GB;
2113 if (link_speeds & ETH_LINK_SPEED_10G)
2114 link_speed |= I40E_LINK_SPEED_10GB;
2115 if (link_speeds & ETH_LINK_SPEED_1G)
2116 link_speed |= I40E_LINK_SPEED_1GB;
2117 if (link_speeds & ETH_LINK_SPEED_100M)
2118 link_speed |= I40E_LINK_SPEED_100MB;
2124 i40e_phy_conf_link(struct i40e_hw *hw,
2126 uint8_t force_speed,
2129 enum i40e_status_code status;
2130 struct i40e_aq_get_phy_abilities_resp phy_ab;
2131 struct i40e_aq_set_phy_config phy_conf;
2132 enum i40e_aq_phy_type cnt;
2133 uint8_t avail_speed;
2134 uint32_t phy_type_mask = 0;
2136 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2137 I40E_AQ_PHY_FLAG_PAUSE_RX |
2138 I40E_AQ_PHY_FLAG_PAUSE_RX |
2139 I40E_AQ_PHY_FLAG_LOW_POWER;
2142 /* To get phy capabilities of available speeds. */
2143 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2146 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2150 avail_speed = phy_ab.link_speed;
2152 /* To get the current phy config. */
2153 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2156 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2161 /* If link needs to go up and it is in autoneg mode the speed is OK,
2162 * no need to set up again.
2164 if (is_up && phy_ab.phy_type != 0 &&
2165 abilities & I40E_AQ_PHY_AN_ENABLED &&
2166 phy_ab.link_speed != 0)
2167 return I40E_SUCCESS;
2169 memset(&phy_conf, 0, sizeof(phy_conf));
2171 /* bits 0-2 use the values from get_phy_abilities_resp */
2173 abilities |= phy_ab.abilities & mask;
2175 phy_conf.abilities = abilities;
2177 /* If link needs to go up, but the force speed is not supported,
2178 * Warn users and config the default available speeds.
2180 if (is_up && !(force_speed & avail_speed)) {
2181 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2182 phy_conf.link_speed = avail_speed;
2184 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2187 /* PHY type mask needs to include each type except PHY type extension */
2188 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2189 phy_type_mask |= 1 << cnt;
2191 /* use get_phy_abilities_resp value for the rest */
2192 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2193 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2194 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2195 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2196 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2197 phy_conf.eee_capability = phy_ab.eee_capability;
2198 phy_conf.eeer = phy_ab.eeer_val;
2199 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2201 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2202 phy_ab.abilities, phy_ab.link_speed);
2203 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2204 phy_conf.abilities, phy_conf.link_speed);
2206 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2210 return I40E_SUCCESS;
2214 i40e_apply_link_speed(struct rte_eth_dev *dev)
2217 uint8_t abilities = 0;
2218 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219 struct rte_eth_conf *conf = &dev->data->dev_conf;
2221 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2222 conf->link_speeds = ETH_LINK_SPEED_40G |
2223 ETH_LINK_SPEED_25G |
2224 ETH_LINK_SPEED_20G |
2225 ETH_LINK_SPEED_10G |
2227 ETH_LINK_SPEED_100M;
2229 speed = i40e_parse_link_speeds(conf->link_speeds);
2230 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2231 I40E_AQ_PHY_AN_ENABLED |
2232 I40E_AQ_PHY_LINK_ENABLED;
2234 return i40e_phy_conf_link(hw, abilities, speed, true);
2238 i40e_dev_start(struct rte_eth_dev *dev)
2240 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2241 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242 struct i40e_vsi *main_vsi = pf->main_vsi;
2244 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2245 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2246 uint32_t intr_vector = 0;
2247 struct i40e_vsi *vsi;
2249 hw->adapter_stopped = 0;
2251 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2253 "Invalid link_speeds for port %u, autonegotiation disabled",
2254 dev->data->port_id);
2258 rte_intr_disable(intr_handle);
2260 if ((rte_intr_cap_multiple(intr_handle) ||
2261 !RTE_ETH_DEV_SRIOV(dev).active) &&
2262 dev->data->dev_conf.intr_conf.rxq != 0) {
2263 intr_vector = dev->data->nb_rx_queues;
2264 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2269 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2270 intr_handle->intr_vec =
2271 rte_zmalloc("intr_vec",
2272 dev->data->nb_rx_queues * sizeof(int),
2274 if (!intr_handle->intr_vec) {
2276 "Failed to allocate %d rx_queues intr_vec",
2277 dev->data->nb_rx_queues);
2282 /* Initialize VSI */
2283 ret = i40e_dev_rxtx_init(pf);
2284 if (ret != I40E_SUCCESS) {
2285 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2289 /* Map queues with MSIX interrupt */
2290 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2291 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2292 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2293 i40e_vsi_enable_queues_intr(main_vsi);
2295 /* Map VMDQ VSI queues with MSIX interrupt */
2296 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2297 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2298 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2299 I40E_ITR_INDEX_DEFAULT);
2300 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2303 /* enable FDIR MSIX interrupt */
2304 if (pf->fdir.fdir_vsi) {
2305 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2306 I40E_ITR_INDEX_NONE);
2307 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2310 /* Enable all queues which have been configured */
2311 ret = i40e_dev_switch_queues(pf, TRUE);
2312 if (ret != I40E_SUCCESS) {
2313 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2317 /* Enable receiving broadcast packets */
2318 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2319 if (ret != I40E_SUCCESS)
2320 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2322 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2323 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2325 if (ret != I40E_SUCCESS)
2326 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2329 /* Enable the VLAN promiscuous mode. */
2331 for (i = 0; i < pf->vf_num; i++) {
2332 vsi = pf->vfs[i].vsi;
2333 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2338 /* Enable mac loopback mode */
2339 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2340 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2341 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2342 if (ret != I40E_SUCCESS) {
2343 PMD_DRV_LOG(ERR, "fail to set loopback link");
2348 /* Apply link configure */
2349 ret = i40e_apply_link_speed(dev);
2350 if (I40E_SUCCESS != ret) {
2351 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2355 if (!rte_intr_allow_others(intr_handle)) {
2356 rte_intr_callback_unregister(intr_handle,
2357 i40e_dev_interrupt_handler,
2359 /* configure and enable device interrupt */
2360 i40e_pf_config_irq0(hw, FALSE);
2361 i40e_pf_enable_irq0(hw);
2363 if (dev->data->dev_conf.intr_conf.lsc != 0)
2365 "lsc won't enable because of no intr multiplex");
2367 ret = i40e_aq_set_phy_int_mask(hw,
2368 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2369 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2370 I40E_AQ_EVENT_MEDIA_NA), NULL);
2371 if (ret != I40E_SUCCESS)
2372 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2374 /* Call get_link_info aq commond to enable/disable LSE */
2375 i40e_dev_link_update(dev, 0);
2378 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2379 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2380 i40e_dev_alarm_handler, dev);
2382 /* enable uio intr after callback register */
2383 rte_intr_enable(intr_handle);
2386 i40e_filter_restore(pf);
2388 if (pf->tm_conf.root && !pf->tm_conf.committed)
2389 PMD_DRV_LOG(WARNING,
2390 "please call hierarchy_commit() "
2391 "before starting the port");
2393 return I40E_SUCCESS;
2396 i40e_dev_switch_queues(pf, FALSE);
2397 i40e_dev_clear_queues(dev);
2403 i40e_dev_stop(struct rte_eth_dev *dev)
2405 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2406 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407 struct i40e_vsi *main_vsi = pf->main_vsi;
2408 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2409 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2412 if (hw->adapter_stopped == 1)
2415 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2416 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2417 rte_intr_enable(intr_handle);
2420 /* Disable all queues */
2421 i40e_dev_switch_queues(pf, FALSE);
2423 /* un-map queues with interrupt registers */
2424 i40e_vsi_disable_queues_intr(main_vsi);
2425 i40e_vsi_queues_unbind_intr(main_vsi);
2427 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2428 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2429 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2432 if (pf->fdir.fdir_vsi) {
2433 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2434 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2436 /* Clear all queues and release memory */
2437 i40e_dev_clear_queues(dev);
2440 i40e_dev_set_link_down(dev);
2442 if (!rte_intr_allow_others(intr_handle))
2443 /* resume to the default handler */
2444 rte_intr_callback_register(intr_handle,
2445 i40e_dev_interrupt_handler,
2448 /* Clean datapath event and queue/vec mapping */
2449 rte_intr_efd_disable(intr_handle);
2450 if (intr_handle->intr_vec) {
2451 rte_free(intr_handle->intr_vec);
2452 intr_handle->intr_vec = NULL;
2455 /* reset hierarchy commit */
2456 pf->tm_conf.committed = false;
2458 hw->adapter_stopped = 1;
2460 pf->adapter->rss_reta_updated = 0;
2464 i40e_dev_close(struct rte_eth_dev *dev)
2466 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2467 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2469 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2470 struct i40e_mirror_rule *p_mirror;
2475 PMD_INIT_FUNC_TRACE();
2479 /* Remove all mirror rules */
2480 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2481 ret = i40e_aq_del_mirror_rule(hw,
2482 pf->main_vsi->veb->seid,
2483 p_mirror->rule_type,
2485 p_mirror->num_entries,
2488 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2489 "status = %d, aq_err = %d.", ret,
2490 hw->aq.asq_last_status);
2492 /* remove mirror software resource anyway */
2493 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2495 pf->nb_mirror_rule--;
2498 i40e_dev_free_queues(dev);
2500 /* Disable interrupt */
2501 i40e_pf_disable_irq0(hw);
2502 rte_intr_disable(intr_handle);
2505 * Only legacy filter API needs the following fdir config. So when the
2506 * legacy filter API is deprecated, the following code should also be
2509 i40e_fdir_teardown(pf);
2511 /* shutdown and destroy the HMC */
2512 i40e_shutdown_lan_hmc(hw);
2514 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2515 i40e_vsi_release(pf->vmdq[i].vsi);
2516 pf->vmdq[i].vsi = NULL;
2521 /* release all the existing VSIs and VEBs */
2522 i40e_vsi_release(pf->main_vsi);
2524 /* shutdown the adminq */
2525 i40e_aq_queue_shutdown(hw, true);
2526 i40e_shutdown_adminq(hw);
2528 i40e_res_pool_destroy(&pf->qp_pool);
2529 i40e_res_pool_destroy(&pf->msix_pool);
2531 /* Disable flexible payload in global configuration */
2532 if (!pf->support_multi_driver)
2533 i40e_flex_payload_reg_set_default(hw);
2535 /* force a PF reset to clean anything leftover */
2536 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2537 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2538 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2539 I40E_WRITE_FLUSH(hw);
2541 hw->adapter_closed = 1;
2545 * Reset PF device only to re-initialize resources in PMD layer
2548 i40e_dev_reset(struct rte_eth_dev *dev)
2552 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2553 * its VF to make them align with it. The detailed notification
2554 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2555 * To avoid unexpected behavior in VF, currently reset of PF with
2556 * SR-IOV activation is not supported. It might be supported later.
2558 if (dev->data->sriov.active)
2561 ret = eth_i40e_dev_uninit(dev);
2565 ret = eth_i40e_dev_init(dev, NULL);
2571 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2573 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2574 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575 struct i40e_vsi *vsi = pf->main_vsi;
2578 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2580 if (status != I40E_SUCCESS)
2581 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2583 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2585 if (status != I40E_SUCCESS)
2586 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2591 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2593 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2594 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2595 struct i40e_vsi *vsi = pf->main_vsi;
2598 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2600 if (status != I40E_SUCCESS)
2601 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2603 /* must remain in all_multicast mode */
2604 if (dev->data->all_multicast == 1)
2607 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2609 if (status != I40E_SUCCESS)
2610 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2614 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2616 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2617 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618 struct i40e_vsi *vsi = pf->main_vsi;
2621 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2622 if (ret != I40E_SUCCESS)
2623 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2627 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2629 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2630 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631 struct i40e_vsi *vsi = pf->main_vsi;
2634 if (dev->data->promiscuous == 1)
2635 return; /* must remain in all_multicast mode */
2637 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2638 vsi->seid, FALSE, NULL);
2639 if (ret != I40E_SUCCESS)
2640 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2644 * Set device link up.
2647 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2649 /* re-apply link speed setting */
2650 return i40e_apply_link_speed(dev);
2654 * Set device link down.
2657 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2659 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2660 uint8_t abilities = 0;
2661 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2663 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2664 return i40e_phy_conf_link(hw, abilities, speed, false);
2667 static __rte_always_inline void
2668 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2670 /* Link status registers and values*/
2671 #define I40E_PRTMAC_LINKSTA 0x001E2420
2672 #define I40E_REG_LINK_UP 0x40000080
2673 #define I40E_PRTMAC_MACC 0x001E24E0
2674 #define I40E_REG_MACC_25GB 0x00020000
2675 #define I40E_REG_SPEED_MASK 0x38000000
2676 #define I40E_REG_SPEED_0 0x00000000
2677 #define I40E_REG_SPEED_1 0x08000000
2678 #define I40E_REG_SPEED_2 0x10000000
2679 #define I40E_REG_SPEED_3 0x18000000
2680 #define I40E_REG_SPEED_4 0x20000000
2681 uint32_t link_speed;
2684 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2685 link_speed = reg_val & I40E_REG_SPEED_MASK;
2686 reg_val &= I40E_REG_LINK_UP;
2687 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2689 if (unlikely(link->link_status == 0))
2692 /* Parse the link status */
2693 switch (link_speed) {
2694 case I40E_REG_SPEED_0:
2695 link->link_speed = ETH_SPEED_NUM_100M;
2697 case I40E_REG_SPEED_1:
2698 link->link_speed = ETH_SPEED_NUM_1G;
2700 case I40E_REG_SPEED_2:
2701 if (hw->mac.type == I40E_MAC_X722)
2702 link->link_speed = ETH_SPEED_NUM_2_5G;
2704 link->link_speed = ETH_SPEED_NUM_10G;
2706 case I40E_REG_SPEED_3:
2707 if (hw->mac.type == I40E_MAC_X722) {
2708 link->link_speed = ETH_SPEED_NUM_5G;
2710 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2712 if (reg_val & I40E_REG_MACC_25GB)
2713 link->link_speed = ETH_SPEED_NUM_25G;
2715 link->link_speed = ETH_SPEED_NUM_40G;
2718 case I40E_REG_SPEED_4:
2719 if (hw->mac.type == I40E_MAC_X722)
2720 link->link_speed = ETH_SPEED_NUM_10G;
2722 link->link_speed = ETH_SPEED_NUM_20G;
2725 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2730 static __rte_always_inline void
2731 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2732 bool enable_lse, int wait_to_complete)
2734 #define CHECK_INTERVAL 100 /* 100ms */
2735 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2736 uint32_t rep_cnt = MAX_REPEAT_TIME;
2737 struct i40e_link_status link_status;
2740 memset(&link_status, 0, sizeof(link_status));
2743 memset(&link_status, 0, sizeof(link_status));
2745 /* Get link status information from hardware */
2746 status = i40e_aq_get_link_info(hw, enable_lse,
2747 &link_status, NULL);
2748 if (unlikely(status != I40E_SUCCESS)) {
2749 link->link_speed = ETH_SPEED_NUM_100M;
2750 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2751 PMD_DRV_LOG(ERR, "Failed to get link info");
2755 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2756 if (!wait_to_complete || link->link_status)
2759 rte_delay_ms(CHECK_INTERVAL);
2760 } while (--rep_cnt);
2762 /* Parse the link status */
2763 switch (link_status.link_speed) {
2764 case I40E_LINK_SPEED_100MB:
2765 link->link_speed = ETH_SPEED_NUM_100M;
2767 case I40E_LINK_SPEED_1GB:
2768 link->link_speed = ETH_SPEED_NUM_1G;
2770 case I40E_LINK_SPEED_10GB:
2771 link->link_speed = ETH_SPEED_NUM_10G;
2773 case I40E_LINK_SPEED_20GB:
2774 link->link_speed = ETH_SPEED_NUM_20G;
2776 case I40E_LINK_SPEED_25GB:
2777 link->link_speed = ETH_SPEED_NUM_25G;
2779 case I40E_LINK_SPEED_40GB:
2780 link->link_speed = ETH_SPEED_NUM_40G;
2783 link->link_speed = ETH_SPEED_NUM_100M;
2789 i40e_dev_link_update(struct rte_eth_dev *dev,
2790 int wait_to_complete)
2792 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793 struct rte_eth_link link;
2794 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2797 memset(&link, 0, sizeof(link));
2799 /* i40e uses full duplex only */
2800 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2801 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2802 ETH_LINK_SPEED_FIXED);
2804 if (!wait_to_complete && !enable_lse)
2805 update_link_reg(hw, &link);
2807 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2809 ret = rte_eth_linkstatus_set(dev, &link);
2810 i40e_notify_all_vfs_link_status(dev);
2815 /* Get all the statistics of a VSI */
2817 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2819 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2820 struct i40e_eth_stats *nes = &vsi->eth_stats;
2821 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2822 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2824 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2825 vsi->offset_loaded, &oes->rx_bytes,
2827 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2828 vsi->offset_loaded, &oes->rx_unicast,
2830 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2831 vsi->offset_loaded, &oes->rx_multicast,
2832 &nes->rx_multicast);
2833 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2834 vsi->offset_loaded, &oes->rx_broadcast,
2835 &nes->rx_broadcast);
2836 /* exclude CRC bytes */
2837 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2838 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2840 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2841 &oes->rx_discards, &nes->rx_discards);
2842 /* GLV_REPC not supported */
2843 /* GLV_RMPC not supported */
2844 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2845 &oes->rx_unknown_protocol,
2846 &nes->rx_unknown_protocol);
2847 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2848 vsi->offset_loaded, &oes->tx_bytes,
2850 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2851 vsi->offset_loaded, &oes->tx_unicast,
2853 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2854 vsi->offset_loaded, &oes->tx_multicast,
2855 &nes->tx_multicast);
2856 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2857 vsi->offset_loaded, &oes->tx_broadcast,
2858 &nes->tx_broadcast);
2859 /* GLV_TDPC not supported */
2860 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2861 &oes->tx_errors, &nes->tx_errors);
2862 vsi->offset_loaded = true;
2864 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2866 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2867 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2868 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2869 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2870 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2871 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2872 nes->rx_unknown_protocol);
2873 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2874 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2875 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2876 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2877 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2878 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2879 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2884 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2887 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2888 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2890 /* Get rx/tx bytes of internal transfer packets */
2891 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2892 I40E_GLV_GORCL(hw->port),
2894 &pf->internal_stats_offset.rx_bytes,
2895 &pf->internal_stats.rx_bytes);
2897 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2898 I40E_GLV_GOTCL(hw->port),
2900 &pf->internal_stats_offset.tx_bytes,
2901 &pf->internal_stats.tx_bytes);
2902 /* Get total internal rx packet count */
2903 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2904 I40E_GLV_UPRCL(hw->port),
2906 &pf->internal_stats_offset.rx_unicast,
2907 &pf->internal_stats.rx_unicast);
2908 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2909 I40E_GLV_MPRCL(hw->port),
2911 &pf->internal_stats_offset.rx_multicast,
2912 &pf->internal_stats.rx_multicast);
2913 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2914 I40E_GLV_BPRCL(hw->port),
2916 &pf->internal_stats_offset.rx_broadcast,
2917 &pf->internal_stats.rx_broadcast);
2918 /* Get total internal tx packet count */
2919 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2920 I40E_GLV_UPTCL(hw->port),
2922 &pf->internal_stats_offset.tx_unicast,
2923 &pf->internal_stats.tx_unicast);
2924 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2925 I40E_GLV_MPTCL(hw->port),
2927 &pf->internal_stats_offset.tx_multicast,
2928 &pf->internal_stats.tx_multicast);
2929 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2930 I40E_GLV_BPTCL(hw->port),
2932 &pf->internal_stats_offset.tx_broadcast,
2933 &pf->internal_stats.tx_broadcast);
2935 /* exclude CRC size */
2936 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2937 pf->internal_stats.rx_multicast +
2938 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
2940 /* Get statistics of struct i40e_eth_stats */
2941 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2942 I40E_GLPRT_GORCL(hw->port),
2943 pf->offset_loaded, &os->eth.rx_bytes,
2945 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2946 I40E_GLPRT_UPRCL(hw->port),
2947 pf->offset_loaded, &os->eth.rx_unicast,
2948 &ns->eth.rx_unicast);
2949 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2950 I40E_GLPRT_MPRCL(hw->port),
2951 pf->offset_loaded, &os->eth.rx_multicast,
2952 &ns->eth.rx_multicast);
2953 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2954 I40E_GLPRT_BPRCL(hw->port),
2955 pf->offset_loaded, &os->eth.rx_broadcast,
2956 &ns->eth.rx_broadcast);
2957 /* Workaround: CRC size should not be included in byte statistics,
2958 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
2961 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2962 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
2964 /* exclude internal rx bytes
2965 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2966 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2968 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2970 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2971 ns->eth.rx_bytes = 0;
2973 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2975 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2976 ns->eth.rx_unicast = 0;
2978 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2980 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2981 ns->eth.rx_multicast = 0;
2983 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2985 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2986 ns->eth.rx_broadcast = 0;
2988 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2990 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2991 pf->offset_loaded, &os->eth.rx_discards,
2992 &ns->eth.rx_discards);
2993 /* GLPRT_REPC not supported */
2994 /* GLPRT_RMPC not supported */
2995 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2997 &os->eth.rx_unknown_protocol,
2998 &ns->eth.rx_unknown_protocol);
2999 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3000 I40E_GLPRT_GOTCL(hw->port),
3001 pf->offset_loaded, &os->eth.tx_bytes,
3003 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3004 I40E_GLPRT_UPTCL(hw->port),
3005 pf->offset_loaded, &os->eth.tx_unicast,
3006 &ns->eth.tx_unicast);
3007 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3008 I40E_GLPRT_MPTCL(hw->port),
3009 pf->offset_loaded, &os->eth.tx_multicast,
3010 &ns->eth.tx_multicast);
3011 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3012 I40E_GLPRT_BPTCL(hw->port),
3013 pf->offset_loaded, &os->eth.tx_broadcast,
3014 &ns->eth.tx_broadcast);
3015 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3016 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3018 /* exclude internal tx bytes
3019 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3020 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3022 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3024 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3025 ns->eth.tx_bytes = 0;
3027 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3029 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3030 ns->eth.tx_unicast = 0;
3032 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3034 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3035 ns->eth.tx_multicast = 0;
3037 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3039 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3040 ns->eth.tx_broadcast = 0;
3042 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3044 /* GLPRT_TEPC not supported */
3046 /* additional port specific stats */
3047 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3048 pf->offset_loaded, &os->tx_dropped_link_down,
3049 &ns->tx_dropped_link_down);
3050 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3051 pf->offset_loaded, &os->crc_errors,
3053 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3054 pf->offset_loaded, &os->illegal_bytes,
3055 &ns->illegal_bytes);
3056 /* GLPRT_ERRBC not supported */
3057 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3058 pf->offset_loaded, &os->mac_local_faults,
3059 &ns->mac_local_faults);
3060 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3061 pf->offset_loaded, &os->mac_remote_faults,
3062 &ns->mac_remote_faults);
3063 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3064 pf->offset_loaded, &os->rx_length_errors,
3065 &ns->rx_length_errors);
3066 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3067 pf->offset_loaded, &os->link_xon_rx,
3069 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3070 pf->offset_loaded, &os->link_xoff_rx,
3072 for (i = 0; i < 8; i++) {
3073 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3075 &os->priority_xon_rx[i],
3076 &ns->priority_xon_rx[i]);
3077 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3079 &os->priority_xoff_rx[i],
3080 &ns->priority_xoff_rx[i]);
3082 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3083 pf->offset_loaded, &os->link_xon_tx,
3085 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3086 pf->offset_loaded, &os->link_xoff_tx,
3088 for (i = 0; i < 8; i++) {
3089 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3091 &os->priority_xon_tx[i],
3092 &ns->priority_xon_tx[i]);
3093 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3095 &os->priority_xoff_tx[i],
3096 &ns->priority_xoff_tx[i]);
3097 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3099 &os->priority_xon_2_xoff[i],
3100 &ns->priority_xon_2_xoff[i]);
3102 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3103 I40E_GLPRT_PRC64L(hw->port),
3104 pf->offset_loaded, &os->rx_size_64,
3106 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3107 I40E_GLPRT_PRC127L(hw->port),
3108 pf->offset_loaded, &os->rx_size_127,
3110 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3111 I40E_GLPRT_PRC255L(hw->port),
3112 pf->offset_loaded, &os->rx_size_255,
3114 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3115 I40E_GLPRT_PRC511L(hw->port),
3116 pf->offset_loaded, &os->rx_size_511,
3118 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3119 I40E_GLPRT_PRC1023L(hw->port),
3120 pf->offset_loaded, &os->rx_size_1023,
3122 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3123 I40E_GLPRT_PRC1522L(hw->port),
3124 pf->offset_loaded, &os->rx_size_1522,
3126 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3127 I40E_GLPRT_PRC9522L(hw->port),
3128 pf->offset_loaded, &os->rx_size_big,
3130 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3131 pf->offset_loaded, &os->rx_undersize,
3133 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3134 pf->offset_loaded, &os->rx_fragments,
3136 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3137 pf->offset_loaded, &os->rx_oversize,
3139 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3140 pf->offset_loaded, &os->rx_jabber,
3142 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3143 I40E_GLPRT_PTC64L(hw->port),
3144 pf->offset_loaded, &os->tx_size_64,
3146 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3147 I40E_GLPRT_PTC127L(hw->port),
3148 pf->offset_loaded, &os->tx_size_127,
3150 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3151 I40E_GLPRT_PTC255L(hw->port),
3152 pf->offset_loaded, &os->tx_size_255,
3154 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3155 I40E_GLPRT_PTC511L(hw->port),
3156 pf->offset_loaded, &os->tx_size_511,
3158 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3159 I40E_GLPRT_PTC1023L(hw->port),
3160 pf->offset_loaded, &os->tx_size_1023,
3162 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3163 I40E_GLPRT_PTC1522L(hw->port),
3164 pf->offset_loaded, &os->tx_size_1522,
3166 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3167 I40E_GLPRT_PTC9522L(hw->port),
3168 pf->offset_loaded, &os->tx_size_big,
3170 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3172 &os->fd_sb_match, &ns->fd_sb_match);
3173 /* GLPRT_MSPDC not supported */
3174 /* GLPRT_XEC not supported */
3176 pf->offset_loaded = true;
3179 i40e_update_vsi_stats(pf->main_vsi);
3182 /* Get all statistics of a port */
3184 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3186 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3187 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3188 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3189 struct i40e_vsi *vsi;
3192 /* call read registers - updates values, now write them to struct */
3193 i40e_read_stats_registers(pf, hw);
3195 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3196 pf->main_vsi->eth_stats.rx_multicast +
3197 pf->main_vsi->eth_stats.rx_broadcast -
3198 pf->main_vsi->eth_stats.rx_discards;
3199 stats->opackets = ns->eth.tx_unicast +
3200 ns->eth.tx_multicast +
3201 ns->eth.tx_broadcast;
3202 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3203 stats->obytes = ns->eth.tx_bytes;
3204 stats->oerrors = ns->eth.tx_errors +
3205 pf->main_vsi->eth_stats.tx_errors;
3208 stats->imissed = ns->eth.rx_discards +
3209 pf->main_vsi->eth_stats.rx_discards;
3210 stats->ierrors = ns->crc_errors +
3211 ns->rx_length_errors + ns->rx_undersize +
3212 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3215 for (i = 0; i < pf->vf_num; i++) {
3216 vsi = pf->vfs[i].vsi;
3217 i40e_update_vsi_stats(vsi);
3219 stats->ipackets += (vsi->eth_stats.rx_unicast +
3220 vsi->eth_stats.rx_multicast +
3221 vsi->eth_stats.rx_broadcast -
3222 vsi->eth_stats.rx_discards);
3223 stats->ibytes += vsi->eth_stats.rx_bytes;
3224 stats->oerrors += vsi->eth_stats.tx_errors;
3225 stats->imissed += vsi->eth_stats.rx_discards;
3229 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3230 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3231 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3232 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3233 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3234 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3235 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3236 ns->eth.rx_unknown_protocol);
3237 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3238 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3239 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3240 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3241 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3242 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3244 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3245 ns->tx_dropped_link_down);
3246 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3247 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3249 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3250 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3251 ns->mac_local_faults);
3252 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3253 ns->mac_remote_faults);
3254 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3255 ns->rx_length_errors);
3256 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3257 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3258 for (i = 0; i < 8; i++) {
3259 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3260 i, ns->priority_xon_rx[i]);
3261 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3262 i, ns->priority_xoff_rx[i]);
3264 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3265 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3266 for (i = 0; i < 8; i++) {
3267 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3268 i, ns->priority_xon_tx[i]);
3269 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3270 i, ns->priority_xoff_tx[i]);
3271 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3272 i, ns->priority_xon_2_xoff[i]);
3274 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3275 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3276 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3277 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3278 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3279 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3280 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3281 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3282 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3283 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3284 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3285 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3286 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3287 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3288 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3289 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3290 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3291 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3292 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3293 ns->mac_short_packet_dropped);
3294 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3295 ns->checksum_error);
3296 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3297 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3301 /* Reset the statistics */
3303 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3305 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3306 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3308 /* Mark PF and VSI stats to update the offset, aka "reset" */
3309 pf->offset_loaded = false;
3311 pf->main_vsi->offset_loaded = false;
3313 /* read the stats, reading current register values into offset */
3314 i40e_read_stats_registers(pf, hw);
3318 i40e_xstats_calc_num(void)
3320 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3321 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3322 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3325 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3326 struct rte_eth_xstat_name *xstats_names,
3327 __rte_unused unsigned limit)
3332 if (xstats_names == NULL)
3333 return i40e_xstats_calc_num();
3335 /* Note: limit checked in rte_eth_xstats_names() */
3337 /* Get stats from i40e_eth_stats struct */
3338 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3339 strlcpy(xstats_names[count].name,
3340 rte_i40e_stats_strings[i].name,
3341 sizeof(xstats_names[count].name));
3345 /* Get individiual stats from i40e_hw_port struct */
3346 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3347 strlcpy(xstats_names[count].name,
3348 rte_i40e_hw_port_strings[i].name,
3349 sizeof(xstats_names[count].name));
3353 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3354 for (prio = 0; prio < 8; prio++) {
3355 snprintf(xstats_names[count].name,
3356 sizeof(xstats_names[count].name),
3357 "rx_priority%u_%s", prio,
3358 rte_i40e_rxq_prio_strings[i].name);
3363 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3364 for (prio = 0; prio < 8; prio++) {
3365 snprintf(xstats_names[count].name,
3366 sizeof(xstats_names[count].name),
3367 "tx_priority%u_%s", prio,
3368 rte_i40e_txq_prio_strings[i].name);
3376 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3379 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3380 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3381 unsigned i, count, prio;
3382 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3384 count = i40e_xstats_calc_num();
3388 i40e_read_stats_registers(pf, hw);
3395 /* Get stats from i40e_eth_stats struct */
3396 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3397 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3398 rte_i40e_stats_strings[i].offset);
3399 xstats[count].id = count;
3403 /* Get individiual stats from i40e_hw_port struct */
3404 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3405 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3406 rte_i40e_hw_port_strings[i].offset);
3407 xstats[count].id = count;
3411 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3412 for (prio = 0; prio < 8; prio++) {
3413 xstats[count].value =
3414 *(uint64_t *)(((char *)hw_stats) +
3415 rte_i40e_rxq_prio_strings[i].offset +
3416 (sizeof(uint64_t) * prio));
3417 xstats[count].id = count;
3422 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3423 for (prio = 0; prio < 8; prio++) {
3424 xstats[count].value =
3425 *(uint64_t *)(((char *)hw_stats) +
3426 rte_i40e_txq_prio_strings[i].offset +
3427 (sizeof(uint64_t) * prio));
3428 xstats[count].id = count;
3437 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3438 __rte_unused uint16_t queue_id,
3439 __rte_unused uint8_t stat_idx,
3440 __rte_unused uint8_t is_rx)
3442 PMD_INIT_FUNC_TRACE();
3448 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3450 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3456 full_ver = hw->nvm.oem_ver;
3457 ver = (u8)(full_ver >> 24);
3458 build = (u16)((full_ver >> 8) & 0xffff);
3459 patch = (u8)(full_ver & 0xff);
3461 ret = snprintf(fw_version, fw_size,
3462 "%d.%d%d 0x%08x %d.%d.%d",
3463 ((hw->nvm.version >> 12) & 0xf),
3464 ((hw->nvm.version >> 4) & 0xff),
3465 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3468 ret += 1; /* add the size of '\0' */
3469 if (fw_size < (u32)ret)
3476 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3477 * the Rx data path does not hang if the FW LLDP is stopped.
3478 * return true if lldp need to stop
3479 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3482 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3485 char ver_str[64] = {0};
3486 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3488 i40e_fw_version_get(dev, ver_str, 64);
3489 nvm_ver = atof(ver_str);
3490 if ((hw->mac.type == I40E_MAC_X722 ||
3491 hw->mac.type == I40E_MAC_X722_VF) &&
3492 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3494 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3501 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3503 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3504 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3505 struct i40e_vsi *vsi = pf->main_vsi;
3506 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3508 dev_info->max_rx_queues = vsi->nb_qps;
3509 dev_info->max_tx_queues = vsi->nb_qps;
3510 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3511 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3512 dev_info->max_mac_addrs = vsi->max_macaddrs;
3513 dev_info->max_vfs = pci_dev->max_vfs;
3514 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3515 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3516 dev_info->rx_queue_offload_capa = 0;
3517 dev_info->rx_offload_capa =
3518 DEV_RX_OFFLOAD_VLAN_STRIP |
3519 DEV_RX_OFFLOAD_QINQ_STRIP |
3520 DEV_RX_OFFLOAD_IPV4_CKSUM |
3521 DEV_RX_OFFLOAD_UDP_CKSUM |
3522 DEV_RX_OFFLOAD_TCP_CKSUM |
3523 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3524 DEV_RX_OFFLOAD_KEEP_CRC |
3525 DEV_RX_OFFLOAD_SCATTER |
3526 DEV_RX_OFFLOAD_VLAN_EXTEND |
3527 DEV_RX_OFFLOAD_VLAN_FILTER |
3528 DEV_RX_OFFLOAD_JUMBO_FRAME;
3530 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3531 dev_info->tx_offload_capa =
3532 DEV_TX_OFFLOAD_VLAN_INSERT |
3533 DEV_TX_OFFLOAD_QINQ_INSERT |
3534 DEV_TX_OFFLOAD_IPV4_CKSUM |
3535 DEV_TX_OFFLOAD_UDP_CKSUM |
3536 DEV_TX_OFFLOAD_TCP_CKSUM |
3537 DEV_TX_OFFLOAD_SCTP_CKSUM |
3538 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3539 DEV_TX_OFFLOAD_TCP_TSO |
3540 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3541 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3542 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3543 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3544 DEV_TX_OFFLOAD_MULTI_SEGS |
3545 dev_info->tx_queue_offload_capa;
3546 dev_info->dev_capa =
3547 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3548 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3550 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3552 dev_info->reta_size = pf->hash_lut_size;
3553 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3555 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3557 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3558 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3559 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3561 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3566 dev_info->default_txconf = (struct rte_eth_txconf) {
3568 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3569 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3570 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3572 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3573 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3577 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3578 .nb_max = I40E_MAX_RING_DESC,
3579 .nb_min = I40E_MIN_RING_DESC,
3580 .nb_align = I40E_ALIGN_RING_DESC,
3583 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3584 .nb_max = I40E_MAX_RING_DESC,
3585 .nb_min = I40E_MIN_RING_DESC,
3586 .nb_align = I40E_ALIGN_RING_DESC,
3587 .nb_seg_max = I40E_TX_MAX_SEG,
3588 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3591 if (pf->flags & I40E_FLAG_VMDQ) {
3592 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3593 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3594 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3595 pf->max_nb_vmdq_vsi;
3596 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3597 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3598 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3601 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3603 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3604 dev_info->default_rxportconf.nb_queues = 2;
3605 dev_info->default_txportconf.nb_queues = 2;
3606 if (dev->data->nb_rx_queues == 1)
3607 dev_info->default_rxportconf.ring_size = 2048;
3609 dev_info->default_rxportconf.ring_size = 1024;
3610 if (dev->data->nb_tx_queues == 1)
3611 dev_info->default_txportconf.ring_size = 1024;
3613 dev_info->default_txportconf.ring_size = 512;
3615 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3617 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3618 dev_info->default_rxportconf.nb_queues = 1;
3619 dev_info->default_txportconf.nb_queues = 1;
3620 dev_info->default_rxportconf.ring_size = 256;
3621 dev_info->default_txportconf.ring_size = 256;
3624 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3625 dev_info->default_rxportconf.nb_queues = 1;
3626 dev_info->default_txportconf.nb_queues = 1;
3627 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3628 dev_info->default_rxportconf.ring_size = 512;
3629 dev_info->default_txportconf.ring_size = 256;
3631 dev_info->default_rxportconf.ring_size = 256;
3632 dev_info->default_txportconf.ring_size = 256;
3635 dev_info->default_rxportconf.burst_size = 32;
3636 dev_info->default_txportconf.burst_size = 32;
3640 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3642 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3643 struct i40e_vsi *vsi = pf->main_vsi;
3644 PMD_INIT_FUNC_TRACE();
3647 return i40e_vsi_add_vlan(vsi, vlan_id);
3649 return i40e_vsi_delete_vlan(vsi, vlan_id);
3653 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3654 enum rte_vlan_type vlan_type,
3655 uint16_t tpid, int qinq)
3657 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3660 uint16_t reg_id = 3;
3664 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3668 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3670 if (ret != I40E_SUCCESS) {
3672 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3677 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3680 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3681 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3682 if (reg_r == reg_w) {
3683 PMD_DRV_LOG(DEBUG, "No need to write");
3687 ret = i40e_aq_debug_write_global_register(hw,
3688 I40E_GL_SWT_L2TAGCTRL(reg_id),
3690 if (ret != I40E_SUCCESS) {
3692 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3697 "Global register 0x%08x is changed with value 0x%08x",
3698 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3704 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3705 enum rte_vlan_type vlan_type,
3708 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3710 int qinq = dev->data->dev_conf.rxmode.offloads &
3711 DEV_RX_OFFLOAD_VLAN_EXTEND;
3714 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3715 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3716 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3718 "Unsupported vlan type.");
3722 if (pf->support_multi_driver) {
3723 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3727 /* 802.1ad frames ability is added in NVM API 1.7*/
3728 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3730 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3731 hw->first_tag = rte_cpu_to_le_16(tpid);
3732 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3733 hw->second_tag = rte_cpu_to_le_16(tpid);
3735 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3736 hw->second_tag = rte_cpu_to_le_16(tpid);
3738 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3739 if (ret != I40E_SUCCESS) {
3741 "Set switch config failed aq_err: %d",
3742 hw->aq.asq_last_status);
3746 /* If NVM API < 1.7, keep the register setting */
3747 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3754 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3756 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3757 struct i40e_vsi *vsi = pf->main_vsi;
3758 struct rte_eth_rxmode *rxmode;
3760 rxmode = &dev->data->dev_conf.rxmode;
3761 if (mask & ETH_VLAN_FILTER_MASK) {
3762 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3763 i40e_vsi_config_vlan_filter(vsi, TRUE);
3765 i40e_vsi_config_vlan_filter(vsi, FALSE);
3768 if (mask & ETH_VLAN_STRIP_MASK) {
3769 /* Enable or disable VLAN stripping */
3770 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3771 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3773 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3776 if (mask & ETH_VLAN_EXTEND_MASK) {
3777 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3778 i40e_vsi_config_double_vlan(vsi, TRUE);
3779 /* Set global registers with default ethertype. */
3780 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3781 RTE_ETHER_TYPE_VLAN);
3782 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3783 RTE_ETHER_TYPE_VLAN);
3786 i40e_vsi_config_double_vlan(vsi, FALSE);
3793 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3794 __rte_unused uint16_t queue,
3795 __rte_unused int on)
3797 PMD_INIT_FUNC_TRACE();
3801 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3803 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3804 struct i40e_vsi *vsi = pf->main_vsi;
3805 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3806 struct i40e_vsi_vlan_pvid_info info;
3808 memset(&info, 0, sizeof(info));
3811 info.config.pvid = pvid;
3813 info.config.reject.tagged =
3814 data->dev_conf.txmode.hw_vlan_reject_tagged;
3815 info.config.reject.untagged =
3816 data->dev_conf.txmode.hw_vlan_reject_untagged;
3819 return i40e_vsi_vlan_pvid_set(vsi, &info);
3823 i40e_dev_led_on(struct rte_eth_dev *dev)
3825 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3826 uint32_t mode = i40e_led_get(hw);
3829 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3835 i40e_dev_led_off(struct rte_eth_dev *dev)
3837 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3838 uint32_t mode = i40e_led_get(hw);
3841 i40e_led_set(hw, 0, false);
3847 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3849 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3850 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3852 fc_conf->pause_time = pf->fc_conf.pause_time;
3854 /* read out from register, in case they are modified by other port */
3855 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3856 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3857 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3858 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3860 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3861 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3863 /* Return current mode according to actual setting*/
3864 switch (hw->fc.current_mode) {
3866 fc_conf->mode = RTE_FC_FULL;
3868 case I40E_FC_TX_PAUSE:
3869 fc_conf->mode = RTE_FC_TX_PAUSE;
3871 case I40E_FC_RX_PAUSE:
3872 fc_conf->mode = RTE_FC_RX_PAUSE;
3876 fc_conf->mode = RTE_FC_NONE;
3883 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3885 uint32_t mflcn_reg, fctrl_reg, reg;
3886 uint32_t max_high_water;
3887 uint8_t i, aq_failure;
3891 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3892 [RTE_FC_NONE] = I40E_FC_NONE,
3893 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3894 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3895 [RTE_FC_FULL] = I40E_FC_FULL
3898 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3900 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3901 if ((fc_conf->high_water > max_high_water) ||
3902 (fc_conf->high_water < fc_conf->low_water)) {
3904 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3909 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3910 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3911 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3913 pf->fc_conf.pause_time = fc_conf->pause_time;
3914 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3915 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3917 PMD_INIT_FUNC_TRACE();
3919 /* All the link flow control related enable/disable register
3920 * configuration is handle by the F/W
3922 err = i40e_set_fc(hw, &aq_failure, true);
3926 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3927 /* Configure flow control refresh threshold,
3928 * the value for stat_tx_pause_refresh_timer[8]
3929 * is used for global pause operation.
3933 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3934 pf->fc_conf.pause_time);
3936 /* configure the timer value included in transmitted pause
3938 * the value for stat_tx_pause_quanta[8] is used for global
3941 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3942 pf->fc_conf.pause_time);
3944 fctrl_reg = I40E_READ_REG(hw,
3945 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3947 if (fc_conf->mac_ctrl_frame_fwd != 0)
3948 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3950 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3952 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3955 /* Configure pause time (2 TCs per register) */
3956 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3957 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3958 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3960 /* Configure flow control refresh threshold value */
3961 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3962 pf->fc_conf.pause_time / 2);
3964 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3966 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3967 *depending on configuration
3969 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3970 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3971 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3973 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3974 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3977 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3980 if (!pf->support_multi_driver) {
3981 /* config water marker both based on the packets and bytes */
3982 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3983 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3984 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3985 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3986 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3987 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3988 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3989 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3991 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3992 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3996 "Water marker configuration is not supported.");
3999 I40E_WRITE_FLUSH(hw);
4005 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4006 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4008 PMD_INIT_FUNC_TRACE();
4013 /* Add a MAC address, and update filters */
4015 i40e_macaddr_add(struct rte_eth_dev *dev,
4016 struct rte_ether_addr *mac_addr,
4017 __rte_unused uint32_t index,
4020 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4021 struct i40e_mac_filter_info mac_filter;
4022 struct i40e_vsi *vsi;
4023 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4026 /* If VMDQ not enabled or configured, return */
4027 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4028 !pf->nb_cfg_vmdq_vsi)) {
4029 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4030 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4035 if (pool > pf->nb_cfg_vmdq_vsi) {
4036 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4037 pool, pf->nb_cfg_vmdq_vsi);
4041 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4042 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4043 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4045 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4050 vsi = pf->vmdq[pool - 1].vsi;
4052 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4053 if (ret != I40E_SUCCESS) {
4054 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4060 /* Remove a MAC address, and update filters */
4062 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4064 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4065 struct i40e_vsi *vsi;
4066 struct rte_eth_dev_data *data = dev->data;
4067 struct rte_ether_addr *macaddr;
4072 macaddr = &(data->mac_addrs[index]);
4074 pool_sel = dev->data->mac_pool_sel[index];
4076 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4077 if (pool_sel & (1ULL << i)) {
4081 /* No VMDQ pool enabled or configured */
4082 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4083 (i > pf->nb_cfg_vmdq_vsi)) {
4085 "No VMDQ pool enabled/configured");
4088 vsi = pf->vmdq[i - 1].vsi;
4090 ret = i40e_vsi_delete_mac(vsi, macaddr);
4093 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4100 /* Set perfect match or hash match of MAC and VLAN for a VF */
4102 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4103 struct rte_eth_mac_filter *filter,
4107 struct i40e_mac_filter_info mac_filter;
4108 struct rte_ether_addr old_mac;
4109 struct rte_ether_addr *new_mac;
4110 struct i40e_pf_vf *vf = NULL;
4115 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4118 hw = I40E_PF_TO_HW(pf);
4120 if (filter == NULL) {
4121 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4125 new_mac = &filter->mac_addr;
4127 if (rte_is_zero_ether_addr(new_mac)) {
4128 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4132 vf_id = filter->dst_id;
4134 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4135 PMD_DRV_LOG(ERR, "Invalid argument.");
4138 vf = &pf->vfs[vf_id];
4140 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4141 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4146 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4147 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4148 RTE_ETHER_ADDR_LEN);
4149 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4150 RTE_ETHER_ADDR_LEN);
4152 mac_filter.filter_type = filter->filter_type;
4153 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4154 if (ret != I40E_SUCCESS) {
4155 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4158 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4160 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4161 RTE_ETHER_ADDR_LEN);
4162 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4163 if (ret != I40E_SUCCESS) {
4164 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4168 /* Clear device address as it has been removed */
4169 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4170 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4176 /* MAC filter handle */
4178 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4181 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4182 struct rte_eth_mac_filter *filter;
4183 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4184 int ret = I40E_NOT_SUPPORTED;
4186 filter = (struct rte_eth_mac_filter *)(arg);
4188 switch (filter_op) {
4189 case RTE_ETH_FILTER_NOP:
4192 case RTE_ETH_FILTER_ADD:
4193 i40e_pf_disable_irq0(hw);
4195 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4196 i40e_pf_enable_irq0(hw);
4198 case RTE_ETH_FILTER_DELETE:
4199 i40e_pf_disable_irq0(hw);
4201 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4202 i40e_pf_enable_irq0(hw);
4205 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4206 ret = I40E_ERR_PARAM;
4214 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4216 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4217 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4224 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4225 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4226 vsi->type != I40E_VSI_SRIOV,
4229 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4233 uint32_t *lut_dw = (uint32_t *)lut;
4234 uint16_t i, lut_size_dw = lut_size / 4;
4236 if (vsi->type == I40E_VSI_SRIOV) {
4237 for (i = 0; i <= lut_size_dw; i++) {
4238 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4239 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4242 for (i = 0; i < lut_size_dw; i++)
4243 lut_dw[i] = I40E_READ_REG(hw,
4252 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4261 pf = I40E_VSI_TO_PF(vsi);
4262 hw = I40E_VSI_TO_HW(vsi);
4264 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4265 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4266 vsi->type != I40E_VSI_SRIOV,
4269 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4273 uint32_t *lut_dw = (uint32_t *)lut;
4274 uint16_t i, lut_size_dw = lut_size / 4;
4276 if (vsi->type == I40E_VSI_SRIOV) {
4277 for (i = 0; i < lut_size_dw; i++)
4280 I40E_VFQF_HLUT1(i, vsi->user_param),
4283 for (i = 0; i < lut_size_dw; i++)
4284 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4287 I40E_WRITE_FLUSH(hw);
4294 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4295 struct rte_eth_rss_reta_entry64 *reta_conf,
4298 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4299 uint16_t i, lut_size = pf->hash_lut_size;
4300 uint16_t idx, shift;
4304 if (reta_size != lut_size ||
4305 reta_size > ETH_RSS_RETA_SIZE_512) {
4307 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4308 reta_size, lut_size);
4312 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4314 PMD_DRV_LOG(ERR, "No memory can be allocated");
4317 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4320 for (i = 0; i < reta_size; i++) {
4321 idx = i / RTE_RETA_GROUP_SIZE;
4322 shift = i % RTE_RETA_GROUP_SIZE;
4323 if (reta_conf[idx].mask & (1ULL << shift))
4324 lut[i] = reta_conf[idx].reta[shift];
4326 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4328 pf->adapter->rss_reta_updated = 1;
4337 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4338 struct rte_eth_rss_reta_entry64 *reta_conf,
4341 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4342 uint16_t i, lut_size = pf->hash_lut_size;
4343 uint16_t idx, shift;
4347 if (reta_size != lut_size ||
4348 reta_size > ETH_RSS_RETA_SIZE_512) {
4350 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4351 reta_size, lut_size);
4355 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4357 PMD_DRV_LOG(ERR, "No memory can be allocated");
4361 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4364 for (i = 0; i < reta_size; i++) {
4365 idx = i / RTE_RETA_GROUP_SIZE;
4366 shift = i % RTE_RETA_GROUP_SIZE;
4367 if (reta_conf[idx].mask & (1ULL << shift))
4368 reta_conf[idx].reta[shift] = lut[i];
4378 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4379 * @hw: pointer to the HW structure
4380 * @mem: pointer to mem struct to fill out
4381 * @size: size of memory requested
4382 * @alignment: what to align the allocation to
4384 enum i40e_status_code
4385 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4386 struct i40e_dma_mem *mem,
4390 const struct rte_memzone *mz = NULL;
4391 char z_name[RTE_MEMZONE_NAMESIZE];
4394 return I40E_ERR_PARAM;
4396 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4397 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4398 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4400 return I40E_ERR_NO_MEMORY;
4405 mem->zone = (const void *)mz;
4407 "memzone %s allocated with physical address: %"PRIu64,
4410 return I40E_SUCCESS;
4414 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4415 * @hw: pointer to the HW structure
4416 * @mem: ptr to mem struct to free
4418 enum i40e_status_code
4419 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4420 struct i40e_dma_mem *mem)
4423 return I40E_ERR_PARAM;
4426 "memzone %s to be freed with physical address: %"PRIu64,
4427 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4428 rte_memzone_free((const struct rte_memzone *)mem->zone);
4433 return I40E_SUCCESS;
4437 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4438 * @hw: pointer to the HW structure
4439 * @mem: pointer to mem struct to fill out
4440 * @size: size of memory requested
4442 enum i40e_status_code
4443 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4444 struct i40e_virt_mem *mem,
4448 return I40E_ERR_PARAM;
4451 mem->va = rte_zmalloc("i40e", size, 0);
4454 return I40E_SUCCESS;
4456 return I40E_ERR_NO_MEMORY;
4460 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4461 * @hw: pointer to the HW structure
4462 * @mem: pointer to mem struct to free
4464 enum i40e_status_code
4465 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4466 struct i40e_virt_mem *mem)
4469 return I40E_ERR_PARAM;
4474 return I40E_SUCCESS;
4478 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4480 rte_spinlock_init(&sp->spinlock);
4484 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4486 rte_spinlock_lock(&sp->spinlock);
4490 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4492 rte_spinlock_unlock(&sp->spinlock);
4496 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4502 * Get the hardware capabilities, which will be parsed
4503 * and saved into struct i40e_hw.
4506 i40e_get_cap(struct i40e_hw *hw)
4508 struct i40e_aqc_list_capabilities_element_resp *buf;
4509 uint16_t len, size = 0;
4512 /* Calculate a huge enough buff for saving response data temporarily */
4513 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4514 I40E_MAX_CAP_ELE_NUM;
4515 buf = rte_zmalloc("i40e", len, 0);
4517 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4518 return I40E_ERR_NO_MEMORY;
4521 /* Get, parse the capabilities and save it to hw */
4522 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4523 i40e_aqc_opc_list_func_capabilities, NULL);
4524 if (ret != I40E_SUCCESS)
4525 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4527 /* Free the temporary buffer after being used */
4533 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4535 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4543 pf = (struct i40e_pf *)opaque;
4547 num = strtoul(value, &end, 0);
4548 if (errno != 0 || end == value || *end != 0) {
4549 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4550 "kept the value = %hu", value, pf->vf_nb_qp_max);
4554 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4555 pf->vf_nb_qp_max = (uint16_t)num;
4557 /* here return 0 to make next valid same argument work */
4558 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4559 "power of 2 and equal or less than 16 !, Now it is "
4560 "kept the value = %hu", num, pf->vf_nb_qp_max);
4565 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4567 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4568 struct rte_kvargs *kvlist;
4571 /* set default queue number per VF as 4 */
4572 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4574 if (dev->device->devargs == NULL)
4577 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4581 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4582 if (!kvargs_count) {
4583 rte_kvargs_free(kvlist);
4587 if (kvargs_count > 1)
4588 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4589 "the first invalid or last valid one is used !",
4590 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4592 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4593 i40e_pf_parse_vf_queue_number_handler, pf);
4595 rte_kvargs_free(kvlist);
4601 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4603 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4604 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4605 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4606 uint16_t qp_count = 0, vsi_count = 0;
4608 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4609 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4613 i40e_pf_config_vf_rxq_number(dev);
4615 /* Add the parameter init for LFC */
4616 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4617 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4618 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4620 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4621 pf->max_num_vsi = hw->func_caps.num_vsis;
4622 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4623 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4625 /* FDir queue/VSI allocation */
4626 pf->fdir_qp_offset = 0;
4627 if (hw->func_caps.fd) {
4628 pf->flags |= I40E_FLAG_FDIR;
4629 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4631 pf->fdir_nb_qps = 0;
4633 qp_count += pf->fdir_nb_qps;
4636 /* LAN queue/VSI allocation */
4637 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4638 if (!hw->func_caps.rss) {
4641 pf->flags |= I40E_FLAG_RSS;
4642 if (hw->mac.type == I40E_MAC_X722)
4643 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4644 pf->lan_nb_qps = pf->lan_nb_qp_max;
4646 qp_count += pf->lan_nb_qps;
4649 /* VF queue/VSI allocation */
4650 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4651 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4652 pf->flags |= I40E_FLAG_SRIOV;
4653 pf->vf_nb_qps = pf->vf_nb_qp_max;
4654 pf->vf_num = pci_dev->max_vfs;
4656 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4657 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4662 qp_count += pf->vf_nb_qps * pf->vf_num;
4663 vsi_count += pf->vf_num;
4665 /* VMDq queue/VSI allocation */
4666 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4667 pf->vmdq_nb_qps = 0;
4668 pf->max_nb_vmdq_vsi = 0;
4669 if (hw->func_caps.vmdq) {
4670 if (qp_count < hw->func_caps.num_tx_qp &&
4671 vsi_count < hw->func_caps.num_vsis) {
4672 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4673 qp_count) / pf->vmdq_nb_qp_max;
4675 /* Limit the maximum number of VMDq vsi to the maximum
4676 * ethdev can support
4678 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4679 hw->func_caps.num_vsis - vsi_count);
4680 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4682 if (pf->max_nb_vmdq_vsi) {
4683 pf->flags |= I40E_FLAG_VMDQ;
4684 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4686 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4687 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4688 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4691 "No enough queues left for VMDq");
4694 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4697 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4698 vsi_count += pf->max_nb_vmdq_vsi;
4700 if (hw->func_caps.dcb)
4701 pf->flags |= I40E_FLAG_DCB;
4703 if (qp_count > hw->func_caps.num_tx_qp) {
4705 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4706 qp_count, hw->func_caps.num_tx_qp);
4709 if (vsi_count > hw->func_caps.num_vsis) {
4711 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4712 vsi_count, hw->func_caps.num_vsis);
4720 i40e_pf_get_switch_config(struct i40e_pf *pf)
4722 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4723 struct i40e_aqc_get_switch_config_resp *switch_config;
4724 struct i40e_aqc_switch_config_element_resp *element;
4725 uint16_t start_seid = 0, num_reported;
4728 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4729 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4730 if (!switch_config) {
4731 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4735 /* Get the switch configurations */
4736 ret = i40e_aq_get_switch_config(hw, switch_config,
4737 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4738 if (ret != I40E_SUCCESS) {
4739 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4742 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4743 if (num_reported != 1) { /* The number should be 1 */
4744 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4748 /* Parse the switch configuration elements */
4749 element = &(switch_config->element[0]);
4750 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4751 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4752 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4754 PMD_DRV_LOG(INFO, "Unknown element type");
4757 rte_free(switch_config);
4763 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4766 struct pool_entry *entry;
4768 if (pool == NULL || num == 0)
4771 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4772 if (entry == NULL) {
4773 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4777 /* queue heap initialize */
4778 pool->num_free = num;
4779 pool->num_alloc = 0;
4781 LIST_INIT(&pool->alloc_list);
4782 LIST_INIT(&pool->free_list);
4784 /* Initialize element */
4788 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4793 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4795 struct pool_entry *entry, *next_entry;
4800 for (entry = LIST_FIRST(&pool->alloc_list);
4801 entry && (next_entry = LIST_NEXT(entry, next), 1);
4802 entry = next_entry) {
4803 LIST_REMOVE(entry, next);
4807 for (entry = LIST_FIRST(&pool->free_list);
4808 entry && (next_entry = LIST_NEXT(entry, next), 1);
4809 entry = next_entry) {
4810 LIST_REMOVE(entry, next);
4815 pool->num_alloc = 0;
4817 LIST_INIT(&pool->alloc_list);
4818 LIST_INIT(&pool->free_list);
4822 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4825 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4826 uint32_t pool_offset;
4830 PMD_DRV_LOG(ERR, "Invalid parameter");
4834 pool_offset = base - pool->base;
4835 /* Lookup in alloc list */
4836 LIST_FOREACH(entry, &pool->alloc_list, next) {
4837 if (entry->base == pool_offset) {
4838 valid_entry = entry;
4839 LIST_REMOVE(entry, next);
4844 /* Not find, return */
4845 if (valid_entry == NULL) {
4846 PMD_DRV_LOG(ERR, "Failed to find entry");
4851 * Found it, move it to free list and try to merge.
4852 * In order to make merge easier, always sort it by qbase.
4853 * Find adjacent prev and last entries.
4856 LIST_FOREACH(entry, &pool->free_list, next) {
4857 if (entry->base > valid_entry->base) {
4865 /* Try to merge with next one*/
4867 /* Merge with next one */
4868 if (valid_entry->base + valid_entry->len == next->base) {
4869 next->base = valid_entry->base;
4870 next->len += valid_entry->len;
4871 rte_free(valid_entry);
4878 /* Merge with previous one */
4879 if (prev->base + prev->len == valid_entry->base) {
4880 prev->len += valid_entry->len;
4881 /* If it merge with next one, remove next node */
4883 LIST_REMOVE(valid_entry, next);
4884 rte_free(valid_entry);
4886 rte_free(valid_entry);
4892 /* Not find any entry to merge, insert */
4895 LIST_INSERT_AFTER(prev, valid_entry, next);
4896 else if (next != NULL)
4897 LIST_INSERT_BEFORE(next, valid_entry, next);
4898 else /* It's empty list, insert to head */
4899 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4902 pool->num_free += valid_entry->len;
4903 pool->num_alloc -= valid_entry->len;
4909 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4912 struct pool_entry *entry, *valid_entry;
4914 if (pool == NULL || num == 0) {
4915 PMD_DRV_LOG(ERR, "Invalid parameter");
4919 if (pool->num_free < num) {
4920 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4921 num, pool->num_free);
4926 /* Lookup in free list and find most fit one */
4927 LIST_FOREACH(entry, &pool->free_list, next) {
4928 if (entry->len >= num) {
4930 if (entry->len == num) {
4931 valid_entry = entry;
4934 if (valid_entry == NULL || valid_entry->len > entry->len)
4935 valid_entry = entry;
4939 /* Not find one to satisfy the request, return */
4940 if (valid_entry == NULL) {
4941 PMD_DRV_LOG(ERR, "No valid entry found");
4945 * The entry have equal queue number as requested,
4946 * remove it from alloc_list.
4948 if (valid_entry->len == num) {
4949 LIST_REMOVE(valid_entry, next);
4952 * The entry have more numbers than requested,
4953 * create a new entry for alloc_list and minus its
4954 * queue base and number in free_list.
4956 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4957 if (entry == NULL) {
4959 "Failed to allocate memory for resource pool");
4962 entry->base = valid_entry->base;
4964 valid_entry->base += num;
4965 valid_entry->len -= num;
4966 valid_entry = entry;
4969 /* Insert it into alloc list, not sorted */
4970 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4972 pool->num_free -= valid_entry->len;
4973 pool->num_alloc += valid_entry->len;
4975 return valid_entry->base + pool->base;
4979 * bitmap_is_subset - Check whether src2 is subset of src1
4982 bitmap_is_subset(uint8_t src1, uint8_t src2)
4984 return !((src1 ^ src2) & src2);
4987 static enum i40e_status_code
4988 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4990 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4992 /* If DCB is not supported, only default TC is supported */
4993 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4994 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4995 return I40E_NOT_SUPPORTED;
4998 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5000 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5001 hw->func_caps.enabled_tcmap, enabled_tcmap);
5002 return I40E_NOT_SUPPORTED;
5004 return I40E_SUCCESS;
5008 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5009 struct i40e_vsi_vlan_pvid_info *info)
5012 struct i40e_vsi_context ctxt;
5013 uint8_t vlan_flags = 0;
5016 if (vsi == NULL || info == NULL) {
5017 PMD_DRV_LOG(ERR, "invalid parameters");
5018 return I40E_ERR_PARAM;
5022 vsi->info.pvid = info->config.pvid;
5024 * If insert pvid is enabled, only tagged pkts are
5025 * allowed to be sent out.
5027 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5028 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5031 if (info->config.reject.tagged == 0)
5032 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5034 if (info->config.reject.untagged == 0)
5035 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5037 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5038 I40E_AQ_VSI_PVLAN_MODE_MASK);
5039 vsi->info.port_vlan_flags |= vlan_flags;
5040 vsi->info.valid_sections =
5041 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5042 memset(&ctxt, 0, sizeof(ctxt));
5043 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5044 ctxt.seid = vsi->seid;
5046 hw = I40E_VSI_TO_HW(vsi);
5047 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5048 if (ret != I40E_SUCCESS)
5049 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5055 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5057 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5059 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5061 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5062 if (ret != I40E_SUCCESS)
5066 PMD_DRV_LOG(ERR, "seid not valid");
5070 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5071 tc_bw_data.tc_valid_bits = enabled_tcmap;
5072 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5073 tc_bw_data.tc_bw_credits[i] =
5074 (enabled_tcmap & (1 << i)) ? 1 : 0;
5076 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5077 if (ret != I40E_SUCCESS) {
5078 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5082 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5083 sizeof(vsi->info.qs_handle));
5084 return I40E_SUCCESS;
5087 static enum i40e_status_code
5088 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5089 struct i40e_aqc_vsi_properties_data *info,
5090 uint8_t enabled_tcmap)
5092 enum i40e_status_code ret;
5093 int i, total_tc = 0;
5094 uint16_t qpnum_per_tc, bsf, qp_idx;
5096 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5097 if (ret != I40E_SUCCESS)
5100 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5101 if (enabled_tcmap & (1 << i))
5105 vsi->enabled_tc = enabled_tcmap;
5107 /* Number of queues per enabled TC */
5108 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5109 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5110 bsf = rte_bsf32(qpnum_per_tc);
5112 /* Adjust the queue number to actual queues that can be applied */
5113 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5114 vsi->nb_qps = qpnum_per_tc * total_tc;
5117 * Configure TC and queue mapping parameters, for enabled TC,
5118 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5119 * default queue will serve it.
5122 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5123 if (vsi->enabled_tc & (1 << i)) {
5124 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5125 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5126 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5127 qp_idx += qpnum_per_tc;
5129 info->tc_mapping[i] = 0;
5132 /* Associate queue number with VSI */
5133 if (vsi->type == I40E_VSI_SRIOV) {
5134 info->mapping_flags |=
5135 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5136 for (i = 0; i < vsi->nb_qps; i++)
5137 info->queue_mapping[i] =
5138 rte_cpu_to_le_16(vsi->base_queue + i);
5140 info->mapping_flags |=
5141 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5142 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5144 info->valid_sections |=
5145 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5147 return I40E_SUCCESS;
5151 i40e_veb_release(struct i40e_veb *veb)
5153 struct i40e_vsi *vsi;
5159 if (!TAILQ_EMPTY(&veb->head)) {
5160 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5163 /* associate_vsi field is NULL for floating VEB */
5164 if (veb->associate_vsi != NULL) {
5165 vsi = veb->associate_vsi;
5166 hw = I40E_VSI_TO_HW(vsi);
5168 vsi->uplink_seid = veb->uplink_seid;
5171 veb->associate_pf->main_vsi->floating_veb = NULL;
5172 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5175 i40e_aq_delete_element(hw, veb->seid, NULL);
5177 return I40E_SUCCESS;
5181 static struct i40e_veb *
5182 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5184 struct i40e_veb *veb;
5190 "veb setup failed, associated PF shouldn't null");
5193 hw = I40E_PF_TO_HW(pf);
5195 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5197 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5201 veb->associate_vsi = vsi;
5202 veb->associate_pf = pf;
5203 TAILQ_INIT(&veb->head);
5204 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5206 /* create floating veb if vsi is NULL */
5208 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5209 I40E_DEFAULT_TCMAP, false,
5210 &veb->seid, false, NULL);
5212 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5213 true, &veb->seid, false, NULL);
5216 if (ret != I40E_SUCCESS) {
5217 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5218 hw->aq.asq_last_status);
5221 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5223 /* get statistics index */
5224 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5225 &veb->stats_idx, NULL, NULL, NULL);
5226 if (ret != I40E_SUCCESS) {
5227 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5228 hw->aq.asq_last_status);
5231 /* Get VEB bandwidth, to be implemented */
5232 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5234 vsi->uplink_seid = veb->seid;
5243 i40e_vsi_release(struct i40e_vsi *vsi)
5247 struct i40e_vsi_list *vsi_list;
5250 struct i40e_mac_filter *f;
5251 uint16_t user_param;
5254 return I40E_SUCCESS;
5259 user_param = vsi->user_param;
5261 pf = I40E_VSI_TO_PF(vsi);
5262 hw = I40E_VSI_TO_HW(vsi);
5264 /* VSI has child to attach, release child first */
5266 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5267 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5270 i40e_veb_release(vsi->veb);
5273 if (vsi->floating_veb) {
5274 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5275 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5280 /* Remove all macvlan filters of the VSI */
5281 i40e_vsi_remove_all_macvlan_filter(vsi);
5282 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5285 if (vsi->type != I40E_VSI_MAIN &&
5286 ((vsi->type != I40E_VSI_SRIOV) ||
5287 !pf->floating_veb_list[user_param])) {
5288 /* Remove vsi from parent's sibling list */
5289 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5290 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5291 return I40E_ERR_PARAM;
5293 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5294 &vsi->sib_vsi_list, list);
5296 /* Remove all switch element of the VSI */
5297 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5298 if (ret != I40E_SUCCESS)
5299 PMD_DRV_LOG(ERR, "Failed to delete element");
5302 if ((vsi->type == I40E_VSI_SRIOV) &&
5303 pf->floating_veb_list[user_param]) {
5304 /* Remove vsi from parent's sibling list */
5305 if (vsi->parent_vsi == NULL ||
5306 vsi->parent_vsi->floating_veb == NULL) {
5307 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5308 return I40E_ERR_PARAM;
5310 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5311 &vsi->sib_vsi_list, list);
5313 /* Remove all switch element of the VSI */
5314 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5315 if (ret != I40E_SUCCESS)
5316 PMD_DRV_LOG(ERR, "Failed to delete element");
5319 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5321 if (vsi->type != I40E_VSI_SRIOV)
5322 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5325 return I40E_SUCCESS;
5329 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5331 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5332 struct i40e_aqc_remove_macvlan_element_data def_filter;
5333 struct i40e_mac_filter_info filter;
5336 if (vsi->type != I40E_VSI_MAIN)
5337 return I40E_ERR_CONFIG;
5338 memset(&def_filter, 0, sizeof(def_filter));
5339 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5341 def_filter.vlan_tag = 0;
5342 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5343 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5344 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5345 if (ret != I40E_SUCCESS) {
5346 struct i40e_mac_filter *f;
5347 struct rte_ether_addr *mac;
5350 "Cannot remove the default macvlan filter");
5351 /* It needs to add the permanent mac into mac list */
5352 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5354 PMD_DRV_LOG(ERR, "failed to allocate memory");
5355 return I40E_ERR_NO_MEMORY;
5357 mac = &f->mac_info.mac_addr;
5358 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5360 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5361 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5366 rte_memcpy(&filter.mac_addr,
5367 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5368 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5369 return i40e_vsi_add_mac(vsi, &filter);
5373 * i40e_vsi_get_bw_config - Query VSI BW Information
5374 * @vsi: the VSI to be queried
5376 * Returns 0 on success, negative value on failure
5378 static enum i40e_status_code
5379 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5381 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5382 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5383 struct i40e_hw *hw = &vsi->adapter->hw;
5388 memset(&bw_config, 0, sizeof(bw_config));
5389 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5390 if (ret != I40E_SUCCESS) {
5391 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5392 hw->aq.asq_last_status);
5396 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5397 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5398 &ets_sla_config, NULL);
5399 if (ret != I40E_SUCCESS) {
5401 "VSI failed to get TC bandwdith configuration %u",
5402 hw->aq.asq_last_status);
5406 /* store and print out BW info */
5407 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5408 vsi->bw_info.bw_max = bw_config.max_bw;
5409 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5410 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5411 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5412 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5414 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5415 vsi->bw_info.bw_ets_share_credits[i] =
5416 ets_sla_config.share_credits[i];
5417 vsi->bw_info.bw_ets_credits[i] =
5418 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5419 /* 4 bits per TC, 4th bit is reserved */
5420 vsi->bw_info.bw_ets_max[i] =
5421 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5422 RTE_LEN2MASK(3, uint8_t));
5423 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5424 vsi->bw_info.bw_ets_share_credits[i]);
5425 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5426 vsi->bw_info.bw_ets_credits[i]);
5427 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5428 vsi->bw_info.bw_ets_max[i]);
5431 return I40E_SUCCESS;
5434 /* i40e_enable_pf_lb
5435 * @pf: pointer to the pf structure
5437 * allow loopback on pf
5440 i40e_enable_pf_lb(struct i40e_pf *pf)
5442 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5443 struct i40e_vsi_context ctxt;
5446 /* Use the FW API if FW >= v5.0 */
5447 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5448 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5452 memset(&ctxt, 0, sizeof(ctxt));
5453 ctxt.seid = pf->main_vsi_seid;
5454 ctxt.pf_num = hw->pf_id;
5455 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5457 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5458 ret, hw->aq.asq_last_status);
5461 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5462 ctxt.info.valid_sections =
5463 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5464 ctxt.info.switch_id |=
5465 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5467 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5469 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5470 hw->aq.asq_last_status);
5475 i40e_vsi_setup(struct i40e_pf *pf,
5476 enum i40e_vsi_type type,
5477 struct i40e_vsi *uplink_vsi,
5478 uint16_t user_param)
5480 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5481 struct i40e_vsi *vsi;
5482 struct i40e_mac_filter_info filter;
5484 struct i40e_vsi_context ctxt;
5485 struct rte_ether_addr broadcast =
5486 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5488 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5489 uplink_vsi == NULL) {
5491 "VSI setup failed, VSI link shouldn't be NULL");
5495 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5497 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5502 * 1.type is not MAIN and uplink vsi is not NULL
5503 * If uplink vsi didn't setup VEB, create one first under veb field
5504 * 2.type is SRIOV and the uplink is NULL
5505 * If floating VEB is NULL, create one veb under floating veb field
5508 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5509 uplink_vsi->veb == NULL) {
5510 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5512 if (uplink_vsi->veb == NULL) {
5513 PMD_DRV_LOG(ERR, "VEB setup failed");
5516 /* set ALLOWLOOPBACk on pf, when veb is created */
5517 i40e_enable_pf_lb(pf);
5520 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5521 pf->main_vsi->floating_veb == NULL) {
5522 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5524 if (pf->main_vsi->floating_veb == NULL) {
5525 PMD_DRV_LOG(ERR, "VEB setup failed");
5530 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5532 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5535 TAILQ_INIT(&vsi->mac_list);
5537 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5538 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5539 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5540 vsi->user_param = user_param;
5541 vsi->vlan_anti_spoof_on = 0;
5542 vsi->vlan_filter_on = 0;
5543 /* Allocate queues */
5544 switch (vsi->type) {
5545 case I40E_VSI_MAIN :
5546 vsi->nb_qps = pf->lan_nb_qps;
5548 case I40E_VSI_SRIOV :
5549 vsi->nb_qps = pf->vf_nb_qps;
5551 case I40E_VSI_VMDQ2:
5552 vsi->nb_qps = pf->vmdq_nb_qps;
5555 vsi->nb_qps = pf->fdir_nb_qps;
5561 * The filter status descriptor is reported in rx queue 0,
5562 * while the tx queue for fdir filter programming has no
5563 * such constraints, can be non-zero queues.
5564 * To simplify it, choose FDIR vsi use queue 0 pair.
5565 * To make sure it will use queue 0 pair, queue allocation
5566 * need be done before this function is called
5568 if (type != I40E_VSI_FDIR) {
5569 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5571 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5575 vsi->base_queue = ret;
5577 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5579 /* VF has MSIX interrupt in VF range, don't allocate here */
5580 if (type == I40E_VSI_MAIN) {
5581 if (pf->support_multi_driver) {
5582 /* If support multi-driver, need to use INT0 instead of
5583 * allocating from msix pool. The Msix pool is init from
5584 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5585 * to 1 without calling i40e_res_pool_alloc.
5590 ret = i40e_res_pool_alloc(&pf->msix_pool,
5591 RTE_MIN(vsi->nb_qps,
5592 RTE_MAX_RXTX_INTR_VEC_ID));
5595 "VSI MAIN %d get heap failed %d",
5597 goto fail_queue_alloc;
5599 vsi->msix_intr = ret;
5600 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5601 RTE_MAX_RXTX_INTR_VEC_ID);
5603 } else if (type != I40E_VSI_SRIOV) {
5604 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5606 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5607 goto fail_queue_alloc;
5609 vsi->msix_intr = ret;
5617 if (type == I40E_VSI_MAIN) {
5618 /* For main VSI, no need to add since it's default one */
5619 vsi->uplink_seid = pf->mac_seid;
5620 vsi->seid = pf->main_vsi_seid;
5621 /* Bind queues with specific MSIX interrupt */
5623 * Needs 2 interrupt at least, one for misc cause which will
5624 * enabled from OS side, Another for queues binding the
5625 * interrupt from device side only.
5628 /* Get default VSI parameters from hardware */
5629 memset(&ctxt, 0, sizeof(ctxt));
5630 ctxt.seid = vsi->seid;
5631 ctxt.pf_num = hw->pf_id;
5632 ctxt.uplink_seid = vsi->uplink_seid;
5634 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5635 if (ret != I40E_SUCCESS) {
5636 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5637 goto fail_msix_alloc;
5639 rte_memcpy(&vsi->info, &ctxt.info,
5640 sizeof(struct i40e_aqc_vsi_properties_data));
5641 vsi->vsi_id = ctxt.vsi_number;
5642 vsi->info.valid_sections = 0;
5644 /* Configure tc, enabled TC0 only */
5645 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5647 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5648 goto fail_msix_alloc;
5651 /* TC, queue mapping */
5652 memset(&ctxt, 0, sizeof(ctxt));
5653 vsi->info.valid_sections |=
5654 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5655 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5656 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5657 rte_memcpy(&ctxt.info, &vsi->info,
5658 sizeof(struct i40e_aqc_vsi_properties_data));
5659 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5660 I40E_DEFAULT_TCMAP);
5661 if (ret != I40E_SUCCESS) {
5663 "Failed to configure TC queue mapping");
5664 goto fail_msix_alloc;
5666 ctxt.seid = vsi->seid;
5667 ctxt.pf_num = hw->pf_id;
5668 ctxt.uplink_seid = vsi->uplink_seid;
5671 /* Update VSI parameters */
5672 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5673 if (ret != I40E_SUCCESS) {
5674 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5675 goto fail_msix_alloc;
5678 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5679 sizeof(vsi->info.tc_mapping));
5680 rte_memcpy(&vsi->info.queue_mapping,
5681 &ctxt.info.queue_mapping,
5682 sizeof(vsi->info.queue_mapping));
5683 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5684 vsi->info.valid_sections = 0;
5686 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5690 * Updating default filter settings are necessary to prevent
5691 * reception of tagged packets.
5692 * Some old firmware configurations load a default macvlan
5693 * filter which accepts both tagged and untagged packets.
5694 * The updating is to use a normal filter instead if needed.
5695 * For NVM 4.2.2 or after, the updating is not needed anymore.
5696 * The firmware with correct configurations load the default
5697 * macvlan filter which is expected and cannot be removed.
5699 i40e_update_default_filter_setting(vsi);
5700 i40e_config_qinq(hw, vsi);
5701 } else if (type == I40E_VSI_SRIOV) {
5702 memset(&ctxt, 0, sizeof(ctxt));
5704 * For other VSI, the uplink_seid equals to uplink VSI's
5705 * uplink_seid since they share same VEB
5707 if (uplink_vsi == NULL)
5708 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5710 vsi->uplink_seid = uplink_vsi->uplink_seid;
5711 ctxt.pf_num = hw->pf_id;
5712 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5713 ctxt.uplink_seid = vsi->uplink_seid;
5714 ctxt.connection_type = 0x1;
5715 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5717 /* Use the VEB configuration if FW >= v5.0 */
5718 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5719 /* Configure switch ID */
5720 ctxt.info.valid_sections |=
5721 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5722 ctxt.info.switch_id =
5723 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5726 /* Configure port/vlan */
5727 ctxt.info.valid_sections |=
5728 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5729 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5730 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5731 hw->func_caps.enabled_tcmap);
5732 if (ret != I40E_SUCCESS) {
5734 "Failed to configure TC queue mapping");
5735 goto fail_msix_alloc;
5738 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5739 ctxt.info.valid_sections |=
5740 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5742 * Since VSI is not created yet, only configure parameter,
5743 * will add vsi below.
5746 i40e_config_qinq(hw, vsi);
5747 } else if (type == I40E_VSI_VMDQ2) {
5748 memset(&ctxt, 0, sizeof(ctxt));
5750 * For other VSI, the uplink_seid equals to uplink VSI's
5751 * uplink_seid since they share same VEB
5753 vsi->uplink_seid = uplink_vsi->uplink_seid;
5754 ctxt.pf_num = hw->pf_id;
5756 ctxt.uplink_seid = vsi->uplink_seid;
5757 ctxt.connection_type = 0x1;
5758 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5760 ctxt.info.valid_sections |=
5761 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5762 /* user_param carries flag to enable loop back */
5764 ctxt.info.switch_id =
5765 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5766 ctxt.info.switch_id |=
5767 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5770 /* Configure port/vlan */
5771 ctxt.info.valid_sections |=
5772 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5773 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5774 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5775 I40E_DEFAULT_TCMAP);
5776 if (ret != I40E_SUCCESS) {
5778 "Failed to configure TC queue mapping");
5779 goto fail_msix_alloc;
5781 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5782 ctxt.info.valid_sections |=
5783 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5784 } else if (type == I40E_VSI_FDIR) {
5785 memset(&ctxt, 0, sizeof(ctxt));
5786 vsi->uplink_seid = uplink_vsi->uplink_seid;
5787 ctxt.pf_num = hw->pf_id;
5789 ctxt.uplink_seid = vsi->uplink_seid;
5790 ctxt.connection_type = 0x1; /* regular data port */
5791 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5792 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5793 I40E_DEFAULT_TCMAP);
5794 if (ret != I40E_SUCCESS) {
5796 "Failed to configure TC queue mapping.");
5797 goto fail_msix_alloc;
5799 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5800 ctxt.info.valid_sections |=
5801 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5803 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5804 goto fail_msix_alloc;
5807 if (vsi->type != I40E_VSI_MAIN) {
5808 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5809 if (ret != I40E_SUCCESS) {
5810 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5811 hw->aq.asq_last_status);
5812 goto fail_msix_alloc;
5814 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5815 vsi->info.valid_sections = 0;
5816 vsi->seid = ctxt.seid;
5817 vsi->vsi_id = ctxt.vsi_number;
5818 vsi->sib_vsi_list.vsi = vsi;
5819 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5820 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5821 &vsi->sib_vsi_list, list);
5823 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5824 &vsi->sib_vsi_list, list);
5828 /* MAC/VLAN configuration */
5829 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5830 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5832 ret = i40e_vsi_add_mac(vsi, &filter);
5833 if (ret != I40E_SUCCESS) {
5834 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5835 goto fail_msix_alloc;
5838 /* Get VSI BW information */
5839 i40e_vsi_get_bw_config(vsi);
5842 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5844 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5850 /* Configure vlan filter on or off */
5852 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5855 struct i40e_mac_filter *f;
5857 struct i40e_mac_filter_info *mac_filter;
5858 enum rte_mac_filter_type desired_filter;
5859 int ret = I40E_SUCCESS;
5862 /* Filter to match MAC and VLAN */
5863 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5865 /* Filter to match only MAC */
5866 desired_filter = RTE_MAC_PERFECT_MATCH;
5871 mac_filter = rte_zmalloc("mac_filter_info_data",
5872 num * sizeof(*mac_filter), 0);
5873 if (mac_filter == NULL) {
5874 PMD_DRV_LOG(ERR, "failed to allocate memory");
5875 return I40E_ERR_NO_MEMORY;
5880 /* Remove all existing mac */
5881 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5882 mac_filter[i] = f->mac_info;
5883 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5885 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5886 on ? "enable" : "disable");
5892 /* Override with new filter */
5893 for (i = 0; i < num; i++) {
5894 mac_filter[i].filter_type = desired_filter;
5895 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5897 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5898 on ? "enable" : "disable");
5904 rte_free(mac_filter);
5908 /* Configure vlan stripping on or off */
5910 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5912 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5913 struct i40e_vsi_context ctxt;
5915 int ret = I40E_SUCCESS;
5917 /* Check if it has been already on or off */
5918 if (vsi->info.valid_sections &
5919 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5921 if ((vsi->info.port_vlan_flags &
5922 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5923 return 0; /* already on */
5925 if ((vsi->info.port_vlan_flags &
5926 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5927 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5928 return 0; /* already off */
5933 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5935 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5936 vsi->info.valid_sections =
5937 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5938 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5939 vsi->info.port_vlan_flags |= vlan_flags;
5940 ctxt.seid = vsi->seid;
5941 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5942 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5944 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5945 on ? "enable" : "disable");
5951 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5953 struct rte_eth_dev_data *data = dev->data;
5957 /* Apply vlan offload setting */
5958 mask = ETH_VLAN_STRIP_MASK |
5959 ETH_VLAN_FILTER_MASK |
5960 ETH_VLAN_EXTEND_MASK;
5961 ret = i40e_vlan_offload_set(dev, mask);
5963 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5967 /* Apply pvid setting */
5968 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5969 data->dev_conf.txmode.hw_vlan_insert_pvid);
5971 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5977 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5979 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5981 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5985 i40e_update_flow_control(struct i40e_hw *hw)
5987 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5988 struct i40e_link_status link_status;
5989 uint32_t rxfc = 0, txfc = 0, reg;
5993 memset(&link_status, 0, sizeof(link_status));
5994 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5995 if (ret != I40E_SUCCESS) {
5996 PMD_DRV_LOG(ERR, "Failed to get link status information");
5997 goto write_reg; /* Disable flow control */
6000 an_info = hw->phy.link_info.an_info;
6001 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6002 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6003 ret = I40E_ERR_NOT_READY;
6004 goto write_reg; /* Disable flow control */
6007 * If link auto negotiation is enabled, flow control needs to
6008 * be configured according to it
6010 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6011 case I40E_LINK_PAUSE_RXTX:
6014 hw->fc.current_mode = I40E_FC_FULL;
6016 case I40E_AQ_LINK_PAUSE_RX:
6018 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6020 case I40E_AQ_LINK_PAUSE_TX:
6022 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6025 hw->fc.current_mode = I40E_FC_NONE;
6030 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6031 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6032 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6033 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6034 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6035 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6042 i40e_pf_setup(struct i40e_pf *pf)
6044 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6045 struct i40e_filter_control_settings settings;
6046 struct i40e_vsi *vsi;
6049 /* Clear all stats counters */
6050 pf->offset_loaded = FALSE;
6051 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6052 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6053 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6054 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6056 ret = i40e_pf_get_switch_config(pf);
6057 if (ret != I40E_SUCCESS) {
6058 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6062 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6064 PMD_INIT_LOG(WARNING,
6065 "failed to allocate switch domain for device %d", ret);
6067 if (pf->flags & I40E_FLAG_FDIR) {
6068 /* make queue allocated first, let FDIR use queue pair 0*/
6069 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6070 if (ret != I40E_FDIR_QUEUE_ID) {
6072 "queue allocation fails for FDIR: ret =%d",
6074 pf->flags &= ~I40E_FLAG_FDIR;
6077 /* main VSI setup */
6078 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6080 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6081 return I40E_ERR_NOT_READY;
6085 /* Configure filter control */
6086 memset(&settings, 0, sizeof(settings));
6087 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6088 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6089 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6090 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6092 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6093 hw->func_caps.rss_table_size);
6094 return I40E_ERR_PARAM;
6096 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6097 hw->func_caps.rss_table_size);
6098 pf->hash_lut_size = hw->func_caps.rss_table_size;
6100 /* Enable ethtype and macvlan filters */
6101 settings.enable_ethtype = TRUE;
6102 settings.enable_macvlan = TRUE;
6103 ret = i40e_set_filter_control(hw, &settings);
6105 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6108 /* Update flow control according to the auto negotiation */
6109 i40e_update_flow_control(hw);
6111 return I40E_SUCCESS;
6115 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6121 * Set or clear TX Queue Disable flags,
6122 * which is required by hardware.
6124 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6125 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6127 /* Wait until the request is finished */
6128 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6129 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6130 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6131 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6132 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6138 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6139 return I40E_SUCCESS; /* already on, skip next steps */
6141 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6142 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6144 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6145 return I40E_SUCCESS; /* already off, skip next steps */
6146 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6148 /* Write the register */
6149 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6150 /* Check the result */
6151 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6152 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6153 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6155 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6156 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6159 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6160 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6164 /* Check if it is timeout */
6165 if (j >= I40E_CHK_Q_ENA_COUNT) {
6166 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6167 (on ? "enable" : "disable"), q_idx);
6168 return I40E_ERR_TIMEOUT;
6171 return I40E_SUCCESS;
6174 /* Swith on or off the tx queues */
6176 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6178 struct rte_eth_dev_data *dev_data = pf->dev_data;
6179 struct i40e_tx_queue *txq;
6180 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6184 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6185 txq = dev_data->tx_queues[i];
6186 /* Don't operate the queue if not configured or
6187 * if starting only per queue */
6188 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6191 ret = i40e_dev_tx_queue_start(dev, i);
6193 ret = i40e_dev_tx_queue_stop(dev, i);
6194 if ( ret != I40E_SUCCESS)
6198 return I40E_SUCCESS;
6202 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6207 /* Wait until the request is finished */
6208 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6209 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6210 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6211 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6212 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6217 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6218 return I40E_SUCCESS; /* Already on, skip next steps */
6219 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6221 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6222 return I40E_SUCCESS; /* Already off, skip next steps */
6223 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6226 /* Write the register */
6227 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6228 /* Check the result */
6229 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6230 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6231 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6233 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6234 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6237 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6238 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6243 /* Check if it is timeout */
6244 if (j >= I40E_CHK_Q_ENA_COUNT) {
6245 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6246 (on ? "enable" : "disable"), q_idx);
6247 return I40E_ERR_TIMEOUT;
6250 return I40E_SUCCESS;
6252 /* Switch on or off the rx queues */
6254 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6256 struct rte_eth_dev_data *dev_data = pf->dev_data;
6257 struct i40e_rx_queue *rxq;
6258 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6262 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6263 rxq = dev_data->rx_queues[i];
6264 /* Don't operate the queue if not configured or
6265 * if starting only per queue */
6266 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6269 ret = i40e_dev_rx_queue_start(dev, i);
6271 ret = i40e_dev_rx_queue_stop(dev, i);
6272 if (ret != I40E_SUCCESS)
6276 return I40E_SUCCESS;
6279 /* Switch on or off all the rx/tx queues */
6281 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6286 /* enable rx queues before enabling tx queues */
6287 ret = i40e_dev_switch_rx_queues(pf, on);
6289 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6292 ret = i40e_dev_switch_tx_queues(pf, on);
6294 /* Stop tx queues before stopping rx queues */
6295 ret = i40e_dev_switch_tx_queues(pf, on);
6297 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6300 ret = i40e_dev_switch_rx_queues(pf, on);
6306 /* Initialize VSI for TX */
6308 i40e_dev_tx_init(struct i40e_pf *pf)
6310 struct rte_eth_dev_data *data = pf->dev_data;
6312 uint32_t ret = I40E_SUCCESS;
6313 struct i40e_tx_queue *txq;
6315 for (i = 0; i < data->nb_tx_queues; i++) {
6316 txq = data->tx_queues[i];
6317 if (!txq || !txq->q_set)
6319 ret = i40e_tx_queue_init(txq);
6320 if (ret != I40E_SUCCESS)
6323 if (ret == I40E_SUCCESS)
6324 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6330 /* Initialize VSI for RX */
6332 i40e_dev_rx_init(struct i40e_pf *pf)
6334 struct rte_eth_dev_data *data = pf->dev_data;
6335 int ret = I40E_SUCCESS;
6337 struct i40e_rx_queue *rxq;
6339 i40e_pf_config_mq_rx(pf);
6340 for (i = 0; i < data->nb_rx_queues; i++) {
6341 rxq = data->rx_queues[i];
6342 if (!rxq || !rxq->q_set)
6345 ret = i40e_rx_queue_init(rxq);
6346 if (ret != I40E_SUCCESS) {
6348 "Failed to do RX queue initialization");
6352 if (ret == I40E_SUCCESS)
6353 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6360 i40e_dev_rxtx_init(struct i40e_pf *pf)
6364 err = i40e_dev_tx_init(pf);
6366 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6369 err = i40e_dev_rx_init(pf);
6371 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6379 i40e_vmdq_setup(struct rte_eth_dev *dev)
6381 struct rte_eth_conf *conf = &dev->data->dev_conf;
6382 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6383 int i, err, conf_vsis, j, loop;
6384 struct i40e_vsi *vsi;
6385 struct i40e_vmdq_info *vmdq_info;
6386 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6387 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6390 * Disable interrupt to avoid message from VF. Furthermore, it will
6391 * avoid race condition in VSI creation/destroy.
6393 i40e_pf_disable_irq0(hw);
6395 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6396 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6400 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6401 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6402 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6403 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6404 pf->max_nb_vmdq_vsi);
6408 if (pf->vmdq != NULL) {
6409 PMD_INIT_LOG(INFO, "VMDQ already configured");
6413 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6414 sizeof(*vmdq_info) * conf_vsis, 0);
6416 if (pf->vmdq == NULL) {
6417 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6421 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6423 /* Create VMDQ VSI */
6424 for (i = 0; i < conf_vsis; i++) {
6425 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6426 vmdq_conf->enable_loop_back);
6428 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6432 vmdq_info = &pf->vmdq[i];
6434 vmdq_info->vsi = vsi;
6436 pf->nb_cfg_vmdq_vsi = conf_vsis;
6438 /* Configure Vlan */
6439 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6440 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6441 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6442 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6443 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6444 vmdq_conf->pool_map[i].vlan_id, j);
6446 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6447 vmdq_conf->pool_map[i].vlan_id);
6449 PMD_INIT_LOG(ERR, "Failed to add vlan");
6457 i40e_pf_enable_irq0(hw);
6462 for (i = 0; i < conf_vsis; i++)
6463 if (pf->vmdq[i].vsi == NULL)
6466 i40e_vsi_release(pf->vmdq[i].vsi);
6470 i40e_pf_enable_irq0(hw);
6475 i40e_stat_update_32(struct i40e_hw *hw,
6483 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6487 if (new_data >= *offset)
6488 *stat = (uint64_t)(new_data - *offset);
6490 *stat = (uint64_t)((new_data +
6491 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6495 i40e_stat_update_48(struct i40e_hw *hw,
6504 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6505 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6506 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6511 if (new_data >= *offset)
6512 *stat = new_data - *offset;
6514 *stat = (uint64_t)((new_data +
6515 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6517 *stat &= I40E_48_BIT_MASK;
6522 i40e_pf_disable_irq0(struct i40e_hw *hw)
6524 /* Disable all interrupt types */
6525 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6526 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6527 I40E_WRITE_FLUSH(hw);
6532 i40e_pf_enable_irq0(struct i40e_hw *hw)
6534 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6535 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6536 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6537 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6538 I40E_WRITE_FLUSH(hw);
6542 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6544 /* read pending request and disable first */
6545 i40e_pf_disable_irq0(hw);
6546 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6547 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6548 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6551 /* Link no queues with irq0 */
6552 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6553 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6557 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6559 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6560 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6563 uint32_t index, offset, val;
6568 * Try to find which VF trigger a reset, use absolute VF id to access
6569 * since the reg is global register.
6571 for (i = 0; i < pf->vf_num; i++) {
6572 abs_vf_id = hw->func_caps.vf_base_id + i;
6573 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6574 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6575 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6576 /* VFR event occurred */
6577 if (val & (0x1 << offset)) {
6580 /* Clear the event first */
6581 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6583 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6585 * Only notify a VF reset event occurred,
6586 * don't trigger another SW reset
6588 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6589 if (ret != I40E_SUCCESS)
6590 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6596 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6598 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6601 for (i = 0; i < pf->vf_num; i++)
6602 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6606 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6608 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6609 struct i40e_arq_event_info info;
6610 uint16_t pending, opcode;
6613 info.buf_len = I40E_AQ_BUF_SZ;
6614 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6615 if (!info.msg_buf) {
6616 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6622 ret = i40e_clean_arq_element(hw, &info, &pending);
6624 if (ret != I40E_SUCCESS) {
6626 "Failed to read msg from AdminQ, aq_err: %u",
6627 hw->aq.asq_last_status);
6630 opcode = rte_le_to_cpu_16(info.desc.opcode);
6633 case i40e_aqc_opc_send_msg_to_pf:
6634 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6635 i40e_pf_host_handle_vf_msg(dev,
6636 rte_le_to_cpu_16(info.desc.retval),
6637 rte_le_to_cpu_32(info.desc.cookie_high),
6638 rte_le_to_cpu_32(info.desc.cookie_low),
6642 case i40e_aqc_opc_get_link_status:
6643 ret = i40e_dev_link_update(dev, 0);
6645 _rte_eth_dev_callback_process(dev,
6646 RTE_ETH_EVENT_INTR_LSC, NULL);
6649 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6654 rte_free(info.msg_buf);
6658 * Interrupt handler triggered by NIC for handling
6659 * specific interrupt.
6662 * Pointer to interrupt handle.
6664 * The address of parameter (struct rte_eth_dev *) regsitered before.
6670 i40e_dev_interrupt_handler(void *param)
6672 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6673 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6676 /* Disable interrupt */
6677 i40e_pf_disable_irq0(hw);
6679 /* read out interrupt causes */
6680 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6682 /* No interrupt event indicated */
6683 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6684 PMD_DRV_LOG(INFO, "No interrupt event");
6687 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6688 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6689 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6690 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6691 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6692 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6693 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6694 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6695 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6696 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6697 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6698 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6699 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6700 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6702 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6703 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6704 i40e_dev_handle_vfr_event(dev);
6706 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6707 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6708 i40e_dev_handle_aq_msg(dev);
6712 /* Enable interrupt */
6713 i40e_pf_enable_irq0(hw);
6717 i40e_dev_alarm_handler(void *param)
6719 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6720 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6723 /* Disable interrupt */
6724 i40e_pf_disable_irq0(hw);
6726 /* read out interrupt causes */
6727 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6729 /* No interrupt event indicated */
6730 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6732 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6733 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6734 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6735 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6736 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6737 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6738 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6739 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6740 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6741 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6742 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6743 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6744 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6745 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6747 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6748 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6749 i40e_dev_handle_vfr_event(dev);
6751 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6752 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6753 i40e_dev_handle_aq_msg(dev);
6757 /* Enable interrupt */
6758 i40e_pf_enable_irq0(hw);
6759 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6760 i40e_dev_alarm_handler, dev);
6764 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6765 struct i40e_macvlan_filter *filter,
6768 int ele_num, ele_buff_size;
6769 int num, actual_num, i;
6771 int ret = I40E_SUCCESS;
6772 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6773 struct i40e_aqc_add_macvlan_element_data *req_list;
6775 if (filter == NULL || total == 0)
6776 return I40E_ERR_PARAM;
6777 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6778 ele_buff_size = hw->aq.asq_buf_size;
6780 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6781 if (req_list == NULL) {
6782 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6783 return I40E_ERR_NO_MEMORY;
6788 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6789 memset(req_list, 0, ele_buff_size);
6791 for (i = 0; i < actual_num; i++) {
6792 rte_memcpy(req_list[i].mac_addr,
6793 &filter[num + i].macaddr, ETH_ADDR_LEN);
6794 req_list[i].vlan_tag =
6795 rte_cpu_to_le_16(filter[num + i].vlan_id);
6797 switch (filter[num + i].filter_type) {
6798 case RTE_MAC_PERFECT_MATCH:
6799 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6800 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6802 case RTE_MACVLAN_PERFECT_MATCH:
6803 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6805 case RTE_MAC_HASH_MATCH:
6806 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6807 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6809 case RTE_MACVLAN_HASH_MATCH:
6810 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6813 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6814 ret = I40E_ERR_PARAM;
6818 req_list[i].queue_number = 0;
6820 req_list[i].flags = rte_cpu_to_le_16(flags);
6823 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6825 if (ret != I40E_SUCCESS) {
6826 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6830 } while (num < total);
6838 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6839 struct i40e_macvlan_filter *filter,
6842 int ele_num, ele_buff_size;
6843 int num, actual_num, i;
6845 int ret = I40E_SUCCESS;
6846 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6847 struct i40e_aqc_remove_macvlan_element_data *req_list;
6849 if (filter == NULL || total == 0)
6850 return I40E_ERR_PARAM;
6852 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6853 ele_buff_size = hw->aq.asq_buf_size;
6855 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6856 if (req_list == NULL) {
6857 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6858 return I40E_ERR_NO_MEMORY;
6863 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6864 memset(req_list, 0, ele_buff_size);
6866 for (i = 0; i < actual_num; i++) {
6867 rte_memcpy(req_list[i].mac_addr,
6868 &filter[num + i].macaddr, ETH_ADDR_LEN);
6869 req_list[i].vlan_tag =
6870 rte_cpu_to_le_16(filter[num + i].vlan_id);
6872 switch (filter[num + i].filter_type) {
6873 case RTE_MAC_PERFECT_MATCH:
6874 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6875 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6877 case RTE_MACVLAN_PERFECT_MATCH:
6878 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6880 case RTE_MAC_HASH_MATCH:
6881 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6882 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6884 case RTE_MACVLAN_HASH_MATCH:
6885 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6888 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6889 ret = I40E_ERR_PARAM;
6892 req_list[i].flags = rte_cpu_to_le_16(flags);
6895 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6897 if (ret != I40E_SUCCESS) {
6898 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6902 } while (num < total);
6909 /* Find out specific MAC filter */
6910 static struct i40e_mac_filter *
6911 i40e_find_mac_filter(struct i40e_vsi *vsi,
6912 struct rte_ether_addr *macaddr)
6914 struct i40e_mac_filter *f;
6916 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6917 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6925 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6928 uint32_t vid_idx, vid_bit;
6930 if (vlan_id > ETH_VLAN_ID_MAX)
6933 vid_idx = I40E_VFTA_IDX(vlan_id);
6934 vid_bit = I40E_VFTA_BIT(vlan_id);
6936 if (vsi->vfta[vid_idx] & vid_bit)
6943 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6944 uint16_t vlan_id, bool on)
6946 uint32_t vid_idx, vid_bit;
6948 vid_idx = I40E_VFTA_IDX(vlan_id);
6949 vid_bit = I40E_VFTA_BIT(vlan_id);
6952 vsi->vfta[vid_idx] |= vid_bit;
6954 vsi->vfta[vid_idx] &= ~vid_bit;
6958 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6959 uint16_t vlan_id, bool on)
6961 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6962 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6965 if (vlan_id > ETH_VLAN_ID_MAX)
6968 i40e_store_vlan_filter(vsi, vlan_id, on);
6970 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6973 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6976 ret = i40e_aq_add_vlan(hw, vsi->seid,
6977 &vlan_data, 1, NULL);
6978 if (ret != I40E_SUCCESS)
6979 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6981 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6982 &vlan_data, 1, NULL);
6983 if (ret != I40E_SUCCESS)
6985 "Failed to remove vlan filter");
6990 * Find all vlan options for specific mac addr,
6991 * return with actual vlan found.
6994 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6995 struct i40e_macvlan_filter *mv_f,
6996 int num, struct rte_ether_addr *addr)
7002 * Not to use i40e_find_vlan_filter to decrease the loop time,
7003 * although the code looks complex.
7005 if (num < vsi->vlan_num)
7006 return I40E_ERR_PARAM;
7009 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7011 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7012 if (vsi->vfta[j] & (1 << k)) {
7015 "vlan number doesn't match");
7016 return I40E_ERR_PARAM;
7018 rte_memcpy(&mv_f[i].macaddr,
7019 addr, ETH_ADDR_LEN);
7021 j * I40E_UINT32_BIT_SIZE + k;
7027 return I40E_SUCCESS;
7031 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7032 struct i40e_macvlan_filter *mv_f,
7037 struct i40e_mac_filter *f;
7039 if (num < vsi->mac_num)
7040 return I40E_ERR_PARAM;
7042 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7044 PMD_DRV_LOG(ERR, "buffer number not match");
7045 return I40E_ERR_PARAM;
7047 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7049 mv_f[i].vlan_id = vlan;
7050 mv_f[i].filter_type = f->mac_info.filter_type;
7054 return I40E_SUCCESS;
7058 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7061 struct i40e_mac_filter *f;
7062 struct i40e_macvlan_filter *mv_f;
7063 int ret = I40E_SUCCESS;
7065 if (vsi == NULL || vsi->mac_num == 0)
7066 return I40E_ERR_PARAM;
7068 /* Case that no vlan is set */
7069 if (vsi->vlan_num == 0)
7072 num = vsi->mac_num * vsi->vlan_num;
7074 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7076 PMD_DRV_LOG(ERR, "failed to allocate memory");
7077 return I40E_ERR_NO_MEMORY;
7081 if (vsi->vlan_num == 0) {
7082 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7083 rte_memcpy(&mv_f[i].macaddr,
7084 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7085 mv_f[i].filter_type = f->mac_info.filter_type;
7086 mv_f[i].vlan_id = 0;
7090 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7091 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7092 vsi->vlan_num, &f->mac_info.mac_addr);
7093 if (ret != I40E_SUCCESS)
7095 for (j = i; j < i + vsi->vlan_num; j++)
7096 mv_f[j].filter_type = f->mac_info.filter_type;
7101 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7109 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7111 struct i40e_macvlan_filter *mv_f;
7113 int ret = I40E_SUCCESS;
7115 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7116 return I40E_ERR_PARAM;
7118 /* If it's already set, just return */
7119 if (i40e_find_vlan_filter(vsi,vlan))
7120 return I40E_SUCCESS;
7122 mac_num = vsi->mac_num;
7125 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7126 return I40E_ERR_PARAM;
7129 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7132 PMD_DRV_LOG(ERR, "failed to allocate memory");
7133 return I40E_ERR_NO_MEMORY;
7136 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7138 if (ret != I40E_SUCCESS)
7141 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7143 if (ret != I40E_SUCCESS)
7146 i40e_set_vlan_filter(vsi, vlan, 1);
7156 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7158 struct i40e_macvlan_filter *mv_f;
7160 int ret = I40E_SUCCESS;
7163 * Vlan 0 is the generic filter for untagged packets
7164 * and can't be removed.
7166 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7167 return I40E_ERR_PARAM;
7169 /* If can't find it, just return */
7170 if (!i40e_find_vlan_filter(vsi, vlan))
7171 return I40E_ERR_PARAM;
7173 mac_num = vsi->mac_num;
7176 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7177 return I40E_ERR_PARAM;
7180 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7183 PMD_DRV_LOG(ERR, "failed to allocate memory");
7184 return I40E_ERR_NO_MEMORY;
7187 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7189 if (ret != I40E_SUCCESS)
7192 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7194 if (ret != I40E_SUCCESS)
7197 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7198 if (vsi->vlan_num == 1) {
7199 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7200 if (ret != I40E_SUCCESS)
7203 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7204 if (ret != I40E_SUCCESS)
7208 i40e_set_vlan_filter(vsi, vlan, 0);
7218 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7220 struct i40e_mac_filter *f;
7221 struct i40e_macvlan_filter *mv_f;
7222 int i, vlan_num = 0;
7223 int ret = I40E_SUCCESS;
7225 /* If it's add and we've config it, return */
7226 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7228 return I40E_SUCCESS;
7229 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7230 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7233 * If vlan_num is 0, that's the first time to add mac,
7234 * set mask for vlan_id 0.
7236 if (vsi->vlan_num == 0) {
7237 i40e_set_vlan_filter(vsi, 0, 1);
7240 vlan_num = vsi->vlan_num;
7241 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7242 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7245 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7247 PMD_DRV_LOG(ERR, "failed to allocate memory");
7248 return I40E_ERR_NO_MEMORY;
7251 for (i = 0; i < vlan_num; i++) {
7252 mv_f[i].filter_type = mac_filter->filter_type;
7253 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7257 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7258 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7259 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7260 &mac_filter->mac_addr);
7261 if (ret != I40E_SUCCESS)
7265 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7266 if (ret != I40E_SUCCESS)
7269 /* Add the mac addr into mac list */
7270 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7272 PMD_DRV_LOG(ERR, "failed to allocate memory");
7273 ret = I40E_ERR_NO_MEMORY;
7276 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7278 f->mac_info.filter_type = mac_filter->filter_type;
7279 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7290 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7292 struct i40e_mac_filter *f;
7293 struct i40e_macvlan_filter *mv_f;
7295 enum rte_mac_filter_type filter_type;
7296 int ret = I40E_SUCCESS;
7298 /* Can't find it, return an error */
7299 f = i40e_find_mac_filter(vsi, addr);
7301 return I40E_ERR_PARAM;
7303 vlan_num = vsi->vlan_num;
7304 filter_type = f->mac_info.filter_type;
7305 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7306 filter_type == RTE_MACVLAN_HASH_MATCH) {
7307 if (vlan_num == 0) {
7308 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7309 return I40E_ERR_PARAM;
7311 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7312 filter_type == RTE_MAC_HASH_MATCH)
7315 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7317 PMD_DRV_LOG(ERR, "failed to allocate memory");
7318 return I40E_ERR_NO_MEMORY;
7321 for (i = 0; i < vlan_num; i++) {
7322 mv_f[i].filter_type = filter_type;
7323 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7326 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7327 filter_type == RTE_MACVLAN_HASH_MATCH) {
7328 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7329 if (ret != I40E_SUCCESS)
7333 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7334 if (ret != I40E_SUCCESS)
7337 /* Remove the mac addr into mac list */
7338 TAILQ_REMOVE(&vsi->mac_list, f, next);
7348 /* Configure hash enable flags for RSS */
7350 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7358 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7359 if (flags & (1ULL << i))
7360 hena |= adapter->pctypes_tbl[i];
7366 /* Parse the hash enable flags */
7368 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7370 uint64_t rss_hf = 0;
7376 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7377 if (flags & adapter->pctypes_tbl[i])
7378 rss_hf |= (1ULL << i);
7385 i40e_pf_disable_rss(struct i40e_pf *pf)
7387 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7389 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7390 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7391 I40E_WRITE_FLUSH(hw);
7395 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7397 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7398 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7399 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7400 I40E_VFQF_HKEY_MAX_INDEX :
7401 I40E_PFQF_HKEY_MAX_INDEX;
7404 if (!key || key_len == 0) {
7405 PMD_DRV_LOG(DEBUG, "No key to be configured");
7407 } else if (key_len != (key_idx + 1) *
7409 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7413 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7414 struct i40e_aqc_get_set_rss_key_data *key_dw =
7415 (struct i40e_aqc_get_set_rss_key_data *)key;
7417 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7419 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7421 uint32_t *hash_key = (uint32_t *)key;
7424 if (vsi->type == I40E_VSI_SRIOV) {
7425 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7428 I40E_VFQF_HKEY1(i, vsi->user_param),
7432 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7433 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7436 I40E_WRITE_FLUSH(hw);
7443 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7445 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7446 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7450 if (!key || !key_len)
7453 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7454 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7455 (struct i40e_aqc_get_set_rss_key_data *)key);
7457 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7461 uint32_t *key_dw = (uint32_t *)key;
7464 if (vsi->type == I40E_VSI_SRIOV) {
7465 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7466 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7467 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7469 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7472 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7473 reg = I40E_PFQF_HKEY(i);
7474 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7476 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7484 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7486 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7490 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7491 rss_conf->rss_key_len);
7495 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7496 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7497 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7498 I40E_WRITE_FLUSH(hw);
7504 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7505 struct rte_eth_rss_conf *rss_conf)
7507 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7508 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7509 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7512 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7513 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7515 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7516 if (rss_hf != 0) /* Enable RSS */
7518 return 0; /* Nothing to do */
7521 if (rss_hf == 0) /* Disable RSS */
7524 return i40e_hw_rss_hash_set(pf, rss_conf);
7528 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7529 struct rte_eth_rss_conf *rss_conf)
7531 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7532 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7539 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7540 &rss_conf->rss_key_len);
7544 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7545 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7546 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7552 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7554 switch (filter_type) {
7555 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7556 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7558 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7559 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7561 case RTE_TUNNEL_FILTER_IMAC_TENID:
7562 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7564 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7565 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7567 case ETH_TUNNEL_FILTER_IMAC:
7568 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7570 case ETH_TUNNEL_FILTER_OIP:
7571 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7573 case ETH_TUNNEL_FILTER_IIP:
7574 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7577 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7584 /* Convert tunnel filter structure */
7586 i40e_tunnel_filter_convert(
7587 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7588 struct i40e_tunnel_filter *tunnel_filter)
7590 rte_ether_addr_copy((struct rte_ether_addr *)
7591 &cld_filter->element.outer_mac,
7592 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7593 rte_ether_addr_copy((struct rte_ether_addr *)
7594 &cld_filter->element.inner_mac,
7595 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7596 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7597 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7598 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7599 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7600 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7602 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7603 tunnel_filter->input.flags = cld_filter->element.flags;
7604 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7605 tunnel_filter->queue = cld_filter->element.queue_number;
7606 rte_memcpy(tunnel_filter->input.general_fields,
7607 cld_filter->general_fields,
7608 sizeof(cld_filter->general_fields));
7613 /* Check if there exists the tunnel filter */
7614 struct i40e_tunnel_filter *
7615 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7616 const struct i40e_tunnel_filter_input *input)
7620 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7624 return tunnel_rule->hash_map[ret];
7627 /* Add a tunnel filter into the SW list */
7629 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7630 struct i40e_tunnel_filter *tunnel_filter)
7632 struct i40e_tunnel_rule *rule = &pf->tunnel;
7635 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7638 "Failed to insert tunnel filter to hash table %d!",
7642 rule->hash_map[ret] = tunnel_filter;
7644 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7649 /* Delete a tunnel filter from the SW list */
7651 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7652 struct i40e_tunnel_filter_input *input)
7654 struct i40e_tunnel_rule *rule = &pf->tunnel;
7655 struct i40e_tunnel_filter *tunnel_filter;
7658 ret = rte_hash_del_key(rule->hash_table, input);
7661 "Failed to delete tunnel filter to hash table %d!",
7665 tunnel_filter = rule->hash_map[ret];
7666 rule->hash_map[ret] = NULL;
7668 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7669 rte_free(tunnel_filter);
7675 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7676 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7680 uint32_t ipv4_addr, ipv4_addr_le;
7681 uint8_t i, tun_type = 0;
7682 /* internal varialbe to convert ipv6 byte order */
7683 uint32_t convert_ipv6[4];
7685 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7686 struct i40e_vsi *vsi = pf->main_vsi;
7687 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7688 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7689 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7690 struct i40e_tunnel_filter *tunnel, *node;
7691 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7693 cld_filter = rte_zmalloc("tunnel_filter",
7694 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7697 if (NULL == cld_filter) {
7698 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7701 pfilter = cld_filter;
7703 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7704 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7705 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7706 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7708 pfilter->element.inner_vlan =
7709 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7710 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7711 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7712 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7713 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7714 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7716 sizeof(pfilter->element.ipaddr.v4.data));
7718 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7719 for (i = 0; i < 4; i++) {
7721 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7723 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7725 sizeof(pfilter->element.ipaddr.v6.data));
7728 /* check tunneled type */
7729 switch (tunnel_filter->tunnel_type) {
7730 case RTE_TUNNEL_TYPE_VXLAN:
7731 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7733 case RTE_TUNNEL_TYPE_NVGRE:
7734 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7736 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7737 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7739 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7740 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7743 /* Other tunnel types is not supported. */
7744 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7745 rte_free(cld_filter);
7749 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7750 &pfilter->element.flags);
7752 rte_free(cld_filter);
7756 pfilter->element.flags |= rte_cpu_to_le_16(
7757 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7758 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7759 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7760 pfilter->element.queue_number =
7761 rte_cpu_to_le_16(tunnel_filter->queue_id);
7763 /* Check if there is the filter in SW list */
7764 memset(&check_filter, 0, sizeof(check_filter));
7765 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7766 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7768 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7769 rte_free(cld_filter);
7773 if (!add && !node) {
7774 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7775 rte_free(cld_filter);
7780 ret = i40e_aq_add_cloud_filters(hw,
7781 vsi->seid, &cld_filter->element, 1);
7783 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7784 rte_free(cld_filter);
7787 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7788 if (tunnel == NULL) {
7789 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7790 rte_free(cld_filter);
7794 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7795 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7799 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7800 &cld_filter->element, 1);
7802 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7803 rte_free(cld_filter);
7806 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7809 rte_free(cld_filter);
7813 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7814 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7815 #define I40E_TR_GENEVE_KEY_MASK 0x8
7816 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7817 #define I40E_TR_GRE_KEY_MASK 0x400
7818 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7819 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7822 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7824 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7825 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7826 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7827 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7828 enum i40e_status_code status = I40E_SUCCESS;
7830 if (pf->support_multi_driver) {
7831 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7832 return I40E_NOT_SUPPORTED;
7835 memset(&filter_replace, 0,
7836 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7837 memset(&filter_replace_buf, 0,
7838 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7840 /* create L1 filter */
7841 filter_replace.old_filter_type =
7842 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7843 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7844 filter_replace.tr_bit = 0;
7846 /* Prepare the buffer, 3 entries */
7847 filter_replace_buf.data[0] =
7848 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7849 filter_replace_buf.data[0] |=
7850 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7851 filter_replace_buf.data[2] = 0xFF;
7852 filter_replace_buf.data[3] = 0xFF;
7853 filter_replace_buf.data[4] =
7854 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7855 filter_replace_buf.data[4] |=
7856 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7857 filter_replace_buf.data[7] = 0xF0;
7858 filter_replace_buf.data[8]
7859 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7860 filter_replace_buf.data[8] |=
7861 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7862 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7863 I40E_TR_GENEVE_KEY_MASK |
7864 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7865 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7866 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7867 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7869 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7870 &filter_replace_buf);
7871 if (!status && (filter_replace.old_filter_type !=
7872 filter_replace.new_filter_type))
7873 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7874 " original: 0x%x, new: 0x%x",
7876 filter_replace.old_filter_type,
7877 filter_replace.new_filter_type);
7883 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7885 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7886 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7887 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7888 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7889 enum i40e_status_code status = I40E_SUCCESS;
7891 if (pf->support_multi_driver) {
7892 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7893 return I40E_NOT_SUPPORTED;
7897 memset(&filter_replace, 0,
7898 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7899 memset(&filter_replace_buf, 0,
7900 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7901 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7902 I40E_AQC_MIRROR_CLOUD_FILTER;
7903 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7904 filter_replace.new_filter_type =
7905 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7906 /* Prepare the buffer, 2 entries */
7907 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7908 filter_replace_buf.data[0] |=
7909 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7910 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7911 filter_replace_buf.data[4] |=
7912 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7913 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7914 &filter_replace_buf);
7917 if (filter_replace.old_filter_type !=
7918 filter_replace.new_filter_type)
7919 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7920 " original: 0x%x, new: 0x%x",
7922 filter_replace.old_filter_type,
7923 filter_replace.new_filter_type);
7926 memset(&filter_replace, 0,
7927 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7928 memset(&filter_replace_buf, 0,
7929 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7931 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7932 I40E_AQC_MIRROR_CLOUD_FILTER;
7933 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7934 filter_replace.new_filter_type =
7935 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7936 /* Prepare the buffer, 2 entries */
7937 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7938 filter_replace_buf.data[0] |=
7939 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7940 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7941 filter_replace_buf.data[4] |=
7942 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7944 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7945 &filter_replace_buf);
7946 if (!status && (filter_replace.old_filter_type !=
7947 filter_replace.new_filter_type))
7948 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7949 " original: 0x%x, new: 0x%x",
7951 filter_replace.old_filter_type,
7952 filter_replace.new_filter_type);
7957 static enum i40e_status_code
7958 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7960 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7961 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7962 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7963 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7964 enum i40e_status_code status = I40E_SUCCESS;
7966 if (pf->support_multi_driver) {
7967 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7968 return I40E_NOT_SUPPORTED;
7972 memset(&filter_replace, 0,
7973 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7974 memset(&filter_replace_buf, 0,
7975 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7976 /* create L1 filter */
7977 filter_replace.old_filter_type =
7978 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7979 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7980 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7981 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7982 /* Prepare the buffer, 2 entries */
7983 filter_replace_buf.data[0] =
7984 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7985 filter_replace_buf.data[0] |=
7986 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7987 filter_replace_buf.data[2] = 0xFF;
7988 filter_replace_buf.data[3] = 0xFF;
7989 filter_replace_buf.data[4] =
7990 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7991 filter_replace_buf.data[4] |=
7992 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7993 filter_replace_buf.data[6] = 0xFF;
7994 filter_replace_buf.data[7] = 0xFF;
7995 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7996 &filter_replace_buf);
7999 if (filter_replace.old_filter_type !=
8000 filter_replace.new_filter_type)
8001 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8002 " original: 0x%x, new: 0x%x",
8004 filter_replace.old_filter_type,
8005 filter_replace.new_filter_type);
8008 memset(&filter_replace, 0,
8009 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8010 memset(&filter_replace_buf, 0,
8011 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8012 /* create L1 filter */
8013 filter_replace.old_filter_type =
8014 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8015 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8016 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8017 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8018 /* Prepare the buffer, 2 entries */
8019 filter_replace_buf.data[0] =
8020 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8021 filter_replace_buf.data[0] |=
8022 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8023 filter_replace_buf.data[2] = 0xFF;
8024 filter_replace_buf.data[3] = 0xFF;
8025 filter_replace_buf.data[4] =
8026 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8027 filter_replace_buf.data[4] |=
8028 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8029 filter_replace_buf.data[6] = 0xFF;
8030 filter_replace_buf.data[7] = 0xFF;
8032 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8033 &filter_replace_buf);
8034 if (!status && (filter_replace.old_filter_type !=
8035 filter_replace.new_filter_type))
8036 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8037 " original: 0x%x, new: 0x%x",
8039 filter_replace.old_filter_type,
8040 filter_replace.new_filter_type);
8046 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8048 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8049 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8050 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8051 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8052 enum i40e_status_code status = I40E_SUCCESS;
8054 if (pf->support_multi_driver) {
8055 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8056 return I40E_NOT_SUPPORTED;
8060 memset(&filter_replace, 0,
8061 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8062 memset(&filter_replace_buf, 0,
8063 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8064 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8065 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8066 filter_replace.new_filter_type =
8067 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8068 /* Prepare the buffer, 2 entries */
8069 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8070 filter_replace_buf.data[0] |=
8071 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8072 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8073 filter_replace_buf.data[4] |=
8074 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8075 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8076 &filter_replace_buf);
8079 if (filter_replace.old_filter_type !=
8080 filter_replace.new_filter_type)
8081 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8082 " original: 0x%x, new: 0x%x",
8084 filter_replace.old_filter_type,
8085 filter_replace.new_filter_type);
8088 memset(&filter_replace, 0,
8089 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8090 memset(&filter_replace_buf, 0,
8091 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8092 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8093 filter_replace.old_filter_type =
8094 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8095 filter_replace.new_filter_type =
8096 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8097 /* Prepare the buffer, 2 entries */
8098 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8099 filter_replace_buf.data[0] |=
8100 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8101 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8102 filter_replace_buf.data[4] |=
8103 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8105 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8106 &filter_replace_buf);
8107 if (!status && (filter_replace.old_filter_type !=
8108 filter_replace.new_filter_type))
8109 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8110 " original: 0x%x, new: 0x%x",
8112 filter_replace.old_filter_type,
8113 filter_replace.new_filter_type);
8119 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8120 struct i40e_tunnel_filter_conf *tunnel_filter,
8124 uint32_t ipv4_addr, ipv4_addr_le;
8125 uint8_t i, tun_type = 0;
8126 /* internal variable to convert ipv6 byte order */
8127 uint32_t convert_ipv6[4];
8129 struct i40e_pf_vf *vf = NULL;
8130 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8131 struct i40e_vsi *vsi;
8132 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8133 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8134 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8135 struct i40e_tunnel_filter *tunnel, *node;
8136 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8138 bool big_buffer = 0;
8140 cld_filter = rte_zmalloc("tunnel_filter",
8141 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8144 if (cld_filter == NULL) {
8145 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8148 pfilter = cld_filter;
8150 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8151 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8152 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8153 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8155 pfilter->element.inner_vlan =
8156 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8157 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8158 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8159 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8160 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8161 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8163 sizeof(pfilter->element.ipaddr.v4.data));
8165 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8166 for (i = 0; i < 4; i++) {
8168 rte_cpu_to_le_32(rte_be_to_cpu_32(
8169 tunnel_filter->ip_addr.ipv6_addr[i]));
8171 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8173 sizeof(pfilter->element.ipaddr.v6.data));
8176 /* check tunneled type */
8177 switch (tunnel_filter->tunnel_type) {
8178 case I40E_TUNNEL_TYPE_VXLAN:
8179 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8181 case I40E_TUNNEL_TYPE_NVGRE:
8182 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8184 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8185 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8187 case I40E_TUNNEL_TYPE_MPLSoUDP:
8188 if (!pf->mpls_replace_flag) {
8189 i40e_replace_mpls_l1_filter(pf);
8190 i40e_replace_mpls_cloud_filter(pf);
8191 pf->mpls_replace_flag = 1;
8193 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8194 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8196 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8197 (teid_le & 0xF) << 12;
8198 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8201 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8203 case I40E_TUNNEL_TYPE_MPLSoGRE:
8204 if (!pf->mpls_replace_flag) {
8205 i40e_replace_mpls_l1_filter(pf);
8206 i40e_replace_mpls_cloud_filter(pf);
8207 pf->mpls_replace_flag = 1;
8209 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8210 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8212 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8213 (teid_le & 0xF) << 12;
8214 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8217 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8219 case I40E_TUNNEL_TYPE_GTPC:
8220 if (!pf->gtp_replace_flag) {
8221 i40e_replace_gtp_l1_filter(pf);
8222 i40e_replace_gtp_cloud_filter(pf);
8223 pf->gtp_replace_flag = 1;
8225 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8226 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8227 (teid_le >> 16) & 0xFFFF;
8228 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8230 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8234 case I40E_TUNNEL_TYPE_GTPU:
8235 if (!pf->gtp_replace_flag) {
8236 i40e_replace_gtp_l1_filter(pf);
8237 i40e_replace_gtp_cloud_filter(pf);
8238 pf->gtp_replace_flag = 1;
8240 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8241 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8242 (teid_le >> 16) & 0xFFFF;
8243 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8245 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8249 case I40E_TUNNEL_TYPE_QINQ:
8250 if (!pf->qinq_replace_flag) {
8251 ret = i40e_cloud_filter_qinq_create(pf);
8254 "QinQ tunnel filter already created.");
8255 pf->qinq_replace_flag = 1;
8257 /* Add in the General fields the values of
8258 * the Outer and Inner VLAN
8259 * Big Buffer should be set, see changes in
8260 * i40e_aq_add_cloud_filters
8262 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8263 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8267 /* Other tunnel types is not supported. */
8268 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8269 rte_free(cld_filter);
8273 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8274 pfilter->element.flags =
8275 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8276 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8277 pfilter->element.flags =
8278 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8279 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8280 pfilter->element.flags =
8281 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8282 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8283 pfilter->element.flags =
8284 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8285 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8286 pfilter->element.flags |=
8287 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8289 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8290 &pfilter->element.flags);
8292 rte_free(cld_filter);
8297 pfilter->element.flags |= rte_cpu_to_le_16(
8298 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8299 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8300 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8301 pfilter->element.queue_number =
8302 rte_cpu_to_le_16(tunnel_filter->queue_id);
8304 if (!tunnel_filter->is_to_vf)
8307 if (tunnel_filter->vf_id >= pf->vf_num) {
8308 PMD_DRV_LOG(ERR, "Invalid argument.");
8309 rte_free(cld_filter);
8312 vf = &pf->vfs[tunnel_filter->vf_id];
8316 /* Check if there is the filter in SW list */
8317 memset(&check_filter, 0, sizeof(check_filter));
8318 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8319 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8320 check_filter.vf_id = tunnel_filter->vf_id;
8321 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8323 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8324 rte_free(cld_filter);
8328 if (!add && !node) {
8329 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8330 rte_free(cld_filter);
8336 ret = i40e_aq_add_cloud_filters_bb(hw,
8337 vsi->seid, cld_filter, 1);
8339 ret = i40e_aq_add_cloud_filters(hw,
8340 vsi->seid, &cld_filter->element, 1);
8342 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8343 rte_free(cld_filter);
8346 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8347 if (tunnel == NULL) {
8348 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8349 rte_free(cld_filter);
8353 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8354 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8359 ret = i40e_aq_rem_cloud_filters_bb(
8360 hw, vsi->seid, cld_filter, 1);
8362 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8363 &cld_filter->element, 1);
8365 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8366 rte_free(cld_filter);
8369 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8372 rte_free(cld_filter);
8377 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8381 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8382 if (pf->vxlan_ports[i] == port)
8390 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8394 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8396 idx = i40e_get_vxlan_port_idx(pf, port);
8398 /* Check if port already exists */
8400 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8404 /* Now check if there is space to add the new port */
8405 idx = i40e_get_vxlan_port_idx(pf, 0);
8408 "Maximum number of UDP ports reached, not adding port %d",
8413 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8416 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8420 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8423 /* New port: add it and mark its index in the bitmap */
8424 pf->vxlan_ports[idx] = port;
8425 pf->vxlan_bitmap |= (1 << idx);
8427 if (!(pf->flags & I40E_FLAG_VXLAN))
8428 pf->flags |= I40E_FLAG_VXLAN;
8434 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8437 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8439 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8440 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8444 idx = i40e_get_vxlan_port_idx(pf, port);
8447 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8451 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8452 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8456 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8459 pf->vxlan_ports[idx] = 0;
8460 pf->vxlan_bitmap &= ~(1 << idx);
8462 if (!pf->vxlan_bitmap)
8463 pf->flags &= ~I40E_FLAG_VXLAN;
8468 /* Add UDP tunneling port */
8470 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8471 struct rte_eth_udp_tunnel *udp_tunnel)
8474 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8476 if (udp_tunnel == NULL)
8479 switch (udp_tunnel->prot_type) {
8480 case RTE_TUNNEL_TYPE_VXLAN:
8481 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8482 I40E_AQC_TUNNEL_TYPE_VXLAN);
8484 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8485 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8486 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8488 case RTE_TUNNEL_TYPE_GENEVE:
8489 case RTE_TUNNEL_TYPE_TEREDO:
8490 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8495 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8503 /* Remove UDP tunneling port */
8505 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8506 struct rte_eth_udp_tunnel *udp_tunnel)
8509 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8511 if (udp_tunnel == NULL)
8514 switch (udp_tunnel->prot_type) {
8515 case RTE_TUNNEL_TYPE_VXLAN:
8516 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8517 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8519 case RTE_TUNNEL_TYPE_GENEVE:
8520 case RTE_TUNNEL_TYPE_TEREDO:
8521 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8525 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8533 /* Calculate the maximum number of contiguous PF queues that are configured */
8535 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8537 struct rte_eth_dev_data *data = pf->dev_data;
8539 struct i40e_rx_queue *rxq;
8542 for (i = 0; i < pf->lan_nb_qps; i++) {
8543 rxq = data->rx_queues[i];
8544 if (rxq && rxq->q_set)
8555 i40e_pf_config_rss(struct i40e_pf *pf)
8557 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8558 struct rte_eth_rss_conf rss_conf;
8559 uint32_t i, lut = 0;
8563 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8564 * It's necessary to calculate the actual PF queues that are configured.
8566 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8567 num = i40e_pf_calc_configured_queues_num(pf);
8569 num = pf->dev_data->nb_rx_queues;
8571 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8572 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8576 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8580 if (pf->adapter->rss_reta_updated == 0) {
8581 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8584 lut = (lut << 8) | (j & ((0x1 <<
8585 hw->func_caps.rss_table_entry_width) - 1));
8587 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8592 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8593 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8594 i40e_pf_disable_rss(pf);
8597 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8598 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8599 /* Random default keys */
8600 static uint32_t rss_key_default[] = {0x6b793944,
8601 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8602 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8603 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8605 rss_conf.rss_key = (uint8_t *)rss_key_default;
8606 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8610 return i40e_hw_rss_hash_set(pf, &rss_conf);
8614 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8615 struct rte_eth_tunnel_filter_conf *filter)
8617 if (pf == NULL || filter == NULL) {
8618 PMD_DRV_LOG(ERR, "Invalid parameter");
8622 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8623 PMD_DRV_LOG(ERR, "Invalid queue ID");
8627 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8628 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8632 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8633 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8634 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8638 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8639 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8640 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8647 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8648 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8650 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8652 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8656 if (pf->support_multi_driver) {
8657 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8661 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8662 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8665 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8666 } else if (len == 4) {
8667 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8669 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8674 ret = i40e_aq_debug_write_global_register(hw,
8675 I40E_GL_PRS_FVBM(2),
8679 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8680 "with value 0x%08x",
8681 I40E_GL_PRS_FVBM(2), reg);
8685 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8686 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8692 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8699 switch (cfg->cfg_type) {
8700 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8701 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8704 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8712 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8713 enum rte_filter_op filter_op,
8716 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8717 int ret = I40E_ERR_PARAM;
8719 switch (filter_op) {
8720 case RTE_ETH_FILTER_SET:
8721 ret = i40e_dev_global_config_set(hw,
8722 (struct rte_eth_global_cfg *)arg);
8725 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8733 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8734 enum rte_filter_op filter_op,
8737 struct rte_eth_tunnel_filter_conf *filter;
8738 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8739 int ret = I40E_SUCCESS;
8741 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8743 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8744 return I40E_ERR_PARAM;
8746 switch (filter_op) {
8747 case RTE_ETH_FILTER_NOP:
8748 if (!(pf->flags & I40E_FLAG_VXLAN))
8749 ret = I40E_NOT_SUPPORTED;
8751 case RTE_ETH_FILTER_ADD:
8752 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8754 case RTE_ETH_FILTER_DELETE:
8755 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8758 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8759 ret = I40E_ERR_PARAM;
8767 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8770 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8773 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8774 ret = i40e_pf_config_rss(pf);
8776 i40e_pf_disable_rss(pf);
8781 /* Get the symmetric hash enable configurations per port */
8783 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8785 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8787 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8790 /* Set the symmetric hash enable configurations per port */
8792 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8794 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8797 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8799 "Symmetric hash has already been enabled");
8802 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8804 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8806 "Symmetric hash has already been disabled");
8809 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8811 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8812 I40E_WRITE_FLUSH(hw);
8816 * Get global configurations of hash function type and symmetric hash enable
8817 * per flow type (pctype). Note that global configuration means it affects all
8818 * the ports on the same NIC.
8821 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8822 struct rte_eth_hash_global_conf *g_cfg)
8824 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8828 memset(g_cfg, 0, sizeof(*g_cfg));
8829 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8830 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8831 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8833 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8834 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8835 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8838 * As i40e supports less than 64 flow types, only first 64 bits need to
8841 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8842 g_cfg->valid_bit_mask[i] = 0ULL;
8843 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8846 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8848 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8849 if (!adapter->pctypes_tbl[i])
8851 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8852 j < I40E_FILTER_PCTYPE_MAX; j++) {
8853 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8854 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8855 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8856 g_cfg->sym_hash_enable_mask[0] |=
8867 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8868 const struct rte_eth_hash_global_conf *g_cfg)
8871 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8873 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8874 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8875 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8876 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8882 * As i40e supports less than 64 flow types, only first 64 bits need to
8885 mask0 = g_cfg->valid_bit_mask[0];
8886 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8888 /* Check if any unsupported flow type configured */
8889 if ((mask0 | i40e_mask) ^ i40e_mask)
8892 if (g_cfg->valid_bit_mask[i])
8900 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8906 * Set global configurations of hash function type and symmetric hash enable
8907 * per flow type (pctype). Note any modifying global configuration will affect
8908 * all the ports on the same NIC.
8911 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8912 struct rte_eth_hash_global_conf *g_cfg)
8914 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8915 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8919 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8921 if (pf->support_multi_driver) {
8922 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8926 /* Check the input parameters */
8927 ret = i40e_hash_global_config_check(adapter, g_cfg);
8932 * As i40e supports less than 64 flow types, only first 64 bits need to
8935 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8936 if (mask0 & (1UL << i)) {
8937 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8938 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8940 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8941 j < I40E_FILTER_PCTYPE_MAX; j++) {
8942 if (adapter->pctypes_tbl[i] & (1ULL << j))
8943 i40e_write_global_rx_ctl(hw,
8950 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8951 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8953 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8955 "Hash function already set to Toeplitz");
8958 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8959 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8961 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8963 "Hash function already set to Simple XOR");
8966 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8968 /* Use the default, and keep it as it is */
8971 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8974 I40E_WRITE_FLUSH(hw);
8980 * Valid input sets for hash and flow director filters per PCTYPE
8983 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8984 enum rte_filter_type filter)
8988 static const uint64_t valid_hash_inset_table[] = {
8989 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8990 I40E_INSET_DMAC | I40E_INSET_SMAC |
8991 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8992 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8993 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8994 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8995 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8996 I40E_INSET_FLEX_PAYLOAD,
8997 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8998 I40E_INSET_DMAC | I40E_INSET_SMAC |
8999 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9000 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9001 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9002 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9003 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9004 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9005 I40E_INSET_FLEX_PAYLOAD,
9006 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9007 I40E_INSET_DMAC | I40E_INSET_SMAC |
9008 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9009 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9010 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9011 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9012 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9013 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9014 I40E_INSET_FLEX_PAYLOAD,
9015 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9016 I40E_INSET_DMAC | I40E_INSET_SMAC |
9017 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9018 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9019 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9020 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9021 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9022 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9023 I40E_INSET_FLEX_PAYLOAD,
9024 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9025 I40E_INSET_DMAC | I40E_INSET_SMAC |
9026 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9027 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9028 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9029 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9030 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9031 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9032 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9033 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9034 I40E_INSET_DMAC | I40E_INSET_SMAC |
9035 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9036 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9037 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9038 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9039 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9040 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9041 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9042 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9043 I40E_INSET_DMAC | I40E_INSET_SMAC |
9044 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9045 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9046 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9047 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9048 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9049 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9050 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9051 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9052 I40E_INSET_DMAC | I40E_INSET_SMAC |
9053 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9054 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9055 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9056 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9057 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9058 I40E_INSET_FLEX_PAYLOAD,
9059 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9060 I40E_INSET_DMAC | I40E_INSET_SMAC |
9061 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9062 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9063 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9064 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9065 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9066 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9067 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9068 I40E_INSET_DMAC | I40E_INSET_SMAC |
9069 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9070 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9071 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9072 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9073 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9074 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9075 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9076 I40E_INSET_DMAC | I40E_INSET_SMAC |
9077 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9078 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9079 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9080 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9081 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9082 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9083 I40E_INSET_FLEX_PAYLOAD,
9084 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9085 I40E_INSET_DMAC | I40E_INSET_SMAC |
9086 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9087 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9088 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9089 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9090 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9091 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9092 I40E_INSET_FLEX_PAYLOAD,
9093 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9094 I40E_INSET_DMAC | I40E_INSET_SMAC |
9095 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9096 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9097 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9098 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9099 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9100 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9101 I40E_INSET_FLEX_PAYLOAD,
9102 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9103 I40E_INSET_DMAC | I40E_INSET_SMAC |
9104 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9105 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9106 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9107 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9108 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9109 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9110 I40E_INSET_FLEX_PAYLOAD,
9111 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9112 I40E_INSET_DMAC | I40E_INSET_SMAC |
9113 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9114 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9115 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9116 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9117 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9118 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9119 I40E_INSET_FLEX_PAYLOAD,
9120 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9121 I40E_INSET_DMAC | I40E_INSET_SMAC |
9122 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9123 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9124 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9125 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9126 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9127 I40E_INSET_FLEX_PAYLOAD,
9128 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9129 I40E_INSET_DMAC | I40E_INSET_SMAC |
9130 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9131 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9132 I40E_INSET_FLEX_PAYLOAD,
9136 * Flow director supports only fields defined in
9137 * union rte_eth_fdir_flow.
9139 static const uint64_t valid_fdir_inset_table[] = {
9140 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9141 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9142 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9143 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9144 I40E_INSET_IPV4_TTL,
9145 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9146 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9147 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9148 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9149 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9150 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9151 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9152 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9153 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9154 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9155 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9156 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9157 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9158 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9159 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9160 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9161 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9162 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9163 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9164 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9165 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9166 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9167 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9168 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9169 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9170 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9171 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9172 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9173 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9174 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9176 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9177 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9178 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9179 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9180 I40E_INSET_IPV4_TTL,
9181 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9182 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9183 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9184 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9185 I40E_INSET_IPV6_HOP_LIMIT,
9186 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9187 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9188 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9189 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9190 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9191 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9192 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9193 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9194 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9195 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9196 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9197 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9198 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9199 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9200 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9201 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9202 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9203 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9204 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9205 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9206 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9207 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9208 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9209 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9210 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9211 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9212 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9214 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9215 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9217 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9218 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9219 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9220 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9221 I40E_INSET_IPV6_HOP_LIMIT,
9222 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9223 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9224 I40E_INSET_LAST_ETHER_TYPE,
9227 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9229 if (filter == RTE_ETH_FILTER_HASH)
9230 valid = valid_hash_inset_table[pctype];
9232 valid = valid_fdir_inset_table[pctype];
9238 * Validate if the input set is allowed for a specific PCTYPE
9241 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9242 enum rte_filter_type filter, uint64_t inset)
9246 valid = i40e_get_valid_input_set(pctype, filter);
9247 if (inset & (~valid))
9253 /* default input set fields combination per pctype */
9255 i40e_get_default_input_set(uint16_t pctype)
9257 static const uint64_t default_inset_table[] = {
9258 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9259 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9260 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9261 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9262 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9263 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9264 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9265 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9266 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9267 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9268 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9269 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9270 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9271 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9272 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9273 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9274 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9275 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9276 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9277 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9279 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9280 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9281 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9282 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9283 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9284 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9285 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9286 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9287 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9288 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9289 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9290 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9291 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9292 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9293 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9294 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9295 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9296 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9297 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9298 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9299 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9300 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9302 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9303 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9304 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9305 I40E_INSET_LAST_ETHER_TYPE,
9308 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9311 return default_inset_table[pctype];
9315 * Parse the input set from index to logical bit masks
9318 i40e_parse_input_set(uint64_t *inset,
9319 enum i40e_filter_pctype pctype,
9320 enum rte_eth_input_set_field *field,
9326 static const struct {
9327 enum rte_eth_input_set_field field;
9329 } inset_convert_table[] = {
9330 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9331 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9332 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9333 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9334 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9335 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9336 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9337 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9338 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9339 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9340 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9341 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9342 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9343 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9344 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9345 I40E_INSET_IPV6_NEXT_HDR},
9346 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9347 I40E_INSET_IPV6_HOP_LIMIT},
9348 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9349 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9350 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9351 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9352 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9353 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9354 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9355 I40E_INSET_SCTP_VT},
9356 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9357 I40E_INSET_TUNNEL_DMAC},
9358 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9359 I40E_INSET_VLAN_TUNNEL},
9360 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9361 I40E_INSET_TUNNEL_ID},
9362 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9363 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9364 I40E_INSET_FLEX_PAYLOAD_W1},
9365 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9366 I40E_INSET_FLEX_PAYLOAD_W2},
9367 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9368 I40E_INSET_FLEX_PAYLOAD_W3},
9369 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9370 I40E_INSET_FLEX_PAYLOAD_W4},
9371 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9372 I40E_INSET_FLEX_PAYLOAD_W5},
9373 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9374 I40E_INSET_FLEX_PAYLOAD_W6},
9375 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9376 I40E_INSET_FLEX_PAYLOAD_W7},
9377 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9378 I40E_INSET_FLEX_PAYLOAD_W8},
9381 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9384 /* Only one item allowed for default or all */
9386 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9387 *inset = i40e_get_default_input_set(pctype);
9389 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9390 *inset = I40E_INSET_NONE;
9395 for (i = 0, *inset = 0; i < size; i++) {
9396 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9397 if (field[i] == inset_convert_table[j].field) {
9398 *inset |= inset_convert_table[j].inset;
9403 /* It contains unsupported input set, return immediately */
9404 if (j == RTE_DIM(inset_convert_table))
9412 * Translate the input set from bit masks to register aware bit masks
9416 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9426 static const struct inset_map inset_map_common[] = {
9427 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9428 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9429 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9430 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9431 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9432 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9433 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9434 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9435 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9436 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9437 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9438 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9439 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9440 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9441 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9442 {I40E_INSET_TUNNEL_DMAC,
9443 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9444 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9445 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9446 {I40E_INSET_TUNNEL_SRC_PORT,
9447 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9448 {I40E_INSET_TUNNEL_DST_PORT,
9449 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9450 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9451 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9452 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9453 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9454 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9455 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9456 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9457 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9458 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9461 /* some different registers map in x722*/
9462 static const struct inset_map inset_map_diff_x722[] = {
9463 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9464 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9465 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9466 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9469 static const struct inset_map inset_map_diff_not_x722[] = {
9470 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9471 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9472 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9473 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9479 /* Translate input set to register aware inset */
9480 if (type == I40E_MAC_X722) {
9481 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9482 if (input & inset_map_diff_x722[i].inset)
9483 val |= inset_map_diff_x722[i].inset_reg;
9486 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9487 if (input & inset_map_diff_not_x722[i].inset)
9488 val |= inset_map_diff_not_x722[i].inset_reg;
9492 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9493 if (input & inset_map_common[i].inset)
9494 val |= inset_map_common[i].inset_reg;
9501 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9504 uint64_t inset_need_mask = inset;
9506 static const struct {
9509 } inset_mask_map[] = {
9510 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9511 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9512 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9513 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9514 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9515 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9516 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9517 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9520 if (!inset || !mask || !nb_elem)
9523 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9524 /* Clear the inset bit, if no MASK is required,
9525 * for example proto + ttl
9527 if ((inset & inset_mask_map[i].inset) ==
9528 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9529 inset_need_mask &= ~inset_mask_map[i].inset;
9530 if (!inset_need_mask)
9533 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9534 if ((inset_need_mask & inset_mask_map[i].inset) ==
9535 inset_mask_map[i].inset) {
9536 if (idx >= nb_elem) {
9537 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9540 mask[idx] = inset_mask_map[i].mask;
9549 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9551 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9553 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9555 i40e_write_rx_ctl(hw, addr, val);
9556 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9557 (uint32_t)i40e_read_rx_ctl(hw, addr));
9561 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9563 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9564 struct rte_eth_dev *dev;
9566 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9568 i40e_write_rx_ctl(hw, addr, val);
9569 PMD_DRV_LOG(WARNING,
9570 "i40e device %s changed global register [0x%08x]."
9571 " original: 0x%08x, new: 0x%08x",
9572 dev->device->name, addr, reg,
9573 (uint32_t)i40e_read_rx_ctl(hw, addr));
9578 i40e_filter_input_set_init(struct i40e_pf *pf)
9580 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9581 enum i40e_filter_pctype pctype;
9582 uint64_t input_set, inset_reg;
9583 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9587 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9588 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9589 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9591 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9594 input_set = i40e_get_default_input_set(pctype);
9596 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9597 I40E_INSET_MASK_NUM_REG);
9600 if (pf->support_multi_driver && num > 0) {
9601 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9604 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9607 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9608 (uint32_t)(inset_reg & UINT32_MAX));
9609 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9610 (uint32_t)((inset_reg >>
9611 I40E_32_BIT_WIDTH) & UINT32_MAX));
9612 if (!pf->support_multi_driver) {
9613 i40e_check_write_global_reg(hw,
9614 I40E_GLQF_HASH_INSET(0, pctype),
9615 (uint32_t)(inset_reg & UINT32_MAX));
9616 i40e_check_write_global_reg(hw,
9617 I40E_GLQF_HASH_INSET(1, pctype),
9618 (uint32_t)((inset_reg >>
9619 I40E_32_BIT_WIDTH) & UINT32_MAX));
9621 for (i = 0; i < num; i++) {
9622 i40e_check_write_global_reg(hw,
9623 I40E_GLQF_FD_MSK(i, pctype),
9625 i40e_check_write_global_reg(hw,
9626 I40E_GLQF_HASH_MSK(i, pctype),
9629 /*clear unused mask registers of the pctype */
9630 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9631 i40e_check_write_global_reg(hw,
9632 I40E_GLQF_FD_MSK(i, pctype),
9634 i40e_check_write_global_reg(hw,
9635 I40E_GLQF_HASH_MSK(i, pctype),
9639 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9641 I40E_WRITE_FLUSH(hw);
9643 /* store the default input set */
9644 if (!pf->support_multi_driver)
9645 pf->hash_input_set[pctype] = input_set;
9646 pf->fdir.input_set[pctype] = input_set;
9651 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9652 struct rte_eth_input_set_conf *conf)
9654 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9655 enum i40e_filter_pctype pctype;
9656 uint64_t input_set, inset_reg = 0;
9657 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9661 PMD_DRV_LOG(ERR, "Invalid pointer");
9664 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9665 conf->op != RTE_ETH_INPUT_SET_ADD) {
9666 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9670 if (pf->support_multi_driver) {
9671 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9675 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9676 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9677 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9681 if (hw->mac.type == I40E_MAC_X722) {
9682 /* get translated pctype value in fd pctype register */
9683 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9684 I40E_GLQF_FD_PCTYPES((int)pctype));
9687 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9690 PMD_DRV_LOG(ERR, "Failed to parse input set");
9694 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9695 /* get inset value in register */
9696 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9697 inset_reg <<= I40E_32_BIT_WIDTH;
9698 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9699 input_set |= pf->hash_input_set[pctype];
9701 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9702 I40E_INSET_MASK_NUM_REG);
9706 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9708 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9709 (uint32_t)(inset_reg & UINT32_MAX));
9710 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9711 (uint32_t)((inset_reg >>
9712 I40E_32_BIT_WIDTH) & UINT32_MAX));
9714 for (i = 0; i < num; i++)
9715 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9717 /*clear unused mask registers of the pctype */
9718 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9719 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9721 I40E_WRITE_FLUSH(hw);
9723 pf->hash_input_set[pctype] = input_set;
9728 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9729 struct rte_eth_input_set_conf *conf)
9731 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9732 enum i40e_filter_pctype pctype;
9733 uint64_t input_set, inset_reg = 0;
9734 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9738 PMD_DRV_LOG(ERR, "Invalid pointer");
9741 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9742 conf->op != RTE_ETH_INPUT_SET_ADD) {
9743 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9747 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9749 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9750 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9754 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9757 PMD_DRV_LOG(ERR, "Failed to parse input set");
9761 /* get inset value in register */
9762 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9763 inset_reg <<= I40E_32_BIT_WIDTH;
9764 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9766 /* Can not change the inset reg for flex payload for fdir,
9767 * it is done by writing I40E_PRTQF_FD_FLXINSET
9768 * in i40e_set_flex_mask_on_pctype.
9770 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9771 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9773 input_set |= pf->fdir.input_set[pctype];
9774 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9775 I40E_INSET_MASK_NUM_REG);
9778 if (pf->support_multi_driver && num > 0) {
9779 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9783 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9785 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9786 (uint32_t)(inset_reg & UINT32_MAX));
9787 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9788 (uint32_t)((inset_reg >>
9789 I40E_32_BIT_WIDTH) & UINT32_MAX));
9791 if (!pf->support_multi_driver) {
9792 for (i = 0; i < num; i++)
9793 i40e_check_write_global_reg(hw,
9794 I40E_GLQF_FD_MSK(i, pctype),
9796 /*clear unused mask registers of the pctype */
9797 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9798 i40e_check_write_global_reg(hw,
9799 I40E_GLQF_FD_MSK(i, pctype),
9802 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9804 I40E_WRITE_FLUSH(hw);
9806 pf->fdir.input_set[pctype] = input_set;
9811 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9816 PMD_DRV_LOG(ERR, "Invalid pointer");
9820 switch (info->info_type) {
9821 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9822 i40e_get_symmetric_hash_enable_per_port(hw,
9823 &(info->info.enable));
9825 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9826 ret = i40e_get_hash_filter_global_config(hw,
9827 &(info->info.global_conf));
9830 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9840 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9845 PMD_DRV_LOG(ERR, "Invalid pointer");
9849 switch (info->info_type) {
9850 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9851 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9853 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9854 ret = i40e_set_hash_filter_global_config(hw,
9855 &(info->info.global_conf));
9857 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9858 ret = i40e_hash_filter_inset_select(hw,
9859 &(info->info.input_set_conf));
9863 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9872 /* Operations for hash function */
9874 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9875 enum rte_filter_op filter_op,
9878 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9881 switch (filter_op) {
9882 case RTE_ETH_FILTER_NOP:
9884 case RTE_ETH_FILTER_GET:
9885 ret = i40e_hash_filter_get(hw,
9886 (struct rte_eth_hash_filter_info *)arg);
9888 case RTE_ETH_FILTER_SET:
9889 ret = i40e_hash_filter_set(hw,
9890 (struct rte_eth_hash_filter_info *)arg);
9893 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9902 /* Convert ethertype filter structure */
9904 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9905 struct i40e_ethertype_filter *filter)
9907 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9908 RTE_ETHER_ADDR_LEN);
9909 filter->input.ether_type = input->ether_type;
9910 filter->flags = input->flags;
9911 filter->queue = input->queue;
9916 /* Check if there exists the ehtertype filter */
9917 struct i40e_ethertype_filter *
9918 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9919 const struct i40e_ethertype_filter_input *input)
9923 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9927 return ethertype_rule->hash_map[ret];
9930 /* Add ethertype filter in SW list */
9932 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9933 struct i40e_ethertype_filter *filter)
9935 struct i40e_ethertype_rule *rule = &pf->ethertype;
9938 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9941 "Failed to insert ethertype filter"
9942 " to hash table %d!",
9946 rule->hash_map[ret] = filter;
9948 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9953 /* Delete ethertype filter in SW list */
9955 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9956 struct i40e_ethertype_filter_input *input)
9958 struct i40e_ethertype_rule *rule = &pf->ethertype;
9959 struct i40e_ethertype_filter *filter;
9962 ret = rte_hash_del_key(rule->hash_table, input);
9965 "Failed to delete ethertype filter"
9966 " to hash table %d!",
9970 filter = rule->hash_map[ret];
9971 rule->hash_map[ret] = NULL;
9973 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9980 * Configure ethertype filter, which can director packet by filtering
9981 * with mac address and ether_type or only ether_type
9984 i40e_ethertype_filter_set(struct i40e_pf *pf,
9985 struct rte_eth_ethertype_filter *filter,
9988 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9989 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9990 struct i40e_ethertype_filter *ethertype_filter, *node;
9991 struct i40e_ethertype_filter check_filter;
9992 struct i40e_control_filter_stats stats;
9996 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9997 PMD_DRV_LOG(ERR, "Invalid queue ID");
10000 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10001 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10003 "unsupported ether_type(0x%04x) in control packet filter.",
10004 filter->ether_type);
10007 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10008 PMD_DRV_LOG(WARNING,
10009 "filter vlan ether_type in first tag is not supported.");
10011 /* Check if there is the filter in SW list */
10012 memset(&check_filter, 0, sizeof(check_filter));
10013 i40e_ethertype_filter_convert(filter, &check_filter);
10014 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10015 &check_filter.input);
10017 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10021 if (!add && !node) {
10022 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10026 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10027 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10028 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10029 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10030 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10032 memset(&stats, 0, sizeof(stats));
10033 ret = i40e_aq_add_rem_control_packet_filter(hw,
10034 filter->mac_addr.addr_bytes,
10035 filter->ether_type, flags,
10036 pf->main_vsi->seid,
10037 filter->queue, add, &stats, NULL);
10040 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10041 ret, stats.mac_etype_used, stats.etype_used,
10042 stats.mac_etype_free, stats.etype_free);
10046 /* Add or delete a filter in SW list */
10048 ethertype_filter = rte_zmalloc("ethertype_filter",
10049 sizeof(*ethertype_filter), 0);
10050 if (ethertype_filter == NULL) {
10051 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10055 rte_memcpy(ethertype_filter, &check_filter,
10056 sizeof(check_filter));
10057 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10059 rte_free(ethertype_filter);
10061 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10068 * Handle operations for ethertype filter.
10071 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10072 enum rte_filter_op filter_op,
10075 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10078 if (filter_op == RTE_ETH_FILTER_NOP)
10082 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10087 switch (filter_op) {
10088 case RTE_ETH_FILTER_ADD:
10089 ret = i40e_ethertype_filter_set(pf,
10090 (struct rte_eth_ethertype_filter *)arg,
10093 case RTE_ETH_FILTER_DELETE:
10094 ret = i40e_ethertype_filter_set(pf,
10095 (struct rte_eth_ethertype_filter *)arg,
10099 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10107 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10108 enum rte_filter_type filter_type,
10109 enum rte_filter_op filter_op,
10117 switch (filter_type) {
10118 case RTE_ETH_FILTER_NONE:
10119 /* For global configuration */
10120 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10122 case RTE_ETH_FILTER_HASH:
10123 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10125 case RTE_ETH_FILTER_MACVLAN:
10126 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10128 case RTE_ETH_FILTER_ETHERTYPE:
10129 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10131 case RTE_ETH_FILTER_TUNNEL:
10132 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10134 case RTE_ETH_FILTER_FDIR:
10135 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10137 case RTE_ETH_FILTER_GENERIC:
10138 if (filter_op != RTE_ETH_FILTER_GET)
10140 *(const void **)arg = &i40e_flow_ops;
10143 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10153 * Check and enable Extended Tag.
10154 * Enabling Extended Tag is important for 40G performance.
10157 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10159 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10163 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10166 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10170 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10171 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10176 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10179 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10183 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10184 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10187 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10188 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10191 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10198 * As some registers wouldn't be reset unless a global hardware reset,
10199 * hardware initialization is needed to put those registers into an
10200 * expected initial state.
10203 i40e_hw_init(struct rte_eth_dev *dev)
10205 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10207 i40e_enable_extended_tag(dev);
10209 /* clear the PF Queue Filter control register */
10210 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10212 /* Disable symmetric hash per port */
10213 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10217 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10218 * however this function will return only one highest pctype index,
10219 * which is not quite correct. This is known problem of i40e driver
10220 * and needs to be fixed later.
10222 enum i40e_filter_pctype
10223 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10226 uint64_t pctype_mask;
10228 if (flow_type < I40E_FLOW_TYPE_MAX) {
10229 pctype_mask = adapter->pctypes_tbl[flow_type];
10230 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10231 if (pctype_mask & (1ULL << i))
10232 return (enum i40e_filter_pctype)i;
10235 return I40E_FILTER_PCTYPE_INVALID;
10239 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10240 enum i40e_filter_pctype pctype)
10243 uint64_t pctype_mask = 1ULL << pctype;
10245 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10247 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10251 return RTE_ETH_FLOW_UNKNOWN;
10255 * On X710, performance number is far from the expectation on recent firmware
10256 * versions; on XL710, performance number is also far from the expectation on
10257 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10258 * mode is enabled and port MAC address is equal to the packet destination MAC
10259 * address. The fix for this issue may not be integrated in the following
10260 * firmware version. So the workaround in software driver is needed. It needs
10261 * to modify the initial values of 3 internal only registers for both X710 and
10262 * XL710. Note that the values for X710 or XL710 could be different, and the
10263 * workaround can be removed when it is fixed in firmware in the future.
10266 /* For both X710 and XL710 */
10267 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10268 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10269 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10271 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10272 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10275 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10276 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10279 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10281 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10282 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10285 * GL_SWR_PM_UP_THR:
10286 * The value is not impacted from the link speed, its value is set according
10287 * to the total number of ports for a better pipe-monitor configuration.
10290 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10292 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10293 .device_id = (dev), \
10294 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10296 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10297 .device_id = (dev), \
10298 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10300 static const struct {
10301 uint16_t device_id;
10303 } swr_pm_table[] = {
10304 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10305 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10306 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10307 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10309 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10310 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10311 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10312 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10313 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10314 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10315 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10319 if (value == NULL) {
10320 PMD_DRV_LOG(ERR, "value is NULL");
10324 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10325 if (hw->device_id == swr_pm_table[i].device_id) {
10326 *value = swr_pm_table[i].val;
10328 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10330 hw->device_id, *value);
10339 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10341 enum i40e_status_code status;
10342 struct i40e_aq_get_phy_abilities_resp phy_ab;
10343 int ret = -ENOTSUP;
10346 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10350 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10353 rte_delay_us(100000);
10355 status = i40e_aq_get_phy_capabilities(hw, false,
10356 true, &phy_ab, NULL);
10364 i40e_configure_registers(struct i40e_hw *hw)
10370 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10371 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10372 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10378 for (i = 0; i < RTE_DIM(reg_table); i++) {
10379 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10380 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10382 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10383 else /* For X710/XL710/XXV710 */
10384 if (hw->aq.fw_maj_ver < 6)
10386 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10389 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10392 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10393 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10395 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10396 else /* For X710/XL710/XXV710 */
10398 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10401 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10404 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10405 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10406 "GL_SWR_PM_UP_THR value fixup",
10411 reg_table[i].val = cfg_val;
10414 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10417 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10418 reg_table[i].addr);
10421 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10422 reg_table[i].addr, reg);
10423 if (reg == reg_table[i].val)
10426 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10427 reg_table[i].val, NULL);
10430 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10431 reg_table[i].val, reg_table[i].addr);
10434 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10435 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10439 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10440 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10441 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10442 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10444 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10449 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10450 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10454 /* Configure for double VLAN RX stripping */
10455 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10456 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10457 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10458 ret = i40e_aq_debug_write_register(hw,
10459 I40E_VSI_TSR(vsi->vsi_id),
10462 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10464 return I40E_ERR_CONFIG;
10468 /* Configure for double VLAN TX insertion */
10469 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10470 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10471 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10472 ret = i40e_aq_debug_write_register(hw,
10473 I40E_VSI_L2TAGSTXVALID(
10474 vsi->vsi_id), reg, NULL);
10477 "Failed to update VSI_L2TAGSTXVALID[%d]",
10479 return I40E_ERR_CONFIG;
10487 * i40e_aq_add_mirror_rule
10488 * @hw: pointer to the hardware structure
10489 * @seid: VEB seid to add mirror rule to
10490 * @dst_id: destination vsi seid
10491 * @entries: Buffer which contains the entities to be mirrored
10492 * @count: number of entities contained in the buffer
10493 * @rule_id:the rule_id of the rule to be added
10495 * Add a mirror rule for a given veb.
10498 static enum i40e_status_code
10499 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10500 uint16_t seid, uint16_t dst_id,
10501 uint16_t rule_type, uint16_t *entries,
10502 uint16_t count, uint16_t *rule_id)
10504 struct i40e_aq_desc desc;
10505 struct i40e_aqc_add_delete_mirror_rule cmd;
10506 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10507 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10510 enum i40e_status_code status;
10512 i40e_fill_default_direct_cmd_desc(&desc,
10513 i40e_aqc_opc_add_mirror_rule);
10514 memset(&cmd, 0, sizeof(cmd));
10516 buff_len = sizeof(uint16_t) * count;
10517 desc.datalen = rte_cpu_to_le_16(buff_len);
10519 desc.flags |= rte_cpu_to_le_16(
10520 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10521 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10522 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10523 cmd.num_entries = rte_cpu_to_le_16(count);
10524 cmd.seid = rte_cpu_to_le_16(seid);
10525 cmd.destination = rte_cpu_to_le_16(dst_id);
10527 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10528 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10530 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10531 hw->aq.asq_last_status, resp->rule_id,
10532 resp->mirror_rules_used, resp->mirror_rules_free);
10533 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10539 * i40e_aq_del_mirror_rule
10540 * @hw: pointer to the hardware structure
10541 * @seid: VEB seid to add mirror rule to
10542 * @entries: Buffer which contains the entities to be mirrored
10543 * @count: number of entities contained in the buffer
10544 * @rule_id:the rule_id of the rule to be delete
10546 * Delete a mirror rule for a given veb.
10549 static enum i40e_status_code
10550 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10551 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10552 uint16_t count, uint16_t rule_id)
10554 struct i40e_aq_desc desc;
10555 struct i40e_aqc_add_delete_mirror_rule cmd;
10556 uint16_t buff_len = 0;
10557 enum i40e_status_code status;
10560 i40e_fill_default_direct_cmd_desc(&desc,
10561 i40e_aqc_opc_delete_mirror_rule);
10562 memset(&cmd, 0, sizeof(cmd));
10563 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10564 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10566 cmd.num_entries = count;
10567 buff_len = sizeof(uint16_t) * count;
10568 desc.datalen = rte_cpu_to_le_16(buff_len);
10569 buff = (void *)entries;
10571 /* rule id is filled in destination field for deleting mirror rule */
10572 cmd.destination = rte_cpu_to_le_16(rule_id);
10574 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10575 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10576 cmd.seid = rte_cpu_to_le_16(seid);
10578 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10579 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10585 * i40e_mirror_rule_set
10586 * @dev: pointer to the hardware structure
10587 * @mirror_conf: mirror rule info
10588 * @sw_id: mirror rule's sw_id
10589 * @on: enable/disable
10591 * set a mirror rule.
10595 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10596 struct rte_eth_mirror_conf *mirror_conf,
10597 uint8_t sw_id, uint8_t on)
10599 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10600 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10601 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10602 struct i40e_mirror_rule *parent = NULL;
10603 uint16_t seid, dst_seid, rule_id;
10607 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10609 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10611 "mirror rule can not be configured without veb or vfs.");
10614 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10615 PMD_DRV_LOG(ERR, "mirror table is full.");
10618 if (mirror_conf->dst_pool > pf->vf_num) {
10619 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10620 mirror_conf->dst_pool);
10624 seid = pf->main_vsi->veb->seid;
10626 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10627 if (sw_id <= it->index) {
10633 if (mirr_rule && sw_id == mirr_rule->index) {
10635 PMD_DRV_LOG(ERR, "mirror rule exists.");
10638 ret = i40e_aq_del_mirror_rule(hw, seid,
10639 mirr_rule->rule_type,
10640 mirr_rule->entries,
10641 mirr_rule->num_entries, mirr_rule->id);
10644 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10645 ret, hw->aq.asq_last_status);
10648 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10649 rte_free(mirr_rule);
10650 pf->nb_mirror_rule--;
10654 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10658 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10659 sizeof(struct i40e_mirror_rule) , 0);
10661 PMD_DRV_LOG(ERR, "failed to allocate memory");
10662 return I40E_ERR_NO_MEMORY;
10664 switch (mirror_conf->rule_type) {
10665 case ETH_MIRROR_VLAN:
10666 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10667 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10668 mirr_rule->entries[j] =
10669 mirror_conf->vlan.vlan_id[i];
10674 PMD_DRV_LOG(ERR, "vlan is not specified.");
10675 rte_free(mirr_rule);
10678 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10680 case ETH_MIRROR_VIRTUAL_POOL_UP:
10681 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10682 /* check if the specified pool bit is out of range */
10683 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10684 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10685 rte_free(mirr_rule);
10688 for (i = 0, j = 0; i < pf->vf_num; i++) {
10689 if (mirror_conf->pool_mask & (1ULL << i)) {
10690 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10694 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10695 /* add pf vsi to entries */
10696 mirr_rule->entries[j] = pf->main_vsi_seid;
10700 PMD_DRV_LOG(ERR, "pool is not specified.");
10701 rte_free(mirr_rule);
10704 /* egress and ingress in aq commands means from switch but not port */
10705 mirr_rule->rule_type =
10706 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10707 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10708 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10710 case ETH_MIRROR_UPLINK_PORT:
10711 /* egress and ingress in aq commands means from switch but not port*/
10712 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10714 case ETH_MIRROR_DOWNLINK_PORT:
10715 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10718 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10719 mirror_conf->rule_type);
10720 rte_free(mirr_rule);
10724 /* If the dst_pool is equal to vf_num, consider it as PF */
10725 if (mirror_conf->dst_pool == pf->vf_num)
10726 dst_seid = pf->main_vsi_seid;
10728 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10730 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10731 mirr_rule->rule_type, mirr_rule->entries,
10735 "failed to add mirror rule: ret = %d, aq_err = %d.",
10736 ret, hw->aq.asq_last_status);
10737 rte_free(mirr_rule);
10741 mirr_rule->index = sw_id;
10742 mirr_rule->num_entries = j;
10743 mirr_rule->id = rule_id;
10744 mirr_rule->dst_vsi_seid = dst_seid;
10747 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10749 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10751 pf->nb_mirror_rule++;
10756 * i40e_mirror_rule_reset
10757 * @dev: pointer to the device
10758 * @sw_id: mirror rule's sw_id
10760 * reset a mirror rule.
10764 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10766 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10767 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10768 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10772 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10774 seid = pf->main_vsi->veb->seid;
10776 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10777 if (sw_id == it->index) {
10783 ret = i40e_aq_del_mirror_rule(hw, seid,
10784 mirr_rule->rule_type,
10785 mirr_rule->entries,
10786 mirr_rule->num_entries, mirr_rule->id);
10789 "failed to remove mirror rule: status = %d, aq_err = %d.",
10790 ret, hw->aq.asq_last_status);
10793 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10794 rte_free(mirr_rule);
10795 pf->nb_mirror_rule--;
10797 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10804 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10806 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10807 uint64_t systim_cycles;
10809 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10810 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10813 return systim_cycles;
10817 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10819 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10820 uint64_t rx_tstamp;
10822 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10823 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10830 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10832 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10833 uint64_t tx_tstamp;
10835 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10836 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10843 i40e_start_timecounters(struct rte_eth_dev *dev)
10845 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10846 struct i40e_adapter *adapter =
10847 (struct i40e_adapter *)dev->data->dev_private;
10848 struct rte_eth_link link;
10849 uint32_t tsync_inc_l;
10850 uint32_t tsync_inc_h;
10852 /* Get current link speed. */
10853 i40e_dev_link_update(dev, 1);
10854 rte_eth_linkstatus_get(dev, &link);
10856 switch (link.link_speed) {
10857 case ETH_SPEED_NUM_40G:
10858 case ETH_SPEED_NUM_25G:
10859 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10860 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10862 case ETH_SPEED_NUM_10G:
10863 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10864 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10866 case ETH_SPEED_NUM_1G:
10867 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10868 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10875 /* Set the timesync increment value. */
10876 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10877 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10879 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10880 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10881 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10883 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10884 adapter->systime_tc.cc_shift = 0;
10885 adapter->systime_tc.nsec_mask = 0;
10887 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10888 adapter->rx_tstamp_tc.cc_shift = 0;
10889 adapter->rx_tstamp_tc.nsec_mask = 0;
10891 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10892 adapter->tx_tstamp_tc.cc_shift = 0;
10893 adapter->tx_tstamp_tc.nsec_mask = 0;
10897 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10899 struct i40e_adapter *adapter =
10900 (struct i40e_adapter *)dev->data->dev_private;
10902 adapter->systime_tc.nsec += delta;
10903 adapter->rx_tstamp_tc.nsec += delta;
10904 adapter->tx_tstamp_tc.nsec += delta;
10910 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10913 struct i40e_adapter *adapter =
10914 (struct i40e_adapter *)dev->data->dev_private;
10916 ns = rte_timespec_to_ns(ts);
10918 /* Set the timecounters to a new value. */
10919 adapter->systime_tc.nsec = ns;
10920 adapter->rx_tstamp_tc.nsec = ns;
10921 adapter->tx_tstamp_tc.nsec = ns;
10927 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10929 uint64_t ns, systime_cycles;
10930 struct i40e_adapter *adapter =
10931 (struct i40e_adapter *)dev->data->dev_private;
10933 systime_cycles = i40e_read_systime_cyclecounter(dev);
10934 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10935 *ts = rte_ns_to_timespec(ns);
10941 i40e_timesync_enable(struct rte_eth_dev *dev)
10943 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10944 uint32_t tsync_ctl_l;
10945 uint32_t tsync_ctl_h;
10947 /* Stop the timesync system time. */
10948 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10949 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10950 /* Reset the timesync system time value. */
10951 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10952 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10954 i40e_start_timecounters(dev);
10956 /* Clear timesync registers. */
10957 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10958 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10959 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10960 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10961 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10962 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10964 /* Enable timestamping of PTP packets. */
10965 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10966 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10968 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10969 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10970 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10972 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10973 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10979 i40e_timesync_disable(struct rte_eth_dev *dev)
10981 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10982 uint32_t tsync_ctl_l;
10983 uint32_t tsync_ctl_h;
10985 /* Disable timestamping of transmitted PTP packets. */
10986 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10987 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10989 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10990 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10992 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10993 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10995 /* Reset the timesync increment value. */
10996 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10997 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11003 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11004 struct timespec *timestamp, uint32_t flags)
11006 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11007 struct i40e_adapter *adapter =
11008 (struct i40e_adapter *)dev->data->dev_private;
11010 uint32_t sync_status;
11011 uint32_t index = flags & 0x03;
11012 uint64_t rx_tstamp_cycles;
11015 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11016 if ((sync_status & (1 << index)) == 0)
11019 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11020 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11021 *timestamp = rte_ns_to_timespec(ns);
11027 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11028 struct timespec *timestamp)
11030 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11031 struct i40e_adapter *adapter =
11032 (struct i40e_adapter *)dev->data->dev_private;
11034 uint32_t sync_status;
11035 uint64_t tx_tstamp_cycles;
11038 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11039 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11042 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11043 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11044 *timestamp = rte_ns_to_timespec(ns);
11050 * i40e_parse_dcb_configure - parse dcb configure from user
11051 * @dev: the device being configured
11052 * @dcb_cfg: pointer of the result of parse
11053 * @*tc_map: bit map of enabled traffic classes
11055 * Returns 0 on success, negative value on failure
11058 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11059 struct i40e_dcbx_config *dcb_cfg,
11062 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11063 uint8_t i, tc_bw, bw_lf;
11065 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11067 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11068 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11069 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11073 /* assume each tc has the same bw */
11074 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11075 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11076 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11077 /* to ensure the sum of tcbw is equal to 100 */
11078 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11079 for (i = 0; i < bw_lf; i++)
11080 dcb_cfg->etscfg.tcbwtable[i]++;
11082 /* assume each tc has the same Transmission Selection Algorithm */
11083 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11084 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11086 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11087 dcb_cfg->etscfg.prioritytable[i] =
11088 dcb_rx_conf->dcb_tc[i];
11090 /* FW needs one App to configure HW */
11091 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11092 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11093 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11094 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11096 if (dcb_rx_conf->nb_tcs == 0)
11097 *tc_map = 1; /* tc0 only */
11099 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11101 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11102 dcb_cfg->pfc.willing = 0;
11103 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11104 dcb_cfg->pfc.pfcenable = *tc_map;
11110 static enum i40e_status_code
11111 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11112 struct i40e_aqc_vsi_properties_data *info,
11113 uint8_t enabled_tcmap)
11115 enum i40e_status_code ret;
11116 int i, total_tc = 0;
11117 uint16_t qpnum_per_tc, bsf, qp_idx;
11118 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11119 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11120 uint16_t used_queues;
11122 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11123 if (ret != I40E_SUCCESS)
11126 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11127 if (enabled_tcmap & (1 << i))
11132 vsi->enabled_tc = enabled_tcmap;
11134 /* different VSI has different queues assigned */
11135 if (vsi->type == I40E_VSI_MAIN)
11136 used_queues = dev_data->nb_rx_queues -
11137 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11138 else if (vsi->type == I40E_VSI_VMDQ2)
11139 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11141 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11142 return I40E_ERR_NO_AVAILABLE_VSI;
11145 qpnum_per_tc = used_queues / total_tc;
11146 /* Number of queues per enabled TC */
11147 if (qpnum_per_tc == 0) {
11148 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11149 return I40E_ERR_INVALID_QP_ID;
11151 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11152 I40E_MAX_Q_PER_TC);
11153 bsf = rte_bsf32(qpnum_per_tc);
11156 * Configure TC and queue mapping parameters, for enabled TC,
11157 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11158 * default queue will serve it.
11161 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11162 if (vsi->enabled_tc & (1 << i)) {
11163 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11164 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11165 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11166 qp_idx += qpnum_per_tc;
11168 info->tc_mapping[i] = 0;
11171 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11172 if (vsi->type == I40E_VSI_SRIOV) {
11173 info->mapping_flags |=
11174 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11175 for (i = 0; i < vsi->nb_qps; i++)
11176 info->queue_mapping[i] =
11177 rte_cpu_to_le_16(vsi->base_queue + i);
11179 info->mapping_flags |=
11180 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11181 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11183 info->valid_sections |=
11184 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11186 return I40E_SUCCESS;
11190 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11191 * @veb: VEB to be configured
11192 * @tc_map: enabled TC bitmap
11194 * Returns 0 on success, negative value on failure
11196 static enum i40e_status_code
11197 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11199 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11200 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11201 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11202 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11203 enum i40e_status_code ret = I40E_SUCCESS;
11207 /* Check if enabled_tc is same as existing or new TCs */
11208 if (veb->enabled_tc == tc_map)
11211 /* configure tc bandwidth */
11212 memset(&veb_bw, 0, sizeof(veb_bw));
11213 veb_bw.tc_valid_bits = tc_map;
11214 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11215 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11216 if (tc_map & BIT_ULL(i))
11217 veb_bw.tc_bw_share_credits[i] = 1;
11219 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11223 "AQ command Config switch_comp BW allocation per TC failed = %d",
11224 hw->aq.asq_last_status);
11228 memset(&ets_query, 0, sizeof(ets_query));
11229 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11231 if (ret != I40E_SUCCESS) {
11233 "Failed to get switch_comp ETS configuration %u",
11234 hw->aq.asq_last_status);
11237 memset(&bw_query, 0, sizeof(bw_query));
11238 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11240 if (ret != I40E_SUCCESS) {
11242 "Failed to get switch_comp bandwidth configuration %u",
11243 hw->aq.asq_last_status);
11247 /* store and print out BW info */
11248 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11249 veb->bw_info.bw_max = ets_query.tc_bw_max;
11250 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11251 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11252 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11253 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11254 I40E_16_BIT_WIDTH);
11255 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11256 veb->bw_info.bw_ets_share_credits[i] =
11257 bw_query.tc_bw_share_credits[i];
11258 veb->bw_info.bw_ets_credits[i] =
11259 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11260 /* 4 bits per TC, 4th bit is reserved */
11261 veb->bw_info.bw_ets_max[i] =
11262 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11263 RTE_LEN2MASK(3, uint8_t));
11264 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11265 veb->bw_info.bw_ets_share_credits[i]);
11266 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11267 veb->bw_info.bw_ets_credits[i]);
11268 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11269 veb->bw_info.bw_ets_max[i]);
11272 veb->enabled_tc = tc_map;
11279 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11280 * @vsi: VSI to be configured
11281 * @tc_map: enabled TC bitmap
11283 * Returns 0 on success, negative value on failure
11285 static enum i40e_status_code
11286 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11288 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11289 struct i40e_vsi_context ctxt;
11290 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11291 enum i40e_status_code ret = I40E_SUCCESS;
11294 /* Check if enabled_tc is same as existing or new TCs */
11295 if (vsi->enabled_tc == tc_map)
11298 /* configure tc bandwidth */
11299 memset(&bw_data, 0, sizeof(bw_data));
11300 bw_data.tc_valid_bits = tc_map;
11301 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11302 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11303 if (tc_map & BIT_ULL(i))
11304 bw_data.tc_bw_credits[i] = 1;
11306 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11309 "AQ command Config VSI BW allocation per TC failed = %d",
11310 hw->aq.asq_last_status);
11313 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11314 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11316 /* Update Queue Pairs Mapping for currently enabled UPs */
11317 ctxt.seid = vsi->seid;
11318 ctxt.pf_num = hw->pf_id;
11320 ctxt.uplink_seid = vsi->uplink_seid;
11321 ctxt.info = vsi->info;
11323 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11327 /* Update the VSI after updating the VSI queue-mapping information */
11328 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11330 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11331 hw->aq.asq_last_status);
11334 /* update the local VSI info with updated queue map */
11335 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11336 sizeof(vsi->info.tc_mapping));
11337 rte_memcpy(&vsi->info.queue_mapping,
11338 &ctxt.info.queue_mapping,
11339 sizeof(vsi->info.queue_mapping));
11340 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11341 vsi->info.valid_sections = 0;
11343 /* query and update current VSI BW information */
11344 ret = i40e_vsi_get_bw_config(vsi);
11347 "Failed updating vsi bw info, err %s aq_err %s",
11348 i40e_stat_str(hw, ret),
11349 i40e_aq_str(hw, hw->aq.asq_last_status));
11353 vsi->enabled_tc = tc_map;
11360 * i40e_dcb_hw_configure - program the dcb setting to hw
11361 * @pf: pf the configuration is taken on
11362 * @new_cfg: new configuration
11363 * @tc_map: enabled TC bitmap
11365 * Returns 0 on success, negative value on failure
11367 static enum i40e_status_code
11368 i40e_dcb_hw_configure(struct i40e_pf *pf,
11369 struct i40e_dcbx_config *new_cfg,
11372 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11373 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11374 struct i40e_vsi *main_vsi = pf->main_vsi;
11375 struct i40e_vsi_list *vsi_list;
11376 enum i40e_status_code ret;
11380 /* Use the FW API if FW > v4.4*/
11381 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11382 (hw->aq.fw_maj_ver >= 5))) {
11384 "FW < v4.4, can not use FW LLDP API to configure DCB");
11385 return I40E_ERR_FIRMWARE_API_VERSION;
11388 /* Check if need reconfiguration */
11389 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11390 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11391 return I40E_SUCCESS;
11394 /* Copy the new config to the current config */
11395 *old_cfg = *new_cfg;
11396 old_cfg->etsrec = old_cfg->etscfg;
11397 ret = i40e_set_dcb_config(hw);
11399 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11400 i40e_stat_str(hw, ret),
11401 i40e_aq_str(hw, hw->aq.asq_last_status));
11404 /* set receive Arbiter to RR mode and ETS scheme by default */
11405 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11406 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11407 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11408 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11409 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11410 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11411 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11412 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11413 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11414 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11415 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11416 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11417 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11419 /* get local mib to check whether it is configured correctly */
11421 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11422 /* Get Local DCB Config */
11423 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11424 &hw->local_dcbx_config);
11426 /* if Veb is created, need to update TC of it at first */
11427 if (main_vsi->veb) {
11428 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11430 PMD_INIT_LOG(WARNING,
11431 "Failed configuring TC for VEB seid=%d",
11432 main_vsi->veb->seid);
11434 /* Update each VSI */
11435 i40e_vsi_config_tc(main_vsi, tc_map);
11436 if (main_vsi->veb) {
11437 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11438 /* Beside main VSI and VMDQ VSIs, only enable default
11439 * TC for other VSIs
11441 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11442 ret = i40e_vsi_config_tc(vsi_list->vsi,
11445 ret = i40e_vsi_config_tc(vsi_list->vsi,
11446 I40E_DEFAULT_TCMAP);
11448 PMD_INIT_LOG(WARNING,
11449 "Failed configuring TC for VSI seid=%d",
11450 vsi_list->vsi->seid);
11454 return I40E_SUCCESS;
11458 * i40e_dcb_init_configure - initial dcb config
11459 * @dev: device being configured
11460 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11462 * Returns 0 on success, negative value on failure
11465 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11467 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11468 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11471 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11472 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11476 /* DCB initialization:
11477 * Update DCB configuration from the Firmware and configure
11478 * LLDP MIB change event.
11480 if (sw_dcb == TRUE) {
11481 if (i40e_need_stop_lldp(dev)) {
11482 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11483 if (ret != I40E_SUCCESS)
11484 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11487 ret = i40e_init_dcb(hw);
11488 /* If lldp agent is stopped, the return value from
11489 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11490 * adminq status. Otherwise, it should return success.
11492 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11493 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11494 memset(&hw->local_dcbx_config, 0,
11495 sizeof(struct i40e_dcbx_config));
11496 /* set dcb default configuration */
11497 hw->local_dcbx_config.etscfg.willing = 0;
11498 hw->local_dcbx_config.etscfg.maxtcs = 0;
11499 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11500 hw->local_dcbx_config.etscfg.tsatable[0] =
11502 /* all UPs mapping to TC0 */
11503 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11504 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11505 hw->local_dcbx_config.etsrec =
11506 hw->local_dcbx_config.etscfg;
11507 hw->local_dcbx_config.pfc.willing = 0;
11508 hw->local_dcbx_config.pfc.pfccap =
11509 I40E_MAX_TRAFFIC_CLASS;
11510 /* FW needs one App to configure HW */
11511 hw->local_dcbx_config.numapps = 1;
11512 hw->local_dcbx_config.app[0].selector =
11513 I40E_APP_SEL_ETHTYPE;
11514 hw->local_dcbx_config.app[0].priority = 3;
11515 hw->local_dcbx_config.app[0].protocolid =
11516 I40E_APP_PROTOID_FCOE;
11517 ret = i40e_set_dcb_config(hw);
11520 "default dcb config fails. err = %d, aq_err = %d.",
11521 ret, hw->aq.asq_last_status);
11526 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11527 ret, hw->aq.asq_last_status);
11531 ret = i40e_aq_start_lldp(hw, NULL);
11532 if (ret != I40E_SUCCESS)
11533 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11535 ret = i40e_init_dcb(hw);
11537 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11539 "HW doesn't support DCBX offload.");
11544 "DCBX configuration failed, err = %d, aq_err = %d.",
11545 ret, hw->aq.asq_last_status);
11553 * i40e_dcb_setup - setup dcb related config
11554 * @dev: device being configured
11556 * Returns 0 on success, negative value on failure
11559 i40e_dcb_setup(struct rte_eth_dev *dev)
11561 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11562 struct i40e_dcbx_config dcb_cfg;
11563 uint8_t tc_map = 0;
11566 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11567 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11571 if (pf->vf_num != 0)
11572 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11574 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11576 PMD_INIT_LOG(ERR, "invalid dcb config");
11579 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11581 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11589 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11590 struct rte_eth_dcb_info *dcb_info)
11592 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11593 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11594 struct i40e_vsi *vsi = pf->main_vsi;
11595 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11596 uint16_t bsf, tc_mapping;
11599 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11600 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11602 dcb_info->nb_tcs = 1;
11603 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11604 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11605 for (i = 0; i < dcb_info->nb_tcs; i++)
11606 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11608 /* get queue mapping if vmdq is disabled */
11609 if (!pf->nb_cfg_vmdq_vsi) {
11610 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11611 if (!(vsi->enabled_tc & (1 << i)))
11613 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11614 dcb_info->tc_queue.tc_rxq[j][i].base =
11615 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11616 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11617 dcb_info->tc_queue.tc_txq[j][i].base =
11618 dcb_info->tc_queue.tc_rxq[j][i].base;
11619 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11620 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11621 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11622 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11623 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11628 /* get queue mapping if vmdq is enabled */
11630 vsi = pf->vmdq[j].vsi;
11631 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11632 if (!(vsi->enabled_tc & (1 << i)))
11634 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11635 dcb_info->tc_queue.tc_rxq[j][i].base =
11636 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11637 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11638 dcb_info->tc_queue.tc_txq[j][i].base =
11639 dcb_info->tc_queue.tc_rxq[j][i].base;
11640 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11641 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11642 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11643 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11644 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11647 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11652 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11654 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11655 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11656 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11657 uint16_t msix_intr;
11659 msix_intr = intr_handle->intr_vec[queue_id];
11660 if (msix_intr == I40E_MISC_VEC_ID)
11661 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11662 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11663 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11664 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11667 I40E_PFINT_DYN_CTLN(msix_intr -
11668 I40E_RX_VEC_START),
11669 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11670 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11671 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11673 I40E_WRITE_FLUSH(hw);
11674 rte_intr_enable(&pci_dev->intr_handle);
11680 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11682 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11683 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11684 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11685 uint16_t msix_intr;
11687 msix_intr = intr_handle->intr_vec[queue_id];
11688 if (msix_intr == I40E_MISC_VEC_ID)
11689 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11690 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11693 I40E_PFINT_DYN_CTLN(msix_intr -
11694 I40E_RX_VEC_START),
11695 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11696 I40E_WRITE_FLUSH(hw);
11702 * This function is used to check if the register is valid.
11703 * Below is the valid registers list for X722 only:
11707 * 0x208e00--0x209000
11708 * 0x20be00--0x20c000
11709 * 0x263c00--0x264000
11710 * 0x265c00--0x266000
11712 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11714 if ((type != I40E_MAC_X722) &&
11715 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11716 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11717 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11718 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11719 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11720 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11721 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11727 static int i40e_get_regs(struct rte_eth_dev *dev,
11728 struct rte_dev_reg_info *regs)
11730 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11731 uint32_t *ptr_data = regs->data;
11732 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11733 const struct i40e_reg_info *reg_info;
11735 if (ptr_data == NULL) {
11736 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11737 regs->width = sizeof(uint32_t);
11741 /* The first few registers have to be read using AQ operations */
11743 while (i40e_regs_adminq[reg_idx].name) {
11744 reg_info = &i40e_regs_adminq[reg_idx++];
11745 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11747 arr_idx2 <= reg_info->count2;
11749 reg_offset = arr_idx * reg_info->stride1 +
11750 arr_idx2 * reg_info->stride2;
11751 reg_offset += reg_info->base_addr;
11752 ptr_data[reg_offset >> 2] =
11753 i40e_read_rx_ctl(hw, reg_offset);
11757 /* The remaining registers can be read using primitives */
11759 while (i40e_regs_others[reg_idx].name) {
11760 reg_info = &i40e_regs_others[reg_idx++];
11761 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11763 arr_idx2 <= reg_info->count2;
11765 reg_offset = arr_idx * reg_info->stride1 +
11766 arr_idx2 * reg_info->stride2;
11767 reg_offset += reg_info->base_addr;
11768 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11769 ptr_data[reg_offset >> 2] = 0;
11771 ptr_data[reg_offset >> 2] =
11772 I40E_READ_REG(hw, reg_offset);
11779 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11783 /* Convert word count to byte count */
11784 return hw->nvm.sr_size << 1;
11787 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11788 struct rte_dev_eeprom_info *eeprom)
11790 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11791 uint16_t *data = eeprom->data;
11792 uint16_t offset, length, cnt_words;
11795 offset = eeprom->offset >> 1;
11796 length = eeprom->length >> 1;
11797 cnt_words = length;
11799 if (offset > hw->nvm.sr_size ||
11800 offset + length > hw->nvm.sr_size) {
11801 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11805 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11807 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11808 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11809 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11816 static int i40e_get_module_info(struct rte_eth_dev *dev,
11817 struct rte_eth_dev_module_info *modinfo)
11819 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11820 uint32_t sff8472_comp = 0;
11821 uint32_t sff8472_swap = 0;
11822 uint32_t sff8636_rev = 0;
11823 i40e_status status;
11826 /* Check if firmware supports reading module EEPROM. */
11827 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11829 "Module EEPROM memory read not supported. "
11830 "Please update the NVM image.\n");
11834 status = i40e_update_link_info(hw);
11838 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11840 "Cannot read module EEPROM memory. "
11841 "No module connected.\n");
11845 type = hw->phy.link_info.module_type[0];
11848 case I40E_MODULE_TYPE_SFP:
11849 status = i40e_aq_get_phy_register(hw,
11850 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11851 I40E_I2C_EEPROM_DEV_ADDR, 1,
11852 I40E_MODULE_SFF_8472_COMP,
11853 &sff8472_comp, NULL);
11857 status = i40e_aq_get_phy_register(hw,
11858 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11859 I40E_I2C_EEPROM_DEV_ADDR, 1,
11860 I40E_MODULE_SFF_8472_SWAP,
11861 &sff8472_swap, NULL);
11865 /* Check if the module requires address swap to access
11866 * the other EEPROM memory page.
11868 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11869 PMD_DRV_LOG(WARNING,
11870 "Module address swap to access "
11871 "page 0xA2 is not supported.\n");
11872 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11873 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11874 } else if (sff8472_comp == 0x00) {
11875 /* Module is not SFF-8472 compliant */
11876 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11877 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11879 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11880 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11883 case I40E_MODULE_TYPE_QSFP_PLUS:
11884 /* Read from memory page 0. */
11885 status = i40e_aq_get_phy_register(hw,
11886 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11888 I40E_MODULE_REVISION_ADDR,
11889 &sff8636_rev, NULL);
11892 /* Determine revision compliance byte */
11893 if (sff8636_rev > 0x02) {
11894 /* Module is SFF-8636 compliant */
11895 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11896 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11898 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11899 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11902 case I40E_MODULE_TYPE_QSFP28:
11903 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11904 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11907 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11913 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11914 struct rte_dev_eeprom_info *info)
11916 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11917 bool is_sfp = false;
11918 i40e_status status;
11920 uint32_t value = 0;
11923 if (!info || !info->length || !info->data)
11926 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11930 for (i = 0; i < info->length; i++) {
11931 u32 offset = i + info->offset;
11932 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11934 /* Check if we need to access the other memory page */
11936 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11937 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11938 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11941 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11942 /* Compute memory page number and offset. */
11943 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11947 status = i40e_aq_get_phy_register(hw,
11948 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11949 addr, offset, 1, &value, NULL);
11952 data[i] = (uint8_t)value;
11957 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11958 struct rte_ether_addr *mac_addr)
11960 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11961 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11962 struct i40e_vsi *vsi = pf->main_vsi;
11963 struct i40e_mac_filter_info mac_filter;
11964 struct i40e_mac_filter *f;
11967 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11968 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11972 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11973 if (rte_is_same_ether_addr(&pf->dev_addr,
11974 &f->mac_info.mac_addr))
11979 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11983 mac_filter = f->mac_info;
11984 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11985 if (ret != I40E_SUCCESS) {
11986 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11989 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11990 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11991 if (ret != I40E_SUCCESS) {
11992 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11995 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11997 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11998 mac_addr->addr_bytes, NULL);
11999 if (ret != I40E_SUCCESS) {
12000 PMD_DRV_LOG(ERR, "Failed to change mac");
12008 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12010 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12011 struct rte_eth_dev_data *dev_data = pf->dev_data;
12012 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12015 /* check if mtu is within the allowed range */
12016 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12019 /* mtu setting is forbidden if port is start */
12020 if (dev_data->dev_started) {
12021 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12022 dev_data->port_id);
12026 if (frame_size > RTE_ETHER_MAX_LEN)
12027 dev_data->dev_conf.rxmode.offloads |=
12028 DEV_RX_OFFLOAD_JUMBO_FRAME;
12030 dev_data->dev_conf.rxmode.offloads &=
12031 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12033 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12038 /* Restore ethertype filter */
12040 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12042 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12043 struct i40e_ethertype_filter_list
12044 *ethertype_list = &pf->ethertype.ethertype_list;
12045 struct i40e_ethertype_filter *f;
12046 struct i40e_control_filter_stats stats;
12049 TAILQ_FOREACH(f, ethertype_list, rules) {
12051 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12052 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12053 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12054 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12055 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12057 memset(&stats, 0, sizeof(stats));
12058 i40e_aq_add_rem_control_packet_filter(hw,
12059 f->input.mac_addr.addr_bytes,
12060 f->input.ether_type,
12061 flags, pf->main_vsi->seid,
12062 f->queue, 1, &stats, NULL);
12064 PMD_DRV_LOG(INFO, "Ethertype filter:"
12065 " mac_etype_used = %u, etype_used = %u,"
12066 " mac_etype_free = %u, etype_free = %u",
12067 stats.mac_etype_used, stats.etype_used,
12068 stats.mac_etype_free, stats.etype_free);
12071 /* Restore tunnel filter */
12073 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12075 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12076 struct i40e_vsi *vsi;
12077 struct i40e_pf_vf *vf;
12078 struct i40e_tunnel_filter_list
12079 *tunnel_list = &pf->tunnel.tunnel_list;
12080 struct i40e_tunnel_filter *f;
12081 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12082 bool big_buffer = 0;
12084 TAILQ_FOREACH(f, tunnel_list, rules) {
12086 vsi = pf->main_vsi;
12088 vf = &pf->vfs[f->vf_id];
12091 memset(&cld_filter, 0, sizeof(cld_filter));
12092 rte_ether_addr_copy((struct rte_ether_addr *)
12093 &f->input.outer_mac,
12094 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12095 rte_ether_addr_copy((struct rte_ether_addr *)
12096 &f->input.inner_mac,
12097 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12098 cld_filter.element.inner_vlan = f->input.inner_vlan;
12099 cld_filter.element.flags = f->input.flags;
12100 cld_filter.element.tenant_id = f->input.tenant_id;
12101 cld_filter.element.queue_number = f->queue;
12102 rte_memcpy(cld_filter.general_fields,
12103 f->input.general_fields,
12104 sizeof(f->input.general_fields));
12106 if (((f->input.flags &
12107 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12108 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12110 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12111 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12113 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12114 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12118 i40e_aq_add_cloud_filters_bb(hw,
12119 vsi->seid, &cld_filter, 1);
12121 i40e_aq_add_cloud_filters(hw, vsi->seid,
12122 &cld_filter.element, 1);
12126 /* Restore rss filter */
12128 i40e_rss_filter_restore(struct i40e_pf *pf)
12130 struct i40e_rte_flow_rss_conf *conf =
12132 if (conf->conf.queue_num)
12133 i40e_config_rss_filter(pf, conf, TRUE);
12137 i40e_filter_restore(struct i40e_pf *pf)
12139 i40e_ethertype_filter_restore(pf);
12140 i40e_tunnel_filter_restore(pf);
12141 i40e_fdir_filter_restore(pf);
12142 i40e_rss_filter_restore(pf);
12146 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12148 if (strcmp(dev->device->driver->name, drv->driver.name))
12155 is_i40e_supported(struct rte_eth_dev *dev)
12157 return is_device_supported(dev, &rte_i40e_pmd);
12160 struct i40e_customized_pctype*
12161 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12165 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12166 if (pf->customized_pctype[i].index == index)
12167 return &pf->customized_pctype[i];
12173 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12174 uint32_t pkg_size, uint32_t proto_num,
12175 struct rte_pmd_i40e_proto_info *proto,
12176 enum rte_pmd_i40e_package_op op)
12178 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12179 uint32_t pctype_num;
12180 struct rte_pmd_i40e_ptype_info *pctype;
12181 uint32_t buff_size;
12182 struct i40e_customized_pctype *new_pctype = NULL;
12184 uint8_t pctype_value;
12189 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12190 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12191 PMD_DRV_LOG(ERR, "Unsupported operation.");
12195 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12196 (uint8_t *)&pctype_num, sizeof(pctype_num),
12197 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12199 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12203 PMD_DRV_LOG(INFO, "No new pctype added");
12207 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12208 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12210 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12213 /* get information about new pctype list */
12214 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12215 (uint8_t *)pctype, buff_size,
12216 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12218 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12223 /* Update customized pctype. */
12224 for (i = 0; i < pctype_num; i++) {
12225 pctype_value = pctype[i].ptype_id;
12226 memset(name, 0, sizeof(name));
12227 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12228 proto_id = pctype[i].protocols[j];
12229 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12231 for (n = 0; n < proto_num; n++) {
12232 if (proto[n].proto_id != proto_id)
12234 strlcat(name, proto[n].name, sizeof(name));
12235 strlcat(name, "_", sizeof(name));
12239 name[strlen(name) - 1] = '\0';
12240 if (!strcmp(name, "GTPC"))
12242 i40e_find_customized_pctype(pf,
12243 I40E_CUSTOMIZED_GTPC);
12244 else if (!strcmp(name, "GTPU_IPV4"))
12246 i40e_find_customized_pctype(pf,
12247 I40E_CUSTOMIZED_GTPU_IPV4);
12248 else if (!strcmp(name, "GTPU_IPV6"))
12250 i40e_find_customized_pctype(pf,
12251 I40E_CUSTOMIZED_GTPU_IPV6);
12252 else if (!strcmp(name, "GTPU"))
12254 i40e_find_customized_pctype(pf,
12255 I40E_CUSTOMIZED_GTPU);
12257 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12258 new_pctype->pctype = pctype_value;
12259 new_pctype->valid = true;
12261 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12262 new_pctype->valid = false;
12272 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12273 uint32_t pkg_size, uint32_t proto_num,
12274 struct rte_pmd_i40e_proto_info *proto,
12275 enum rte_pmd_i40e_package_op op)
12277 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12278 uint16_t port_id = dev->data->port_id;
12279 uint32_t ptype_num;
12280 struct rte_pmd_i40e_ptype_info *ptype;
12281 uint32_t buff_size;
12283 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12288 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12289 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12290 PMD_DRV_LOG(ERR, "Unsupported operation.");
12294 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12295 rte_pmd_i40e_ptype_mapping_reset(port_id);
12299 /* get information about new ptype num */
12300 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12301 (uint8_t *)&ptype_num, sizeof(ptype_num),
12302 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12304 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12308 PMD_DRV_LOG(INFO, "No new ptype added");
12312 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12313 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12315 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12319 /* get information about new ptype list */
12320 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12321 (uint8_t *)ptype, buff_size,
12322 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12324 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12329 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12330 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12331 if (!ptype_mapping) {
12332 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12337 /* Update ptype mapping table. */
12338 for (i = 0; i < ptype_num; i++) {
12339 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12340 ptype_mapping[i].sw_ptype = 0;
12342 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12343 proto_id = ptype[i].protocols[j];
12344 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12346 for (n = 0; n < proto_num; n++) {
12347 if (proto[n].proto_id != proto_id)
12349 memset(name, 0, sizeof(name));
12350 strcpy(name, proto[n].name);
12351 if (!strncasecmp(name, "PPPOE", 5))
12352 ptype_mapping[i].sw_ptype |=
12353 RTE_PTYPE_L2_ETHER_PPPOE;
12354 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12356 ptype_mapping[i].sw_ptype |=
12357 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12358 ptype_mapping[i].sw_ptype |=
12360 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12362 ptype_mapping[i].sw_ptype |=
12363 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12364 ptype_mapping[i].sw_ptype |=
12365 RTE_PTYPE_INNER_L4_FRAG;
12366 } else if (!strncasecmp(name, "OIPV4", 5)) {
12367 ptype_mapping[i].sw_ptype |=
12368 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12370 } else if (!strncasecmp(name, "IPV4", 4) &&
12372 ptype_mapping[i].sw_ptype |=
12373 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12374 else if (!strncasecmp(name, "IPV4", 4) &&
12376 ptype_mapping[i].sw_ptype |=
12377 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12378 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12380 ptype_mapping[i].sw_ptype |=
12381 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12382 ptype_mapping[i].sw_ptype |=
12384 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12386 ptype_mapping[i].sw_ptype |=
12387 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12388 ptype_mapping[i].sw_ptype |=
12389 RTE_PTYPE_INNER_L4_FRAG;
12390 } else if (!strncasecmp(name, "OIPV6", 5)) {
12391 ptype_mapping[i].sw_ptype |=
12392 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12394 } else if (!strncasecmp(name, "IPV6", 4) &&
12396 ptype_mapping[i].sw_ptype |=
12397 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12398 else if (!strncasecmp(name, "IPV6", 4) &&
12400 ptype_mapping[i].sw_ptype |=
12401 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12402 else if (!strncasecmp(name, "UDP", 3) &&
12404 ptype_mapping[i].sw_ptype |=
12406 else if (!strncasecmp(name, "UDP", 3) &&
12408 ptype_mapping[i].sw_ptype |=
12409 RTE_PTYPE_INNER_L4_UDP;
12410 else if (!strncasecmp(name, "TCP", 3) &&
12412 ptype_mapping[i].sw_ptype |=
12414 else if (!strncasecmp(name, "TCP", 3) &&
12416 ptype_mapping[i].sw_ptype |=
12417 RTE_PTYPE_INNER_L4_TCP;
12418 else if (!strncasecmp(name, "SCTP", 4) &&
12420 ptype_mapping[i].sw_ptype |=
12422 else if (!strncasecmp(name, "SCTP", 4) &&
12424 ptype_mapping[i].sw_ptype |=
12425 RTE_PTYPE_INNER_L4_SCTP;
12426 else if ((!strncasecmp(name, "ICMP", 4) ||
12427 !strncasecmp(name, "ICMPV6", 6)) &&
12429 ptype_mapping[i].sw_ptype |=
12431 else if ((!strncasecmp(name, "ICMP", 4) ||
12432 !strncasecmp(name, "ICMPV6", 6)) &&
12434 ptype_mapping[i].sw_ptype |=
12435 RTE_PTYPE_INNER_L4_ICMP;
12436 else if (!strncasecmp(name, "GTPC", 4)) {
12437 ptype_mapping[i].sw_ptype |=
12438 RTE_PTYPE_TUNNEL_GTPC;
12440 } else if (!strncasecmp(name, "GTPU", 4)) {
12441 ptype_mapping[i].sw_ptype |=
12442 RTE_PTYPE_TUNNEL_GTPU;
12444 } else if (!strncasecmp(name, "GRENAT", 6)) {
12445 ptype_mapping[i].sw_ptype |=
12446 RTE_PTYPE_TUNNEL_GRENAT;
12448 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12449 !strncasecmp(name, "L2TPV2", 6)) {
12450 ptype_mapping[i].sw_ptype |=
12451 RTE_PTYPE_TUNNEL_L2TP;
12460 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12463 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12465 rte_free(ptype_mapping);
12471 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12472 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12474 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12475 uint32_t proto_num;
12476 struct rte_pmd_i40e_proto_info *proto;
12477 uint32_t buff_size;
12481 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12482 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12483 PMD_DRV_LOG(ERR, "Unsupported operation.");
12487 /* get information about protocol number */
12488 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12489 (uint8_t *)&proto_num, sizeof(proto_num),
12490 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12492 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12496 PMD_DRV_LOG(INFO, "No new protocol added");
12500 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12501 proto = rte_zmalloc("new_proto", buff_size, 0);
12503 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12507 /* get information about protocol list */
12508 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12509 (uint8_t *)proto, buff_size,
12510 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12512 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12517 /* Check if GTP is supported. */
12518 for (i = 0; i < proto_num; i++) {
12519 if (!strncmp(proto[i].name, "GTP", 3)) {
12520 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12521 pf->gtp_support = true;
12523 pf->gtp_support = false;
12528 /* Update customized pctype info */
12529 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12530 proto_num, proto, op);
12532 PMD_DRV_LOG(INFO, "No pctype is updated.");
12534 /* Update customized ptype info */
12535 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12536 proto_num, proto, op);
12538 PMD_DRV_LOG(INFO, "No ptype is updated.");
12543 /* Create a QinQ cloud filter
12545 * The Fortville NIC has limited resources for tunnel filters,
12546 * so we can only reuse existing filters.
12548 * In step 1 we define which Field Vector fields can be used for
12550 * As we do not have the inner tag defined as a field,
12551 * we have to define it first, by reusing one of L1 entries.
12553 * In step 2 we are replacing one of existing filter types with
12554 * a new one for QinQ.
12555 * As we reusing L1 and replacing L2, some of the default filter
12556 * types will disappear,which depends on L1 and L2 entries we reuse.
12558 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12560 * 1. Create L1 filter of outer vlan (12b) which will be in use
12561 * later when we define the cloud filter.
12562 * a. Valid_flags.replace_cloud = 0
12563 * b. Old_filter = 10 (Stag_Inner_Vlan)
12564 * c. New_filter = 0x10
12565 * d. TR bit = 0xff (optional, not used here)
12566 * e. Buffer – 2 entries:
12567 * i. Byte 0 = 8 (outer vlan FV index).
12569 * Byte 2-3 = 0x0fff
12570 * ii. Byte 0 = 37 (inner vlan FV index).
12572 * Byte 2-3 = 0x0fff
12575 * 2. Create cloud filter using two L1 filters entries: stag and
12576 * new filter(outer vlan+ inner vlan)
12577 * a. Valid_flags.replace_cloud = 1
12578 * b. Old_filter = 1 (instead of outer IP)
12579 * c. New_filter = 0x10
12580 * d. Buffer – 2 entries:
12581 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12582 * Byte 1-3 = 0 (rsv)
12583 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12584 * Byte 9-11 = 0 (rsv)
12587 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12589 int ret = -ENOTSUP;
12590 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12591 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12592 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12593 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12595 if (pf->support_multi_driver) {
12596 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12601 memset(&filter_replace, 0,
12602 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12603 memset(&filter_replace_buf, 0,
12604 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12606 /* create L1 filter */
12607 filter_replace.old_filter_type =
12608 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12609 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12610 filter_replace.tr_bit = 0;
12612 /* Prepare the buffer, 2 entries */
12613 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12614 filter_replace_buf.data[0] |=
12615 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12616 /* Field Vector 12b mask */
12617 filter_replace_buf.data[2] = 0xff;
12618 filter_replace_buf.data[3] = 0x0f;
12619 filter_replace_buf.data[4] =
12620 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12621 filter_replace_buf.data[4] |=
12622 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12623 /* Field Vector 12b mask */
12624 filter_replace_buf.data[6] = 0xff;
12625 filter_replace_buf.data[7] = 0x0f;
12626 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12627 &filter_replace_buf);
12628 if (ret != I40E_SUCCESS)
12631 if (filter_replace.old_filter_type !=
12632 filter_replace.new_filter_type)
12633 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12634 " original: 0x%x, new: 0x%x",
12636 filter_replace.old_filter_type,
12637 filter_replace.new_filter_type);
12639 /* Apply the second L2 cloud filter */
12640 memset(&filter_replace, 0,
12641 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12642 memset(&filter_replace_buf, 0,
12643 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12645 /* create L2 filter, input for L2 filter will be L1 filter */
12646 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12647 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12648 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12650 /* Prepare the buffer, 2 entries */
12651 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12652 filter_replace_buf.data[0] |=
12653 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12654 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12655 filter_replace_buf.data[4] |=
12656 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12657 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12658 &filter_replace_buf);
12659 if (!ret && (filter_replace.old_filter_type !=
12660 filter_replace.new_filter_type))
12661 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12662 " original: 0x%x, new: 0x%x",
12664 filter_replace.old_filter_type,
12665 filter_replace.new_filter_type);
12671 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12672 const struct rte_flow_action_rss *in)
12674 if (in->key_len > RTE_DIM(out->key) ||
12675 in->queue_num > RTE_DIM(out->queue))
12677 if (!in->key && in->key_len)
12679 out->conf = (struct rte_flow_action_rss){
12681 .level = in->level,
12682 .types = in->types,
12683 .key_len = in->key_len,
12684 .queue_num = in->queue_num,
12685 .queue = memcpy(out->queue, in->queue,
12686 sizeof(*in->queue) * in->queue_num),
12689 out->conf.key = memcpy(out->key, in->key, in->key_len);
12694 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12695 const struct rte_flow_action_rss *with)
12697 return (comp->func == with->func &&
12698 comp->level == with->level &&
12699 comp->types == with->types &&
12700 comp->key_len == with->key_len &&
12701 comp->queue_num == with->queue_num &&
12702 !memcmp(comp->key, with->key, with->key_len) &&
12703 !memcmp(comp->queue, with->queue,
12704 sizeof(*with->queue) * with->queue_num));
12708 i40e_config_rss_filter(struct i40e_pf *pf,
12709 struct i40e_rte_flow_rss_conf *conf, bool add)
12711 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12712 uint32_t i, lut = 0;
12714 struct rte_eth_rss_conf rss_conf = {
12715 .rss_key = conf->conf.key_len ?
12716 (void *)(uintptr_t)conf->conf.key : NULL,
12717 .rss_key_len = conf->conf.key_len,
12718 .rss_hf = conf->conf.types,
12720 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12723 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12724 i40e_pf_disable_rss(pf);
12725 memset(rss_info, 0,
12726 sizeof(struct i40e_rte_flow_rss_conf));
12732 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12733 * It's necessary to calculate the actual PF queues that are configured.
12735 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12736 num = i40e_pf_calc_configured_queues_num(pf);
12738 num = pf->dev_data->nb_rx_queues;
12740 num = RTE_MIN(num, conf->conf.queue_num);
12741 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12745 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12749 /* Fill in redirection table */
12750 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12753 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12754 hw->func_caps.rss_table_entry_width) - 1));
12756 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12759 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12760 i40e_pf_disable_rss(pf);
12763 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12764 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12765 /* Random default keys */
12766 static uint32_t rss_key_default[] = {0x6b793944,
12767 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12768 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12769 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12771 rss_conf.rss_key = (uint8_t *)rss_key_default;
12772 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12775 "No valid RSS key config for i40e, using default\n");
12778 i40e_hw_rss_hash_set(pf, &rss_conf);
12780 if (i40e_rss_conf_init(rss_info, &conf->conf))
12786 RTE_INIT(i40e_init_log)
12788 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12789 if (i40e_logtype_init >= 0)
12790 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12791 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12792 if (i40e_logtype_driver >= 0)
12793 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12796 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12797 ETH_I40E_FLOATING_VEB_ARG "=1"
12798 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12799 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12800 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12801 ETH_I40E_USE_LATEST_VEC "=0|1");