drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static void i40e_configure_registers(struct i40e_hw *hw);
 415 static void i40e_hw_init(struct rte_eth_dev *dev);
 416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 418                         struct rte_eth_mirror_conf *mirror_conf,
 419                         uint8_t sw_id, uint8_t on);
 420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 421
 422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp,
 426                                            uint32_t flags);
 427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 428                                            struct timespec *timestamp);
 429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 430
 431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 432
 433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 434                                    struct timespec *timestamp);
 435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 436                                     const struct timespec *timestamp);
 437
 438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 439                                          uint16_t queue_id);
 440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 441                                           uint16_t queue_id);
 442
 443 static int i40e_get_regs(struct rte_eth_dev *dev,
 444                          struct rte_dev_reg_info *regs);
 445
 446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 447
 448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 449                            struct rte_dev_eeprom_info *eeprom);
 450
 451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 452                                       struct ether_addr *mac_addr);
 453
 454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 455
 456 static const struct rte_pci_id pci_id_i40e_map[] = {
 457         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 458         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 459         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 460         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 461         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 462         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 463         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 464         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_I_X722) },
 478         { .vendor_id = 0, /* sentinel */ },
 479 };
 480
 481 static const struct eth_dev_ops i40e_eth_dev_ops = {
 482         .dev_configure                = i40e_dev_configure,
 483         .dev_start                    = i40e_dev_start,
 484         .dev_stop                     = i40e_dev_stop,
 485         .dev_close                    = i40e_dev_close,
 486         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 487         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 488         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 489         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 490         .dev_set_link_up              = i40e_dev_set_link_up,
 491         .dev_set_link_down            = i40e_dev_set_link_down,
 492         .link_update                  = i40e_dev_link_update,
 493         .stats_get                    = i40e_dev_stats_get,
 494         .xstats_get                   = i40e_dev_xstats_get,
 495         .xstats_get_names             = i40e_dev_xstats_get_names,
 496         .stats_reset                  = i40e_dev_stats_reset,
 497         .xstats_reset                 = i40e_dev_stats_reset,
 498         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 499         .dev_infos_get                = i40e_dev_info_get,
 500         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 501         .vlan_filter_set              = i40e_vlan_filter_set,
 502         .vlan_tpid_set                = i40e_vlan_tpid_set,
 503         .vlan_offload_set             = i40e_vlan_offload_set,
 504         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 505         .vlan_pvid_set                = i40e_vlan_pvid_set,
 506         .rx_queue_start               = i40e_dev_rx_queue_start,
 507         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 508         .tx_queue_start               = i40e_dev_tx_queue_start,
 509         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 510         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 511         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 512         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 513         .rx_queue_release             = i40e_dev_rx_queue_release,
 514         .rx_queue_count               = i40e_dev_rx_queue_count,
 515         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 516         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 517         .tx_queue_release             = i40e_dev_tx_queue_release,
 518         .dev_led_on                   = i40e_dev_led_on,
 519         .dev_led_off                  = i40e_dev_led_off,
 520         .flow_ctrl_get                = i40e_flow_ctrl_get,
 521         .flow_ctrl_set                = i40e_flow_ctrl_set,
 522         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 523         .mac_addr_add                 = i40e_macaddr_add,
 524         .mac_addr_remove              = i40e_macaddr_remove,
 525         .reta_update                  = i40e_dev_rss_reta_update,
 526         .reta_query                   = i40e_dev_rss_reta_query,
 527         .rss_hash_update              = i40e_dev_rss_hash_update,
 528         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 529         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 530         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 531         .filter_ctrl                  = i40e_dev_filter_ctrl,
 532         .rxq_info_get                 = i40e_rxq_info_get,
 533         .txq_info_get                 = i40e_txq_info_get,
 534         .mirror_rule_set              = i40e_mirror_rule_set,
 535         .mirror_rule_reset            = i40e_mirror_rule_reset,
 536         .timesync_enable              = i40e_timesync_enable,
 537         .timesync_disable             = i40e_timesync_disable,
 538         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 539         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 540         .get_dcb_info                 = i40e_dev_get_dcb_info,
 541         .timesync_adjust_time         = i40e_timesync_adjust_time,
 542         .timesync_read_time           = i40e_timesync_read_time,
 543         .timesync_write_time          = i40e_timesync_write_time,
 544         .get_reg                      = i40e_get_regs,
 545         .get_eeprom_length            = i40e_get_eeprom_length,
 546         .get_eeprom                   = i40e_get_eeprom,
 547         .mac_addr_set                 = i40e_set_default_mac_addr,
 548         .mtu_set                      = i40e_dev_mtu_set,
 549 };
 550
 551 /* store statistics names and its offset in stats structure */
 552 struct rte_i40e_xstats_name_off {
 553         char name[RTE_ETH_XSTATS_NAME_SIZE];
 554         unsigned offset;
 555 };
 556
 557 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 558         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 559         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 560         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 561         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 562         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 563                 rx_unknown_protocol)},
 564         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 565         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 566         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 567         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 568 };
 569
 570 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 571                 sizeof(rte_i40e_stats_strings[0]))
 572
 573 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 574         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 575                 tx_dropped_link_down)},
 576         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 577         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 578                 illegal_bytes)},
 579         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 580         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 581                 mac_local_faults)},
 582         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 583                 mac_remote_faults)},
 584         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_length_errors)},
 586         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 587         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 588         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 589         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 590         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 591         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 592                 rx_size_127)},
 593         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 594                 rx_size_255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 596                 rx_size_511)},
 597         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 598                 rx_size_1023)},
 599         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 600                 rx_size_1522)},
 601         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 602                 rx_size_big)},
 603         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 604                 rx_undersize)},
 605         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 606                 rx_oversize)},
 607         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 608                 mac_short_packet_dropped)},
 609         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 610                 rx_fragments)},
 611         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 612         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 614                 tx_size_127)},
 615         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 616                 tx_size_255)},
 617         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 618                 tx_size_511)},
 619         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 620                 tx_size_1023)},
 621         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 622                 tx_size_1522)},
 623         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 624                 tx_size_big)},
 625         {"rx_flow_director_atr_match_packets",
 626                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 627         {"rx_flow_director_sb_match_packets",
 628                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 629         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 630                 tx_lpi_status)},
 631         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 632                 rx_lpi_status)},
 633         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 634                 tx_lpi_count)},
 635         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 636                 rx_lpi_count)},
 637 };
 638
 639 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 640                 sizeof(rte_i40e_hw_port_strings[0]))
 641
 642 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 643         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 644                 priority_xon_rx)},
 645         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 646                 priority_xoff_rx)},
 647 };
 648
 649 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 650                 sizeof(rte_i40e_rxq_prio_strings[0]))
 651
 652 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 653         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 654                 priority_xon_tx)},
 655         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 656                 priority_xoff_tx)},
 657         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 658                 priority_xon_2_xoff)},
 659 };
 660
 661 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 662                 sizeof(rte_i40e_txq_prio_strings[0]))
 663
 664 static struct eth_driver rte_i40e_pmd = {
 665         .pci_drv = {
 666                 .id_table = pci_id_i40e_map,
 667                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 668                         RTE_PCI_DRV_DETACHABLE,
 669                 .probe = rte_eth_dev_pci_probe,
 670                 .remove = rte_eth_dev_pci_remove,
 671         },
 672         .eth_dev_init = eth_i40e_dev_init,
 673         .eth_dev_uninit = eth_i40e_dev_uninit,
 674         .dev_private_size = sizeof(struct i40e_adapter),
 675 };
 676
 677 static inline int
 678 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 679                                      struct rte_eth_link *link)
 680 {
 681         struct rte_eth_link *dst = link;
 682         struct rte_eth_link *src = &(dev->data->dev_link);
 683
 684         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 685                                         *(uint64_t *)src) == 0)
 686                 return -1;
 687
 688         return 0;
 689 }
 690
 691 static inline int
 692 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 693                                       struct rte_eth_link *link)
 694 {
 695         struct rte_eth_link *dst = &(dev->data->dev_link);
 696         struct rte_eth_link *src = link;
 697
 698         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 699                                         *(uint64_t *)src) == 0)
 700                 return -1;
 701
 702         return 0;
 703 }
 704
 705 DRIVER_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 706 DRIVER_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 707
 708 /*
 709  * Initialize registers for flexible payload, which should be set by NVM.
 710  * This should be removed from code once it is fixed in NVM.
 711  */
 712 #ifndef I40E_GLQF_ORT
 713 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 714 #endif
 715 #ifndef I40E_GLQF_PIT
 716 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 717 #endif
 718
 719 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 720 {
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 731
 732         /* GLQF_PIT Registers */
 733         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 734         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 735 }
 736
 737 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 738
 739 /*
 740  * Add a ethertype filter to drop all flow control frames transmitted
 741  * from VSIs.
 742 */
 743 static void
 744 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 745 {
 746         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 747         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 748                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 749                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 750         int ret;
 751
 752         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 753                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 754                                 pf->main_vsi_seid, 0,
 755                                 TRUE, NULL, NULL);
 756         if (ret)
 757                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 758                                   " frames from VSIs.");
 759 }
 760
 761 static int
 762 floating_veb_list_handler(__rte_unused const char *key,
 763                           const char *floating_veb_value,
 764                           void *opaque)
 765 {
 766         int idx = 0;
 767         unsigned int count = 0;
 768         char *end = NULL;
 769         int min, max;
 770         bool *vf_floating_veb = opaque;
 771
 772         while (isblank(*floating_veb_value))
 773                 floating_veb_value++;
 774
 775         /* Reset floating VEB configuration for VFs */
 776         for (idx = 0; idx < I40E_MAX_VF; idx++)
 777                 vf_floating_veb[idx] = false;
 778
 779         min = I40E_MAX_VF;
 780         do {
 781                 while (isblank(*floating_veb_value))
 782                         floating_veb_value++;
 783                 if (*floating_veb_value == '\0')
 784                         return -1;
 785                 errno = 0;
 786                 idx = strtoul(floating_veb_value, &end, 10);
 787                 if (errno || end == NULL)
 788                         return -1;
 789                 while (isblank(*end))
 790                         end++;
 791                 if (*end == '-') {
 792                         min = idx;
 793                 } else if ((*end == ';') || (*end == '\0')) {
 794                         max = idx;
 795                         if (min == I40E_MAX_VF)
 796                                 min = idx;
 797                         if (max >= I40E_MAX_VF)
 798                                 max = I40E_MAX_VF - 1;
 799                         for (idx = min; idx <= max; idx++) {
 800                                 vf_floating_veb[idx] = true;
 801                                 count++;
 802                         }
 803                         min = I40E_MAX_VF;
 804                 } else {
 805                         return -1;
 806                 }
 807                 floating_veb_value = end + 1;
 808         } while (*end != '\0');
 809
 810         if (count == 0)
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 static void
 817 config_vf_floating_veb(struct rte_devargs *devargs,
 818                        uint16_t floating_veb,
 819                        bool *vf_floating_veb)
 820 {
 821         struct rte_kvargs *kvlist;
 822         int i;
 823         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 824
 825         if (!floating_veb)
 826                 return;
 827         /* All the VFs attach to the floating VEB by default
 828          * when the floating VEB is enabled.
 829          */
 830         for (i = 0; i < I40E_MAX_VF; i++)
 831                 vf_floating_veb[i] = true;
 832
 833         if (devargs == NULL)
 834                 return;
 835
 836         kvlist = rte_kvargs_parse(devargs->args, NULL);
 837         if (kvlist == NULL)
 838                 return;
 839
 840         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 841                 rte_kvargs_free(kvlist);
 842                 return;
 843         }
 844         /* When the floating_veb_list parameter exists, all the VFs
 845          * will attach to the legacy VEB firstly, then configure VFs
 846          * to the floating VEB according to the floating_veb_list.
 847          */
 848         if (rte_kvargs_process(kvlist, floating_veb_list,
 849                                floating_veb_list_handler,
 850                                vf_floating_veb) < 0) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         rte_kvargs_free(kvlist);
 855 }
 856
 857 static int
 858 i40e_check_floating_handler(__rte_unused const char *key,
 859                             const char *value,
 860                             __rte_unused void *opaque)
 861 {
 862         if (strcmp(value, "1"))
 863                 return -1;
 864
 865         return 0;
 866 }
 867
 868 static int
 869 is_floating_veb_supported(struct rte_devargs *devargs)
 870 {
 871         struct rte_kvargs *kvlist;
 872         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 873
 874         if (devargs == NULL)
 875                 return 0;
 876
 877         kvlist = rte_kvargs_parse(devargs->args, NULL);
 878         if (kvlist == NULL)
 879                 return 0;
 880
 881         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 882                 rte_kvargs_free(kvlist);
 883                 return 0;
 884         }
 885         /* Floating VEB is enabled when there's key-value:
 886          * enable_floating_veb=1
 887          */
 888         if (rte_kvargs_process(kvlist, floating_veb_key,
 889                                i40e_check_floating_handler, NULL) < 0) {
 890                 rte_kvargs_free(kvlist);
 891                 return 0;
 892         }
 893         rte_kvargs_free(kvlist);
 894
 895         return 1;
 896 }
 897
 898 static void
 899 config_floating_veb(struct rte_eth_dev *dev)
 900 {
 901         struct rte_pci_device *pci_dev = dev->pci_dev;
 902         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 903         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 904
 905         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 906
 907         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 908                 pf->floating_veb =
 909                         is_floating_veb_supported(pci_dev->device.devargs);
 910                 config_vf_floating_veb(pci_dev->device.devargs,
 911                                        pf->floating_veb,
 912                                        pf->floating_veb_list);
 913         } else {
 914                 pf->floating_veb = false;
 915         }
 916 }
 917
 918 static int
 919 eth_i40e_dev_init(struct rte_eth_dev *dev)
 920 {
 921         struct rte_pci_device *pci_dev;
 922         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 923         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 924         struct i40e_vsi *vsi;
 925         int ret;
 926         uint32_t len;
 927         uint8_t aq_fail = 0;
 928
 929         PMD_INIT_FUNC_TRACE();
 930
 931         dev->dev_ops = &i40e_eth_dev_ops;
 932         dev->rx_pkt_burst = i40e_recv_pkts;
 933         dev->tx_pkt_burst = i40e_xmit_pkts;
 934
 935         /* for secondary processes, we don't initialise any further as primary
 936          * has already done this work. Only check we don't need a different
 937          * RX function */
 938         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 939                 i40e_set_rx_function(dev);
 940                 i40e_set_tx_function(dev);
 941                 return 0;
 942         }
 943         pci_dev = dev->pci_dev;
 944
 945         rte_eth_copy_pci_info(dev, pci_dev);
 946
 947         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 948         pf->adapter->eth_dev = dev;
 949         pf->dev_data = dev->data;
 950
 951         hw->back = I40E_PF_TO_ADAPTER(pf);
 952         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 953         if (!hw->hw_addr) {
 954                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 955                              "as address is NULL");
 956                 return -ENODEV;
 957         }
 958
 959         hw->vendor_id = pci_dev->id.vendor_id;
 960         hw->device_id = pci_dev->id.device_id;
 961         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 962         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 963         hw->bus.device = pci_dev->addr.devid;
 964         hw->bus.func = pci_dev->addr.function;
 965         hw->adapter_stopped = 0;
 966
 967         /* Make sure all is clean before doing PF reset */
 968         i40e_clear_hw(hw);
 969
 970         /* Initialize the hardware */
 971         i40e_hw_init(dev);
 972
 973         /* Reset here to make sure all is clean for each PF */
 974         ret = i40e_pf_reset(hw);
 975         if (ret) {
 976                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 977                 return ret;
 978         }
 979
 980         /* Initialize the shared code (base driver) */
 981         ret = i40e_init_shared_code(hw);
 982         if (ret) {
 983                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 984                 return ret;
 985         }
 986
 987         /*
 988          * To work around the NVM issue,initialize registers
 989          * for flexible payload by software.
 990          * It should be removed once issues are fixed in NVM.
 991          */
 992         i40e_flex_payload_reg_init(hw);
 993
 994         /* Initialize the input set for filters (hash and fd) to default value */
 995         i40e_filter_input_set_init(pf);
 996
 997         /* Initialize the parameters for adminq */
 998         i40e_init_adminq_parameter(hw);
 999         ret = i40e_init_adminq(hw);
1000         if (ret != I40E_SUCCESS) {
1001                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1002                 return -EIO;
1003         }
1004         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1005                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1006                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1007                      ((hw->nvm.version >> 12) & 0xf),
1008                      ((hw->nvm.version >> 4) & 0xff),
1009                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1010
1011         /* Need the special FW version to support floating VEB */
1012         config_floating_veb(dev);
1013         /* Clear PXE mode */
1014         i40e_clear_pxe_mode(hw);
1015
1016         /*
1017          * On X710, performance number is far from the expectation on recent
1018          * firmware versions. The fix for this issue may not be integrated in
1019          * the following firmware version. So the workaround in software driver
1020          * is needed. It needs to modify the initial values of 3 internal only
1021          * registers. Note that the workaround can be removed when it is fixed
1022          * in firmware in the future.
1023          */
1024         i40e_configure_registers(hw);
1025
1026         /* Get hw capabilities */
1027         ret = i40e_get_cap(hw);
1028         if (ret != I40E_SUCCESS) {
1029                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1030                 goto err_get_capabilities;
1031         }
1032
1033         /* Initialize parameters for PF */
1034         ret = i40e_pf_parameter_init(dev);
1035         if (ret != 0) {
1036                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1037                 goto err_parameter_init;
1038         }
1039
1040         /* Initialize the queue management */
1041         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1042         if (ret < 0) {
1043                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1044                 goto err_qp_pool_init;
1045         }
1046         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1047                                 hw->func_caps.num_msix_vectors - 1);
1048         if (ret < 0) {
1049                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1050                 goto err_msix_pool_init;
1051         }
1052
1053         /* Initialize lan hmc */
1054         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1055                                 hw->func_caps.num_rx_qp, 0, 0);
1056         if (ret != I40E_SUCCESS) {
1057                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1058                 goto err_init_lan_hmc;
1059         }
1060
1061         /* Configure lan hmc */
1062         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1063         if (ret != I40E_SUCCESS) {
1064                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1065                 goto err_configure_lan_hmc;
1066         }
1067
1068         /* Get and check the mac address */
1069         i40e_get_mac_addr(hw, hw->mac.addr);
1070         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1071                 PMD_INIT_LOG(ERR, "mac address is not valid");
1072                 ret = -EIO;
1073                 goto err_get_mac_addr;
1074         }
1075         /* Copy the permanent MAC address */
1076         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1077                         (struct ether_addr *) hw->mac.perm_addr);
1078
1079         /* Disable flow control */
1080         hw->fc.requested_mode = I40E_FC_NONE;
1081         i40e_set_fc(hw, &aq_fail, TRUE);
1082
1083         /* Set the global registers with default ether type value */
1084         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1085         if (ret != I40E_SUCCESS) {
1086                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1087                              "VLAN ether type");
1088                 goto err_setup_pf_switch;
1089         }
1090
1091         /* PF setup, which includes VSI setup */
1092         ret = i40e_pf_setup(pf);
1093         if (ret) {
1094                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1095                 goto err_setup_pf_switch;
1096         }
1097
1098         /* reset all stats of the device, including pf and main vsi */
1099         i40e_dev_stats_reset(dev);
1100
1101         vsi = pf->main_vsi;
1102
1103         /* Disable double vlan by default */
1104         i40e_vsi_config_double_vlan(vsi, FALSE);
1105
1106         if (!vsi->max_macaddrs)
1107                 len = ETHER_ADDR_LEN;
1108         else
1109                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1110
1111         /* Should be after VSI initialized */
1112         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1113         if (!dev->data->mac_addrs) {
1114                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1115                                         "for storing mac address");
1116                 goto err_mac_alloc;
1117         }
1118         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1119                                         &dev->data->mac_addrs[0]);
1120
1121         /* initialize pf host driver to setup SRIOV resource if applicable */
1122         i40e_pf_host_init(dev);
1123
1124         /* register callback func to eal lib */
1125         rte_intr_callback_register(&(pci_dev->intr_handle),
1126                 i40e_dev_interrupt_handler, (void *)dev);
1127
1128         /* configure and enable device interrupt */
1129         i40e_pf_config_irq0(hw, TRUE);
1130         i40e_pf_enable_irq0(hw);
1131
1132         /* enable uio intr after callback register */
1133         rte_intr_enable(&(pci_dev->intr_handle));
1134         /*
1135          * Add an ethertype filter to drop all flow control frames transmitted
1136          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1137          * frames to wire.
1138          */
1139         i40e_add_tx_flow_control_drop_filter(pf);
1140
1141         /* Set the max frame size to 0x2600 by default,
1142          * in case other drivers changed the default value.
1143          */
1144         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1145
1146         /* initialize mirror rule list */
1147         TAILQ_INIT(&pf->mirror_list);
1148
1149         /* Init dcb to sw mode by default */
1150         ret = i40e_dcb_init_configure(dev, TRUE);
1151         if (ret != I40E_SUCCESS) {
1152                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1153                 pf->flags &= ~I40E_FLAG_DCB;
1154         }
1155
1156         return 0;
1157
1158 err_mac_alloc:
1159         i40e_vsi_release(pf->main_vsi);
1160 err_setup_pf_switch:
1161 err_get_mac_addr:
1162 err_configure_lan_hmc:
1163         (void)i40e_shutdown_lan_hmc(hw);
1164 err_init_lan_hmc:
1165         i40e_res_pool_destroy(&pf->msix_pool);
1166 err_msix_pool_init:
1167         i40e_res_pool_destroy(&pf->qp_pool);
1168 err_qp_pool_init:
1169 err_parameter_init:
1170 err_get_capabilities:
1171         (void)i40e_shutdown_adminq(hw);
1172
1173         return ret;
1174 }
1175
1176 static int
1177 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1178 {
1179         struct rte_pci_device *pci_dev;
1180         struct i40e_hw *hw;
1181         struct i40e_filter_control_settings settings;
1182         int ret;
1183         uint8_t aq_fail = 0;
1184
1185         PMD_INIT_FUNC_TRACE();
1186
1187         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1188                 return 0;
1189
1190         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191         pci_dev = dev->pci_dev;
1192
1193         if (hw->adapter_stopped == 0)
1194                 i40e_dev_close(dev);
1195
1196         dev->dev_ops = NULL;
1197         dev->rx_pkt_burst = NULL;
1198         dev->tx_pkt_burst = NULL;
1199
1200         /* Disable LLDP */
1201         ret = i40e_aq_stop_lldp(hw, true, NULL);
1202         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1203                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1204
1205         /* Clear PXE mode */
1206         i40e_clear_pxe_mode(hw);
1207
1208         /* Unconfigure filter control */
1209         memset(&settings, 0, sizeof(settings));
1210         ret = i40e_set_filter_control(hw, &settings);
1211         if (ret)
1212                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1213                                         ret);
1214
1215         /* Disable flow control */
1216         hw->fc.requested_mode = I40E_FC_NONE;
1217         i40e_set_fc(hw, &aq_fail, TRUE);
1218
1219         /* uninitialize pf host driver */
1220         i40e_pf_host_uninit(dev);
1221
1222         rte_free(dev->data->mac_addrs);
1223         dev->data->mac_addrs = NULL;
1224
1225         /* disable uio intr before callback unregister */
1226         rte_intr_disable(&(pci_dev->intr_handle));
1227
1228         /* register callback func to eal lib */
1229         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1230                 i40e_dev_interrupt_handler, (void *)dev);
1231
1232         return 0;
1233 }
1234
1235 static int
1236 i40e_dev_configure(struct rte_eth_dev *dev)
1237 {
1238         struct i40e_adapter *ad =
1239                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1240         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1241         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1242         int i, ret;
1243
1244         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1245          * bulk allocation or vector Rx preconditions we will reset it.
1246          */
1247         ad->rx_bulk_alloc_allowed = true;
1248         ad->rx_vec_allowed = true;
1249         ad->tx_simple_allowed = true;
1250         ad->tx_vec_allowed = true;
1251
1252         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1253                 ret = i40e_fdir_setup(pf);
1254                 if (ret != I40E_SUCCESS) {
1255                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1256                         return -ENOTSUP;
1257                 }
1258                 ret = i40e_fdir_configure(dev);
1259                 if (ret < 0) {
1260                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1261                         goto err;
1262                 }
1263         } else
1264                 i40e_fdir_teardown(pf);
1265
1266         ret = i40e_dev_init_vlan(dev);
1267         if (ret < 0)
1268                 goto err;
1269
1270         /* VMDQ setup.
1271          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1272          *  RSS setting have different requirements.
1273          *  General PMD driver call sequence are NIC init, configure,
1274          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1275          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1276          *  applicable. So, VMDQ setting has to be done before
1277          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1278          *  For RSS setting, it will try to calculate actual configured RX queue
1279          *  number, which will be available after rx_queue_setup(). dev_start()
1280          *  function is good to place RSS setup.
1281          */
1282         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1283                 ret = i40e_vmdq_setup(dev);
1284                 if (ret)
1285                         goto err;
1286         }
1287
1288         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1289                 ret = i40e_dcb_setup(dev);
1290                 if (ret) {
1291                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1292                         goto err_dcb;
1293                 }
1294         }
1295
1296         return 0;
1297
1298 err_dcb:
1299         /* need to release vmdq resource if exists */
1300         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1301                 i40e_vsi_release(pf->vmdq[i].vsi);
1302                 pf->vmdq[i].vsi = NULL;
1303         }
1304         rte_free(pf->vmdq);
1305         pf->vmdq = NULL;
1306 err:
1307         /* need to release fdir resource if exists */
1308         i40e_fdir_teardown(pf);
1309         return ret;
1310 }
1311
1312 void
1313 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1314 {
1315         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1316         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1317         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1318         uint16_t msix_vect = vsi->msix_intr;
1319         uint16_t i;
1320
1321         for (i = 0; i < vsi->nb_qps; i++) {
1322                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1323                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1324                 rte_wmb();
1325         }
1326
1327         if (vsi->type != I40E_VSI_SRIOV) {
1328                 if (!rte_intr_allow_others(intr_handle)) {
1329                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1330                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1331                         I40E_WRITE_REG(hw,
1332                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1333                                        0);
1334                 } else {
1335                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1336                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1337                         I40E_WRITE_REG(hw,
1338                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1339                                                        msix_vect - 1), 0);
1340                 }
1341         } else {
1342                 uint32_t reg;
1343                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1344                         vsi->user_param + (msix_vect - 1);
1345
1346                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1347                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1348         }
1349         I40E_WRITE_FLUSH(hw);
1350 }
1351
1352 static void
1353 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1354                        int base_queue, int nb_queue)
1355 {
1356         int i;
1357         uint32_t val;
1358         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1359
1360         /* Bind all RX queues to allocated MSIX interrupt */
1361         for (i = 0; i < nb_queue; i++) {
1362                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1363                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1364                         ((base_queue + i + 1) <<
1365                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1366                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1367                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1368
1369                 if (i == nb_queue - 1)
1370                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1371                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1372         }
1373
1374         /* Write first RX queue to Link list register as the head element */
1375         if (vsi->type != I40E_VSI_SRIOV) {
1376                 uint16_t interval =
1377                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1378
1379                 if (msix_vect == I40E_MISC_VEC_ID) {
1380                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1381                                        (base_queue <<
1382                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1383                                        (0x0 <<
1384                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1385                         I40E_WRITE_REG(hw,
1386                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1387                                        interval);
1388                 } else {
1389                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1390                                        (base_queue <<
1391                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1392                                        (0x0 <<
1393                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1394                         I40E_WRITE_REG(hw,
1395                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1396                                                        msix_vect - 1),
1397                                        interval);
1398                 }
1399         } else {
1400                 uint32_t reg;
1401
1402                 if (msix_vect == I40E_MISC_VEC_ID) {
1403                         I40E_WRITE_REG(hw,
1404                                        I40E_VPINT_LNKLST0(vsi->user_param),
1405                                        (base_queue <<
1406                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1407                                        (0x0 <<
1408                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1409                 } else {
1410                         /* num_msix_vectors_vf needs to minus irq0 */
1411                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1412                                 vsi->user_param + (msix_vect - 1);
1413
1414                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1415                                        (base_queue <<
1416                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1417                                        (0x0 <<
1418                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1419                 }
1420         }
1421
1422         I40E_WRITE_FLUSH(hw);
1423 }
1424
1425 void
1426 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1427 {
1428         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1429         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1430         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1431         uint16_t msix_vect = vsi->msix_intr;
1432         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1433         uint16_t queue_idx = 0;
1434         int record = 0;
1435         uint32_t val;
1436         int i;
1437
1438         for (i = 0; i < vsi->nb_qps; i++) {
1439                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1440                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1441         }
1442
1443         /* INTENA flag is not auto-cleared for interrupt */
1444         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1445         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1446                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1447                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1448         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1449
1450         /* VF bind interrupt */
1451         if (vsi->type == I40E_VSI_SRIOV) {
1452                 __vsi_queues_bind_intr(vsi, msix_vect,
1453                                        vsi->base_queue, vsi->nb_qps);
1454                 return;
1455         }
1456
1457         /* PF & VMDq bind interrupt */
1458         if (rte_intr_dp_is_en(intr_handle)) {
1459                 if (vsi->type == I40E_VSI_MAIN) {
1460                         queue_idx = 0;
1461                         record = 1;
1462                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1463                         struct i40e_vsi *main_vsi =
1464                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1465                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1466                         record = 1;
1467                 }
1468         }
1469
1470         for (i = 0; i < vsi->nb_used_qps; i++) {
1471                 if (nb_msix <= 1) {
1472                         if (!rte_intr_allow_others(intr_handle))
1473                                 /* allow to share MISC_VEC_ID */
1474                                 msix_vect = I40E_MISC_VEC_ID;
1475
1476                         /* no enough msix_vect, map all to one */
1477                         __vsi_queues_bind_intr(vsi, msix_vect,
1478                                                vsi->base_queue + i,
1479                                                vsi->nb_used_qps - i);
1480                         for (; !!record && i < vsi->nb_used_qps; i++)
1481                                 intr_handle->intr_vec[queue_idx + i] =
1482                                         msix_vect;
1483                         break;
1484                 }
1485                 /* 1:1 queue/msix_vect mapping */
1486                 __vsi_queues_bind_intr(vsi, msix_vect,
1487                                        vsi->base_queue + i, 1);
1488                 if (!!record)
1489                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1490
1491                 msix_vect++;
1492                 nb_msix--;
1493         }
1494 }
1495
1496 static void
1497 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1498 {
1499         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1500         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1501         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1502         uint16_t interval = i40e_calc_itr_interval(\
1503                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1504         uint16_t msix_intr, i;
1505
1506         if (rte_intr_allow_others(intr_handle))
1507                 for (i = 0; i < vsi->nb_msix; i++) {
1508                         msix_intr = vsi->msix_intr + i;
1509                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1510                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1511                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1512                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1513                                 (interval <<
1514                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1515                 }
1516         else
1517                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1518                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1519                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1520                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1521                                (interval <<
1522                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1523
1524         I40E_WRITE_FLUSH(hw);
1525 }
1526
1527 static void
1528 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1529 {
1530         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1531         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1532         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1533         uint16_t msix_intr, i;
1534
1535         if (rte_intr_allow_others(intr_handle))
1536                 for (i = 0; i < vsi->nb_msix; i++) {
1537                         msix_intr = vsi->msix_intr + i;
1538                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1539                                        0);
1540                 }
1541         else
1542                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1543
1544         I40E_WRITE_FLUSH(hw);
1545 }
1546
1547 static inline uint8_t
1548 i40e_parse_link_speeds(uint16_t link_speeds)
1549 {
1550         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1551
1552         if (link_speeds & ETH_LINK_SPEED_40G)
1553                 link_speed |= I40E_LINK_SPEED_40GB;
1554         if (link_speeds & ETH_LINK_SPEED_20G)
1555                 link_speed |= I40E_LINK_SPEED_20GB;
1556         if (link_speeds & ETH_LINK_SPEED_10G)
1557                 link_speed |= I40E_LINK_SPEED_10GB;
1558         if (link_speeds & ETH_LINK_SPEED_1G)
1559                 link_speed |= I40E_LINK_SPEED_1GB;
1560         if (link_speeds & ETH_LINK_SPEED_100M)
1561                 link_speed |= I40E_LINK_SPEED_100MB;
1562
1563         return link_speed;
1564 }
1565
1566 static int
1567 i40e_phy_conf_link(struct i40e_hw *hw,
1568                    uint8_t abilities,
1569                    uint8_t force_speed)
1570 {
1571         enum i40e_status_code status;
1572         struct i40e_aq_get_phy_abilities_resp phy_ab;
1573         struct i40e_aq_set_phy_config phy_conf;
1574         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1575                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1576                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1577                         I40E_AQ_PHY_FLAG_LOW_POWER;
1578         const uint8_t advt = I40E_LINK_SPEED_40GB |
1579                         I40E_LINK_SPEED_10GB |
1580                         I40E_LINK_SPEED_1GB |
1581                         I40E_LINK_SPEED_100MB;
1582         int ret = -ENOTSUP;
1583
1584
1585         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1586                                               NULL);
1587         if (status)
1588                 return ret;
1589
1590         memset(&phy_conf, 0, sizeof(phy_conf));
1591
1592         /* bits 0-2 use the values from get_phy_abilities_resp */
1593         abilities &= ~mask;
1594         abilities |= phy_ab.abilities & mask;
1595
1596         /* update ablities and speed */
1597         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1598                 phy_conf.link_speed = advt;
1599         else
1600                 phy_conf.link_speed = force_speed;
1601
1602         phy_conf.abilities = abilities;
1603
1604         /* use get_phy_abilities_resp value for the rest */
1605         phy_conf.phy_type = phy_ab.phy_type;
1606         phy_conf.eee_capability = phy_ab.eee_capability;
1607         phy_conf.eeer = phy_ab.eeer_val;
1608         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1609
1610         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1611                     phy_ab.abilities, phy_ab.link_speed);
1612         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1613                     phy_conf.abilities, phy_conf.link_speed);
1614
1615         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1616         if (status)
1617                 return ret;
1618
1619         return I40E_SUCCESS;
1620 }
1621
1622 static int
1623 i40e_apply_link_speed(struct rte_eth_dev *dev)
1624 {
1625         uint8_t speed;
1626         uint8_t abilities = 0;
1627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628         struct rte_eth_conf *conf = &dev->data->dev_conf;
1629
1630         speed = i40e_parse_link_speeds(conf->link_speeds);
1631         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1632         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1633                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1634         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1635
1636         /* Skip changing speed on 40G interfaces, FW does not support */
1637         if (i40e_is_40G_device(hw->device_id)) {
1638                 speed =  I40E_LINK_SPEED_UNKNOWN;
1639                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1640         }
1641
1642         return i40e_phy_conf_link(hw, abilities, speed);
1643 }
1644
1645 static int
1646 i40e_dev_start(struct rte_eth_dev *dev)
1647 {
1648         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1649         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         struct i40e_vsi *main_vsi = pf->main_vsi;
1651         int ret, i;
1652         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1653         uint32_t intr_vector = 0;
1654
1655         hw->adapter_stopped = 0;
1656
1657         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1658                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1659                              dev->data->port_id);
1660                 return -EINVAL;
1661         }
1662
1663         rte_intr_disable(intr_handle);
1664
1665         if ((rte_intr_cap_multiple(intr_handle) ||
1666              !RTE_ETH_DEV_SRIOV(dev).active) &&
1667             dev->data->dev_conf.intr_conf.rxq != 0) {
1668                 intr_vector = dev->data->nb_rx_queues;
1669                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1670                         return -1;
1671         }
1672
1673         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1674                 intr_handle->intr_vec =
1675                         rte_zmalloc("intr_vec",
1676                                     dev->data->nb_rx_queues * sizeof(int),
1677                                     0);
1678                 if (!intr_handle->intr_vec) {
1679                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1680                                      " intr_vec\n", dev->data->nb_rx_queues);
1681                         return -ENOMEM;
1682                 }
1683         }
1684
1685         /* Initialize VSI */
1686         ret = i40e_dev_rxtx_init(pf);
1687         if (ret != I40E_SUCCESS) {
1688                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1689                 goto err_up;
1690         }
1691
1692         /* Map queues with MSIX interrupt */
1693         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1694                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1695         i40e_vsi_queues_bind_intr(main_vsi);
1696         i40e_vsi_enable_queues_intr(main_vsi);
1697
1698         /* Map VMDQ VSI queues with MSIX interrupt */
1699         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1700                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1701                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1702                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1703         }
1704
1705         /* enable FDIR MSIX interrupt */
1706         if (pf->fdir.fdir_vsi) {
1707                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1708                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1709         }
1710
1711         /* Enable all queues which have been configured */
1712         ret = i40e_dev_switch_queues(pf, TRUE);
1713         if (ret != I40E_SUCCESS) {
1714                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1715                 goto err_up;
1716         }
1717
1718         /* Enable receiving broadcast packets */
1719         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1720         if (ret != I40E_SUCCESS)
1721                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1722
1723         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1724                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1725                                                 true, NULL);
1726                 if (ret != I40E_SUCCESS)
1727                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1728         }
1729
1730         /* Apply link configure */
1731         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1732                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1733                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1734                 PMD_DRV_LOG(ERR, "Invalid link setting");
1735                 goto err_up;
1736         }
1737         ret = i40e_apply_link_speed(dev);
1738         if (I40E_SUCCESS != ret) {
1739                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1740                 goto err_up;
1741         }
1742
1743         if (!rte_intr_allow_others(intr_handle)) {
1744                 rte_intr_callback_unregister(intr_handle,
1745                                              i40e_dev_interrupt_handler,
1746                                              (void *)dev);
1747                 /* configure and enable device interrupt */
1748                 i40e_pf_config_irq0(hw, FALSE);
1749                 i40e_pf_enable_irq0(hw);
1750
1751                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1752                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1753                                      " no intr multiplex\n");
1754         }
1755
1756         /* enable uio intr after callback register */
1757         rte_intr_enable(intr_handle);
1758
1759         return I40E_SUCCESS;
1760
1761 err_up:
1762         i40e_dev_switch_queues(pf, FALSE);
1763         i40e_dev_clear_queues(dev);
1764
1765         return ret;
1766 }
1767
1768 static void
1769 i40e_dev_stop(struct rte_eth_dev *dev)
1770 {
1771         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1772         struct i40e_vsi *main_vsi = pf->main_vsi;
1773         struct i40e_mirror_rule *p_mirror;
1774         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1775         int i;
1776
1777         /* Disable all queues */
1778         i40e_dev_switch_queues(pf, FALSE);
1779
1780         /* un-map queues with interrupt registers */
1781         i40e_vsi_disable_queues_intr(main_vsi);
1782         i40e_vsi_queues_unbind_intr(main_vsi);
1783
1784         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1785                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1786                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1787         }
1788
1789         if (pf->fdir.fdir_vsi) {
1790                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1791                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1792         }
1793         /* Clear all queues and release memory */
1794         i40e_dev_clear_queues(dev);
1795
1796         /* Set link down */
1797         i40e_dev_set_link_down(dev);
1798
1799         /* Remove all mirror rules */
1800         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1801                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1802                 rte_free(p_mirror);
1803         }
1804         pf->nb_mirror_rule = 0;
1805
1806         if (!rte_intr_allow_others(intr_handle))
1807                 /* resume to the default handler */
1808                 rte_intr_callback_register(intr_handle,
1809                                            i40e_dev_interrupt_handler,
1810                                            (void *)dev);
1811
1812         /* Clean datapath event and queue/vec mapping */
1813         rte_intr_efd_disable(intr_handle);
1814         if (intr_handle->intr_vec) {
1815                 rte_free(intr_handle->intr_vec);
1816                 intr_handle->intr_vec = NULL;
1817         }
1818 }
1819
1820 static void
1821 i40e_dev_close(struct rte_eth_dev *dev)
1822 {
1823         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1824         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         uint32_t reg;
1826         int i;
1827
1828         PMD_INIT_FUNC_TRACE();
1829
1830         i40e_dev_stop(dev);
1831         hw->adapter_stopped = 1;
1832         i40e_dev_free_queues(dev);
1833
1834         /* Disable interrupt */
1835         i40e_pf_disable_irq0(hw);
1836         rte_intr_disable(&(dev->pci_dev->intr_handle));
1837
1838         /* shutdown and destroy the HMC */
1839         i40e_shutdown_lan_hmc(hw);
1840
1841         /* release all the existing VSIs and VEBs */
1842         i40e_fdir_teardown(pf);
1843         i40e_vsi_release(pf->main_vsi);
1844
1845         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1846                 i40e_vsi_release(pf->vmdq[i].vsi);
1847                 pf->vmdq[i].vsi = NULL;
1848         }
1849
1850         rte_free(pf->vmdq);
1851         pf->vmdq = NULL;
1852
1853         /* shutdown the adminq */
1854         i40e_aq_queue_shutdown(hw, true);
1855         i40e_shutdown_adminq(hw);
1856
1857         i40e_res_pool_destroy(&pf->qp_pool);
1858         i40e_res_pool_destroy(&pf->msix_pool);
1859
1860         /* force a PF reset to clean anything leftover */
1861         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1862         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1863                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1864         I40E_WRITE_FLUSH(hw);
1865 }
1866
1867 static void
1868 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1869 {
1870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1871         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         struct i40e_vsi *vsi = pf->main_vsi;
1873         int status;
1874
1875         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1876                                                      true, NULL, true);
1877         if (status != I40E_SUCCESS)
1878                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1879
1880         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1881                                                         TRUE, NULL);
1882         if (status != I40E_SUCCESS)
1883                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1884
1885 }
1886
1887 static void
1888 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1889 {
1890         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1892         struct i40e_vsi *vsi = pf->main_vsi;
1893         int status;
1894
1895         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1896                                                      false, NULL, true);
1897         if (status != I40E_SUCCESS)
1898                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1899
1900         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1901                                                         false, NULL);
1902         if (status != I40E_SUCCESS)
1903                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1904 }
1905
1906 static void
1907 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1908 {
1909         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         struct i40e_vsi *vsi = pf->main_vsi;
1912         int ret;
1913
1914         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1915         if (ret != I40E_SUCCESS)
1916                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1917 }
1918
1919 static void
1920 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1921 {
1922         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1923         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924         struct i40e_vsi *vsi = pf->main_vsi;
1925         int ret;
1926
1927         if (dev->data->promiscuous == 1)
1928                 return; /* must remain in all_multicast mode */
1929
1930         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1931                                 vsi->seid, FALSE, NULL);
1932         if (ret != I40E_SUCCESS)
1933                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1934 }
1935
1936 /*
1937  * Set device link up.
1938  */
1939 static int
1940 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1941 {
1942         /* re-apply link speed setting */
1943         return i40e_apply_link_speed(dev);
1944 }
1945
1946 /*
1947  * Set device link down.
1948  */
1949 static int
1950 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1951 {
1952         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1953         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1954         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955
1956         return i40e_phy_conf_link(hw, abilities, speed);
1957 }
1958
1959 int
1960 i40e_dev_link_update(struct rte_eth_dev *dev,
1961                      int wait_to_complete)
1962 {
1963 #define CHECK_INTERVAL 100  /* 100ms */
1964 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1966         struct i40e_link_status link_status;
1967         struct rte_eth_link link, old;
1968         int status;
1969         unsigned rep_cnt = MAX_REPEAT_TIME;
1970
1971         memset(&link, 0, sizeof(link));
1972         memset(&old, 0, sizeof(old));
1973         memset(&link_status, 0, sizeof(link_status));
1974         rte_i40e_dev_atomic_read_link_status(dev, &old);
1975
1976         do {
1977                 /* Get link status information from hardware */
1978                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1979                 if (status != I40E_SUCCESS) {
1980                         link.link_speed = ETH_SPEED_NUM_100M;
1981                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1982                         PMD_DRV_LOG(ERR, "Failed to get link info");
1983                         goto out;
1984                 }
1985
1986                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1987                 if (!wait_to_complete)
1988                         break;
1989
1990                 rte_delay_ms(CHECK_INTERVAL);
1991         } while (!link.link_status && rep_cnt--);
1992
1993         if (!link.link_status)
1994                 goto out;
1995
1996         /* i40e uses full duplex only */
1997         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1998
1999         /* Parse the link status */
2000         switch (link_status.link_speed) {
2001         case I40E_LINK_SPEED_100MB:
2002                 link.link_speed = ETH_SPEED_NUM_100M;
2003                 break;
2004         case I40E_LINK_SPEED_1GB:
2005                 link.link_speed = ETH_SPEED_NUM_1G;
2006                 break;
2007         case I40E_LINK_SPEED_10GB:
2008                 link.link_speed = ETH_SPEED_NUM_10G;
2009                 break;
2010         case I40E_LINK_SPEED_20GB:
2011                 link.link_speed = ETH_SPEED_NUM_20G;
2012                 break;
2013         case I40E_LINK_SPEED_40GB:
2014                 link.link_speed = ETH_SPEED_NUM_40G;
2015                 break;
2016         default:
2017                 link.link_speed = ETH_SPEED_NUM_100M;
2018                 break;
2019         }
2020
2021         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2022                         ETH_LINK_SPEED_FIXED);
2023
2024 out:
2025         rte_i40e_dev_atomic_write_link_status(dev, &link);
2026         if (link.link_status == old.link_status)
2027                 return -1;
2028
2029         return 0;
2030 }
2031
2032 /* Get all the statistics of a VSI */
2033 void
2034 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2035 {
2036         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2037         struct i40e_eth_stats *nes = &vsi->eth_stats;
2038         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2039         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2040
2041         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2042                             vsi->offset_loaded, &oes->rx_bytes,
2043                             &nes->rx_bytes);
2044         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2045                             vsi->offset_loaded, &oes->rx_unicast,
2046                             &nes->rx_unicast);
2047         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2048                             vsi->offset_loaded, &oes->rx_multicast,
2049                             &nes->rx_multicast);
2050         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2051                             vsi->offset_loaded, &oes->rx_broadcast,
2052                             &nes->rx_broadcast);
2053         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2054                             &oes->rx_discards, &nes->rx_discards);
2055         /* GLV_REPC not supported */
2056         /* GLV_RMPC not supported */
2057         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2058                             &oes->rx_unknown_protocol,
2059                             &nes->rx_unknown_protocol);
2060         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2061                             vsi->offset_loaded, &oes->tx_bytes,
2062                             &nes->tx_bytes);
2063         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2064                             vsi->offset_loaded, &oes->tx_unicast,
2065                             &nes->tx_unicast);
2066         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2067                             vsi->offset_loaded, &oes->tx_multicast,
2068                             &nes->tx_multicast);
2069         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2070                             vsi->offset_loaded,  &oes->tx_broadcast,
2071                             &nes->tx_broadcast);
2072         /* GLV_TDPC not supported */
2073         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2074                             &oes->tx_errors, &nes->tx_errors);
2075         vsi->offset_loaded = true;
2076
2077         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2078                     vsi->vsi_id);
2079         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2080         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2081         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2082         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2083         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2084         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2085                     nes->rx_unknown_protocol);
2086         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2087         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2088         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2089         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2090         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2091         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2092         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2093                     vsi->vsi_id);
2094 }
2095
2096 static void
2097 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2098 {
2099         unsigned int i;
2100         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2101         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2102
2103         /* Get statistics of struct i40e_eth_stats */
2104         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2105                             I40E_GLPRT_GORCL(hw->port),
2106                             pf->offset_loaded, &os->eth.rx_bytes,
2107                             &ns->eth.rx_bytes);
2108         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2109                             I40E_GLPRT_UPRCL(hw->port),
2110                             pf->offset_loaded, &os->eth.rx_unicast,
2111                             &ns->eth.rx_unicast);
2112         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2113                             I40E_GLPRT_MPRCL(hw->port),
2114                             pf->offset_loaded, &os->eth.rx_multicast,
2115                             &ns->eth.rx_multicast);
2116         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2117                             I40E_GLPRT_BPRCL(hw->port),
2118                             pf->offset_loaded, &os->eth.rx_broadcast,
2119                             &ns->eth.rx_broadcast);
2120         /* Workaround: CRC size should not be included in byte statistics,
2121          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2122          */
2123         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2124                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2125
2126         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2127                             pf->offset_loaded, &os->eth.rx_discards,
2128                             &ns->eth.rx_discards);
2129         /* GLPRT_REPC not supported */
2130         /* GLPRT_RMPC not supported */
2131         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2132                             pf->offset_loaded,
2133                             &os->eth.rx_unknown_protocol,
2134                             &ns->eth.rx_unknown_protocol);
2135         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2136                             I40E_GLPRT_GOTCL(hw->port),
2137                             pf->offset_loaded, &os->eth.tx_bytes,
2138                             &ns->eth.tx_bytes);
2139         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2140                             I40E_GLPRT_UPTCL(hw->port),
2141                             pf->offset_loaded, &os->eth.tx_unicast,
2142                             &ns->eth.tx_unicast);
2143         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2144                             I40E_GLPRT_MPTCL(hw->port),
2145                             pf->offset_loaded, &os->eth.tx_multicast,
2146                             &ns->eth.tx_multicast);
2147         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2148                             I40E_GLPRT_BPTCL(hw->port),
2149                             pf->offset_loaded, &os->eth.tx_broadcast,
2150                             &ns->eth.tx_broadcast);
2151         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2152                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2153         /* GLPRT_TEPC not supported */
2154
2155         /* additional port specific stats */
2156         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2157                             pf->offset_loaded, &os->tx_dropped_link_down,
2158                             &ns->tx_dropped_link_down);
2159         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2160                             pf->offset_loaded, &os->crc_errors,
2161                             &ns->crc_errors);
2162         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2163                             pf->offset_loaded, &os->illegal_bytes,
2164                             &ns->illegal_bytes);
2165         /* GLPRT_ERRBC not supported */
2166         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2167                             pf->offset_loaded, &os->mac_local_faults,
2168                             &ns->mac_local_faults);
2169         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2170                             pf->offset_loaded, &os->mac_remote_faults,
2171                             &ns->mac_remote_faults);
2172         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2173                             pf->offset_loaded, &os->rx_length_errors,
2174                             &ns->rx_length_errors);
2175         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2176                             pf->offset_loaded, &os->link_xon_rx,
2177                             &ns->link_xon_rx);
2178         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2179                             pf->offset_loaded, &os->link_xoff_rx,
2180                             &ns->link_xoff_rx);
2181         for (i = 0; i < 8; i++) {
2182                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2183                                     pf->offset_loaded,
2184                                     &os->priority_xon_rx[i],
2185                                     &ns->priority_xon_rx[i]);
2186                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2187                                     pf->offset_loaded,
2188                                     &os->priority_xoff_rx[i],
2189                                     &ns->priority_xoff_rx[i]);
2190         }
2191         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2192                             pf->offset_loaded, &os->link_xon_tx,
2193                             &ns->link_xon_tx);
2194         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2195                             pf->offset_loaded, &os->link_xoff_tx,
2196                             &ns->link_xoff_tx);
2197         for (i = 0; i < 8; i++) {
2198                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2199                                     pf->offset_loaded,
2200                                     &os->priority_xon_tx[i],
2201                                     &ns->priority_xon_tx[i]);
2202                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2203                                     pf->offset_loaded,
2204                                     &os->priority_xoff_tx[i],
2205                                     &ns->priority_xoff_tx[i]);
2206                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2207                                     pf->offset_loaded,
2208                                     &os->priority_xon_2_xoff[i],
2209                                     &ns->priority_xon_2_xoff[i]);
2210         }
2211         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2212                             I40E_GLPRT_PRC64L(hw->port),
2213                             pf->offset_loaded, &os->rx_size_64,
2214                             &ns->rx_size_64);
2215         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2216                             I40E_GLPRT_PRC127L(hw->port),
2217                             pf->offset_loaded, &os->rx_size_127,
2218                             &ns->rx_size_127);
2219         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2220                             I40E_GLPRT_PRC255L(hw->port),
2221                             pf->offset_loaded, &os->rx_size_255,
2222                             &ns->rx_size_255);
2223         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2224                             I40E_GLPRT_PRC511L(hw->port),
2225                             pf->offset_loaded, &os->rx_size_511,
2226                             &ns->rx_size_511);
2227         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2228                             I40E_GLPRT_PRC1023L(hw->port),
2229                             pf->offset_loaded, &os->rx_size_1023,
2230                             &ns->rx_size_1023);
2231         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2232                             I40E_GLPRT_PRC1522L(hw->port),
2233                             pf->offset_loaded, &os->rx_size_1522,
2234                             &ns->rx_size_1522);
2235         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2236                             I40E_GLPRT_PRC9522L(hw->port),
2237                             pf->offset_loaded, &os->rx_size_big,
2238                             &ns->rx_size_big);
2239         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2240                             pf->offset_loaded, &os->rx_undersize,
2241                             &ns->rx_undersize);
2242         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2243                             pf->offset_loaded, &os->rx_fragments,
2244                             &ns->rx_fragments);
2245         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2246                             pf->offset_loaded, &os->rx_oversize,
2247                             &ns->rx_oversize);
2248         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2249                             pf->offset_loaded, &os->rx_jabber,
2250                             &ns->rx_jabber);
2251         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2252                             I40E_GLPRT_PTC64L(hw->port),
2253                             pf->offset_loaded, &os->tx_size_64,
2254                             &ns->tx_size_64);
2255         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2256                             I40E_GLPRT_PTC127L(hw->port),
2257                             pf->offset_loaded, &os->tx_size_127,
2258                             &ns->tx_size_127);
2259         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2260                             I40E_GLPRT_PTC255L(hw->port),
2261                             pf->offset_loaded, &os->tx_size_255,
2262                             &ns->tx_size_255);
2263         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2264                             I40E_GLPRT_PTC511L(hw->port),
2265                             pf->offset_loaded, &os->tx_size_511,
2266                             &ns->tx_size_511);
2267         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2268                             I40E_GLPRT_PTC1023L(hw->port),
2269                             pf->offset_loaded, &os->tx_size_1023,
2270                             &ns->tx_size_1023);
2271         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2272                             I40E_GLPRT_PTC1522L(hw->port),
2273                             pf->offset_loaded, &os->tx_size_1522,
2274                             &ns->tx_size_1522);
2275         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2276                             I40E_GLPRT_PTC9522L(hw->port),
2277                             pf->offset_loaded, &os->tx_size_big,
2278                             &ns->tx_size_big);
2279         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2280                            pf->offset_loaded,
2281                            &os->fd_sb_match, &ns->fd_sb_match);
2282         /* GLPRT_MSPDC not supported */
2283         /* GLPRT_XEC not supported */
2284
2285         pf->offset_loaded = true;
2286
2287         if (pf->main_vsi)
2288                 i40e_update_vsi_stats(pf->main_vsi);
2289 }
2290
2291 /* Get all statistics of a port */
2292 static void
2293 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2294 {
2295         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2296         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2298         unsigned i;
2299
2300         /* call read registers - updates values, now write them to struct */
2301         i40e_read_stats_registers(pf, hw);
2302
2303         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2304                         pf->main_vsi->eth_stats.rx_multicast +
2305                         pf->main_vsi->eth_stats.rx_broadcast -
2306                         pf->main_vsi->eth_stats.rx_discards;
2307         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2308                         pf->main_vsi->eth_stats.tx_multicast +
2309                         pf->main_vsi->eth_stats.tx_broadcast;
2310         stats->ibytes   = ns->eth.rx_bytes;
2311         stats->obytes   = ns->eth.tx_bytes;
2312         stats->oerrors  = ns->eth.tx_errors +
2313                         pf->main_vsi->eth_stats.tx_errors;
2314
2315         /* Rx Errors */
2316         stats->imissed  = ns->eth.rx_discards +
2317                         pf->main_vsi->eth_stats.rx_discards;
2318         stats->ierrors  = ns->crc_errors +
2319                         ns->rx_length_errors + ns->rx_undersize +
2320                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2321
2322         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2323         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2324         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2325         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2326         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2327         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2328         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2329                     ns->eth.rx_unknown_protocol);
2330         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2331         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2332         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2333         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2334         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2335         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2336
2337         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2338                     ns->tx_dropped_link_down);
2339         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2340         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2341                     ns->illegal_bytes);
2342         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2343         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2344                     ns->mac_local_faults);
2345         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2346                     ns->mac_remote_faults);
2347         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2348                     ns->rx_length_errors);
2349         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2350         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2351         for (i = 0; i < 8; i++) {
2352                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2353                                 i, ns->priority_xon_rx[i]);
2354                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2355                                 i, ns->priority_xoff_rx[i]);
2356         }
2357         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2358         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2359         for (i = 0; i < 8; i++) {
2360                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2361                                 i, ns->priority_xon_tx[i]);
2362                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2363                                 i, ns->priority_xoff_tx[i]);
2364                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2365                                 i, ns->priority_xon_2_xoff[i]);
2366         }
2367         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2368         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2369         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2370         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2371         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2372         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2373         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2374         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2375         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2376         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2377         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2378         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2379         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2380         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2381         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2382         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2383         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2384         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2385         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2386                         ns->mac_short_packet_dropped);
2387         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2388                     ns->checksum_error);
2389         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2390         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2391 }
2392
2393 /* Reset the statistics */
2394 static void
2395 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2396 {
2397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2398         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399
2400         /* Mark PF and VSI stats to update the offset, aka "reset" */
2401         pf->offset_loaded = false;
2402         if (pf->main_vsi)
2403                 pf->main_vsi->offset_loaded = false;
2404
2405         /* read the stats, reading current register values into offset */
2406         i40e_read_stats_registers(pf, hw);
2407 }
2408
2409 static uint32_t
2410 i40e_xstats_calc_num(void)
2411 {
2412         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2413                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2414                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2415 }
2416
2417 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2418                                      struct rte_eth_xstat_name *xstats_names,
2419                                      __rte_unused unsigned limit)
2420 {
2421         unsigned count = 0;
2422         unsigned i, prio;
2423
2424         if (xstats_names == NULL)
2425                 return i40e_xstats_calc_num();
2426
2427         /* Note: limit checked in rte_eth_xstats_names() */
2428
2429         /* Get stats from i40e_eth_stats struct */
2430         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2431                 snprintf(xstats_names[count].name,
2432                          sizeof(xstats_names[count].name),
2433                          "%s", rte_i40e_stats_strings[i].name);
2434                 count++;
2435         }
2436
2437         /* Get individiual stats from i40e_hw_port struct */
2438         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2439                 snprintf(xstats_names[count].name,
2440                         sizeof(xstats_names[count].name),
2441                          "%s", rte_i40e_hw_port_strings[i].name);
2442                 count++;
2443         }
2444
2445         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2446                 for (prio = 0; prio < 8; prio++) {
2447                         snprintf(xstats_names[count].name,
2448                                  sizeof(xstats_names[count].name),
2449                                  "rx_priority%u_%s", prio,
2450                                  rte_i40e_rxq_prio_strings[i].name);
2451                         count++;
2452                 }
2453         }
2454
2455         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2456                 for (prio = 0; prio < 8; prio++) {
2457                         snprintf(xstats_names[count].name,
2458                                  sizeof(xstats_names[count].name),
2459                                  "tx_priority%u_%s", prio,
2460                                  rte_i40e_txq_prio_strings[i].name);
2461                         count++;
2462                 }
2463         }
2464         return count;
2465 }
2466
2467 static int
2468 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2469                     unsigned n)
2470 {
2471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2473         unsigned i, count, prio;
2474         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2475
2476         count = i40e_xstats_calc_num();
2477         if (n < count)
2478                 return count;
2479
2480         i40e_read_stats_registers(pf, hw);
2481
2482         if (xstats == NULL)
2483                 return 0;
2484
2485         count = 0;
2486
2487         /* Get stats from i40e_eth_stats struct */
2488         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2489                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2490                         rte_i40e_stats_strings[i].offset);
2491                 count++;
2492         }
2493
2494         /* Get individiual stats from i40e_hw_port struct */
2495         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2496                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2497                         rte_i40e_hw_port_strings[i].offset);
2498                 count++;
2499         }
2500
2501         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2502                 for (prio = 0; prio < 8; prio++) {
2503                         xstats[count].value =
2504                                 *(uint64_t *)(((char *)hw_stats) +
2505                                 rte_i40e_rxq_prio_strings[i].offset +
2506                                 (sizeof(uint64_t) * prio));
2507                         count++;
2508                 }
2509         }
2510
2511         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2512                 for (prio = 0; prio < 8; prio++) {
2513                         xstats[count].value =
2514                                 *(uint64_t *)(((char *)hw_stats) +
2515                                 rte_i40e_txq_prio_strings[i].offset +
2516                                 (sizeof(uint64_t) * prio));
2517                         count++;
2518                 }
2519         }
2520
2521         return count;
2522 }
2523
2524 static int
2525 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2526                                  __rte_unused uint16_t queue_id,
2527                                  __rte_unused uint8_t stat_idx,
2528                                  __rte_unused uint8_t is_rx)
2529 {
2530         PMD_INIT_FUNC_TRACE();
2531
2532         return -ENOSYS;
2533 }
2534
2535 static void
2536 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2537 {
2538         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2540         struct i40e_vsi *vsi = pf->main_vsi;
2541
2542         dev_info->max_rx_queues = vsi->nb_qps;
2543         dev_info->max_tx_queues = vsi->nb_qps;
2544         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2545         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2546         dev_info->max_mac_addrs = vsi->max_macaddrs;
2547         dev_info->max_vfs = dev->pci_dev->max_vfs;
2548         dev_info->rx_offload_capa =
2549                 DEV_RX_OFFLOAD_VLAN_STRIP |
2550                 DEV_RX_OFFLOAD_QINQ_STRIP |
2551                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2552                 DEV_RX_OFFLOAD_UDP_CKSUM |
2553                 DEV_RX_OFFLOAD_TCP_CKSUM;
2554         dev_info->tx_offload_capa =
2555                 DEV_TX_OFFLOAD_VLAN_INSERT |
2556                 DEV_TX_OFFLOAD_QINQ_INSERT |
2557                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2558                 DEV_TX_OFFLOAD_UDP_CKSUM |
2559                 DEV_TX_OFFLOAD_TCP_CKSUM |
2560                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2561                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2562                 DEV_TX_OFFLOAD_TCP_TSO;
2563         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2564                                                 sizeof(uint32_t);
2565         dev_info->reta_size = pf->hash_lut_size;
2566         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2567
2568         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2569                 .rx_thresh = {
2570                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2571                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2572                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2573                 },
2574                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2575                 .rx_drop_en = 0,
2576         };
2577
2578         dev_info->default_txconf = (struct rte_eth_txconf) {
2579                 .tx_thresh = {
2580                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2581                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2582                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2583                 },
2584                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2585                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2586                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2587                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2588         };
2589
2590         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2591                 .nb_max = I40E_MAX_RING_DESC,
2592                 .nb_min = I40E_MIN_RING_DESC,
2593                 .nb_align = I40E_ALIGN_RING_DESC,
2594         };
2595
2596         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2597                 .nb_max = I40E_MAX_RING_DESC,
2598                 .nb_min = I40E_MIN_RING_DESC,
2599                 .nb_align = I40E_ALIGN_RING_DESC,
2600         };
2601
2602         if (pf->flags & I40E_FLAG_VMDQ) {
2603                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2604                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2605                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2606                                                 pf->max_nb_vmdq_vsi;
2607                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2608                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2609                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2610         }
2611
2612         if (i40e_is_40G_device(hw->device_id))
2613                 /* For XL710 */
2614                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2615         else
2616                 /* For X710 */
2617                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2618 }
2619
2620 static int
2621 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2622 {
2623         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2624         struct i40e_vsi *vsi = pf->main_vsi;
2625         PMD_INIT_FUNC_TRACE();
2626
2627         if (on)
2628                 return i40e_vsi_add_vlan(vsi, vlan_id);
2629         else
2630                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2631 }
2632
2633 static int
2634 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2635                    enum rte_vlan_type vlan_type,
2636                    uint16_t tpid)
2637 {
2638         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639         uint64_t reg_r = 0, reg_w = 0;
2640         uint16_t reg_id = 0;
2641         int ret = 0;
2642         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2643
2644         switch (vlan_type) {
2645         case ETH_VLAN_TYPE_OUTER:
2646                 if (qinq)
2647                         reg_id = 2;
2648                 else
2649                         reg_id = 3;
2650                 break;
2651         case ETH_VLAN_TYPE_INNER:
2652                 if (qinq)
2653                         reg_id = 3;
2654                 else {
2655                         ret = -EINVAL;
2656                         PMD_DRV_LOG(ERR,
2657                                 "Unsupported vlan type in single vlan.\n");
2658                         return ret;
2659                 }
2660                 break;
2661         default:
2662                 ret = -EINVAL;
2663                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2664                 return ret;
2665         }
2666         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2667                                           &reg_r, NULL);
2668         if (ret != I40E_SUCCESS) {
2669                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2670                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2671                 ret = -EIO;
2672                 return ret;
2673         }
2674         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2675                     "0x%08"PRIx64"", reg_id, reg_r);
2676
2677         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2678         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2679         if (reg_r == reg_w) {
2680                 ret = 0;
2681                 PMD_DRV_LOG(DEBUG, "No need to write");
2682                 return ret;
2683         }
2684
2685         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2686                                            reg_w, NULL);
2687         if (ret != I40E_SUCCESS) {
2688                 ret = -EIO;
2689                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2690                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2691                 return ret;
2692         }
2693         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2694                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2695
2696         return ret;
2697 }
2698
2699 static void
2700 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2701 {
2702         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2703         struct i40e_vsi *vsi = pf->main_vsi;
2704
2705         if (mask & ETH_VLAN_FILTER_MASK) {
2706                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2707                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2708                 else
2709                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2710         }
2711
2712         if (mask & ETH_VLAN_STRIP_MASK) {
2713                 /* Enable or disable VLAN stripping */
2714                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2715                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2716                 else
2717                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2718         }
2719
2720         if (mask & ETH_VLAN_EXTEND_MASK) {
2721                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2722                         i40e_vsi_config_double_vlan(vsi, TRUE);
2723                         /* Set global registers with default ether type value */
2724                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2725                                            ETHER_TYPE_VLAN);
2726                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2727                                            ETHER_TYPE_VLAN);
2728                 }
2729                 else
2730                         i40e_vsi_config_double_vlan(vsi, FALSE);
2731         }
2732 }
2733
2734 static void
2735 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2736                           __rte_unused uint16_t queue,
2737                           __rte_unused int on)
2738 {
2739         PMD_INIT_FUNC_TRACE();
2740 }
2741
2742 static int
2743 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2744 {
2745         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2746         struct i40e_vsi *vsi = pf->main_vsi;
2747         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2748         struct i40e_vsi_vlan_pvid_info info;
2749
2750         memset(&info, 0, sizeof(info));
2751         info.on = on;
2752         if (info.on)
2753                 info.config.pvid = pvid;
2754         else {
2755                 info.config.reject.tagged =
2756                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2757                 info.config.reject.untagged =
2758                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2759         }
2760
2761         return i40e_vsi_vlan_pvid_set(vsi, &info);
2762 }
2763
2764 static int
2765 i40e_dev_led_on(struct rte_eth_dev *dev)
2766 {
2767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2768         uint32_t mode = i40e_led_get(hw);
2769
2770         if (mode == 0)
2771                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2772
2773         return 0;
2774 }
2775
2776 static int
2777 i40e_dev_led_off(struct rte_eth_dev *dev)
2778 {
2779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2780         uint32_t mode = i40e_led_get(hw);
2781
2782         if (mode != 0)
2783                 i40e_led_set(hw, 0, false);
2784
2785         return 0;
2786 }
2787
2788 static int
2789 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2790 {
2791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2793
2794         fc_conf->pause_time = pf->fc_conf.pause_time;
2795         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2796         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2797
2798          /* Return current mode according to actual setting*/
2799         switch (hw->fc.current_mode) {
2800         case I40E_FC_FULL:
2801                 fc_conf->mode = RTE_FC_FULL;
2802                 break;
2803         case I40E_FC_TX_PAUSE:
2804                 fc_conf->mode = RTE_FC_TX_PAUSE;
2805                 break;
2806         case I40E_FC_RX_PAUSE:
2807                 fc_conf->mode = RTE_FC_RX_PAUSE;
2808                 break;
2809         case I40E_FC_NONE:
2810         default:
2811                 fc_conf->mode = RTE_FC_NONE;
2812         };
2813
2814         return 0;
2815 }
2816
2817 static int
2818 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2819 {
2820         uint32_t mflcn_reg, fctrl_reg, reg;
2821         uint32_t max_high_water;
2822         uint8_t i, aq_failure;
2823         int err;
2824         struct i40e_hw *hw;
2825         struct i40e_pf *pf;
2826         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2827                 [RTE_FC_NONE] = I40E_FC_NONE,
2828                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2829                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2830                 [RTE_FC_FULL] = I40E_FC_FULL
2831         };
2832
2833         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2834
2835         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2836         if ((fc_conf->high_water > max_high_water) ||
2837                         (fc_conf->high_water < fc_conf->low_water)) {
2838                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2839                         "High_water must <= %d.", max_high_water);
2840                 return -EINVAL;
2841         }
2842
2843         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2845         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2846
2847         pf->fc_conf.pause_time = fc_conf->pause_time;
2848         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2849         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2850
2851         PMD_INIT_FUNC_TRACE();
2852
2853         /* All the link flow control related enable/disable register
2854          * configuration is handle by the F/W
2855          */
2856         err = i40e_set_fc(hw, &aq_failure, true);
2857         if (err < 0)
2858                 return -ENOSYS;
2859
2860         if (i40e_is_40G_device(hw->device_id)) {
2861                 /* Configure flow control refresh threshold,
2862                  * the value for stat_tx_pause_refresh_timer[8]
2863                  * is used for global pause operation.
2864                  */
2865
2866                 I40E_WRITE_REG(hw,
2867                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2868                                pf->fc_conf.pause_time);
2869
2870                 /* configure the timer value included in transmitted pause
2871                  * frame,
2872                  * the value for stat_tx_pause_quanta[8] is used for global
2873                  * pause operation
2874                  */
2875                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2876                                pf->fc_conf.pause_time);
2877
2878                 fctrl_reg = I40E_READ_REG(hw,
2879                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2880
2881                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2882                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2883                 else
2884                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2885
2886                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2887                                fctrl_reg);
2888         } else {
2889                 /* Configure pause time (2 TCs per register) */
2890                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2891                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2892                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2893
2894                 /* Configure flow control refresh threshold value */
2895                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2896                                pf->fc_conf.pause_time / 2);
2897
2898                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2899
2900                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2901                  *depending on configuration
2902                  */
2903                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2904                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2905                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2906                 } else {
2907                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2908                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2909                 }
2910
2911                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2912         }
2913
2914         /* config the water marker both based on the packets and bytes */
2915         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2916                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2917                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2918         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2919                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2920                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2921         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2922                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2923                        << I40E_KILOSHIFT);
2924         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2925                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2926                        << I40E_KILOSHIFT);
2927
2928         I40E_WRITE_FLUSH(hw);
2929
2930         return 0;
2931 }
2932
2933 static int
2934 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2935                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2936 {
2937         PMD_INIT_FUNC_TRACE();
2938
2939         return -ENOSYS;
2940 }
2941
2942 /* Add a MAC address, and update filters */
2943 static void
2944 i40e_macaddr_add(struct rte_eth_dev *dev,
2945                  struct ether_addr *mac_addr,
2946                  __rte_unused uint32_t index,
2947                  uint32_t pool)
2948 {
2949         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2950         struct i40e_mac_filter_info mac_filter;
2951         struct i40e_vsi *vsi;
2952         int ret;
2953
2954         /* If VMDQ not enabled or configured, return */
2955         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2956                           !pf->nb_cfg_vmdq_vsi)) {
2957                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2958                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2959                         pool);
2960                 return;
2961         }
2962
2963         if (pool > pf->nb_cfg_vmdq_vsi) {
2964                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2965                                 pool, pf->nb_cfg_vmdq_vsi);
2966                 return;
2967         }
2968
2969         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2970         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2971                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2972         else
2973                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2974
2975         if (pool == 0)
2976                 vsi = pf->main_vsi;
2977         else
2978                 vsi = pf->vmdq[pool - 1].vsi;
2979
2980         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2981         if (ret != I40E_SUCCESS) {
2982                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2983                 return;
2984         }
2985 }
2986
2987 /* Remove a MAC address, and update filters */
2988 static void
2989 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2990 {
2991         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2992         struct i40e_vsi *vsi;
2993         struct rte_eth_dev_data *data = dev->data;
2994         struct ether_addr *macaddr;
2995         int ret;
2996         uint32_t i;
2997         uint64_t pool_sel;
2998
2999         macaddr = &(data->mac_addrs[index]);
3000
3001         pool_sel = dev->data->mac_pool_sel[index];
3002
3003         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3004                 if (pool_sel & (1ULL << i)) {
3005                         if (i == 0)
3006                                 vsi = pf->main_vsi;
3007                         else {
3008                                 /* No VMDQ pool enabled or configured */
3009                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3010                                         (i > pf->nb_cfg_vmdq_vsi)) {
3011                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3012                                                         "/configured");
3013                                         return;
3014                                 }
3015                                 vsi = pf->vmdq[i - 1].vsi;
3016                         }
3017                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3018
3019                         if (ret) {
3020                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3021                                 return;
3022                         }
3023                 }
3024         }
3025 }
3026
3027 /* Set perfect match or hash match of MAC and VLAN for a VF */
3028 static int
3029 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3030                  struct rte_eth_mac_filter *filter,
3031                  bool add)
3032 {
3033         struct i40e_hw *hw;
3034         struct i40e_mac_filter_info mac_filter;
3035         struct ether_addr old_mac;
3036         struct ether_addr *new_mac;
3037         struct i40e_pf_vf *vf = NULL;
3038         uint16_t vf_id;
3039         int ret;
3040
3041         if (pf == NULL) {
3042                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3043                 return -EINVAL;
3044         }
3045         hw = I40E_PF_TO_HW(pf);
3046
3047         if (filter == NULL) {
3048                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3049                 return -EINVAL;
3050         }
3051
3052         new_mac = &filter->mac_addr;
3053
3054         if (is_zero_ether_addr(new_mac)) {
3055                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3056                 return -EINVAL;
3057         }
3058
3059         vf_id = filter->dst_id;
3060
3061         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3062                 PMD_DRV_LOG(ERR, "Invalid argument.");
3063                 return -EINVAL;
3064         }
3065         vf = &pf->vfs[vf_id];
3066
3067         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3068                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3069                 return -EINVAL;
3070         }
3071
3072         if (add) {
3073                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3074                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3075                                 ETHER_ADDR_LEN);
3076                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3077                                  ETHER_ADDR_LEN);
3078
3079                 mac_filter.filter_type = filter->filter_type;
3080                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3081                 if (ret != I40E_SUCCESS) {
3082                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3083                         return -1;
3084                 }
3085                 ether_addr_copy(new_mac, &pf->dev_addr);
3086         } else {
3087                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3088                                 ETHER_ADDR_LEN);
3089                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3090                 if (ret != I40E_SUCCESS) {
3091                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3092                         return -1;
3093                 }
3094
3095                 /* Clear device address as it has been removed */
3096                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3097                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3098         }
3099
3100         return 0;
3101 }
3102
3103 /* MAC filter handle */
3104 static int
3105 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3106                 void *arg)
3107 {
3108         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3109         struct rte_eth_mac_filter *filter;
3110         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3111         int ret = I40E_NOT_SUPPORTED;
3112
3113         filter = (struct rte_eth_mac_filter *)(arg);
3114
3115         switch (filter_op) {
3116         case RTE_ETH_FILTER_NOP:
3117                 ret = I40E_SUCCESS;
3118                 break;
3119         case RTE_ETH_FILTER_ADD:
3120                 i40e_pf_disable_irq0(hw);
3121                 if (filter->is_vf)
3122                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3123                 i40e_pf_enable_irq0(hw);
3124                 break;
3125         case RTE_ETH_FILTER_DELETE:
3126                 i40e_pf_disable_irq0(hw);
3127                 if (filter->is_vf)
3128                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3129                 i40e_pf_enable_irq0(hw);
3130                 break;
3131         default:
3132                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3133                 ret = I40E_ERR_PARAM;
3134                 break;
3135         }
3136
3137         return ret;
3138 }
3139
3140 static int
3141 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3142 {
3143         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3144         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3145         int ret;
3146
3147         if (!lut)
3148                 return -EINVAL;
3149
3150         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3151                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3152                                           lut, lut_size);
3153                 if (ret) {
3154                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3155                         return ret;
3156                 }
3157         } else {
3158                 uint32_t *lut_dw = (uint32_t *)lut;
3159                 uint16_t i, lut_size_dw = lut_size / 4;
3160
3161                 for (i = 0; i < lut_size_dw; i++)
3162                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3163         }
3164
3165         return 0;
3166 }
3167
3168 static int
3169 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3170 {
3171         struct i40e_pf *pf;
3172         struct i40e_hw *hw;
3173         int ret;
3174
3175         if (!vsi || !lut)
3176                 return -EINVAL;
3177
3178         pf = I40E_VSI_TO_PF(vsi);
3179         hw = I40E_VSI_TO_HW(vsi);
3180
3181         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3182                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3183                                           lut, lut_size);
3184                 if (ret) {
3185                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3186                         return ret;
3187                 }
3188         } else {
3189                 uint32_t *lut_dw = (uint32_t *)lut;
3190                 uint16_t i, lut_size_dw = lut_size / 4;
3191
3192                 for (i = 0; i < lut_size_dw; i++)
3193                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3194                 I40E_WRITE_FLUSH(hw);
3195         }
3196
3197         return 0;
3198 }
3199
3200 static int
3201 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3202                          struct rte_eth_rss_reta_entry64 *reta_conf,
3203                          uint16_t reta_size)
3204 {
3205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3206         uint16_t i, lut_size = pf->hash_lut_size;
3207         uint16_t idx, shift;
3208         uint8_t *lut;
3209         int ret;
3210
3211         if (reta_size != lut_size ||
3212                 reta_size > ETH_RSS_RETA_SIZE_512) {
3213                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3214                         "(%d) doesn't match the number hardware can supported "
3215                                         "(%d)\n", reta_size, lut_size);
3216                 return -EINVAL;
3217         }
3218
3219         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3220         if (!lut) {
3221                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3222                 return -ENOMEM;
3223         }
3224         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3225         if (ret)
3226                 goto out;
3227         for (i = 0; i < reta_size; i++) {
3228                 idx = i / RTE_RETA_GROUP_SIZE;
3229                 shift = i % RTE_RETA_GROUP_SIZE;
3230                 if (reta_conf[idx].mask & (1ULL << shift))
3231                         lut[i] = reta_conf[idx].reta[shift];
3232         }
3233         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3234
3235 out:
3236         rte_free(lut);
3237
3238         return ret;
3239 }
3240
3241 static int
3242 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3243                         struct rte_eth_rss_reta_entry64 *reta_conf,
3244                         uint16_t reta_size)
3245 {
3246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3247         uint16_t i, lut_size = pf->hash_lut_size;
3248         uint16_t idx, shift;
3249         uint8_t *lut;
3250         int ret;
3251
3252         if (reta_size != lut_size ||
3253                 reta_size > ETH_RSS_RETA_SIZE_512) {
3254                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3255                         "(%d) doesn't match the number hardware can supported "
3256                                         "(%d)\n", reta_size, lut_size);
3257                 return -EINVAL;
3258         }
3259
3260         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3261         if (!lut) {
3262                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3263                 return -ENOMEM;
3264         }
3265
3266         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3267         if (ret)
3268                 goto out;
3269         for (i = 0; i < reta_size; i++) {
3270                 idx = i / RTE_RETA_GROUP_SIZE;
3271                 shift = i % RTE_RETA_GROUP_SIZE;
3272                 if (reta_conf[idx].mask & (1ULL << shift))
3273                         reta_conf[idx].reta[shift] = lut[i];
3274         }
3275
3276 out:
3277         rte_free(lut);
3278
3279         return ret;
3280 }
3281
3282 /**
3283  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3284  * @hw:   pointer to the HW structure
3285  * @mem:  pointer to mem struct to fill out
3286  * @size: size of memory requested
3287  * @alignment: what to align the allocation to
3288  **/
3289 enum i40e_status_code
3290 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3291                         struct i40e_dma_mem *mem,
3292                         u64 size,
3293                         u32 alignment)
3294 {
3295         const struct rte_memzone *mz = NULL;
3296         char z_name[RTE_MEMZONE_NAMESIZE];
3297
3298         if (!mem)
3299                 return I40E_ERR_PARAM;
3300
3301         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3302         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3303                                          alignment, RTE_PGSIZE_2M);
3304         if (!mz)
3305                 return I40E_ERR_NO_MEMORY;
3306
3307         mem->size = size;
3308         mem->va = mz->addr;
3309         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3310         mem->zone = (const void *)mz;
3311         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3312                     "%"PRIu64, mz->name, mem->pa);
3313
3314         return I40E_SUCCESS;
3315 }
3316
3317 /**
3318  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3319  * @hw:   pointer to the HW structure
3320  * @mem:  ptr to mem struct to free
3321  **/
3322 enum i40e_status_code
3323 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3324                     struct i40e_dma_mem *mem)
3325 {
3326         if (!mem)
3327                 return I40E_ERR_PARAM;
3328
3329         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3330                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3331                     mem->pa);
3332         rte_memzone_free((const struct rte_memzone *)mem->zone);
3333         mem->zone = NULL;
3334         mem->va = NULL;
3335         mem->pa = (u64)0;
3336
3337         return I40E_SUCCESS;
3338 }
3339
3340 /**
3341  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3342  * @hw:   pointer to the HW structure
3343  * @mem:  pointer to mem struct to fill out
3344  * @size: size of memory requested
3345  **/
3346 enum i40e_status_code
3347 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3348                          struct i40e_virt_mem *mem,
3349                          u32 size)
3350 {
3351         if (!mem)
3352                 return I40E_ERR_PARAM;
3353
3354         mem->size = size;
3355         mem->va = rte_zmalloc("i40e", size, 0);
3356
3357         if (mem->va)
3358                 return I40E_SUCCESS;
3359         else
3360                 return I40E_ERR_NO_MEMORY;
3361 }
3362
3363 /**
3364  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3365  * @hw:   pointer to the HW structure
3366  * @mem:  pointer to mem struct to free
3367  **/
3368 enum i40e_status_code
3369 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3370                      struct i40e_virt_mem *mem)
3371 {
3372         if (!mem)
3373                 return I40E_ERR_PARAM;
3374
3375         rte_free(mem->va);
3376         mem->va = NULL;
3377
3378         return I40E_SUCCESS;
3379 }
3380
3381 void
3382 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3383 {
3384         rte_spinlock_init(&sp->spinlock);
3385 }
3386
3387 void
3388 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3389 {
3390         rte_spinlock_lock(&sp->spinlock);
3391 }
3392
3393 void
3394 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3395 {
3396         rte_spinlock_unlock(&sp->spinlock);
3397 }
3398
3399 void
3400 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3401 {
3402         return;
3403 }
3404
3405 /**
3406  * Get the hardware capabilities, which will be parsed
3407  * and saved into struct i40e_hw.
3408  */
3409 static int
3410 i40e_get_cap(struct i40e_hw *hw)
3411 {
3412         struct i40e_aqc_list_capabilities_element_resp *buf;
3413         uint16_t len, size = 0;
3414         int ret;
3415
3416         /* Calculate a huge enough buff for saving response data temporarily */
3417         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3418                                                 I40E_MAX_CAP_ELE_NUM;
3419         buf = rte_zmalloc("i40e", len, 0);
3420         if (!buf) {
3421                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3422                 return I40E_ERR_NO_MEMORY;
3423         }
3424
3425         /* Get, parse the capabilities and save it to hw */
3426         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3427                         i40e_aqc_opc_list_func_capabilities, NULL);
3428         if (ret != I40E_SUCCESS)
3429                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3430
3431         /* Free the temporary buffer after being used */
3432         rte_free(buf);
3433
3434         return ret;
3435 }
3436
3437 static int
3438 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3439 {
3440         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3441         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3442         uint16_t qp_count = 0, vsi_count = 0;
3443
3444         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3445                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3446                 return -EINVAL;
3447         }
3448         /* Add the parameter init for LFC */
3449         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3450         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3451         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3452
3453         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3454         pf->max_num_vsi = hw->func_caps.num_vsis;
3455         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3456         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3457         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3458
3459         /* FDir queue/VSI allocation */
3460         pf->fdir_qp_offset = 0;
3461         if (hw->func_caps.fd) {
3462                 pf->flags |= I40E_FLAG_FDIR;
3463                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3464         } else {
3465                 pf->fdir_nb_qps = 0;
3466         }
3467         qp_count += pf->fdir_nb_qps;
3468         vsi_count += 1;
3469
3470         /* LAN queue/VSI allocation */
3471         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3472         if (!hw->func_caps.rss) {
3473                 pf->lan_nb_qps = 1;
3474         } else {
3475                 pf->flags |= I40E_FLAG_RSS;
3476                 if (hw->mac.type == I40E_MAC_X722)
3477                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3478                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3479         }
3480         qp_count += pf->lan_nb_qps;
3481         vsi_count += 1;
3482
3483         /* VF queue/VSI allocation */
3484         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3485         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3486                 pf->flags |= I40E_FLAG_SRIOV;
3487                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3488                 pf->vf_num = dev->pci_dev->max_vfs;
3489                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3490                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3491                             pf->vf_nb_qps * pf->vf_num);
3492         } else {
3493                 pf->vf_nb_qps = 0;
3494                 pf->vf_num = 0;
3495         }
3496         qp_count += pf->vf_nb_qps * pf->vf_num;
3497         vsi_count += pf->vf_num;
3498
3499         /* VMDq queue/VSI allocation */
3500         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3501         pf->vmdq_nb_qps = 0;
3502         pf->max_nb_vmdq_vsi = 0;
3503         if (hw->func_caps.vmdq) {
3504                 if (qp_count < hw->func_caps.num_tx_qp &&
3505                         vsi_count < hw->func_caps.num_vsis) {
3506                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3507                                 qp_count) / pf->vmdq_nb_qp_max;
3508
3509                         /* Limit the maximum number of VMDq vsi to the maximum
3510                          * ethdev can support
3511                          */
3512                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3513                                 hw->func_caps.num_vsis - vsi_count);
3514                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3515                                 ETH_64_POOLS);
3516                         if (pf->max_nb_vmdq_vsi) {
3517                                 pf->flags |= I40E_FLAG_VMDQ;
3518                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3519                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3520                                             "per VMDQ VSI, in total %u queues",
3521                                             pf->max_nb_vmdq_vsi,
3522                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3523                                             pf->max_nb_vmdq_vsi);
3524                         } else {
3525                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3526                                             "VMDq");
3527                         }
3528                 } else {
3529                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3530                 }
3531         }
3532         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3533         vsi_count += pf->max_nb_vmdq_vsi;
3534
3535         if (hw->func_caps.dcb)
3536                 pf->flags |= I40E_FLAG_DCB;
3537
3538         if (qp_count > hw->func_caps.num_tx_qp) {
3539                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3540                             "the hardware maximum %u", qp_count,
3541                             hw->func_caps.num_tx_qp);
3542                 return -EINVAL;
3543         }
3544         if (vsi_count > hw->func_caps.num_vsis) {
3545                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3546                             "the hardware maximum %u", vsi_count,
3547                             hw->func_caps.num_vsis);
3548                 return -EINVAL;
3549         }
3550
3551         return 0;
3552 }
3553
3554 static int
3555 i40e_pf_get_switch_config(struct i40e_pf *pf)
3556 {
3557         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3558         struct i40e_aqc_get_switch_config_resp *switch_config;
3559         struct i40e_aqc_switch_config_element_resp *element;
3560         uint16_t start_seid = 0, num_reported;
3561         int ret;
3562
3563         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3564                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3565         if (!switch_config) {
3566                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3567                 return -ENOMEM;
3568         }
3569
3570         /* Get the switch configurations */
3571         ret = i40e_aq_get_switch_config(hw, switch_config,
3572                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3573         if (ret != I40E_SUCCESS) {
3574                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3575                 goto fail;
3576         }
3577         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3578         if (num_reported != 1) { /* The number should be 1 */
3579                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3580                 goto fail;
3581         }
3582
3583         /* Parse the switch configuration elements */
3584         element = &(switch_config->element[0]);
3585         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3586                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3587                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3588         } else
3589                 PMD_DRV_LOG(INFO, "Unknown element type");
3590
3591 fail:
3592         rte_free(switch_config);
3593
3594         return ret;
3595 }
3596
3597 static int
3598 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3599                         uint32_t num)
3600 {
3601         struct pool_entry *entry;
3602
3603         if (pool == NULL || num == 0)
3604                 return -EINVAL;
3605
3606         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3607         if (entry == NULL) {
3608                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3609                 return -ENOMEM;
3610         }
3611
3612         /* queue heap initialize */
3613         pool->num_free = num;
3614         pool->num_alloc = 0;
3615         pool->base = base;
3616         LIST_INIT(&pool->alloc_list);
3617         LIST_INIT(&pool->free_list);
3618
3619         /* Initialize element  */
3620         entry->base = 0;
3621         entry->len = num;
3622
3623         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3624         return 0;
3625 }
3626
3627 static void
3628 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3629 {
3630         struct pool_entry *entry, *next_entry;
3631
3632         if (pool == NULL)
3633                 return;
3634
3635         for (entry = LIST_FIRST(&pool->alloc_list);
3636                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3637                         entry = next_entry) {
3638                 LIST_REMOVE(entry, next);
3639                 rte_free(entry);
3640         }
3641
3642         for (entry = LIST_FIRST(&pool->free_list);
3643                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3644                         entry = next_entry) {
3645                 LIST_REMOVE(entry, next);
3646                 rte_free(entry);
3647         }
3648
3649         pool->num_free = 0;
3650         pool->num_alloc = 0;
3651         pool->base = 0;
3652         LIST_INIT(&pool->alloc_list);
3653         LIST_INIT(&pool->free_list);
3654 }
3655
3656 static int
3657 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3658                        uint32_t base)
3659 {
3660         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3661         uint32_t pool_offset;
3662         int insert;
3663
3664         if (pool == NULL) {
3665                 PMD_DRV_LOG(ERR, "Invalid parameter");
3666                 return -EINVAL;
3667         }
3668
3669         pool_offset = base - pool->base;
3670         /* Lookup in alloc list */
3671         LIST_FOREACH(entry, &pool->alloc_list, next) {
3672                 if (entry->base == pool_offset) {
3673                         valid_entry = entry;
3674                         LIST_REMOVE(entry, next);
3675                         break;
3676                 }
3677         }
3678
3679         /* Not find, return */
3680         if (valid_entry == NULL) {
3681                 PMD_DRV_LOG(ERR, "Failed to find entry");
3682                 return -EINVAL;
3683         }
3684
3685         /**
3686          * Found it, move it to free list  and try to merge.
3687          * In order to make merge easier, always sort it by qbase.
3688          * Find adjacent prev and last entries.
3689          */
3690         prev = next = NULL;
3691         LIST_FOREACH(entry, &pool->free_list, next) {
3692                 if (entry->base > valid_entry->base) {
3693                         next = entry;
3694                         break;
3695                 }
3696                 prev = entry;
3697         }
3698
3699         insert = 0;
3700         /* Try to merge with next one*/
3701         if (next != NULL) {
3702                 /* Merge with next one */
3703                 if (valid_entry->base + valid_entry->len == next->base) {
3704                         next->base = valid_entry->base;
3705                         next->len += valid_entry->len;
3706                         rte_free(valid_entry);
3707                         valid_entry = next;
3708                         insert = 1;
3709                 }
3710         }
3711
3712         if (prev != NULL) {
3713                 /* Merge with previous one */
3714                 if (prev->base + prev->len == valid_entry->base) {
3715                         prev->len += valid_entry->len;
3716                         /* If it merge with next one, remove next node */
3717                         if (insert == 1) {
3718                                 LIST_REMOVE(valid_entry, next);
3719                                 rte_free(valid_entry);
3720                         } else {
3721                                 rte_free(valid_entry);
3722                                 insert = 1;
3723                         }
3724                 }
3725         }
3726
3727         /* Not find any entry to merge, insert */
3728         if (insert == 0) {
3729                 if (prev != NULL)
3730                         LIST_INSERT_AFTER(prev, valid_entry, next);
3731                 else if (next != NULL)
3732                         LIST_INSERT_BEFORE(next, valid_entry, next);
3733                 else /* It's empty list, insert to head */
3734                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3735         }
3736
3737         pool->num_free += valid_entry->len;
3738         pool->num_alloc -= valid_entry->len;
3739
3740         return 0;
3741 }
3742
3743 static int
3744 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3745                        uint16_t num)
3746 {
3747         struct pool_entry *entry, *valid_entry;
3748
3749         if (pool == NULL || num == 0) {
3750                 PMD_DRV_LOG(ERR, "Invalid parameter");
3751                 return -EINVAL;
3752         }
3753
3754         if (pool->num_free < num) {
3755                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3756                             num, pool->num_free);
3757                 return -ENOMEM;
3758         }
3759
3760         valid_entry = NULL;
3761         /* Lookup  in free list and find most fit one */
3762         LIST_FOREACH(entry, &pool->free_list, next) {
3763                 if (entry->len >= num) {
3764                         /* Find best one */
3765                         if (entry->len == num) {
3766                                 valid_entry = entry;
3767                                 break;
3768                         }
3769                         if (valid_entry == NULL || valid_entry->len > entry->len)
3770                                 valid_entry = entry;
3771                 }
3772         }
3773
3774         /* Not find one to satisfy the request, return */
3775         if (valid_entry == NULL) {
3776                 PMD_DRV_LOG(ERR, "No valid entry found");
3777                 return -ENOMEM;
3778         }
3779         /**
3780          * The entry have equal queue number as requested,
3781          * remove it from alloc_list.
3782          */
3783         if (valid_entry->len == num) {
3784                 LIST_REMOVE(valid_entry, next);
3785         } else {
3786                 /**
3787                  * The entry have more numbers than requested,
3788                  * create a new entry for alloc_list and minus its
3789                  * queue base and number in free_list.
3790                  */
3791                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3792                 if (entry == NULL) {
3793                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3794                                     "resource pool");
3795                         return -ENOMEM;
3796                 }
3797                 entry->base = valid_entry->base;
3798                 entry->len = num;
3799                 valid_entry->base += num;
3800                 valid_entry->len -= num;
3801                 valid_entry = entry;
3802         }
3803
3804         /* Insert it into alloc list, not sorted */
3805         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3806
3807         pool->num_free -= valid_entry->len;
3808         pool->num_alloc += valid_entry->len;
3809
3810         return valid_entry->base + pool->base;
3811 }
3812
3813 /**
3814  * bitmap_is_subset - Check whether src2 is subset of src1
3815  **/
3816 static inline int
3817 bitmap_is_subset(uint8_t src1, uint8_t src2)
3818 {
3819         return !((src1 ^ src2) & src2);
3820 }
3821
3822 static enum i40e_status_code
3823 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3824 {
3825         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3826
3827         /* If DCB is not supported, only default TC is supported */
3828         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3829                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3830                 return I40E_NOT_SUPPORTED;
3831         }
3832
3833         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3834                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3835                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3836                             enabled_tcmap);
3837                 return I40E_NOT_SUPPORTED;
3838         }
3839         return I40E_SUCCESS;
3840 }
3841
3842 int
3843 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3844                                 struct i40e_vsi_vlan_pvid_info *info)
3845 {
3846         struct i40e_hw *hw;
3847         struct i40e_vsi_context ctxt;
3848         uint8_t vlan_flags = 0;
3849         int ret;
3850
3851         if (vsi == NULL || info == NULL) {
3852                 PMD_DRV_LOG(ERR, "invalid parameters");
3853                 return I40E_ERR_PARAM;
3854         }
3855
3856         if (info->on) {
3857                 vsi->info.pvid = info->config.pvid;
3858                 /**
3859                  * If insert pvid is enabled, only tagged pkts are
3860                  * allowed to be sent out.
3861                  */
3862                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3863                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3864         } else {
3865                 vsi->info.pvid = 0;
3866                 if (info->config.reject.tagged == 0)
3867                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3868
3869                 if (info->config.reject.untagged == 0)
3870                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3871         }
3872         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3873                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3874         vsi->info.port_vlan_flags |= vlan_flags;
3875         vsi->info.valid_sections =
3876                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3877         memset(&ctxt, 0, sizeof(ctxt));
3878         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3879         ctxt.seid = vsi->seid;
3880
3881         hw = I40E_VSI_TO_HW(vsi);
3882         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3883         if (ret != I40E_SUCCESS)
3884                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3885
3886         return ret;
3887 }
3888
3889 static int
3890 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3891 {
3892         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3893         int i, ret;
3894         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3895
3896         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3897         if (ret != I40E_SUCCESS)
3898                 return ret;
3899
3900         if (!vsi->seid) {
3901                 PMD_DRV_LOG(ERR, "seid not valid");
3902                 return -EINVAL;
3903         }
3904
3905         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3906         tc_bw_data.tc_valid_bits = enabled_tcmap;
3907         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3908                 tc_bw_data.tc_bw_credits[i] =
3909                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3910
3911         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3912         if (ret != I40E_SUCCESS) {
3913                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3914                 return ret;
3915         }
3916
3917         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3918                                         sizeof(vsi->info.qs_handle));
3919         return I40E_SUCCESS;
3920 }
3921
3922 static enum i40e_status_code
3923 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3924                                  struct i40e_aqc_vsi_properties_data *info,
3925                                  uint8_t enabled_tcmap)
3926 {
3927         enum i40e_status_code ret;
3928         int i, total_tc = 0;
3929         uint16_t qpnum_per_tc, bsf, qp_idx;
3930
3931         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3932         if (ret != I40E_SUCCESS)
3933                 return ret;
3934
3935         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3936                 if (enabled_tcmap & (1 << i))
3937                         total_tc++;
3938         vsi->enabled_tc = enabled_tcmap;
3939
3940         /* Number of queues per enabled TC */
3941         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3942         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3943         bsf = rte_bsf32(qpnum_per_tc);
3944
3945         /* Adjust the queue number to actual queues that can be applied */
3946         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3947                 vsi->nb_qps = qpnum_per_tc * total_tc;
3948
3949         /**
3950          * Configure TC and queue mapping parameters, for enabled TC,
3951          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3952          * default queue will serve it.
3953          */
3954         qp_idx = 0;
3955         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3956                 if (vsi->enabled_tc & (1 << i)) {
3957                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3958                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3959                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3960                         qp_idx += qpnum_per_tc;
3961                 } else
3962                         info->tc_mapping[i] = 0;
3963         }
3964
3965         /* Associate queue number with VSI */
3966         if (vsi->type == I40E_VSI_SRIOV) {
3967                 info->mapping_flags |=
3968                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3969                 for (i = 0; i < vsi->nb_qps; i++)
3970                         info->queue_mapping[i] =
3971                                 rte_cpu_to_le_16(vsi->base_queue + i);
3972         } else {
3973                 info->mapping_flags |=
3974                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3975                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3976         }
3977         info->valid_sections |=
3978                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3979
3980         return I40E_SUCCESS;
3981 }
3982
3983 static int
3984 i40e_veb_release(struct i40e_veb *veb)
3985 {
3986         struct i40e_vsi *vsi;
3987         struct i40e_hw *hw;
3988
3989         if (veb == NULL)
3990                 return -EINVAL;
3991
3992         if (!TAILQ_EMPTY(&veb->head)) {
3993                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3994                 return -EACCES;
3995         }
3996         /* associate_vsi field is NULL for floating VEB */
3997         if (veb->associate_vsi != NULL) {
3998                 vsi = veb->associate_vsi;
3999                 hw = I40E_VSI_TO_HW(vsi);
4000
4001                 vsi->uplink_seid = veb->uplink_seid;
4002                 vsi->veb = NULL;
4003         } else {
4004                 veb->associate_pf->main_vsi->floating_veb = NULL;
4005                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4006         }
4007
4008         i40e_aq_delete_element(hw, veb->seid, NULL);
4009         rte_free(veb);
4010         return I40E_SUCCESS;
4011 }
4012
4013 /* Setup a veb */
4014 static struct i40e_veb *
4015 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4016 {
4017         struct i40e_veb *veb;
4018         int ret;
4019         struct i40e_hw *hw;
4020
4021         if (pf == NULL) {
4022                 PMD_DRV_LOG(ERR,
4023                             "veb setup failed, associated PF shouldn't null");
4024                 return NULL;
4025         }
4026         hw = I40E_PF_TO_HW(pf);
4027
4028         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4029         if (!veb) {
4030                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4031                 goto fail;
4032         }
4033
4034         veb->associate_vsi = vsi;
4035         veb->associate_pf = pf;
4036         TAILQ_INIT(&veb->head);
4037         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4038
4039         /* create floating veb if vsi is NULL */
4040         if (vsi != NULL) {
4041                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4042                                       I40E_DEFAULT_TCMAP, false,
4043                                       &veb->seid, false, NULL);
4044         } else {
4045                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4046                                       true, &veb->seid, false, NULL);
4047         }
4048
4049         if (ret != I40E_SUCCESS) {
4050                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4051                             hw->aq.asq_last_status);
4052                 goto fail;
4053         }
4054
4055         /* get statistics index */
4056         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4057                                 &veb->stats_idx, NULL, NULL, NULL);
4058         if (ret != I40E_SUCCESS) {
4059                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4060                             hw->aq.asq_last_status);
4061                 goto fail;
4062         }
4063         /* Get VEB bandwidth, to be implemented */
4064         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4065         if (vsi)
4066                 vsi->uplink_seid = veb->seid;
4067
4068         return veb;
4069 fail:
4070         rte_free(veb);
4071         return NULL;
4072 }
4073
4074 int
4075 i40e_vsi_release(struct i40e_vsi *vsi)
4076 {
4077         struct i40e_pf *pf;
4078         struct i40e_hw *hw;
4079         struct i40e_vsi_list *vsi_list;
4080         void *temp;
4081         int ret;
4082         struct i40e_mac_filter *f;
4083         uint16_t user_param = vsi->user_param;
4084
4085         if (!vsi)
4086                 return I40E_SUCCESS;
4087
4088         pf = I40E_VSI_TO_PF(vsi);
4089         hw = I40E_VSI_TO_HW(vsi);
4090
4091         /* VSI has child to attach, release child first */
4092         if (vsi->veb) {
4093                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4094                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4095                                 return -1;
4096                 }
4097                 i40e_veb_release(vsi->veb);
4098         }
4099
4100         if (vsi->floating_veb) {
4101                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4102                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4103                                 return -1;
4104                 }
4105         }
4106
4107         /* Remove all macvlan filters of the VSI */
4108         i40e_vsi_remove_all_macvlan_filter(vsi);
4109         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4110                 rte_free(f);
4111
4112         if (vsi->type != I40E_VSI_MAIN &&
4113             ((vsi->type != I40E_VSI_SRIOV) ||
4114             !pf->floating_veb_list[user_param])) {
4115                 /* Remove vsi from parent's sibling list */
4116                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4117                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4118                         return I40E_ERR_PARAM;
4119                 }
4120                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4121                                 &vsi->sib_vsi_list, list);
4122
4123                 /* Remove all switch element of the VSI */
4124                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4125                 if (ret != I40E_SUCCESS)
4126                         PMD_DRV_LOG(ERR, "Failed to delete element");
4127         }
4128
4129         if ((vsi->type == I40E_VSI_SRIOV) &&
4130             pf->floating_veb_list[user_param]) {
4131                 /* Remove vsi from parent's sibling list */
4132                 if (vsi->parent_vsi == NULL ||
4133                     vsi->parent_vsi->floating_veb == NULL) {
4134                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4135                         return I40E_ERR_PARAM;
4136                 }
4137                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4138                              &vsi->sib_vsi_list, list);
4139
4140                 /* Remove all switch element of the VSI */
4141                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4142                 if (ret != I40E_SUCCESS)
4143                         PMD_DRV_LOG(ERR, "Failed to delete element");
4144         }
4145
4146         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4147
4148         if (vsi->type != I40E_VSI_SRIOV)
4149                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4150         rte_free(vsi);
4151
4152         return I40E_SUCCESS;
4153 }
4154
4155 static int
4156 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4157 {
4158         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4159         struct i40e_aqc_remove_macvlan_element_data def_filter;
4160         struct i40e_mac_filter_info filter;
4161         int ret;
4162
4163         if (vsi->type != I40E_VSI_MAIN)
4164                 return I40E_ERR_CONFIG;
4165         memset(&def_filter, 0, sizeof(def_filter));
4166         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4167                                         ETH_ADDR_LEN);
4168         def_filter.vlan_tag = 0;
4169         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4170                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4171         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4172         if (ret != I40E_SUCCESS) {
4173                 struct i40e_mac_filter *f;
4174                 struct ether_addr *mac;
4175
4176                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4177                             "macvlan filter");
4178                 /* It needs to add the permanent mac into mac list */
4179                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4180                 if (f == NULL) {
4181                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4182                         return I40E_ERR_NO_MEMORY;
4183                 }
4184                 mac = &f->mac_info.mac_addr;
4185                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4186                                 ETH_ADDR_LEN);
4187                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4188                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4189                 vsi->mac_num++;
4190
4191                 return ret;
4192         }
4193         (void)rte_memcpy(&filter.mac_addr,
4194                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4195         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4196         return i40e_vsi_add_mac(vsi, &filter);
4197 }
4198
4199 /*
4200  * i40e_vsi_get_bw_config - Query VSI BW Information
4201  * @vsi: the VSI to be queried
4202  *
4203  * Returns 0 on success, negative value on failure
4204  */
4205 static enum i40e_status_code
4206 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4207 {
4208         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4209         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4210         struct i40e_hw *hw = &vsi->adapter->hw;
4211         i40e_status ret;
4212         int i;
4213         uint32_t bw_max;
4214
4215         memset(&bw_config, 0, sizeof(bw_config));
4216         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4217         if (ret != I40E_SUCCESS) {
4218                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4219                             hw->aq.asq_last_status);
4220                 return ret;
4221         }
4222
4223         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4224         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4225                                         &ets_sla_config, NULL);
4226         if (ret != I40E_SUCCESS) {
4227                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4228                             "configuration %u", hw->aq.asq_last_status);
4229                 return ret;
4230         }
4231
4232         /* store and print out BW info */
4233         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4234         vsi->bw_info.bw_max = bw_config.max_bw;
4235         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4236         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4237         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4238                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4239                      I40E_16_BIT_WIDTH);
4240         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4241                 vsi->bw_info.bw_ets_share_credits[i] =
4242                                 ets_sla_config.share_credits[i];
4243                 vsi->bw_info.bw_ets_credits[i] =
4244                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4245                 /* 4 bits per TC, 4th bit is reserved */
4246                 vsi->bw_info.bw_ets_max[i] =
4247                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4248                                   RTE_LEN2MASK(3, uint8_t));
4249                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4250                             vsi->bw_info.bw_ets_share_credits[i]);
4251                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4252                             vsi->bw_info.bw_ets_credits[i]);
4253                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4254                             vsi->bw_info.bw_ets_max[i]);
4255         }
4256
4257         return I40E_SUCCESS;
4258 }
4259
4260 /* i40e_enable_pf_lb
4261  * @pf: pointer to the pf structure
4262  *
4263  * allow loopback on pf
4264  */
4265 static inline void
4266 i40e_enable_pf_lb(struct i40e_pf *pf)
4267 {
4268         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4269         struct i40e_vsi_context ctxt;
4270         int ret;
4271
4272         /* Use the FW API if FW >= v5.0 */
4273         if (hw->aq.fw_maj_ver < 5) {
4274                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4275                 return;
4276         }
4277
4278         memset(&ctxt, 0, sizeof(ctxt));
4279         ctxt.seid = pf->main_vsi_seid;
4280         ctxt.pf_num = hw->pf_id;
4281         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4282         if (ret) {
4283                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4284                             ret, hw->aq.asq_last_status);
4285                 return;
4286         }
4287         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4288         ctxt.info.valid_sections =
4289                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4290         ctxt.info.switch_id |=
4291                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4292
4293         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4294         if (ret)
4295                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4296                             hw->aq.asq_last_status);
4297 }
4298
4299 /* Setup a VSI */
4300 struct i40e_vsi *
4301 i40e_vsi_setup(struct i40e_pf *pf,
4302                enum i40e_vsi_type type,
4303                struct i40e_vsi *uplink_vsi,
4304                uint16_t user_param)
4305 {
4306         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4307         struct i40e_vsi *vsi;
4308         struct i40e_mac_filter_info filter;
4309         int ret;
4310         struct i40e_vsi_context ctxt;
4311         struct ether_addr broadcast =
4312                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4313
4314         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4315             uplink_vsi == NULL) {
4316                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4317                             "VSI link shouldn't be NULL");
4318                 return NULL;
4319         }
4320
4321         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4322                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4323                             "uplink VSI should be NULL");
4324                 return NULL;
4325         }
4326
4327         /* two situations
4328          * 1.type is not MAIN and uplink vsi is not NULL
4329          * If uplink vsi didn't setup VEB, create one first under veb field
4330          * 2.type is SRIOV and the uplink is NULL
4331          * If floating VEB is NULL, create one veb under floating veb field
4332          */
4333
4334         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4335             uplink_vsi->veb == NULL) {
4336                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4337
4338                 if (uplink_vsi->veb == NULL) {
4339                         PMD_DRV_LOG(ERR, "VEB setup failed");
4340                         return NULL;
4341                 }
4342                 /* set ALLOWLOOPBACk on pf, when veb is created */
4343                 i40e_enable_pf_lb(pf);
4344         }
4345
4346         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4347             pf->main_vsi->floating_veb == NULL) {
4348                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4349
4350                 if (pf->main_vsi->floating_veb == NULL) {
4351                         PMD_DRV_LOG(ERR, "VEB setup failed");
4352                         return NULL;
4353                 }
4354         }
4355
4356         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4357         if (!vsi) {
4358                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4359                 return NULL;
4360         }
4361         TAILQ_INIT(&vsi->mac_list);
4362         vsi->type = type;
4363         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4364         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4365         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4366         vsi->user_param = user_param;
4367         /* Allocate queues */
4368         switch (vsi->type) {
4369         case I40E_VSI_MAIN  :
4370                 vsi->nb_qps = pf->lan_nb_qps;
4371                 break;
4372         case I40E_VSI_SRIOV :
4373                 vsi->nb_qps = pf->vf_nb_qps;
4374                 break;
4375         case I40E_VSI_VMDQ2:
4376                 vsi->nb_qps = pf->vmdq_nb_qps;
4377                 break;
4378         case I40E_VSI_FDIR:
4379                 vsi->nb_qps = pf->fdir_nb_qps;
4380                 break;
4381         default:
4382                 goto fail_mem;
4383         }
4384         /*
4385          * The filter status descriptor is reported in rx queue 0,
4386          * while the tx queue for fdir filter programming has no
4387          * such constraints, can be non-zero queues.
4388          * To simplify it, choose FDIR vsi use queue 0 pair.
4389          * To make sure it will use queue 0 pair, queue allocation
4390          * need be done before this function is called
4391          */
4392         if (type != I40E_VSI_FDIR) {
4393                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4394                         if (ret < 0) {
4395                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4396                                                 vsi->seid, ret);
4397                                 goto fail_mem;
4398                         }
4399                         vsi->base_queue = ret;
4400         } else
4401                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4402
4403         /* VF has MSIX interrupt in VF range, don't allocate here */
4404         if (type == I40E_VSI_MAIN) {
4405                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4406                                           RTE_MIN(vsi->nb_qps,
4407                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4408                 if (ret < 0) {
4409                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4410                                     vsi->seid, ret);
4411                         goto fail_queue_alloc;
4412                 }
4413                 vsi->msix_intr = ret;
4414                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4415         } else if (type != I40E_VSI_SRIOV) {
4416                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4417                 if (ret < 0) {
4418                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4419                         goto fail_queue_alloc;
4420                 }
4421                 vsi->msix_intr = ret;
4422                 vsi->nb_msix = 1;
4423         } else {
4424                 vsi->msix_intr = 0;
4425                 vsi->nb_msix = 0;
4426         }
4427
4428         /* Add VSI */
4429         if (type == I40E_VSI_MAIN) {
4430                 /* For main VSI, no need to add since it's default one */
4431                 vsi->uplink_seid = pf->mac_seid;
4432                 vsi->seid = pf->main_vsi_seid;
4433                 /* Bind queues with specific MSIX interrupt */
4434                 /**
4435                  * Needs 2 interrupt at least, one for misc cause which will
4436                  * enabled from OS side, Another for queues binding the
4437                  * interrupt from device side only.
4438                  */
4439
4440                 /* Get default VSI parameters from hardware */
4441                 memset(&ctxt, 0, sizeof(ctxt));
4442                 ctxt.seid = vsi->seid;
4443                 ctxt.pf_num = hw->pf_id;
4444                 ctxt.uplink_seid = vsi->uplink_seid;
4445                 ctxt.vf_num = 0;
4446                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4447                 if (ret != I40E_SUCCESS) {
4448                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4449                         goto fail_msix_alloc;
4450                 }
4451                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4452                         sizeof(struct i40e_aqc_vsi_properties_data));
4453                 vsi->vsi_id = ctxt.vsi_number;
4454                 vsi->info.valid_sections = 0;
4455
4456                 /* Configure tc, enabled TC0 only */
4457                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4458                         I40E_SUCCESS) {
4459                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4460                         goto fail_msix_alloc;
4461                 }
4462
4463                 /* TC, queue mapping */
4464                 memset(&ctxt, 0, sizeof(ctxt));
4465                 vsi->info.valid_sections |=
4466                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4467                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4468                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4469                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4470                         sizeof(struct i40e_aqc_vsi_properties_data));
4471                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4472                                                 I40E_DEFAULT_TCMAP);
4473                 if (ret != I40E_SUCCESS) {
4474                         PMD_DRV_LOG(ERR, "Failed to configure "
4475                                     "TC queue mapping");
4476                         goto fail_msix_alloc;
4477                 }
4478                 ctxt.seid = vsi->seid;
4479                 ctxt.pf_num = hw->pf_id;
4480                 ctxt.uplink_seid = vsi->uplink_seid;
4481                 ctxt.vf_num = 0;
4482
4483                 /* Update VSI parameters */
4484                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4485                 if (ret != I40E_SUCCESS) {
4486                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4487                         goto fail_msix_alloc;
4488                 }
4489
4490                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4491                                                 sizeof(vsi->info.tc_mapping));
4492                 (void)rte_memcpy(&vsi->info.queue_mapping,
4493                                 &ctxt.info.queue_mapping,
4494                         sizeof(vsi->info.queue_mapping));
4495                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4496                 vsi->info.valid_sections = 0;
4497
4498                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4499                                 ETH_ADDR_LEN);
4500
4501                 /**
4502                  * Updating default filter settings are necessary to prevent
4503                  * reception of tagged packets.
4504                  * Some old firmware configurations load a default macvlan
4505                  * filter which accepts both tagged and untagged packets.
4506                  * The updating is to use a normal filter instead if needed.
4507                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4508                  * The firmware with correct configurations load the default
4509                  * macvlan filter which is expected and cannot be removed.
4510                  */
4511                 i40e_update_default_filter_setting(vsi);
4512                 i40e_config_qinq(hw, vsi);
4513         } else if (type == I40E_VSI_SRIOV) {
4514                 memset(&ctxt, 0, sizeof(ctxt));
4515                 /**
4516                  * For other VSI, the uplink_seid equals to uplink VSI's
4517                  * uplink_seid since they share same VEB
4518                  */
4519                 if (uplink_vsi == NULL)
4520                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4521                 else
4522                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4523                 ctxt.pf_num = hw->pf_id;
4524                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4525                 ctxt.uplink_seid = vsi->uplink_seid;
4526                 ctxt.connection_type = 0x1;
4527                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4528
4529                 /* Use the VEB configuration if FW >= v5.0 */
4530                 if (hw->aq.fw_maj_ver >= 5) {
4531                         /* Configure switch ID */
4532                         ctxt.info.valid_sections |=
4533                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4534                         ctxt.info.switch_id =
4535                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4536                 }
4537
4538                 /* Configure port/vlan */
4539                 ctxt.info.valid_sections |=
4540                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4541                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4542                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4543                                                 I40E_DEFAULT_TCMAP);
4544                 if (ret != I40E_SUCCESS) {
4545                         PMD_DRV_LOG(ERR, "Failed to configure "
4546                                     "TC queue mapping");
4547                         goto fail_msix_alloc;
4548                 }
4549                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4550                 ctxt.info.valid_sections |=
4551                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4552                 /**
4553                  * Since VSI is not created yet, only configure parameter,
4554                  * will add vsi below.
4555                  */
4556
4557                 i40e_config_qinq(hw, vsi);
4558         } else if (type == I40E_VSI_VMDQ2) {
4559                 memset(&ctxt, 0, sizeof(ctxt));
4560                 /*
4561                  * For other VSI, the uplink_seid equals to uplink VSI's
4562                  * uplink_seid since they share same VEB
4563                  */
4564                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4565                 ctxt.pf_num = hw->pf_id;
4566                 ctxt.vf_num = 0;
4567                 ctxt.uplink_seid = vsi->uplink_seid;
4568                 ctxt.connection_type = 0x1;
4569                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4570
4571                 ctxt.info.valid_sections |=
4572                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4573                 /* user_param carries flag to enable loop back */
4574                 if (user_param) {
4575                         ctxt.info.switch_id =
4576                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4577                         ctxt.info.switch_id |=
4578                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4579                 }
4580
4581                 /* Configure port/vlan */
4582                 ctxt.info.valid_sections |=
4583                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4584                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4585                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4586                                                 I40E_DEFAULT_TCMAP);
4587                 if (ret != I40E_SUCCESS) {
4588                         PMD_DRV_LOG(ERR, "Failed to configure "
4589                                         "TC queue mapping");
4590                         goto fail_msix_alloc;
4591                 }
4592                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4593                 ctxt.info.valid_sections |=
4594                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4595         } else if (type == I40E_VSI_FDIR) {
4596                 memset(&ctxt, 0, sizeof(ctxt));
4597                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4598                 ctxt.pf_num = hw->pf_id;
4599                 ctxt.vf_num = 0;
4600                 ctxt.uplink_seid = vsi->uplink_seid;
4601                 ctxt.connection_type = 0x1;     /* regular data port */
4602                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4603                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4604                                                 I40E_DEFAULT_TCMAP);
4605                 if (ret != I40E_SUCCESS) {
4606                         PMD_DRV_LOG(ERR, "Failed to configure "
4607                                         "TC queue mapping.");
4608                         goto fail_msix_alloc;
4609                 }
4610                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4611                 ctxt.info.valid_sections |=
4612                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4613         } else {
4614                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4615                 goto fail_msix_alloc;
4616         }
4617
4618         if (vsi->type != I40E_VSI_MAIN) {
4619                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4620                 if (ret != I40E_SUCCESS) {
4621                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4622                                     hw->aq.asq_last_status);
4623                         goto fail_msix_alloc;
4624                 }
4625                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4626                 vsi->info.valid_sections = 0;
4627                 vsi->seid = ctxt.seid;
4628                 vsi->vsi_id = ctxt.vsi_number;
4629                 vsi->sib_vsi_list.vsi = vsi;
4630                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4631                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4632                                           &vsi->sib_vsi_list, list);
4633                 } else {
4634                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4635                                           &vsi->sib_vsi_list, list);
4636                 }
4637         }
4638
4639         /* MAC/VLAN configuration */
4640         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4641         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4642
4643         ret = i40e_vsi_add_mac(vsi, &filter);
4644         if (ret != I40E_SUCCESS) {
4645                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4646                 goto fail_msix_alloc;
4647         }
4648
4649         /* Get VSI BW information */
4650         i40e_vsi_get_bw_config(vsi);
4651         return vsi;
4652 fail_msix_alloc:
4653         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4654 fail_queue_alloc:
4655         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4656 fail_mem:
4657         rte_free(vsi);
4658         return NULL;
4659 }
4660
4661 /* Configure vlan filter on or off */
4662 int
4663 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4664 {
4665         int i, num;
4666         struct i40e_mac_filter *f;
4667         void *temp;
4668         struct i40e_mac_filter_info *mac_filter;
4669         enum rte_mac_filter_type desired_filter;
4670         int ret = I40E_SUCCESS;
4671
4672         if (on) {
4673                 /* Filter to match MAC and VLAN */
4674                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4675         } else {
4676                 /* Filter to match only MAC */
4677                 desired_filter = RTE_MAC_PERFECT_MATCH;
4678         }
4679
4680         num = vsi->mac_num;
4681
4682         mac_filter = rte_zmalloc("mac_filter_info_data",
4683                                  num * sizeof(*mac_filter), 0);
4684         if (mac_filter == NULL) {
4685                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4686                 return I40E_ERR_NO_MEMORY;
4687         }
4688
4689         i = 0;
4690
4691         /* Remove all existing mac */
4692         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4693                 mac_filter[i] = f->mac_info;
4694                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4695                 if (ret) {
4696                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4697                                     on ? "enable" : "disable");
4698                         goto DONE;
4699                 }
4700                 i++;
4701         }
4702
4703         /* Override with new filter */
4704         for (i = 0; i < num; i++) {
4705                 mac_filter[i].filter_type = desired_filter;
4706                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4707                 if (ret) {
4708                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4709                                     on ? "enable" : "disable");
4710                         goto DONE;
4711                 }
4712         }
4713
4714 DONE:
4715         rte_free(mac_filter);
4716         return ret;
4717 }
4718
4719 /* Configure vlan stripping on or off */
4720 int
4721 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4722 {
4723         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4724         struct i40e_vsi_context ctxt;
4725         uint8_t vlan_flags;
4726         int ret = I40E_SUCCESS;
4727
4728         /* Check if it has been already on or off */
4729         if (vsi->info.valid_sections &
4730                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4731                 if (on) {
4732                         if ((vsi->info.port_vlan_flags &
4733                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4734                                 return 0; /* already on */
4735                 } else {
4736                         if ((vsi->info.port_vlan_flags &
4737                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4738                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4739                                 return 0; /* already off */
4740                 }
4741         }
4742
4743         if (on)
4744                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4745         else
4746                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4747         vsi->info.valid_sections =
4748                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4749         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4750         vsi->info.port_vlan_flags |= vlan_flags;
4751         ctxt.seid = vsi->seid;
4752         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4753         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4754         if (ret)
4755                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4756                             on ? "enable" : "disable");
4757
4758         return ret;
4759 }
4760
4761 static int
4762 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4763 {
4764         struct rte_eth_dev_data *data = dev->data;
4765         int ret;
4766         int mask = 0;
4767
4768         /* Apply vlan offload setting */
4769         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4770         i40e_vlan_offload_set(dev, mask);
4771
4772         /* Apply double-vlan setting, not implemented yet */
4773
4774         /* Apply pvid setting */
4775         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4776                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4777         if (ret)
4778                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4779
4780         return ret;
4781 }
4782
4783 static int
4784 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4785 {
4786         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4787
4788         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4789 }
4790
4791 static int
4792 i40e_update_flow_control(struct i40e_hw *hw)
4793 {
4794 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4795         struct i40e_link_status link_status;
4796         uint32_t rxfc = 0, txfc = 0, reg;
4797         uint8_t an_info;
4798         int ret;
4799
4800         memset(&link_status, 0, sizeof(link_status));
4801         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4802         if (ret != I40E_SUCCESS) {
4803                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4804                 goto write_reg; /* Disable flow control */
4805         }
4806
4807         an_info = hw->phy.link_info.an_info;
4808         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4809                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4810                 ret = I40E_ERR_NOT_READY;
4811                 goto write_reg; /* Disable flow control */
4812         }
4813         /**
4814          * If link auto negotiation is enabled, flow control needs to
4815          * be configured according to it
4816          */
4817         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4818         case I40E_LINK_PAUSE_RXTX:
4819                 rxfc = 1;
4820                 txfc = 1;
4821                 hw->fc.current_mode = I40E_FC_FULL;
4822                 break;
4823         case I40E_AQ_LINK_PAUSE_RX:
4824                 rxfc = 1;
4825                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4826                 break;
4827         case I40E_AQ_LINK_PAUSE_TX:
4828                 txfc = 1;
4829                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4830                 break;
4831         default:
4832                 hw->fc.current_mode = I40E_FC_NONE;
4833                 break;
4834         }
4835
4836 write_reg:
4837         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4838                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4839         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4840         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4841         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4842         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4843
4844         return ret;
4845 }
4846
4847 /* PF setup */
4848 static int
4849 i40e_pf_setup(struct i40e_pf *pf)
4850 {
4851         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4852         struct i40e_filter_control_settings settings;
4853         struct i40e_vsi *vsi;
4854         int ret;
4855
4856         /* Clear all stats counters */
4857         pf->offset_loaded = FALSE;
4858         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4859         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4860
4861         ret = i40e_pf_get_switch_config(pf);
4862         if (ret != I40E_SUCCESS) {
4863                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4864                 return ret;
4865         }
4866         if (pf->flags & I40E_FLAG_FDIR) {
4867                 /* make queue allocated first, let FDIR use queue pair 0*/
4868                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4869                 if (ret != I40E_FDIR_QUEUE_ID) {
4870                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4871                                     " ret =%d", ret);
4872                         pf->flags &= ~I40E_FLAG_FDIR;
4873                 }
4874         }
4875         /*  main VSI setup */
4876         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4877         if (!vsi) {
4878                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4879                 return I40E_ERR_NOT_READY;
4880         }
4881         pf->main_vsi = vsi;
4882
4883         /* Configure filter control */
4884         memset(&settings, 0, sizeof(settings));
4885         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4886                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4887         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4888                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4889         else {
4890                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4891                                                 hw->func_caps.rss_table_size);
4892                 return I40E_ERR_PARAM;
4893         }
4894         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4895                         "size: %u\n", hw->func_caps.rss_table_size);
4896         pf->hash_lut_size = hw->func_caps.rss_table_size;
4897
4898         /* Enable ethtype and macvlan filters */
4899         settings.enable_ethtype = TRUE;
4900         settings.enable_macvlan = TRUE;
4901         ret = i40e_set_filter_control(hw, &settings);
4902         if (ret)
4903                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4904                                                                 ret);
4905
4906         /* Update flow control according to the auto negotiation */
4907         i40e_update_flow_control(hw);
4908
4909         return I40E_SUCCESS;
4910 }
4911
4912 int
4913 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4914 {
4915         uint32_t reg;
4916         uint16_t j;
4917
4918         /**
4919          * Set or clear TX Queue Disable flags,
4920          * which is required by hardware.
4921          */
4922         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4923         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4924
4925         /* Wait until the request is finished */
4926         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4927                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4928                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4929                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4930                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4931                                                         & 0x1))) {
4932                         break;
4933                 }
4934         }
4935         if (on) {
4936                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4937                         return I40E_SUCCESS; /* already on, skip next steps */
4938
4939                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4940                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4941         } else {
4942                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4943                         return I40E_SUCCESS; /* already off, skip next steps */
4944                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4945         }
4946         /* Write the register */
4947         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4948         /* Check the result */
4949         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4950                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4951                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4952                 if (on) {
4953                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4954                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4955                                 break;
4956                 } else {
4957                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4958                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4959                                 break;
4960                 }
4961         }
4962         /* Check if it is timeout */
4963         if (j >= I40E_CHK_Q_ENA_COUNT) {
4964                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4965                             (on ? "enable" : "disable"), q_idx);
4966                 return I40E_ERR_TIMEOUT;
4967         }
4968
4969         return I40E_SUCCESS;
4970 }
4971
4972 /* Swith on or off the tx queues */
4973 static int
4974 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4975 {
4976         struct rte_eth_dev_data *dev_data = pf->dev_data;
4977         struct i40e_tx_queue *txq;
4978         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4979         uint16_t i;
4980         int ret;
4981
4982         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4983                 txq = dev_data->tx_queues[i];
4984                 /* Don't operate the queue if not configured or
4985                  * if starting only per queue */
4986                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4987                         continue;
4988                 if (on)
4989                         ret = i40e_dev_tx_queue_start(dev, i);
4990                 else
4991                         ret = i40e_dev_tx_queue_stop(dev, i);
4992                 if ( ret != I40E_SUCCESS)
4993                         return ret;
4994         }
4995
4996         return I40E_SUCCESS;
4997 }
4998
4999 int
5000 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5001 {
5002         uint32_t reg;
5003         uint16_t j;
5004
5005         /* Wait until the request is finished */
5006         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5007                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5008                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5009                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5010                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5011                         break;
5012         }
5013
5014         if (on) {
5015                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5016                         return I40E_SUCCESS; /* Already on, skip next steps */
5017                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5018         } else {
5019                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5020                         return I40E_SUCCESS; /* Already off, skip next steps */
5021                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5022         }
5023
5024         /* Write the register */
5025         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5026         /* Check the result */
5027         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5028                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5029                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5030                 if (on) {
5031                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5032                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5033                                 break;
5034                 } else {
5035                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5036                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5037                                 break;
5038                 }
5039         }
5040
5041         /* Check if it is timeout */
5042         if (j >= I40E_CHK_Q_ENA_COUNT) {
5043                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5044                             (on ? "enable" : "disable"), q_idx);
5045                 return I40E_ERR_TIMEOUT;
5046         }
5047
5048         return I40E_SUCCESS;
5049 }
5050 /* Switch on or off the rx queues */
5051 static int
5052 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5053 {
5054         struct rte_eth_dev_data *dev_data = pf->dev_data;
5055         struct i40e_rx_queue *rxq;
5056         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5057         uint16_t i;
5058         int ret;
5059
5060         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5061                 rxq = dev_data->rx_queues[i];
5062                 /* Don't operate the queue if not configured or
5063                  * if starting only per queue */
5064                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5065                         continue;
5066                 if (on)
5067                         ret = i40e_dev_rx_queue_start(dev, i);
5068                 else
5069                         ret = i40e_dev_rx_queue_stop(dev, i);
5070                 if (ret != I40E_SUCCESS)
5071                         return ret;
5072         }
5073
5074         return I40E_SUCCESS;
5075 }
5076
5077 /* Switch on or off all the rx/tx queues */
5078 int
5079 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5080 {
5081         int ret;
5082
5083         if (on) {
5084                 /* enable rx queues before enabling tx queues */
5085                 ret = i40e_dev_switch_rx_queues(pf, on);
5086                 if (ret) {
5087                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5088                         return ret;
5089                 }
5090                 ret = i40e_dev_switch_tx_queues(pf, on);
5091         } else {
5092                 /* Stop tx queues before stopping rx queues */
5093                 ret = i40e_dev_switch_tx_queues(pf, on);
5094                 if (ret) {
5095                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5096                         return ret;
5097                 }
5098                 ret = i40e_dev_switch_rx_queues(pf, on);
5099         }
5100
5101         return ret;
5102 }
5103
5104 /* Initialize VSI for TX */
5105 static int
5106 i40e_dev_tx_init(struct i40e_pf *pf)
5107 {
5108         struct rte_eth_dev_data *data = pf->dev_data;
5109         uint16_t i;
5110         uint32_t ret = I40E_SUCCESS;
5111         struct i40e_tx_queue *txq;
5112
5113         for (i = 0; i < data->nb_tx_queues; i++) {
5114                 txq = data->tx_queues[i];
5115                 if (!txq || !txq->q_set)
5116                         continue;
5117                 ret = i40e_tx_queue_init(txq);
5118                 if (ret != I40E_SUCCESS)
5119                         break;
5120         }
5121         if (ret == I40E_SUCCESS)
5122                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5123                                      ->eth_dev);
5124
5125         return ret;
5126 }
5127
5128 /* Initialize VSI for RX */
5129 static int
5130 i40e_dev_rx_init(struct i40e_pf *pf)
5131 {
5132         struct rte_eth_dev_data *data = pf->dev_data;
5133         int ret = I40E_SUCCESS;
5134         uint16_t i;
5135         struct i40e_rx_queue *rxq;
5136
5137         i40e_pf_config_mq_rx(pf);
5138         for (i = 0; i < data->nb_rx_queues; i++) {
5139                 rxq = data->rx_queues[i];
5140                 if (!rxq || !rxq->q_set)
5141                         continue;
5142
5143                 ret = i40e_rx_queue_init(rxq);
5144                 if (ret != I40E_SUCCESS) {
5145                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5146                                     "initialization");
5147                         break;
5148                 }
5149         }
5150         if (ret == I40E_SUCCESS)
5151                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5152                                      ->eth_dev);
5153
5154         return ret;
5155 }
5156
5157 static int
5158 i40e_dev_rxtx_init(struct i40e_pf *pf)
5159 {
5160         int err;
5161
5162         err = i40e_dev_tx_init(pf);
5163         if (err) {
5164                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5165                 return err;
5166         }
5167         err = i40e_dev_rx_init(pf);
5168         if (err) {
5169                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5170                 return err;
5171         }
5172
5173         return err;
5174 }
5175
5176 static int
5177 i40e_vmdq_setup(struct rte_eth_dev *dev)
5178 {
5179         struct rte_eth_conf *conf = &dev->data->dev_conf;
5180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5181         int i, err, conf_vsis, j, loop;
5182         struct i40e_vsi *vsi;
5183         struct i40e_vmdq_info *vmdq_info;
5184         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5185         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5186
5187         /*
5188          * Disable interrupt to avoid message from VF. Furthermore, it will
5189          * avoid race condition in VSI creation/destroy.
5190          */
5191         i40e_pf_disable_irq0(hw);
5192
5193         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5194                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5195                 return -ENOTSUP;
5196         }
5197
5198         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5199         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5200                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5201                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5202                         pf->max_nb_vmdq_vsi);
5203                 return -ENOTSUP;
5204         }
5205
5206         if (pf->vmdq != NULL) {
5207                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5208                 return 0;
5209         }
5210
5211         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5212                                 sizeof(*vmdq_info) * conf_vsis, 0);
5213
5214         if (pf->vmdq == NULL) {
5215                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5216                 return -ENOMEM;
5217         }
5218
5219         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5220
5221         /* Create VMDQ VSI */
5222         for (i = 0; i < conf_vsis; i++) {
5223                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5224                                 vmdq_conf->enable_loop_back);
5225                 if (vsi == NULL) {
5226                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5227                         err = -1;
5228                         goto err_vsi_setup;
5229                 }
5230                 vmdq_info = &pf->vmdq[i];
5231                 vmdq_info->pf = pf;
5232                 vmdq_info->vsi = vsi;
5233         }
5234         pf->nb_cfg_vmdq_vsi = conf_vsis;
5235
5236         /* Configure Vlan */
5237         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5238         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5239                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5240                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5241                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5242                                         vmdq_conf->pool_map[i].vlan_id, j);
5243
5244                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5245                                                 vmdq_conf->pool_map[i].vlan_id);
5246                                 if (err) {
5247                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5248                                         err = -1;
5249                                         goto err_vsi_setup;
5250                                 }
5251                         }
5252                 }
5253         }
5254
5255         i40e_pf_enable_irq0(hw);
5256
5257         return 0;
5258
5259 err_vsi_setup:
5260         for (i = 0; i < conf_vsis; i++)
5261                 if (pf->vmdq[i].vsi == NULL)
5262                         break;
5263                 else
5264                         i40e_vsi_release(pf->vmdq[i].vsi);
5265
5266         rte_free(pf->vmdq);
5267         pf->vmdq = NULL;
5268         i40e_pf_enable_irq0(hw);
5269         return err;
5270 }
5271
5272 static void
5273 i40e_stat_update_32(struct i40e_hw *hw,
5274                    uint32_t reg,
5275                    bool offset_loaded,
5276                    uint64_t *offset,
5277                    uint64_t *stat)
5278 {
5279         uint64_t new_data;
5280
5281         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5282         if (!offset_loaded)
5283                 *offset = new_data;
5284
5285         if (new_data >= *offset)
5286                 *stat = (uint64_t)(new_data - *offset);
5287         else
5288                 *stat = (uint64_t)((new_data +
5289                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5290 }
5291
5292 static void
5293 i40e_stat_update_48(struct i40e_hw *hw,
5294                    uint32_t hireg,
5295                    uint32_t loreg,
5296                    bool offset_loaded,
5297                    uint64_t *offset,
5298                    uint64_t *stat)
5299 {
5300         uint64_t new_data;
5301
5302         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5303         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5304                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5305
5306         if (!offset_loaded)
5307                 *offset = new_data;
5308
5309         if (new_data >= *offset)
5310                 *stat = new_data - *offset;
5311         else
5312                 *stat = (uint64_t)((new_data +
5313                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5314
5315         *stat &= I40E_48_BIT_MASK;
5316 }
5317
5318 /* Disable IRQ0 */
5319 void
5320 i40e_pf_disable_irq0(struct i40e_hw *hw)
5321 {
5322         /* Disable all interrupt types */
5323         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5324         I40E_WRITE_FLUSH(hw);
5325 }
5326
5327 /* Enable IRQ0 */
5328 void
5329 i40e_pf_enable_irq0(struct i40e_hw *hw)
5330 {
5331         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5332                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5333                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5334                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5335         I40E_WRITE_FLUSH(hw);
5336 }
5337
5338 static void
5339 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5340 {
5341         /* read pending request and disable first */
5342         i40e_pf_disable_irq0(hw);
5343         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5344         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5345                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5346
5347         if (no_queue)
5348                 /* Link no queues with irq0 */
5349                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5350                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5351 }
5352
5353 static void
5354 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5355 {
5356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5357         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5358         int i;
5359         uint16_t abs_vf_id;
5360         uint32_t index, offset, val;
5361
5362         if (!pf->vfs)
5363                 return;
5364         /**
5365          * Try to find which VF trigger a reset, use absolute VF id to access
5366          * since the reg is global register.
5367          */
5368         for (i = 0; i < pf->vf_num; i++) {
5369                 abs_vf_id = hw->func_caps.vf_base_id + i;
5370                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5371                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5372                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5373                 /* VFR event occured */
5374                 if (val & (0x1 << offset)) {
5375                         int ret;
5376
5377                         /* Clear the event first */
5378                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5379                                                         (0x1 << offset));
5380                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5381                         /**
5382                          * Only notify a VF reset event occured,
5383                          * don't trigger another SW reset
5384                          */
5385                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5386                         if (ret != I40E_SUCCESS)
5387                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5388                 }
5389         }
5390 }
5391
5392 static void
5393 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5394 {
5395         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5396         struct i40e_arq_event_info info;
5397         uint16_t pending, opcode;
5398         int ret;
5399
5400         info.buf_len = I40E_AQ_BUF_SZ;
5401         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5402         if (!info.msg_buf) {
5403                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5404                 return;
5405         }
5406
5407         pending = 1;
5408         while (pending) {
5409                 ret = i40e_clean_arq_element(hw, &info, &pending);
5410
5411                 if (ret != I40E_SUCCESS) {
5412                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5413                                     "aq_err: %u", hw->aq.asq_last_status);
5414                         break;
5415                 }
5416                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5417
5418                 switch (opcode) {
5419                 case i40e_aqc_opc_send_msg_to_pf:
5420                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5421                         i40e_pf_host_handle_vf_msg(dev,
5422                                         rte_le_to_cpu_16(info.desc.retval),
5423                                         rte_le_to_cpu_32(info.desc.cookie_high),
5424                                         rte_le_to_cpu_32(info.desc.cookie_low),
5425                                         info.msg_buf,
5426                                         info.msg_len);
5427                         break;
5428                 default:
5429                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5430                                     opcode);
5431                         break;
5432                 }
5433         }
5434         rte_free(info.msg_buf);
5435 }
5436
5437 /*
5438  * Interrupt handler is registered as the alarm callback for handling LSC
5439  * interrupt in a definite of time, in order to wait the NIC into a stable
5440  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5441  * no need for link down interrupt.
5442  */
5443 static void
5444 i40e_dev_interrupt_delayed_handler(void *param)
5445 {
5446         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5447         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5448         uint32_t icr0;
5449
5450         /* read interrupt causes again */
5451         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5452
5453 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5454         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5455                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5456         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5457                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5458         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5459                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5460         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5461                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5462         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5463                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5464                                                                 "state\n");
5465         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5466                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5467         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5468                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5469 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5470
5471         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5472                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5473                 i40e_dev_handle_vfr_event(dev);
5474         }
5475         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5476                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5477                 i40e_dev_handle_aq_msg(dev);
5478         }
5479
5480         /* handle the link up interrupt in an alarm callback */
5481         i40e_dev_link_update(dev, 0);
5482         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5483
5484         i40e_pf_enable_irq0(hw);
5485         rte_intr_enable(&(dev->pci_dev->intr_handle));
5486 }
5487
5488 /**
5489  * Interrupt handler triggered by NIC  for handling
5490  * specific interrupt.
5491  *
5492  * @param handle
5493  *  Pointer to interrupt handle.
5494  * @param param
5495  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5496  *
5497  * @return
5498  *  void
5499  */
5500 static void
5501 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5502                            void *param)
5503 {
5504         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5505         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5506         uint32_t icr0;
5507
5508         /* Disable interrupt */
5509         i40e_pf_disable_irq0(hw);
5510
5511         /* read out interrupt causes */
5512         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5513
5514         /* No interrupt event indicated */
5515         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5516                 PMD_DRV_LOG(INFO, "No interrupt event");
5517                 goto done;
5518         }
5519 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5520         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5521                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5522         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5523                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5524         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5525                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5526         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5527                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5528         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5529                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5530         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5531                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5532         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5533                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5534 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5535
5536         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5537                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5538                 i40e_dev_handle_vfr_event(dev);
5539         }
5540         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5541                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5542                 i40e_dev_handle_aq_msg(dev);
5543         }
5544
5545         /* Link Status Change interrupt */
5546         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5547 #define I40E_US_PER_SECOND 1000000
5548                 struct rte_eth_link link;
5549
5550                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5551                 memset(&link, 0, sizeof(link));
5552                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5553                 i40e_dev_link_update(dev, 0);
5554
5555                 /*
5556                  * For link up interrupt, it needs to wait 1 second to let the
5557                  * hardware be a stable state. Otherwise several consecutive
5558                  * interrupts can be observed.
5559                  * For link down interrupt, no need to wait.
5560                  */
5561                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5562                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5563                         return;
5564                 else
5565                         _rte_eth_dev_callback_process(dev,
5566                                 RTE_ETH_EVENT_INTR_LSC);
5567         }
5568
5569 done:
5570         /* Enable interrupt */
5571         i40e_pf_enable_irq0(hw);
5572         rte_intr_enable(&(dev->pci_dev->intr_handle));
5573 }
5574
5575 static int
5576 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5577                          struct i40e_macvlan_filter *filter,
5578                          int total)
5579 {
5580         int ele_num, ele_buff_size;
5581         int num, actual_num, i;
5582         uint16_t flags;
5583         int ret = I40E_SUCCESS;
5584         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5585         struct i40e_aqc_add_macvlan_element_data *req_list;
5586
5587         if (filter == NULL  || total == 0)
5588                 return I40E_ERR_PARAM;
5589         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5590         ele_buff_size = hw->aq.asq_buf_size;
5591
5592         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5593         if (req_list == NULL) {
5594                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5595                 return I40E_ERR_NO_MEMORY;
5596         }
5597
5598         num = 0;
5599         do {
5600                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5601                 memset(req_list, 0, ele_buff_size);
5602
5603                 for (i = 0; i < actual_num; i++) {
5604                         (void)rte_memcpy(req_list[i].mac_addr,
5605                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5606                         req_list[i].vlan_tag =
5607                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5608
5609                         switch (filter[num + i].filter_type) {
5610                         case RTE_MAC_PERFECT_MATCH:
5611                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5612                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5613                                 break;
5614                         case RTE_MACVLAN_PERFECT_MATCH:
5615                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5616                                 break;
5617                         case RTE_MAC_HASH_MATCH:
5618                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5619                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5620                                 break;
5621                         case RTE_MACVLAN_HASH_MATCH:
5622                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5623                                 break;
5624                         default:
5625                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5626                                 ret = I40E_ERR_PARAM;
5627                                 goto DONE;
5628                         }
5629
5630                         req_list[i].queue_number = 0;
5631
5632                         req_list[i].flags = rte_cpu_to_le_16(flags);
5633                 }
5634
5635                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5636                                                 actual_num, NULL);
5637                 if (ret != I40E_SUCCESS) {
5638                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5639                         goto DONE;
5640                 }
5641                 num += actual_num;
5642         } while (num < total);
5643
5644 DONE:
5645         rte_free(req_list);
5646         return ret;
5647 }
5648
5649 static int
5650 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5651                             struct i40e_macvlan_filter *filter,
5652                             int total)
5653 {
5654         int ele_num, ele_buff_size;
5655         int num, actual_num, i;
5656         uint16_t flags;
5657         int ret = I40E_SUCCESS;
5658         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5659         struct i40e_aqc_remove_macvlan_element_data *req_list;
5660
5661         if (filter == NULL  || total == 0)
5662                 return I40E_ERR_PARAM;
5663
5664         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5665         ele_buff_size = hw->aq.asq_buf_size;
5666
5667         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5668         if (req_list == NULL) {
5669                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5670                 return I40E_ERR_NO_MEMORY;
5671         }
5672
5673         num = 0;
5674         do {
5675                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5676                 memset(req_list, 0, ele_buff_size);
5677
5678                 for (i = 0; i < actual_num; i++) {
5679                         (void)rte_memcpy(req_list[i].mac_addr,
5680                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5681                         req_list[i].vlan_tag =
5682                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5683
5684                         switch (filter[num + i].filter_type) {
5685                         case RTE_MAC_PERFECT_MATCH:
5686                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5687                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5688                                 break;
5689                         case RTE_MACVLAN_PERFECT_MATCH:
5690                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5691                                 break;
5692                         case RTE_MAC_HASH_MATCH:
5693                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5694                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5695                                 break;
5696                         case RTE_MACVLAN_HASH_MATCH:
5697                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5698                                 break;
5699                         default:
5700                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5701                                 ret = I40E_ERR_PARAM;
5702                                 goto DONE;
5703                         }
5704                         req_list[i].flags = rte_cpu_to_le_16(flags);
5705                 }
5706
5707                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5708                                                 actual_num, NULL);
5709                 if (ret != I40E_SUCCESS) {
5710                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5711                         goto DONE;
5712                 }
5713                 num += actual_num;
5714         } while (num < total);
5715
5716 DONE:
5717         rte_free(req_list);
5718         return ret;
5719 }
5720
5721 /* Find out specific MAC filter */
5722 static struct i40e_mac_filter *
5723 i40e_find_mac_filter(struct i40e_vsi *vsi,
5724                          struct ether_addr *macaddr)
5725 {
5726         struct i40e_mac_filter *f;
5727
5728         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5729                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5730                         return f;
5731         }
5732
5733         return NULL;
5734 }
5735
5736 static bool
5737 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5738                          uint16_t vlan_id)
5739 {
5740         uint32_t vid_idx, vid_bit;
5741
5742         if (vlan_id > ETH_VLAN_ID_MAX)
5743                 return 0;
5744
5745         vid_idx = I40E_VFTA_IDX(vlan_id);
5746         vid_bit = I40E_VFTA_BIT(vlan_id);
5747
5748         if (vsi->vfta[vid_idx] & vid_bit)
5749                 return 1;
5750         else
5751                 return 0;
5752 }
5753
5754 static void
5755 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5756                          uint16_t vlan_id, bool on)
5757 {
5758         uint32_t vid_idx, vid_bit;
5759
5760         if (vlan_id > ETH_VLAN_ID_MAX)
5761                 return;
5762
5763         vid_idx = I40E_VFTA_IDX(vlan_id);
5764         vid_bit = I40E_VFTA_BIT(vlan_id);
5765
5766         if (on)
5767                 vsi->vfta[vid_idx] |= vid_bit;
5768         else
5769                 vsi->vfta[vid_idx] &= ~vid_bit;
5770 }
5771
5772 /**
5773  * Find all vlan options for specific mac addr,
5774  * return with actual vlan found.
5775  */
5776 static inline int
5777 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5778                            struct i40e_macvlan_filter *mv_f,
5779                            int num, struct ether_addr *addr)
5780 {
5781         int i;
5782         uint32_t j, k;
5783
5784         /**
5785          * Not to use i40e_find_vlan_filter to decrease the loop time,
5786          * although the code looks complex.
5787           */
5788         if (num < vsi->vlan_num)
5789                 return I40E_ERR_PARAM;
5790
5791         i = 0;
5792         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5793                 if (vsi->vfta[j]) {
5794                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5795                                 if (vsi->vfta[j] & (1 << k)) {
5796                                         if (i > num - 1) {
5797                                                 PMD_DRV_LOG(ERR, "vlan number "
5798                                                             "not match");
5799                                                 return I40E_ERR_PARAM;
5800                                         }
5801                                         (void)rte_memcpy(&mv_f[i].macaddr,
5802                                                         addr, ETH_ADDR_LEN);
5803                                         mv_f[i].vlan_id =
5804                                                 j * I40E_UINT32_BIT_SIZE + k;
5805                                         i++;
5806                                 }
5807                         }
5808                 }
5809         }
5810         return I40E_SUCCESS;
5811 }
5812
5813 static inline int
5814 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5815                            struct i40e_macvlan_filter *mv_f,
5816                            int num,
5817                            uint16_t vlan)
5818 {
5819         int i = 0;
5820         struct i40e_mac_filter *f;
5821
5822         if (num < vsi->mac_num)
5823                 return I40E_ERR_PARAM;
5824
5825         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5826                 if (i > num - 1) {
5827                         PMD_DRV_LOG(ERR, "buffer number not match");
5828                         return I40E_ERR_PARAM;
5829                 }
5830                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5831                                 ETH_ADDR_LEN);
5832                 mv_f[i].vlan_id = vlan;
5833                 mv_f[i].filter_type = f->mac_info.filter_type;
5834                 i++;
5835         }
5836
5837         return I40E_SUCCESS;
5838 }
5839
5840 static int
5841 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5842 {
5843         int i, num;
5844         struct i40e_mac_filter *f;
5845         struct i40e_macvlan_filter *mv_f;
5846         int ret = I40E_SUCCESS;
5847
5848         if (vsi == NULL || vsi->mac_num == 0)
5849                 return I40E_ERR_PARAM;
5850
5851         /* Case that no vlan is set */
5852         if (vsi->vlan_num == 0)
5853                 num = vsi->mac_num;
5854         else
5855                 num = vsi->mac_num * vsi->vlan_num;
5856
5857         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5858         if (mv_f == NULL) {
5859                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5860                 return I40E_ERR_NO_MEMORY;
5861         }
5862
5863         i = 0;
5864         if (vsi->vlan_num == 0) {
5865                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5866                         (void)rte_memcpy(&mv_f[i].macaddr,
5867                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5868                         mv_f[i].vlan_id = 0;
5869                         i++;
5870                 }
5871         } else {
5872                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5873                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5874                                         vsi->vlan_num, &f->mac_info.mac_addr);
5875                         if (ret != I40E_SUCCESS)
5876                                 goto DONE;
5877                         i += vsi->vlan_num;
5878                 }
5879         }
5880
5881         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5882 DONE:
5883         rte_free(mv_f);
5884
5885         return ret;
5886 }
5887
5888 int
5889 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5890 {
5891         struct i40e_macvlan_filter *mv_f;
5892         int mac_num;
5893         int ret = I40E_SUCCESS;
5894
5895         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5896                 return I40E_ERR_PARAM;
5897
5898         /* If it's already set, just return */
5899         if (i40e_find_vlan_filter(vsi,vlan))
5900                 return I40E_SUCCESS;
5901
5902         mac_num = vsi->mac_num;
5903
5904         if (mac_num == 0) {
5905                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5906                 return I40E_ERR_PARAM;
5907         }
5908
5909         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5910
5911         if (mv_f == NULL) {
5912                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5913                 return I40E_ERR_NO_MEMORY;
5914         }
5915
5916         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5917
5918         if (ret != I40E_SUCCESS)
5919                 goto DONE;
5920
5921         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5922
5923         if (ret != I40E_SUCCESS)
5924                 goto DONE;
5925
5926         i40e_set_vlan_filter(vsi, vlan, 1);
5927
5928         vsi->vlan_num++;
5929         ret = I40E_SUCCESS;
5930 DONE:
5931         rte_free(mv_f);
5932         return ret;
5933 }
5934
5935 int
5936 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5937 {
5938         struct i40e_macvlan_filter *mv_f;
5939         int mac_num;
5940         int ret = I40E_SUCCESS;
5941
5942         /**
5943          * Vlan 0 is the generic filter for untagged packets
5944          * and can't be removed.
5945          */
5946         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5947                 return I40E_ERR_PARAM;
5948
5949         /* If can't find it, just return */
5950         if (!i40e_find_vlan_filter(vsi, vlan))
5951                 return I40E_ERR_PARAM;
5952
5953         mac_num = vsi->mac_num;
5954
5955         if (mac_num == 0) {
5956                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5957                 return I40E_ERR_PARAM;
5958         }
5959
5960         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5961
5962         if (mv_f == NULL) {
5963                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5964                 return I40E_ERR_NO_MEMORY;
5965         }
5966
5967         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5968
5969         if (ret != I40E_SUCCESS)
5970                 goto DONE;
5971
5972         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5973
5974         if (ret != I40E_SUCCESS)
5975                 goto DONE;
5976
5977         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5978         if (vsi->vlan_num == 1) {
5979                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5980                 if (ret != I40E_SUCCESS)
5981                         goto DONE;
5982
5983                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5984                 if (ret != I40E_SUCCESS)
5985                         goto DONE;
5986         }
5987
5988         i40e_set_vlan_filter(vsi, vlan, 0);
5989
5990         vsi->vlan_num--;
5991         ret = I40E_SUCCESS;
5992 DONE:
5993         rte_free(mv_f);
5994         return ret;
5995 }
5996
5997 int
5998 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5999 {
6000         struct i40e_mac_filter *f;
6001         struct i40e_macvlan_filter *mv_f;
6002         int i, vlan_num = 0;
6003         int ret = I40E_SUCCESS;
6004
6005         /* If it's add and we've config it, return */
6006         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6007         if (f != NULL)
6008                 return I40E_SUCCESS;
6009         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6010                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6011
6012                 /**
6013                  * If vlan_num is 0, that's the first time to add mac,
6014                  * set mask for vlan_id 0.
6015                  */
6016                 if (vsi->vlan_num == 0) {
6017                         i40e_set_vlan_filter(vsi, 0, 1);
6018                         vsi->vlan_num = 1;
6019                 }
6020                 vlan_num = vsi->vlan_num;
6021         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6022                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6023                 vlan_num = 1;
6024
6025         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6026         if (mv_f == NULL) {
6027                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6028                 return I40E_ERR_NO_MEMORY;
6029         }
6030
6031         for (i = 0; i < vlan_num; i++) {
6032                 mv_f[i].filter_type = mac_filter->filter_type;
6033                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6034                                 ETH_ADDR_LEN);
6035         }
6036
6037         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6038                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6039                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6040                                         &mac_filter->mac_addr);
6041                 if (ret != I40E_SUCCESS)
6042                         goto DONE;
6043         }
6044
6045         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6046         if (ret != I40E_SUCCESS)
6047                 goto DONE;
6048
6049         /* Add the mac addr into mac list */
6050         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6051         if (f == NULL) {
6052                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6053                 ret = I40E_ERR_NO_MEMORY;
6054                 goto DONE;
6055         }
6056         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6057                         ETH_ADDR_LEN);
6058         f->mac_info.filter_type = mac_filter->filter_type;
6059         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6060         vsi->mac_num++;
6061
6062         ret = I40E_SUCCESS;
6063 DONE:
6064         rte_free(mv_f);
6065
6066         return ret;
6067 }
6068
6069 int
6070 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6071 {
6072         struct i40e_mac_filter *f;
6073         struct i40e_macvlan_filter *mv_f;
6074         int i, vlan_num;
6075         enum rte_mac_filter_type filter_type;
6076         int ret = I40E_SUCCESS;
6077
6078         /* Can't find it, return an error */
6079         f = i40e_find_mac_filter(vsi, addr);
6080         if (f == NULL)
6081                 return I40E_ERR_PARAM;
6082
6083         vlan_num = vsi->vlan_num;
6084         filter_type = f->mac_info.filter_type;
6085         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6086                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6087                 if (vlan_num == 0) {
6088                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6089                         return I40E_ERR_PARAM;
6090                 }
6091         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6092                         filter_type == RTE_MAC_HASH_MATCH)
6093                 vlan_num = 1;
6094
6095         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6096         if (mv_f == NULL) {
6097                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6098                 return I40E_ERR_NO_MEMORY;
6099         }
6100
6101         for (i = 0; i < vlan_num; i++) {
6102                 mv_f[i].filter_type = filter_type;
6103                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6104                                 ETH_ADDR_LEN);
6105         }
6106         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6107                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6108                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6109                 if (ret != I40E_SUCCESS)
6110                         goto DONE;
6111         }
6112
6113         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6114         if (ret != I40E_SUCCESS)
6115                 goto DONE;
6116
6117         /* Remove the mac addr into mac list */
6118         TAILQ_REMOVE(&vsi->mac_list, f, next);
6119         rte_free(f);
6120         vsi->mac_num--;
6121
6122         ret = I40E_SUCCESS;
6123 DONE:
6124         rte_free(mv_f);
6125         return ret;
6126 }
6127
6128 /* Configure hash enable flags for RSS */
6129 uint64_t
6130 i40e_config_hena(uint64_t flags)
6131 {
6132         uint64_t hena = 0;
6133
6134         if (!flags)
6135                 return hena;
6136
6137         if (flags & ETH_RSS_FRAG_IPV4)
6138                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6139         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6140 #ifdef X722_SUPPORT
6141                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6142                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6143 #else
6144                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6145 #endif
6146         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6147 #ifdef X722_SUPPORT
6148                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6149                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6150                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6151 #else
6152                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6153 #endif
6154         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6155                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6156         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6157                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6158         if (flags & ETH_RSS_FRAG_IPV6)
6159                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6160         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6161 #ifdef X722_SUPPORT
6162                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6163                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6164 #else
6165                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6166 #endif
6167         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6168 #ifdef X722_SUPPORT
6169                 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6170                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6171                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6172 #else
6173                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6174 #endif
6175         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6176                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6177         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6178                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6179         if (flags & ETH_RSS_L2_PAYLOAD)
6180                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6181
6182         return hena;
6183 }
6184
6185 /* Parse the hash enable flags */
6186 uint64_t
6187 i40e_parse_hena(uint64_t flags)
6188 {
6189         uint64_t rss_hf = 0;
6190
6191         if (!flags)
6192                 return rss_hf;
6193         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6194                 rss_hf |= ETH_RSS_FRAG_IPV4;
6195         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6196                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6197 #ifdef X722_SUPPORT
6198         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6199                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6200 #endif
6201         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6202                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6203 #ifdef X722_SUPPORT
6204         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6205                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6206         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6207                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6208 #endif
6209         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6210                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6211         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6212                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6213         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6214                 rss_hf |= ETH_RSS_FRAG_IPV6;
6215         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6216                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6217 #ifdef X722_SUPPORT
6218         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6219                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6220 #endif
6221         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6222                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6223 #ifdef X722_SUPPORT
6224         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6225                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6226         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6227                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6228 #endif
6229         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6230                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6231         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6232                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6233         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6234                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6235
6236         return rss_hf;
6237 }
6238
6239 /* Disable RSS */
6240 static void
6241 i40e_pf_disable_rss(struct i40e_pf *pf)
6242 {
6243         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6244         uint64_t hena;
6245
6246         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6247         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6248         hena &= ~I40E_RSS_HENA_ALL;
6249         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6250         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6251         I40E_WRITE_FLUSH(hw);
6252 }
6253
6254 static int
6255 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6256 {
6257         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6258         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6259         int ret = 0;
6260
6261         if (!key || key_len == 0) {
6262                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6263                 return 0;
6264         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6265                 sizeof(uint32_t)) {
6266                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6267                 return -EINVAL;
6268         }
6269
6270         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6271                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6272                         (struct i40e_aqc_get_set_rss_key_data *)key;
6273
6274                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6275                 if (ret)
6276                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6277                                      "via AQ");
6278         } else {
6279                 uint32_t *hash_key = (uint32_t *)key;
6280                 uint16_t i;
6281
6282                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6283                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6284                 I40E_WRITE_FLUSH(hw);
6285         }
6286
6287         return ret;
6288 }
6289
6290 static int
6291 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6292 {
6293         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6294         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6295         int ret;
6296
6297         if (!key || !key_len)
6298                 return -EINVAL;
6299
6300         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6301                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6302                         (struct i40e_aqc_get_set_rss_key_data *)key);
6303                 if (ret) {
6304                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6305                         return ret;
6306                 }
6307         } else {
6308                 uint32_t *key_dw = (uint32_t *)key;
6309                 uint16_t i;
6310
6311                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6312                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6313         }
6314         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6315
6316         return 0;
6317 }
6318
6319 static int
6320 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6321 {
6322         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6323         uint64_t rss_hf;
6324         uint64_t hena;
6325         int ret;
6326
6327         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6328                                rss_conf->rss_key_len);
6329         if (ret)
6330                 return ret;
6331
6332         rss_hf = rss_conf->rss_hf;
6333         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6334         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6335         hena &= ~I40E_RSS_HENA_ALL;
6336         hena |= i40e_config_hena(rss_hf);
6337         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6338         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6339         I40E_WRITE_FLUSH(hw);
6340
6341         return 0;
6342 }
6343
6344 static int
6345 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6346                          struct rte_eth_rss_conf *rss_conf)
6347 {
6348         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6349         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6350         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6351         uint64_t hena;
6352
6353         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6354         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6355         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6356                 if (rss_hf != 0) /* Enable RSS */
6357                         return -EINVAL;
6358                 return 0; /* Nothing to do */
6359         }
6360         /* RSS enabled */
6361         if (rss_hf == 0) /* Disable RSS */
6362                 return -EINVAL;
6363
6364         return i40e_hw_rss_hash_set(pf, rss_conf);
6365 }
6366
6367 static int
6368 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6369                            struct rte_eth_rss_conf *rss_conf)
6370 {
6371         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6372         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6373         uint64_t hena;
6374
6375         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6376                          &rss_conf->rss_key_len);
6377
6378         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6379         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6380         rss_conf->rss_hf = i40e_parse_hena(hena);
6381
6382         return 0;
6383 }
6384
6385 static int
6386 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6387 {
6388         switch (filter_type) {
6389         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6390                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6391                 break;
6392         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6393                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6394                 break;
6395         case RTE_TUNNEL_FILTER_IMAC_TENID:
6396                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6397                 break;
6398         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6399                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6400                 break;
6401         case ETH_TUNNEL_FILTER_IMAC:
6402                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6403                 break;
6404         case ETH_TUNNEL_FILTER_OIP:
6405                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6406                 break;
6407         case ETH_TUNNEL_FILTER_IIP:
6408                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6409                 break;
6410         default:
6411                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6412                 return -EINVAL;
6413         }
6414
6415         return 0;
6416 }
6417
6418 static int
6419 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6420                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6421                         uint8_t add)
6422 {
6423         uint16_t ip_type;
6424         uint32_t ipv4_addr;
6425         uint8_t i, tun_type = 0;
6426         /* internal varialbe to convert ipv6 byte order */
6427         uint32_t convert_ipv6[4];
6428         int val, ret = 0;
6429         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6430         struct i40e_vsi *vsi = pf->main_vsi;
6431         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6432         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6433
6434         cld_filter = rte_zmalloc("tunnel_filter",
6435                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6436                 0);
6437
6438         if (NULL == cld_filter) {
6439                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6440                 return -EINVAL;
6441         }
6442         pfilter = cld_filter;
6443
6444         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6445         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6446
6447         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6448         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6449                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6450                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6451                 rte_memcpy(&pfilter->ipaddr.v4.data,
6452                                 &rte_cpu_to_le_32(ipv4_addr),
6453                                 sizeof(pfilter->ipaddr.v4.data));
6454         } else {
6455                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6456                 for (i = 0; i < 4; i++) {
6457                         convert_ipv6[i] =
6458                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6459                 }
6460                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6461                                 sizeof(pfilter->ipaddr.v6.data));
6462         }
6463
6464         /* check tunneled type */
6465         switch (tunnel_filter->tunnel_type) {
6466         case RTE_TUNNEL_TYPE_VXLAN:
6467                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6468                 break;
6469         case RTE_TUNNEL_TYPE_NVGRE:
6470                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6471                 break;
6472         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6473                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6474                 break;
6475         default:
6476                 /* Other tunnel types is not supported. */
6477                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6478                 rte_free(cld_filter);
6479                 return -EINVAL;
6480         }
6481
6482         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6483                                                 &pfilter->flags);
6484         if (val < 0) {
6485                 rte_free(cld_filter);
6486                 return -EINVAL;
6487         }
6488
6489         pfilter->flags |= rte_cpu_to_le_16(
6490                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6491                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6492         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6493         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6494
6495         if (add)
6496                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6497         else
6498                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6499                                                 cld_filter, 1);
6500
6501         rte_free(cld_filter);
6502         return ret;
6503 }
6504
6505 static int
6506 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6507 {
6508         uint8_t i;
6509
6510         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6511                 if (pf->vxlan_ports[i] == port)
6512                         return i;
6513         }
6514
6515         return -1;
6516 }
6517
6518 static int
6519 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6520 {
6521         int  idx, ret;
6522         uint8_t filter_idx;
6523         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6524
6525         idx = i40e_get_vxlan_port_idx(pf, port);
6526
6527         /* Check if port already exists */
6528         if (idx >= 0) {
6529                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6530                 return -EINVAL;
6531         }
6532
6533         /* Now check if there is space to add the new port */
6534         idx = i40e_get_vxlan_port_idx(pf, 0);
6535         if (idx < 0) {
6536                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6537                         "not adding port %d", port);
6538                 return -ENOSPC;
6539         }
6540
6541         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6542                                         &filter_idx, NULL);
6543         if (ret < 0) {
6544                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6545                 return -1;
6546         }
6547
6548         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6549                          port,  filter_idx);
6550
6551         /* New port: add it and mark its index in the bitmap */
6552         pf->vxlan_ports[idx] = port;
6553         pf->vxlan_bitmap |= (1 << idx);
6554
6555         if (!(pf->flags & I40E_FLAG_VXLAN))
6556                 pf->flags |= I40E_FLAG_VXLAN;
6557
6558         return 0;
6559 }
6560
6561 static int
6562 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6563 {
6564         int idx;
6565         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6566
6567         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6568                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6569                 return -EINVAL;
6570         }
6571
6572         idx = i40e_get_vxlan_port_idx(pf, port);
6573
6574         if (idx < 0) {
6575                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6576                 return -EINVAL;
6577         }
6578
6579         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6580                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6581                 return -1;
6582         }
6583
6584         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6585                         port, idx);
6586
6587         pf->vxlan_ports[idx] = 0;
6588         pf->vxlan_bitmap &= ~(1 << idx);
6589
6590         if (!pf->vxlan_bitmap)
6591                 pf->flags &= ~I40E_FLAG_VXLAN;
6592
6593         return 0;
6594 }
6595
6596 /* Add UDP tunneling port */
6597 static int
6598 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6599                              struct rte_eth_udp_tunnel *udp_tunnel)
6600 {
6601         int ret = 0;
6602         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6603
6604         if (udp_tunnel == NULL)
6605                 return -EINVAL;
6606
6607         switch (udp_tunnel->prot_type) {
6608         case RTE_TUNNEL_TYPE_VXLAN:
6609                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6610                 break;
6611
6612         case RTE_TUNNEL_TYPE_GENEVE:
6613         case RTE_TUNNEL_TYPE_TEREDO:
6614                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6615                 ret = -1;
6616                 break;
6617
6618         default:
6619                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6620                 ret = -1;
6621                 break;
6622         }
6623
6624         return ret;
6625 }
6626
6627 /* Remove UDP tunneling port */
6628 static int
6629 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6630                              struct rte_eth_udp_tunnel *udp_tunnel)
6631 {
6632         int ret = 0;
6633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6634
6635         if (udp_tunnel == NULL)
6636                 return -EINVAL;
6637
6638         switch (udp_tunnel->prot_type) {
6639         case RTE_TUNNEL_TYPE_VXLAN:
6640                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6641                 break;
6642         case RTE_TUNNEL_TYPE_GENEVE:
6643         case RTE_TUNNEL_TYPE_TEREDO:
6644                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6645                 ret = -1;
6646                 break;
6647         default:
6648                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6649                 ret = -1;
6650                 break;
6651         }
6652
6653         return ret;
6654 }
6655
6656 /* Calculate the maximum number of contiguous PF queues that are configured */
6657 static int
6658 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6659 {
6660         struct rte_eth_dev_data *data = pf->dev_data;
6661         int i, num;
6662         struct i40e_rx_queue *rxq;
6663
6664         num = 0;
6665         for (i = 0; i < pf->lan_nb_qps; i++) {
6666                 rxq = data->rx_queues[i];
6667                 if (rxq && rxq->q_set)
6668                         num++;
6669                 else
6670                         break;
6671         }
6672
6673         return num;
6674 }
6675
6676 /* Configure RSS */
6677 static int
6678 i40e_pf_config_rss(struct i40e_pf *pf)
6679 {
6680         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6681         struct rte_eth_rss_conf rss_conf;
6682         uint32_t i, lut = 0;
6683         uint16_t j, num;
6684
6685         /*
6686          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6687          * It's necessary to calulate the actual PF queues that are configured.
6688          */
6689         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6690                 num = i40e_pf_calc_configured_queues_num(pf);
6691         else
6692                 num = pf->dev_data->nb_rx_queues;
6693
6694         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6695         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6696                         num);
6697
6698         if (num == 0) {
6699                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6700                 return -ENOTSUP;
6701         }
6702
6703         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6704                 if (j == num)
6705                         j = 0;
6706                 lut = (lut << 8) | (j & ((0x1 <<
6707                         hw->func_caps.rss_table_entry_width) - 1));
6708                 if ((i & 3) == 3)
6709                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6710         }
6711
6712         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6713         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6714                 i40e_pf_disable_rss(pf);
6715                 return 0;
6716         }
6717         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6718                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6719                 /* Random default keys */
6720                 static uint32_t rss_key_default[] = {0x6b793944,
6721                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6722                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6723                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6724
6725                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6726                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6727                                                         sizeof(uint32_t);
6728         }
6729
6730         return i40e_hw_rss_hash_set(pf, &rss_conf);
6731 }
6732
6733 static int
6734 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6735                                struct rte_eth_tunnel_filter_conf *filter)
6736 {
6737         if (pf == NULL || filter == NULL) {
6738                 PMD_DRV_LOG(ERR, "Invalid parameter");
6739                 return -EINVAL;
6740         }
6741
6742         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6743                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6744                 return -EINVAL;
6745         }
6746
6747         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6748                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6749                 return -EINVAL;
6750         }
6751
6752         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6753                 (is_zero_ether_addr(&filter->outer_mac))) {
6754                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6755                 return -EINVAL;
6756         }
6757
6758         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6759                 (is_zero_ether_addr(&filter->inner_mac))) {
6760                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6761                 return -EINVAL;
6762         }
6763
6764         return 0;
6765 }
6766
6767 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6768 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6769 static int
6770 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6771 {
6772         uint32_t val, reg;
6773         int ret = -EINVAL;
6774
6775         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6776         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6777
6778         if (len == 3) {
6779                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6780         } else if (len == 4) {
6781                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6782         } else {
6783                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6784                 return ret;
6785         }
6786
6787         if (reg != val) {
6788                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6789                                                    reg, NULL);
6790                 if (ret != 0)
6791                         return ret;
6792         } else {
6793                 ret = 0;
6794         }
6795         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6796                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6797
6798         return ret;
6799 }
6800
6801 static int
6802 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6803 {
6804         int ret = -EINVAL;
6805
6806         if (!hw || !cfg)
6807                 return -EINVAL;
6808
6809         switch (cfg->cfg_type) {
6810         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6811                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6812                 break;
6813         default:
6814                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6815                 break;
6816         }
6817
6818         return ret;
6819 }
6820
6821 static int
6822 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6823                                enum rte_filter_op filter_op,
6824                                void *arg)
6825 {
6826         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6827         int ret = I40E_ERR_PARAM;
6828
6829         switch (filter_op) {
6830         case RTE_ETH_FILTER_SET:
6831                 ret = i40e_dev_global_config_set(hw,
6832                         (struct rte_eth_global_cfg *)arg);
6833                 break;
6834         default:
6835                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6836                 break;
6837         }
6838
6839         return ret;
6840 }
6841
6842 static int
6843 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6844                           enum rte_filter_op filter_op,
6845                           void *arg)
6846 {
6847         struct rte_eth_tunnel_filter_conf *filter;
6848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6849         int ret = I40E_SUCCESS;
6850
6851         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6852
6853         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6854                 return I40E_ERR_PARAM;
6855
6856         switch (filter_op) {
6857         case RTE_ETH_FILTER_NOP:
6858                 if (!(pf->flags & I40E_FLAG_VXLAN))
6859                         ret = I40E_NOT_SUPPORTED;
6860                 break;
6861         case RTE_ETH_FILTER_ADD:
6862                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6863                 break;
6864         case RTE_ETH_FILTER_DELETE:
6865                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6866                 break;
6867         default:
6868                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6869                 ret = I40E_ERR_PARAM;
6870                 break;
6871         }
6872
6873         return ret;
6874 }
6875
6876 static int
6877 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6878 {
6879         int ret = 0;
6880         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6881
6882         /* RSS setup */
6883         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6884                 ret = i40e_pf_config_rss(pf);
6885         else
6886                 i40e_pf_disable_rss(pf);
6887
6888         return ret;
6889 }
6890
6891 /* Get the symmetric hash enable configurations per port */
6892 static void
6893 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6894 {
6895         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6896
6897         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6898 }
6899
6900 /* Set the symmetric hash enable configurations per port */
6901 static void
6902 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6903 {
6904         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6905
6906         if (enable > 0) {
6907                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6908                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6909                                                         "been enabled");
6910                         return;
6911                 }
6912                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6913         } else {
6914                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6915                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6916                                                         "been disabled");
6917                         return;
6918                 }
6919                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6920         }
6921         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6922         I40E_WRITE_FLUSH(hw);
6923 }
6924
6925 /*
6926  * Get global configurations of hash function type and symmetric hash enable
6927  * per flow type (pctype). Note that global configuration means it affects all
6928  * the ports on the same NIC.
6929  */
6930 static int
6931 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6932                                    struct rte_eth_hash_global_conf *g_cfg)
6933 {
6934         uint32_t reg, mask = I40E_FLOW_TYPES;
6935         uint16_t i;
6936         enum i40e_filter_pctype pctype;
6937
6938         memset(g_cfg, 0, sizeof(*g_cfg));
6939         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6940         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6941                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6942         else
6943                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6944         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6945                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6946
6947         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6948                 if (!(mask & (1UL << i)))
6949                         continue;
6950                 mask &= ~(1UL << i);
6951                 /* Bit set indicats the coresponding flow type is supported */
6952                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6953                 /* if flowtype is invalid, continue */
6954                 if (!I40E_VALID_FLOW(i))
6955                         continue;
6956                 pctype = i40e_flowtype_to_pctype(i);
6957                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6958                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6959                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6960         }
6961
6962         return 0;
6963 }
6964
6965 static int
6966 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6967 {
6968         uint32_t i;
6969         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6970
6971         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6972                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6973                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6974                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6975                                                 g_cfg->hash_func);
6976                 return -EINVAL;
6977         }
6978
6979         /*
6980          * As i40e supports less than 32 flow types, only first 32 bits need to
6981          * be checked.
6982          */
6983         mask0 = g_cfg->valid_bit_mask[0];
6984         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6985                 if (i == 0) {
6986                         /* Check if any unsupported flow type configured */
6987                         if ((mask0 | i40e_mask) ^ i40e_mask)
6988                                 goto mask_err;
6989                 } else {
6990                         if (g_cfg->valid_bit_mask[i])
6991                                 goto mask_err;
6992                 }
6993         }
6994
6995         return 0;
6996
6997 mask_err:
6998         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6999
7000         return -EINVAL;
7001 }
7002
7003 /*
7004  * Set global configurations of hash function type and symmetric hash enable
7005  * per flow type (pctype). Note any modifying global configuration will affect
7006  * all the ports on the same NIC.
7007  */
7008 static int
7009 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7010                                    struct rte_eth_hash_global_conf *g_cfg)
7011 {
7012         int ret;
7013         uint16_t i;
7014         uint32_t reg;
7015         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7016         enum i40e_filter_pctype pctype;
7017
7018         /* Check the input parameters */
7019         ret = i40e_hash_global_config_check(g_cfg);
7020         if (ret < 0)
7021                 return ret;
7022
7023         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7024                 if (!(mask0 & (1UL << i)))
7025                         continue;
7026                 mask0 &= ~(1UL << i);
7027                 /* if flowtype is invalid, continue */
7028                 if (!I40E_VALID_FLOW(i))
7029                         continue;
7030                 pctype = i40e_flowtype_to_pctype(i);
7031                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7032                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7033                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7034         }
7035
7036         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7037         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7038                 /* Toeplitz */
7039                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7040                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7041                                                                 "Toeplitz");
7042                         goto out;
7043                 }
7044                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7045         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7046                 /* Simple XOR */
7047                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7048                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7049                                                         "Simple XOR");
7050                         goto out;
7051                 }
7052                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7053         } else
7054                 /* Use the default, and keep it as it is */
7055                 goto out;
7056
7057         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7058
7059 out:
7060         I40E_WRITE_FLUSH(hw);
7061
7062         return 0;
7063 }
7064
7065 /**
7066  * Valid input sets for hash and flow director filters per PCTYPE
7067  */
7068 static uint64_t
7069 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7070                 enum rte_filter_type filter)
7071 {
7072         uint64_t valid;
7073
7074         static const uint64_t valid_hash_inset_table[] = {
7075                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7076                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7077                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7078                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7079                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7080                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7081                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7082                         I40E_INSET_FLEX_PAYLOAD,
7083                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7084                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7085                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7086                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7087                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7088                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7089                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7090                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7091                         I40E_INSET_FLEX_PAYLOAD,
7092 #ifdef X722_SUPPORT
7093                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7094                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7095                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7096                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7097                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7098                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7099                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7100                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7101                         I40E_INSET_FLEX_PAYLOAD,
7102                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7103                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7104                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7105                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7106                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7107                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7108                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7109                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7110                         I40E_INSET_FLEX_PAYLOAD,
7111 #endif
7112                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7113                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7114                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7115                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7116                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7117                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7118                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7119                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7120                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7121 #ifdef X722_SUPPORT
7122                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7123                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7124                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7125                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7126                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7127                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7128                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7129                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7130                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7131 #endif
7132                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7133                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7134                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7135                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7136                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7137                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7138                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7139                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7140                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7141                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7142                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7143                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7144                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7145                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7146                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7147                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7148                         I40E_INSET_FLEX_PAYLOAD,
7149                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7150                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7151                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7152                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7153                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7154                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7155                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7156                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7157                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7158                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7159                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7160                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7161                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7162                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7163                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7164                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7165 #ifdef X722_SUPPORT
7166                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7167                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7168                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7169                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7170                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7171                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7172                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7173                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7174                         I40E_INSET_FLEX_PAYLOAD,
7175                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7176                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7177                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7178                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7179                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7180                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7181                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7182                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7183                         I40E_INSET_FLEX_PAYLOAD,
7184 #endif
7185                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7186                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7187                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7188                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7189                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7190                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7191                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7192                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7193                         I40E_INSET_FLEX_PAYLOAD,
7194 #ifdef X722_SUPPORT
7195                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7196                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7197                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7198                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7199                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7200                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7201                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7202                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7203                         I40E_INSET_FLEX_PAYLOAD,
7204 #endif
7205                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7206                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7207                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7208                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7209                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7210                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7211                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7212                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7213                         I40E_INSET_FLEX_PAYLOAD,
7214                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7215                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7216                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7217                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7218                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7219                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7220                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7221                         I40E_INSET_FLEX_PAYLOAD,
7222                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7223                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7224                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7225                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7226                         I40E_INSET_FLEX_PAYLOAD,
7227         };
7228
7229         /**
7230          * Flow director supports only fields defined in
7231          * union rte_eth_fdir_flow.
7232          */
7233         static const uint64_t valid_fdir_inset_table[] = {
7234                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7235                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7236                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7237                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7238                 I40E_INSET_IPV4_TTL,
7239                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7240                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7241                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7242                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7243                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7244 #ifdef X722_SUPPORT
7245                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7246                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7247                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7248                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7249                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7250                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7251                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7252                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7253                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7254                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7255 #endif
7256                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7257                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7258                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7259                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7260                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7261 #ifdef X722_SUPPORT
7262                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7263                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7264                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7265                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7266                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7267 #endif
7268                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7269                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7270                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7271                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7272                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7273                 I40E_INSET_SCTP_VT,
7274                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7275                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7276                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7277                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7278                 I40E_INSET_IPV4_TTL,
7279                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7280                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7281                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7282                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7283                 I40E_INSET_IPV6_HOP_LIMIT,
7284                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7285                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7286                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7287                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7288                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7289 #ifdef X722_SUPPORT
7290                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7291                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7292                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7293                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7294                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7295                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7296                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7297                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7298                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7299                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7300 #endif
7301                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7302                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7303                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7304                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7305                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7306 #ifdef X722_SUPPORT
7307                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7308                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7309                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7310                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7311                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7312 #endif
7313                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7314                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7315                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7316                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7317                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7318                 I40E_INSET_SCTP_VT,
7319                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7320                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7321                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7322                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7323                 I40E_INSET_IPV6_HOP_LIMIT,
7324                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7325                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7326                 I40E_INSET_LAST_ETHER_TYPE,
7327         };
7328
7329         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7330                 return 0;
7331         if (filter == RTE_ETH_FILTER_HASH)
7332                 valid = valid_hash_inset_table[pctype];
7333         else
7334                 valid = valid_fdir_inset_table[pctype];
7335
7336         return valid;
7337 }
7338
7339 /**
7340  * Validate if the input set is allowed for a specific PCTYPE
7341  */
7342 static int
7343 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7344                 enum rte_filter_type filter, uint64_t inset)
7345 {
7346         uint64_t valid;
7347
7348         valid = i40e_get_valid_input_set(pctype, filter);
7349         if (inset & (~valid))
7350                 return -EINVAL;
7351
7352         return 0;
7353 }
7354
7355 /* default input set fields combination per pctype */
7356 static uint64_t
7357 i40e_get_default_input_set(uint16_t pctype)
7358 {
7359         static const uint64_t default_inset_table[] = {
7360                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7361                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7362                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7363                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7364                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7365 #ifdef X722_SUPPORT
7366                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7367                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7368                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7369                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7370                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7371                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7372 #endif
7373                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7374                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7375                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7376 #ifdef X722_SUPPORT
7377                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7378                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7379                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7380 #endif
7381                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7382                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7383                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7384                         I40E_INSET_SCTP_VT,
7385                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7386                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7387                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7388                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7389                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7390                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7391                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7392 #ifdef X722_SUPPORT
7393                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7394                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7395                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7396                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7397                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7398                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7399 #endif
7400                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7401                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7402                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7403 #ifdef X722_SUPPORT
7404                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7405                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7406                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7407 #endif
7408                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7409                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7410                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7411                         I40E_INSET_SCTP_VT,
7412                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7413                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7414                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7415                         I40E_INSET_LAST_ETHER_TYPE,
7416         };
7417
7418         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7419                 return 0;
7420
7421         return default_inset_table[pctype];
7422 }
7423
7424 /**
7425  * Parse the input set from index to logical bit masks
7426  */
7427 static int
7428 i40e_parse_input_set(uint64_t *inset,
7429                      enum i40e_filter_pctype pctype,
7430                      enum rte_eth_input_set_field *field,
7431                      uint16_t size)
7432 {
7433         uint16_t i, j;
7434         int ret = -EINVAL;
7435
7436         static const struct {
7437                 enum rte_eth_input_set_field field;
7438                 uint64_t inset;
7439         } inset_convert_table[] = {
7440                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7441                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7442                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7443                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7444                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7445                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7446                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7447                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7448                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7449                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7450                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7451                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7452                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7453                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7454                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7455                         I40E_INSET_IPV6_NEXT_HDR},
7456                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7457                         I40E_INSET_IPV6_HOP_LIMIT},
7458                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7459                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7460                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7461                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7462                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7463                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7464                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7465                         I40E_INSET_SCTP_VT},
7466                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7467                         I40E_INSET_TUNNEL_DMAC},
7468                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7469                         I40E_INSET_VLAN_TUNNEL},
7470                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7471                         I40E_INSET_TUNNEL_ID},
7472                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7473                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7474                         I40E_INSET_FLEX_PAYLOAD_W1},
7475                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7476                         I40E_INSET_FLEX_PAYLOAD_W2},
7477                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7478                         I40E_INSET_FLEX_PAYLOAD_W3},
7479                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7480                         I40E_INSET_FLEX_PAYLOAD_W4},
7481                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7482                         I40E_INSET_FLEX_PAYLOAD_W5},
7483                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7484                         I40E_INSET_FLEX_PAYLOAD_W6},
7485                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7486                         I40E_INSET_FLEX_PAYLOAD_W7},
7487                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7488                         I40E_INSET_FLEX_PAYLOAD_W8},
7489         };
7490
7491         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7492                 return ret;
7493
7494         /* Only one item allowed for default or all */
7495         if (size == 1) {
7496                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7497                         *inset = i40e_get_default_input_set(pctype);
7498                         return 0;
7499                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7500                         *inset = I40E_INSET_NONE;
7501                         return 0;
7502                 }
7503         }
7504
7505         for (i = 0, *inset = 0; i < size; i++) {
7506                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7507                         if (field[i] == inset_convert_table[j].field) {
7508                                 *inset |= inset_convert_table[j].inset;
7509                                 break;
7510                         }
7511                 }
7512
7513                 /* It contains unsupported input set, return immediately */
7514                 if (j == RTE_DIM(inset_convert_table))
7515                         return ret;
7516         }
7517
7518         return 0;
7519 }
7520
7521 /**
7522  * Translate the input set from bit masks to register aware bit masks
7523  * and vice versa
7524  */
7525 static uint64_t
7526 i40e_translate_input_set_reg(uint64_t input)
7527 {
7528         uint64_t val = 0;
7529         uint16_t i;
7530
7531         static const struct {
7532                 uint64_t inset;
7533                 uint64_t inset_reg;
7534         } inset_map[] = {
7535                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7536                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7537                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7538                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7539                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7540                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7541                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7542                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7543                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7544                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7545                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7546                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7547                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7548                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7549                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7550                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7551                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7552                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7553                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7554                 {I40E_INSET_TUNNEL_DMAC,
7555                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7556                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7557                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7558                 {I40E_INSET_TUNNEL_SRC_PORT,
7559                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7560                 {I40E_INSET_TUNNEL_DST_PORT,
7561                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7562                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7563                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7564                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7565                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7566                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7567                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7568                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7569                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7570                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7571         };
7572
7573         if (input == 0)
7574                 return val;
7575
7576         /* Translate input set to register aware inset */
7577         for (i = 0; i < RTE_DIM(inset_map); i++) {
7578                 if (input & inset_map[i].inset)
7579                         val |= inset_map[i].inset_reg;
7580         }
7581
7582         return val;
7583 }
7584
7585 static int
7586 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7587 {
7588         uint8_t i, idx = 0;
7589         uint64_t inset_need_mask = inset;
7590
7591         static const struct {
7592                 uint64_t inset;
7593                 uint32_t mask;
7594         } inset_mask_map[] = {
7595                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7596                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7597                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7598                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7599                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7600                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7601                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7602                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7603         };
7604
7605         if (!inset || !mask || !nb_elem)
7606                 return 0;
7607
7608         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7609                 /* Clear the inset bit, if no MASK is required,
7610                  * for example proto + ttl
7611                  */
7612                 if ((inset & inset_mask_map[i].inset) ==
7613                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7614                         inset_need_mask &= ~inset_mask_map[i].inset;
7615                 if (!inset_need_mask)
7616                         return 0;
7617         }
7618         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7619                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7620                     inset_mask_map[i].inset) {
7621                         if (idx >= nb_elem) {
7622                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7623                                 return -EINVAL;
7624                         }
7625                         mask[idx] = inset_mask_map[i].mask;
7626                         idx++;
7627                 }
7628         }
7629
7630         return idx;
7631 }
7632
7633 static void
7634 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7635 {
7636         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7637
7638         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7639         if (reg != val)
7640                 i40e_write_rx_ctl(hw, addr, val);
7641         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7642                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7643 }
7644
7645 static void
7646 i40e_filter_input_set_init(struct i40e_pf *pf)
7647 {
7648         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7649         enum i40e_filter_pctype pctype;
7650         uint64_t input_set, inset_reg;
7651         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7652         int num, i;
7653
7654         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7655              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7656                 if (!I40E_VALID_PCTYPE(pctype))
7657                         continue;
7658                 input_set = i40e_get_default_input_set(pctype);
7659
7660                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7661                                                    I40E_INSET_MASK_NUM_REG);
7662                 if (num < 0)
7663                         return;
7664                 inset_reg = i40e_translate_input_set_reg(input_set);
7665
7666                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7667                                       (uint32_t)(inset_reg & UINT32_MAX));
7668                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7669                                      (uint32_t)((inset_reg >>
7670                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7671                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7672                                       (uint32_t)(inset_reg & UINT32_MAX));
7673                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7674                                      (uint32_t)((inset_reg >>
7675                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7676
7677                 for (i = 0; i < num; i++) {
7678                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7679                                              mask_reg[i]);
7680                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7681                                              mask_reg[i]);
7682                 }
7683                 /*clear unused mask registers of the pctype */
7684                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7685                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7686                                              0);
7687                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7688                                              0);
7689                 }
7690                 I40E_WRITE_FLUSH(hw);
7691
7692                 /* store the default input set */
7693                 pf->hash_input_set[pctype] = input_set;
7694                 pf->fdir.input_set[pctype] = input_set;
7695         }
7696 }
7697
7698 int
7699 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7700                          struct rte_eth_input_set_conf *conf)
7701 {
7702         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7703         enum i40e_filter_pctype pctype;
7704         uint64_t input_set, inset_reg = 0;
7705         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7706         int ret, i, num;
7707
7708         if (!conf) {
7709                 PMD_DRV_LOG(ERR, "Invalid pointer");
7710                 return -EFAULT;
7711         }
7712         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7713             conf->op != RTE_ETH_INPUT_SET_ADD) {
7714                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7715                 return -EINVAL;
7716         }
7717
7718         if (!I40E_VALID_FLOW(conf->flow_type)) {
7719                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7720                 return -EINVAL;
7721         }
7722         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7723         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7724                                    conf->inset_size);
7725         if (ret) {
7726                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7727                 return -EINVAL;
7728         }
7729         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7730                                     input_set) != 0) {
7731                 PMD_DRV_LOG(ERR, "Invalid input set");
7732                 return -EINVAL;
7733         }
7734         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7735                 /* get inset value in register */
7736                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7737                 inset_reg <<= I40E_32_BIT_WIDTH;
7738                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7739                 input_set |= pf->hash_input_set[pctype];
7740         }
7741         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7742                                            I40E_INSET_MASK_NUM_REG);
7743         if (num < 0)
7744                 return -EINVAL;
7745
7746         inset_reg |= i40e_translate_input_set_reg(input_set);
7747
7748         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7749                               (uint32_t)(inset_reg & UINT32_MAX));
7750         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7751                              (uint32_t)((inset_reg >>
7752                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7753
7754         for (i = 0; i < num; i++)
7755                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7756                                      mask_reg[i]);
7757         /*clear unused mask registers of the pctype */
7758         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7759                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7760                                      0);
7761         I40E_WRITE_FLUSH(hw);
7762
7763         pf->hash_input_set[pctype] = input_set;
7764         return 0;
7765 }
7766
7767 int
7768 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7769                          struct rte_eth_input_set_conf *conf)
7770 {
7771         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7772         enum i40e_filter_pctype pctype;
7773         uint64_t input_set, inset_reg = 0;
7774         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7775         int ret, i, num;
7776
7777         if (!hw || !conf) {
7778                 PMD_DRV_LOG(ERR, "Invalid pointer");
7779                 return -EFAULT;
7780         }
7781         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7782             conf->op != RTE_ETH_INPUT_SET_ADD) {
7783                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7784                 return -EINVAL;
7785         }
7786
7787         if (!I40E_VALID_FLOW(conf->flow_type)) {
7788                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7789                 return -EINVAL;
7790         }
7791         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7792         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7793                                    conf->inset_size);
7794         if (ret) {
7795                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7796                 return -EINVAL;
7797         }
7798         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7799                                     input_set) != 0) {
7800                 PMD_DRV_LOG(ERR, "Invalid input set");
7801                 return -EINVAL;
7802         }
7803
7804         /* get inset value in register */
7805         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7806         inset_reg <<= I40E_32_BIT_WIDTH;
7807         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7808
7809         /* Can not change the inset reg for flex payload for fdir,
7810          * it is done by writing I40E_PRTQF_FD_FLXINSET
7811          * in i40e_set_flex_mask_on_pctype.
7812          */
7813         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7814                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7815         else
7816                 input_set |= pf->fdir.input_set[pctype];
7817         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7818                                            I40E_INSET_MASK_NUM_REG);
7819         if (num < 0)
7820                 return -EINVAL;
7821
7822         inset_reg |= i40e_translate_input_set_reg(input_set);
7823
7824         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7825                               (uint32_t)(inset_reg & UINT32_MAX));
7826         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7827                              (uint32_t)((inset_reg >>
7828                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7829
7830         for (i = 0; i < num; i++)
7831                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7832                                      mask_reg[i]);
7833         /*clear unused mask registers of the pctype */
7834         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7835                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7836                                      0);
7837         I40E_WRITE_FLUSH(hw);
7838
7839         pf->fdir.input_set[pctype] = input_set;
7840         return 0;
7841 }
7842
7843 static int
7844 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7845 {
7846         int ret = 0;
7847
7848         if (!hw || !info) {
7849                 PMD_DRV_LOG(ERR, "Invalid pointer");
7850                 return -EFAULT;
7851         }
7852
7853         switch (info->info_type) {
7854         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7855                 i40e_get_symmetric_hash_enable_per_port(hw,
7856                                         &(info->info.enable));
7857                 break;
7858         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7859                 ret = i40e_get_hash_filter_global_config(hw,
7860                                 &(info->info.global_conf));
7861                 break;
7862         default:
7863                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7864                                                         info->info_type);
7865                 ret = -EINVAL;
7866                 break;
7867         }
7868
7869         return ret;
7870 }
7871
7872 static int
7873 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7874 {
7875         int ret = 0;
7876
7877         if (!hw || !info) {
7878                 PMD_DRV_LOG(ERR, "Invalid pointer");
7879                 return -EFAULT;
7880         }
7881
7882         switch (info->info_type) {
7883         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7884                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7885                 break;
7886         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7887                 ret = i40e_set_hash_filter_global_config(hw,
7888                                 &(info->info.global_conf));
7889                 break;
7890         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7891                 ret = i40e_hash_filter_inset_select(hw,
7892                                                &(info->info.input_set_conf));
7893                 break;
7894
7895         default:
7896                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7897                                                         info->info_type);
7898                 ret = -EINVAL;
7899                 break;
7900         }
7901
7902         return ret;
7903 }
7904
7905 /* Operations for hash function */
7906 static int
7907 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7908                       enum rte_filter_op filter_op,
7909                       void *arg)
7910 {
7911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7912         int ret = 0;
7913
7914         switch (filter_op) {
7915         case RTE_ETH_FILTER_NOP:
7916                 break;
7917         case RTE_ETH_FILTER_GET:
7918                 ret = i40e_hash_filter_get(hw,
7919                         (struct rte_eth_hash_filter_info *)arg);
7920                 break;
7921         case RTE_ETH_FILTER_SET:
7922                 ret = i40e_hash_filter_set(hw,
7923                         (struct rte_eth_hash_filter_info *)arg);
7924                 break;
7925         default:
7926                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7927                                                                 filter_op);
7928                 ret = -ENOTSUP;
7929                 break;
7930         }
7931
7932         return ret;
7933 }
7934
7935 /*
7936  * Configure ethertype filter, which can director packet by filtering
7937  * with mac address and ether_type or only ether_type
7938  */
7939 static int
7940 i40e_ethertype_filter_set(struct i40e_pf *pf,
7941                         struct rte_eth_ethertype_filter *filter,
7942                         bool add)
7943 {
7944         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7945         struct i40e_control_filter_stats stats;
7946         uint16_t flags = 0;
7947         int ret;
7948
7949         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7950                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7951                 return -EINVAL;
7952         }
7953         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7954                 filter->ether_type == ETHER_TYPE_IPv6) {
7955                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7956                         " control packet filter.", filter->ether_type);
7957                 return -EINVAL;
7958         }
7959         if (filter->ether_type == ETHER_TYPE_VLAN)
7960                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7961                         " not supported.");
7962
7963         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7964                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7965         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7966                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7967         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7968
7969         memset(&stats, 0, sizeof(stats));
7970         ret = i40e_aq_add_rem_control_packet_filter(hw,
7971                         filter->mac_addr.addr_bytes,
7972                         filter->ether_type, flags,
7973                         pf->main_vsi->seid,
7974                         filter->queue, add, &stats, NULL);
7975
7976         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7977                          " mac_etype_used = %u, etype_used = %u,"
7978                          " mac_etype_free = %u, etype_free = %u\n",
7979                          ret, stats.mac_etype_used, stats.etype_used,
7980                          stats.mac_etype_free, stats.etype_free);
7981         if (ret < 0)
7982                 return -ENOSYS;
7983         return 0;
7984 }
7985
7986 /*
7987  * Handle operations for ethertype filter.
7988  */
7989 static int
7990 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7991                                 enum rte_filter_op filter_op,
7992                                 void *arg)
7993 {
7994         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7995         int ret = 0;
7996
7997         if (filter_op == RTE_ETH_FILTER_NOP)
7998                 return ret;
7999
8000         if (arg == NULL) {
8001                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8002                             filter_op);
8003                 return -EINVAL;
8004         }
8005
8006         switch (filter_op) {
8007         case RTE_ETH_FILTER_ADD:
8008                 ret = i40e_ethertype_filter_set(pf,
8009                         (struct rte_eth_ethertype_filter *)arg,
8010                         TRUE);
8011                 break;
8012         case RTE_ETH_FILTER_DELETE:
8013                 ret = i40e_ethertype_filter_set(pf,
8014                         (struct rte_eth_ethertype_filter *)arg,
8015                         FALSE);
8016                 break;
8017         default:
8018                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8019                 ret = -ENOSYS;
8020                 break;
8021         }
8022         return ret;
8023 }
8024
8025 static int
8026 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8027                      enum rte_filter_type filter_type,
8028                      enum rte_filter_op filter_op,
8029                      void *arg)
8030 {
8031         int ret = 0;
8032
8033         if (dev == NULL)
8034                 return -EINVAL;
8035
8036         switch (filter_type) {
8037         case RTE_ETH_FILTER_NONE:
8038                 /* For global configuration */
8039                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8040                 break;
8041         case RTE_ETH_FILTER_HASH:
8042                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8043                 break;
8044         case RTE_ETH_FILTER_MACVLAN:
8045                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8046                 break;
8047         case RTE_ETH_FILTER_ETHERTYPE:
8048                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8049                 break;
8050         case RTE_ETH_FILTER_TUNNEL:
8051                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8052                 break;
8053         case RTE_ETH_FILTER_FDIR:
8054                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8055                 break;
8056         default:
8057                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8058                                                         filter_type);
8059                 ret = -EINVAL;
8060                 break;
8061         }
8062
8063         return ret;
8064 }
8065
8066 /*
8067  * Check and enable Extended Tag.
8068  * Enabling Extended Tag is important for 40G performance.
8069  */
8070 static void
8071 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8072 {
8073         uint32_t buf = 0;
8074         int ret;
8075
8076         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8077                                       PCI_DEV_CAP_REG);
8078         if (ret < 0) {
8079                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8080                             PCI_DEV_CAP_REG);
8081                 return;
8082         }
8083         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8084                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8085                 return;
8086         }
8087
8088         buf = 0;
8089         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8090                                       PCI_DEV_CTRL_REG);
8091         if (ret < 0) {
8092                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8093                             PCI_DEV_CTRL_REG);
8094                 return;
8095         }
8096         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8097                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8098                 return;
8099         }
8100         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8101         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8102                                        PCI_DEV_CTRL_REG);
8103         if (ret < 0) {
8104                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8105                             PCI_DEV_CTRL_REG);
8106                 return;
8107         }
8108 }
8109
8110 /*
8111  * As some registers wouldn't be reset unless a global hardware reset,
8112  * hardware initialization is needed to put those registers into an
8113  * expected initial state.
8114  */
8115 static void
8116 i40e_hw_init(struct rte_eth_dev *dev)
8117 {
8118         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8119
8120         i40e_enable_extended_tag(dev);
8121
8122         /* clear the PF Queue Filter control register */
8123         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8124
8125         /* Disable symmetric hash per port */
8126         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8127 }
8128
8129 enum i40e_filter_pctype
8130 i40e_flowtype_to_pctype(uint16_t flow_type)
8131 {
8132         static const enum i40e_filter_pctype pctype_table[] = {
8133                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8134                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8135                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8136                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8137                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8138                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8139                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8140                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8141                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8142                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8143                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8144                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8145                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8146                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8147                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8148                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8149                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8150                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8151                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8152         };
8153
8154         return pctype_table[flow_type];
8155 }
8156
8157 uint16_t
8158 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8159 {
8160         static const uint16_t flowtype_table[] = {
8161                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8162                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8163                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8164 #ifdef X722_SUPPORT
8165                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8166                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8167                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8168                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8169 #endif
8170                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8171                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8172 #ifdef X722_SUPPORT
8173                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8174                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8175 #endif
8176                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8177                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8178                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8179                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8180                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8181                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8182                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8183 #ifdef X722_SUPPORT
8184                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8185                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8186                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8187                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8188 #endif
8189                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8190                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8191 #ifdef X722_SUPPORT
8192                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8193                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8194 #endif
8195                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8196                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8197                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8198                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8199                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8200         };
8201
8202         return flowtype_table[pctype];
8203 }
8204
8205 /*
8206  * On X710, performance number is far from the expectation on recent firmware
8207  * versions; on XL710, performance number is also far from the expectation on
8208  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8209  * mode is enabled and port MAC address is equal to the packet destination MAC
8210  * address. The fix for this issue may not be integrated in the following
8211  * firmware version. So the workaround in software driver is needed. It needs
8212  * to modify the initial values of 3 internal only registers for both X710 and
8213  * XL710. Note that the values for X710 or XL710 could be different, and the
8214  * workaround can be removed when it is fixed in firmware in the future.
8215  */
8216
8217 /* For both X710 and XL710 */
8218 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8219 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8220
8221 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8222 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8223
8224 /* For X710 */
8225 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8226 /* For XL710 */
8227 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8228 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8229
8230 static void
8231 i40e_configure_registers(struct i40e_hw *hw)
8232 {
8233         static struct {
8234                 uint32_t addr;
8235                 uint64_t val;
8236         } reg_table[] = {
8237                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8238                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8239                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8240         };
8241         uint64_t reg;
8242         uint32_t i;
8243         int ret;
8244
8245         for (i = 0; i < RTE_DIM(reg_table); i++) {
8246                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8247                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8248                                 reg_table[i].val =
8249                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8250                         else /* For X710 */
8251                                 reg_table[i].val =
8252                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8253                 }
8254
8255                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8256                                                         &reg, NULL);
8257                 if (ret < 0) {
8258                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8259                                                         reg_table[i].addr);
8260                         break;
8261                 }
8262                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8263                                                 reg_table[i].addr, reg);
8264                 if (reg == reg_table[i].val)
8265                         continue;
8266
8267                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8268                                                 reg_table[i].val, NULL);
8269                 if (ret < 0) {
8270                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8271                                 "address of 0x%"PRIx32, reg_table[i].val,
8272                                                         reg_table[i].addr);
8273                         break;
8274                 }
8275                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8276                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8277         }
8278 }
8279
8280 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8281 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8282 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8283 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8284 static int
8285 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8286 {
8287         uint32_t reg;
8288         int ret;
8289
8290         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8291                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8292                 return -EINVAL;
8293         }
8294
8295         /* Configure for double VLAN RX stripping */
8296         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8297         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8298                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8299                 ret = i40e_aq_debug_write_register(hw,
8300                                                    I40E_VSI_TSR(vsi->vsi_id),
8301                                                    reg, NULL);
8302                 if (ret < 0) {
8303                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8304                                     vsi->vsi_id);
8305                         return I40E_ERR_CONFIG;
8306                 }
8307         }
8308
8309         /* Configure for double VLAN TX insertion */
8310         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8311         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8312                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8313                 ret = i40e_aq_debug_write_register(hw,
8314                                                    I40E_VSI_L2TAGSTXVALID(
8315                                                    vsi->vsi_id), reg, NULL);
8316                 if (ret < 0) {
8317                         PMD_DRV_LOG(ERR, "Failed to update "
8318                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8319                         return I40E_ERR_CONFIG;
8320                 }
8321         }
8322
8323         return 0;
8324 }
8325
8326 /**
8327  * i40e_aq_add_mirror_rule
8328  * @hw: pointer to the hardware structure
8329  * @seid: VEB seid to add mirror rule to
8330  * @dst_id: destination vsi seid
8331  * @entries: Buffer which contains the entities to be mirrored
8332  * @count: number of entities contained in the buffer
8333  * @rule_id:the rule_id of the rule to be added
8334  *
8335  * Add a mirror rule for a given veb.
8336  *
8337  **/
8338 static enum i40e_status_code
8339 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8340                         uint16_t seid, uint16_t dst_id,
8341                         uint16_t rule_type, uint16_t *entries,
8342                         uint16_t count, uint16_t *rule_id)
8343 {
8344         struct i40e_aq_desc desc;
8345         struct i40e_aqc_add_delete_mirror_rule cmd;
8346         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8347                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8348                 &desc.params.raw;
8349         uint16_t buff_len;
8350         enum i40e_status_code status;
8351
8352         i40e_fill_default_direct_cmd_desc(&desc,
8353                                           i40e_aqc_opc_add_mirror_rule);
8354         memset(&cmd, 0, sizeof(cmd));
8355
8356         buff_len = sizeof(uint16_t) * count;
8357         desc.datalen = rte_cpu_to_le_16(buff_len);
8358         if (buff_len > 0)
8359                 desc.flags |= rte_cpu_to_le_16(
8360                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8361         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8362                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8363         cmd.num_entries = rte_cpu_to_le_16(count);
8364         cmd.seid = rte_cpu_to_le_16(seid);
8365         cmd.destination = rte_cpu_to_le_16(dst_id);
8366
8367         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8368         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8369         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8370                          "rule_id = %u"
8371                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8372                          hw->aq.asq_last_status, resp->rule_id,
8373                          resp->mirror_rules_used, resp->mirror_rules_free);
8374         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8375
8376         return status;
8377 }
8378
8379 /**
8380  * i40e_aq_del_mirror_rule
8381  * @hw: pointer to the hardware structure
8382  * @seid: VEB seid to add mirror rule to
8383  * @entries: Buffer which contains the entities to be mirrored
8384  * @count: number of entities contained in the buffer
8385  * @rule_id:the rule_id of the rule to be delete
8386  *
8387  * Delete a mirror rule for a given veb.
8388  *
8389  **/
8390 static enum i40e_status_code
8391 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8392                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8393                 uint16_t count, uint16_t rule_id)
8394 {
8395         struct i40e_aq_desc desc;
8396         struct i40e_aqc_add_delete_mirror_rule cmd;
8397         uint16_t buff_len = 0;
8398         enum i40e_status_code status;
8399         void *buff = NULL;
8400
8401         i40e_fill_default_direct_cmd_desc(&desc,
8402                                           i40e_aqc_opc_delete_mirror_rule);
8403         memset(&cmd, 0, sizeof(cmd));
8404         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8405                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8406                                                           I40E_AQ_FLAG_RD));
8407                 cmd.num_entries = count;
8408                 buff_len = sizeof(uint16_t) * count;
8409                 desc.datalen = rte_cpu_to_le_16(buff_len);
8410                 buff = (void *)entries;
8411         } else
8412                 /* rule id is filled in destination field for deleting mirror rule */
8413                 cmd.destination = rte_cpu_to_le_16(rule_id);
8414
8415         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8416                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8417         cmd.seid = rte_cpu_to_le_16(seid);
8418
8419         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8420         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8421
8422         return status;
8423 }
8424
8425 /**
8426  * i40e_mirror_rule_set
8427  * @dev: pointer to the hardware structure
8428  * @mirror_conf: mirror rule info
8429  * @sw_id: mirror rule's sw_id
8430  * @on: enable/disable
8431  *
8432  * set a mirror rule.
8433  *
8434  **/
8435 static int
8436 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8437                         struct rte_eth_mirror_conf *mirror_conf,
8438                         uint8_t sw_id, uint8_t on)
8439 {
8440         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8441         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8442         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8443         struct i40e_mirror_rule *parent = NULL;
8444         uint16_t seid, dst_seid, rule_id;
8445         uint16_t i, j = 0;
8446         int ret;
8447
8448         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8449
8450         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8451                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8452                         " without veb or vfs.");
8453                 return -ENOSYS;
8454         }
8455         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8456                 PMD_DRV_LOG(ERR, "mirror table is full.");
8457                 return -ENOSPC;
8458         }
8459         if (mirror_conf->dst_pool > pf->vf_num) {
8460                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8461                                  mirror_conf->dst_pool);
8462                 return -EINVAL;
8463         }
8464
8465         seid = pf->main_vsi->veb->seid;
8466
8467         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8468                 if (sw_id <= it->index) {
8469                         mirr_rule = it;
8470                         break;
8471                 }
8472                 parent = it;
8473         }
8474         if (mirr_rule && sw_id == mirr_rule->index) {
8475                 if (on) {
8476                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8477                         return -EEXIST;
8478                 } else {
8479                         ret = i40e_aq_del_mirror_rule(hw, seid,
8480                                         mirr_rule->rule_type,
8481                                         mirr_rule->entries,
8482                                         mirr_rule->num_entries, mirr_rule->id);
8483                         if (ret < 0) {
8484                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8485                                                    " ret = %d, aq_err = %d.",
8486                                                    ret, hw->aq.asq_last_status);
8487                                 return -ENOSYS;
8488                         }
8489                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8490                         rte_free(mirr_rule);
8491                         pf->nb_mirror_rule--;
8492                         return 0;
8493                 }
8494         } else if (!on) {
8495                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8496                 return -ENOENT;
8497         }
8498
8499         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8500                                 sizeof(struct i40e_mirror_rule) , 0);
8501         if (!mirr_rule) {
8502                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8503                 return I40E_ERR_NO_MEMORY;
8504         }
8505         switch (mirror_conf->rule_type) {
8506         case ETH_MIRROR_VLAN:
8507                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8508                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8509                                 mirr_rule->entries[j] =
8510                                         mirror_conf->vlan.vlan_id[i];
8511                                 j++;
8512                         }
8513                 }
8514                 if (j == 0) {
8515                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8516                         rte_free(mirr_rule);
8517                         return -EINVAL;
8518                 }
8519                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8520                 break;
8521         case ETH_MIRROR_VIRTUAL_POOL_UP:
8522         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8523                 /* check if the specified pool bit is out of range */
8524                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8525                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8526                         rte_free(mirr_rule);
8527                         return -EINVAL;
8528                 }
8529                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8530                         if (mirror_conf->pool_mask & (1ULL << i)) {
8531                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8532                                 j++;
8533                         }
8534                 }
8535                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8536                         /* add pf vsi to entries */
8537                         mirr_rule->entries[j] = pf->main_vsi_seid;
8538                         j++;
8539                 }
8540                 if (j == 0) {
8541                         PMD_DRV_LOG(ERR, "pool is not specified.");
8542                         rte_free(mirr_rule);
8543                         return -EINVAL;
8544                 }
8545                 /* egress and ingress in aq commands means from switch but not port */
8546                 mirr_rule->rule_type =
8547                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8548                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8549                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8550                 break;
8551         case ETH_MIRROR_UPLINK_PORT:
8552                 /* egress and ingress in aq commands means from switch but not port*/
8553                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8554                 break;
8555         case ETH_MIRROR_DOWNLINK_PORT:
8556                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8557                 break;
8558         default:
8559                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8560                         mirror_conf->rule_type);
8561                 rte_free(mirr_rule);
8562                 return -EINVAL;
8563         }
8564
8565         /* If the dst_pool is equal to vf_num, consider it as PF */
8566         if (mirror_conf->dst_pool == pf->vf_num)
8567                 dst_seid = pf->main_vsi_seid;
8568         else
8569                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8570
8571         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8572                                       mirr_rule->rule_type, mirr_rule->entries,
8573                                       j, &rule_id);
8574         if (ret < 0) {
8575                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8576                                    " ret = %d, aq_err = %d.",
8577                                    ret, hw->aq.asq_last_status);
8578                 rte_free(mirr_rule);
8579                 return -ENOSYS;
8580         }
8581
8582         mirr_rule->index = sw_id;
8583         mirr_rule->num_entries = j;
8584         mirr_rule->id = rule_id;
8585         mirr_rule->dst_vsi_seid = dst_seid;
8586
8587         if (parent)
8588                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8589         else
8590                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8591
8592         pf->nb_mirror_rule++;
8593         return 0;
8594 }
8595
8596 /**
8597  * i40e_mirror_rule_reset
8598  * @dev: pointer to the device
8599  * @sw_id: mirror rule's sw_id
8600  *
8601  * reset a mirror rule.
8602  *
8603  **/
8604 static int
8605 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8606 {
8607         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8608         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8609         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8610         uint16_t seid;
8611         int ret;
8612
8613         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8614
8615         seid = pf->main_vsi->veb->seid;
8616
8617         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8618                 if (sw_id == it->index) {
8619                         mirr_rule = it;
8620                         break;
8621                 }
8622         }
8623         if (mirr_rule) {
8624                 ret = i40e_aq_del_mirror_rule(hw, seid,
8625                                 mirr_rule->rule_type,
8626                                 mirr_rule->entries,
8627                                 mirr_rule->num_entries, mirr_rule->id);
8628                 if (ret < 0) {
8629                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8630                                            " status = %d, aq_err = %d.",
8631                                            ret, hw->aq.asq_last_status);
8632                         return -ENOSYS;
8633                 }
8634                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8635                 rte_free(mirr_rule);
8636                 pf->nb_mirror_rule--;
8637         } else {
8638                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8639                 return -ENOENT;
8640         }
8641         return 0;
8642 }
8643
8644 static uint64_t
8645 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8646 {
8647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8648         uint64_t systim_cycles;
8649
8650         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8651         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8652                         << 32;
8653
8654         return systim_cycles;
8655 }
8656
8657 static uint64_t
8658 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8659 {
8660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8661         uint64_t rx_tstamp;
8662
8663         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8664         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8665                         << 32;
8666
8667         return rx_tstamp;
8668 }
8669
8670 static uint64_t
8671 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8672 {
8673         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8674         uint64_t tx_tstamp;
8675
8676         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8677         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8678                         << 32;
8679
8680         return tx_tstamp;
8681 }
8682
8683 static void
8684 i40e_start_timecounters(struct rte_eth_dev *dev)
8685 {
8686         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8687         struct i40e_adapter *adapter =
8688                         (struct i40e_adapter *)dev->data->dev_private;
8689         struct rte_eth_link link;
8690         uint32_t tsync_inc_l;
8691         uint32_t tsync_inc_h;
8692
8693         /* Get current link speed. */
8694         memset(&link, 0, sizeof(link));
8695         i40e_dev_link_update(dev, 1);
8696         rte_i40e_dev_atomic_read_link_status(dev, &link);
8697
8698         switch (link.link_speed) {
8699         case ETH_SPEED_NUM_40G:
8700                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8701                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8702                 break;
8703         case ETH_SPEED_NUM_10G:
8704                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8705                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8706                 break;
8707         case ETH_SPEED_NUM_1G:
8708                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8709                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8710                 break;
8711         default:
8712                 tsync_inc_l = 0x0;
8713                 tsync_inc_h = 0x0;
8714         }
8715
8716         /* Set the timesync increment value. */
8717         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8718         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8719
8720         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8721         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8722         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8723
8724         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8725         adapter->systime_tc.cc_shift = 0;
8726         adapter->systime_tc.nsec_mask = 0;
8727
8728         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8729         adapter->rx_tstamp_tc.cc_shift = 0;
8730         adapter->rx_tstamp_tc.nsec_mask = 0;
8731
8732         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8733         adapter->tx_tstamp_tc.cc_shift = 0;
8734         adapter->tx_tstamp_tc.nsec_mask = 0;
8735 }
8736
8737 static int
8738 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8739 {
8740         struct i40e_adapter *adapter =
8741                         (struct i40e_adapter *)dev->data->dev_private;
8742
8743         adapter->systime_tc.nsec += delta;
8744         adapter->rx_tstamp_tc.nsec += delta;
8745         adapter->tx_tstamp_tc.nsec += delta;
8746
8747         return 0;
8748 }
8749
8750 static int
8751 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8752 {
8753         uint64_t ns;
8754         struct i40e_adapter *adapter =
8755                         (struct i40e_adapter *)dev->data->dev_private;
8756
8757         ns = rte_timespec_to_ns(ts);
8758
8759         /* Set the timecounters to a new value. */
8760         adapter->systime_tc.nsec = ns;
8761         adapter->rx_tstamp_tc.nsec = ns;
8762         adapter->tx_tstamp_tc.nsec = ns;
8763
8764         return 0;
8765 }
8766
8767 static int
8768 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8769 {
8770         uint64_t ns, systime_cycles;
8771         struct i40e_adapter *adapter =
8772                         (struct i40e_adapter *)dev->data->dev_private;
8773
8774         systime_cycles = i40e_read_systime_cyclecounter(dev);
8775         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8776         *ts = rte_ns_to_timespec(ns);
8777
8778         return 0;
8779 }
8780
8781 static int
8782 i40e_timesync_enable(struct rte_eth_dev *dev)
8783 {
8784         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8785         uint32_t tsync_ctl_l;
8786         uint32_t tsync_ctl_h;
8787
8788         /* Stop the timesync system time. */
8789         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8790         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8791         /* Reset the timesync system time value. */
8792         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8793         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8794
8795         i40e_start_timecounters(dev);
8796
8797         /* Clear timesync registers. */
8798         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8799         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8800         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8801         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8802         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8803         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8804
8805         /* Enable timestamping of PTP packets. */
8806         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8807         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8808
8809         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8810         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8811         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8812
8813         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8814         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8815
8816         return 0;
8817 }
8818
8819 static int
8820 i40e_timesync_disable(struct rte_eth_dev *dev)
8821 {
8822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8823         uint32_t tsync_ctl_l;
8824         uint32_t tsync_ctl_h;
8825
8826         /* Disable timestamping of transmitted PTP packets. */
8827         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8828         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8829
8830         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8831         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8832
8833         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8834         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8835
8836         /* Reset the timesync increment value. */
8837         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8838         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8839
8840         return 0;
8841 }
8842
8843 static int
8844 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8845                                 struct timespec *timestamp, uint32_t flags)
8846 {
8847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8848         struct i40e_adapter *adapter =
8849                 (struct i40e_adapter *)dev->data->dev_private;
8850
8851         uint32_t sync_status;
8852         uint32_t index = flags & 0x03;
8853         uint64_t rx_tstamp_cycles;
8854         uint64_t ns;
8855
8856         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8857         if ((sync_status & (1 << index)) == 0)
8858                 return -EINVAL;
8859
8860         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8861         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8862         *timestamp = rte_ns_to_timespec(ns);
8863
8864         return 0;
8865 }
8866
8867 static int
8868 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8869                                 struct timespec *timestamp)
8870 {
8871         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8872         struct i40e_adapter *adapter =
8873                 (struct i40e_adapter *)dev->data->dev_private;
8874
8875         uint32_t sync_status;
8876         uint64_t tx_tstamp_cycles;
8877         uint64_t ns;
8878
8879         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8880         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8881                 return -EINVAL;
8882
8883         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8884         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8885         *timestamp = rte_ns_to_timespec(ns);
8886
8887         return 0;
8888 }
8889
8890 /*
8891  * i40e_parse_dcb_configure - parse dcb configure from user
8892  * @dev: the device being configured
8893  * @dcb_cfg: pointer of the result of parse
8894  * @*tc_map: bit map of enabled traffic classes
8895  *
8896  * Returns 0 on success, negative value on failure
8897  */
8898 static int
8899 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8900                          struct i40e_dcbx_config *dcb_cfg,
8901                          uint8_t *tc_map)
8902 {
8903         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8904         uint8_t i, tc_bw, bw_lf;
8905
8906         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8907
8908         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8909         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8910                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8911                 return -EINVAL;
8912         }
8913
8914         /* assume each tc has the same bw */
8915         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8916         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8917                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8918         /* to ensure the sum of tcbw is equal to 100 */
8919         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8920         for (i = 0; i < bw_lf; i++)
8921                 dcb_cfg->etscfg.tcbwtable[i]++;
8922
8923         /* assume each tc has the same Transmission Selection Algorithm */
8924         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8925                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8926
8927         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8928                 dcb_cfg->etscfg.prioritytable[i] =
8929                                 dcb_rx_conf->dcb_tc[i];
8930
8931         /* FW needs one App to configure HW */
8932         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8933         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8934         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8935         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8936
8937         if (dcb_rx_conf->nb_tcs == 0)
8938                 *tc_map = 1; /* tc0 only */
8939         else
8940                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8941
8942         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8943                 dcb_cfg->pfc.willing = 0;
8944                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8945                 dcb_cfg->pfc.pfcenable = *tc_map;
8946         }
8947         return 0;
8948 }
8949
8950
8951 static enum i40e_status_code
8952 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8953                               struct i40e_aqc_vsi_properties_data *info,
8954                               uint8_t enabled_tcmap)
8955 {
8956         enum i40e_status_code ret;
8957         int i, total_tc = 0;
8958         uint16_t qpnum_per_tc, bsf, qp_idx;
8959         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8960         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8961         uint16_t used_queues;
8962
8963         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8964         if (ret != I40E_SUCCESS)
8965                 return ret;
8966
8967         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8968                 if (enabled_tcmap & (1 << i))
8969                         total_tc++;
8970         }
8971         if (total_tc == 0)
8972                 total_tc = 1;
8973         vsi->enabled_tc = enabled_tcmap;
8974
8975         /* different VSI has different queues assigned */
8976         if (vsi->type == I40E_VSI_MAIN)
8977                 used_queues = dev_data->nb_rx_queues -
8978                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8979         else if (vsi->type == I40E_VSI_VMDQ2)
8980                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8981         else {
8982                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8983                 return I40E_ERR_NO_AVAILABLE_VSI;
8984         }
8985
8986         qpnum_per_tc = used_queues / total_tc;
8987         /* Number of queues per enabled TC */
8988         if (qpnum_per_tc == 0) {
8989                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8990                 return I40E_ERR_INVALID_QP_ID;
8991         }
8992         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8993                                 I40E_MAX_Q_PER_TC);
8994         bsf = rte_bsf32(qpnum_per_tc);
8995
8996         /**
8997          * Configure TC and queue mapping parameters, for enabled TC,
8998          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8999          * default queue will serve it.
9000          */
9001         qp_idx = 0;
9002         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9003                 if (vsi->enabled_tc & (1 << i)) {
9004                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9005                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9006                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9007                         qp_idx += qpnum_per_tc;
9008                 } else
9009                         info->tc_mapping[i] = 0;
9010         }
9011
9012         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9013         if (vsi->type == I40E_VSI_SRIOV) {
9014                 info->mapping_flags |=
9015                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9016                 for (i = 0; i < vsi->nb_qps; i++)
9017                         info->queue_mapping[i] =
9018                                 rte_cpu_to_le_16(vsi->base_queue + i);
9019         } else {
9020                 info->mapping_flags |=
9021                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9022                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9023         }
9024         info->valid_sections |=
9025                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9026
9027         return I40E_SUCCESS;
9028 }
9029
9030 /*
9031  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9032  * @veb: VEB to be configured
9033  * @tc_map: enabled TC bitmap
9034  *
9035  * Returns 0 on success, negative value on failure
9036  */
9037 static enum i40e_status_code
9038 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9039 {
9040         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9041         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9042         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9043         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9044         enum i40e_status_code ret = I40E_SUCCESS;
9045         int i;
9046         uint32_t bw_max;
9047
9048         /* Check if enabled_tc is same as existing or new TCs */
9049         if (veb->enabled_tc == tc_map)
9050                 return ret;
9051
9052         /* configure tc bandwidth */
9053         memset(&veb_bw, 0, sizeof(veb_bw));
9054         veb_bw.tc_valid_bits = tc_map;
9055         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9056         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9057                 if (tc_map & BIT_ULL(i))
9058                         veb_bw.tc_bw_share_credits[i] = 1;
9059         }
9060         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9061                                                    &veb_bw, NULL);
9062         if (ret) {
9063                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9064                                   " per TC failed = %d",
9065                                   hw->aq.asq_last_status);
9066                 return ret;
9067         }
9068
9069         memset(&ets_query, 0, sizeof(ets_query));
9070         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9071                                                    &ets_query, NULL);
9072         if (ret != I40E_SUCCESS) {
9073                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9074                                  " configuration %u", hw->aq.asq_last_status);
9075                 return ret;
9076         }
9077         memset(&bw_query, 0, sizeof(bw_query));
9078         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9079                                                   &bw_query, NULL);
9080         if (ret != I40E_SUCCESS) {
9081                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9082                                  " configuration %u", hw->aq.asq_last_status);
9083                 return ret;
9084         }
9085
9086         /* store and print out BW info */
9087         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9088         veb->bw_info.bw_max = ets_query.tc_bw_max;
9089         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9090         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9091         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9092                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9093                      I40E_16_BIT_WIDTH);
9094         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9095                 veb->bw_info.bw_ets_share_credits[i] =
9096                                 bw_query.tc_bw_share_credits[i];
9097                 veb->bw_info.bw_ets_credits[i] =
9098                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9099                 /* 4 bits per TC, 4th bit is reserved */
9100                 veb->bw_info.bw_ets_max[i] =
9101                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9102                                   RTE_LEN2MASK(3, uint8_t));
9103                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9104                             veb->bw_info.bw_ets_share_credits[i]);
9105                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9106                             veb->bw_info.bw_ets_credits[i]);
9107                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9108                             veb->bw_info.bw_ets_max[i]);
9109         }
9110
9111         veb->enabled_tc = tc_map;
9112
9113         return ret;
9114 }
9115
9116
9117 /*
9118  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9119  * @vsi: VSI to be configured
9120  * @tc_map: enabled TC bitmap
9121  *
9122  * Returns 0 on success, negative value on failure
9123  */
9124 static enum i40e_status_code
9125 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9126 {
9127         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9128         struct i40e_vsi_context ctxt;
9129         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9130         enum i40e_status_code ret = I40E_SUCCESS;
9131         int i;
9132
9133         /* Check if enabled_tc is same as existing or new TCs */
9134         if (vsi->enabled_tc == tc_map)
9135                 return ret;
9136
9137         /* configure tc bandwidth */
9138         memset(&bw_data, 0, sizeof(bw_data));
9139         bw_data.tc_valid_bits = tc_map;
9140         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9141         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9142                 if (tc_map & BIT_ULL(i))
9143                         bw_data.tc_bw_credits[i] = 1;
9144         }
9145         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9146         if (ret) {
9147                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9148                         " per TC failed = %d",
9149                         hw->aq.asq_last_status);
9150                 goto out;
9151         }
9152         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9153                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9154
9155         /* Update Queue Pairs Mapping for currently enabled UPs */
9156         ctxt.seid = vsi->seid;
9157         ctxt.pf_num = hw->pf_id;
9158         ctxt.vf_num = 0;
9159         ctxt.uplink_seid = vsi->uplink_seid;
9160         ctxt.info = vsi->info;
9161         i40e_get_cap(hw);
9162         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9163         if (ret)
9164                 goto out;
9165
9166         /* Update the VSI after updating the VSI queue-mapping information */
9167         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9168         if (ret) {
9169                 PMD_INIT_LOG(ERR, "Failed to configure "
9170                             "TC queue mapping = %d",
9171                             hw->aq.asq_last_status);
9172                 goto out;
9173         }
9174         /* update the local VSI info with updated queue map */
9175         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9176                                         sizeof(vsi->info.tc_mapping));
9177         (void)rte_memcpy(&vsi->info.queue_mapping,
9178                         &ctxt.info.queue_mapping,
9179                 sizeof(vsi->info.queue_mapping));
9180         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9181         vsi->info.valid_sections = 0;
9182
9183         /* query and update current VSI BW information */
9184         ret = i40e_vsi_get_bw_config(vsi);
9185         if (ret) {
9186                 PMD_INIT_LOG(ERR,
9187                          "Failed updating vsi bw info, err %s aq_err %s",
9188                          i40e_stat_str(hw, ret),
9189                          i40e_aq_str(hw, hw->aq.asq_last_status));
9190                 goto out;
9191         }
9192
9193         vsi->enabled_tc = tc_map;
9194
9195 out:
9196         return ret;
9197 }
9198
9199 /*
9200  * i40e_dcb_hw_configure - program the dcb setting to hw
9201  * @pf: pf the configuration is taken on
9202  * @new_cfg: new configuration
9203  * @tc_map: enabled TC bitmap
9204  *
9205  * Returns 0 on success, negative value on failure
9206  */
9207 static enum i40e_status_code
9208 i40e_dcb_hw_configure(struct i40e_pf *pf,
9209                       struct i40e_dcbx_config *new_cfg,
9210                       uint8_t tc_map)
9211 {
9212         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9213         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9214         struct i40e_vsi *main_vsi = pf->main_vsi;
9215         struct i40e_vsi_list *vsi_list;
9216         enum i40e_status_code ret;
9217         int i;
9218         uint32_t val;
9219
9220         /* Use the FW API if FW > v4.4*/
9221         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9222               (hw->aq.fw_maj_ver >= 5))) {
9223                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9224                                   " to configure DCB");
9225                 return I40E_ERR_FIRMWARE_API_VERSION;
9226         }
9227
9228         /* Check if need reconfiguration */
9229         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9230                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9231                 return I40E_SUCCESS;
9232         }
9233
9234         /* Copy the new config to the current config */
9235         *old_cfg = *new_cfg;
9236         old_cfg->etsrec = old_cfg->etscfg;
9237         ret = i40e_set_dcb_config(hw);
9238         if (ret) {
9239                 PMD_INIT_LOG(ERR,
9240                          "Set DCB Config failed, err %s aq_err %s\n",
9241                          i40e_stat_str(hw, ret),
9242                          i40e_aq_str(hw, hw->aq.asq_last_status));
9243                 return ret;
9244         }
9245         /* set receive Arbiter to RR mode and ETS scheme by default */
9246         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9247                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9248                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9249                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9250                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9251                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9252                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9253                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9254                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9255                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9256                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9257                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9258                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9259         }
9260         /* get local mib to check whether it is configured correctly */
9261         /* IEEE mode */
9262         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9263         /* Get Local DCB Config */
9264         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9265                                      &hw->local_dcbx_config);
9266
9267         /* if Veb is created, need to update TC of it at first */
9268         if (main_vsi->veb) {
9269                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9270                 if (ret)
9271                         PMD_INIT_LOG(WARNING,
9272                                  "Failed configuring TC for VEB seid=%d\n",
9273                                  main_vsi->veb->seid);
9274         }
9275         /* Update each VSI */
9276         i40e_vsi_config_tc(main_vsi, tc_map);
9277         if (main_vsi->veb) {
9278                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9279                         /* Beside main VSI and VMDQ VSIs, only enable default
9280                          * TC for other VSIs
9281                          */
9282                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9283                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9284                                                          tc_map);
9285                         else
9286                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9287                                                          I40E_DEFAULT_TCMAP);
9288                         if (ret)
9289                                 PMD_INIT_LOG(WARNING,
9290                                          "Failed configuring TC for VSI seid=%d\n",
9291                                          vsi_list->vsi->seid);
9292                         /* continue */
9293                 }
9294         }
9295         return I40E_SUCCESS;
9296 }
9297
9298 /*
9299  * i40e_dcb_init_configure - initial dcb config
9300  * @dev: device being configured
9301  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9302  *
9303  * Returns 0 on success, negative value on failure
9304  */
9305 static int
9306 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9307 {
9308         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9309         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9310         int ret = 0;
9311
9312         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9313                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9314                 return -ENOTSUP;
9315         }
9316
9317         /* DCB initialization:
9318          * Update DCB configuration from the Firmware and configure
9319          * LLDP MIB change event.
9320          */
9321         if (sw_dcb == TRUE) {
9322                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9323                 if (ret != I40E_SUCCESS)
9324                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9325
9326                 ret = i40e_init_dcb(hw);
9327                 /* if sw_dcb, lldp agent is stopped, the return from
9328                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9329                  * adminq status.
9330                  */
9331                 if (ret != I40E_SUCCESS &&
9332                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9333                         memset(&hw->local_dcbx_config, 0,
9334                                 sizeof(struct i40e_dcbx_config));
9335                         /* set dcb default configuration */
9336                         hw->local_dcbx_config.etscfg.willing = 0;
9337                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9338                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9339                         hw->local_dcbx_config.etscfg.tsatable[0] =
9340                                                 I40E_IEEE_TSA_ETS;
9341                         hw->local_dcbx_config.etsrec =
9342                                 hw->local_dcbx_config.etscfg;
9343                         hw->local_dcbx_config.pfc.willing = 0;
9344                         hw->local_dcbx_config.pfc.pfccap =
9345                                                 I40E_MAX_TRAFFIC_CLASS;
9346                         /* FW needs one App to configure HW */
9347                         hw->local_dcbx_config.numapps = 1;
9348                         hw->local_dcbx_config.app[0].selector =
9349                                                 I40E_APP_SEL_ETHTYPE;
9350                         hw->local_dcbx_config.app[0].priority = 3;
9351                         hw->local_dcbx_config.app[0].protocolid =
9352                                                 I40E_APP_PROTOID_FCOE;
9353                         ret = i40e_set_dcb_config(hw);
9354                         if (ret) {
9355                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9356                                         " err = %d, aq_err = %d.", ret,
9357                                           hw->aq.asq_last_status);
9358                                 return -ENOSYS;
9359                         }
9360                 } else {
9361                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9362                                           " aq_err = %d.", ret,
9363                                           hw->aq.asq_last_status);
9364                         return -ENOTSUP;
9365                 }
9366         } else {
9367                 ret = i40e_aq_start_lldp(hw, NULL);
9368                 if (ret != I40E_SUCCESS)
9369                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9370
9371                 ret = i40e_init_dcb(hw);
9372                 if (!ret) {
9373                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9374                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9375                                                   " DCBX offload.");
9376                                 return -ENOTSUP;
9377                         }
9378                 } else {
9379                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9380                                           " aq_err = %d.", ret,
9381                                           hw->aq.asq_last_status);
9382                         return -ENOTSUP;
9383                 }
9384         }
9385         return 0;
9386 }
9387
9388 /*
9389  * i40e_dcb_setup - setup dcb related config
9390  * @dev: device being configured
9391  *
9392  * Returns 0 on success, negative value on failure
9393  */
9394 static int
9395 i40e_dcb_setup(struct rte_eth_dev *dev)
9396 {
9397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9398         struct i40e_dcbx_config dcb_cfg;
9399         uint8_t tc_map = 0;
9400         int ret = 0;
9401
9402         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9403                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9404                 return -ENOTSUP;
9405         }
9406
9407         if (pf->vf_num != 0)
9408                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9409
9410         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9411         if (ret) {
9412                 PMD_INIT_LOG(ERR, "invalid dcb config");
9413                 return -EINVAL;
9414         }
9415         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9416         if (ret) {
9417                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9418                 return -ENOSYS;
9419         }
9420
9421         return 0;
9422 }
9423
9424 static int
9425 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9426                       struct rte_eth_dcb_info *dcb_info)
9427 {
9428         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9429         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9430         struct i40e_vsi *vsi = pf->main_vsi;
9431         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9432         uint16_t bsf, tc_mapping;
9433         int i, j = 0;
9434
9435         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9436                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9437         else
9438                 dcb_info->nb_tcs = 1;
9439         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9440                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9441         for (i = 0; i < dcb_info->nb_tcs; i++)
9442                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9443
9444         /* get queue mapping if vmdq is disabled */
9445         if (!pf->nb_cfg_vmdq_vsi) {
9446                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9447                         if (!(vsi->enabled_tc & (1 << i)))
9448                                 continue;
9449                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9450                         dcb_info->tc_queue.tc_rxq[j][i].base =
9451                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9452                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9453                         dcb_info->tc_queue.tc_txq[j][i].base =
9454                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9455                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9456                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9457                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9458                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9459                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9460                 }
9461                 return 0;
9462         }
9463
9464         /* get queue mapping if vmdq is enabled */
9465         do {
9466                 vsi = pf->vmdq[j].vsi;
9467                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9468                         if (!(vsi->enabled_tc & (1 << i)))
9469                                 continue;
9470                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9471                         dcb_info->tc_queue.tc_rxq[j][i].base =
9472                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9473                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9474                         dcb_info->tc_queue.tc_txq[j][i].base =
9475                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9476                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9477                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9478                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9479                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9480                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9481                 }
9482                 j++;
9483         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9484         return 0;
9485 }
9486
9487 static int
9488 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9489 {
9490         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9491         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9492         uint16_t interval =
9493                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9494         uint16_t msix_intr;
9495
9496         msix_intr = intr_handle->intr_vec[queue_id];
9497         if (msix_intr == I40E_MISC_VEC_ID)
9498                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9499                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9500                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9501                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9502                                (interval <<
9503                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9504         else
9505                 I40E_WRITE_REG(hw,
9506                                I40E_PFINT_DYN_CTLN(msix_intr -
9507                                                    I40E_RX_VEC_START),
9508                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9509                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9510                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9511                                (interval <<
9512                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9513
9514         I40E_WRITE_FLUSH(hw);
9515         rte_intr_enable(&dev->pci_dev->intr_handle);
9516
9517         return 0;
9518 }
9519
9520 static int
9521 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9522 {
9523         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9524         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9525         uint16_t msix_intr;
9526
9527         msix_intr = intr_handle->intr_vec[queue_id];
9528         if (msix_intr == I40E_MISC_VEC_ID)
9529                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9530         else
9531                 I40E_WRITE_REG(hw,
9532                                I40E_PFINT_DYN_CTLN(msix_intr -
9533                                                    I40E_RX_VEC_START),
9534                                0);
9535         I40E_WRITE_FLUSH(hw);
9536
9537         return 0;
9538 }
9539
9540 static int i40e_get_regs(struct rte_eth_dev *dev,
9541                          struct rte_dev_reg_info *regs)
9542 {
9543         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9544         uint32_t *ptr_data = regs->data;
9545         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9546         const struct i40e_reg_info *reg_info;
9547
9548         if (ptr_data == NULL) {
9549                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9550                 regs->width = sizeof(uint32_t);
9551                 return 0;
9552         }
9553
9554         /* The first few registers have to be read using AQ operations */
9555         reg_idx = 0;
9556         while (i40e_regs_adminq[reg_idx].name) {
9557                 reg_info = &i40e_regs_adminq[reg_idx++];
9558                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9559                         for (arr_idx2 = 0;
9560                                         arr_idx2 <= reg_info->count2;
9561                                         arr_idx2++) {
9562                                 reg_offset = arr_idx * reg_info->stride1 +
9563                                         arr_idx2 * reg_info->stride2;
9564                                 reg_offset += reg_info->base_addr;
9565                                 ptr_data[reg_offset >> 2] =
9566                                         i40e_read_rx_ctl(hw, reg_offset);
9567                         }
9568         }
9569
9570         /* The remaining registers can be read using primitives */
9571         reg_idx = 0;
9572         while (i40e_regs_others[reg_idx].name) {
9573                 reg_info = &i40e_regs_others[reg_idx++];
9574                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9575                         for (arr_idx2 = 0;
9576                                         arr_idx2 <= reg_info->count2;
9577                                         arr_idx2++) {
9578                                 reg_offset = arr_idx * reg_info->stride1 +
9579                                         arr_idx2 * reg_info->stride2;
9580                                 reg_offset += reg_info->base_addr;
9581                                 ptr_data[reg_offset >> 2] =
9582                                         I40E_READ_REG(hw, reg_offset);
9583                         }
9584         }
9585
9586         return 0;
9587 }
9588
9589 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9590 {
9591         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9592
9593         /* Convert word count to byte count */
9594         return hw->nvm.sr_size << 1;
9595 }
9596
9597 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9598                            struct rte_dev_eeprom_info *eeprom)
9599 {
9600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9601         uint16_t *data = eeprom->data;
9602         uint16_t offset, length, cnt_words;
9603         int ret_code;
9604
9605         offset = eeprom->offset >> 1;
9606         length = eeprom->length >> 1;
9607         cnt_words = length;
9608
9609         if (offset > hw->nvm.sr_size ||
9610                 offset + length > hw->nvm.sr_size) {
9611                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9612                 return -EINVAL;
9613         }
9614
9615         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9616
9617         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9618         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9619                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9620                 return -EIO;
9621         }
9622
9623         return 0;
9624 }
9625
9626 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9627                                       struct ether_addr *mac_addr)
9628 {
9629         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9630
9631         if (!is_valid_assigned_ether_addr(mac_addr)) {
9632                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9633                 return;
9634         }
9635
9636         /* Flags: 0x3 updates port address */
9637         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9638 }
9639
9640 static int
9641 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9642 {
9643         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9644         struct rte_eth_dev_data *dev_data = pf->dev_data;
9645         uint32_t frame_size = mtu + ETHER_HDR_LEN
9646                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9647         int ret = 0;
9648
9649         /* check if mtu is within the allowed range */
9650         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9651                 return -EINVAL;
9652
9653         /* mtu setting is forbidden if port is start */
9654         if (dev_data->dev_started) {
9655                 PMD_DRV_LOG(ERR,
9656                             "port %d must be stopped before configuration\n",
9657                             dev_data->port_id);
9658                 return -EBUSY;
9659         }
9660
9661         if (frame_size > ETHER_MAX_LEN)
9662                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9663         else
9664                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9665
9666         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9667
9668         return ret;
9669 }