drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44
  45 #define I40E_CLEAR_PXE_WAIT_MS     200
  46
  47 /* Maximun number of capability elements */
  48 #define I40E_MAX_CAP_ELE_NUM       128
  49
  50 /* Wait count and interval */
  51 #define I40E_CHK_Q_ENA_COUNT       1000
  52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  53
  54 /* Maximun number of VSI */
  55 #define I40E_MAX_NUM_VSIS          (384UL)
  56
  57 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  58
  59 /* Flow control default timer */
  60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  61
  62 /* Flow control enable fwd bit */
  63 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  64
  65 /* Receive Packet Buffer size */
  66 #define I40E_RXPBSIZE (968 * 1024)
  67
  68 /* Kilobytes shift */
  69 #define I40E_KILOSHIFT 10
  70
  71 /* Flow control default high water */
  72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  73
  74 /* Flow control default low water */
  75 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Receive Average Packet Size in Byte*/
  78 #define I40E_PACKET_AVERAGE_SIZE 128
  79
  80 /* Mask of PF interrupt causes */
  81 #define I40E_PFINT_ICR0_ENA_MASK ( \
  82                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  83                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  84                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  85                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  86                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  91
  92 #define I40E_FLOW_TYPES ( \
  93         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  94         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 104
 105 /* Additional timesync values. */
 106 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 107 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 108 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 109 #define I40E_PRTTSYN_TSYNENA     0x80000000
 110 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 111 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 /**
 114  * Below are values for writing un-exposed registers suggested
 115  * by silicon experts
 116  */
 117 /* Destination MAC address */
 118 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 119 /* Source MAC address */
 120 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 122 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 124 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 125 /* Single VLAN tag in the inner L2 header */
 126 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 127 /* Source IPv4 address */
 128 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 129 /* Destination IPv4 address */
 130 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 131 /* Source IPv4 address for X722 */
 132 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 133 /* Destination IPv4 address for X722 */
 134 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 135 /* IPv4 Protocol for X722 */
 136 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 137 /* IPv4 Time to Live for X722 */
 138 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 139 /* IPv4 Type of Service (TOS) */
 140 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 141 /* IPv4 Protocol */
 142 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 143 /* IPv4 Time to Live */
 144 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 145 /* Source IPv6 address */
 146 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 147 /* Destination IPv6 address */
 148 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 149 /* IPv6 Traffic Class (TC) */
 150 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 151 /* IPv6 Next Header */
 152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 153 /* IPv6 Hop Limit */
 154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 155 /* Source L4 port */
 156 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 157 /* Destination L4 port */
 158 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 159 /* SCTP verification tag */
 160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 163 /* Source port of tunneling UDP */
 164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 165 /* Destination port of tunneling UDP */
 166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 167 /* UDP Tunneling ID, NVGRE/GRE key */
 168 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 169 /* Last ether type */
 170 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 171 /* Tunneling outer destination IPv4 address */
 172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 173 /* Tunneling outer destination IPv6 address */
 174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 175 /* 1st word of flex payload */
 176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 177 /* 2nd word of flex payload */
 178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 179 /* 3rd word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 181 /* 4th word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 183 /* 5th word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 185 /* 6th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 187 /* 7th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 189 /* 8th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 191 /* all 8 words flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 193 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 194
 195 #define I40E_TRANSLATE_INSET 0
 196 #define I40E_TRANSLATE_REG   1
 197
 198 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 199 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 200 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 201 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 203 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 204
 205 /* PCI offset for querying capability */
 206 #define PCI_DEV_CAP_REG            0xA4
 207 /* PCI offset for enabling/disabling Extended Tag */
 208 #define PCI_DEV_CTRL_REG           0xA8
 209 /* Bit mask of Extended Tag capability */
 210 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 211 /* Bit shift of Extended Tag enable/disable */
 212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 213 /* Bit mask of Extended Tag enable/disable */
 214 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 215
 216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int i40e_dev_configure(struct rte_eth_dev *dev);
 219 static int i40e_dev_start(struct rte_eth_dev *dev);
 220 static void i40e_dev_stop(struct rte_eth_dev *dev);
 221 static void i40e_dev_close(struct rte_eth_dev *dev);
 222 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_stats *stats);
 231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_xstat *xstats, unsigned n);
 233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 234                                      struct rte_eth_xstat_name *xstats_names,
 235                                      unsigned limit);
 236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 238                                             uint16_t queue_id,
 239                                             uint8_t stat_idx,
 240                                             uint8_t is_rx);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 244                               struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 373                                       struct ether_addr *mac_addr);
 374
 375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 376
 377 static int i40e_ethertype_filter_convert(
 378         const struct rte_eth_ethertype_filter *input,
 379         struct i40e_ethertype_filter *filter);
 380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 381                                    struct i40e_ethertype_filter *filter);
 382
 383 static int i40e_tunnel_filter_convert(
 384         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 385         struct i40e_tunnel_filter *tunnel_filter);
 386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 387                                 struct i40e_tunnel_filter *tunnel_filter);
 388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 389
 390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 392 static void i40e_filter_restore(struct i40e_pf *pf);
 393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 394
 395 int i40e_logtype_init;
 396 int i40e_logtype_driver;
 397
 398 static const struct rte_pci_id pci_id_i40e_map[] = {
 399         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 419         { .vendor_id = 0, /* sentinel */ },
 420 };
 421
 422 static const struct eth_dev_ops i40e_eth_dev_ops = {
 423         .dev_configure                = i40e_dev_configure,
 424         .dev_start                    = i40e_dev_start,
 425         .dev_stop                     = i40e_dev_stop,
 426         .dev_close                    = i40e_dev_close,
 427         .dev_reset                    = i40e_dev_reset,
 428         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 429         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 430         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 431         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 432         .dev_set_link_up              = i40e_dev_set_link_up,
 433         .dev_set_link_down            = i40e_dev_set_link_down,
 434         .link_update                  = i40e_dev_link_update,
 435         .stats_get                    = i40e_dev_stats_get,
 436         .xstats_get                   = i40e_dev_xstats_get,
 437         .xstats_get_names             = i40e_dev_xstats_get_names,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .fw_version_get               = i40e_fw_version_get,
 442         .dev_infos_get                = i40e_dev_info_get,
 443         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 444         .vlan_filter_set              = i40e_vlan_filter_set,
 445         .vlan_tpid_set                = i40e_vlan_tpid_set,
 446         .vlan_offload_set             = i40e_vlan_offload_set,
 447         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 448         .vlan_pvid_set                = i40e_vlan_pvid_set,
 449         .rx_queue_start               = i40e_dev_rx_queue_start,
 450         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 451         .tx_queue_start               = i40e_dev_tx_queue_start,
 452         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 453         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 454         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 455         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 456         .rx_queue_release             = i40e_dev_rx_queue_release,
 457         .rx_queue_count               = i40e_dev_rx_queue_count,
 458         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 459         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 460         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 461         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 462         .tx_queue_release             = i40e_dev_tx_queue_release,
 463         .dev_led_on                   = i40e_dev_led_on,
 464         .dev_led_off                  = i40e_dev_led_off,
 465         .flow_ctrl_get                = i40e_flow_ctrl_get,
 466         .flow_ctrl_set                = i40e_flow_ctrl_set,
 467         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 468         .mac_addr_add                 = i40e_macaddr_add,
 469         .mac_addr_remove              = i40e_macaddr_remove,
 470         .reta_update                  = i40e_dev_rss_reta_update,
 471         .reta_query                   = i40e_dev_rss_reta_query,
 472         .rss_hash_update              = i40e_dev_rss_hash_update,
 473         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 474         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 475         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 476         .filter_ctrl                  = i40e_dev_filter_ctrl,
 477         .rxq_info_get                 = i40e_rxq_info_get,
 478         .txq_info_get                 = i40e_txq_info_get,
 479         .mirror_rule_set              = i40e_mirror_rule_set,
 480         .mirror_rule_reset            = i40e_mirror_rule_reset,
 481         .timesync_enable              = i40e_timesync_enable,
 482         .timesync_disable             = i40e_timesync_disable,
 483         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 484         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 485         .get_dcb_info                 = i40e_dev_get_dcb_info,
 486         .timesync_adjust_time         = i40e_timesync_adjust_time,
 487         .timesync_read_time           = i40e_timesync_read_time,
 488         .timesync_write_time          = i40e_timesync_write_time,
 489         .get_reg                      = i40e_get_regs,
 490         .get_eeprom_length            = i40e_get_eeprom_length,
 491         .get_eeprom                   = i40e_get_eeprom,
 492         .mac_addr_set                 = i40e_set_default_mac_addr,
 493         .mtu_set                      = i40e_dev_mtu_set,
 494         .tm_ops_get                   = i40e_tm_ops_get,
 495 };
 496
 497 /* store statistics names and its offset in stats structure */
 498 struct rte_i40e_xstats_name_off {
 499         char name[RTE_ETH_XSTATS_NAME_SIZE];
 500         unsigned offset;
 501 };
 502
 503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 504         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 505         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 506         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 507         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 508         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 509                 rx_unknown_protocol)},
 510         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 511         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 512         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 513         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 514 };
 515
 516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 517                 sizeof(rte_i40e_stats_strings[0]))
 518
 519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 520         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 521                 tx_dropped_link_down)},
 522         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 523         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 524                 illegal_bytes)},
 525         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 526         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 527                 mac_local_faults)},
 528         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 529                 mac_remote_faults)},
 530         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 531                 rx_length_errors)},
 532         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 533         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 534         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 535         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 536         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 537         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_127)},
 539         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 540                 rx_size_255)},
 541         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 542                 rx_size_511)},
 543         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 544                 rx_size_1023)},
 545         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_1522)},
 547         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_big)},
 549         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_undersize)},
 551         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_oversize)},
 553         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 554                 mac_short_packet_dropped)},
 555         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_fragments)},
 557         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 558         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 559         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_127)},
 561         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 tx_size_255)},
 563         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 tx_size_511)},
 565         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 tx_size_1023)},
 567         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_1522)},
 569         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_big)},
 571         {"rx_flow_director_atr_match_packets",
 572                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 573         {"rx_flow_director_sb_match_packets",
 574                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 575         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 576                 tx_lpi_status)},
 577         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 578                 rx_lpi_status)},
 579         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 580                 tx_lpi_count)},
 581         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 582                 rx_lpi_count)},
 583 };
 584
 585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 586                 sizeof(rte_i40e_hw_port_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_rx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_rx)},
 593 };
 594
 595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 596                 sizeof(rte_i40e_rxq_prio_strings[0]))
 597
 598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 599         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xon_tx)},
 601         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 602                 priority_xoff_tx)},
 603         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 604                 priority_xon_2_xoff)},
 605 };
 606
 607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 608                 sizeof(rte_i40e_txq_prio_strings[0]))
 609
 610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 611         struct rte_pci_device *pci_dev)
 612 {
 613         return rte_eth_dev_pci_generic_probe(pci_dev,
 614                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 615 }
 616
 617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 618 {
 619         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 620 }
 621
 622 static struct rte_pci_driver rte_i40e_pmd = {
 623         .id_table = pci_id_i40e_map,
 624         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 625                      RTE_PCI_DRV_IOVA_AS_VA,
 626         .probe = eth_i40e_pci_probe,
 627         .remove = eth_i40e_pci_remove,
 628 };
 629
 630 static inline int
 631 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 632                                      struct rte_eth_link *link)
 633 {
 634         struct rte_eth_link *dst = link;
 635         struct rte_eth_link *src = &(dev->data->dev_link);
 636
 637         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 638                                         *(uint64_t *)src) == 0)
 639                 return -1;
 640
 641         return 0;
 642 }
 643
 644 static inline int
 645 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 646                                       struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = &(dev->data->dev_link);
 649         struct rte_eth_link *src = link;
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 659 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 660 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 661
 662 #ifndef I40E_GLQF_ORT
 663 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 664 #endif
 665 #ifndef I40E_GLQF_PIT
 666 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 667 #endif
 668 #ifndef I40E_GLQF_L3_MAP
 669 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 670 #endif
 671
 672 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 673 {
 674         /*
 675          * Initialize registers for parsing packet type of QinQ
 676          * This should be removed from code once proper
 677          * configuration API is added to avoid configuration conflicts
 678          * between ports of the same device.
 679          */
 680         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 681         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 682 }
 683
 684 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 685
 686 /*
 687  * Add a ethertype filter to drop all flow control frames transmitted
 688  * from VSIs.
 689 */
 690 static void
 691 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 692 {
 693         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 694         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 695                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 696                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 697         int ret;
 698
 699         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 700                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 701                                 pf->main_vsi_seid, 0,
 702                                 TRUE, NULL, NULL);
 703         if (ret)
 704                 PMD_INIT_LOG(ERR,
 705                         "Failed to add filter to drop flow control frames from VSIs.");
 706 }
 707
 708 static int
 709 floating_veb_list_handler(__rte_unused const char *key,
 710                           const char *floating_veb_value,
 711                           void *opaque)
 712 {
 713         int idx = 0;
 714         unsigned int count = 0;
 715         char *end = NULL;
 716         int min, max;
 717         bool *vf_floating_veb = opaque;
 718
 719         while (isblank(*floating_veb_value))
 720                 floating_veb_value++;
 721
 722         /* Reset floating VEB configuration for VFs */
 723         for (idx = 0; idx < I40E_MAX_VF; idx++)
 724                 vf_floating_veb[idx] = false;
 725
 726         min = I40E_MAX_VF;
 727         do {
 728                 while (isblank(*floating_veb_value))
 729                         floating_veb_value++;
 730                 if (*floating_veb_value == '\0')
 731                         return -1;
 732                 errno = 0;
 733                 idx = strtoul(floating_veb_value, &end, 10);
 734                 if (errno || end == NULL)
 735                         return -1;
 736                 while (isblank(*end))
 737                         end++;
 738                 if (*end == '-') {
 739                         min = idx;
 740                 } else if ((*end == ';') || (*end == '\0')) {
 741                         max = idx;
 742                         if (min == I40E_MAX_VF)
 743                                 min = idx;
 744                         if (max >= I40E_MAX_VF)
 745                                 max = I40E_MAX_VF - 1;
 746                         for (idx = min; idx <= max; idx++) {
 747                                 vf_floating_veb[idx] = true;
 748                                 count++;
 749                         }
 750                         min = I40E_MAX_VF;
 751                 } else {
 752                         return -1;
 753                 }
 754                 floating_veb_value = end + 1;
 755         } while (*end != '\0');
 756
 757         if (count == 0)
 758                 return -1;
 759
 760         return 0;
 761 }
 762
 763 static void
 764 config_vf_floating_veb(struct rte_devargs *devargs,
 765                        uint16_t floating_veb,
 766                        bool *vf_floating_veb)
 767 {
 768         struct rte_kvargs *kvlist;
 769         int i;
 770         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 771
 772         if (!floating_veb)
 773                 return;
 774         /* All the VFs attach to the floating VEB by default
 775          * when the floating VEB is enabled.
 776          */
 777         for (i = 0; i < I40E_MAX_VF; i++)
 778                 vf_floating_veb[i] = true;
 779
 780         if (devargs == NULL)
 781                 return;
 782
 783         kvlist = rte_kvargs_parse(devargs->args, NULL);
 784         if (kvlist == NULL)
 785                 return;
 786
 787         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 788                 rte_kvargs_free(kvlist);
 789                 return;
 790         }
 791         /* When the floating_veb_list parameter exists, all the VFs
 792          * will attach to the legacy VEB firstly, then configure VFs
 793          * to the floating VEB according to the floating_veb_list.
 794          */
 795         if (rte_kvargs_process(kvlist, floating_veb_list,
 796                                floating_veb_list_handler,
 797                                vf_floating_veb) < 0) {
 798                 rte_kvargs_free(kvlist);
 799                 return;
 800         }
 801         rte_kvargs_free(kvlist);
 802 }
 803
 804 static int
 805 i40e_check_floating_handler(__rte_unused const char *key,
 806                             const char *value,
 807                             __rte_unused void *opaque)
 808 {
 809         if (strcmp(value, "1"))
 810                 return -1;
 811
 812         return 0;
 813 }
 814
 815 static int
 816 is_floating_veb_supported(struct rte_devargs *devargs)
 817 {
 818         struct rte_kvargs *kvlist;
 819         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 820
 821         if (devargs == NULL)
 822                 return 0;
 823
 824         kvlist = rte_kvargs_parse(devargs->args, NULL);
 825         if (kvlist == NULL)
 826                 return 0;
 827
 828         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 829                 rte_kvargs_free(kvlist);
 830                 return 0;
 831         }
 832         /* Floating VEB is enabled when there's key-value:
 833          * enable_floating_veb=1
 834          */
 835         if (rte_kvargs_process(kvlist, floating_veb_key,
 836                                i40e_check_floating_handler, NULL) < 0) {
 837                 rte_kvargs_free(kvlist);
 838                 return 0;
 839         }
 840         rte_kvargs_free(kvlist);
 841
 842         return 1;
 843 }
 844
 845 static void
 846 config_floating_veb(struct rte_eth_dev *dev)
 847 {
 848         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 849         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 850         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 851
 852         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 853
 854         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 855                 pf->floating_veb =
 856                         is_floating_veb_supported(pci_dev->device.devargs);
 857                 config_vf_floating_veb(pci_dev->device.devargs,
 858                                        pf->floating_veb,
 859                                        pf->floating_veb_list);
 860         } else {
 861                 pf->floating_veb = false;
 862         }
 863 }
 864
 865 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 866 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 867
 868 static int
 869 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 870 {
 871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 872         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 873         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 874         int ret;
 875
 876         struct rte_hash_parameters ethertype_hash_params = {
 877                 .name = ethertype_hash_name,
 878                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 879                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 880                 .hash_func = rte_hash_crc,
 881                 .hash_func_init_val = 0,
 882                 .socket_id = rte_socket_id(),
 883         };
 884
 885         /* Initialize ethertype filter rule list and hash */
 886         TAILQ_INIT(&ethertype_rule->ethertype_list);
 887         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 888                  "ethertype_%s", dev->device->name);
 889         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 890         if (!ethertype_rule->hash_table) {
 891                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 892                 return -EINVAL;
 893         }
 894         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 895                                        sizeof(struct i40e_ethertype_filter *) *
 896                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 897                                        0);
 898         if (!ethertype_rule->hash_map) {
 899                 PMD_INIT_LOG(ERR,
 900                              "Failed to allocate memory for ethertype hash map!");
 901                 ret = -ENOMEM;
 902                 goto err_ethertype_hash_map_alloc;
 903         }
 904
 905         return 0;
 906
 907 err_ethertype_hash_map_alloc:
 908         rte_hash_free(ethertype_rule->hash_table);
 909
 910         return ret;
 911 }
 912
 913 static int
 914 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 915 {
 916         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 917         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 918         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 919         int ret;
 920
 921         struct rte_hash_parameters tunnel_hash_params = {
 922                 .name = tunnel_hash_name,
 923                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 924                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 925                 .hash_func = rte_hash_crc,
 926                 .hash_func_init_val = 0,
 927                 .socket_id = rte_socket_id(),
 928         };
 929
 930         /* Initialize tunnel filter rule list and hash */
 931         TAILQ_INIT(&tunnel_rule->tunnel_list);
 932         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 933                  "tunnel_%s", dev->device->name);
 934         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 935         if (!tunnel_rule->hash_table) {
 936                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 937                 return -EINVAL;
 938         }
 939         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 940                                     sizeof(struct i40e_tunnel_filter *) *
 941                                     I40E_MAX_TUNNEL_FILTER_NUM,
 942                                     0);
 943         if (!tunnel_rule->hash_map) {
 944                 PMD_INIT_LOG(ERR,
 945                              "Failed to allocate memory for tunnel hash map!");
 946                 ret = -ENOMEM;
 947                 goto err_tunnel_hash_map_alloc;
 948         }
 949
 950         return 0;
 951
 952 err_tunnel_hash_map_alloc:
 953         rte_hash_free(tunnel_rule->hash_table);
 954
 955         return ret;
 956 }
 957
 958 static int
 959 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 960 {
 961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 962         struct i40e_fdir_info *fdir_info = &pf->fdir;
 963         char fdir_hash_name[RTE_HASH_NAMESIZE];
 964         int ret;
 965
 966         struct rte_hash_parameters fdir_hash_params = {
 967                 .name = fdir_hash_name,
 968                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 969                 .key_len = sizeof(struct i40e_fdir_input),
 970                 .hash_func = rte_hash_crc,
 971                 .hash_func_init_val = 0,
 972                 .socket_id = rte_socket_id(),
 973         };
 974
 975         /* Initialize flow director filter rule list and hash */
 976         TAILQ_INIT(&fdir_info->fdir_list);
 977         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 978                  "fdir_%s", dev->device->name);
 979         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 980         if (!fdir_info->hash_table) {
 981                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 982                 return -EINVAL;
 983         }
 984         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 985                                           sizeof(struct i40e_fdir_filter *) *
 986                                           I40E_MAX_FDIR_FILTER_NUM,
 987                                           0);
 988         if (!fdir_info->hash_map) {
 989                 PMD_INIT_LOG(ERR,
 990                              "Failed to allocate memory for fdir hash map!");
 991                 ret = -ENOMEM;
 992                 goto err_fdir_hash_map_alloc;
 993         }
 994         return 0;
 995
 996 err_fdir_hash_map_alloc:
 997         rte_hash_free(fdir_info->hash_table);
 998
 999         return ret;
1000 }
1001
1002 static void
1003 i40e_init_customized_info(struct i40e_pf *pf)
1004 {
1005         int i;
1006
1007         /* Initialize customized pctype */
1008         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1009                 pf->customized_pctype[i].index = i;
1010                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1011                 pf->customized_pctype[i].valid = false;
1012         }
1013
1014         pf->gtp_support = false;
1015 }
1016
1017 void
1018 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1019 {
1020         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1022         struct i40e_queue_regions *info = &pf->queue_region;
1023         uint16_t i;
1024
1025         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1026                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1027
1028         memset(info, 0, sizeof(struct i40e_queue_regions));
1029 }
1030
1031 static int
1032 eth_i40e_dev_init(struct rte_eth_dev *dev)
1033 {
1034         struct rte_pci_device *pci_dev;
1035         struct rte_intr_handle *intr_handle;
1036         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1037         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038         struct i40e_vsi *vsi;
1039         int ret;
1040         uint32_t len;
1041         uint8_t aq_fail = 0;
1042
1043         PMD_INIT_FUNC_TRACE();
1044
1045         dev->dev_ops = &i40e_eth_dev_ops;
1046         dev->rx_pkt_burst = i40e_recv_pkts;
1047         dev->tx_pkt_burst = i40e_xmit_pkts;
1048         dev->tx_pkt_prepare = i40e_prep_pkts;
1049
1050         /* for secondary processes, we don't initialise any further as primary
1051          * has already done this work. Only check we don't need a different
1052          * RX function */
1053         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1054                 i40e_set_rx_function(dev);
1055                 i40e_set_tx_function(dev);
1056                 return 0;
1057         }
1058         i40e_set_default_ptype_table(dev);
1059         i40e_set_default_pctype_table(dev);
1060         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1061         intr_handle = &pci_dev->intr_handle;
1062
1063         rte_eth_copy_pci_info(dev, pci_dev);
1064
1065         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1066         pf->adapter->eth_dev = dev;
1067         pf->dev_data = dev->data;
1068
1069         hw->back = I40E_PF_TO_ADAPTER(pf);
1070         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1071         if (!hw->hw_addr) {
1072                 PMD_INIT_LOG(ERR,
1073                         "Hardware is not available, as address is NULL");
1074                 return -ENODEV;
1075         }
1076
1077         hw->vendor_id = pci_dev->id.vendor_id;
1078         hw->device_id = pci_dev->id.device_id;
1079         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1080         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1081         hw->bus.device = pci_dev->addr.devid;
1082         hw->bus.func = pci_dev->addr.function;
1083         hw->adapter_stopped = 0;
1084
1085         /* Make sure all is clean before doing PF reset */
1086         i40e_clear_hw(hw);
1087
1088         /* Initialize the hardware */
1089         i40e_hw_init(dev);
1090
1091         /* Reset here to make sure all is clean for each PF */
1092         ret = i40e_pf_reset(hw);
1093         if (ret) {
1094                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1095                 return ret;
1096         }
1097
1098         /* Initialize the shared code (base driver) */
1099         ret = i40e_init_shared_code(hw);
1100         if (ret) {
1101                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1102                 return ret;
1103         }
1104
1105         /*
1106          * To work around the NVM issue, initialize registers
1107          * for packet type of QinQ by software.
1108          * It should be removed once issues are fixed in NVM.
1109          */
1110         i40e_GLQF_reg_init(hw);
1111
1112         /* Initialize the input set for filters (hash and fd) to default value */
1113         i40e_filter_input_set_init(pf);
1114
1115         /* Initialize the parameters for adminq */
1116         i40e_init_adminq_parameter(hw);
1117         ret = i40e_init_adminq(hw);
1118         if (ret != I40E_SUCCESS) {
1119                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1120                 return -EIO;
1121         }
1122         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1123                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1124                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1125                      ((hw->nvm.version >> 12) & 0xf),
1126                      ((hw->nvm.version >> 4) & 0xff),
1127                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1128
1129         /* initialise the L3_MAP register */
1130         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1131                                    0x00000028,  NULL);
1132         if (ret)
1133                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1134
1135         /* Need the special FW version to support floating VEB */
1136         config_floating_veb(dev);
1137         /* Clear PXE mode */
1138         i40e_clear_pxe_mode(hw);
1139         i40e_dev_sync_phy_type(hw);
1140
1141         /*
1142          * On X710, performance number is far from the expectation on recent
1143          * firmware versions. The fix for this issue may not be integrated in
1144          * the following firmware version. So the workaround in software driver
1145          * is needed. It needs to modify the initial values of 3 internal only
1146          * registers. Note that the workaround can be removed when it is fixed
1147          * in firmware in the future.
1148          */
1149         i40e_configure_registers(hw);
1150
1151         /* Get hw capabilities */
1152         ret = i40e_get_cap(hw);
1153         if (ret != I40E_SUCCESS) {
1154                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1155                 goto err_get_capabilities;
1156         }
1157
1158         /* Initialize parameters for PF */
1159         ret = i40e_pf_parameter_init(dev);
1160         if (ret != 0) {
1161                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1162                 goto err_parameter_init;
1163         }
1164
1165         /* Initialize the queue management */
1166         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1167         if (ret < 0) {
1168                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1169                 goto err_qp_pool_init;
1170         }
1171         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1172                                 hw->func_caps.num_msix_vectors - 1);
1173         if (ret < 0) {
1174                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1175                 goto err_msix_pool_init;
1176         }
1177
1178         /* Initialize lan hmc */
1179         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1180                                 hw->func_caps.num_rx_qp, 0, 0);
1181         if (ret != I40E_SUCCESS) {
1182                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1183                 goto err_init_lan_hmc;
1184         }
1185
1186         /* Configure lan hmc */
1187         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1190                 goto err_configure_lan_hmc;
1191         }
1192
1193         /* Get and check the mac address */
1194         i40e_get_mac_addr(hw, hw->mac.addr);
1195         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "mac address is not valid");
1197                 ret = -EIO;
1198                 goto err_get_mac_addr;
1199         }
1200         /* Copy the permanent MAC address */
1201         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1202                         (struct ether_addr *) hw->mac.perm_addr);
1203
1204         /* Disable flow control */
1205         hw->fc.requested_mode = I40E_FC_NONE;
1206         i40e_set_fc(hw, &aq_fail, TRUE);
1207
1208         /* Set the global registers with default ether type value */
1209         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1210         if (ret != I40E_SUCCESS) {
1211                 PMD_INIT_LOG(ERR,
1212                         "Failed to set the default outer VLAN ether type");
1213                 goto err_setup_pf_switch;
1214         }
1215
1216         /* PF setup, which includes VSI setup */
1217         ret = i40e_pf_setup(pf);
1218         if (ret) {
1219                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* reset all stats of the device, including pf and main vsi */
1224         i40e_dev_stats_reset(dev);
1225
1226         vsi = pf->main_vsi;
1227
1228         /* Disable double vlan by default */
1229         i40e_vsi_config_double_vlan(vsi, FALSE);
1230
1231         /* Disable S-TAG identification when floating_veb is disabled */
1232         if (!pf->floating_veb) {
1233                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1234                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1235                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1236                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1237                 }
1238         }
1239
1240         if (!vsi->max_macaddrs)
1241                 len = ETHER_ADDR_LEN;
1242         else
1243                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1244
1245         /* Should be after VSI initialized */
1246         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1247         if (!dev->data->mac_addrs) {
1248                 PMD_INIT_LOG(ERR,
1249                         "Failed to allocated memory for storing mac address");
1250                 goto err_mac_alloc;
1251         }
1252         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1253                                         &dev->data->mac_addrs[0]);
1254
1255         /* Init dcb to sw mode by default */
1256         ret = i40e_dcb_init_configure(dev, TRUE);
1257         if (ret != I40E_SUCCESS) {
1258                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1259                 pf->flags &= ~I40E_FLAG_DCB;
1260         }
1261         /* Update HW struct after DCB configuration */
1262         i40e_get_cap(hw);
1263
1264         /* initialize pf host driver to setup SRIOV resource if applicable */
1265         i40e_pf_host_init(dev);
1266
1267         /* register callback func to eal lib */
1268         rte_intr_callback_register(intr_handle,
1269                                    i40e_dev_interrupt_handler, dev);
1270
1271         /* configure and enable device interrupt */
1272         i40e_pf_config_irq0(hw, TRUE);
1273         i40e_pf_enable_irq0(hw);
1274
1275         /* enable uio intr after callback register */
1276         rte_intr_enable(intr_handle);
1277
1278         /* By default disable flexible payload in global configuration */
1279         i40e_flex_payload_reg_set_default(hw);
1280
1281         /*
1282          * Add an ethertype filter to drop all flow control frames transmitted
1283          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1284          * frames to wire.
1285          */
1286         i40e_add_tx_flow_control_drop_filter(pf);
1287
1288         /* Set the max frame size to 0x2600 by default,
1289          * in case other drivers changed the default value.
1290          */
1291         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1292
1293         /* initialize mirror rule list */
1294         TAILQ_INIT(&pf->mirror_list);
1295
1296         /* initialize Traffic Manager configuration */
1297         i40e_tm_conf_init(dev);
1298
1299         /* Initialize customized information */
1300         i40e_init_customized_info(pf);
1301
1302         ret = i40e_init_ethtype_filter_list(dev);
1303         if (ret < 0)
1304                 goto err_init_ethtype_filter_list;
1305         ret = i40e_init_tunnel_filter_list(dev);
1306         if (ret < 0)
1307                 goto err_init_tunnel_filter_list;
1308         ret = i40e_init_fdir_filter_list(dev);
1309         if (ret < 0)
1310                 goto err_init_fdir_filter_list;
1311
1312         /* initialize queue region configuration */
1313         i40e_init_queue_region_conf(dev);
1314
1315         return 0;
1316
1317 err_init_fdir_filter_list:
1318         rte_free(pf->tunnel.hash_table);
1319         rte_free(pf->tunnel.hash_map);
1320 err_init_tunnel_filter_list:
1321         rte_free(pf->ethertype.hash_table);
1322         rte_free(pf->ethertype.hash_map);
1323 err_init_ethtype_filter_list:
1324         rte_free(dev->data->mac_addrs);
1325 err_mac_alloc:
1326         i40e_vsi_release(pf->main_vsi);
1327 err_setup_pf_switch:
1328 err_get_mac_addr:
1329 err_configure_lan_hmc:
1330         (void)i40e_shutdown_lan_hmc(hw);
1331 err_init_lan_hmc:
1332         i40e_res_pool_destroy(&pf->msix_pool);
1333 err_msix_pool_init:
1334         i40e_res_pool_destroy(&pf->qp_pool);
1335 err_qp_pool_init:
1336 err_parameter_init:
1337 err_get_capabilities:
1338         (void)i40e_shutdown_adminq(hw);
1339
1340         return ret;
1341 }
1342
1343 static void
1344 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1345 {
1346         struct i40e_ethertype_filter *p_ethertype;
1347         struct i40e_ethertype_rule *ethertype_rule;
1348
1349         ethertype_rule = &pf->ethertype;
1350         /* Remove all ethertype filter rules and hash */
1351         if (ethertype_rule->hash_map)
1352                 rte_free(ethertype_rule->hash_map);
1353         if (ethertype_rule->hash_table)
1354                 rte_hash_free(ethertype_rule->hash_table);
1355
1356         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1357                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1358                              p_ethertype, rules);
1359                 rte_free(p_ethertype);
1360         }
1361 }
1362
1363 static void
1364 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1365 {
1366         struct i40e_tunnel_filter *p_tunnel;
1367         struct i40e_tunnel_rule *tunnel_rule;
1368
1369         tunnel_rule = &pf->tunnel;
1370         /* Remove all tunnel director rules and hash */
1371         if (tunnel_rule->hash_map)
1372                 rte_free(tunnel_rule->hash_map);
1373         if (tunnel_rule->hash_table)
1374                 rte_hash_free(tunnel_rule->hash_table);
1375
1376         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1377                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1378                 rte_free(p_tunnel);
1379         }
1380 }
1381
1382 static void
1383 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1384 {
1385         struct i40e_fdir_filter *p_fdir;
1386         struct i40e_fdir_info *fdir_info;
1387
1388         fdir_info = &pf->fdir;
1389         /* Remove all flow director rules and hash */
1390         if (fdir_info->hash_map)
1391                 rte_free(fdir_info->hash_map);
1392         if (fdir_info->hash_table)
1393                 rte_hash_free(fdir_info->hash_table);
1394
1395         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1396                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1397                 rte_free(p_fdir);
1398         }
1399 }
1400
1401 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1402 {
1403         /*
1404          * Disable by default flexible payload
1405          * for corresponding L2/L3/L4 layers.
1406          */
1407         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1408         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1409         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1410 }
1411
1412 static int
1413 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1414 {
1415         struct i40e_pf *pf;
1416         struct rte_pci_device *pci_dev;
1417         struct rte_intr_handle *intr_handle;
1418         struct i40e_hw *hw;
1419         struct i40e_filter_control_settings settings;
1420         struct rte_flow *p_flow;
1421         int ret;
1422         uint8_t aq_fail = 0;
1423
1424         PMD_INIT_FUNC_TRACE();
1425
1426         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1427                 return 0;
1428
1429         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1430         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1432         intr_handle = &pci_dev->intr_handle;
1433
1434         if (hw->adapter_stopped == 0)
1435                 i40e_dev_close(dev);
1436
1437         dev->dev_ops = NULL;
1438         dev->rx_pkt_burst = NULL;
1439         dev->tx_pkt_burst = NULL;
1440
1441         /* Clear PXE mode */
1442         i40e_clear_pxe_mode(hw);
1443
1444         /* Unconfigure filter control */
1445         memset(&settings, 0, sizeof(settings));
1446         ret = i40e_set_filter_control(hw, &settings);
1447         if (ret)
1448                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1449                                         ret);
1450
1451         /* Disable flow control */
1452         hw->fc.requested_mode = I40E_FC_NONE;
1453         i40e_set_fc(hw, &aq_fail, TRUE);
1454
1455         /* uninitialize pf host driver */
1456         i40e_pf_host_uninit(dev);
1457
1458         rte_free(dev->data->mac_addrs);
1459         dev->data->mac_addrs = NULL;
1460
1461         /* disable uio intr before callback unregister */
1462         rte_intr_disable(intr_handle);
1463
1464         /* register callback func to eal lib */
1465         rte_intr_callback_unregister(intr_handle,
1466                                      i40e_dev_interrupt_handler, dev);
1467
1468         i40e_rm_ethtype_filter_list(pf);
1469         i40e_rm_tunnel_filter_list(pf);
1470         i40e_rm_fdir_filter_list(pf);
1471
1472         /* Remove all flows */
1473         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1474                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1475                 rte_free(p_flow);
1476         }
1477
1478         /* Remove all Traffic Manager configuration */
1479         i40e_tm_conf_uninit(dev);
1480
1481         return 0;
1482 }
1483
1484 static int
1485 i40e_dev_configure(struct rte_eth_dev *dev)
1486 {
1487         struct i40e_adapter *ad =
1488                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1489         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1490         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1491         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1492         int i, ret;
1493
1494         ret = i40e_dev_sync_phy_type(hw);
1495         if (ret)
1496                 return ret;
1497
1498         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1499          * bulk allocation or vector Rx preconditions we will reset it.
1500          */
1501         ad->rx_bulk_alloc_allowed = true;
1502         ad->rx_vec_allowed = true;
1503         ad->tx_simple_allowed = true;
1504         ad->tx_vec_allowed = true;
1505
1506         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1507                 ret = i40e_fdir_setup(pf);
1508                 if (ret != I40E_SUCCESS) {
1509                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1510                         return -ENOTSUP;
1511                 }
1512                 ret = i40e_fdir_configure(dev);
1513                 if (ret < 0) {
1514                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1515                         goto err;
1516                 }
1517         } else
1518                 i40e_fdir_teardown(pf);
1519
1520         ret = i40e_dev_init_vlan(dev);
1521         if (ret < 0)
1522                 goto err;
1523
1524         /* VMDQ setup.
1525          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1526          *  RSS setting have different requirements.
1527          *  General PMD driver call sequence are NIC init, configure,
1528          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1529          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1530          *  applicable. So, VMDQ setting has to be done before
1531          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1532          *  For RSS setting, it will try to calculate actual configured RX queue
1533          *  number, which will be available after rx_queue_setup(). dev_start()
1534          *  function is good to place RSS setup.
1535          */
1536         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1537                 ret = i40e_vmdq_setup(dev);
1538                 if (ret)
1539                         goto err;
1540         }
1541
1542         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1543                 ret = i40e_dcb_setup(dev);
1544                 if (ret) {
1545                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1546                         goto err_dcb;
1547                 }
1548         }
1549
1550         TAILQ_INIT(&pf->flow_list);
1551
1552         return 0;
1553
1554 err_dcb:
1555         /* need to release vmdq resource if exists */
1556         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1557                 i40e_vsi_release(pf->vmdq[i].vsi);
1558                 pf->vmdq[i].vsi = NULL;
1559         }
1560         rte_free(pf->vmdq);
1561         pf->vmdq = NULL;
1562 err:
1563         /* need to release fdir resource if exists */
1564         i40e_fdir_teardown(pf);
1565         return ret;
1566 }
1567
1568 void
1569 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1570 {
1571         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1572         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1573         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1574         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1575         uint16_t msix_vect = vsi->msix_intr;
1576         uint16_t i;
1577
1578         for (i = 0; i < vsi->nb_qps; i++) {
1579                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1580                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1581                 rte_wmb();
1582         }
1583
1584         if (vsi->type != I40E_VSI_SRIOV) {
1585                 if (!rte_intr_allow_others(intr_handle)) {
1586                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1587                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1588                         I40E_WRITE_REG(hw,
1589                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1590                                        0);
1591                 } else {
1592                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1593                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1594                         I40E_WRITE_REG(hw,
1595                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1596                                                        msix_vect - 1), 0);
1597                 }
1598         } else {
1599                 uint32_t reg;
1600                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1601                         vsi->user_param + (msix_vect - 1);
1602
1603                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1604                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1605         }
1606         I40E_WRITE_FLUSH(hw);
1607 }
1608
1609 static void
1610 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1611                        int base_queue, int nb_queue,
1612                        uint16_t itr_idx)
1613 {
1614         int i;
1615         uint32_t val;
1616         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1617
1618         /* Bind all RX queues to allocated MSIX interrupt */
1619         for (i = 0; i < nb_queue; i++) {
1620                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1621                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1622                         ((base_queue + i + 1) <<
1623                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1624                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1625                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1626
1627                 if (i == nb_queue - 1)
1628                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1629                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1630         }
1631
1632         /* Write first RX queue to Link list register as the head element */
1633         if (vsi->type != I40E_VSI_SRIOV) {
1634                 uint16_t interval =
1635                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1636
1637                 if (msix_vect == I40E_MISC_VEC_ID) {
1638                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1639                                        (base_queue <<
1640                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1641                                        (0x0 <<
1642                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1643                         I40E_WRITE_REG(hw,
1644                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1645                                        interval);
1646                 } else {
1647                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1648                                        (base_queue <<
1649                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1650                                        (0x0 <<
1651                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1652                         I40E_WRITE_REG(hw,
1653                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1654                                                        msix_vect - 1),
1655                                        interval);
1656                 }
1657         } else {
1658                 uint32_t reg;
1659
1660                 if (msix_vect == I40E_MISC_VEC_ID) {
1661                         I40E_WRITE_REG(hw,
1662                                        I40E_VPINT_LNKLST0(vsi->user_param),
1663                                        (base_queue <<
1664                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1665                                        (0x0 <<
1666                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1667                 } else {
1668                         /* num_msix_vectors_vf needs to minus irq0 */
1669                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1670                                 vsi->user_param + (msix_vect - 1);
1671
1672                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1673                                        (base_queue <<
1674                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1675                                        (0x0 <<
1676                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1677                 }
1678         }
1679
1680         I40E_WRITE_FLUSH(hw);
1681 }
1682
1683 void
1684 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1685 {
1686         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1687         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1688         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1689         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1690         uint16_t msix_vect = vsi->msix_intr;
1691         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1692         uint16_t queue_idx = 0;
1693         int record = 0;
1694         uint32_t val;
1695         int i;
1696
1697         for (i = 0; i < vsi->nb_qps; i++) {
1698                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1699                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1700         }
1701
1702         /* INTENA flag is not auto-cleared for interrupt */
1703         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1704         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1705                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1706                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1707         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1708
1709         /* VF bind interrupt */
1710         if (vsi->type == I40E_VSI_SRIOV) {
1711                 __vsi_queues_bind_intr(vsi, msix_vect,
1712                                        vsi->base_queue, vsi->nb_qps,
1713                                        itr_idx);
1714                 return;
1715         }
1716
1717         /* PF & VMDq bind interrupt */
1718         if (rte_intr_dp_is_en(intr_handle)) {
1719                 if (vsi->type == I40E_VSI_MAIN) {
1720                         queue_idx = 0;
1721                         record = 1;
1722                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1723                         struct i40e_vsi *main_vsi =
1724                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1725                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1726                         record = 1;
1727                 }
1728         }
1729
1730         for (i = 0; i < vsi->nb_used_qps; i++) {
1731                 if (nb_msix <= 1) {
1732                         if (!rte_intr_allow_others(intr_handle))
1733                                 /* allow to share MISC_VEC_ID */
1734                                 msix_vect = I40E_MISC_VEC_ID;
1735
1736                         /* no enough msix_vect, map all to one */
1737                         __vsi_queues_bind_intr(vsi, msix_vect,
1738                                                vsi->base_queue + i,
1739                                                vsi->nb_used_qps - i,
1740                                                itr_idx);
1741                         for (; !!record && i < vsi->nb_used_qps; i++)
1742                                 intr_handle->intr_vec[queue_idx + i] =
1743                                         msix_vect;
1744                         break;
1745                 }
1746                 /* 1:1 queue/msix_vect mapping */
1747                 __vsi_queues_bind_intr(vsi, msix_vect,
1748                                        vsi->base_queue + i, 1,
1749                                        itr_idx);
1750                 if (!!record)
1751                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1752
1753                 msix_vect++;
1754                 nb_msix--;
1755         }
1756 }
1757
1758 static void
1759 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1760 {
1761         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1762         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1763         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1764         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1765         uint16_t interval = i40e_calc_itr_interval(\
1766                 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1767         uint16_t msix_intr, i;
1768
1769         if (rte_intr_allow_others(intr_handle))
1770                 for (i = 0; i < vsi->nb_msix; i++) {
1771                         msix_intr = vsi->msix_intr + i;
1772                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1773                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1774                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1775                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1776                                 (interval <<
1777                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1778                 }
1779         else
1780                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1781                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1782                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1783                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1784                                (interval <<
1785                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1786
1787         I40E_WRITE_FLUSH(hw);
1788 }
1789
1790 static void
1791 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1792 {
1793         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1795         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1796         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1797         uint16_t msix_intr, i;
1798
1799         if (rte_intr_allow_others(intr_handle))
1800                 for (i = 0; i < vsi->nb_msix; i++) {
1801                         msix_intr = vsi->msix_intr + i;
1802                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1803                                        0);
1804                 }
1805         else
1806                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1807
1808         I40E_WRITE_FLUSH(hw);
1809 }
1810
1811 static inline uint8_t
1812 i40e_parse_link_speeds(uint16_t link_speeds)
1813 {
1814         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1815
1816         if (link_speeds & ETH_LINK_SPEED_40G)
1817                 link_speed |= I40E_LINK_SPEED_40GB;
1818         if (link_speeds & ETH_LINK_SPEED_25G)
1819                 link_speed |= I40E_LINK_SPEED_25GB;
1820         if (link_speeds & ETH_LINK_SPEED_20G)
1821                 link_speed |= I40E_LINK_SPEED_20GB;
1822         if (link_speeds & ETH_LINK_SPEED_10G)
1823                 link_speed |= I40E_LINK_SPEED_10GB;
1824         if (link_speeds & ETH_LINK_SPEED_1G)
1825                 link_speed |= I40E_LINK_SPEED_1GB;
1826         if (link_speeds & ETH_LINK_SPEED_100M)
1827                 link_speed |= I40E_LINK_SPEED_100MB;
1828
1829         return link_speed;
1830 }
1831
1832 static int
1833 i40e_phy_conf_link(struct i40e_hw *hw,
1834                    uint8_t abilities,
1835                    uint8_t force_speed,
1836                    bool is_up)
1837 {
1838         enum i40e_status_code status;
1839         struct i40e_aq_get_phy_abilities_resp phy_ab;
1840         struct i40e_aq_set_phy_config phy_conf;
1841         enum i40e_aq_phy_type cnt;
1842         uint32_t phy_type_mask = 0;
1843
1844         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1845                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1846                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1847                         I40E_AQ_PHY_FLAG_LOW_POWER;
1848         const uint8_t advt = I40E_LINK_SPEED_40GB |
1849                         I40E_LINK_SPEED_25GB |
1850                         I40E_LINK_SPEED_10GB |
1851                         I40E_LINK_SPEED_1GB |
1852                         I40E_LINK_SPEED_100MB;
1853         int ret = -ENOTSUP;
1854
1855
1856         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1857                                               NULL);
1858         if (status)
1859                 return ret;
1860
1861         /* If link already up, no need to set up again */
1862         if (is_up && phy_ab.phy_type != 0)
1863                 return I40E_SUCCESS;
1864
1865         memset(&phy_conf, 0, sizeof(phy_conf));
1866
1867         /* bits 0-2 use the values from get_phy_abilities_resp */
1868         abilities &= ~mask;
1869         abilities |= phy_ab.abilities & mask;
1870
1871         /* update ablities and speed */
1872         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1873                 phy_conf.link_speed = advt;
1874         else
1875                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1876
1877         phy_conf.abilities = abilities;
1878
1879
1880
1881         /* To enable link, phy_type mask needs to include each type */
1882         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1883                 phy_type_mask |= 1 << cnt;
1884
1885         /* use get_phy_abilities_resp value for the rest */
1886         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1887         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1888                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1889                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1890         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1891         phy_conf.eee_capability = phy_ab.eee_capability;
1892         phy_conf.eeer = phy_ab.eeer_val;
1893         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1894
1895         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1896                     phy_ab.abilities, phy_ab.link_speed);
1897         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1898                     phy_conf.abilities, phy_conf.link_speed);
1899
1900         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1901         if (status)
1902                 return ret;
1903
1904         return I40E_SUCCESS;
1905 }
1906
1907 static int
1908 i40e_apply_link_speed(struct rte_eth_dev *dev)
1909 {
1910         uint8_t speed;
1911         uint8_t abilities = 0;
1912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913         struct rte_eth_conf *conf = &dev->data->dev_conf;
1914
1915         speed = i40e_parse_link_speeds(conf->link_speeds);
1916         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1917         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1918                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1919         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1920
1921         return i40e_phy_conf_link(hw, abilities, speed, true);
1922 }
1923
1924 static int
1925 i40e_dev_start(struct rte_eth_dev *dev)
1926 {
1927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         struct i40e_vsi *main_vsi = pf->main_vsi;
1930         int ret, i;
1931         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1932         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1933         uint32_t intr_vector = 0;
1934         struct i40e_vsi *vsi;
1935
1936         hw->adapter_stopped = 0;
1937
1938         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1939                 PMD_INIT_LOG(ERR,
1940                 "Invalid link_speeds for port %u, autonegotiation disabled",
1941                               dev->data->port_id);
1942                 return -EINVAL;
1943         }
1944
1945         rte_intr_disable(intr_handle);
1946
1947         if ((rte_intr_cap_multiple(intr_handle) ||
1948              !RTE_ETH_DEV_SRIOV(dev).active) &&
1949             dev->data->dev_conf.intr_conf.rxq != 0) {
1950                 intr_vector = dev->data->nb_rx_queues;
1951                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1952                 if (ret)
1953                         return ret;
1954         }
1955
1956         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1957                 intr_handle->intr_vec =
1958                         rte_zmalloc("intr_vec",
1959                                     dev->data->nb_rx_queues * sizeof(int),
1960                                     0);
1961                 if (!intr_handle->intr_vec) {
1962                         PMD_INIT_LOG(ERR,
1963                                 "Failed to allocate %d rx_queues intr_vec",
1964                                 dev->data->nb_rx_queues);
1965                         return -ENOMEM;
1966                 }
1967         }
1968
1969         /* Initialize VSI */
1970         ret = i40e_dev_rxtx_init(pf);
1971         if (ret != I40E_SUCCESS) {
1972                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1973                 goto err_up;
1974         }
1975
1976         /* Map queues with MSIX interrupt */
1977         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1978                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1979         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1980         i40e_vsi_enable_queues_intr(main_vsi);
1981
1982         /* Map VMDQ VSI queues with MSIX interrupt */
1983         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1984                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1985                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1986                                           I40E_ITR_INDEX_DEFAULT);
1987                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1988         }
1989
1990         /* enable FDIR MSIX interrupt */
1991         if (pf->fdir.fdir_vsi) {
1992                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1993                                           I40E_ITR_INDEX_NONE);
1994                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1995         }
1996
1997         /* Enable all queues which have been configured */
1998         ret = i40e_dev_switch_queues(pf, TRUE);
1999         if (ret != I40E_SUCCESS) {
2000                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2001                 goto err_up;
2002         }
2003
2004         /* Enable receiving broadcast packets */
2005         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2006         if (ret != I40E_SUCCESS)
2007                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2008
2009         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2010                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2011                                                 true, NULL);
2012                 if (ret != I40E_SUCCESS)
2013                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2014         }
2015
2016         /* Enable the VLAN promiscuous mode. */
2017         if (pf->vfs) {
2018                 for (i = 0; i < pf->vf_num; i++) {
2019                         vsi = pf->vfs[i].vsi;
2020                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2021                                                      true, NULL);
2022                 }
2023         }
2024
2025         /* Enable mac loopback mode */
2026         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2027             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2028                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2029                 if (ret != I40E_SUCCESS) {
2030                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2031                         goto err_up;
2032                 }
2033         }
2034
2035         /* Apply link configure */
2036         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2037                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2038                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2039                                 ETH_LINK_SPEED_40G)) {
2040                 PMD_DRV_LOG(ERR, "Invalid link setting");
2041                 goto err_up;
2042         }
2043         ret = i40e_apply_link_speed(dev);
2044         if (I40E_SUCCESS != ret) {
2045                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2046                 goto err_up;
2047         }
2048
2049         if (!rte_intr_allow_others(intr_handle)) {
2050                 rte_intr_callback_unregister(intr_handle,
2051                                              i40e_dev_interrupt_handler,
2052                                              (void *)dev);
2053                 /* configure and enable device interrupt */
2054                 i40e_pf_config_irq0(hw, FALSE);
2055                 i40e_pf_enable_irq0(hw);
2056
2057                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2058                         PMD_INIT_LOG(INFO,
2059                                 "lsc won't enable because of no intr multiplex");
2060         } else {
2061                 ret = i40e_aq_set_phy_int_mask(hw,
2062                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2063                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2064                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2065                 if (ret != I40E_SUCCESS)
2066                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2067
2068                 /* Call get_link_info aq commond to enable/disable LSE */
2069                 i40e_dev_link_update(dev, 0);
2070         }
2071
2072         /* enable uio intr after callback register */
2073         rte_intr_enable(intr_handle);
2074
2075         i40e_filter_restore(pf);
2076
2077         if (pf->tm_conf.root && !pf->tm_conf.committed)
2078                 PMD_DRV_LOG(WARNING,
2079                             "please call hierarchy_commit() "
2080                             "before starting the port");
2081
2082         return I40E_SUCCESS;
2083
2084 err_up:
2085         i40e_dev_switch_queues(pf, FALSE);
2086         i40e_dev_clear_queues(dev);
2087
2088         return ret;
2089 }
2090
2091 static void
2092 i40e_dev_stop(struct rte_eth_dev *dev)
2093 {
2094         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2095         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096         struct i40e_vsi *main_vsi = pf->main_vsi;
2097         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2098         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2099         int i;
2100
2101         if (hw->adapter_stopped == 1)
2102                 return;
2103         /* Disable all queues */
2104         i40e_dev_switch_queues(pf, FALSE);
2105
2106         /* un-map queues with interrupt registers */
2107         i40e_vsi_disable_queues_intr(main_vsi);
2108         i40e_vsi_queues_unbind_intr(main_vsi);
2109
2110         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2111                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2112                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2113         }
2114
2115         if (pf->fdir.fdir_vsi) {
2116                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2117                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2118         }
2119         /* Clear all queues and release memory */
2120         i40e_dev_clear_queues(dev);
2121
2122         /* Set link down */
2123         i40e_dev_set_link_down(dev);
2124
2125         if (!rte_intr_allow_others(intr_handle))
2126                 /* resume to the default handler */
2127                 rte_intr_callback_register(intr_handle,
2128                                            i40e_dev_interrupt_handler,
2129                                            (void *)dev);
2130
2131         /* Clean datapath event and queue/vec mapping */
2132         rte_intr_efd_disable(intr_handle);
2133         if (intr_handle->intr_vec) {
2134                 rte_free(intr_handle->intr_vec);
2135                 intr_handle->intr_vec = NULL;
2136         }
2137
2138         /* reset hierarchy commit */
2139         pf->tm_conf.committed = false;
2140
2141         /* Remove all the queue region configuration */
2142         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2143
2144         hw->adapter_stopped = 1;
2145 }
2146
2147 static void
2148 i40e_dev_close(struct rte_eth_dev *dev)
2149 {
2150         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2152         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2153         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2154         struct i40e_mirror_rule *p_mirror;
2155         uint32_t reg;
2156         int i;
2157         int ret;
2158
2159         PMD_INIT_FUNC_TRACE();
2160
2161         i40e_dev_stop(dev);
2162
2163         /* Remove all mirror rules */
2164         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2165                 ret = i40e_aq_del_mirror_rule(hw,
2166                                               pf->main_vsi->veb->seid,
2167                                               p_mirror->rule_type,
2168                                               p_mirror->entries,
2169                                               p_mirror->num_entries,
2170                                               p_mirror->id);
2171                 if (ret < 0)
2172                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2173                                     "status = %d, aq_err = %d.", ret,
2174                                     hw->aq.asq_last_status);
2175
2176                 /* remove mirror software resource anyway */
2177                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2178                 rte_free(p_mirror);
2179                 pf->nb_mirror_rule--;
2180         }
2181
2182         i40e_dev_free_queues(dev);
2183
2184         /* Disable interrupt */
2185         i40e_pf_disable_irq0(hw);
2186         rte_intr_disable(intr_handle);
2187
2188         /* shutdown and destroy the HMC */
2189         i40e_shutdown_lan_hmc(hw);
2190
2191         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2192                 i40e_vsi_release(pf->vmdq[i].vsi);
2193                 pf->vmdq[i].vsi = NULL;
2194         }
2195         rte_free(pf->vmdq);
2196         pf->vmdq = NULL;
2197
2198         /* release all the existing VSIs and VEBs */
2199         i40e_fdir_teardown(pf);
2200         i40e_vsi_release(pf->main_vsi);
2201
2202         /* shutdown the adminq */
2203         i40e_aq_queue_shutdown(hw, true);
2204         i40e_shutdown_adminq(hw);
2205
2206         i40e_res_pool_destroy(&pf->qp_pool);
2207         i40e_res_pool_destroy(&pf->msix_pool);
2208
2209         /* Disable flexible payload in global configuration */
2210         i40e_flex_payload_reg_set_default(hw);
2211
2212         /* force a PF reset to clean anything leftover */
2213         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2214         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2215                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2216         I40E_WRITE_FLUSH(hw);
2217 }
2218
2219 /*
2220  * Reset PF device only to re-initialize resources in PMD layer
2221  */
2222 static int
2223 i40e_dev_reset(struct rte_eth_dev *dev)
2224 {
2225         int ret;
2226
2227         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2228          * its VF to make them align with it. The detailed notification
2229          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2230          * To avoid unexpected behavior in VF, currently reset of PF with
2231          * SR-IOV activation is not supported. It might be supported later.
2232          */
2233         if (dev->data->sriov.active)
2234                 return -ENOTSUP;
2235
2236         ret = eth_i40e_dev_uninit(dev);
2237         if (ret)
2238                 return ret;
2239
2240         ret = eth_i40e_dev_init(dev);
2241
2242         return ret;
2243 }
2244
2245 static void
2246 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2247 {
2248         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2249         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250         struct i40e_vsi *vsi = pf->main_vsi;
2251         int status;
2252
2253         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2254                                                      true, NULL, true);
2255         if (status != I40E_SUCCESS)
2256                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2257
2258         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2259                                                         TRUE, NULL);
2260         if (status != I40E_SUCCESS)
2261                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2262
2263 }
2264
2265 static void
2266 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2267 {
2268         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2269         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2270         struct i40e_vsi *vsi = pf->main_vsi;
2271         int status;
2272
2273         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2274                                                      false, NULL, true);
2275         if (status != I40E_SUCCESS)
2276                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2277
2278         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2279                                                         false, NULL);
2280         if (status != I40E_SUCCESS)
2281                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2282 }
2283
2284 static void
2285 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2286 {
2287         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2288         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289         struct i40e_vsi *vsi = pf->main_vsi;
2290         int ret;
2291
2292         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2293         if (ret != I40E_SUCCESS)
2294                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2295 }
2296
2297 static void
2298 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2299 {
2300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2301         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302         struct i40e_vsi *vsi = pf->main_vsi;
2303         int ret;
2304
2305         if (dev->data->promiscuous == 1)
2306                 return; /* must remain in all_multicast mode */
2307
2308         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2309                                 vsi->seid, FALSE, NULL);
2310         if (ret != I40E_SUCCESS)
2311                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2312 }
2313
2314 /*
2315  * Set device link up.
2316  */
2317 static int
2318 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2319 {
2320         /* re-apply link speed setting */
2321         return i40e_apply_link_speed(dev);
2322 }
2323
2324 /*
2325  * Set device link down.
2326  */
2327 static int
2328 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2329 {
2330         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2331         uint8_t abilities = 0;
2332         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333
2334         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2335         return i40e_phy_conf_link(hw, abilities, speed, false);
2336 }
2337
2338 int
2339 i40e_dev_link_update(struct rte_eth_dev *dev,
2340                      int wait_to_complete)
2341 {
2342 #define CHECK_INTERVAL 100  /* 100ms */
2343 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2344         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345         struct i40e_link_status link_status;
2346         struct rte_eth_link link, old;
2347         int status;
2348         unsigned rep_cnt = MAX_REPEAT_TIME;
2349         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2350
2351         memset(&link, 0, sizeof(link));
2352         memset(&old, 0, sizeof(old));
2353         memset(&link_status, 0, sizeof(link_status));
2354         rte_i40e_dev_atomic_read_link_status(dev, &old);
2355
2356         do {
2357                 /* Get link status information from hardware */
2358                 status = i40e_aq_get_link_info(hw, enable_lse,
2359                                                 &link_status, NULL);
2360                 if (status != I40E_SUCCESS) {
2361                         link.link_speed = ETH_SPEED_NUM_100M;
2362                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2363                         PMD_DRV_LOG(ERR, "Failed to get link info");
2364                         goto out;
2365                 }
2366
2367                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2368                 if (!wait_to_complete || link.link_status)
2369                         break;
2370
2371                 rte_delay_ms(CHECK_INTERVAL);
2372         } while (--rep_cnt);
2373
2374         if (!link.link_status)
2375                 goto out;
2376
2377         /* i40e uses full duplex only */
2378         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2379
2380         /* Parse the link status */
2381         switch (link_status.link_speed) {
2382         case I40E_LINK_SPEED_100MB:
2383                 link.link_speed = ETH_SPEED_NUM_100M;
2384                 break;
2385         case I40E_LINK_SPEED_1GB:
2386                 link.link_speed = ETH_SPEED_NUM_1G;
2387                 break;
2388         case I40E_LINK_SPEED_10GB:
2389                 link.link_speed = ETH_SPEED_NUM_10G;
2390                 break;
2391         case I40E_LINK_SPEED_20GB:
2392                 link.link_speed = ETH_SPEED_NUM_20G;
2393                 break;
2394         case I40E_LINK_SPEED_25GB:
2395                 link.link_speed = ETH_SPEED_NUM_25G;
2396                 break;
2397         case I40E_LINK_SPEED_40GB:
2398                 link.link_speed = ETH_SPEED_NUM_40G;
2399                 break;
2400         default:
2401                 link.link_speed = ETH_SPEED_NUM_100M;
2402                 break;
2403         }
2404
2405         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2406                         ETH_LINK_SPEED_FIXED);
2407
2408 out:
2409         rte_i40e_dev_atomic_write_link_status(dev, &link);
2410         if (link.link_status == old.link_status)
2411                 return -1;
2412
2413         i40e_notify_all_vfs_link_status(dev);
2414
2415         return 0;
2416 }
2417
2418 /* Get all the statistics of a VSI */
2419 void
2420 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2421 {
2422         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2423         struct i40e_eth_stats *nes = &vsi->eth_stats;
2424         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2425         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2426
2427         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2428                             vsi->offset_loaded, &oes->rx_bytes,
2429                             &nes->rx_bytes);
2430         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2431                             vsi->offset_loaded, &oes->rx_unicast,
2432                             &nes->rx_unicast);
2433         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2434                             vsi->offset_loaded, &oes->rx_multicast,
2435                             &nes->rx_multicast);
2436         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2437                             vsi->offset_loaded, &oes->rx_broadcast,
2438                             &nes->rx_broadcast);
2439         /* exclude CRC bytes */
2440         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2441                 nes->rx_broadcast) * ETHER_CRC_LEN;
2442
2443         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2444                             &oes->rx_discards, &nes->rx_discards);
2445         /* GLV_REPC not supported */
2446         /* GLV_RMPC not supported */
2447         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2448                             &oes->rx_unknown_protocol,
2449                             &nes->rx_unknown_protocol);
2450         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2451                             vsi->offset_loaded, &oes->tx_bytes,
2452                             &nes->tx_bytes);
2453         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2454                             vsi->offset_loaded, &oes->tx_unicast,
2455                             &nes->tx_unicast);
2456         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2457                             vsi->offset_loaded, &oes->tx_multicast,
2458                             &nes->tx_multicast);
2459         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2460                             vsi->offset_loaded,  &oes->tx_broadcast,
2461                             &nes->tx_broadcast);
2462         /* GLV_TDPC not supported */
2463         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2464                             &oes->tx_errors, &nes->tx_errors);
2465         vsi->offset_loaded = true;
2466
2467         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2468                     vsi->vsi_id);
2469         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2470         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2471         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2472         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2473         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2474         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2475                     nes->rx_unknown_protocol);
2476         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2477         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2478         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2479         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2480         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2481         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2482         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2483                     vsi->vsi_id);
2484 }
2485
2486 static void
2487 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2488 {
2489         unsigned int i;
2490         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2491         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2492
2493         /* Get rx/tx bytes of internal transfer packets */
2494         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2495                         I40E_GLV_GORCL(hw->port),
2496                         pf->offset_loaded,
2497                         &pf->internal_stats_offset.rx_bytes,
2498                         &pf->internal_stats.rx_bytes);
2499
2500         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2501                         I40E_GLV_GOTCL(hw->port),
2502                         pf->offset_loaded,
2503                         &pf->internal_stats_offset.tx_bytes,
2504                         &pf->internal_stats.tx_bytes);
2505         /* Get total internal rx packet count */
2506         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2507                             I40E_GLV_UPRCL(hw->port),
2508                             pf->offset_loaded,
2509                             &pf->internal_stats_offset.rx_unicast,
2510                             &pf->internal_stats.rx_unicast);
2511         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2512                             I40E_GLV_MPRCL(hw->port),
2513                             pf->offset_loaded,
2514                             &pf->internal_stats_offset.rx_multicast,
2515                             &pf->internal_stats.rx_multicast);
2516         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2517                             I40E_GLV_BPRCL(hw->port),
2518                             pf->offset_loaded,
2519                             &pf->internal_stats_offset.rx_broadcast,
2520                             &pf->internal_stats.rx_broadcast);
2521         /* Get total internal tx packet count */
2522         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2523                             I40E_GLV_UPTCL(hw->port),
2524                             pf->offset_loaded,
2525                             &pf->internal_stats_offset.tx_unicast,
2526                             &pf->internal_stats.tx_unicast);
2527         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2528                             I40E_GLV_MPTCL(hw->port),
2529                             pf->offset_loaded,
2530                             &pf->internal_stats_offset.tx_multicast,
2531                             &pf->internal_stats.tx_multicast);
2532         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2533                             I40E_GLV_BPTCL(hw->port),
2534                             pf->offset_loaded,
2535                             &pf->internal_stats_offset.tx_broadcast,
2536                             &pf->internal_stats.tx_broadcast);
2537
2538         /* exclude CRC size */
2539         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2540                 pf->internal_stats.rx_multicast +
2541                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2542
2543         /* Get statistics of struct i40e_eth_stats */
2544         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2545                             I40E_GLPRT_GORCL(hw->port),
2546                             pf->offset_loaded, &os->eth.rx_bytes,
2547                             &ns->eth.rx_bytes);
2548         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2549                             I40E_GLPRT_UPRCL(hw->port),
2550                             pf->offset_loaded, &os->eth.rx_unicast,
2551                             &ns->eth.rx_unicast);
2552         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2553                             I40E_GLPRT_MPRCL(hw->port),
2554                             pf->offset_loaded, &os->eth.rx_multicast,
2555                             &ns->eth.rx_multicast);
2556         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2557                             I40E_GLPRT_BPRCL(hw->port),
2558                             pf->offset_loaded, &os->eth.rx_broadcast,
2559                             &ns->eth.rx_broadcast);
2560         /* Workaround: CRC size should not be included in byte statistics,
2561          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2562          */
2563         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2564                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2565
2566         /* exclude internal rx bytes
2567          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2568          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2569          * value.
2570          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2571          */
2572         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2573                 ns->eth.rx_bytes = 0;
2574         else
2575                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2576
2577         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2578                 ns->eth.rx_unicast = 0;
2579         else
2580                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2581
2582         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2583                 ns->eth.rx_multicast = 0;
2584         else
2585                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2586
2587         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2588                 ns->eth.rx_broadcast = 0;
2589         else
2590                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2591
2592         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2593                             pf->offset_loaded, &os->eth.rx_discards,
2594                             &ns->eth.rx_discards);
2595         /* GLPRT_REPC not supported */
2596         /* GLPRT_RMPC not supported */
2597         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2598                             pf->offset_loaded,
2599                             &os->eth.rx_unknown_protocol,
2600                             &ns->eth.rx_unknown_protocol);
2601         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2602                             I40E_GLPRT_GOTCL(hw->port),
2603                             pf->offset_loaded, &os->eth.tx_bytes,
2604                             &ns->eth.tx_bytes);
2605         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2606                             I40E_GLPRT_UPTCL(hw->port),
2607                             pf->offset_loaded, &os->eth.tx_unicast,
2608                             &ns->eth.tx_unicast);
2609         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2610                             I40E_GLPRT_MPTCL(hw->port),
2611                             pf->offset_loaded, &os->eth.tx_multicast,
2612                             &ns->eth.tx_multicast);
2613         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2614                             I40E_GLPRT_BPTCL(hw->port),
2615                             pf->offset_loaded, &os->eth.tx_broadcast,
2616                             &ns->eth.tx_broadcast);
2617         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2618                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2619
2620         /* exclude internal tx bytes
2621          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2622          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2623          * value.
2624          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2625          */
2626         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2627                 ns->eth.tx_bytes = 0;
2628         else
2629                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2630
2631         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2632                 ns->eth.tx_unicast = 0;
2633         else
2634                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2635
2636         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2637                 ns->eth.tx_multicast = 0;
2638         else
2639                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2640
2641         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2642                 ns->eth.tx_broadcast = 0;
2643         else
2644                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2645
2646         /* GLPRT_TEPC not supported */
2647
2648         /* additional port specific stats */
2649         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2650                             pf->offset_loaded, &os->tx_dropped_link_down,
2651                             &ns->tx_dropped_link_down);
2652         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2653                             pf->offset_loaded, &os->crc_errors,
2654                             &ns->crc_errors);
2655         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2656                             pf->offset_loaded, &os->illegal_bytes,
2657                             &ns->illegal_bytes);
2658         /* GLPRT_ERRBC not supported */
2659         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2660                             pf->offset_loaded, &os->mac_local_faults,
2661                             &ns->mac_local_faults);
2662         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2663                             pf->offset_loaded, &os->mac_remote_faults,
2664                             &ns->mac_remote_faults);
2665         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2666                             pf->offset_loaded, &os->rx_length_errors,
2667                             &ns->rx_length_errors);
2668         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2669                             pf->offset_loaded, &os->link_xon_rx,
2670                             &ns->link_xon_rx);
2671         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2672                             pf->offset_loaded, &os->link_xoff_rx,
2673                             &ns->link_xoff_rx);
2674         for (i = 0; i < 8; i++) {
2675                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2676                                     pf->offset_loaded,
2677                                     &os->priority_xon_rx[i],
2678                                     &ns->priority_xon_rx[i]);
2679                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2680                                     pf->offset_loaded,
2681                                     &os->priority_xoff_rx[i],
2682                                     &ns->priority_xoff_rx[i]);
2683         }
2684         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2685                             pf->offset_loaded, &os->link_xon_tx,
2686                             &ns->link_xon_tx);
2687         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2688                             pf->offset_loaded, &os->link_xoff_tx,
2689                             &ns->link_xoff_tx);
2690         for (i = 0; i < 8; i++) {
2691                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2692                                     pf->offset_loaded,
2693                                     &os->priority_xon_tx[i],
2694                                     &ns->priority_xon_tx[i]);
2695                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2696                                     pf->offset_loaded,
2697                                     &os->priority_xoff_tx[i],
2698                                     &ns->priority_xoff_tx[i]);
2699                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2700                                     pf->offset_loaded,
2701                                     &os->priority_xon_2_xoff[i],
2702                                     &ns->priority_xon_2_xoff[i]);
2703         }
2704         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2705                             I40E_GLPRT_PRC64L(hw->port),
2706                             pf->offset_loaded, &os->rx_size_64,
2707                             &ns->rx_size_64);
2708         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2709                             I40E_GLPRT_PRC127L(hw->port),
2710                             pf->offset_loaded, &os->rx_size_127,
2711                             &ns->rx_size_127);
2712         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2713                             I40E_GLPRT_PRC255L(hw->port),
2714                             pf->offset_loaded, &os->rx_size_255,
2715                             &ns->rx_size_255);
2716         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2717                             I40E_GLPRT_PRC511L(hw->port),
2718                             pf->offset_loaded, &os->rx_size_511,
2719                             &ns->rx_size_511);
2720         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2721                             I40E_GLPRT_PRC1023L(hw->port),
2722                             pf->offset_loaded, &os->rx_size_1023,
2723                             &ns->rx_size_1023);
2724         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2725                             I40E_GLPRT_PRC1522L(hw->port),
2726                             pf->offset_loaded, &os->rx_size_1522,
2727                             &ns->rx_size_1522);
2728         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2729                             I40E_GLPRT_PRC9522L(hw->port),
2730                             pf->offset_loaded, &os->rx_size_big,
2731                             &ns->rx_size_big);
2732         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2733                             pf->offset_loaded, &os->rx_undersize,
2734                             &ns->rx_undersize);
2735         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2736                             pf->offset_loaded, &os->rx_fragments,
2737                             &ns->rx_fragments);
2738         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2739                             pf->offset_loaded, &os->rx_oversize,
2740                             &ns->rx_oversize);
2741         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2742                             pf->offset_loaded, &os->rx_jabber,
2743                             &ns->rx_jabber);
2744         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2745                             I40E_GLPRT_PTC64L(hw->port),
2746                             pf->offset_loaded, &os->tx_size_64,
2747                             &ns->tx_size_64);
2748         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2749                             I40E_GLPRT_PTC127L(hw->port),
2750                             pf->offset_loaded, &os->tx_size_127,
2751                             &ns->tx_size_127);
2752         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2753                             I40E_GLPRT_PTC255L(hw->port),
2754                             pf->offset_loaded, &os->tx_size_255,
2755                             &ns->tx_size_255);
2756         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2757                             I40E_GLPRT_PTC511L(hw->port),
2758                             pf->offset_loaded, &os->tx_size_511,
2759                             &ns->tx_size_511);
2760         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2761                             I40E_GLPRT_PTC1023L(hw->port),
2762                             pf->offset_loaded, &os->tx_size_1023,
2763                             &ns->tx_size_1023);
2764         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2765                             I40E_GLPRT_PTC1522L(hw->port),
2766                             pf->offset_loaded, &os->tx_size_1522,
2767                             &ns->tx_size_1522);
2768         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2769                             I40E_GLPRT_PTC9522L(hw->port),
2770                             pf->offset_loaded, &os->tx_size_big,
2771                             &ns->tx_size_big);
2772         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2773                            pf->offset_loaded,
2774                            &os->fd_sb_match, &ns->fd_sb_match);
2775         /* GLPRT_MSPDC not supported */
2776         /* GLPRT_XEC not supported */
2777
2778         pf->offset_loaded = true;
2779
2780         if (pf->main_vsi)
2781                 i40e_update_vsi_stats(pf->main_vsi);
2782 }
2783
2784 /* Get all statistics of a port */
2785 static int
2786 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2787 {
2788         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2791         unsigned i;
2792
2793         /* call read registers - updates values, now write them to struct */
2794         i40e_read_stats_registers(pf, hw);
2795
2796         stats->ipackets = ns->eth.rx_unicast +
2797                         ns->eth.rx_multicast +
2798                         ns->eth.rx_broadcast -
2799                         ns->eth.rx_discards -
2800                         pf->main_vsi->eth_stats.rx_discards;
2801         stats->opackets = ns->eth.tx_unicast +
2802                         ns->eth.tx_multicast +
2803                         ns->eth.tx_broadcast;
2804         stats->ibytes   = ns->eth.rx_bytes;
2805         stats->obytes   = ns->eth.tx_bytes;
2806         stats->oerrors  = ns->eth.tx_errors +
2807                         pf->main_vsi->eth_stats.tx_errors;
2808
2809         /* Rx Errors */
2810         stats->imissed  = ns->eth.rx_discards +
2811                         pf->main_vsi->eth_stats.rx_discards;
2812         stats->ierrors  = ns->crc_errors +
2813                         ns->rx_length_errors + ns->rx_undersize +
2814                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2815
2816         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2817         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2818         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2819         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2820         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2821         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2822         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2823                     ns->eth.rx_unknown_protocol);
2824         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2825         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2826         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2827         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2828         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2829         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2830
2831         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2832                     ns->tx_dropped_link_down);
2833         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2834         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2835                     ns->illegal_bytes);
2836         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2837         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2838                     ns->mac_local_faults);
2839         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2840                     ns->mac_remote_faults);
2841         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2842                     ns->rx_length_errors);
2843         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2844         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2845         for (i = 0; i < 8; i++) {
2846                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2847                                 i, ns->priority_xon_rx[i]);
2848                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2849                                 i, ns->priority_xoff_rx[i]);
2850         }
2851         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2852         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2853         for (i = 0; i < 8; i++) {
2854                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2855                                 i, ns->priority_xon_tx[i]);
2856                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2857                                 i, ns->priority_xoff_tx[i]);
2858                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2859                                 i, ns->priority_xon_2_xoff[i]);
2860         }
2861         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2862         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2863         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2864         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2865         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2866         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2867         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2868         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2869         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2870         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2871         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2872         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2873         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2874         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2875         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2876         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2877         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2878         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2879         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2880                         ns->mac_short_packet_dropped);
2881         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2882                     ns->checksum_error);
2883         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2884         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2885         return 0;
2886 }
2887
2888 /* Reset the statistics */
2889 static void
2890 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2891 {
2892         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2893         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2894
2895         /* Mark PF and VSI stats to update the offset, aka "reset" */
2896         pf->offset_loaded = false;
2897         if (pf->main_vsi)
2898                 pf->main_vsi->offset_loaded = false;
2899
2900         /* read the stats, reading current register values into offset */
2901         i40e_read_stats_registers(pf, hw);
2902 }
2903
2904 static uint32_t
2905 i40e_xstats_calc_num(void)
2906 {
2907         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2908                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2909                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2910 }
2911
2912 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2913                                      struct rte_eth_xstat_name *xstats_names,
2914                                      __rte_unused unsigned limit)
2915 {
2916         unsigned count = 0;
2917         unsigned i, prio;
2918
2919         if (xstats_names == NULL)
2920                 return i40e_xstats_calc_num();
2921
2922         /* Note: limit checked in rte_eth_xstats_names() */
2923
2924         /* Get stats from i40e_eth_stats struct */
2925         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2926                 snprintf(xstats_names[count].name,
2927                          sizeof(xstats_names[count].name),
2928                          "%s", rte_i40e_stats_strings[i].name);
2929                 count++;
2930         }
2931
2932         /* Get individiual stats from i40e_hw_port struct */
2933         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2934                 snprintf(xstats_names[count].name,
2935                         sizeof(xstats_names[count].name),
2936                          "%s", rte_i40e_hw_port_strings[i].name);
2937                 count++;
2938         }
2939
2940         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2941                 for (prio = 0; prio < 8; prio++) {
2942                         snprintf(xstats_names[count].name,
2943                                  sizeof(xstats_names[count].name),
2944                                  "rx_priority%u_%s", prio,
2945                                  rte_i40e_rxq_prio_strings[i].name);
2946                         count++;
2947                 }
2948         }
2949
2950         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2951                 for (prio = 0; prio < 8; prio++) {
2952                         snprintf(xstats_names[count].name,
2953                                  sizeof(xstats_names[count].name),
2954                                  "tx_priority%u_%s", prio,
2955                                  rte_i40e_txq_prio_strings[i].name);
2956                         count++;
2957                 }
2958         }
2959         return count;
2960 }
2961
2962 static int
2963 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2964                     unsigned n)
2965 {
2966         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2967         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968         unsigned i, count, prio;
2969         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2970
2971         count = i40e_xstats_calc_num();
2972         if (n < count)
2973                 return count;
2974
2975         i40e_read_stats_registers(pf, hw);
2976
2977         if (xstats == NULL)
2978                 return 0;
2979
2980         count = 0;
2981
2982         /* Get stats from i40e_eth_stats struct */
2983         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2984                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2985                         rte_i40e_stats_strings[i].offset);
2986                 xstats[count].id = count;
2987                 count++;
2988         }
2989
2990         /* Get individiual stats from i40e_hw_port struct */
2991         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2992                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2993                         rte_i40e_hw_port_strings[i].offset);
2994                 xstats[count].id = count;
2995                 count++;
2996         }
2997
2998         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2999                 for (prio = 0; prio < 8; prio++) {
3000                         xstats[count].value =
3001                                 *(uint64_t *)(((char *)hw_stats) +
3002                                 rte_i40e_rxq_prio_strings[i].offset +
3003                                 (sizeof(uint64_t) * prio));
3004                         xstats[count].id = count;
3005                         count++;
3006                 }
3007         }
3008
3009         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3010                 for (prio = 0; prio < 8; prio++) {
3011                         xstats[count].value =
3012                                 *(uint64_t *)(((char *)hw_stats) +
3013                                 rte_i40e_txq_prio_strings[i].offset +
3014                                 (sizeof(uint64_t) * prio));
3015                         xstats[count].id = count;
3016                         count++;
3017                 }
3018         }
3019
3020         return count;
3021 }
3022
3023 static int
3024 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3025                                  __rte_unused uint16_t queue_id,
3026                                  __rte_unused uint8_t stat_idx,
3027                                  __rte_unused uint8_t is_rx)
3028 {
3029         PMD_INIT_FUNC_TRACE();
3030
3031         return -ENOSYS;
3032 }
3033
3034 static int
3035 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3036 {
3037         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3038         u32 full_ver;
3039         u8 ver, patch;
3040         u16 build;
3041         int ret;
3042
3043         full_ver = hw->nvm.oem_ver;
3044         ver = (u8)(full_ver >> 24);
3045         build = (u16)((full_ver >> 8) & 0xffff);
3046         patch = (u8)(full_ver & 0xff);
3047
3048         ret = snprintf(fw_version, fw_size,
3049                  "%d.%d%d 0x%08x %d.%d.%d",
3050                  ((hw->nvm.version >> 12) & 0xf),
3051                  ((hw->nvm.version >> 4) & 0xff),
3052                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3053                  ver, build, patch);
3054
3055         ret += 1; /* add the size of '\0' */
3056         if (fw_size < (u32)ret)
3057                 return ret;
3058         else
3059                 return 0;
3060 }
3061
3062 static void
3063 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3064 {
3065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067         struct i40e_vsi *vsi = pf->main_vsi;
3068         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3069
3070         dev_info->pci_dev = pci_dev;
3071         dev_info->max_rx_queues = vsi->nb_qps;
3072         dev_info->max_tx_queues = vsi->nb_qps;
3073         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3074         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3075         dev_info->max_mac_addrs = vsi->max_macaddrs;
3076         dev_info->max_vfs = pci_dev->max_vfs;
3077         dev_info->rx_offload_capa =
3078                 DEV_RX_OFFLOAD_VLAN_STRIP |
3079                 DEV_RX_OFFLOAD_QINQ_STRIP |
3080                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3081                 DEV_RX_OFFLOAD_UDP_CKSUM |
3082                 DEV_RX_OFFLOAD_TCP_CKSUM;
3083         dev_info->tx_offload_capa =
3084                 DEV_TX_OFFLOAD_VLAN_INSERT |
3085                 DEV_TX_OFFLOAD_QINQ_INSERT |
3086                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3087                 DEV_TX_OFFLOAD_UDP_CKSUM |
3088                 DEV_TX_OFFLOAD_TCP_CKSUM |
3089                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3090                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3091                 DEV_TX_OFFLOAD_TCP_TSO |
3092                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3093                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3094                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3095                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3096         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3097                                                 sizeof(uint32_t);
3098         dev_info->reta_size = pf->hash_lut_size;
3099         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3100
3101         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3102                 .rx_thresh = {
3103                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3104                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3105                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3106                 },
3107                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3108                 .rx_drop_en = 0,
3109         };
3110
3111         dev_info->default_txconf = (struct rte_eth_txconf) {
3112                 .tx_thresh = {
3113                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3114                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3115                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3116                 },
3117                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3118                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3119                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3120                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3121         };
3122
3123         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3124                 .nb_max = I40E_MAX_RING_DESC,
3125                 .nb_min = I40E_MIN_RING_DESC,
3126                 .nb_align = I40E_ALIGN_RING_DESC,
3127         };
3128
3129         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3130                 .nb_max = I40E_MAX_RING_DESC,
3131                 .nb_min = I40E_MIN_RING_DESC,
3132                 .nb_align = I40E_ALIGN_RING_DESC,
3133                 .nb_seg_max = I40E_TX_MAX_SEG,
3134                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3135         };
3136
3137         if (pf->flags & I40E_FLAG_VMDQ) {
3138                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3139                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3140                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3141                                                 pf->max_nb_vmdq_vsi;
3142                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3143                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3144                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3145         }
3146
3147         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3148                 /* For XL710 */
3149                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3150         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3151                 /* For XXV710 */
3152                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3153         else
3154                 /* For X710 */
3155                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3156 }
3157
3158 static int
3159 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3160 {
3161         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3162         struct i40e_vsi *vsi = pf->main_vsi;
3163         PMD_INIT_FUNC_TRACE();
3164
3165         if (on)
3166                 return i40e_vsi_add_vlan(vsi, vlan_id);
3167         else
3168                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3169 }
3170
3171 static int
3172 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3173                                 enum rte_vlan_type vlan_type,
3174                                 uint16_t tpid, int qinq)
3175 {
3176         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3177         uint64_t reg_r = 0;
3178         uint64_t reg_w = 0;
3179         uint16_t reg_id = 3;
3180         int ret;
3181
3182         if (qinq) {
3183                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3184                         reg_id = 2;
3185         }
3186
3187         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3188                                           &reg_r, NULL);
3189         if (ret != I40E_SUCCESS) {
3190                 PMD_DRV_LOG(ERR,
3191                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3192                            reg_id);
3193                 return -EIO;
3194         }
3195         PMD_DRV_LOG(DEBUG,
3196                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3197                     reg_id, reg_r);
3198
3199         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3200         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3201         if (reg_r == reg_w) {
3202                 PMD_DRV_LOG(DEBUG, "No need to write");
3203                 return 0;
3204         }
3205
3206         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3207                                            reg_w, NULL);
3208         if (ret != I40E_SUCCESS) {
3209                 PMD_DRV_LOG(ERR,
3210                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3211                             reg_id);
3212                 return -EIO;
3213         }
3214         PMD_DRV_LOG(DEBUG,
3215                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3216                     reg_w, reg_id);
3217
3218         return 0;
3219 }
3220
3221 static int
3222 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3223                    enum rte_vlan_type vlan_type,
3224                    uint16_t tpid)
3225 {
3226         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3227         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3228         int ret = 0;
3229
3230         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3231              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3232             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3233                 PMD_DRV_LOG(ERR,
3234                             "Unsupported vlan type.");
3235                 return -EINVAL;
3236         }
3237         /* 802.1ad frames ability is added in NVM API 1.7*/
3238         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3239                 if (qinq) {
3240                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3241                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3242                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3243                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3244                 } else {
3245                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3246                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3247                 }
3248                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3249                 if (ret != I40E_SUCCESS) {
3250                         PMD_DRV_LOG(ERR,
3251                                     "Set switch config failed aq_err: %d",
3252                                     hw->aq.asq_last_status);
3253                         ret = -EIO;
3254                 }
3255         } else
3256                 /* If NVM API < 1.7, keep the register setting */
3257                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3258                                                       tpid, qinq);
3259
3260         return ret;
3261 }
3262
3263 static int
3264 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3265 {
3266         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3267         struct i40e_vsi *vsi = pf->main_vsi;
3268
3269         if (mask & ETH_VLAN_FILTER_MASK) {
3270                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3271                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3272                 else
3273                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3274         }
3275
3276         if (mask & ETH_VLAN_STRIP_MASK) {
3277                 /* Enable or disable VLAN stripping */
3278                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3279                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3280                 else
3281                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3282         }
3283
3284         if (mask & ETH_VLAN_EXTEND_MASK) {
3285                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3286                         i40e_vsi_config_double_vlan(vsi, TRUE);
3287                         /* Set global registers with default ethertype. */
3288                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3289                                            ETHER_TYPE_VLAN);
3290                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3291                                            ETHER_TYPE_VLAN);
3292                 }
3293                 else
3294                         i40e_vsi_config_double_vlan(vsi, FALSE);
3295         }
3296
3297         return 0;
3298 }
3299
3300 static void
3301 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3302                           __rte_unused uint16_t queue,
3303                           __rte_unused int on)
3304 {
3305         PMD_INIT_FUNC_TRACE();
3306 }
3307
3308 static int
3309 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3310 {
3311         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3312         struct i40e_vsi *vsi = pf->main_vsi;
3313         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3314         struct i40e_vsi_vlan_pvid_info info;
3315
3316         memset(&info, 0, sizeof(info));
3317         info.on = on;
3318         if (info.on)
3319                 info.config.pvid = pvid;
3320         else {
3321                 info.config.reject.tagged =
3322                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3323                 info.config.reject.untagged =
3324                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3325         }
3326
3327         return i40e_vsi_vlan_pvid_set(vsi, &info);
3328 }
3329
3330 static int
3331 i40e_dev_led_on(struct rte_eth_dev *dev)
3332 {
3333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3334         uint32_t mode = i40e_led_get(hw);
3335
3336         if (mode == 0)
3337                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3338
3339         return 0;
3340 }
3341
3342 static int
3343 i40e_dev_led_off(struct rte_eth_dev *dev)
3344 {
3345         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3346         uint32_t mode = i40e_led_get(hw);
3347
3348         if (mode != 0)
3349                 i40e_led_set(hw, 0, false);
3350
3351         return 0;
3352 }
3353
3354 static int
3355 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3356 {
3357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3359
3360         fc_conf->pause_time = pf->fc_conf.pause_time;
3361
3362         /* read out from register, in case they are modified by other port */
3363         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3364                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3365         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3366                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3367
3368         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3369         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3370
3371          /* Return current mode according to actual setting*/
3372         switch (hw->fc.current_mode) {
3373         case I40E_FC_FULL:
3374                 fc_conf->mode = RTE_FC_FULL;
3375                 break;
3376         case I40E_FC_TX_PAUSE:
3377                 fc_conf->mode = RTE_FC_TX_PAUSE;
3378                 break;
3379         case I40E_FC_RX_PAUSE:
3380                 fc_conf->mode = RTE_FC_RX_PAUSE;
3381                 break;
3382         case I40E_FC_NONE:
3383         default:
3384                 fc_conf->mode = RTE_FC_NONE;
3385         };
3386
3387         return 0;
3388 }
3389
3390 static int
3391 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3392 {
3393         uint32_t mflcn_reg, fctrl_reg, reg;
3394         uint32_t max_high_water;
3395         uint8_t i, aq_failure;
3396         int err;
3397         struct i40e_hw *hw;
3398         struct i40e_pf *pf;
3399         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3400                 [RTE_FC_NONE] = I40E_FC_NONE,
3401                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3402                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3403                 [RTE_FC_FULL] = I40E_FC_FULL
3404         };
3405
3406         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3407
3408         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3409         if ((fc_conf->high_water > max_high_water) ||
3410                         (fc_conf->high_water < fc_conf->low_water)) {
3411                 PMD_INIT_LOG(ERR,
3412                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3413                         max_high_water);
3414                 return -EINVAL;
3415         }
3416
3417         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3418         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3419         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3420
3421         pf->fc_conf.pause_time = fc_conf->pause_time;
3422         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3423         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3424
3425         PMD_INIT_FUNC_TRACE();
3426
3427         /* All the link flow control related enable/disable register
3428          * configuration is handle by the F/W
3429          */
3430         err = i40e_set_fc(hw, &aq_failure, true);
3431         if (err < 0)
3432                 return -ENOSYS;
3433
3434         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3435                 /* Configure flow control refresh threshold,
3436                  * the value for stat_tx_pause_refresh_timer[8]
3437                  * is used for global pause operation.
3438                  */
3439
3440                 I40E_WRITE_REG(hw,
3441                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3442                                pf->fc_conf.pause_time);
3443
3444                 /* configure the timer value included in transmitted pause
3445                  * frame,
3446                  * the value for stat_tx_pause_quanta[8] is used for global
3447                  * pause operation
3448                  */
3449                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3450                                pf->fc_conf.pause_time);
3451
3452                 fctrl_reg = I40E_READ_REG(hw,
3453                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3454
3455                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3456                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3457                 else
3458                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3459
3460                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3461                                fctrl_reg);
3462         } else {
3463                 /* Configure pause time (2 TCs per register) */
3464                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3465                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3466                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3467
3468                 /* Configure flow control refresh threshold value */
3469                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3470                                pf->fc_conf.pause_time / 2);
3471
3472                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3473
3474                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3475                  *depending on configuration
3476                  */
3477                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3478                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3479                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3480                 } else {
3481                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3482                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3483                 }
3484
3485                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3486         }
3487
3488         /* config the water marker both based on the packets and bytes */
3489         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3490                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3491                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3492         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3493                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3494                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3495         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3496                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3497                        << I40E_KILOSHIFT);
3498         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3499                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3500                        << I40E_KILOSHIFT);
3501
3502         I40E_WRITE_FLUSH(hw);
3503
3504         return 0;
3505 }
3506
3507 static int
3508 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3509                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3510 {
3511         PMD_INIT_FUNC_TRACE();
3512
3513         return -ENOSYS;
3514 }
3515
3516 /* Add a MAC address, and update filters */
3517 static int
3518 i40e_macaddr_add(struct rte_eth_dev *dev,
3519                  struct ether_addr *mac_addr,
3520                  __rte_unused uint32_t index,
3521                  uint32_t pool)
3522 {
3523         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3524         struct i40e_mac_filter_info mac_filter;
3525         struct i40e_vsi *vsi;
3526         int ret;
3527
3528         /* If VMDQ not enabled or configured, return */
3529         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3530                           !pf->nb_cfg_vmdq_vsi)) {
3531                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3532                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3533                         pool);
3534                 return -ENOTSUP;
3535         }
3536
3537         if (pool > pf->nb_cfg_vmdq_vsi) {
3538                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3539                                 pool, pf->nb_cfg_vmdq_vsi);
3540                 return -EINVAL;
3541         }
3542
3543         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3544         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3545                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3546         else
3547                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3548
3549         if (pool == 0)
3550                 vsi = pf->main_vsi;
3551         else
3552                 vsi = pf->vmdq[pool - 1].vsi;
3553
3554         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3555         if (ret != I40E_SUCCESS) {
3556                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3557                 return -ENODEV;
3558         }
3559         return 0;
3560 }
3561
3562 /* Remove a MAC address, and update filters */
3563 static void
3564 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3565 {
3566         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3567         struct i40e_vsi *vsi;
3568         struct rte_eth_dev_data *data = dev->data;
3569         struct ether_addr *macaddr;
3570         int ret;
3571         uint32_t i;
3572         uint64_t pool_sel;
3573
3574         macaddr = &(data->mac_addrs[index]);
3575
3576         pool_sel = dev->data->mac_pool_sel[index];
3577
3578         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3579                 if (pool_sel & (1ULL << i)) {
3580                         if (i == 0)
3581                                 vsi = pf->main_vsi;
3582                         else {
3583                                 /* No VMDQ pool enabled or configured */
3584                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3585                                         (i > pf->nb_cfg_vmdq_vsi)) {
3586                                         PMD_DRV_LOG(ERR,
3587                                                 "No VMDQ pool enabled/configured");
3588                                         return;
3589                                 }
3590                                 vsi = pf->vmdq[i - 1].vsi;
3591                         }
3592                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3593
3594                         if (ret) {
3595                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3596                                 return;
3597                         }
3598                 }
3599         }
3600 }
3601
3602 /* Set perfect match or hash match of MAC and VLAN for a VF */
3603 static int
3604 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3605                  struct rte_eth_mac_filter *filter,
3606                  bool add)
3607 {
3608         struct i40e_hw *hw;
3609         struct i40e_mac_filter_info mac_filter;
3610         struct ether_addr old_mac;
3611         struct ether_addr *new_mac;
3612         struct i40e_pf_vf *vf = NULL;
3613         uint16_t vf_id;
3614         int ret;
3615
3616         if (pf == NULL) {
3617                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3618                 return -EINVAL;
3619         }
3620         hw = I40E_PF_TO_HW(pf);
3621
3622         if (filter == NULL) {
3623                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3624                 return -EINVAL;
3625         }
3626
3627         new_mac = &filter->mac_addr;
3628
3629         if (is_zero_ether_addr(new_mac)) {
3630                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3631                 return -EINVAL;
3632         }
3633
3634         vf_id = filter->dst_id;
3635
3636         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3637                 PMD_DRV_LOG(ERR, "Invalid argument.");
3638                 return -EINVAL;
3639         }
3640         vf = &pf->vfs[vf_id];
3641
3642         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3643                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3644                 return -EINVAL;
3645         }
3646
3647         if (add) {
3648                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3649                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3650                                 ETHER_ADDR_LEN);
3651                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3652                                  ETHER_ADDR_LEN);
3653
3654                 mac_filter.filter_type = filter->filter_type;
3655                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3656                 if (ret != I40E_SUCCESS) {
3657                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3658                         return -1;
3659                 }
3660                 ether_addr_copy(new_mac, &pf->dev_addr);
3661         } else {
3662                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3663                                 ETHER_ADDR_LEN);
3664                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3665                 if (ret != I40E_SUCCESS) {
3666                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3667                         return -1;
3668                 }
3669
3670                 /* Clear device address as it has been removed */
3671                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3672                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3673         }
3674
3675         return 0;
3676 }
3677
3678 /* MAC filter handle */
3679 static int
3680 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3681                 void *arg)
3682 {
3683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3684         struct rte_eth_mac_filter *filter;
3685         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3686         int ret = I40E_NOT_SUPPORTED;
3687
3688         filter = (struct rte_eth_mac_filter *)(arg);
3689
3690         switch (filter_op) {
3691         case RTE_ETH_FILTER_NOP:
3692                 ret = I40E_SUCCESS;
3693                 break;
3694         case RTE_ETH_FILTER_ADD:
3695                 i40e_pf_disable_irq0(hw);
3696                 if (filter->is_vf)
3697                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3698                 i40e_pf_enable_irq0(hw);
3699                 break;
3700         case RTE_ETH_FILTER_DELETE:
3701                 i40e_pf_disable_irq0(hw);
3702                 if (filter->is_vf)
3703                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3704                 i40e_pf_enable_irq0(hw);
3705                 break;
3706         default:
3707                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3708                 ret = I40E_ERR_PARAM;
3709                 break;
3710         }
3711
3712         return ret;
3713 }
3714
3715 static int
3716 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3717 {
3718         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3719         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3720         int ret;
3721
3722         if (!lut)
3723                 return -EINVAL;
3724
3725         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3726                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3727                                           lut, lut_size);
3728                 if (ret) {
3729                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3730                         return ret;
3731                 }
3732         } else {
3733                 uint32_t *lut_dw = (uint32_t *)lut;
3734                 uint16_t i, lut_size_dw = lut_size / 4;
3735
3736                 for (i = 0; i < lut_size_dw; i++)
3737                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3738         }
3739
3740         return 0;
3741 }
3742
3743 static int
3744 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3745 {
3746         struct i40e_pf *pf;
3747         struct i40e_hw *hw;
3748         int ret;
3749
3750         if (!vsi || !lut)
3751                 return -EINVAL;
3752
3753         pf = I40E_VSI_TO_PF(vsi);
3754         hw = I40E_VSI_TO_HW(vsi);
3755
3756         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3757                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3758                                           lut, lut_size);
3759                 if (ret) {
3760                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3761                         return ret;
3762                 }
3763         } else {
3764                 uint32_t *lut_dw = (uint32_t *)lut;
3765                 uint16_t i, lut_size_dw = lut_size / 4;
3766
3767                 for (i = 0; i < lut_size_dw; i++)
3768                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3769                 I40E_WRITE_FLUSH(hw);
3770         }
3771
3772         return 0;
3773 }
3774
3775 static int
3776 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3777                          struct rte_eth_rss_reta_entry64 *reta_conf,
3778                          uint16_t reta_size)
3779 {
3780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3781         uint16_t i, lut_size = pf->hash_lut_size;
3782         uint16_t idx, shift;
3783         uint8_t *lut;
3784         int ret;
3785
3786         if (reta_size != lut_size ||
3787                 reta_size > ETH_RSS_RETA_SIZE_512) {
3788                 PMD_DRV_LOG(ERR,
3789                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3790                         reta_size, lut_size);
3791                 return -EINVAL;
3792         }
3793
3794         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3795         if (!lut) {
3796                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3797                 return -ENOMEM;
3798         }
3799         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3800         if (ret)
3801                 goto out;
3802         for (i = 0; i < reta_size; i++) {
3803                 idx = i / RTE_RETA_GROUP_SIZE;
3804                 shift = i % RTE_RETA_GROUP_SIZE;
3805                 if (reta_conf[idx].mask & (1ULL << shift))
3806                         lut[i] = reta_conf[idx].reta[shift];
3807         }
3808         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3809
3810 out:
3811         rte_free(lut);
3812
3813         return ret;
3814 }
3815
3816 static int
3817 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3818                         struct rte_eth_rss_reta_entry64 *reta_conf,
3819                         uint16_t reta_size)
3820 {
3821         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3822         uint16_t i, lut_size = pf->hash_lut_size;
3823         uint16_t idx, shift;
3824         uint8_t *lut;
3825         int ret;
3826
3827         if (reta_size != lut_size ||
3828                 reta_size > ETH_RSS_RETA_SIZE_512) {
3829                 PMD_DRV_LOG(ERR,
3830                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3831                         reta_size, lut_size);
3832                 return -EINVAL;
3833         }
3834
3835         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3836         if (!lut) {
3837                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3838                 return -ENOMEM;
3839         }
3840
3841         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3842         if (ret)
3843                 goto out;
3844         for (i = 0; i < reta_size; i++) {
3845                 idx = i / RTE_RETA_GROUP_SIZE;
3846                 shift = i % RTE_RETA_GROUP_SIZE;
3847                 if (reta_conf[idx].mask & (1ULL << shift))
3848                         reta_conf[idx].reta[shift] = lut[i];
3849         }
3850
3851 out:
3852         rte_free(lut);
3853
3854         return ret;
3855 }
3856
3857 /**
3858  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3859  * @hw:   pointer to the HW structure
3860  * @mem:  pointer to mem struct to fill out
3861  * @size: size of memory requested
3862  * @alignment: what to align the allocation to
3863  **/
3864 enum i40e_status_code
3865 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3866                         struct i40e_dma_mem *mem,
3867                         u64 size,
3868                         u32 alignment)
3869 {
3870         const struct rte_memzone *mz = NULL;
3871         char z_name[RTE_MEMZONE_NAMESIZE];
3872
3873         if (!mem)
3874                 return I40E_ERR_PARAM;
3875
3876         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3877         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3878                                          alignment, RTE_PGSIZE_2M);
3879         if (!mz)
3880                 return I40E_ERR_NO_MEMORY;
3881
3882         mem->size = size;
3883         mem->va = mz->addr;
3884         mem->pa = mz->iova;
3885         mem->zone = (const void *)mz;
3886         PMD_DRV_LOG(DEBUG,
3887                 "memzone %s allocated with physical address: %"PRIu64,
3888                 mz->name, mem->pa);
3889
3890         return I40E_SUCCESS;
3891 }
3892
3893 /**
3894  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3895  * @hw:   pointer to the HW structure
3896  * @mem:  ptr to mem struct to free
3897  **/
3898 enum i40e_status_code
3899 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3900                     struct i40e_dma_mem *mem)
3901 {
3902         if (!mem)
3903                 return I40E_ERR_PARAM;
3904
3905         PMD_DRV_LOG(DEBUG,
3906                 "memzone %s to be freed with physical address: %"PRIu64,
3907                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3908         rte_memzone_free((const struct rte_memzone *)mem->zone);
3909         mem->zone = NULL;
3910         mem->va = NULL;
3911         mem->pa = (u64)0;
3912
3913         return I40E_SUCCESS;
3914 }
3915
3916 /**
3917  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3918  * @hw:   pointer to the HW structure
3919  * @mem:  pointer to mem struct to fill out
3920  * @size: size of memory requested
3921  **/
3922 enum i40e_status_code
3923 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3924                          struct i40e_virt_mem *mem,
3925                          u32 size)
3926 {
3927         if (!mem)
3928                 return I40E_ERR_PARAM;
3929
3930         mem->size = size;
3931         mem->va = rte_zmalloc("i40e", size, 0);
3932
3933         if (mem->va)
3934                 return I40E_SUCCESS;
3935         else
3936                 return I40E_ERR_NO_MEMORY;
3937 }
3938
3939 /**
3940  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3941  * @hw:   pointer to the HW structure
3942  * @mem:  pointer to mem struct to free
3943  **/
3944 enum i40e_status_code
3945 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3946                      struct i40e_virt_mem *mem)
3947 {
3948         if (!mem)
3949                 return I40E_ERR_PARAM;
3950
3951         rte_free(mem->va);
3952         mem->va = NULL;
3953
3954         return I40E_SUCCESS;
3955 }
3956
3957 void
3958 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3959 {
3960         rte_spinlock_init(&sp->spinlock);
3961 }
3962
3963 void
3964 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3965 {
3966         rte_spinlock_lock(&sp->spinlock);
3967 }
3968
3969 void
3970 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3971 {
3972         rte_spinlock_unlock(&sp->spinlock);
3973 }
3974
3975 void
3976 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3977 {
3978         return;
3979 }
3980
3981 /**
3982  * Get the hardware capabilities, which will be parsed
3983  * and saved into struct i40e_hw.
3984  */
3985 static int
3986 i40e_get_cap(struct i40e_hw *hw)
3987 {
3988         struct i40e_aqc_list_capabilities_element_resp *buf;
3989         uint16_t len, size = 0;
3990         int ret;
3991
3992         /* Calculate a huge enough buff for saving response data temporarily */
3993         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3994                                                 I40E_MAX_CAP_ELE_NUM;
3995         buf = rte_zmalloc("i40e", len, 0);
3996         if (!buf) {
3997                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3998                 return I40E_ERR_NO_MEMORY;
3999         }
4000
4001         /* Get, parse the capabilities and save it to hw */
4002         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4003                         i40e_aqc_opc_list_func_capabilities, NULL);
4004         if (ret != I40E_SUCCESS)
4005                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4006
4007         /* Free the temporary buffer after being used */
4008         rte_free(buf);
4009
4010         return ret;
4011 }
4012
4013 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4014 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4015 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16");
4016
4017 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4018                 const char *value,
4019                 void *opaque)
4020 {
4021         struct i40e_pf *pf;
4022         unsigned long num;
4023         char *end;
4024
4025         pf = (struct i40e_pf *)opaque;
4026         RTE_SET_USED(key);
4027
4028         errno = 0;
4029         num = strtoul(value, &end, 0);
4030         if (errno != 0 || end == value || *end != 0) {
4031                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4032                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4033                 return -(EINVAL);
4034         }
4035
4036         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4037                 pf->vf_nb_qp_max = (uint16_t)num;
4038         else
4039                 /* here return 0 to make next valid same argument work */
4040                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4041                             "power of 2 and equal or less than 16 !, Now it is "
4042                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4043
4044         return 0;
4045 }
4046
4047 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4048 {
4049         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4051         struct rte_kvargs *kvlist;
4052
4053         /* set default queue number per VF as 4 */
4054         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4055
4056         if (dev->device->devargs == NULL)
4057                 return 0;
4058
4059         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4060         if (kvlist == NULL)
4061                 return -(EINVAL);
4062
4063         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4064                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4065                             "the first invalid or last valid one is used !",
4066                             QUEUE_NUM_PER_VF_ARG);
4067
4068         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4069                            i40e_pf_parse_vf_queue_number_handler, pf);
4070
4071         rte_kvargs_free(kvlist);
4072
4073         return 0;
4074 }
4075
4076 static int
4077 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4078 {
4079         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4080         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4081         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4082         uint16_t qp_count = 0, vsi_count = 0;
4083
4084         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4085                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4086                 return -EINVAL;
4087         }
4088
4089         i40e_pf_config_vf_rxq_number(dev);
4090
4091         /* Add the parameter init for LFC */
4092         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4093         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4094         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4095
4096         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4097         pf->max_num_vsi = hw->func_caps.num_vsis;
4098         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4099         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4100
4101         /* FDir queue/VSI allocation */
4102         pf->fdir_qp_offset = 0;
4103         if (hw->func_caps.fd) {
4104                 pf->flags |= I40E_FLAG_FDIR;
4105                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4106         } else {
4107                 pf->fdir_nb_qps = 0;
4108         }
4109         qp_count += pf->fdir_nb_qps;
4110         vsi_count += 1;
4111
4112         /* LAN queue/VSI allocation */
4113         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4114         if (!hw->func_caps.rss) {
4115                 pf->lan_nb_qps = 1;
4116         } else {
4117                 pf->flags |= I40E_FLAG_RSS;
4118                 if (hw->mac.type == I40E_MAC_X722)
4119                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4120                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4121         }
4122         qp_count += pf->lan_nb_qps;
4123         vsi_count += 1;
4124
4125         /* VF queue/VSI allocation */
4126         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4127         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4128                 pf->flags |= I40E_FLAG_SRIOV;
4129                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4130                 pf->vf_num = pci_dev->max_vfs;
4131                 PMD_DRV_LOG(DEBUG,
4132                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4133                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4134         } else {
4135                 pf->vf_nb_qps = 0;
4136                 pf->vf_num = 0;
4137         }
4138         qp_count += pf->vf_nb_qps * pf->vf_num;
4139         vsi_count += pf->vf_num;
4140
4141         /* VMDq queue/VSI allocation */
4142         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4143         pf->vmdq_nb_qps = 0;
4144         pf->max_nb_vmdq_vsi = 0;
4145         if (hw->func_caps.vmdq) {
4146                 if (qp_count < hw->func_caps.num_tx_qp &&
4147                         vsi_count < hw->func_caps.num_vsis) {
4148                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4149                                 qp_count) / pf->vmdq_nb_qp_max;
4150
4151                         /* Limit the maximum number of VMDq vsi to the maximum
4152                          * ethdev can support
4153                          */
4154                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4155                                 hw->func_caps.num_vsis - vsi_count);
4156                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4157                                 ETH_64_POOLS);
4158                         if (pf->max_nb_vmdq_vsi) {
4159                                 pf->flags |= I40E_FLAG_VMDQ;
4160                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4161                                 PMD_DRV_LOG(DEBUG,
4162                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4163                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4164                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4165                         } else {
4166                                 PMD_DRV_LOG(INFO,
4167                                         "No enough queues left for VMDq");
4168                         }
4169                 } else {
4170                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4171                 }
4172         }
4173         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4174         vsi_count += pf->max_nb_vmdq_vsi;
4175
4176         if (hw->func_caps.dcb)
4177                 pf->flags |= I40E_FLAG_DCB;
4178
4179         if (qp_count > hw->func_caps.num_tx_qp) {
4180                 PMD_DRV_LOG(ERR,
4181                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4182                         qp_count, hw->func_caps.num_tx_qp);
4183                 return -EINVAL;
4184         }
4185         if (vsi_count > hw->func_caps.num_vsis) {
4186                 PMD_DRV_LOG(ERR,
4187                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4188                         vsi_count, hw->func_caps.num_vsis);
4189                 return -EINVAL;
4190         }
4191
4192         return 0;
4193 }
4194
4195 static int
4196 i40e_pf_get_switch_config(struct i40e_pf *pf)
4197 {
4198         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4199         struct i40e_aqc_get_switch_config_resp *switch_config;
4200         struct i40e_aqc_switch_config_element_resp *element;
4201         uint16_t start_seid = 0, num_reported;
4202         int ret;
4203
4204         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4205                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4206         if (!switch_config) {
4207                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4208                 return -ENOMEM;
4209         }
4210
4211         /* Get the switch configurations */
4212         ret = i40e_aq_get_switch_config(hw, switch_config,
4213                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4214         if (ret != I40E_SUCCESS) {
4215                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4216                 goto fail;
4217         }
4218         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4219         if (num_reported != 1) { /* The number should be 1 */
4220                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4221                 goto fail;
4222         }
4223
4224         /* Parse the switch configuration elements */
4225         element = &(switch_config->element[0]);
4226         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4227                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4228                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4229         } else
4230                 PMD_DRV_LOG(INFO, "Unknown element type");
4231
4232 fail:
4233         rte_free(switch_config);
4234
4235         return ret;
4236 }
4237
4238 static int
4239 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4240                         uint32_t num)
4241 {
4242         struct pool_entry *entry;
4243
4244         if (pool == NULL || num == 0)
4245                 return -EINVAL;
4246
4247         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4248         if (entry == NULL) {
4249                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4250                 return -ENOMEM;
4251         }
4252
4253         /* queue heap initialize */
4254         pool->num_free = num;
4255         pool->num_alloc = 0;
4256         pool->base = base;
4257         LIST_INIT(&pool->alloc_list);
4258         LIST_INIT(&pool->free_list);
4259
4260         /* Initialize element  */
4261         entry->base = 0;
4262         entry->len = num;
4263
4264         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4265         return 0;
4266 }
4267
4268 static void
4269 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4270 {
4271         struct pool_entry *entry, *next_entry;
4272
4273         if (pool == NULL)
4274                 return;
4275
4276         for (entry = LIST_FIRST(&pool->alloc_list);
4277                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4278                         entry = next_entry) {
4279                 LIST_REMOVE(entry, next);
4280                 rte_free(entry);
4281         }
4282
4283         for (entry = LIST_FIRST(&pool->free_list);
4284                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4285                         entry = next_entry) {
4286                 LIST_REMOVE(entry, next);
4287                 rte_free(entry);
4288         }
4289
4290         pool->num_free = 0;
4291         pool->num_alloc = 0;
4292         pool->base = 0;
4293         LIST_INIT(&pool->alloc_list);
4294         LIST_INIT(&pool->free_list);
4295 }
4296
4297 static int
4298 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4299                        uint32_t base)
4300 {
4301         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4302         uint32_t pool_offset;
4303         int insert;
4304
4305         if (pool == NULL) {
4306                 PMD_DRV_LOG(ERR, "Invalid parameter");
4307                 return -EINVAL;
4308         }
4309
4310         pool_offset = base - pool->base;
4311         /* Lookup in alloc list */
4312         LIST_FOREACH(entry, &pool->alloc_list, next) {
4313                 if (entry->base == pool_offset) {
4314                         valid_entry = entry;
4315                         LIST_REMOVE(entry, next);
4316                         break;
4317                 }
4318         }
4319
4320         /* Not find, return */
4321         if (valid_entry == NULL) {
4322                 PMD_DRV_LOG(ERR, "Failed to find entry");
4323                 return -EINVAL;
4324         }
4325
4326         /**
4327          * Found it, move it to free list  and try to merge.
4328          * In order to make merge easier, always sort it by qbase.
4329          * Find adjacent prev and last entries.
4330          */
4331         prev = next = NULL;
4332         LIST_FOREACH(entry, &pool->free_list, next) {
4333                 if (entry->base > valid_entry->base) {
4334                         next = entry;
4335                         break;
4336                 }
4337                 prev = entry;
4338         }
4339
4340         insert = 0;
4341         /* Try to merge with next one*/
4342         if (next != NULL) {
4343                 /* Merge with next one */
4344                 if (valid_entry->base + valid_entry->len == next->base) {
4345                         next->base = valid_entry->base;
4346                         next->len += valid_entry->len;
4347                         rte_free(valid_entry);
4348                         valid_entry = next;
4349                         insert = 1;
4350                 }
4351         }
4352
4353         if (prev != NULL) {
4354                 /* Merge with previous one */
4355                 if (prev->base + prev->len == valid_entry->base) {
4356                         prev->len += valid_entry->len;
4357                         /* If it merge with next one, remove next node */
4358                         if (insert == 1) {
4359                                 LIST_REMOVE(valid_entry, next);
4360                                 rte_free(valid_entry);
4361                         } else {
4362                                 rte_free(valid_entry);
4363                                 insert = 1;
4364                         }
4365                 }
4366         }
4367
4368         /* Not find any entry to merge, insert */
4369         if (insert == 0) {
4370                 if (prev != NULL)
4371                         LIST_INSERT_AFTER(prev, valid_entry, next);
4372                 else if (next != NULL)
4373                         LIST_INSERT_BEFORE(next, valid_entry, next);
4374                 else /* It's empty list, insert to head */
4375                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4376         }
4377
4378         pool->num_free += valid_entry->len;
4379         pool->num_alloc -= valid_entry->len;
4380
4381         return 0;
4382 }
4383
4384 static int
4385 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4386                        uint16_t num)
4387 {
4388         struct pool_entry *entry, *valid_entry;
4389
4390         if (pool == NULL || num == 0) {
4391                 PMD_DRV_LOG(ERR, "Invalid parameter");
4392                 return -EINVAL;
4393         }
4394
4395         if (pool->num_free < num) {
4396                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4397                             num, pool->num_free);
4398                 return -ENOMEM;
4399         }
4400
4401         valid_entry = NULL;
4402         /* Lookup  in free list and find most fit one */
4403         LIST_FOREACH(entry, &pool->free_list, next) {
4404                 if (entry->len >= num) {
4405                         /* Find best one */
4406                         if (entry->len == num) {
4407                                 valid_entry = entry;
4408                                 break;
4409                         }
4410                         if (valid_entry == NULL || valid_entry->len > entry->len)
4411                                 valid_entry = entry;
4412                 }
4413         }
4414
4415         /* Not find one to satisfy the request, return */
4416         if (valid_entry == NULL) {
4417                 PMD_DRV_LOG(ERR, "No valid entry found");
4418                 return -ENOMEM;
4419         }
4420         /**
4421          * The entry have equal queue number as requested,
4422          * remove it from alloc_list.
4423          */
4424         if (valid_entry->len == num) {
4425                 LIST_REMOVE(valid_entry, next);
4426         } else {
4427                 /**
4428                  * The entry have more numbers than requested,
4429                  * create a new entry for alloc_list and minus its
4430                  * queue base and number in free_list.
4431                  */
4432                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4433                 if (entry == NULL) {
4434                         PMD_DRV_LOG(ERR,
4435                                 "Failed to allocate memory for resource pool");
4436                         return -ENOMEM;
4437                 }
4438                 entry->base = valid_entry->base;
4439                 entry->len = num;
4440                 valid_entry->base += num;
4441                 valid_entry->len -= num;
4442                 valid_entry = entry;
4443         }
4444
4445         /* Insert it into alloc list, not sorted */
4446         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4447
4448         pool->num_free -= valid_entry->len;
4449         pool->num_alloc += valid_entry->len;
4450
4451         return valid_entry->base + pool->base;
4452 }
4453
4454 /**
4455  * bitmap_is_subset - Check whether src2 is subset of src1
4456  **/
4457 static inline int
4458 bitmap_is_subset(uint8_t src1, uint8_t src2)
4459 {
4460         return !((src1 ^ src2) & src2);
4461 }
4462
4463 static enum i40e_status_code
4464 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4465 {
4466         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4467
4468         /* If DCB is not supported, only default TC is supported */
4469         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4470                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4471                 return I40E_NOT_SUPPORTED;
4472         }
4473
4474         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4475                 PMD_DRV_LOG(ERR,
4476                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4477                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4478                 return I40E_NOT_SUPPORTED;
4479         }
4480         return I40E_SUCCESS;
4481 }
4482
4483 int
4484 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4485                                 struct i40e_vsi_vlan_pvid_info *info)
4486 {
4487         struct i40e_hw *hw;
4488         struct i40e_vsi_context ctxt;
4489         uint8_t vlan_flags = 0;
4490         int ret;
4491
4492         if (vsi == NULL || info == NULL) {
4493                 PMD_DRV_LOG(ERR, "invalid parameters");
4494                 return I40E_ERR_PARAM;
4495         }
4496
4497         if (info->on) {
4498                 vsi->info.pvid = info->config.pvid;
4499                 /**
4500                  * If insert pvid is enabled, only tagged pkts are
4501                  * allowed to be sent out.
4502                  */
4503                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4504                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4505         } else {
4506                 vsi->info.pvid = 0;
4507                 if (info->config.reject.tagged == 0)
4508                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4509
4510                 if (info->config.reject.untagged == 0)
4511                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4512         }
4513         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4514                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4515         vsi->info.port_vlan_flags |= vlan_flags;
4516         vsi->info.valid_sections =
4517                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4518         memset(&ctxt, 0, sizeof(ctxt));
4519         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4520         ctxt.seid = vsi->seid;
4521
4522         hw = I40E_VSI_TO_HW(vsi);
4523         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4524         if (ret != I40E_SUCCESS)
4525                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4526
4527         return ret;
4528 }
4529
4530 static int
4531 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4532 {
4533         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4534         int i, ret;
4535         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4536
4537         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4538         if (ret != I40E_SUCCESS)
4539                 return ret;
4540
4541         if (!vsi->seid) {
4542                 PMD_DRV_LOG(ERR, "seid not valid");
4543                 return -EINVAL;
4544         }
4545
4546         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4547         tc_bw_data.tc_valid_bits = enabled_tcmap;
4548         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4549                 tc_bw_data.tc_bw_credits[i] =
4550                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4551
4552         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4553         if (ret != I40E_SUCCESS) {
4554                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4555                 return ret;
4556         }
4557
4558         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4559                                         sizeof(vsi->info.qs_handle));
4560         return I40E_SUCCESS;
4561 }
4562
4563 static enum i40e_status_code
4564 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4565                                  struct i40e_aqc_vsi_properties_data *info,
4566                                  uint8_t enabled_tcmap)
4567 {
4568         enum i40e_status_code ret;
4569         int i, total_tc = 0;
4570         uint16_t qpnum_per_tc, bsf, qp_idx;
4571
4572         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4573         if (ret != I40E_SUCCESS)
4574                 return ret;
4575
4576         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4577                 if (enabled_tcmap & (1 << i))
4578                         total_tc++;
4579         if (total_tc == 0)
4580                 total_tc = 1;
4581         vsi->enabled_tc = enabled_tcmap;
4582
4583         /* Number of queues per enabled TC */
4584         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4585         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4586         bsf = rte_bsf32(qpnum_per_tc);
4587
4588         /* Adjust the queue number to actual queues that can be applied */
4589         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4590                 vsi->nb_qps = qpnum_per_tc * total_tc;
4591
4592         /**
4593          * Configure TC and queue mapping parameters, for enabled TC,
4594          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4595          * default queue will serve it.
4596          */
4597         qp_idx = 0;
4598         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4599                 if (vsi->enabled_tc & (1 << i)) {
4600                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4601                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4602                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4603                         qp_idx += qpnum_per_tc;
4604                 } else
4605                         info->tc_mapping[i] = 0;
4606         }
4607
4608         /* Associate queue number with VSI */
4609         if (vsi->type == I40E_VSI_SRIOV) {
4610                 info->mapping_flags |=
4611                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4612                 for (i = 0; i < vsi->nb_qps; i++)
4613                         info->queue_mapping[i] =
4614                                 rte_cpu_to_le_16(vsi->base_queue + i);
4615         } else {
4616                 info->mapping_flags |=
4617                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4618                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4619         }
4620         info->valid_sections |=
4621                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4622
4623         return I40E_SUCCESS;
4624 }
4625
4626 static int
4627 i40e_veb_release(struct i40e_veb *veb)
4628 {
4629         struct i40e_vsi *vsi;
4630         struct i40e_hw *hw;
4631
4632         if (veb == NULL)
4633                 return -EINVAL;
4634
4635         if (!TAILQ_EMPTY(&veb->head)) {
4636                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4637                 return -EACCES;
4638         }
4639         /* associate_vsi field is NULL for floating VEB */
4640         if (veb->associate_vsi != NULL) {
4641                 vsi = veb->associate_vsi;
4642                 hw = I40E_VSI_TO_HW(vsi);
4643
4644                 vsi->uplink_seid = veb->uplink_seid;
4645                 vsi->veb = NULL;
4646         } else {
4647                 veb->associate_pf->main_vsi->floating_veb = NULL;
4648                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4649         }
4650
4651         i40e_aq_delete_element(hw, veb->seid, NULL);
4652         rte_free(veb);
4653         return I40E_SUCCESS;
4654 }
4655
4656 /* Setup a veb */
4657 static struct i40e_veb *
4658 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4659 {
4660         struct i40e_veb *veb;
4661         int ret;
4662         struct i40e_hw *hw;
4663
4664         if (pf == NULL) {
4665                 PMD_DRV_LOG(ERR,
4666                             "veb setup failed, associated PF shouldn't null");
4667                 return NULL;
4668         }
4669         hw = I40E_PF_TO_HW(pf);
4670
4671         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4672         if (!veb) {
4673                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4674                 goto fail;
4675         }
4676
4677         veb->associate_vsi = vsi;
4678         veb->associate_pf = pf;
4679         TAILQ_INIT(&veb->head);
4680         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4681
4682         /* create floating veb if vsi is NULL */
4683         if (vsi != NULL) {
4684                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4685                                       I40E_DEFAULT_TCMAP, false,
4686                                       &veb->seid, false, NULL);
4687         } else {
4688                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4689                                       true, &veb->seid, false, NULL);
4690         }
4691
4692         if (ret != I40E_SUCCESS) {
4693                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4694                             hw->aq.asq_last_status);
4695                 goto fail;
4696         }
4697         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4698
4699         /* get statistics index */
4700         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4701                                 &veb->stats_idx, NULL, NULL, NULL);
4702         if (ret != I40E_SUCCESS) {
4703                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4704                             hw->aq.asq_last_status);
4705                 goto fail;
4706         }
4707         /* Get VEB bandwidth, to be implemented */
4708         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4709         if (vsi)
4710                 vsi->uplink_seid = veb->seid;
4711
4712         return veb;
4713 fail:
4714         rte_free(veb);
4715         return NULL;
4716 }
4717
4718 int
4719 i40e_vsi_release(struct i40e_vsi *vsi)
4720 {
4721         struct i40e_pf *pf;
4722         struct i40e_hw *hw;
4723         struct i40e_vsi_list *vsi_list;
4724         void *temp;
4725         int ret;
4726         struct i40e_mac_filter *f;
4727         uint16_t user_param;
4728
4729         if (!vsi)
4730                 return I40E_SUCCESS;
4731
4732         if (!vsi->adapter)
4733                 return -EFAULT;
4734
4735         user_param = vsi->user_param;
4736
4737         pf = I40E_VSI_TO_PF(vsi);
4738         hw = I40E_VSI_TO_HW(vsi);
4739
4740         /* VSI has child to attach, release child first */
4741         if (vsi->veb) {
4742                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4743                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4744                                 return -1;
4745                 }
4746                 i40e_veb_release(vsi->veb);
4747         }
4748
4749         if (vsi->floating_veb) {
4750                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4751                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4752                                 return -1;
4753                 }
4754         }
4755
4756         /* Remove all macvlan filters of the VSI */
4757         i40e_vsi_remove_all_macvlan_filter(vsi);
4758         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4759                 rte_free(f);
4760
4761         if (vsi->type != I40E_VSI_MAIN &&
4762             ((vsi->type != I40E_VSI_SRIOV) ||
4763             !pf->floating_veb_list[user_param])) {
4764                 /* Remove vsi from parent's sibling list */
4765                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4766                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4767                         return I40E_ERR_PARAM;
4768                 }
4769                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4770                                 &vsi->sib_vsi_list, list);
4771
4772                 /* Remove all switch element of the VSI */
4773                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4774                 if (ret != I40E_SUCCESS)
4775                         PMD_DRV_LOG(ERR, "Failed to delete element");
4776         }
4777
4778         if ((vsi->type == I40E_VSI_SRIOV) &&
4779             pf->floating_veb_list[user_param]) {
4780                 /* Remove vsi from parent's sibling list */
4781                 if (vsi->parent_vsi == NULL ||
4782                     vsi->parent_vsi->floating_veb == NULL) {
4783                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4784                         return I40E_ERR_PARAM;
4785                 }
4786                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4787                              &vsi->sib_vsi_list, list);
4788
4789                 /* Remove all switch element of the VSI */
4790                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4791                 if (ret != I40E_SUCCESS)
4792                         PMD_DRV_LOG(ERR, "Failed to delete element");
4793         }
4794
4795         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4796
4797         if (vsi->type != I40E_VSI_SRIOV)
4798                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4799         rte_free(vsi);
4800
4801         return I40E_SUCCESS;
4802 }
4803
4804 static int
4805 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4806 {
4807         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4808         struct i40e_aqc_remove_macvlan_element_data def_filter;
4809         struct i40e_mac_filter_info filter;
4810         int ret;
4811
4812         if (vsi->type != I40E_VSI_MAIN)
4813                 return I40E_ERR_CONFIG;
4814         memset(&def_filter, 0, sizeof(def_filter));
4815         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4816                                         ETH_ADDR_LEN);
4817         def_filter.vlan_tag = 0;
4818         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4819                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4820         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4821         if (ret != I40E_SUCCESS) {
4822                 struct i40e_mac_filter *f;
4823                 struct ether_addr *mac;
4824
4825                 PMD_DRV_LOG(DEBUG,
4826                             "Cannot remove the default macvlan filter");
4827                 /* It needs to add the permanent mac into mac list */
4828                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4829                 if (f == NULL) {
4830                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4831                         return I40E_ERR_NO_MEMORY;
4832                 }
4833                 mac = &f->mac_info.mac_addr;
4834                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4835                                 ETH_ADDR_LEN);
4836                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4837                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4838                 vsi->mac_num++;
4839
4840                 return ret;
4841         }
4842         rte_memcpy(&filter.mac_addr,
4843                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4844         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4845         return i40e_vsi_add_mac(vsi, &filter);
4846 }
4847
4848 /*
4849  * i40e_vsi_get_bw_config - Query VSI BW Information
4850  * @vsi: the VSI to be queried
4851  *
4852  * Returns 0 on success, negative value on failure
4853  */
4854 static enum i40e_status_code
4855 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4856 {
4857         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4858         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4859         struct i40e_hw *hw = &vsi->adapter->hw;
4860         i40e_status ret;
4861         int i;
4862         uint32_t bw_max;
4863
4864         memset(&bw_config, 0, sizeof(bw_config));
4865         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4866         if (ret != I40E_SUCCESS) {
4867                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4868                             hw->aq.asq_last_status);
4869                 return ret;
4870         }
4871
4872         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4873         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4874                                         &ets_sla_config, NULL);
4875         if (ret != I40E_SUCCESS) {
4876                 PMD_DRV_LOG(ERR,
4877                         "VSI failed to get TC bandwdith configuration %u",
4878                         hw->aq.asq_last_status);
4879                 return ret;
4880         }
4881
4882         /* store and print out BW info */
4883         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4884         vsi->bw_info.bw_max = bw_config.max_bw;
4885         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4886         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4887         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4888                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4889                      I40E_16_BIT_WIDTH);
4890         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4891                 vsi->bw_info.bw_ets_share_credits[i] =
4892                                 ets_sla_config.share_credits[i];
4893                 vsi->bw_info.bw_ets_credits[i] =
4894                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4895                 /* 4 bits per TC, 4th bit is reserved */
4896                 vsi->bw_info.bw_ets_max[i] =
4897                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4898                                   RTE_LEN2MASK(3, uint8_t));
4899                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4900                             vsi->bw_info.bw_ets_share_credits[i]);
4901                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4902                             vsi->bw_info.bw_ets_credits[i]);
4903                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4904                             vsi->bw_info.bw_ets_max[i]);
4905         }
4906
4907         return I40E_SUCCESS;
4908 }
4909
4910 /* i40e_enable_pf_lb
4911  * @pf: pointer to the pf structure
4912  *
4913  * allow loopback on pf
4914  */
4915 static inline void
4916 i40e_enable_pf_lb(struct i40e_pf *pf)
4917 {
4918         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4919         struct i40e_vsi_context ctxt;
4920         int ret;
4921
4922         /* Use the FW API if FW >= v5.0 */
4923         if (hw->aq.fw_maj_ver < 5) {
4924                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4925                 return;
4926         }
4927
4928         memset(&ctxt, 0, sizeof(ctxt));
4929         ctxt.seid = pf->main_vsi_seid;
4930         ctxt.pf_num = hw->pf_id;
4931         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4932         if (ret) {
4933                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4934                             ret, hw->aq.asq_last_status);
4935                 return;
4936         }
4937         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4938         ctxt.info.valid_sections =
4939                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4940         ctxt.info.switch_id |=
4941                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4942
4943         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4944         if (ret)
4945                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4946                             hw->aq.asq_last_status);
4947 }
4948
4949 /* Setup a VSI */
4950 struct i40e_vsi *
4951 i40e_vsi_setup(struct i40e_pf *pf,
4952                enum i40e_vsi_type type,
4953                struct i40e_vsi *uplink_vsi,
4954                uint16_t user_param)
4955 {
4956         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4957         struct i40e_vsi *vsi;
4958         struct i40e_mac_filter_info filter;
4959         int ret;
4960         struct i40e_vsi_context ctxt;
4961         struct ether_addr broadcast =
4962                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4963
4964         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4965             uplink_vsi == NULL) {
4966                 PMD_DRV_LOG(ERR,
4967                         "VSI setup failed, VSI link shouldn't be NULL");
4968                 return NULL;
4969         }
4970
4971         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4972                 PMD_DRV_LOG(ERR,
4973                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4974                 return NULL;
4975         }
4976
4977         /* two situations
4978          * 1.type is not MAIN and uplink vsi is not NULL
4979          * If uplink vsi didn't setup VEB, create one first under veb field
4980          * 2.type is SRIOV and the uplink is NULL
4981          * If floating VEB is NULL, create one veb under floating veb field
4982          */
4983
4984         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4985             uplink_vsi->veb == NULL) {
4986                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4987
4988                 if (uplink_vsi->veb == NULL) {
4989                         PMD_DRV_LOG(ERR, "VEB setup failed");
4990                         return NULL;
4991                 }
4992                 /* set ALLOWLOOPBACk on pf, when veb is created */
4993                 i40e_enable_pf_lb(pf);
4994         }
4995
4996         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4997             pf->main_vsi->floating_veb == NULL) {
4998                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4999
5000                 if (pf->main_vsi->floating_veb == NULL) {
5001                         PMD_DRV_LOG(ERR, "VEB setup failed");
5002                         return NULL;
5003                 }
5004         }
5005
5006         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5007         if (!vsi) {
5008                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5009                 return NULL;
5010         }
5011         TAILQ_INIT(&vsi->mac_list);
5012         vsi->type = type;
5013         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5014         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5015         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5016         vsi->user_param = user_param;
5017         vsi->vlan_anti_spoof_on = 0;
5018         vsi->vlan_filter_on = 0;
5019         /* Allocate queues */
5020         switch (vsi->type) {
5021         case I40E_VSI_MAIN  :
5022                 vsi->nb_qps = pf->lan_nb_qps;
5023                 break;
5024         case I40E_VSI_SRIOV :
5025                 vsi->nb_qps = pf->vf_nb_qps;
5026                 break;
5027         case I40E_VSI_VMDQ2:
5028                 vsi->nb_qps = pf->vmdq_nb_qps;
5029                 break;
5030         case I40E_VSI_FDIR:
5031                 vsi->nb_qps = pf->fdir_nb_qps;
5032                 break;
5033         default:
5034                 goto fail_mem;
5035         }
5036         /*
5037          * The filter status descriptor is reported in rx queue 0,
5038          * while the tx queue for fdir filter programming has no
5039          * such constraints, can be non-zero queues.
5040          * To simplify it, choose FDIR vsi use queue 0 pair.
5041          * To make sure it will use queue 0 pair, queue allocation
5042          * need be done before this function is called
5043          */
5044         if (type != I40E_VSI_FDIR) {
5045                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5046                         if (ret < 0) {
5047                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5048                                                 vsi->seid, ret);
5049                                 goto fail_mem;
5050                         }
5051                         vsi->base_queue = ret;
5052         } else
5053                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5054
5055         /* VF has MSIX interrupt in VF range, don't allocate here */
5056         if (type == I40E_VSI_MAIN) {
5057                 ret = i40e_res_pool_alloc(&pf->msix_pool,
5058                                           RTE_MIN(vsi->nb_qps,
5059                                                   RTE_MAX_RXTX_INTR_VEC_ID));
5060                 if (ret < 0) {
5061                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
5062                                     vsi->seid, ret);
5063                         goto fail_queue_alloc;
5064                 }
5065                 vsi->msix_intr = ret;
5066                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
5067         } else if (type != I40E_VSI_SRIOV) {
5068                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5069                 if (ret < 0) {
5070                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5071                         goto fail_queue_alloc;
5072                 }
5073                 vsi->msix_intr = ret;
5074                 vsi->nb_msix = 1;
5075         } else {
5076                 vsi->msix_intr = 0;
5077                 vsi->nb_msix = 0;
5078         }
5079
5080         /* Add VSI */
5081         if (type == I40E_VSI_MAIN) {
5082                 /* For main VSI, no need to add since it's default one */
5083                 vsi->uplink_seid = pf->mac_seid;
5084                 vsi->seid = pf->main_vsi_seid;
5085                 /* Bind queues with specific MSIX interrupt */
5086                 /**
5087                  * Needs 2 interrupt at least, one for misc cause which will
5088                  * enabled from OS side, Another for queues binding the
5089                  * interrupt from device side only.
5090                  */
5091
5092                 /* Get default VSI parameters from hardware */
5093                 memset(&ctxt, 0, sizeof(ctxt));
5094                 ctxt.seid = vsi->seid;
5095                 ctxt.pf_num = hw->pf_id;
5096                 ctxt.uplink_seid = vsi->uplink_seid;
5097                 ctxt.vf_num = 0;
5098                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5099                 if (ret != I40E_SUCCESS) {
5100                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5101                         goto fail_msix_alloc;
5102                 }
5103                 rte_memcpy(&vsi->info, &ctxt.info,
5104                         sizeof(struct i40e_aqc_vsi_properties_data));
5105                 vsi->vsi_id = ctxt.vsi_number;
5106                 vsi->info.valid_sections = 0;
5107
5108                 /* Configure tc, enabled TC0 only */
5109                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5110                         I40E_SUCCESS) {
5111                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5112                         goto fail_msix_alloc;
5113                 }
5114
5115                 /* TC, queue mapping */
5116                 memset(&ctxt, 0, sizeof(ctxt));
5117                 vsi->info.valid_sections |=
5118                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5119                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5120                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5121                 rte_memcpy(&ctxt.info, &vsi->info,
5122                         sizeof(struct i40e_aqc_vsi_properties_data));
5123                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5124                                                 I40E_DEFAULT_TCMAP);
5125                 if (ret != I40E_SUCCESS) {
5126                         PMD_DRV_LOG(ERR,
5127                                 "Failed to configure TC queue mapping");
5128                         goto fail_msix_alloc;
5129                 }
5130                 ctxt.seid = vsi->seid;
5131                 ctxt.pf_num = hw->pf_id;
5132                 ctxt.uplink_seid = vsi->uplink_seid;
5133                 ctxt.vf_num = 0;
5134
5135                 /* Update VSI parameters */
5136                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5137                 if (ret != I40E_SUCCESS) {
5138                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5139                         goto fail_msix_alloc;
5140                 }
5141
5142                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5143                                                 sizeof(vsi->info.tc_mapping));
5144                 rte_memcpy(&vsi->info.queue_mapping,
5145                                 &ctxt.info.queue_mapping,
5146                         sizeof(vsi->info.queue_mapping));
5147                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5148                 vsi->info.valid_sections = 0;
5149
5150                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5151                                 ETH_ADDR_LEN);
5152
5153                 /**
5154                  * Updating default filter settings are necessary to prevent
5155                  * reception of tagged packets.
5156                  * Some old firmware configurations load a default macvlan
5157                  * filter which accepts both tagged and untagged packets.
5158                  * The updating is to use a normal filter instead if needed.
5159                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5160                  * The firmware with correct configurations load the default
5161                  * macvlan filter which is expected and cannot be removed.
5162                  */
5163                 i40e_update_default_filter_setting(vsi);
5164                 i40e_config_qinq(hw, vsi);
5165         } else if (type == I40E_VSI_SRIOV) {
5166                 memset(&ctxt, 0, sizeof(ctxt));
5167                 /**
5168                  * For other VSI, the uplink_seid equals to uplink VSI's
5169                  * uplink_seid since they share same VEB
5170                  */
5171                 if (uplink_vsi == NULL)
5172                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5173                 else
5174                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5175                 ctxt.pf_num = hw->pf_id;
5176                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5177                 ctxt.uplink_seid = vsi->uplink_seid;
5178                 ctxt.connection_type = 0x1;
5179                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5180
5181                 /* Use the VEB configuration if FW >= v5.0 */
5182                 if (hw->aq.fw_maj_ver >= 5) {
5183                         /* Configure switch ID */
5184                         ctxt.info.valid_sections |=
5185                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5186                         ctxt.info.switch_id =
5187                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5188                 }
5189
5190                 /* Configure port/vlan */
5191                 ctxt.info.valid_sections |=
5192                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5193                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5194                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5195                                                 hw->func_caps.enabled_tcmap);
5196                 if (ret != I40E_SUCCESS) {
5197                         PMD_DRV_LOG(ERR,
5198                                 "Failed to configure TC queue mapping");
5199                         goto fail_msix_alloc;
5200                 }
5201
5202                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5203                 ctxt.info.valid_sections |=
5204                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5205                 /**
5206                  * Since VSI is not created yet, only configure parameter,
5207                  * will add vsi below.
5208                  */
5209
5210                 i40e_config_qinq(hw, vsi);
5211         } else if (type == I40E_VSI_VMDQ2) {
5212                 memset(&ctxt, 0, sizeof(ctxt));
5213                 /*
5214                  * For other VSI, the uplink_seid equals to uplink VSI's
5215                  * uplink_seid since they share same VEB
5216                  */
5217                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5218                 ctxt.pf_num = hw->pf_id;
5219                 ctxt.vf_num = 0;
5220                 ctxt.uplink_seid = vsi->uplink_seid;
5221                 ctxt.connection_type = 0x1;
5222                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5223
5224                 ctxt.info.valid_sections |=
5225                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5226                 /* user_param carries flag to enable loop back */
5227                 if (user_param) {
5228                         ctxt.info.switch_id =
5229                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5230                         ctxt.info.switch_id |=
5231                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5232                 }
5233
5234                 /* Configure port/vlan */
5235                 ctxt.info.valid_sections |=
5236                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5237                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5238                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5239                                                 I40E_DEFAULT_TCMAP);
5240                 if (ret != I40E_SUCCESS) {
5241                         PMD_DRV_LOG(ERR,
5242                                 "Failed to configure TC queue mapping");
5243                         goto fail_msix_alloc;
5244                 }
5245                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5246                 ctxt.info.valid_sections |=
5247                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5248         } else if (type == I40E_VSI_FDIR) {
5249                 memset(&ctxt, 0, sizeof(ctxt));
5250                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5251                 ctxt.pf_num = hw->pf_id;
5252                 ctxt.vf_num = 0;
5253                 ctxt.uplink_seid = vsi->uplink_seid;
5254                 ctxt.connection_type = 0x1;     /* regular data port */
5255                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5256                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5257                                                 I40E_DEFAULT_TCMAP);
5258                 if (ret != I40E_SUCCESS) {
5259                         PMD_DRV_LOG(ERR,
5260                                 "Failed to configure TC queue mapping.");
5261                         goto fail_msix_alloc;
5262                 }
5263                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5264                 ctxt.info.valid_sections |=
5265                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5266         } else {
5267                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5268                 goto fail_msix_alloc;
5269         }
5270
5271         if (vsi->type != I40E_VSI_MAIN) {
5272                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5273                 if (ret != I40E_SUCCESS) {
5274                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5275                                     hw->aq.asq_last_status);
5276                         goto fail_msix_alloc;
5277                 }
5278                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5279                 vsi->info.valid_sections = 0;
5280                 vsi->seid = ctxt.seid;
5281                 vsi->vsi_id = ctxt.vsi_number;
5282                 vsi->sib_vsi_list.vsi = vsi;
5283                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5284                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5285                                           &vsi->sib_vsi_list, list);
5286                 } else {
5287                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5288                                           &vsi->sib_vsi_list, list);
5289                 }
5290         }
5291
5292         /* MAC/VLAN configuration */
5293         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5294         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5295
5296         ret = i40e_vsi_add_mac(vsi, &filter);
5297         if (ret != I40E_SUCCESS) {
5298                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5299                 goto fail_msix_alloc;
5300         }
5301
5302         /* Get VSI BW information */
5303         i40e_vsi_get_bw_config(vsi);
5304         return vsi;
5305 fail_msix_alloc:
5306         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5307 fail_queue_alloc:
5308         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5309 fail_mem:
5310         rte_free(vsi);
5311         return NULL;
5312 }
5313
5314 /* Configure vlan filter on or off */
5315 int
5316 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5317 {
5318         int i, num;
5319         struct i40e_mac_filter *f;
5320         void *temp;
5321         struct i40e_mac_filter_info *mac_filter;
5322         enum rte_mac_filter_type desired_filter;
5323         int ret = I40E_SUCCESS;
5324
5325         if (on) {
5326                 /* Filter to match MAC and VLAN */
5327                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5328         } else {
5329                 /* Filter to match only MAC */
5330                 desired_filter = RTE_MAC_PERFECT_MATCH;
5331         }
5332
5333         num = vsi->mac_num;
5334
5335         mac_filter = rte_zmalloc("mac_filter_info_data",
5336                                  num * sizeof(*mac_filter), 0);
5337         if (mac_filter == NULL) {
5338                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5339                 return I40E_ERR_NO_MEMORY;
5340         }
5341
5342         i = 0;
5343
5344         /* Remove all existing mac */
5345         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5346                 mac_filter[i] = f->mac_info;
5347                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5348                 if (ret) {
5349                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5350                                     on ? "enable" : "disable");
5351                         goto DONE;
5352                 }
5353                 i++;
5354         }
5355
5356         /* Override with new filter */
5357         for (i = 0; i < num; i++) {
5358                 mac_filter[i].filter_type = desired_filter;
5359                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5360                 if (ret) {
5361                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5362                                     on ? "enable" : "disable");
5363                         goto DONE;
5364                 }
5365         }
5366
5367 DONE:
5368         rte_free(mac_filter);
5369         return ret;
5370 }
5371
5372 /* Configure vlan stripping on or off */
5373 int
5374 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5375 {
5376         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5377         struct i40e_vsi_context ctxt;
5378         uint8_t vlan_flags;
5379         int ret = I40E_SUCCESS;
5380
5381         /* Check if it has been already on or off */
5382         if (vsi->info.valid_sections &
5383                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5384                 if (on) {
5385                         if ((vsi->info.port_vlan_flags &
5386                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5387                                 return 0; /* already on */
5388                 } else {
5389                         if ((vsi->info.port_vlan_flags &
5390                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5391                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5392                                 return 0; /* already off */
5393                 }
5394         }
5395
5396         if (on)
5397                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5398         else
5399                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5400         vsi->info.valid_sections =
5401                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5402         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5403         vsi->info.port_vlan_flags |= vlan_flags;
5404         ctxt.seid = vsi->seid;
5405         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5406         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5407         if (ret)
5408                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5409                             on ? "enable" : "disable");
5410
5411         return ret;
5412 }
5413
5414 static int
5415 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5416 {
5417         struct rte_eth_dev_data *data = dev->data;
5418         int ret;
5419         int mask = 0;
5420
5421         /* Apply vlan offload setting */
5422         mask = ETH_VLAN_STRIP_MASK |
5423                ETH_VLAN_FILTER_MASK |
5424                ETH_VLAN_EXTEND_MASK;
5425         ret = i40e_vlan_offload_set(dev, mask);
5426         if (ret) {
5427                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5428                 return ret;
5429         }
5430
5431         /* Apply pvid setting */
5432         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5433                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5434         if (ret)
5435                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5436
5437         return ret;
5438 }
5439
5440 static int
5441 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5442 {
5443         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5444
5445         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5446 }
5447
5448 static int
5449 i40e_update_flow_control(struct i40e_hw *hw)
5450 {
5451 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5452         struct i40e_link_status link_status;
5453         uint32_t rxfc = 0, txfc = 0, reg;
5454         uint8_t an_info;
5455         int ret;
5456
5457         memset(&link_status, 0, sizeof(link_status));
5458         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5459         if (ret != I40E_SUCCESS) {
5460                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5461                 goto write_reg; /* Disable flow control */
5462         }
5463
5464         an_info = hw->phy.link_info.an_info;
5465         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5466                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5467                 ret = I40E_ERR_NOT_READY;
5468                 goto write_reg; /* Disable flow control */
5469         }
5470         /**
5471          * If link auto negotiation is enabled, flow control needs to
5472          * be configured according to it
5473          */
5474         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5475         case I40E_LINK_PAUSE_RXTX:
5476                 rxfc = 1;
5477                 txfc = 1;
5478                 hw->fc.current_mode = I40E_FC_FULL;
5479                 break;
5480         case I40E_AQ_LINK_PAUSE_RX:
5481                 rxfc = 1;
5482                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5483                 break;
5484         case I40E_AQ_LINK_PAUSE_TX:
5485                 txfc = 1;
5486                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5487                 break;
5488         default:
5489                 hw->fc.current_mode = I40E_FC_NONE;
5490                 break;
5491         }
5492
5493 write_reg:
5494         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5495                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5496         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5497         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5498         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5499         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5500
5501         return ret;
5502 }
5503
5504 /* PF setup */
5505 static int
5506 i40e_pf_setup(struct i40e_pf *pf)
5507 {
5508         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5509         struct i40e_filter_control_settings settings;
5510         struct i40e_vsi *vsi;
5511         int ret;
5512
5513         /* Clear all stats counters */
5514         pf->offset_loaded = FALSE;
5515         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5516         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5517         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5518         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5519
5520         ret = i40e_pf_get_switch_config(pf);
5521         if (ret != I40E_SUCCESS) {
5522                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5523                 return ret;
5524         }
5525         if (pf->flags & I40E_FLAG_FDIR) {
5526                 /* make queue allocated first, let FDIR use queue pair 0*/
5527                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5528                 if (ret != I40E_FDIR_QUEUE_ID) {
5529                         PMD_DRV_LOG(ERR,
5530                                 "queue allocation fails for FDIR: ret =%d",
5531                                 ret);
5532                         pf->flags &= ~I40E_FLAG_FDIR;
5533                 }
5534         }
5535         /*  main VSI setup */
5536         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5537         if (!vsi) {
5538                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5539                 return I40E_ERR_NOT_READY;
5540         }
5541         pf->main_vsi = vsi;
5542
5543         /* Configure filter control */
5544         memset(&settings, 0, sizeof(settings));
5545         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5546                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5547         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5548                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5549         else {
5550                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5551                         hw->func_caps.rss_table_size);
5552                 return I40E_ERR_PARAM;
5553         }
5554         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5555                 hw->func_caps.rss_table_size);
5556         pf->hash_lut_size = hw->func_caps.rss_table_size;
5557
5558         /* Enable ethtype and macvlan filters */
5559         settings.enable_ethtype = TRUE;
5560         settings.enable_macvlan = TRUE;
5561         ret = i40e_set_filter_control(hw, &settings);
5562         if (ret)
5563                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5564                                                                 ret);
5565
5566         /* Update flow control according to the auto negotiation */
5567         i40e_update_flow_control(hw);
5568
5569         return I40E_SUCCESS;
5570 }
5571
5572 int
5573 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5574 {
5575         uint32_t reg;
5576         uint16_t j;
5577
5578         /**
5579          * Set or clear TX Queue Disable flags,
5580          * which is required by hardware.
5581          */
5582         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5583         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5584
5585         /* Wait until the request is finished */
5586         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5587                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5588                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5589                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5590                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5591                                                         & 0x1))) {
5592                         break;
5593                 }
5594         }
5595         if (on) {
5596                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5597                         return I40E_SUCCESS; /* already on, skip next steps */
5598
5599                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5600                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5601         } else {
5602                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5603                         return I40E_SUCCESS; /* already off, skip next steps */
5604                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5605         }
5606         /* Write the register */
5607         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5608         /* Check the result */
5609         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5610                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5611                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5612                 if (on) {
5613                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5614                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5615                                 break;
5616                 } else {
5617                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5618                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5619                                 break;
5620                 }
5621         }
5622         /* Check if it is timeout */
5623         if (j >= I40E_CHK_Q_ENA_COUNT) {
5624                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5625                             (on ? "enable" : "disable"), q_idx);
5626                 return I40E_ERR_TIMEOUT;
5627         }
5628
5629         return I40E_SUCCESS;
5630 }
5631
5632 /* Swith on or off the tx queues */
5633 static int
5634 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5635 {
5636         struct rte_eth_dev_data *dev_data = pf->dev_data;
5637         struct i40e_tx_queue *txq;
5638         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5639         uint16_t i;
5640         int ret;
5641
5642         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5643                 txq = dev_data->tx_queues[i];
5644                 /* Don't operate the queue if not configured or
5645                  * if starting only per queue */
5646                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5647                         continue;
5648                 if (on)
5649                         ret = i40e_dev_tx_queue_start(dev, i);
5650                 else
5651                         ret = i40e_dev_tx_queue_stop(dev, i);
5652                 if ( ret != I40E_SUCCESS)
5653                         return ret;
5654         }
5655
5656         return I40E_SUCCESS;
5657 }
5658
5659 int
5660 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5661 {
5662         uint32_t reg;
5663         uint16_t j;
5664
5665         /* Wait until the request is finished */
5666         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5667                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5668                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5669                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5670                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5671                         break;
5672         }
5673
5674         if (on) {
5675                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5676                         return I40E_SUCCESS; /* Already on, skip next steps */
5677                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5678         } else {
5679                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5680                         return I40E_SUCCESS; /* Already off, skip next steps */
5681                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5682         }
5683
5684         /* Write the register */
5685         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5686         /* Check the result */
5687         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5688                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5689                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5690                 if (on) {
5691                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5692                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5693                                 break;
5694                 } else {
5695                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5696                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5697                                 break;
5698                 }
5699         }
5700
5701         /* Check if it is timeout */
5702         if (j >= I40E_CHK_Q_ENA_COUNT) {
5703                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5704                             (on ? "enable" : "disable"), q_idx);
5705                 return I40E_ERR_TIMEOUT;
5706         }
5707
5708         return I40E_SUCCESS;
5709 }
5710 /* Switch on or off the rx queues */
5711 static int
5712 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5713 {
5714         struct rte_eth_dev_data *dev_data = pf->dev_data;
5715         struct i40e_rx_queue *rxq;
5716         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5717         uint16_t i;
5718         int ret;
5719
5720         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5721                 rxq = dev_data->rx_queues[i];
5722                 /* Don't operate the queue if not configured or
5723                  * if starting only per queue */
5724                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5725                         continue;
5726                 if (on)
5727                         ret = i40e_dev_rx_queue_start(dev, i);
5728                 else
5729                         ret = i40e_dev_rx_queue_stop(dev, i);
5730                 if (ret != I40E_SUCCESS)
5731                         return ret;
5732         }
5733
5734         return I40E_SUCCESS;
5735 }
5736
5737 /* Switch on or off all the rx/tx queues */
5738 int
5739 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5740 {
5741         int ret;
5742
5743         if (on) {
5744                 /* enable rx queues before enabling tx queues */
5745                 ret = i40e_dev_switch_rx_queues(pf, on);
5746                 if (ret) {
5747                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5748                         return ret;
5749                 }
5750                 ret = i40e_dev_switch_tx_queues(pf, on);
5751         } else {
5752                 /* Stop tx queues before stopping rx queues */
5753                 ret = i40e_dev_switch_tx_queues(pf, on);
5754                 if (ret) {
5755                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5756                         return ret;
5757                 }
5758                 ret = i40e_dev_switch_rx_queues(pf, on);
5759         }
5760
5761         return ret;
5762 }
5763
5764 /* Initialize VSI for TX */
5765 static int
5766 i40e_dev_tx_init(struct i40e_pf *pf)
5767 {
5768         struct rte_eth_dev_data *data = pf->dev_data;
5769         uint16_t i;
5770         uint32_t ret = I40E_SUCCESS;
5771         struct i40e_tx_queue *txq;
5772
5773         for (i = 0; i < data->nb_tx_queues; i++) {
5774                 txq = data->tx_queues[i];
5775                 if (!txq || !txq->q_set)
5776                         continue;
5777                 ret = i40e_tx_queue_init(txq);
5778                 if (ret != I40E_SUCCESS)
5779                         break;
5780         }
5781         if (ret == I40E_SUCCESS)
5782                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5783                                      ->eth_dev);
5784
5785         return ret;
5786 }
5787
5788 /* Initialize VSI for RX */
5789 static int
5790 i40e_dev_rx_init(struct i40e_pf *pf)
5791 {
5792         struct rte_eth_dev_data *data = pf->dev_data;
5793         int ret = I40E_SUCCESS;
5794         uint16_t i;
5795         struct i40e_rx_queue *rxq;
5796
5797         i40e_pf_config_mq_rx(pf);
5798         for (i = 0; i < data->nb_rx_queues; i++) {
5799                 rxq = data->rx_queues[i];
5800                 if (!rxq || !rxq->q_set)
5801                         continue;
5802
5803                 ret = i40e_rx_queue_init(rxq);
5804                 if (ret != I40E_SUCCESS) {
5805                         PMD_DRV_LOG(ERR,
5806                                 "Failed to do RX queue initialization");
5807                         break;
5808                 }
5809         }
5810         if (ret == I40E_SUCCESS)
5811                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5812                                      ->eth_dev);
5813
5814         return ret;
5815 }
5816
5817 static int
5818 i40e_dev_rxtx_init(struct i40e_pf *pf)
5819 {
5820         int err;
5821
5822         err = i40e_dev_tx_init(pf);
5823         if (err) {
5824                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5825                 return err;
5826         }
5827         err = i40e_dev_rx_init(pf);
5828         if (err) {
5829                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5830                 return err;
5831         }
5832
5833         return err;
5834 }
5835
5836 static int
5837 i40e_vmdq_setup(struct rte_eth_dev *dev)
5838 {
5839         struct rte_eth_conf *conf = &dev->data->dev_conf;
5840         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5841         int i, err, conf_vsis, j, loop;
5842         struct i40e_vsi *vsi;
5843         struct i40e_vmdq_info *vmdq_info;
5844         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5845         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5846
5847         /*
5848          * Disable interrupt to avoid message from VF. Furthermore, it will
5849          * avoid race condition in VSI creation/destroy.
5850          */
5851         i40e_pf_disable_irq0(hw);
5852
5853         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5854                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5855                 return -ENOTSUP;
5856         }
5857
5858         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5859         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5860                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5861                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5862                         pf->max_nb_vmdq_vsi);
5863                 return -ENOTSUP;
5864         }
5865
5866         if (pf->vmdq != NULL) {
5867                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5868                 return 0;
5869         }
5870
5871         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5872                                 sizeof(*vmdq_info) * conf_vsis, 0);
5873
5874         if (pf->vmdq == NULL) {
5875                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5876                 return -ENOMEM;
5877         }
5878
5879         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5880
5881         /* Create VMDQ VSI */
5882         for (i = 0; i < conf_vsis; i++) {
5883                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5884                                 vmdq_conf->enable_loop_back);
5885                 if (vsi == NULL) {
5886                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5887                         err = -1;
5888                         goto err_vsi_setup;
5889                 }
5890                 vmdq_info = &pf->vmdq[i];
5891                 vmdq_info->pf = pf;
5892                 vmdq_info->vsi = vsi;
5893         }
5894         pf->nb_cfg_vmdq_vsi = conf_vsis;
5895
5896         /* Configure Vlan */
5897         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5898         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5899                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5900                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5901                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5902                                         vmdq_conf->pool_map[i].vlan_id, j);
5903
5904                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5905                                                 vmdq_conf->pool_map[i].vlan_id);
5906                                 if (err) {
5907                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5908                                         err = -1;
5909                                         goto err_vsi_setup;
5910                                 }
5911                         }
5912                 }
5913         }
5914
5915         i40e_pf_enable_irq0(hw);
5916
5917         return 0;
5918
5919 err_vsi_setup:
5920         for (i = 0; i < conf_vsis; i++)
5921                 if (pf->vmdq[i].vsi == NULL)
5922                         break;
5923                 else
5924                         i40e_vsi_release(pf->vmdq[i].vsi);
5925
5926         rte_free(pf->vmdq);
5927         pf->vmdq = NULL;
5928         i40e_pf_enable_irq0(hw);
5929         return err;
5930 }
5931
5932 static void
5933 i40e_stat_update_32(struct i40e_hw *hw,
5934                    uint32_t reg,
5935                    bool offset_loaded,
5936                    uint64_t *offset,
5937                    uint64_t *stat)
5938 {
5939         uint64_t new_data;
5940
5941         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5942         if (!offset_loaded)
5943                 *offset = new_data;
5944
5945         if (new_data >= *offset)
5946                 *stat = (uint64_t)(new_data - *offset);
5947         else
5948                 *stat = (uint64_t)((new_data +
5949                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5950 }
5951
5952 static void
5953 i40e_stat_update_48(struct i40e_hw *hw,
5954                    uint32_t hireg,
5955                    uint32_t loreg,
5956                    bool offset_loaded,
5957                    uint64_t *offset,
5958                    uint64_t *stat)
5959 {
5960         uint64_t new_data;
5961
5962         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5963         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5964                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5965
5966         if (!offset_loaded)
5967                 *offset = new_data;
5968
5969         if (new_data >= *offset)
5970                 *stat = new_data - *offset;
5971         else
5972                 *stat = (uint64_t)((new_data +
5973                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5974
5975         *stat &= I40E_48_BIT_MASK;
5976 }
5977
5978 /* Disable IRQ0 */
5979 void
5980 i40e_pf_disable_irq0(struct i40e_hw *hw)
5981 {
5982         /* Disable all interrupt types */
5983         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5984         I40E_WRITE_FLUSH(hw);
5985 }
5986
5987 /* Enable IRQ0 */
5988 void
5989 i40e_pf_enable_irq0(struct i40e_hw *hw)
5990 {
5991         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5992                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5993                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5994                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5995         I40E_WRITE_FLUSH(hw);
5996 }
5997
5998 static void
5999 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6000 {
6001         /* read pending request and disable first */
6002         i40e_pf_disable_irq0(hw);
6003         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6004         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6005                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6006
6007         if (no_queue)
6008                 /* Link no queues with irq0 */
6009                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6010                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6011 }
6012
6013 static void
6014 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6015 {
6016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6017         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6018         int i;
6019         uint16_t abs_vf_id;
6020         uint32_t index, offset, val;
6021
6022         if (!pf->vfs)
6023                 return;
6024         /**
6025          * Try to find which VF trigger a reset, use absolute VF id to access
6026          * since the reg is global register.
6027          */
6028         for (i = 0; i < pf->vf_num; i++) {
6029                 abs_vf_id = hw->func_caps.vf_base_id + i;
6030                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6031                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6032                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6033                 /* VFR event occurred */
6034                 if (val & (0x1 << offset)) {
6035                         int ret;
6036
6037                         /* Clear the event first */
6038                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6039                                                         (0x1 << offset));
6040                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6041                         /**
6042                          * Only notify a VF reset event occurred,
6043                          * don't trigger another SW reset
6044                          */
6045                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6046                         if (ret != I40E_SUCCESS)
6047                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6048                 }
6049         }
6050 }
6051
6052 static void
6053 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6054 {
6055         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6056         int i;
6057
6058         for (i = 0; i < pf->vf_num; i++)
6059                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6060 }
6061
6062 static void
6063 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6064 {
6065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6066         struct i40e_arq_event_info info;
6067         uint16_t pending, opcode;
6068         int ret;
6069
6070         info.buf_len = I40E_AQ_BUF_SZ;
6071         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6072         if (!info.msg_buf) {
6073                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6074                 return;
6075         }
6076
6077         pending = 1;
6078         while (pending) {
6079                 ret = i40e_clean_arq_element(hw, &info, &pending);
6080
6081                 if (ret != I40E_SUCCESS) {
6082                         PMD_DRV_LOG(INFO,
6083                                 "Failed to read msg from AdminQ, aq_err: %u",
6084                                 hw->aq.asq_last_status);
6085                         break;
6086                 }
6087                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6088
6089                 switch (opcode) {
6090                 case i40e_aqc_opc_send_msg_to_pf:
6091                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6092                         i40e_pf_host_handle_vf_msg(dev,
6093                                         rte_le_to_cpu_16(info.desc.retval),
6094                                         rte_le_to_cpu_32(info.desc.cookie_high),
6095                                         rte_le_to_cpu_32(info.desc.cookie_low),
6096                                         info.msg_buf,
6097                                         info.msg_len);
6098                         break;
6099                 case i40e_aqc_opc_get_link_status:
6100                         ret = i40e_dev_link_update(dev, 0);
6101                         if (!ret)
6102                                 _rte_eth_dev_callback_process(dev,
6103                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
6104                         break;
6105                 default:
6106                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6107                                     opcode);
6108                         break;
6109                 }
6110         }
6111         rte_free(info.msg_buf);
6112 }
6113
6114 /**
6115  * Interrupt handler triggered by NIC  for handling
6116  * specific interrupt.
6117  *
6118  * @param handle
6119  *  Pointer to interrupt handle.
6120  * @param param
6121  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6122  *
6123  * @return
6124  *  void
6125  */
6126 static void
6127 i40e_dev_interrupt_handler(void *param)
6128 {
6129         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6130         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6131         uint32_t icr0;
6132
6133         /* Disable interrupt */
6134         i40e_pf_disable_irq0(hw);
6135
6136         /* read out interrupt causes */
6137         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6138
6139         /* No interrupt event indicated */
6140         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6141                 PMD_DRV_LOG(INFO, "No interrupt event");
6142                 goto done;
6143         }
6144         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6145                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6146         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6147                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6148         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6149                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6150         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6151                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6152         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6153                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6154         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6155                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6156         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6157                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6158
6159         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6160                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6161                 i40e_dev_handle_vfr_event(dev);
6162         }
6163         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6164                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6165                 i40e_dev_handle_aq_msg(dev);
6166         }
6167
6168 done:
6169         /* Enable interrupt */
6170         i40e_pf_enable_irq0(hw);
6171         rte_intr_enable(dev->intr_handle);
6172 }
6173
6174 int
6175 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6176                          struct i40e_macvlan_filter *filter,
6177                          int total)
6178 {
6179         int ele_num, ele_buff_size;
6180         int num, actual_num, i;
6181         uint16_t flags;
6182         int ret = I40E_SUCCESS;
6183         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6184         struct i40e_aqc_add_macvlan_element_data *req_list;
6185
6186         if (filter == NULL  || total == 0)
6187                 return I40E_ERR_PARAM;
6188         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6189         ele_buff_size = hw->aq.asq_buf_size;
6190
6191         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6192         if (req_list == NULL) {
6193                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6194                 return I40E_ERR_NO_MEMORY;
6195         }
6196
6197         num = 0;
6198         do {
6199                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6200                 memset(req_list, 0, ele_buff_size);
6201
6202                 for (i = 0; i < actual_num; i++) {
6203                         rte_memcpy(req_list[i].mac_addr,
6204                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6205                         req_list[i].vlan_tag =
6206                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6207
6208                         switch (filter[num + i].filter_type) {
6209                         case RTE_MAC_PERFECT_MATCH:
6210                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6211                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6212                                 break;
6213                         case RTE_MACVLAN_PERFECT_MATCH:
6214                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6215                                 break;
6216                         case RTE_MAC_HASH_MATCH:
6217                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6218                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6219                                 break;
6220                         case RTE_MACVLAN_HASH_MATCH:
6221                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6222                                 break;
6223                         default:
6224                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6225                                 ret = I40E_ERR_PARAM;
6226                                 goto DONE;
6227                         }
6228
6229                         req_list[i].queue_number = 0;
6230
6231                         req_list[i].flags = rte_cpu_to_le_16(flags);
6232                 }
6233
6234                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6235                                                 actual_num, NULL);
6236                 if (ret != I40E_SUCCESS) {
6237                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6238                         goto DONE;
6239                 }
6240                 num += actual_num;
6241         } while (num < total);
6242
6243 DONE:
6244         rte_free(req_list);
6245         return ret;
6246 }
6247
6248 int
6249 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6250                             struct i40e_macvlan_filter *filter,
6251                             int total)
6252 {
6253         int ele_num, ele_buff_size;
6254         int num, actual_num, i;
6255         uint16_t flags;
6256         int ret = I40E_SUCCESS;
6257         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6258         struct i40e_aqc_remove_macvlan_element_data *req_list;
6259
6260         if (filter == NULL  || total == 0)
6261                 return I40E_ERR_PARAM;
6262
6263         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6264         ele_buff_size = hw->aq.asq_buf_size;
6265
6266         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6267         if (req_list == NULL) {
6268                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6269                 return I40E_ERR_NO_MEMORY;
6270         }
6271
6272         num = 0;
6273         do {
6274                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6275                 memset(req_list, 0, ele_buff_size);
6276
6277                 for (i = 0; i < actual_num; i++) {
6278                         rte_memcpy(req_list[i].mac_addr,
6279                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6280                         req_list[i].vlan_tag =
6281                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6282
6283                         switch (filter[num + i].filter_type) {
6284                         case RTE_MAC_PERFECT_MATCH:
6285                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6286                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6287                                 break;
6288                         case RTE_MACVLAN_PERFECT_MATCH:
6289                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6290                                 break;
6291                         case RTE_MAC_HASH_MATCH:
6292                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6293                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6294                                 break;
6295                         case RTE_MACVLAN_HASH_MATCH:
6296                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6297                                 break;
6298                         default:
6299                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6300                                 ret = I40E_ERR_PARAM;
6301                                 goto DONE;
6302                         }
6303                         req_list[i].flags = rte_cpu_to_le_16(flags);
6304                 }
6305
6306                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6307                                                 actual_num, NULL);
6308                 if (ret != I40E_SUCCESS) {
6309                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6310                         goto DONE;
6311                 }
6312                 num += actual_num;
6313         } while (num < total);
6314
6315 DONE:
6316         rte_free(req_list);
6317         return ret;
6318 }
6319
6320 /* Find out specific MAC filter */
6321 static struct i40e_mac_filter *
6322 i40e_find_mac_filter(struct i40e_vsi *vsi,
6323                          struct ether_addr *macaddr)
6324 {
6325         struct i40e_mac_filter *f;
6326
6327         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6328                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6329                         return f;
6330         }
6331
6332         return NULL;
6333 }
6334
6335 static bool
6336 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6337                          uint16_t vlan_id)
6338 {
6339         uint32_t vid_idx, vid_bit;
6340
6341         if (vlan_id > ETH_VLAN_ID_MAX)
6342                 return 0;
6343
6344         vid_idx = I40E_VFTA_IDX(vlan_id);
6345         vid_bit = I40E_VFTA_BIT(vlan_id);
6346
6347         if (vsi->vfta[vid_idx] & vid_bit)
6348                 return 1;
6349         else
6350                 return 0;
6351 }
6352
6353 static void
6354 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6355                        uint16_t vlan_id, bool on)
6356 {
6357         uint32_t vid_idx, vid_bit;
6358
6359         vid_idx = I40E_VFTA_IDX(vlan_id);
6360         vid_bit = I40E_VFTA_BIT(vlan_id);
6361
6362         if (on)
6363                 vsi->vfta[vid_idx] |= vid_bit;
6364         else
6365                 vsi->vfta[vid_idx] &= ~vid_bit;
6366 }
6367
6368 void
6369 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6370                      uint16_t vlan_id, bool on)
6371 {
6372         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6373         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6374         int ret;
6375
6376         if (vlan_id > ETH_VLAN_ID_MAX)
6377                 return;
6378
6379         i40e_store_vlan_filter(vsi, vlan_id, on);
6380
6381         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6382                 return;
6383
6384         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6385
6386         if (on) {
6387                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6388                                        &vlan_data, 1, NULL);
6389                 if (ret != I40E_SUCCESS)
6390                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6391         } else {
6392                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6393                                           &vlan_data, 1, NULL);
6394                 if (ret != I40E_SUCCESS)
6395                         PMD_DRV_LOG(ERR,
6396                                     "Failed to remove vlan filter");
6397         }
6398 }
6399
6400 /**
6401  * Find all vlan options for specific mac addr,
6402  * return with actual vlan found.
6403  */
6404 int
6405 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6406                            struct i40e_macvlan_filter *mv_f,
6407                            int num, struct ether_addr *addr)
6408 {
6409         int i;
6410         uint32_t j, k;
6411
6412         /**
6413          * Not to use i40e_find_vlan_filter to decrease the loop time,
6414          * although the code looks complex.
6415           */
6416         if (num < vsi->vlan_num)
6417                 return I40E_ERR_PARAM;
6418
6419         i = 0;
6420         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6421                 if (vsi->vfta[j]) {
6422                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6423                                 if (vsi->vfta[j] & (1 << k)) {
6424                                         if (i > num - 1) {
6425                                                 PMD_DRV_LOG(ERR,
6426                                                         "vlan number doesn't match");
6427                                                 return I40E_ERR_PARAM;
6428                                         }
6429                                         rte_memcpy(&mv_f[i].macaddr,
6430                                                         addr, ETH_ADDR_LEN);
6431                                         mv_f[i].vlan_id =
6432                                                 j * I40E_UINT32_BIT_SIZE + k;
6433                                         i++;
6434                                 }
6435                         }
6436                 }
6437         }
6438         return I40E_SUCCESS;
6439 }
6440
6441 static inline int
6442 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6443                            struct i40e_macvlan_filter *mv_f,
6444                            int num,
6445                            uint16_t vlan)
6446 {
6447         int i = 0;
6448         struct i40e_mac_filter *f;
6449
6450         if (num < vsi->mac_num)
6451                 return I40E_ERR_PARAM;
6452
6453         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6454                 if (i > num - 1) {
6455                         PMD_DRV_LOG(ERR, "buffer number not match");
6456                         return I40E_ERR_PARAM;
6457                 }
6458                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6459                                 ETH_ADDR_LEN);
6460                 mv_f[i].vlan_id = vlan;
6461                 mv_f[i].filter_type = f->mac_info.filter_type;
6462                 i++;
6463         }
6464
6465         return I40E_SUCCESS;
6466 }
6467
6468 static int
6469 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6470 {
6471         int i, j, num;
6472         struct i40e_mac_filter *f;
6473         struct i40e_macvlan_filter *mv_f;
6474         int ret = I40E_SUCCESS;
6475
6476         if (vsi == NULL || vsi->mac_num == 0)
6477                 return I40E_ERR_PARAM;
6478
6479         /* Case that no vlan is set */
6480         if (vsi->vlan_num == 0)
6481                 num = vsi->mac_num;
6482         else
6483                 num = vsi->mac_num * vsi->vlan_num;
6484
6485         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6486         if (mv_f == NULL) {
6487                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6488                 return I40E_ERR_NO_MEMORY;
6489         }
6490
6491         i = 0;
6492         if (vsi->vlan_num == 0) {
6493                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6494                         rte_memcpy(&mv_f[i].macaddr,
6495                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6496                         mv_f[i].filter_type = f->mac_info.filter_type;
6497                         mv_f[i].vlan_id = 0;
6498                         i++;
6499                 }
6500         } else {
6501                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6502                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6503                                         vsi->vlan_num, &f->mac_info.mac_addr);
6504                         if (ret != I40E_SUCCESS)
6505                                 goto DONE;
6506                         for (j = i; j < i + vsi->vlan_num; j++)
6507                                 mv_f[j].filter_type = f->mac_info.filter_type;
6508                         i += vsi->vlan_num;
6509                 }
6510         }
6511
6512         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6513 DONE:
6514         rte_free(mv_f);
6515
6516         return ret;
6517 }
6518
6519 int
6520 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6521 {
6522         struct i40e_macvlan_filter *mv_f;
6523         int mac_num;
6524         int ret = I40E_SUCCESS;
6525
6526         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6527                 return I40E_ERR_PARAM;
6528
6529         /* If it's already set, just return */
6530         if (i40e_find_vlan_filter(vsi,vlan))
6531                 return I40E_SUCCESS;
6532
6533         mac_num = vsi->mac_num;
6534
6535         if (mac_num == 0) {
6536                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6537                 return I40E_ERR_PARAM;
6538         }
6539
6540         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6541
6542         if (mv_f == NULL) {
6543                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6544                 return I40E_ERR_NO_MEMORY;
6545         }
6546
6547         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6548
6549         if (ret != I40E_SUCCESS)
6550                 goto DONE;
6551
6552         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6553
6554         if (ret != I40E_SUCCESS)
6555                 goto DONE;
6556
6557         i40e_set_vlan_filter(vsi, vlan, 1);
6558
6559         vsi->vlan_num++;
6560         ret = I40E_SUCCESS;
6561 DONE:
6562         rte_free(mv_f);
6563         return ret;
6564 }
6565
6566 int
6567 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6568 {
6569         struct i40e_macvlan_filter *mv_f;
6570         int mac_num;
6571         int ret = I40E_SUCCESS;
6572
6573         /**
6574          * Vlan 0 is the generic filter for untagged packets
6575          * and can't be removed.
6576          */
6577         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6578                 return I40E_ERR_PARAM;
6579
6580         /* If can't find it, just return */
6581         if (!i40e_find_vlan_filter(vsi, vlan))
6582                 return I40E_ERR_PARAM;
6583
6584         mac_num = vsi->mac_num;
6585
6586         if (mac_num == 0) {
6587                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6588                 return I40E_ERR_PARAM;
6589         }
6590
6591         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6592
6593         if (mv_f == NULL) {
6594                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6595                 return I40E_ERR_NO_MEMORY;
6596         }
6597
6598         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6599
6600         if (ret != I40E_SUCCESS)
6601                 goto DONE;
6602
6603         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6604
6605         if (ret != I40E_SUCCESS)
6606                 goto DONE;
6607
6608         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6609         if (vsi->vlan_num == 1) {
6610                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6611                 if (ret != I40E_SUCCESS)
6612                         goto DONE;
6613
6614                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6615                 if (ret != I40E_SUCCESS)
6616                         goto DONE;
6617         }
6618
6619         i40e_set_vlan_filter(vsi, vlan, 0);
6620
6621         vsi->vlan_num--;
6622         ret = I40E_SUCCESS;
6623 DONE:
6624         rte_free(mv_f);
6625         return ret;
6626 }
6627
6628 int
6629 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6630 {
6631         struct i40e_mac_filter *f;
6632         struct i40e_macvlan_filter *mv_f;
6633         int i, vlan_num = 0;
6634         int ret = I40E_SUCCESS;
6635
6636         /* If it's add and we've config it, return */
6637         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6638         if (f != NULL)
6639                 return I40E_SUCCESS;
6640         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6641                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6642
6643                 /**
6644                  * If vlan_num is 0, that's the first time to add mac,
6645                  * set mask for vlan_id 0.
6646                  */
6647                 if (vsi->vlan_num == 0) {
6648                         i40e_set_vlan_filter(vsi, 0, 1);
6649                         vsi->vlan_num = 1;
6650                 }
6651                 vlan_num = vsi->vlan_num;
6652         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6653                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6654                 vlan_num = 1;
6655
6656         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6657         if (mv_f == NULL) {
6658                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6659                 return I40E_ERR_NO_MEMORY;
6660         }
6661
6662         for (i = 0; i < vlan_num; i++) {
6663                 mv_f[i].filter_type = mac_filter->filter_type;
6664                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6665                                 ETH_ADDR_LEN);
6666         }
6667
6668         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6669                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6670                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6671                                         &mac_filter->mac_addr);
6672                 if (ret != I40E_SUCCESS)
6673                         goto DONE;
6674         }
6675
6676         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6677         if (ret != I40E_SUCCESS)
6678                 goto DONE;
6679
6680         /* Add the mac addr into mac list */
6681         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6682         if (f == NULL) {
6683                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6684                 ret = I40E_ERR_NO_MEMORY;
6685                 goto DONE;
6686         }
6687         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6688                         ETH_ADDR_LEN);
6689         f->mac_info.filter_type = mac_filter->filter_type;
6690         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6691         vsi->mac_num++;
6692
6693         ret = I40E_SUCCESS;
6694 DONE:
6695         rte_free(mv_f);
6696
6697         return ret;
6698 }
6699
6700 int
6701 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6702 {
6703         struct i40e_mac_filter *f;
6704         struct i40e_macvlan_filter *mv_f;
6705         int i, vlan_num;
6706         enum rte_mac_filter_type filter_type;
6707         int ret = I40E_SUCCESS;
6708
6709         /* Can't find it, return an error */
6710         f = i40e_find_mac_filter(vsi, addr);
6711         if (f == NULL)
6712                 return I40E_ERR_PARAM;
6713
6714         vlan_num = vsi->vlan_num;
6715         filter_type = f->mac_info.filter_type;
6716         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6717                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6718                 if (vlan_num == 0) {
6719                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6720                         return I40E_ERR_PARAM;
6721                 }
6722         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6723                         filter_type == RTE_MAC_HASH_MATCH)
6724                 vlan_num = 1;
6725
6726         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6727         if (mv_f == NULL) {
6728                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6729                 return I40E_ERR_NO_MEMORY;
6730         }
6731
6732         for (i = 0; i < vlan_num; i++) {
6733                 mv_f[i].filter_type = filter_type;
6734                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6735                                 ETH_ADDR_LEN);
6736         }
6737         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6738                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6739                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6740                 if (ret != I40E_SUCCESS)
6741                         goto DONE;
6742         }
6743
6744         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6745         if (ret != I40E_SUCCESS)
6746                 goto DONE;
6747
6748         /* Remove the mac addr into mac list */
6749         TAILQ_REMOVE(&vsi->mac_list, f, next);
6750         rte_free(f);
6751         vsi->mac_num--;
6752
6753         ret = I40E_SUCCESS;
6754 DONE:
6755         rte_free(mv_f);
6756         return ret;
6757 }
6758
6759 /* Configure hash enable flags for RSS */
6760 uint64_t
6761 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6762 {
6763         uint64_t hena = 0;
6764         int i;
6765
6766         if (!flags)
6767                 return hena;
6768
6769         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6770                 if (flags & (1ULL << i))
6771                         hena |= adapter->pctypes_tbl[i];
6772         }
6773
6774         return hena;
6775 }
6776
6777 /* Parse the hash enable flags */
6778 uint64_t
6779 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6780 {
6781         uint64_t rss_hf = 0;
6782
6783         if (!flags)
6784                 return rss_hf;
6785         int i;
6786
6787         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6788                 if (flags & adapter->pctypes_tbl[i])
6789                         rss_hf |= (1ULL << i);
6790         }
6791         return rss_hf;
6792 }
6793
6794 /* Disable RSS */
6795 static void
6796 i40e_pf_disable_rss(struct i40e_pf *pf)
6797 {
6798         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6799
6800         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6801         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6802         I40E_WRITE_FLUSH(hw);
6803 }
6804
6805 static int
6806 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6807 {
6808         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6809         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6810         int ret = 0;
6811
6812         if (!key || key_len == 0) {
6813                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6814                 return 0;
6815         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6816                 sizeof(uint32_t)) {
6817                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6818                 return -EINVAL;
6819         }
6820
6821         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6822                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6823                         (struct i40e_aqc_get_set_rss_key_data *)key;
6824
6825                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6826                 if (ret)
6827                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6828         } else {
6829                 uint32_t *hash_key = (uint32_t *)key;
6830                 uint16_t i;
6831
6832                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6833                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6834                 I40E_WRITE_FLUSH(hw);
6835         }
6836
6837         return ret;
6838 }
6839
6840 static int
6841 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6842 {
6843         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6844         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6845         int ret;
6846
6847         if (!key || !key_len)
6848                 return -EINVAL;
6849
6850         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6851                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6852                         (struct i40e_aqc_get_set_rss_key_data *)key);
6853                 if (ret) {
6854                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6855                         return ret;
6856                 }
6857         } else {
6858                 uint32_t *key_dw = (uint32_t *)key;
6859                 uint16_t i;
6860
6861                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6862                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6863         }
6864         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6865
6866         return 0;
6867 }
6868
6869 static int
6870 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6871 {
6872         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6873         uint64_t hena;
6874         int ret;
6875
6876         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6877                                rss_conf->rss_key_len);
6878         if (ret)
6879                 return ret;
6880
6881         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6882         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6883         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6884         I40E_WRITE_FLUSH(hw);
6885
6886         return 0;
6887 }
6888
6889 static int
6890 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6891                          struct rte_eth_rss_conf *rss_conf)
6892 {
6893         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6894         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6895         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6896         uint64_t hena;
6897
6898         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6899         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6900
6901         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6902                 if (rss_hf != 0) /* Enable RSS */
6903                         return -EINVAL;
6904                 return 0; /* Nothing to do */
6905         }
6906         /* RSS enabled */
6907         if (rss_hf == 0) /* Disable RSS */
6908                 return -EINVAL;
6909
6910         return i40e_hw_rss_hash_set(pf, rss_conf);
6911 }
6912
6913 static int
6914 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6915                            struct rte_eth_rss_conf *rss_conf)
6916 {
6917         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6919         uint64_t hena;
6920
6921         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6922                          &rss_conf->rss_key_len);
6923
6924         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6925         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6926         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6927
6928         return 0;
6929 }
6930
6931 static int
6932 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6933 {
6934         switch (filter_type) {
6935         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6936                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6937                 break;
6938         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6939                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6940                 break;
6941         case RTE_TUNNEL_FILTER_IMAC_TENID:
6942                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6943                 break;
6944         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6945                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6946                 break;
6947         case ETH_TUNNEL_FILTER_IMAC:
6948                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6949                 break;
6950         case ETH_TUNNEL_FILTER_OIP:
6951                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6952                 break;
6953         case ETH_TUNNEL_FILTER_IIP:
6954                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6955                 break;
6956         default:
6957                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6958                 return -EINVAL;
6959         }
6960
6961         return 0;
6962 }
6963
6964 /* Convert tunnel filter structure */
6965 static int
6966 i40e_tunnel_filter_convert(
6967         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6968         struct i40e_tunnel_filter *tunnel_filter)
6969 {
6970         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6971                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6972         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6973                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6974         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6975         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6976              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6977             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6978                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6979         else
6980                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6981         tunnel_filter->input.flags = cld_filter->element.flags;
6982         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6983         tunnel_filter->queue = cld_filter->element.queue_number;
6984         rte_memcpy(tunnel_filter->input.general_fields,
6985                    cld_filter->general_fields,
6986                    sizeof(cld_filter->general_fields));
6987
6988         return 0;
6989 }
6990
6991 /* Check if there exists the tunnel filter */
6992 struct i40e_tunnel_filter *
6993 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6994                              const struct i40e_tunnel_filter_input *input)
6995 {
6996         int ret;
6997
6998         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6999         if (ret < 0)
7000                 return NULL;
7001
7002         return tunnel_rule->hash_map[ret];
7003 }
7004
7005 /* Add a tunnel filter into the SW list */
7006 static int
7007 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7008                              struct i40e_tunnel_filter *tunnel_filter)
7009 {
7010         struct i40e_tunnel_rule *rule = &pf->tunnel;
7011         int ret;
7012
7013         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7014         if (ret < 0) {
7015                 PMD_DRV_LOG(ERR,
7016                             "Failed to insert tunnel filter to hash table %d!",
7017                             ret);
7018                 return ret;
7019         }
7020         rule->hash_map[ret] = tunnel_filter;
7021
7022         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7023
7024         return 0;
7025 }
7026
7027 /* Delete a tunnel filter from the SW list */
7028 int
7029 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7030                           struct i40e_tunnel_filter_input *input)
7031 {
7032         struct i40e_tunnel_rule *rule = &pf->tunnel;
7033         struct i40e_tunnel_filter *tunnel_filter;
7034         int ret;
7035
7036         ret = rte_hash_del_key(rule->hash_table, input);
7037         if (ret < 0) {
7038                 PMD_DRV_LOG(ERR,
7039                             "Failed to delete tunnel filter to hash table %d!",
7040                             ret);
7041                 return ret;
7042         }
7043         tunnel_filter = rule->hash_map[ret];
7044         rule->hash_map[ret] = NULL;
7045
7046         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7047         rte_free(tunnel_filter);
7048
7049         return 0;
7050 }
7051
7052 int
7053 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7054                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7055                         uint8_t add)
7056 {
7057         uint16_t ip_type;
7058         uint32_t ipv4_addr, ipv4_addr_le;
7059         uint8_t i, tun_type = 0;
7060         /* internal varialbe to convert ipv6 byte order */
7061         uint32_t convert_ipv6[4];
7062         int val, ret = 0;
7063         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7064         struct i40e_vsi *vsi = pf->main_vsi;
7065         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7066         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7067         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7068         struct i40e_tunnel_filter *tunnel, *node;
7069         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7070
7071         cld_filter = rte_zmalloc("tunnel_filter",
7072                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7073         0);
7074
7075         if (NULL == cld_filter) {
7076                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7077                 return -ENOMEM;
7078         }
7079         pfilter = cld_filter;
7080
7081         ether_addr_copy(&tunnel_filter->outer_mac,
7082                         (struct ether_addr *)&pfilter->element.outer_mac);
7083         ether_addr_copy(&tunnel_filter->inner_mac,
7084                         (struct ether_addr *)&pfilter->element.inner_mac);
7085
7086         pfilter->element.inner_vlan =
7087                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7088         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7089                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7090                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7091                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7092                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7093                                 &ipv4_addr_le,
7094                                 sizeof(pfilter->element.ipaddr.v4.data));
7095         } else {
7096                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7097                 for (i = 0; i < 4; i++) {
7098                         convert_ipv6[i] =
7099                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7100                 }
7101                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7102                            &convert_ipv6,
7103                            sizeof(pfilter->element.ipaddr.v6.data));
7104         }
7105
7106         /* check tunneled type */
7107         switch (tunnel_filter->tunnel_type) {
7108         case RTE_TUNNEL_TYPE_VXLAN:
7109                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7110                 break;
7111         case RTE_TUNNEL_TYPE_NVGRE:
7112                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7113                 break;
7114         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7115                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7116                 break;
7117         default:
7118                 /* Other tunnel types is not supported. */
7119                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7120                 rte_free(cld_filter);
7121                 return -EINVAL;
7122         }
7123
7124         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7125                                        &pfilter->element.flags);
7126         if (val < 0) {
7127                 rte_free(cld_filter);
7128                 return -EINVAL;
7129         }
7130
7131         pfilter->element.flags |= rte_cpu_to_le_16(
7132                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7133                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7134         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7135         pfilter->element.queue_number =
7136                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7137
7138         /* Check if there is the filter in SW list */
7139         memset(&check_filter, 0, sizeof(check_filter));
7140         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7141         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7142         if (add && node) {
7143                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7144                 return -EINVAL;
7145         }
7146
7147         if (!add && !node) {
7148                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7149                 return -EINVAL;
7150         }
7151
7152         if (add) {
7153                 ret = i40e_aq_add_cloud_filters(hw,
7154                                         vsi->seid, &cld_filter->element, 1);
7155                 if (ret < 0) {
7156                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7157                         return -ENOTSUP;
7158                 }
7159                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7160                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7161                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7162         } else {
7163                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7164                                                    &cld_filter->element, 1);
7165                 if (ret < 0) {
7166                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7167                         return -ENOTSUP;
7168                 }
7169                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7170         }
7171
7172         rte_free(cld_filter);
7173         return ret;
7174 }
7175
7176 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7177 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7178 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7179 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7180 #define I40E_TR_GRE_KEY_MASK                    0x400
7181 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7182 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7183
7184 static enum
7185 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7186 {
7187         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7188         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7189         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7190         enum i40e_status_code status = I40E_SUCCESS;
7191
7192         memset(&filter_replace, 0,
7193                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7194         memset(&filter_replace_buf, 0,
7195                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7196
7197         /* create L1 filter */
7198         filter_replace.old_filter_type =
7199                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7200         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7201         filter_replace.tr_bit = 0;
7202
7203         /* Prepare the buffer, 3 entries */
7204         filter_replace_buf.data[0] =
7205                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7206         filter_replace_buf.data[0] |=
7207                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7208         filter_replace_buf.data[2] = 0xFF;
7209         filter_replace_buf.data[3] = 0xFF;
7210         filter_replace_buf.data[4] =
7211                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7212         filter_replace_buf.data[4] |=
7213                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7214         filter_replace_buf.data[7] = 0xF0;
7215         filter_replace_buf.data[8]
7216                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7217         filter_replace_buf.data[8] |=
7218                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7219         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7220                 I40E_TR_GENEVE_KEY_MASK |
7221                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7222         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7223                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7224                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7225
7226         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7227                                                &filter_replace_buf);
7228         return status;
7229 }
7230
7231 static enum
7232 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7233 {
7234         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7235         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7236         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7237         enum i40e_status_code status = I40E_SUCCESS;
7238
7239         /* For MPLSoUDP */
7240         memset(&filter_replace, 0,
7241                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7242         memset(&filter_replace_buf, 0,
7243                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7244         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7245                 I40E_AQC_MIRROR_CLOUD_FILTER;
7246         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7247         filter_replace.new_filter_type =
7248                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7249         /* Prepare the buffer, 2 entries */
7250         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7251         filter_replace_buf.data[0] |=
7252                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7253         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7254         filter_replace_buf.data[4] |=
7255                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7256         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7257                                                &filter_replace_buf);
7258         if (status < 0)
7259                 return status;
7260
7261         /* For MPLSoGRE */
7262         memset(&filter_replace, 0,
7263                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7264         memset(&filter_replace_buf, 0,
7265                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7266
7267         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7268                 I40E_AQC_MIRROR_CLOUD_FILTER;
7269         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7270         filter_replace.new_filter_type =
7271                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7272         /* Prepare the buffer, 2 entries */
7273         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7274         filter_replace_buf.data[0] |=
7275                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7276         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7277         filter_replace_buf.data[4] |=
7278                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7279
7280         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7281                                                &filter_replace_buf);
7282         return status;
7283 }
7284
7285 static enum i40e_status_code
7286 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7287 {
7288         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7289         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7290         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7291         enum i40e_status_code status = I40E_SUCCESS;
7292
7293         /* For GTP-C */
7294         memset(&filter_replace, 0,
7295                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7296         memset(&filter_replace_buf, 0,
7297                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7298         /* create L1 filter */
7299         filter_replace.old_filter_type =
7300                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7301         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7302         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7303                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7304         /* Prepare the buffer, 2 entries */
7305         filter_replace_buf.data[0] =
7306                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7307         filter_replace_buf.data[0] |=
7308                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7309         filter_replace_buf.data[2] = 0xFF;
7310         filter_replace_buf.data[3] = 0xFF;
7311         filter_replace_buf.data[4] =
7312                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7313         filter_replace_buf.data[4] |=
7314                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7315         filter_replace_buf.data[6] = 0xFF;
7316         filter_replace_buf.data[7] = 0xFF;
7317         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7318                                                &filter_replace_buf);
7319         if (status < 0)
7320                 return status;
7321
7322         /* for GTP-U */
7323         memset(&filter_replace, 0,
7324                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7325         memset(&filter_replace_buf, 0,
7326                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7327         /* create L1 filter */
7328         filter_replace.old_filter_type =
7329                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7330         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7331         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7332                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7333         /* Prepare the buffer, 2 entries */
7334         filter_replace_buf.data[0] =
7335                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7336         filter_replace_buf.data[0] |=
7337                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7338         filter_replace_buf.data[2] = 0xFF;
7339         filter_replace_buf.data[3] = 0xFF;
7340         filter_replace_buf.data[4] =
7341                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7342         filter_replace_buf.data[4] |=
7343                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7344         filter_replace_buf.data[6] = 0xFF;
7345         filter_replace_buf.data[7] = 0xFF;
7346
7347         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7348                                                &filter_replace_buf);
7349         return status;
7350 }
7351
7352 static enum
7353 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7354 {
7355         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7356         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7357         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7358         enum i40e_status_code status = I40E_SUCCESS;
7359
7360         /* for GTP-C */
7361         memset(&filter_replace, 0,
7362                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7363         memset(&filter_replace_buf, 0,
7364                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7365         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7366         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7367         filter_replace.new_filter_type =
7368                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7369         /* Prepare the buffer, 2 entries */
7370         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7371         filter_replace_buf.data[0] |=
7372                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7373         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7374         filter_replace_buf.data[4] |=
7375                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7376         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7377                                                &filter_replace_buf);
7378         if (status < 0)
7379                 return status;
7380
7381         /* for GTP-U */
7382         memset(&filter_replace, 0,
7383                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7384         memset(&filter_replace_buf, 0,
7385                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7386         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7387         filter_replace.old_filter_type =
7388                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7389         filter_replace.new_filter_type =
7390                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7391         /* Prepare the buffer, 2 entries */
7392         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7393         filter_replace_buf.data[0] |=
7394                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7395         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7396         filter_replace_buf.data[4] |=
7397                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7398
7399         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7400                                                &filter_replace_buf);
7401         return status;
7402 }
7403
7404 int
7405 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7406                       struct i40e_tunnel_filter_conf *tunnel_filter,
7407                       uint8_t add)
7408 {
7409         uint16_t ip_type;
7410         uint32_t ipv4_addr, ipv4_addr_le;
7411         uint8_t i, tun_type = 0;
7412         /* internal variable to convert ipv6 byte order */
7413         uint32_t convert_ipv6[4];
7414         int val, ret = 0;
7415         struct i40e_pf_vf *vf = NULL;
7416         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7417         struct i40e_vsi *vsi;
7418         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7419         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7420         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7421         struct i40e_tunnel_filter *tunnel, *node;
7422         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7423         uint32_t teid_le;
7424         bool big_buffer = 0;
7425
7426         cld_filter = rte_zmalloc("tunnel_filter",
7427                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7428                          0);
7429
7430         if (cld_filter == NULL) {
7431                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7432                 return -ENOMEM;
7433         }
7434         pfilter = cld_filter;
7435
7436         ether_addr_copy(&tunnel_filter->outer_mac,
7437                         (struct ether_addr *)&pfilter->element.outer_mac);
7438         ether_addr_copy(&tunnel_filter->inner_mac,
7439                         (struct ether_addr *)&pfilter->element.inner_mac);
7440
7441         pfilter->element.inner_vlan =
7442                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7443         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7444                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7445                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7446                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7447                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7448                                 &ipv4_addr_le,
7449                                 sizeof(pfilter->element.ipaddr.v4.data));
7450         } else {
7451                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7452                 for (i = 0; i < 4; i++) {
7453                         convert_ipv6[i] =
7454                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7455                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7456                 }
7457                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7458                            &convert_ipv6,
7459                            sizeof(pfilter->element.ipaddr.v6.data));
7460         }
7461
7462         /* check tunneled type */
7463         switch (tunnel_filter->tunnel_type) {
7464         case I40E_TUNNEL_TYPE_VXLAN:
7465                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7466                 break;
7467         case I40E_TUNNEL_TYPE_NVGRE:
7468                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7469                 break;
7470         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7471                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7472                 break;
7473         case I40E_TUNNEL_TYPE_MPLSoUDP:
7474                 if (!pf->mpls_replace_flag) {
7475                         i40e_replace_mpls_l1_filter(pf);
7476                         i40e_replace_mpls_cloud_filter(pf);
7477                         pf->mpls_replace_flag = 1;
7478                 }
7479                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7480                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7481                         teid_le >> 4;
7482                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7483                         (teid_le & 0xF) << 12;
7484                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7485                         0x40;
7486                 big_buffer = 1;
7487                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7488                 break;
7489         case I40E_TUNNEL_TYPE_MPLSoGRE:
7490                 if (!pf->mpls_replace_flag) {
7491                         i40e_replace_mpls_l1_filter(pf);
7492                         i40e_replace_mpls_cloud_filter(pf);
7493                         pf->mpls_replace_flag = 1;
7494                 }
7495                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7496                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7497                         teid_le >> 4;
7498                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7499                         (teid_le & 0xF) << 12;
7500                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7501                         0x0;
7502                 big_buffer = 1;
7503                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7504                 break;
7505         case I40E_TUNNEL_TYPE_GTPC:
7506                 if (!pf->gtp_replace_flag) {
7507                         i40e_replace_gtp_l1_filter(pf);
7508                         i40e_replace_gtp_cloud_filter(pf);
7509                         pf->gtp_replace_flag = 1;
7510                 }
7511                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7512                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7513                         (teid_le >> 16) & 0xFFFF;
7514                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7515                         teid_le & 0xFFFF;
7516                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7517                         0x0;
7518                 big_buffer = 1;
7519                 break;
7520         case I40E_TUNNEL_TYPE_GTPU:
7521                 if (!pf->gtp_replace_flag) {
7522                         i40e_replace_gtp_l1_filter(pf);
7523                         i40e_replace_gtp_cloud_filter(pf);
7524                         pf->gtp_replace_flag = 1;
7525                 }
7526                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7527                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7528                         (teid_le >> 16) & 0xFFFF;
7529                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7530                         teid_le & 0xFFFF;
7531                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7532                         0x0;
7533                 big_buffer = 1;
7534                 break;
7535         case I40E_TUNNEL_TYPE_QINQ:
7536                 if (!pf->qinq_replace_flag) {
7537                         ret = i40e_cloud_filter_qinq_create(pf);
7538                         if (ret < 0)
7539                                 PMD_DRV_LOG(DEBUG,
7540                                             "QinQ tunnel filter already created.");
7541                         pf->qinq_replace_flag = 1;
7542                 }
7543                 /*      Add in the General fields the values of
7544                  *      the Outer and Inner VLAN
7545                  *      Big Buffer should be set, see changes in
7546                  *      i40e_aq_add_cloud_filters
7547                  */
7548                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7549                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7550                 big_buffer = 1;
7551                 break;
7552         default:
7553                 /* Other tunnel types is not supported. */
7554                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7555                 rte_free(cld_filter);
7556                 return -EINVAL;
7557         }
7558
7559         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7560                 pfilter->element.flags =
7561                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7562         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7563                 pfilter->element.flags =
7564                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7565         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7566                 pfilter->element.flags =
7567                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7568         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7569                 pfilter->element.flags =
7570                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7571         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7572                 pfilter->element.flags |=
7573                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7574         else {
7575                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7576                                                 &pfilter->element.flags);
7577                 if (val < 0) {
7578                         rte_free(cld_filter);
7579                         return -EINVAL;
7580                 }
7581         }
7582
7583         pfilter->element.flags |= rte_cpu_to_le_16(
7584                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7585                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7586         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7587         pfilter->element.queue_number =
7588                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7589
7590         if (!tunnel_filter->is_to_vf)
7591                 vsi = pf->main_vsi;
7592         else {
7593                 if (tunnel_filter->vf_id >= pf->vf_num) {
7594                         PMD_DRV_LOG(ERR, "Invalid argument.");
7595                         return -EINVAL;
7596                 }
7597                 vf = &pf->vfs[tunnel_filter->vf_id];
7598                 vsi = vf->vsi;
7599         }
7600
7601         /* Check if there is the filter in SW list */
7602         memset(&check_filter, 0, sizeof(check_filter));
7603         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7604         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7605         check_filter.vf_id = tunnel_filter->vf_id;
7606         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7607         if (add && node) {
7608                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7609                 return -EINVAL;
7610         }
7611
7612         if (!add && !node) {
7613                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7614                 return -EINVAL;
7615         }
7616
7617         if (add) {
7618                 if (big_buffer)
7619                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7620                                                    vsi->seid, cld_filter, 1);
7621                 else
7622                         ret = i40e_aq_add_cloud_filters(hw,
7623                                         vsi->seid, &cld_filter->element, 1);
7624                 if (ret < 0) {
7625                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7626                         return -ENOTSUP;
7627                 }
7628                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7629                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7630                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7631         } else {
7632                 if (big_buffer)
7633                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7634                                 hw, vsi->seid, cld_filter, 1);
7635                 else
7636                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7637                                                    &cld_filter->element, 1);
7638                 if (ret < 0) {
7639                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7640                         return -ENOTSUP;
7641                 }
7642                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7643         }
7644
7645         rte_free(cld_filter);
7646         return ret;
7647 }
7648
7649 static int
7650 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7651 {
7652         uint8_t i;
7653
7654         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7655                 if (pf->vxlan_ports[i] == port)
7656                         return i;
7657         }
7658
7659         return -1;
7660 }
7661
7662 static int
7663 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7664 {
7665         int  idx, ret;
7666         uint8_t filter_idx;
7667         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7668
7669         idx = i40e_get_vxlan_port_idx(pf, port);
7670
7671         /* Check if port already exists */
7672         if (idx >= 0) {
7673                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7674                 return -EINVAL;
7675         }
7676
7677         /* Now check if there is space to add the new port */
7678         idx = i40e_get_vxlan_port_idx(pf, 0);
7679         if (idx < 0) {
7680                 PMD_DRV_LOG(ERR,
7681                         "Maximum number of UDP ports reached, not adding port %d",
7682                         port);
7683                 return -ENOSPC;
7684         }
7685
7686         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7687                                         &filter_idx, NULL);
7688         if (ret < 0) {
7689                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7690                 return -1;
7691         }
7692
7693         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7694                          port,  filter_idx);
7695
7696         /* New port: add it and mark its index in the bitmap */
7697         pf->vxlan_ports[idx] = port;
7698         pf->vxlan_bitmap |= (1 << idx);
7699
7700         if (!(pf->flags & I40E_FLAG_VXLAN))
7701                 pf->flags |= I40E_FLAG_VXLAN;
7702
7703         return 0;
7704 }
7705
7706 static int
7707 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7708 {
7709         int idx;
7710         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7711
7712         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7713                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7714                 return -EINVAL;
7715         }
7716
7717         idx = i40e_get_vxlan_port_idx(pf, port);
7718
7719         if (idx < 0) {
7720                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7721                 return -EINVAL;
7722         }
7723
7724         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7725                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7726                 return -1;
7727         }
7728
7729         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7730                         port, idx);
7731
7732         pf->vxlan_ports[idx] = 0;
7733         pf->vxlan_bitmap &= ~(1 << idx);
7734
7735         if (!pf->vxlan_bitmap)
7736                 pf->flags &= ~I40E_FLAG_VXLAN;
7737
7738         return 0;
7739 }
7740
7741 /* Add UDP tunneling port */
7742 static int
7743 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7744                              struct rte_eth_udp_tunnel *udp_tunnel)
7745 {
7746         int ret = 0;
7747         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7748
7749         if (udp_tunnel == NULL)
7750                 return -EINVAL;
7751
7752         switch (udp_tunnel->prot_type) {
7753         case RTE_TUNNEL_TYPE_VXLAN:
7754                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7755                 break;
7756
7757         case RTE_TUNNEL_TYPE_GENEVE:
7758         case RTE_TUNNEL_TYPE_TEREDO:
7759                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7760                 ret = -1;
7761                 break;
7762
7763         default:
7764                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7765                 ret = -1;
7766                 break;
7767         }
7768
7769         return ret;
7770 }
7771
7772 /* Remove UDP tunneling port */
7773 static int
7774 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7775                              struct rte_eth_udp_tunnel *udp_tunnel)
7776 {
7777         int ret = 0;
7778         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7779
7780         if (udp_tunnel == NULL)
7781                 return -EINVAL;
7782
7783         switch (udp_tunnel->prot_type) {
7784         case RTE_TUNNEL_TYPE_VXLAN:
7785                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7786                 break;
7787         case RTE_TUNNEL_TYPE_GENEVE:
7788         case RTE_TUNNEL_TYPE_TEREDO:
7789                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7790                 ret = -1;
7791                 break;
7792         default:
7793                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7794                 ret = -1;
7795                 break;
7796         }
7797
7798         return ret;
7799 }
7800
7801 /* Calculate the maximum number of contiguous PF queues that are configured */
7802 static int
7803 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7804 {
7805         struct rte_eth_dev_data *data = pf->dev_data;
7806         int i, num;
7807         struct i40e_rx_queue *rxq;
7808
7809         num = 0;
7810         for (i = 0; i < pf->lan_nb_qps; i++) {
7811                 rxq = data->rx_queues[i];
7812                 if (rxq && rxq->q_set)
7813                         num++;
7814                 else
7815                         break;
7816         }
7817
7818         return num;
7819 }
7820
7821 /* Configure RSS */
7822 static int
7823 i40e_pf_config_rss(struct i40e_pf *pf)
7824 {
7825         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7826         struct rte_eth_rss_conf rss_conf;
7827         uint32_t i, lut = 0;
7828         uint16_t j, num;
7829
7830         /*
7831          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7832          * It's necessary to calculate the actual PF queues that are configured.
7833          */
7834         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7835                 num = i40e_pf_calc_configured_queues_num(pf);
7836         else
7837                 num = pf->dev_data->nb_rx_queues;
7838
7839         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7840         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7841                         num);
7842
7843         if (num == 0) {
7844                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7845                 return -ENOTSUP;
7846         }
7847
7848         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7849                 if (j == num)
7850                         j = 0;
7851                 lut = (lut << 8) | (j & ((0x1 <<
7852                         hw->func_caps.rss_table_entry_width) - 1));
7853                 if ((i & 3) == 3)
7854                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7855         }
7856
7857         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7858         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7859                 i40e_pf_disable_rss(pf);
7860                 return 0;
7861         }
7862         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7863                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7864                 /* Random default keys */
7865                 static uint32_t rss_key_default[] = {0x6b793944,
7866                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7867                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7868                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7869
7870                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7871                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7872                                                         sizeof(uint32_t);
7873         }
7874
7875         return i40e_hw_rss_hash_set(pf, &rss_conf);
7876 }
7877
7878 static int
7879 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7880                                struct rte_eth_tunnel_filter_conf *filter)
7881 {
7882         if (pf == NULL || filter == NULL) {
7883                 PMD_DRV_LOG(ERR, "Invalid parameter");
7884                 return -EINVAL;
7885         }
7886
7887         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7888                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7889                 return -EINVAL;
7890         }
7891
7892         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7893                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7894                 return -EINVAL;
7895         }
7896
7897         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7898                 (is_zero_ether_addr(&filter->outer_mac))) {
7899                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7900                 return -EINVAL;
7901         }
7902
7903         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7904                 (is_zero_ether_addr(&filter->inner_mac))) {
7905                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7906                 return -EINVAL;
7907         }
7908
7909         return 0;
7910 }
7911
7912 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7913 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7914 static int
7915 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7916 {
7917         uint32_t val, reg;
7918         int ret = -EINVAL;
7919
7920         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7921         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7922
7923         if (len == 3) {
7924                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7925         } else if (len == 4) {
7926                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7927         } else {
7928                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7929                 return ret;
7930         }
7931
7932         if (reg != val) {
7933                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7934                                                    reg, NULL);
7935                 if (ret != 0)
7936                         return ret;
7937         } else {
7938                 ret = 0;
7939         }
7940         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7941                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7942
7943         return ret;
7944 }
7945
7946 static int
7947 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7948 {
7949         int ret = -EINVAL;
7950
7951         if (!hw || !cfg)
7952                 return -EINVAL;
7953
7954         switch (cfg->cfg_type) {
7955         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7956                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7957                 break;
7958         default:
7959                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7960                 break;
7961         }
7962
7963         return ret;
7964 }
7965
7966 static int
7967 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7968                                enum rte_filter_op filter_op,
7969                                void *arg)
7970 {
7971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7972         int ret = I40E_ERR_PARAM;
7973
7974         switch (filter_op) {
7975         case RTE_ETH_FILTER_SET:
7976                 ret = i40e_dev_global_config_set(hw,
7977                         (struct rte_eth_global_cfg *)arg);
7978                 break;
7979         default:
7980                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7981                 break;
7982         }
7983
7984         return ret;
7985 }
7986
7987 static int
7988 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7989                           enum rte_filter_op filter_op,
7990                           void *arg)
7991 {
7992         struct rte_eth_tunnel_filter_conf *filter;
7993         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7994         int ret = I40E_SUCCESS;
7995
7996         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7997
7998         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7999                 return I40E_ERR_PARAM;
8000
8001         switch (filter_op) {
8002         case RTE_ETH_FILTER_NOP:
8003                 if (!(pf->flags & I40E_FLAG_VXLAN))
8004                         ret = I40E_NOT_SUPPORTED;
8005                 break;
8006         case RTE_ETH_FILTER_ADD:
8007                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8008                 break;
8009         case RTE_ETH_FILTER_DELETE:
8010                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8011                 break;
8012         default:
8013                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8014                 ret = I40E_ERR_PARAM;
8015                 break;
8016         }
8017
8018         return ret;
8019 }
8020
8021 static int
8022 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8023 {
8024         int ret = 0;
8025         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8026
8027         /* RSS setup */
8028         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8029                 ret = i40e_pf_config_rss(pf);
8030         else
8031                 i40e_pf_disable_rss(pf);
8032
8033         return ret;
8034 }
8035
8036 /* Get the symmetric hash enable configurations per port */
8037 static void
8038 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8039 {
8040         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8041
8042         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8043 }
8044
8045 /* Set the symmetric hash enable configurations per port */
8046 static void
8047 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8048 {
8049         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8050
8051         if (enable > 0) {
8052                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8053                         PMD_DRV_LOG(INFO,
8054                                 "Symmetric hash has already been enabled");
8055                         return;
8056                 }
8057                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8058         } else {
8059                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8060                         PMD_DRV_LOG(INFO,
8061                                 "Symmetric hash has already been disabled");
8062                         return;
8063                 }
8064                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8065         }
8066         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8067         I40E_WRITE_FLUSH(hw);
8068 }
8069
8070 /*
8071  * Get global configurations of hash function type and symmetric hash enable
8072  * per flow type (pctype). Note that global configuration means it affects all
8073  * the ports on the same NIC.
8074  */
8075 static int
8076 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8077                                    struct rte_eth_hash_global_conf *g_cfg)
8078 {
8079         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8080         uint32_t reg;
8081         uint16_t i, j;
8082
8083         memset(g_cfg, 0, sizeof(*g_cfg));
8084         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8085         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8086                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8087         else
8088                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8089         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8090                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8091
8092         /*
8093          * We work only with lowest 32 bits which is not correct, but to work
8094          * properly the valid_bit_mask size should be increased up to 64 bits
8095          * and this will brake ABI. This modification will be done in next
8096          * release
8097          */
8098         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
8099
8100         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
8101                 if (!adapter->pctypes_tbl[i])
8102                         continue;
8103                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8104                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8105                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8106                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8107                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8108                                         g_cfg->sym_hash_enable_mask[0] |=
8109                                                                 (1UL << i);
8110                                 }
8111                         }
8112                 }
8113         }
8114
8115         return 0;
8116 }
8117
8118 static int
8119 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8120                               const struct rte_eth_hash_global_conf *g_cfg)
8121 {
8122         uint32_t i;
8123         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8124
8125         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8126                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8127                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8128                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8129                                                 g_cfg->hash_func);
8130                 return -EINVAL;
8131         }
8132
8133         /*
8134          * As i40e supports less than 32 flow types, only first 32 bits need to
8135          * be checked.
8136          */
8137         mask0 = g_cfg->valid_bit_mask[0];
8138         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8139                 if (i == 0) {
8140                         /* Check if any unsupported flow type configured */
8141                         if ((mask0 | i40e_mask) ^ i40e_mask)
8142                                 goto mask_err;
8143                 } else {
8144                         if (g_cfg->valid_bit_mask[i])
8145                                 goto mask_err;
8146                 }
8147         }
8148
8149         return 0;
8150
8151 mask_err:
8152         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8153
8154         return -EINVAL;
8155 }
8156
8157 /*
8158  * Set global configurations of hash function type and symmetric hash enable
8159  * per flow type (pctype). Note any modifying global configuration will affect
8160  * all the ports on the same NIC.
8161  */
8162 static int
8163 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8164                                    struct rte_eth_hash_global_conf *g_cfg)
8165 {
8166         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8167         int ret;
8168         uint16_t i, j;
8169         uint32_t reg;
8170         /*
8171          * We work only with lowest 32 bits which is not correct, but to work
8172          * properly the valid_bit_mask size should be increased up to 64 bits
8173          * and this will brake ABI. This modification will be done in next
8174          * release
8175          */
8176         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8177                                         (uint32_t)adapter->flow_types_mask;
8178
8179         /* Check the input parameters */
8180         ret = i40e_hash_global_config_check(adapter, g_cfg);
8181         if (ret < 0)
8182                 return ret;
8183
8184         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8185                 if (mask0 & (1UL << i)) {
8186                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8187                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8188
8189                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8190                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8191                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8192                                         i40e_write_rx_ctl(hw,
8193                                                           I40E_GLQF_HSYM(j),
8194                                                           reg);
8195                         }
8196                 }
8197         }
8198
8199         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8200         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8201                 /* Toeplitz */
8202                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8203                         PMD_DRV_LOG(DEBUG,
8204                                 "Hash function already set to Toeplitz");
8205                         goto out;
8206                 }
8207                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8208         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8209                 /* Simple XOR */
8210                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8211                         PMD_DRV_LOG(DEBUG,
8212                                 "Hash function already set to Simple XOR");
8213                         goto out;
8214                 }
8215                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8216         } else
8217                 /* Use the default, and keep it as it is */
8218                 goto out;
8219
8220         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8221
8222 out:
8223         I40E_WRITE_FLUSH(hw);
8224
8225         return 0;
8226 }
8227
8228 /**
8229  * Valid input sets for hash and flow director filters per PCTYPE
8230  */
8231 static uint64_t
8232 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8233                 enum rte_filter_type filter)
8234 {
8235         uint64_t valid;
8236
8237         static const uint64_t valid_hash_inset_table[] = {
8238                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8239                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8240                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8241                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8242                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8243                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8244                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8245                         I40E_INSET_FLEX_PAYLOAD,
8246                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8247                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8248                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8249                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8250                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8251                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8252                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8253                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8254                         I40E_INSET_FLEX_PAYLOAD,
8255                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8256                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8257                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8258                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8259                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8260                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8261                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8262                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8263                         I40E_INSET_FLEX_PAYLOAD,
8264                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8265                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8266                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8267                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8268                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8269                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8270                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8271                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8272                         I40E_INSET_FLEX_PAYLOAD,
8273                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8274                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8275                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8276                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8277                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8278                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8279                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8280                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8281                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8282                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8283                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8284                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8285                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8286                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8287                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8288                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8289                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8290                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8291                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8292                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8293                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8294                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8295                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8296                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8297                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8298                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8299                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8300                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8301                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8302                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8303                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8304                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8305                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8306                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8307                         I40E_INSET_FLEX_PAYLOAD,
8308                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8309                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8310                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8311                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8312                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8313                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8314                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8315                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8316                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8317                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8318                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8319                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8320                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8321                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8322                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8323                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8324                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8325                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8326                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8327                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8328                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8329                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8330                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8331                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8332                         I40E_INSET_FLEX_PAYLOAD,
8333                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8334                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8335                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8336                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8337                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8338                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8339                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8340                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8341                         I40E_INSET_FLEX_PAYLOAD,
8342                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8343                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8344                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8345                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8346                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8347                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8348                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8349                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8350                         I40E_INSET_FLEX_PAYLOAD,
8351                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8352                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8353                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8354                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8355                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8356                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8357                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8358                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8359                         I40E_INSET_FLEX_PAYLOAD,
8360                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8361                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8362                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8363                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8364                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8365                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8366                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8367                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8368                         I40E_INSET_FLEX_PAYLOAD,
8369                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8370                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8371                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8372                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8373                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8374                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8375                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8376                         I40E_INSET_FLEX_PAYLOAD,
8377                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8378                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8379                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8380                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8381                         I40E_INSET_FLEX_PAYLOAD,
8382         };
8383
8384         /**
8385          * Flow director supports only fields defined in
8386          * union rte_eth_fdir_flow.
8387          */
8388         static const uint64_t valid_fdir_inset_table[] = {
8389                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8390                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8391                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8392                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8393                 I40E_INSET_IPV4_TTL,
8394                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8395                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8396                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8397                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8398                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8399                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8400                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8401                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8402                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8403                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8404                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8405                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8406                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8407                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8408                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8409                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8410                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8411                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8412                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8413                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8414                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8415                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8416                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8417                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8418                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8419                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8420                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8421                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8422                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8423                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8424                 I40E_INSET_SCTP_VT,
8425                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8426                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8427                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8428                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8429                 I40E_INSET_IPV4_TTL,
8430                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8431                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8432                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8433                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8434                 I40E_INSET_IPV6_HOP_LIMIT,
8435                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8436                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8437                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8438                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8439                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8440                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8441                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8442                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8443                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8444                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8445                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8446                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8447                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8448                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8449                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8450                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8451                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8452                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8453                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8454                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8455                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8456                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8457                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8458                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8459                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8460                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8461                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8462                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8463                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8464                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8465                 I40E_INSET_SCTP_VT,
8466                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8467                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8468                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8469                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8470                 I40E_INSET_IPV6_HOP_LIMIT,
8471                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8472                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8473                 I40E_INSET_LAST_ETHER_TYPE,
8474         };
8475
8476         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8477                 return 0;
8478         if (filter == RTE_ETH_FILTER_HASH)
8479                 valid = valid_hash_inset_table[pctype];
8480         else
8481                 valid = valid_fdir_inset_table[pctype];
8482
8483         return valid;
8484 }
8485
8486 /**
8487  * Validate if the input set is allowed for a specific PCTYPE
8488  */
8489 int
8490 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8491                 enum rte_filter_type filter, uint64_t inset)
8492 {
8493         uint64_t valid;
8494
8495         valid = i40e_get_valid_input_set(pctype, filter);
8496         if (inset & (~valid))
8497                 return -EINVAL;
8498
8499         return 0;
8500 }
8501
8502 /* default input set fields combination per pctype */
8503 uint64_t
8504 i40e_get_default_input_set(uint16_t pctype)
8505 {
8506         static const uint64_t default_inset_table[] = {
8507                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8508                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8509                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8510                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8511                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8512                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8513                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8514                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8515                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8516                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8517                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8518                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8519                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8520                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8521                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8522                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8523                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8524                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8525                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8526                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8527                         I40E_INSET_SCTP_VT,
8528                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8529                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8530                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8531                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8532                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8533                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8534                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8535                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8536                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8537                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8538                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8539                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8540                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8541                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8542                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8543                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8544                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8545                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8546                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8547                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8548                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8549                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8550                         I40E_INSET_SCTP_VT,
8551                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8552                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8553                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8554                         I40E_INSET_LAST_ETHER_TYPE,
8555         };
8556
8557         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8558                 return 0;
8559
8560         return default_inset_table[pctype];
8561 }
8562
8563 /**
8564  * Parse the input set from index to logical bit masks
8565  */
8566 static int
8567 i40e_parse_input_set(uint64_t *inset,
8568                      enum i40e_filter_pctype pctype,
8569                      enum rte_eth_input_set_field *field,
8570                      uint16_t size)
8571 {
8572         uint16_t i, j;
8573         int ret = -EINVAL;
8574
8575         static const struct {
8576                 enum rte_eth_input_set_field field;
8577                 uint64_t inset;
8578         } inset_convert_table[] = {
8579                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8580                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8581                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8582                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8583                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8584                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8585                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8586                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8587                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8588                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8589                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8590                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8591                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8592                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8593                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8594                         I40E_INSET_IPV6_NEXT_HDR},
8595                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8596                         I40E_INSET_IPV6_HOP_LIMIT},
8597                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8598                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8599                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8600                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8601                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8602                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8603                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8604                         I40E_INSET_SCTP_VT},
8605                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8606                         I40E_INSET_TUNNEL_DMAC},
8607                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8608                         I40E_INSET_VLAN_TUNNEL},
8609                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8610                         I40E_INSET_TUNNEL_ID},
8611                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8612                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8613                         I40E_INSET_FLEX_PAYLOAD_W1},
8614                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8615                         I40E_INSET_FLEX_PAYLOAD_W2},
8616                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8617                         I40E_INSET_FLEX_PAYLOAD_W3},
8618                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8619                         I40E_INSET_FLEX_PAYLOAD_W4},
8620                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8621                         I40E_INSET_FLEX_PAYLOAD_W5},
8622                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8623                         I40E_INSET_FLEX_PAYLOAD_W6},
8624                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8625                         I40E_INSET_FLEX_PAYLOAD_W7},
8626                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8627                         I40E_INSET_FLEX_PAYLOAD_W8},
8628         };
8629
8630         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8631                 return ret;
8632
8633         /* Only one item allowed for default or all */
8634         if (size == 1) {
8635                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8636                         *inset = i40e_get_default_input_set(pctype);
8637                         return 0;
8638                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8639                         *inset = I40E_INSET_NONE;
8640                         return 0;
8641                 }
8642         }
8643
8644         for (i = 0, *inset = 0; i < size; i++) {
8645                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8646                         if (field[i] == inset_convert_table[j].field) {
8647                                 *inset |= inset_convert_table[j].inset;
8648                                 break;
8649                         }
8650                 }
8651
8652                 /* It contains unsupported input set, return immediately */
8653                 if (j == RTE_DIM(inset_convert_table))
8654                         return ret;
8655         }
8656
8657         return 0;
8658 }
8659
8660 /**
8661  * Translate the input set from bit masks to register aware bit masks
8662  * and vice versa
8663  */
8664 uint64_t
8665 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8666 {
8667         uint64_t val = 0;
8668         uint16_t i;
8669
8670         struct inset_map {
8671                 uint64_t inset;
8672                 uint64_t inset_reg;
8673         };
8674
8675         static const struct inset_map inset_map_common[] = {
8676                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8677                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8678                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8679                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8680                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8681                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8682                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8683                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8684                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8685                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8686                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8687                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8688                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8689                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8690                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8691                 {I40E_INSET_TUNNEL_DMAC,
8692                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8693                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8694                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8695                 {I40E_INSET_TUNNEL_SRC_PORT,
8696                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8697                 {I40E_INSET_TUNNEL_DST_PORT,
8698                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8699                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8700                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8701                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8702                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8703                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8704                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8705                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8706                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8707                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8708         };
8709
8710     /* some different registers map in x722*/
8711         static const struct inset_map inset_map_diff_x722[] = {
8712                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8713                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8714                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8715                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8716         };
8717
8718         static const struct inset_map inset_map_diff_not_x722[] = {
8719                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8720                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8721                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8722                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8723         };
8724
8725         if (input == 0)
8726                 return val;
8727
8728         /* Translate input set to register aware inset */
8729         if (type == I40E_MAC_X722) {
8730                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8731                         if (input & inset_map_diff_x722[i].inset)
8732                                 val |= inset_map_diff_x722[i].inset_reg;
8733                 }
8734         } else {
8735                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8736                         if (input & inset_map_diff_not_x722[i].inset)
8737                                 val |= inset_map_diff_not_x722[i].inset_reg;
8738                 }
8739         }
8740
8741         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8742                 if (input & inset_map_common[i].inset)
8743                         val |= inset_map_common[i].inset_reg;
8744         }
8745
8746         return val;
8747 }
8748
8749 int
8750 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8751 {
8752         uint8_t i, idx = 0;
8753         uint64_t inset_need_mask = inset;
8754
8755         static const struct {
8756                 uint64_t inset;
8757                 uint32_t mask;
8758         } inset_mask_map[] = {
8759                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8760                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8761                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8762                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8763                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8764                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8765                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8766                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8767         };
8768
8769         if (!inset || !mask || !nb_elem)
8770                 return 0;
8771
8772         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8773                 /* Clear the inset bit, if no MASK is required,
8774                  * for example proto + ttl
8775                  */
8776                 if ((inset & inset_mask_map[i].inset) ==
8777                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8778                         inset_need_mask &= ~inset_mask_map[i].inset;
8779                 if (!inset_need_mask)
8780                         return 0;
8781         }
8782         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8783                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8784                     inset_mask_map[i].inset) {
8785                         if (idx >= nb_elem) {
8786                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8787                                 return -EINVAL;
8788                         }
8789                         mask[idx] = inset_mask_map[i].mask;
8790                         idx++;
8791                 }
8792         }
8793
8794         return idx;
8795 }
8796
8797 void
8798 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8799 {
8800         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8801
8802         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8803         if (reg != val)
8804                 i40e_write_rx_ctl(hw, addr, val);
8805         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8806                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8807 }
8808
8809 static void
8810 i40e_filter_input_set_init(struct i40e_pf *pf)
8811 {
8812         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8813         enum i40e_filter_pctype pctype;
8814         uint64_t input_set, inset_reg;
8815         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8816         int num, i;
8817         uint16_t flow_type;
8818
8819         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8820              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8821                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8822
8823                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8824                         continue;
8825
8826                 input_set = i40e_get_default_input_set(pctype);
8827
8828                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8829                                                    I40E_INSET_MASK_NUM_REG);
8830                 if (num < 0)
8831                         return;
8832                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8833                                         input_set);
8834
8835                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8836                                       (uint32_t)(inset_reg & UINT32_MAX));
8837                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8838                                      (uint32_t)((inset_reg >>
8839                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8840                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8841                                       (uint32_t)(inset_reg & UINT32_MAX));
8842                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8843                                      (uint32_t)((inset_reg >>
8844                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8845
8846                 for (i = 0; i < num; i++) {
8847                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8848                                              mask_reg[i]);
8849                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8850                                              mask_reg[i]);
8851                 }
8852                 /*clear unused mask registers of the pctype */
8853                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8854                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8855                                              0);
8856                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8857                                              0);
8858                 }
8859                 I40E_WRITE_FLUSH(hw);
8860
8861                 /* store the default input set */
8862                 pf->hash_input_set[pctype] = input_set;
8863                 pf->fdir.input_set[pctype] = input_set;
8864         }
8865 }
8866
8867 int
8868 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8869                          struct rte_eth_input_set_conf *conf)
8870 {
8871         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8872         enum i40e_filter_pctype pctype;
8873         uint64_t input_set, inset_reg = 0;
8874         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8875         int ret, i, num;
8876
8877         if (!conf) {
8878                 PMD_DRV_LOG(ERR, "Invalid pointer");
8879                 return -EFAULT;
8880         }
8881         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8882             conf->op != RTE_ETH_INPUT_SET_ADD) {
8883                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8884                 return -EINVAL;
8885         }
8886
8887         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8888         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8889                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8890                 return -EINVAL;
8891         }
8892
8893         if (hw->mac.type == I40E_MAC_X722) {
8894                 /* get translated pctype value in fd pctype register */
8895                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8896                         I40E_GLQF_FD_PCTYPES((int)pctype));
8897         }
8898
8899         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8900                                    conf->inset_size);
8901         if (ret) {
8902                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8903                 return -EINVAL;
8904         }
8905
8906         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8907                 /* get inset value in register */
8908                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8909                 inset_reg <<= I40E_32_BIT_WIDTH;
8910                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8911                 input_set |= pf->hash_input_set[pctype];
8912         }
8913         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8914                                            I40E_INSET_MASK_NUM_REG);
8915         if (num < 0)
8916                 return -EINVAL;
8917
8918         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8919
8920         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8921                               (uint32_t)(inset_reg & UINT32_MAX));
8922         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8923                              (uint32_t)((inset_reg >>
8924                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8925
8926         for (i = 0; i < num; i++)
8927                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8928                                      mask_reg[i]);
8929         /*clear unused mask registers of the pctype */
8930         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8931                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8932                                      0);
8933         I40E_WRITE_FLUSH(hw);
8934
8935         pf->hash_input_set[pctype] = input_set;
8936         return 0;
8937 }
8938
8939 int
8940 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8941                          struct rte_eth_input_set_conf *conf)
8942 {
8943         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8944         enum i40e_filter_pctype pctype;
8945         uint64_t input_set, inset_reg = 0;
8946         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8947         int ret, i, num;
8948
8949         if (!hw || !conf) {
8950                 PMD_DRV_LOG(ERR, "Invalid pointer");
8951                 return -EFAULT;
8952         }
8953         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8954             conf->op != RTE_ETH_INPUT_SET_ADD) {
8955                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8956                 return -EINVAL;
8957         }
8958
8959         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8960
8961         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8962                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8963                 return -EINVAL;
8964         }
8965
8966         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8967                                    conf->inset_size);
8968         if (ret) {
8969                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8970                 return -EINVAL;
8971         }
8972
8973         /* get inset value in register */
8974         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8975         inset_reg <<= I40E_32_BIT_WIDTH;
8976         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8977
8978         /* Can not change the inset reg for flex payload for fdir,
8979          * it is done by writing I40E_PRTQF_FD_FLXINSET
8980          * in i40e_set_flex_mask_on_pctype.
8981          */
8982         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8983                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8984         else
8985                 input_set |= pf->fdir.input_set[pctype];
8986         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8987                                            I40E_INSET_MASK_NUM_REG);
8988         if (num < 0)
8989                 return -EINVAL;
8990
8991         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8992
8993         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8994                               (uint32_t)(inset_reg & UINT32_MAX));
8995         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8996                              (uint32_t)((inset_reg >>
8997                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8998
8999         for (i = 0; i < num; i++)
9000                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9001                                      mask_reg[i]);
9002         /*clear unused mask registers of the pctype */
9003         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9004                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9005                                      0);
9006         I40E_WRITE_FLUSH(hw);
9007
9008         pf->fdir.input_set[pctype] = input_set;
9009         return 0;
9010 }
9011
9012 static int
9013 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9014 {
9015         int ret = 0;
9016
9017         if (!hw || !info) {
9018                 PMD_DRV_LOG(ERR, "Invalid pointer");
9019                 return -EFAULT;
9020         }
9021
9022         switch (info->info_type) {
9023         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9024                 i40e_get_symmetric_hash_enable_per_port(hw,
9025                                         &(info->info.enable));
9026                 break;
9027         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9028                 ret = i40e_get_hash_filter_global_config(hw,
9029                                 &(info->info.global_conf));
9030                 break;
9031         default:
9032                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9033                                                         info->info_type);
9034                 ret = -EINVAL;
9035                 break;
9036         }
9037
9038         return ret;
9039 }
9040
9041 static int
9042 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9043 {
9044         int ret = 0;
9045
9046         if (!hw || !info) {
9047                 PMD_DRV_LOG(ERR, "Invalid pointer");
9048                 return -EFAULT;
9049         }
9050
9051         switch (info->info_type) {
9052         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9053                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9054                 break;
9055         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9056                 ret = i40e_set_hash_filter_global_config(hw,
9057                                 &(info->info.global_conf));
9058                 break;
9059         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9060                 ret = i40e_hash_filter_inset_select(hw,
9061                                                &(info->info.input_set_conf));
9062                 break;
9063
9064         default:
9065                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9066                                                         info->info_type);
9067                 ret = -EINVAL;
9068                 break;
9069         }
9070
9071         return ret;
9072 }
9073
9074 /* Operations for hash function */
9075 static int
9076 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9077                       enum rte_filter_op filter_op,
9078                       void *arg)
9079 {
9080         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9081         int ret = 0;
9082
9083         switch (filter_op) {
9084         case RTE_ETH_FILTER_NOP:
9085                 break;
9086         case RTE_ETH_FILTER_GET:
9087                 ret = i40e_hash_filter_get(hw,
9088                         (struct rte_eth_hash_filter_info *)arg);
9089                 break;
9090         case RTE_ETH_FILTER_SET:
9091                 ret = i40e_hash_filter_set(hw,
9092                         (struct rte_eth_hash_filter_info *)arg);
9093                 break;
9094         default:
9095                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9096                                                                 filter_op);
9097                 ret = -ENOTSUP;
9098                 break;
9099         }
9100
9101         return ret;
9102 }
9103
9104 /* Convert ethertype filter structure */
9105 static int
9106 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9107                               struct i40e_ethertype_filter *filter)
9108 {
9109         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9110         filter->input.ether_type = input->ether_type;
9111         filter->flags = input->flags;
9112         filter->queue = input->queue;
9113
9114         return 0;
9115 }
9116
9117 /* Check if there exists the ehtertype filter */
9118 struct i40e_ethertype_filter *
9119 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9120                                 const struct i40e_ethertype_filter_input *input)
9121 {
9122         int ret;
9123
9124         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9125         if (ret < 0)
9126                 return NULL;
9127
9128         return ethertype_rule->hash_map[ret];
9129 }
9130
9131 /* Add ethertype filter in SW list */
9132 static int
9133 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9134                                 struct i40e_ethertype_filter *filter)
9135 {
9136         struct i40e_ethertype_rule *rule = &pf->ethertype;
9137         int ret;
9138
9139         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9140         if (ret < 0) {
9141                 PMD_DRV_LOG(ERR,
9142                             "Failed to insert ethertype filter"
9143                             " to hash table %d!",
9144                             ret);
9145                 return ret;
9146         }
9147         rule->hash_map[ret] = filter;
9148
9149         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9150
9151         return 0;
9152 }
9153
9154 /* Delete ethertype filter in SW list */
9155 int
9156 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9157                              struct i40e_ethertype_filter_input *input)
9158 {
9159         struct i40e_ethertype_rule *rule = &pf->ethertype;
9160         struct i40e_ethertype_filter *filter;
9161         int ret;
9162
9163         ret = rte_hash_del_key(rule->hash_table, input);
9164         if (ret < 0) {
9165                 PMD_DRV_LOG(ERR,
9166                             "Failed to delete ethertype filter"
9167                             " to hash table %d!",
9168                             ret);
9169                 return ret;
9170         }
9171         filter = rule->hash_map[ret];
9172         rule->hash_map[ret] = NULL;
9173
9174         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9175         rte_free(filter);
9176
9177         return 0;
9178 }
9179
9180 /*
9181  * Configure ethertype filter, which can director packet by filtering
9182  * with mac address and ether_type or only ether_type
9183  */
9184 int
9185 i40e_ethertype_filter_set(struct i40e_pf *pf,
9186                         struct rte_eth_ethertype_filter *filter,
9187                         bool add)
9188 {
9189         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9190         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9191         struct i40e_ethertype_filter *ethertype_filter, *node;
9192         struct i40e_ethertype_filter check_filter;
9193         struct i40e_control_filter_stats stats;
9194         uint16_t flags = 0;
9195         int ret;
9196
9197         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9198                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9199                 return -EINVAL;
9200         }
9201         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9202                 filter->ether_type == ETHER_TYPE_IPv6) {
9203                 PMD_DRV_LOG(ERR,
9204                         "unsupported ether_type(0x%04x) in control packet filter.",
9205                         filter->ether_type);
9206                 return -EINVAL;
9207         }
9208         if (filter->ether_type == ETHER_TYPE_VLAN)
9209                 PMD_DRV_LOG(WARNING,
9210                         "filter vlan ether_type in first tag is not supported.");
9211
9212         /* Check if there is the filter in SW list */
9213         memset(&check_filter, 0, sizeof(check_filter));
9214         i40e_ethertype_filter_convert(filter, &check_filter);
9215         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9216                                                &check_filter.input);
9217         if (add && node) {
9218                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9219                 return -EINVAL;
9220         }
9221
9222         if (!add && !node) {
9223                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9224                 return -EINVAL;
9225         }
9226
9227         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9228                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9229         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9230                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9231         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9232
9233         memset(&stats, 0, sizeof(stats));
9234         ret = i40e_aq_add_rem_control_packet_filter(hw,
9235                         filter->mac_addr.addr_bytes,
9236                         filter->ether_type, flags,
9237                         pf->main_vsi->seid,
9238                         filter->queue, add, &stats, NULL);
9239
9240         PMD_DRV_LOG(INFO,
9241                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9242                 ret, stats.mac_etype_used, stats.etype_used,
9243                 stats.mac_etype_free, stats.etype_free);
9244         if (ret < 0)
9245                 return -ENOSYS;
9246
9247         /* Add or delete a filter in SW list */
9248         if (add) {
9249                 ethertype_filter = rte_zmalloc("ethertype_filter",
9250                                        sizeof(*ethertype_filter), 0);
9251                 rte_memcpy(ethertype_filter, &check_filter,
9252                            sizeof(check_filter));
9253                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9254         } else {
9255                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9256         }
9257
9258         return ret;
9259 }
9260
9261 /*
9262  * Handle operations for ethertype filter.
9263  */
9264 static int
9265 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9266                                 enum rte_filter_op filter_op,
9267                                 void *arg)
9268 {
9269         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9270         int ret = 0;
9271
9272         if (filter_op == RTE_ETH_FILTER_NOP)
9273                 return ret;
9274
9275         if (arg == NULL) {
9276                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9277                             filter_op);
9278                 return -EINVAL;
9279         }
9280
9281         switch (filter_op) {
9282         case RTE_ETH_FILTER_ADD:
9283                 ret = i40e_ethertype_filter_set(pf,
9284                         (struct rte_eth_ethertype_filter *)arg,
9285                         TRUE);
9286                 break;
9287         case RTE_ETH_FILTER_DELETE:
9288                 ret = i40e_ethertype_filter_set(pf,
9289                         (struct rte_eth_ethertype_filter *)arg,
9290                         FALSE);
9291                 break;
9292         default:
9293                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9294                 ret = -ENOSYS;
9295                 break;
9296         }
9297         return ret;
9298 }
9299
9300 static int
9301 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9302                      enum rte_filter_type filter_type,
9303                      enum rte_filter_op filter_op,
9304                      void *arg)
9305 {
9306         int ret = 0;
9307
9308         if (dev == NULL)
9309                 return -EINVAL;
9310
9311         switch (filter_type) {
9312         case RTE_ETH_FILTER_NONE:
9313                 /* For global configuration */
9314                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9315                 break;
9316         case RTE_ETH_FILTER_HASH:
9317                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9318                 break;
9319         case RTE_ETH_FILTER_MACVLAN:
9320                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9321                 break;
9322         case RTE_ETH_FILTER_ETHERTYPE:
9323                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9324                 break;
9325         case RTE_ETH_FILTER_TUNNEL:
9326                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9327                 break;
9328         case RTE_ETH_FILTER_FDIR:
9329                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9330                 break;
9331         case RTE_ETH_FILTER_GENERIC:
9332                 if (filter_op != RTE_ETH_FILTER_GET)
9333                         return -EINVAL;
9334                 *(const void **)arg = &i40e_flow_ops;
9335                 break;
9336         default:
9337                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9338                                                         filter_type);
9339                 ret = -EINVAL;
9340                 break;
9341         }
9342
9343         return ret;
9344 }
9345
9346 /*
9347  * Check and enable Extended Tag.
9348  * Enabling Extended Tag is important for 40G performance.
9349  */
9350 static void
9351 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9352 {
9353         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9354         uint32_t buf = 0;
9355         int ret;
9356
9357         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9358                                       PCI_DEV_CAP_REG);
9359         if (ret < 0) {
9360                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9361                             PCI_DEV_CAP_REG);
9362                 return;
9363         }
9364         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9365                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9366                 return;
9367         }
9368
9369         buf = 0;
9370         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9371                                       PCI_DEV_CTRL_REG);
9372         if (ret < 0) {
9373                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9374                             PCI_DEV_CTRL_REG);
9375                 return;
9376         }
9377         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9378                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9379                 return;
9380         }
9381         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9382         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9383                                        PCI_DEV_CTRL_REG);
9384         if (ret < 0) {
9385                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9386                             PCI_DEV_CTRL_REG);
9387                 return;
9388         }
9389 }
9390
9391 /*
9392  * As some registers wouldn't be reset unless a global hardware reset,
9393  * hardware initialization is needed to put those registers into an
9394  * expected initial state.
9395  */
9396 static void
9397 i40e_hw_init(struct rte_eth_dev *dev)
9398 {
9399         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9400
9401         i40e_enable_extended_tag(dev);
9402
9403         /* clear the PF Queue Filter control register */
9404         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9405
9406         /* Disable symmetric hash per port */
9407         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9408 }
9409
9410 /*
9411  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9412  * however this function will return only one highest pctype index,
9413  * which is not quite correct. This is known problem of i40e driver
9414  * and needs to be fixed later.
9415  */
9416 enum i40e_filter_pctype
9417 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9418 {
9419         int i;
9420         uint64_t pctype_mask;
9421
9422         if (flow_type < I40E_FLOW_TYPE_MAX) {
9423                 pctype_mask = adapter->pctypes_tbl[flow_type];
9424                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9425                         if (pctype_mask & (1ULL << i))
9426                                 return (enum i40e_filter_pctype)i;
9427                 }
9428         }
9429         return I40E_FILTER_PCTYPE_INVALID;
9430 }
9431
9432 uint16_t
9433 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9434                         enum i40e_filter_pctype pctype)
9435 {
9436         uint16_t flowtype;
9437         uint64_t pctype_mask = 1ULL << pctype;
9438
9439         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9440              flowtype++) {
9441                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9442                         return flowtype;
9443         }
9444
9445         return RTE_ETH_FLOW_UNKNOWN;
9446 }
9447
9448 /*
9449  * On X710, performance number is far from the expectation on recent firmware
9450  * versions; on XL710, performance number is also far from the expectation on
9451  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9452  * mode is enabled and port MAC address is equal to the packet destination MAC
9453  * address. The fix for this issue may not be integrated in the following
9454  * firmware version. So the workaround in software driver is needed. It needs
9455  * to modify the initial values of 3 internal only registers for both X710 and
9456  * XL710. Note that the values for X710 or XL710 could be different, and the
9457  * workaround can be removed when it is fixed in firmware in the future.
9458  */
9459
9460 /* For both X710 and XL710 */
9461 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9462 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9463 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9464
9465 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9466 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9467
9468 /* For X722 */
9469 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9470 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9471
9472 /* For X710 */
9473 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9474 /* For XL710 */
9475 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9476 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9477
9478 static int
9479 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9480 {
9481         enum i40e_status_code status;
9482         struct i40e_aq_get_phy_abilities_resp phy_ab;
9483         int ret = -ENOTSUP;
9484         int retries = 0;
9485
9486         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9487                                               NULL);
9488
9489         while (status) {
9490                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9491                         status);
9492                 retries++;
9493                 rte_delay_us(100000);
9494                 if  (retries < 5)
9495                         status = i40e_aq_get_phy_capabilities(hw, false,
9496                                         true, &phy_ab, NULL);
9497                 else
9498                         return ret;
9499         }
9500         return 0;
9501 }
9502
9503 static void
9504 i40e_configure_registers(struct i40e_hw *hw)
9505 {
9506         static struct {
9507                 uint32_t addr;
9508                 uint64_t val;
9509         } reg_table[] = {
9510                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9511                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9512                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9513         };
9514         uint64_t reg;
9515         uint32_t i;
9516         int ret;
9517
9518         for (i = 0; i < RTE_DIM(reg_table); i++) {
9519                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9520                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9521                                 reg_table[i].val =
9522                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9523                         else /* For X710/XL710/XXV710 */
9524                                 if (hw->aq.fw_maj_ver < 6)
9525                                         reg_table[i].val =
9526                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9527                                 else
9528                                         reg_table[i].val =
9529                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9530                 }
9531
9532                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9533                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9534                                 reg_table[i].val =
9535                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9536                         else /* For X710/XL710/XXV710 */
9537                                 reg_table[i].val =
9538                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9539                 }
9540
9541                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9542                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9543                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9544                                 reg_table[i].val =
9545                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9546                         else /* For X710 */
9547                                 reg_table[i].val =
9548                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9549                 }
9550
9551                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9552                                                         &reg, NULL);
9553                 if (ret < 0) {
9554                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9555                                                         reg_table[i].addr);
9556                         break;
9557                 }
9558                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9559                                                 reg_table[i].addr, reg);
9560                 if (reg == reg_table[i].val)
9561                         continue;
9562
9563                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9564                                                 reg_table[i].val, NULL);
9565                 if (ret < 0) {
9566                         PMD_DRV_LOG(ERR,
9567                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9568                                 reg_table[i].val, reg_table[i].addr);
9569                         break;
9570                 }
9571                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9572                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9573         }
9574 }
9575
9576 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9577 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9578 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9579 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9580 static int
9581 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9582 {
9583         uint32_t reg;
9584         int ret;
9585
9586         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9587                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9588                 return -EINVAL;
9589         }
9590
9591         /* Configure for double VLAN RX stripping */
9592         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9593         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9594                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9595                 ret = i40e_aq_debug_write_register(hw,
9596                                                    I40E_VSI_TSR(vsi->vsi_id),
9597                                                    reg, NULL);
9598                 if (ret < 0) {
9599                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9600                                     vsi->vsi_id);
9601                         return I40E_ERR_CONFIG;
9602                 }
9603         }
9604
9605         /* Configure for double VLAN TX insertion */
9606         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9607         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9608                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9609                 ret = i40e_aq_debug_write_register(hw,
9610                                                    I40E_VSI_L2TAGSTXVALID(
9611                                                    vsi->vsi_id), reg, NULL);
9612                 if (ret < 0) {
9613                         PMD_DRV_LOG(ERR,
9614                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9615                                 vsi->vsi_id);
9616                         return I40E_ERR_CONFIG;
9617                 }
9618         }
9619
9620         return 0;
9621 }
9622
9623 /**
9624  * i40e_aq_add_mirror_rule
9625  * @hw: pointer to the hardware structure
9626  * @seid: VEB seid to add mirror rule to
9627  * @dst_id: destination vsi seid
9628  * @entries: Buffer which contains the entities to be mirrored
9629  * @count: number of entities contained in the buffer
9630  * @rule_id:the rule_id of the rule to be added
9631  *
9632  * Add a mirror rule for a given veb.
9633  *
9634  **/
9635 static enum i40e_status_code
9636 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9637                         uint16_t seid, uint16_t dst_id,
9638                         uint16_t rule_type, uint16_t *entries,
9639                         uint16_t count, uint16_t *rule_id)
9640 {
9641         struct i40e_aq_desc desc;
9642         struct i40e_aqc_add_delete_mirror_rule cmd;
9643         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9644                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9645                 &desc.params.raw;
9646         uint16_t buff_len;
9647         enum i40e_status_code status;
9648
9649         i40e_fill_default_direct_cmd_desc(&desc,
9650                                           i40e_aqc_opc_add_mirror_rule);
9651         memset(&cmd, 0, sizeof(cmd));
9652
9653         buff_len = sizeof(uint16_t) * count;
9654         desc.datalen = rte_cpu_to_le_16(buff_len);
9655         if (buff_len > 0)
9656                 desc.flags |= rte_cpu_to_le_16(
9657                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9658         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9659                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9660         cmd.num_entries = rte_cpu_to_le_16(count);
9661         cmd.seid = rte_cpu_to_le_16(seid);
9662         cmd.destination = rte_cpu_to_le_16(dst_id);
9663
9664         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9665         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9666         PMD_DRV_LOG(INFO,
9667                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9668                 hw->aq.asq_last_status, resp->rule_id,
9669                 resp->mirror_rules_used, resp->mirror_rules_free);
9670         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9671
9672         return status;
9673 }
9674
9675 /**
9676  * i40e_aq_del_mirror_rule
9677  * @hw: pointer to the hardware structure
9678  * @seid: VEB seid to add mirror rule to
9679  * @entries: Buffer which contains the entities to be mirrored
9680  * @count: number of entities contained in the buffer
9681  * @rule_id:the rule_id of the rule to be delete
9682  *
9683  * Delete a mirror rule for a given veb.
9684  *
9685  **/
9686 static enum i40e_status_code
9687 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9688                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9689                 uint16_t count, uint16_t rule_id)
9690 {
9691         struct i40e_aq_desc desc;
9692         struct i40e_aqc_add_delete_mirror_rule cmd;
9693         uint16_t buff_len = 0;
9694         enum i40e_status_code status;
9695         void *buff = NULL;
9696
9697         i40e_fill_default_direct_cmd_desc(&desc,
9698                                           i40e_aqc_opc_delete_mirror_rule);
9699         memset(&cmd, 0, sizeof(cmd));
9700         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9701                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9702                                                           I40E_AQ_FLAG_RD));
9703                 cmd.num_entries = count;
9704                 buff_len = sizeof(uint16_t) * count;
9705                 desc.datalen = rte_cpu_to_le_16(buff_len);
9706                 buff = (void *)entries;
9707         } else
9708                 /* rule id is filled in destination field for deleting mirror rule */
9709                 cmd.destination = rte_cpu_to_le_16(rule_id);
9710
9711         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9712                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9713         cmd.seid = rte_cpu_to_le_16(seid);
9714
9715         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9716         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9717
9718         return status;
9719 }
9720
9721 /**
9722  * i40e_mirror_rule_set
9723  * @dev: pointer to the hardware structure
9724  * @mirror_conf: mirror rule info
9725  * @sw_id: mirror rule's sw_id
9726  * @on: enable/disable
9727  *
9728  * set a mirror rule.
9729  *
9730  **/
9731 static int
9732 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9733                         struct rte_eth_mirror_conf *mirror_conf,
9734                         uint8_t sw_id, uint8_t on)
9735 {
9736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9737         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9738         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9739         struct i40e_mirror_rule *parent = NULL;
9740         uint16_t seid, dst_seid, rule_id;
9741         uint16_t i, j = 0;
9742         int ret;
9743
9744         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9745
9746         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9747                 PMD_DRV_LOG(ERR,
9748                         "mirror rule can not be configured without veb or vfs.");
9749                 return -ENOSYS;
9750         }
9751         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9752                 PMD_DRV_LOG(ERR, "mirror table is full.");
9753                 return -ENOSPC;
9754         }
9755         if (mirror_conf->dst_pool > pf->vf_num) {
9756                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9757                                  mirror_conf->dst_pool);
9758                 return -EINVAL;
9759         }
9760
9761         seid = pf->main_vsi->veb->seid;
9762
9763         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9764                 if (sw_id <= it->index) {
9765                         mirr_rule = it;
9766                         break;
9767                 }
9768                 parent = it;
9769         }
9770         if (mirr_rule && sw_id == mirr_rule->index) {
9771                 if (on) {
9772                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9773                         return -EEXIST;
9774                 } else {
9775                         ret = i40e_aq_del_mirror_rule(hw, seid,
9776                                         mirr_rule->rule_type,
9777                                         mirr_rule->entries,
9778                                         mirr_rule->num_entries, mirr_rule->id);
9779                         if (ret < 0) {
9780                                 PMD_DRV_LOG(ERR,
9781                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9782                                         ret, hw->aq.asq_last_status);
9783                                 return -ENOSYS;
9784                         }
9785                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9786                         rte_free(mirr_rule);
9787                         pf->nb_mirror_rule--;
9788                         return 0;
9789                 }
9790         } else if (!on) {
9791                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9792                 return -ENOENT;
9793         }
9794
9795         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9796                                 sizeof(struct i40e_mirror_rule) , 0);
9797         if (!mirr_rule) {
9798                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9799                 return I40E_ERR_NO_MEMORY;
9800         }
9801         switch (mirror_conf->rule_type) {
9802         case ETH_MIRROR_VLAN:
9803                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9804                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9805                                 mirr_rule->entries[j] =
9806                                         mirror_conf->vlan.vlan_id[i];
9807                                 j++;
9808                         }
9809                 }
9810                 if (j == 0) {
9811                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9812                         rte_free(mirr_rule);
9813                         return -EINVAL;
9814                 }
9815                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9816                 break;
9817         case ETH_MIRROR_VIRTUAL_POOL_UP:
9818         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9819                 /* check if the specified pool bit is out of range */
9820                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9821                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9822                         rte_free(mirr_rule);
9823                         return -EINVAL;
9824                 }
9825                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9826                         if (mirror_conf->pool_mask & (1ULL << i)) {
9827                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9828                                 j++;
9829                         }
9830                 }
9831                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9832                         /* add pf vsi to entries */
9833                         mirr_rule->entries[j] = pf->main_vsi_seid;
9834                         j++;
9835                 }
9836                 if (j == 0) {
9837                         PMD_DRV_LOG(ERR, "pool is not specified.");
9838                         rte_free(mirr_rule);
9839                         return -EINVAL;
9840                 }
9841                 /* egress and ingress in aq commands means from switch but not port */
9842                 mirr_rule->rule_type =
9843                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9844                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9845                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9846                 break;
9847         case ETH_MIRROR_UPLINK_PORT:
9848                 /* egress and ingress in aq commands means from switch but not port*/
9849                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9850                 break;
9851         case ETH_MIRROR_DOWNLINK_PORT:
9852                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9853                 break;
9854         default:
9855                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9856                         mirror_conf->rule_type);
9857                 rte_free(mirr_rule);
9858                 return -EINVAL;
9859         }
9860
9861         /* If the dst_pool is equal to vf_num, consider it as PF */
9862         if (mirror_conf->dst_pool == pf->vf_num)
9863                 dst_seid = pf->main_vsi_seid;
9864         else
9865                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9866
9867         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9868                                       mirr_rule->rule_type, mirr_rule->entries,
9869                                       j, &rule_id);
9870         if (ret < 0) {
9871                 PMD_DRV_LOG(ERR,
9872                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9873                         ret, hw->aq.asq_last_status);
9874                 rte_free(mirr_rule);
9875                 return -ENOSYS;
9876         }
9877
9878         mirr_rule->index = sw_id;
9879         mirr_rule->num_entries = j;
9880         mirr_rule->id = rule_id;
9881         mirr_rule->dst_vsi_seid = dst_seid;
9882
9883         if (parent)
9884                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9885         else
9886                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9887
9888         pf->nb_mirror_rule++;
9889         return 0;
9890 }
9891
9892 /**
9893  * i40e_mirror_rule_reset
9894  * @dev: pointer to the device
9895  * @sw_id: mirror rule's sw_id
9896  *
9897  * reset a mirror rule.
9898  *
9899  **/
9900 static int
9901 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9902 {
9903         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9904         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9905         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9906         uint16_t seid;
9907         int ret;
9908
9909         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9910
9911         seid = pf->main_vsi->veb->seid;
9912
9913         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9914                 if (sw_id == it->index) {
9915                         mirr_rule = it;
9916                         break;
9917                 }
9918         }
9919         if (mirr_rule) {
9920                 ret = i40e_aq_del_mirror_rule(hw, seid,
9921                                 mirr_rule->rule_type,
9922                                 mirr_rule->entries,
9923                                 mirr_rule->num_entries, mirr_rule->id);
9924                 if (ret < 0) {
9925                         PMD_DRV_LOG(ERR,
9926                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9927                                 ret, hw->aq.asq_last_status);
9928                         return -ENOSYS;
9929                 }
9930                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9931                 rte_free(mirr_rule);
9932                 pf->nb_mirror_rule--;
9933         } else {
9934                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9935                 return -ENOENT;
9936         }
9937         return 0;
9938 }
9939
9940 static uint64_t
9941 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9942 {
9943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9944         uint64_t systim_cycles;
9945
9946         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9947         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9948                         << 32;
9949
9950         return systim_cycles;
9951 }
9952
9953 static uint64_t
9954 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9955 {
9956         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9957         uint64_t rx_tstamp;
9958
9959         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9960         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9961                         << 32;
9962
9963         return rx_tstamp;
9964 }
9965
9966 static uint64_t
9967 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9968 {
9969         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9970         uint64_t tx_tstamp;
9971
9972         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9973         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9974                         << 32;
9975
9976         return tx_tstamp;
9977 }
9978
9979 static void
9980 i40e_start_timecounters(struct rte_eth_dev *dev)
9981 {
9982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9983         struct i40e_adapter *adapter =
9984                         (struct i40e_adapter *)dev->data->dev_private;
9985         struct rte_eth_link link;
9986         uint32_t tsync_inc_l;
9987         uint32_t tsync_inc_h;
9988
9989         /* Get current link speed. */
9990         memset(&link, 0, sizeof(link));
9991         i40e_dev_link_update(dev, 1);
9992         rte_i40e_dev_atomic_read_link_status(dev, &link);
9993
9994         switch (link.link_speed) {
9995         case ETH_SPEED_NUM_40G:
9996                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9997                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9998                 break;
9999         case ETH_SPEED_NUM_10G:
10000                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10001                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10002                 break;
10003         case ETH_SPEED_NUM_1G:
10004                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10005                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10006                 break;
10007         default:
10008                 tsync_inc_l = 0x0;
10009                 tsync_inc_h = 0x0;
10010         }
10011
10012         /* Set the timesync increment value. */
10013         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10014         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10015
10016         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10017         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10018         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10019
10020         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10021         adapter->systime_tc.cc_shift = 0;
10022         adapter->systime_tc.nsec_mask = 0;
10023
10024         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10025         adapter->rx_tstamp_tc.cc_shift = 0;
10026         adapter->rx_tstamp_tc.nsec_mask = 0;
10027
10028         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10029         adapter->tx_tstamp_tc.cc_shift = 0;
10030         adapter->tx_tstamp_tc.nsec_mask = 0;
10031 }
10032
10033 static int
10034 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10035 {
10036         struct i40e_adapter *adapter =
10037                         (struct i40e_adapter *)dev->data->dev_private;
10038
10039         adapter->systime_tc.nsec += delta;
10040         adapter->rx_tstamp_tc.nsec += delta;
10041         adapter->tx_tstamp_tc.nsec += delta;
10042
10043         return 0;
10044 }
10045
10046 static int
10047 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10048 {
10049         uint64_t ns;
10050         struct i40e_adapter *adapter =
10051                         (struct i40e_adapter *)dev->data->dev_private;
10052
10053         ns = rte_timespec_to_ns(ts);
10054
10055         /* Set the timecounters to a new value. */
10056         adapter->systime_tc.nsec = ns;
10057         adapter->rx_tstamp_tc.nsec = ns;
10058         adapter->tx_tstamp_tc.nsec = ns;
10059
10060         return 0;
10061 }
10062
10063 static int
10064 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10065 {
10066         uint64_t ns, systime_cycles;
10067         struct i40e_adapter *adapter =
10068                         (struct i40e_adapter *)dev->data->dev_private;
10069
10070         systime_cycles = i40e_read_systime_cyclecounter(dev);
10071         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10072         *ts = rte_ns_to_timespec(ns);
10073
10074         return 0;
10075 }
10076
10077 static int
10078 i40e_timesync_enable(struct rte_eth_dev *dev)
10079 {
10080         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10081         uint32_t tsync_ctl_l;
10082         uint32_t tsync_ctl_h;
10083
10084         /* Stop the timesync system time. */
10085         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10086         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10087         /* Reset the timesync system time value. */
10088         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10089         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10090
10091         i40e_start_timecounters(dev);
10092
10093         /* Clear timesync registers. */
10094         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10095         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10096         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10097         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10098         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10099         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10100
10101         /* Enable timestamping of PTP packets. */
10102         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10103         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10104
10105         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10106         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10107         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10108
10109         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10110         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10111
10112         return 0;
10113 }
10114
10115 static int
10116 i40e_timesync_disable(struct rte_eth_dev *dev)
10117 {
10118         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10119         uint32_t tsync_ctl_l;
10120         uint32_t tsync_ctl_h;
10121
10122         /* Disable timestamping of transmitted PTP packets. */
10123         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10124         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10125
10126         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10127         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10128
10129         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10130         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10131
10132         /* Reset the timesync increment value. */
10133         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10134         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10135
10136         return 0;
10137 }
10138
10139 static int
10140 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10141                                 struct timespec *timestamp, uint32_t flags)
10142 {
10143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10144         struct i40e_adapter *adapter =
10145                 (struct i40e_adapter *)dev->data->dev_private;
10146
10147         uint32_t sync_status;
10148         uint32_t index = flags & 0x03;
10149         uint64_t rx_tstamp_cycles;
10150         uint64_t ns;
10151
10152         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10153         if ((sync_status & (1 << index)) == 0)
10154                 return -EINVAL;
10155
10156         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10157         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10158         *timestamp = rte_ns_to_timespec(ns);
10159
10160         return 0;
10161 }
10162
10163 static int
10164 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10165                                 struct timespec *timestamp)
10166 {
10167         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10168         struct i40e_adapter *adapter =
10169                 (struct i40e_adapter *)dev->data->dev_private;
10170
10171         uint32_t sync_status;
10172         uint64_t tx_tstamp_cycles;
10173         uint64_t ns;
10174
10175         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10176         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10177                 return -EINVAL;
10178
10179         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10180         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10181         *timestamp = rte_ns_to_timespec(ns);
10182
10183         return 0;
10184 }
10185
10186 /*
10187  * i40e_parse_dcb_configure - parse dcb configure from user
10188  * @dev: the device being configured
10189  * @dcb_cfg: pointer of the result of parse
10190  * @*tc_map: bit map of enabled traffic classes
10191  *
10192  * Returns 0 on success, negative value on failure
10193  */
10194 static int
10195 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10196                          struct i40e_dcbx_config *dcb_cfg,
10197                          uint8_t *tc_map)
10198 {
10199         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10200         uint8_t i, tc_bw, bw_lf;
10201
10202         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10203
10204         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10205         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10206                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10207                 return -EINVAL;
10208         }
10209
10210         /* assume each tc has the same bw */
10211         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10212         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10213                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10214         /* to ensure the sum of tcbw is equal to 100 */
10215         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10216         for (i = 0; i < bw_lf; i++)
10217                 dcb_cfg->etscfg.tcbwtable[i]++;
10218
10219         /* assume each tc has the same Transmission Selection Algorithm */
10220         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10221                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10222
10223         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10224                 dcb_cfg->etscfg.prioritytable[i] =
10225                                 dcb_rx_conf->dcb_tc[i];
10226
10227         /* FW needs one App to configure HW */
10228         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10229         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10230         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10231         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10232
10233         if (dcb_rx_conf->nb_tcs == 0)
10234                 *tc_map = 1; /* tc0 only */
10235         else
10236                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10237
10238         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10239                 dcb_cfg->pfc.willing = 0;
10240                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10241                 dcb_cfg->pfc.pfcenable = *tc_map;
10242         }
10243         return 0;
10244 }
10245
10246
10247 static enum i40e_status_code
10248 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10249                               struct i40e_aqc_vsi_properties_data *info,
10250                               uint8_t enabled_tcmap)
10251 {
10252         enum i40e_status_code ret;
10253         int i, total_tc = 0;
10254         uint16_t qpnum_per_tc, bsf, qp_idx;
10255         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10256         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10257         uint16_t used_queues;
10258
10259         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10260         if (ret != I40E_SUCCESS)
10261                 return ret;
10262
10263         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10264                 if (enabled_tcmap & (1 << i))
10265                         total_tc++;
10266         }
10267         if (total_tc == 0)
10268                 total_tc = 1;
10269         vsi->enabled_tc = enabled_tcmap;
10270
10271         /* different VSI has different queues assigned */
10272         if (vsi->type == I40E_VSI_MAIN)
10273                 used_queues = dev_data->nb_rx_queues -
10274                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10275         else if (vsi->type == I40E_VSI_VMDQ2)
10276                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10277         else {
10278                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10279                 return I40E_ERR_NO_AVAILABLE_VSI;
10280         }
10281
10282         qpnum_per_tc = used_queues / total_tc;
10283         /* Number of queues per enabled TC */
10284         if (qpnum_per_tc == 0) {
10285                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10286                 return I40E_ERR_INVALID_QP_ID;
10287         }
10288         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10289                                 I40E_MAX_Q_PER_TC);
10290         bsf = rte_bsf32(qpnum_per_tc);
10291
10292         /**
10293          * Configure TC and queue mapping parameters, for enabled TC,
10294          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10295          * default queue will serve it.
10296          */
10297         qp_idx = 0;
10298         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10299                 if (vsi->enabled_tc & (1 << i)) {
10300                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10301                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10302                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10303                         qp_idx += qpnum_per_tc;
10304                 } else
10305                         info->tc_mapping[i] = 0;
10306         }
10307
10308         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10309         if (vsi->type == I40E_VSI_SRIOV) {
10310                 info->mapping_flags |=
10311                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10312                 for (i = 0; i < vsi->nb_qps; i++)
10313                         info->queue_mapping[i] =
10314                                 rte_cpu_to_le_16(vsi->base_queue + i);
10315         } else {
10316                 info->mapping_flags |=
10317                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10318                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10319         }
10320         info->valid_sections |=
10321                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10322
10323         return I40E_SUCCESS;
10324 }
10325
10326 /*
10327  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10328  * @veb: VEB to be configured
10329  * @tc_map: enabled TC bitmap
10330  *
10331  * Returns 0 on success, negative value on failure
10332  */
10333 static enum i40e_status_code
10334 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10335 {
10336         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10337         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10338         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10339         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10340         enum i40e_status_code ret = I40E_SUCCESS;
10341         int i;
10342         uint32_t bw_max;
10343
10344         /* Check if enabled_tc is same as existing or new TCs */
10345         if (veb->enabled_tc == tc_map)
10346                 return ret;
10347
10348         /* configure tc bandwidth */
10349         memset(&veb_bw, 0, sizeof(veb_bw));
10350         veb_bw.tc_valid_bits = tc_map;
10351         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10352         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10353                 if (tc_map & BIT_ULL(i))
10354                         veb_bw.tc_bw_share_credits[i] = 1;
10355         }
10356         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10357                                                    &veb_bw, NULL);
10358         if (ret) {
10359                 PMD_INIT_LOG(ERR,
10360                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10361                         hw->aq.asq_last_status);
10362                 return ret;
10363         }
10364
10365         memset(&ets_query, 0, sizeof(ets_query));
10366         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10367                                                    &ets_query, NULL);
10368         if (ret != I40E_SUCCESS) {
10369                 PMD_DRV_LOG(ERR,
10370                         "Failed to get switch_comp ETS configuration %u",
10371                         hw->aq.asq_last_status);
10372                 return ret;
10373         }
10374         memset(&bw_query, 0, sizeof(bw_query));
10375         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10376                                                   &bw_query, NULL);
10377         if (ret != I40E_SUCCESS) {
10378                 PMD_DRV_LOG(ERR,
10379                         "Failed to get switch_comp bandwidth configuration %u",
10380                         hw->aq.asq_last_status);
10381                 return ret;
10382         }
10383
10384         /* store and print out BW info */
10385         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10386         veb->bw_info.bw_max = ets_query.tc_bw_max;
10387         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10388         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10389         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10390                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10391                      I40E_16_BIT_WIDTH);
10392         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10393                 veb->bw_info.bw_ets_share_credits[i] =
10394                                 bw_query.tc_bw_share_credits[i];
10395                 veb->bw_info.bw_ets_credits[i] =
10396                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10397                 /* 4 bits per TC, 4th bit is reserved */
10398                 veb->bw_info.bw_ets_max[i] =
10399                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10400                                   RTE_LEN2MASK(3, uint8_t));
10401                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10402                             veb->bw_info.bw_ets_share_credits[i]);
10403                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10404                             veb->bw_info.bw_ets_credits[i]);
10405                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10406                             veb->bw_info.bw_ets_max[i]);
10407         }
10408
10409         veb->enabled_tc = tc_map;
10410
10411         return ret;
10412 }
10413
10414
10415 /*
10416  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10417  * @vsi: VSI to be configured
10418  * @tc_map: enabled TC bitmap
10419  *
10420  * Returns 0 on success, negative value on failure
10421  */
10422 static enum i40e_status_code
10423 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10424 {
10425         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10426         struct i40e_vsi_context ctxt;
10427         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10428         enum i40e_status_code ret = I40E_SUCCESS;
10429         int i;
10430
10431         /* Check if enabled_tc is same as existing or new TCs */
10432         if (vsi->enabled_tc == tc_map)
10433                 return ret;
10434
10435         /* configure tc bandwidth */
10436         memset(&bw_data, 0, sizeof(bw_data));
10437         bw_data.tc_valid_bits = tc_map;
10438         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10439         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10440                 if (tc_map & BIT_ULL(i))
10441                         bw_data.tc_bw_credits[i] = 1;
10442         }
10443         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10444         if (ret) {
10445                 PMD_INIT_LOG(ERR,
10446                         "AQ command Config VSI BW allocation per TC failed = %d",
10447                         hw->aq.asq_last_status);
10448                 goto out;
10449         }
10450         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10451                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10452
10453         /* Update Queue Pairs Mapping for currently enabled UPs */
10454         ctxt.seid = vsi->seid;
10455         ctxt.pf_num = hw->pf_id;
10456         ctxt.vf_num = 0;
10457         ctxt.uplink_seid = vsi->uplink_seid;
10458         ctxt.info = vsi->info;
10459         i40e_get_cap(hw);
10460         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10461         if (ret)
10462                 goto out;
10463
10464         /* Update the VSI after updating the VSI queue-mapping information */
10465         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10466         if (ret) {
10467                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10468                         hw->aq.asq_last_status);
10469                 goto out;
10470         }
10471         /* update the local VSI info with updated queue map */
10472         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10473                                         sizeof(vsi->info.tc_mapping));
10474         rte_memcpy(&vsi->info.queue_mapping,
10475                         &ctxt.info.queue_mapping,
10476                 sizeof(vsi->info.queue_mapping));
10477         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10478         vsi->info.valid_sections = 0;
10479
10480         /* query and update current VSI BW information */
10481         ret = i40e_vsi_get_bw_config(vsi);
10482         if (ret) {
10483                 PMD_INIT_LOG(ERR,
10484                          "Failed updating vsi bw info, err %s aq_err %s",
10485                          i40e_stat_str(hw, ret),
10486                          i40e_aq_str(hw, hw->aq.asq_last_status));
10487                 goto out;
10488         }
10489
10490         vsi->enabled_tc = tc_map;
10491
10492 out:
10493         return ret;
10494 }
10495
10496 /*
10497  * i40e_dcb_hw_configure - program the dcb setting to hw
10498  * @pf: pf the configuration is taken on
10499  * @new_cfg: new configuration
10500  * @tc_map: enabled TC bitmap
10501  *
10502  * Returns 0 on success, negative value on failure
10503  */
10504 static enum i40e_status_code
10505 i40e_dcb_hw_configure(struct i40e_pf *pf,
10506                       struct i40e_dcbx_config *new_cfg,
10507                       uint8_t tc_map)
10508 {
10509         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10510         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10511         struct i40e_vsi *main_vsi = pf->main_vsi;
10512         struct i40e_vsi_list *vsi_list;
10513         enum i40e_status_code ret;
10514         int i;
10515         uint32_t val;
10516
10517         /* Use the FW API if FW > v4.4*/
10518         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10519               (hw->aq.fw_maj_ver >= 5))) {
10520                 PMD_INIT_LOG(ERR,
10521                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10522                 return I40E_ERR_FIRMWARE_API_VERSION;
10523         }
10524
10525         /* Check if need reconfiguration */
10526         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10527                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10528                 return I40E_SUCCESS;
10529         }
10530
10531         /* Copy the new config to the current config */
10532         *old_cfg = *new_cfg;
10533         old_cfg->etsrec = old_cfg->etscfg;
10534         ret = i40e_set_dcb_config(hw);
10535         if (ret) {
10536                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10537                          i40e_stat_str(hw, ret),
10538                          i40e_aq_str(hw, hw->aq.asq_last_status));
10539                 return ret;
10540         }
10541         /* set receive Arbiter to RR mode and ETS scheme by default */
10542         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10543                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10544                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10545                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10546                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10547                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10548                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10549                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10550                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10551                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10552                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10553                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10554                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10555         }
10556         /* get local mib to check whether it is configured correctly */
10557         /* IEEE mode */
10558         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10559         /* Get Local DCB Config */
10560         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10561                                      &hw->local_dcbx_config);
10562
10563         /* if Veb is created, need to update TC of it at first */
10564         if (main_vsi->veb) {
10565                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10566                 if (ret)
10567                         PMD_INIT_LOG(WARNING,
10568                                  "Failed configuring TC for VEB seid=%d",
10569                                  main_vsi->veb->seid);
10570         }
10571         /* Update each VSI */
10572         i40e_vsi_config_tc(main_vsi, tc_map);
10573         if (main_vsi->veb) {
10574                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10575                         /* Beside main VSI and VMDQ VSIs, only enable default
10576                          * TC for other VSIs
10577                          */
10578                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10579                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10580                                                          tc_map);
10581                         else
10582                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10583                                                          I40E_DEFAULT_TCMAP);
10584                         if (ret)
10585                                 PMD_INIT_LOG(WARNING,
10586                                         "Failed configuring TC for VSI seid=%d",
10587                                         vsi_list->vsi->seid);
10588                         /* continue */
10589                 }
10590         }
10591         return I40E_SUCCESS;
10592 }
10593
10594 /*
10595  * i40e_dcb_init_configure - initial dcb config
10596  * @dev: device being configured
10597  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10598  *
10599  * Returns 0 on success, negative value on failure
10600  */
10601 int
10602 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10603 {
10604         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10605         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10606         int i, ret = 0;
10607
10608         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10609                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10610                 return -ENOTSUP;
10611         }
10612
10613         /* DCB initialization:
10614          * Update DCB configuration from the Firmware and configure
10615          * LLDP MIB change event.
10616          */
10617         if (sw_dcb == TRUE) {
10618                 ret = i40e_init_dcb(hw);
10619                 /* If lldp agent is stopped, the return value from
10620                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10621                  * adminq status. Otherwise, it should return success.
10622                  */
10623                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10624                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10625                         memset(&hw->local_dcbx_config, 0,
10626                                 sizeof(struct i40e_dcbx_config));
10627                         /* set dcb default configuration */
10628                         hw->local_dcbx_config.etscfg.willing = 0;
10629                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10630                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10631                         hw->local_dcbx_config.etscfg.tsatable[0] =
10632                                                 I40E_IEEE_TSA_ETS;
10633                         /* all UPs mapping to TC0 */
10634                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10635                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10636                         hw->local_dcbx_config.etsrec =
10637                                 hw->local_dcbx_config.etscfg;
10638                         hw->local_dcbx_config.pfc.willing = 0;
10639                         hw->local_dcbx_config.pfc.pfccap =
10640                                                 I40E_MAX_TRAFFIC_CLASS;
10641                         /* FW needs one App to configure HW */
10642                         hw->local_dcbx_config.numapps = 1;
10643                         hw->local_dcbx_config.app[0].selector =
10644                                                 I40E_APP_SEL_ETHTYPE;
10645                         hw->local_dcbx_config.app[0].priority = 3;
10646                         hw->local_dcbx_config.app[0].protocolid =
10647                                                 I40E_APP_PROTOID_FCOE;
10648                         ret = i40e_set_dcb_config(hw);
10649                         if (ret) {
10650                                 PMD_INIT_LOG(ERR,
10651                                         "default dcb config fails. err = %d, aq_err = %d.",
10652                                         ret, hw->aq.asq_last_status);
10653                                 return -ENOSYS;
10654                         }
10655                 } else {
10656                         PMD_INIT_LOG(ERR,
10657                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10658                                 ret, hw->aq.asq_last_status);
10659                         return -ENOTSUP;
10660                 }
10661         } else {
10662                 ret = i40e_aq_start_lldp(hw, NULL);
10663                 if (ret != I40E_SUCCESS)
10664                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10665
10666                 ret = i40e_init_dcb(hw);
10667                 if (!ret) {
10668                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10669                                 PMD_INIT_LOG(ERR,
10670                                         "HW doesn't support DCBX offload.");
10671                                 return -ENOTSUP;
10672                         }
10673                 } else {
10674                         PMD_INIT_LOG(ERR,
10675                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10676                                 ret, hw->aq.asq_last_status);
10677                         return -ENOTSUP;
10678                 }
10679         }
10680         return 0;
10681 }
10682
10683 /*
10684  * i40e_dcb_setup - setup dcb related config
10685  * @dev: device being configured
10686  *
10687  * Returns 0 on success, negative value on failure
10688  */
10689 static int
10690 i40e_dcb_setup(struct rte_eth_dev *dev)
10691 {
10692         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10693         struct i40e_dcbx_config dcb_cfg;
10694         uint8_t tc_map = 0;
10695         int ret = 0;
10696
10697         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10698                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10699                 return -ENOTSUP;
10700         }
10701
10702         if (pf->vf_num != 0)
10703                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10704
10705         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10706         if (ret) {
10707                 PMD_INIT_LOG(ERR, "invalid dcb config");
10708                 return -EINVAL;
10709         }
10710         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10711         if (ret) {
10712                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10713                 return -ENOSYS;
10714         }
10715
10716         return 0;
10717 }
10718
10719 static int
10720 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10721                       struct rte_eth_dcb_info *dcb_info)
10722 {
10723         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10724         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10725         struct i40e_vsi *vsi = pf->main_vsi;
10726         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10727         uint16_t bsf, tc_mapping;
10728         int i, j = 0;
10729
10730         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10731                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10732         else
10733                 dcb_info->nb_tcs = 1;
10734         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10735                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10736         for (i = 0; i < dcb_info->nb_tcs; i++)
10737                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10738
10739         /* get queue mapping if vmdq is disabled */
10740         if (!pf->nb_cfg_vmdq_vsi) {
10741                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10742                         if (!(vsi->enabled_tc & (1 << i)))
10743                                 continue;
10744                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10745                         dcb_info->tc_queue.tc_rxq[j][i].base =
10746                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10747                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10748                         dcb_info->tc_queue.tc_txq[j][i].base =
10749                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10750                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10751                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10752                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10753                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10754                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10755                 }
10756                 return 0;
10757         }
10758
10759         /* get queue mapping if vmdq is enabled */
10760         do {
10761                 vsi = pf->vmdq[j].vsi;
10762                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10763                         if (!(vsi->enabled_tc & (1 << i)))
10764                                 continue;
10765                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10766                         dcb_info->tc_queue.tc_rxq[j][i].base =
10767                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10768                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10769                         dcb_info->tc_queue.tc_txq[j][i].base =
10770                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10771                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10772                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10773                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10774                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10775                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10776                 }
10777                 j++;
10778         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10779         return 0;
10780 }
10781
10782 static int
10783 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10784 {
10785         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10786         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10787         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10788         uint16_t interval =
10789                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10790         uint16_t msix_intr;
10791
10792         msix_intr = intr_handle->intr_vec[queue_id];
10793         if (msix_intr == I40E_MISC_VEC_ID)
10794                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10795                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10796                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10797                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10798                                (interval <<
10799                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10800         else
10801                 I40E_WRITE_REG(hw,
10802                                I40E_PFINT_DYN_CTLN(msix_intr -
10803                                                    I40E_RX_VEC_START),
10804                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10805                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10806                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10807                                (interval <<
10808                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10809
10810         I40E_WRITE_FLUSH(hw);
10811         rte_intr_enable(&pci_dev->intr_handle);
10812
10813         return 0;
10814 }
10815
10816 static int
10817 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10818 {
10819         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10820         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10821         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10822         uint16_t msix_intr;
10823
10824         msix_intr = intr_handle->intr_vec[queue_id];
10825         if (msix_intr == I40E_MISC_VEC_ID)
10826                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10827         else
10828                 I40E_WRITE_REG(hw,
10829                                I40E_PFINT_DYN_CTLN(msix_intr -
10830                                                    I40E_RX_VEC_START),
10831                                0);
10832         I40E_WRITE_FLUSH(hw);
10833
10834         return 0;
10835 }
10836
10837 static int i40e_get_regs(struct rte_eth_dev *dev,
10838                          struct rte_dev_reg_info *regs)
10839 {
10840         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10841         uint32_t *ptr_data = regs->data;
10842         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10843         const struct i40e_reg_info *reg_info;
10844
10845         if (ptr_data == NULL) {
10846                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10847                 regs->width = sizeof(uint32_t);
10848                 return 0;
10849         }
10850
10851         /* The first few registers have to be read using AQ operations */
10852         reg_idx = 0;
10853         while (i40e_regs_adminq[reg_idx].name) {
10854                 reg_info = &i40e_regs_adminq[reg_idx++];
10855                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10856                         for (arr_idx2 = 0;
10857                                         arr_idx2 <= reg_info->count2;
10858                                         arr_idx2++) {
10859                                 reg_offset = arr_idx * reg_info->stride1 +
10860                                         arr_idx2 * reg_info->stride2;
10861                                 reg_offset += reg_info->base_addr;
10862                                 ptr_data[reg_offset >> 2] =
10863                                         i40e_read_rx_ctl(hw, reg_offset);
10864                         }
10865         }
10866
10867         /* The remaining registers can be read using primitives */
10868         reg_idx = 0;
10869         while (i40e_regs_others[reg_idx].name) {
10870                 reg_info = &i40e_regs_others[reg_idx++];
10871                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10872                         for (arr_idx2 = 0;
10873                                         arr_idx2 <= reg_info->count2;
10874                                         arr_idx2++) {
10875                                 reg_offset = arr_idx * reg_info->stride1 +
10876                                         arr_idx2 * reg_info->stride2;
10877                                 reg_offset += reg_info->base_addr;
10878                                 ptr_data[reg_offset >> 2] =
10879                                         I40E_READ_REG(hw, reg_offset);
10880                         }
10881         }
10882
10883         return 0;
10884 }
10885
10886 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10887 {
10888         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10889
10890         /* Convert word count to byte count */
10891         return hw->nvm.sr_size << 1;
10892 }
10893
10894 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10895                            struct rte_dev_eeprom_info *eeprom)
10896 {
10897         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10898         uint16_t *data = eeprom->data;
10899         uint16_t offset, length, cnt_words;
10900         int ret_code;
10901
10902         offset = eeprom->offset >> 1;
10903         length = eeprom->length >> 1;
10904         cnt_words = length;
10905
10906         if (offset > hw->nvm.sr_size ||
10907                 offset + length > hw->nvm.sr_size) {
10908                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10909                 return -EINVAL;
10910         }
10911
10912         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10913
10914         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10915         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10916                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10917                 return -EIO;
10918         }
10919
10920         return 0;
10921 }
10922
10923 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10924                                       struct ether_addr *mac_addr)
10925 {
10926         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10927
10928         if (!is_valid_assigned_ether_addr(mac_addr)) {
10929                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10930                 return;
10931         }
10932
10933         /* Flags: 0x3 updates port address */
10934         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10935 }
10936
10937 static int
10938 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10939 {
10940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10941         struct rte_eth_dev_data *dev_data = pf->dev_data;
10942         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10943         int ret = 0;
10944
10945         /* check if mtu is within the allowed range */
10946         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10947                 return -EINVAL;
10948
10949         /* mtu setting is forbidden if port is start */
10950         if (dev_data->dev_started) {
10951                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10952                             dev_data->port_id);
10953                 return -EBUSY;
10954         }
10955
10956         if (frame_size > ETHER_MAX_LEN)
10957                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10958         else
10959                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10960
10961         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10962
10963         return ret;
10964 }
10965
10966 /* Restore ethertype filter */
10967 static void
10968 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10969 {
10970         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10971         struct i40e_ethertype_filter_list
10972                 *ethertype_list = &pf->ethertype.ethertype_list;
10973         struct i40e_ethertype_filter *f;
10974         struct i40e_control_filter_stats stats;
10975         uint16_t flags;
10976
10977         TAILQ_FOREACH(f, ethertype_list, rules) {
10978                 flags = 0;
10979                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10980                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10981                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10982                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10983                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10984
10985                 memset(&stats, 0, sizeof(stats));
10986                 i40e_aq_add_rem_control_packet_filter(hw,
10987                                             f->input.mac_addr.addr_bytes,
10988                                             f->input.ether_type,
10989                                             flags, pf->main_vsi->seid,
10990                                             f->queue, 1, &stats, NULL);
10991         }
10992         PMD_DRV_LOG(INFO, "Ethertype filter:"
10993                     " mac_etype_used = %u, etype_used = %u,"
10994                     " mac_etype_free = %u, etype_free = %u",
10995                     stats.mac_etype_used, stats.etype_used,
10996                     stats.mac_etype_free, stats.etype_free);
10997 }
10998
10999 /* Restore tunnel filter */
11000 static void
11001 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11002 {
11003         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11004         struct i40e_vsi *vsi;
11005         struct i40e_pf_vf *vf;
11006         struct i40e_tunnel_filter_list
11007                 *tunnel_list = &pf->tunnel.tunnel_list;
11008         struct i40e_tunnel_filter *f;
11009         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11010         bool big_buffer = 0;
11011
11012         TAILQ_FOREACH(f, tunnel_list, rules) {
11013                 if (!f->is_to_vf)
11014                         vsi = pf->main_vsi;
11015                 else {
11016                         vf = &pf->vfs[f->vf_id];
11017                         vsi = vf->vsi;
11018                 }
11019                 memset(&cld_filter, 0, sizeof(cld_filter));
11020                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11021                         (struct ether_addr *)&cld_filter.element.outer_mac);
11022                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11023                         (struct ether_addr *)&cld_filter.element.inner_mac);
11024                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11025                 cld_filter.element.flags = f->input.flags;
11026                 cld_filter.element.tenant_id = f->input.tenant_id;
11027                 cld_filter.element.queue_number = f->queue;
11028                 rte_memcpy(cld_filter.general_fields,
11029                            f->input.general_fields,
11030                            sizeof(f->input.general_fields));
11031
11032                 if (((f->input.flags &
11033                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11034                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11035                     ((f->input.flags &
11036                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11037                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11038                     ((f->input.flags &
11039                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11040                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11041                         big_buffer = 1;
11042
11043                 if (big_buffer)
11044                         i40e_aq_add_cloud_filters_big_buffer(hw,
11045                                              vsi->seid, &cld_filter, 1);
11046                 else
11047                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11048                                                   &cld_filter.element, 1);
11049         }
11050 }
11051
11052 static void
11053 i40e_filter_restore(struct i40e_pf *pf)
11054 {
11055         i40e_ethertype_filter_restore(pf);
11056         i40e_tunnel_filter_restore(pf);
11057         i40e_fdir_filter_restore(pf);
11058 }
11059
11060 static bool
11061 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11062 {
11063         if (strcmp(dev->device->driver->name, drv->driver.name))
11064                 return false;
11065
11066         return true;
11067 }
11068
11069 bool
11070 is_i40e_supported(struct rte_eth_dev *dev)
11071 {
11072         return is_device_supported(dev, &rte_i40e_pmd);
11073 }
11074
11075 struct i40e_customized_pctype*
11076 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11077 {
11078         int i;
11079
11080         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11081                 if (pf->customized_pctype[i].index == index)
11082                         return &pf->customized_pctype[i];
11083         }
11084         return NULL;
11085 }
11086
11087 static int
11088 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11089                               uint32_t pkg_size, uint32_t proto_num,
11090                               struct rte_pmd_i40e_proto_info *proto)
11091 {
11092         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11093         uint32_t pctype_num;
11094         struct rte_pmd_i40e_ptype_info *pctype;
11095         uint32_t buff_size;
11096         struct i40e_customized_pctype *new_pctype = NULL;
11097         uint8_t proto_id;
11098         uint8_t pctype_value;
11099         char name[64];
11100         uint32_t i, j, n;
11101         int ret;
11102
11103         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11104                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11105                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11106         if (ret) {
11107                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11108                 return -1;
11109         }
11110         if (!pctype_num) {
11111                 PMD_DRV_LOG(INFO, "No new pctype added");
11112                 return -1;
11113         }
11114
11115         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11116         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11117         if (!pctype) {
11118                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11119                 return -1;
11120         }
11121         /* get information about new pctype list */
11122         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11123                                         (uint8_t *)pctype, buff_size,
11124                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11125         if (ret) {
11126                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11127                 rte_free(pctype);
11128                 return -1;
11129         }
11130
11131         /* Update customized pctype. */
11132         for (i = 0; i < pctype_num; i++) {
11133                 pctype_value = pctype[i].ptype_id;
11134                 memset(name, 0, sizeof(name));
11135                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11136                         proto_id = pctype[i].protocols[j];
11137                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11138                                 continue;
11139                         for (n = 0; n < proto_num; n++) {
11140                                 if (proto[n].proto_id != proto_id)
11141                                         continue;
11142                                 strcat(name, proto[n].name);
11143                                 strcat(name, "_");
11144                                 break;
11145                         }
11146                 }
11147                 name[strlen(name) - 1] = '\0';
11148                 if (!strcmp(name, "GTPC"))
11149                         new_pctype =
11150                                 i40e_find_customized_pctype(pf,
11151                                                       I40E_CUSTOMIZED_GTPC);
11152                 else if (!strcmp(name, "GTPU_IPV4"))
11153                         new_pctype =
11154                                 i40e_find_customized_pctype(pf,
11155                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11156                 else if (!strcmp(name, "GTPU_IPV6"))
11157                         new_pctype =
11158                                 i40e_find_customized_pctype(pf,
11159                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11160                 else if (!strcmp(name, "GTPU"))
11161                         new_pctype =
11162                                 i40e_find_customized_pctype(pf,
11163                                                       I40E_CUSTOMIZED_GTPU);
11164                 if (new_pctype) {
11165                         new_pctype->pctype = pctype_value;
11166                         new_pctype->valid = true;
11167                 }
11168         }
11169
11170         rte_free(pctype);
11171         return 0;
11172 }
11173
11174 static int
11175 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11176                                uint32_t pkg_size, uint32_t proto_num,
11177                                struct rte_pmd_i40e_proto_info *proto)
11178 {
11179         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11180         uint16_t port_id = dev->data->port_id;
11181         uint32_t ptype_num;
11182         struct rte_pmd_i40e_ptype_info *ptype;
11183         uint32_t buff_size;
11184         uint8_t proto_id;
11185         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11186         uint32_t i, j, n;
11187         bool in_tunnel;
11188         int ret;
11189
11190         /* get information about new ptype num */
11191         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11192                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11193                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11194         if (ret) {
11195                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11196                 return ret;
11197         }
11198         if (!ptype_num) {
11199                 PMD_DRV_LOG(INFO, "No new ptype added");
11200                 return -1;
11201         }
11202
11203         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11204         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11205         if (!ptype) {
11206                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11207                 return -1;
11208         }
11209
11210         /* get information about new ptype list */
11211         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11212                                         (uint8_t *)ptype, buff_size,
11213                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11214         if (ret) {
11215                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11216                 rte_free(ptype);
11217                 return ret;
11218         }
11219
11220         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11221         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11222         if (!ptype_mapping) {
11223                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11224                 rte_free(ptype);
11225                 return -1;
11226         }
11227
11228         /* Update ptype mapping table. */
11229         for (i = 0; i < ptype_num; i++) {
11230                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11231                 ptype_mapping[i].sw_ptype = 0;
11232                 in_tunnel = false;
11233                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11234                         proto_id = ptype[i].protocols[j];
11235                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11236                                 continue;
11237                         for (n = 0; n < proto_num; n++) {
11238                                 if (proto[n].proto_id != proto_id)
11239                                         continue;
11240                                 memset(name, 0, sizeof(name));
11241                                 strcpy(name, proto[n].name);
11242                                 if (!strncmp(name, "PPPOE", 5))
11243                                         ptype_mapping[i].sw_ptype |=
11244                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11245                                 else if (!strncmp(name, "OIPV4", 5)) {
11246                                         ptype_mapping[i].sw_ptype |=
11247                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11248                                         in_tunnel = true;
11249                                 } else if (!strncmp(name, "IPV4", 4) &&
11250                                            !in_tunnel)
11251                                         ptype_mapping[i].sw_ptype |=
11252                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11253                                 else if (!strncmp(name, "IPV4FRAG", 8) &&
11254                                          in_tunnel) {
11255                                         ptype_mapping[i].sw_ptype |=
11256                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11257                                         ptype_mapping[i].sw_ptype |=
11258                                                 RTE_PTYPE_INNER_L4_FRAG;
11259                                 } else if (!strncmp(name, "IPV4", 4) &&
11260                                            in_tunnel)
11261                                         ptype_mapping[i].sw_ptype |=
11262                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11263                                 else if (!strncmp(name, "OIPV6", 5)) {
11264                                         ptype_mapping[i].sw_ptype |=
11265                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11266                                         in_tunnel = true;
11267                                 } else if (!strncmp(name, "IPV6", 4) &&
11268                                            !in_tunnel)
11269                                         ptype_mapping[i].sw_ptype |=
11270                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11271                                 else if (!strncmp(name, "IPV6FRAG", 8) &&
11272                                          in_tunnel) {
11273                                         ptype_mapping[i].sw_ptype |=
11274                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11275                                         ptype_mapping[i].sw_ptype |=
11276                                                 RTE_PTYPE_INNER_L4_FRAG;
11277                                 } else if (!strncmp(name, "IPV6", 4) &&
11278                                            in_tunnel)
11279                                         ptype_mapping[i].sw_ptype |=
11280                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11281                                 else if (!strncmp(name, "UDP", 3) && !in_tunnel)
11282                                         ptype_mapping[i].sw_ptype |=
11283                                                 RTE_PTYPE_L4_UDP;
11284                                 else if (!strncmp(name, "UDP", 3) && in_tunnel)
11285                                         ptype_mapping[i].sw_ptype |=
11286                                                 RTE_PTYPE_INNER_L4_UDP;
11287                                 else if (!strncmp(name, "TCP", 3) && !in_tunnel)
11288                                         ptype_mapping[i].sw_ptype |=
11289                                                 RTE_PTYPE_L4_TCP;
11290                                 else if (!strncmp(name, "TCP", 3) && in_tunnel)
11291                                         ptype_mapping[i].sw_ptype |=
11292                                                 RTE_PTYPE_INNER_L4_TCP;
11293                                 else if (!strncmp(name, "SCTP", 4) &&
11294                                          !in_tunnel)
11295                                         ptype_mapping[i].sw_ptype |=
11296                                                 RTE_PTYPE_L4_SCTP;
11297                                 else if (!strncmp(name, "SCTP", 4) && in_tunnel)
11298                                         ptype_mapping[i].sw_ptype |=
11299                                                 RTE_PTYPE_INNER_L4_SCTP;
11300                                 else if ((!strncmp(name, "ICMP", 4) ||
11301                                           !strncmp(name, "ICMPV6", 6)) &&
11302                                          !in_tunnel)
11303                                         ptype_mapping[i].sw_ptype |=
11304                                                 RTE_PTYPE_L4_ICMP;
11305                                 else if ((!strncmp(name, "ICMP", 4) ||
11306                                           !strncmp(name, "ICMPV6", 6)) &&
11307                                          in_tunnel)
11308                                         ptype_mapping[i].sw_ptype |=
11309                                                 RTE_PTYPE_INNER_L4_ICMP;
11310                                 else if (!strncmp(name, "GTPC", 4)) {
11311                                         ptype_mapping[i].sw_ptype |=
11312                                                 RTE_PTYPE_TUNNEL_GTPC;
11313                                         in_tunnel = true;
11314                                 } else if (!strncmp(name, "GTPU", 4)) {
11315                                         ptype_mapping[i].sw_ptype |=
11316                                                 RTE_PTYPE_TUNNEL_GTPU;
11317                                         in_tunnel = true;
11318                                 } else if (!strncmp(name, "GRENAT", 6)) {
11319                                         ptype_mapping[i].sw_ptype |=
11320                                                 RTE_PTYPE_TUNNEL_GRENAT;
11321                                         in_tunnel = true;
11322                                 } else if (!strncmp(name, "L2TPv2CTL", 9)) {
11323                                         ptype_mapping[i].sw_ptype |=
11324                                                 RTE_PTYPE_TUNNEL_L2TP;
11325                                         in_tunnel = true;
11326                                 }
11327
11328                                 break;
11329                         }
11330                 }
11331         }
11332
11333         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11334                                                 ptype_num, 0);
11335         if (ret)
11336                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11337
11338         rte_free(ptype_mapping);
11339         rte_free(ptype);
11340         return ret;
11341 }
11342
11343 void
11344 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11345                               uint32_t pkg_size)
11346 {
11347         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11348         uint32_t proto_num;
11349         struct rte_pmd_i40e_proto_info *proto;
11350         uint32_t buff_size;
11351         uint32_t i;
11352         int ret;
11353
11354         /* get information about protocol number */
11355         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11356                                        (uint8_t *)&proto_num, sizeof(proto_num),
11357                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11358         if (ret) {
11359                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11360                 return;
11361         }
11362         if (!proto_num) {
11363                 PMD_DRV_LOG(INFO, "No new protocol added");
11364                 return;
11365         }
11366
11367         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11368         proto = rte_zmalloc("new_proto", buff_size, 0);
11369         if (!proto) {
11370                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11371                 return;
11372         }
11373
11374         /* get information about protocol list */
11375         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11376                                         (uint8_t *)proto, buff_size,
11377                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11378         if (ret) {
11379                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11380                 rte_free(proto);
11381                 return;
11382         }
11383
11384         /* Check if GTP is supported. */
11385         for (i = 0; i < proto_num; i++) {
11386                 if (!strncmp(proto[i].name, "GTP", 3)) {
11387                         pf->gtp_support = true;
11388                         break;
11389                 }
11390         }
11391
11392         /* Update customized pctype info */
11393         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11394                                             proto_num, proto);
11395         if (ret)
11396                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11397
11398         /* Update customized ptype info */
11399         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11400                                            proto_num, proto);
11401         if (ret)
11402                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11403
11404         rte_free(proto);
11405 }
11406
11407 /* Create a QinQ cloud filter
11408  *
11409  * The Fortville NIC has limited resources for tunnel filters,
11410  * so we can only reuse existing filters.
11411  *
11412  * In step 1 we define which Field Vector fields can be used for
11413  * filter types.
11414  * As we do not have the inner tag defined as a field,
11415  * we have to define it first, by reusing one of L1 entries.
11416  *
11417  * In step 2 we are replacing one of existing filter types with
11418  * a new one for QinQ.
11419  * As we reusing L1 and replacing L2, some of the default filter
11420  * types will disappear,which depends on L1 and L2 entries we reuse.
11421  *
11422  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11423  *
11424  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11425  *              later when we define the cloud filter.
11426  *      a.      Valid_flags.replace_cloud = 0
11427  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11428  *      c.      New_filter = 0x10
11429  *      d.      TR bit = 0xff (optional, not used here)
11430  *      e.      Buffer – 2 entries:
11431  *              i.      Byte 0 = 8 (outer vlan FV index).
11432  *                      Byte 1 = 0 (rsv)
11433  *                      Byte 2-3 = 0x0fff
11434  *              ii.     Byte 0 = 37 (inner vlan FV index).
11435  *                      Byte 1 =0 (rsv)
11436  *                      Byte 2-3 = 0x0fff
11437  *
11438  * Step 2:
11439  * 2.   Create cloud filter using two L1 filters entries: stag and
11440  *              new filter(outer vlan+ inner vlan)
11441  *      a.      Valid_flags.replace_cloud = 1
11442  *      b.      Old_filter = 1 (instead of outer IP)
11443  *      c.      New_filter = 0x10
11444  *      d.      Buffer – 2 entries:
11445  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11446  *                      Byte 1-3 = 0 (rsv)
11447  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11448  *                      Byte 9-11 = 0 (rsv)
11449  */
11450 static int
11451 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11452 {
11453         int ret = -ENOTSUP;
11454         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11455         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11456         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11457
11458         /* Init */
11459         memset(&filter_replace, 0,
11460                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11461         memset(&filter_replace_buf, 0,
11462                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11463
11464         /* create L1 filter */
11465         filter_replace.old_filter_type =
11466                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11467         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11468         filter_replace.tr_bit = 0;
11469
11470         /* Prepare the buffer, 2 entries */
11471         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11472         filter_replace_buf.data[0] |=
11473                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11474         /* Field Vector 12b mask */
11475         filter_replace_buf.data[2] = 0xff;
11476         filter_replace_buf.data[3] = 0x0f;
11477         filter_replace_buf.data[4] =
11478                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11479         filter_replace_buf.data[4] |=
11480                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11481         /* Field Vector 12b mask */
11482         filter_replace_buf.data[6] = 0xff;
11483         filter_replace_buf.data[7] = 0x0f;
11484         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11485                         &filter_replace_buf);
11486         if (ret != I40E_SUCCESS)
11487                 return ret;
11488
11489         /* Apply the second L2 cloud filter */
11490         memset(&filter_replace, 0,
11491                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11492         memset(&filter_replace_buf, 0,
11493                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11494
11495         /* create L2 filter, input for L2 filter will be L1 filter  */
11496         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11497         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11498         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11499
11500         /* Prepare the buffer, 2 entries */
11501         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11502         filter_replace_buf.data[0] |=
11503                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11504         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11505         filter_replace_buf.data[4] |=
11506                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11507         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11508                         &filter_replace_buf);
11509         return ret;
11510 }
11511
11512 RTE_INIT(i40e_init_log);
11513 static void
11514 i40e_init_log(void)
11515 {
11516         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11517         if (i40e_logtype_init >= 0)
11518                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11519         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11520         if (i40e_logtype_driver >= 0)
11521                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11522 }