drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and interval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 295                             struct ether_addr *mac_addr,
 296                             uint32_t index,
 297                             uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 419
 420 int i40e_logtype_init;
 421 int i40e_logtype_driver;
 422
 423 static const struct rte_pci_id pci_id_i40e_map[] = {
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 static const struct eth_dev_ops i40e_eth_dev_ops = {
 448         .dev_configure                = i40e_dev_configure,
 449         .dev_start                    = i40e_dev_start,
 450         .dev_stop                     = i40e_dev_stop,
 451         .dev_close                    = i40e_dev_close,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 465         .fw_version_get               = i40e_fw_version_get,
 466         .dev_infos_get                = i40e_dev_info_get,
 467         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 468         .vlan_filter_set              = i40e_vlan_filter_set,
 469         .vlan_tpid_set                = i40e_vlan_tpid_set,
 470         .vlan_offload_set             = i40e_vlan_offload_set,
 471         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 472         .vlan_pvid_set                = i40e_vlan_pvid_set,
 473         .rx_queue_start               = i40e_dev_rx_queue_start,
 474         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 475         .tx_queue_start               = i40e_dev_tx_queue_start,
 476         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 477         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 478         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 479         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 480         .rx_queue_release             = i40e_dev_rx_queue_release,
 481         .rx_queue_count               = i40e_dev_rx_queue_count,
 482         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 483         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 484         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 485         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 486         .tx_queue_release             = i40e_dev_tx_queue_release,
 487         .dev_led_on                   = i40e_dev_led_on,
 488         .dev_led_off                  = i40e_dev_led_off,
 489         .flow_ctrl_get                = i40e_flow_ctrl_get,
 490         .flow_ctrl_set                = i40e_flow_ctrl_set,
 491         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 492         .mac_addr_add                 = i40e_macaddr_add,
 493         .mac_addr_remove              = i40e_macaddr_remove,
 494         .reta_update                  = i40e_dev_rss_reta_update,
 495         .reta_query                   = i40e_dev_rss_reta_query,
 496         .rss_hash_update              = i40e_dev_rss_hash_update,
 497         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 498         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 499         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 500         .filter_ctrl                  = i40e_dev_filter_ctrl,
 501         .rxq_info_get                 = i40e_rxq_info_get,
 502         .txq_info_get                 = i40e_txq_info_get,
 503         .mirror_rule_set              = i40e_mirror_rule_set,
 504         .mirror_rule_reset            = i40e_mirror_rule_reset,
 505         .timesync_enable              = i40e_timesync_enable,
 506         .timesync_disable             = i40e_timesync_disable,
 507         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 508         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 509         .get_dcb_info                 = i40e_dev_get_dcb_info,
 510         .timesync_adjust_time         = i40e_timesync_adjust_time,
 511         .timesync_read_time           = i40e_timesync_read_time,
 512         .timesync_write_time          = i40e_timesync_write_time,
 513         .get_reg                      = i40e_get_regs,
 514         .get_eeprom_length            = i40e_get_eeprom_length,
 515         .get_eeprom                   = i40e_get_eeprom,
 516         .mac_addr_set                 = i40e_set_default_mac_addr,
 517         .mtu_set                      = i40e_dev_mtu_set,
 518         .tm_ops_get                   = i40e_tm_ops_get,
 519 };
 520
 521 /* store statistics names and its offset in stats structure */
 522 struct rte_i40e_xstats_name_off {
 523         char name[RTE_ETH_XSTATS_NAME_SIZE];
 524         unsigned offset;
 525 };
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 528         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 529         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 530         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 531         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 532         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 533                 rx_unknown_protocol)},
 534         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 535         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 536         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 537         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 538 };
 539
 540 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 541                 sizeof(rte_i40e_stats_strings[0]))
 542
 543 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 544         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 545                 tx_dropped_link_down)},
 546         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 547         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 548                 illegal_bytes)},
 549         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 550         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_local_faults)},
 552         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_remote_faults)},
 554         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 555                 rx_length_errors)},
 556         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 557         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 558         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 559         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 560         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 561         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_127)},
 563         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_255)},
 565         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_511)},
 567         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1023)},
 569         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1522)},
 571         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_big)},
 573         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_undersize)},
 575         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_oversize)},
 577         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 578                 mac_short_packet_dropped)},
 579         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_fragments)},
 581         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 582         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 583         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_127)},
 585         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_255)},
 587         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_511)},
 589         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1023)},
 591         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1522)},
 593         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_big)},
 595         {"rx_flow_director_atr_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 597         {"rx_flow_director_sb_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 599         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_status)},
 601         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_status)},
 603         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_count)},
 605         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_count)},
 607 };
 608
 609 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 610                 sizeof(rte_i40e_hw_port_strings[0]))
 611
 612 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 613         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xon_rx)},
 615         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xoff_rx)},
 617 };
 618
 619 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 620                 sizeof(rte_i40e_rxq_prio_strings[0]))
 621
 622 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 623         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_tx)},
 625         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xoff_tx)},
 627         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_2_xoff)},
 629 };
 630
 631 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 632                 sizeof(rte_i40e_txq_prio_strings[0]))
 633
 634 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 635         struct rte_pci_device *pci_dev)
 636 {
 637         return rte_eth_dev_pci_generic_probe(pci_dev,
 638                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 639 }
 640
 641 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 642 {
 643         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 644 }
 645
 646 static struct rte_pci_driver rte_i40e_pmd = {
 647         .id_table = pci_id_i40e_map,
 648         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 649         .probe = eth_i40e_pci_probe,
 650         .remove = eth_i40e_pci_remove,
 651 };
 652
 653 static inline int
 654 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 655                                      struct rte_eth_link *link)
 656 {
 657         struct rte_eth_link *dst = link;
 658         struct rte_eth_link *src = &(dev->data->dev_link);
 659
 660         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 661                                         *(uint64_t *)src) == 0)
 662                 return -1;
 663
 664         return 0;
 665 }
 666
 667 static inline int
 668 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 669                                       struct rte_eth_link *link)
 670 {
 671         struct rte_eth_link *dst = &(dev->data->dev_link);
 672         struct rte_eth_link *src = link;
 673
 674         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 675                                         *(uint64_t *)src) == 0)
 676                 return -1;
 677
 678         return 0;
 679 }
 680
 681 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 682 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 683 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 684
 685 #ifndef I40E_GLQF_ORT
 686 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 687 #endif
 688 #ifndef I40E_GLQF_PIT
 689 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 690 #endif
 691 #ifndef I40E_GLQF_L3_MAP
 692 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 693 #endif
 694
 695 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 696 {
 697         /*
 698          * Initialize registers for flexible payload, which should be set by NVM.
 699          * This should be removed from code once it is fixed in NVM.
 700          */
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 711         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 712         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 713
 714         /* Initialize registers for parsing packet type of QinQ */
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 716         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 717 }
 718
 719 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 720
 721 /*
 722  * Add a ethertype filter to drop all flow control frames transmitted
 723  * from VSIs.
 724 */
 725 static void
 726 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 727 {
 728         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 729         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 730                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 731                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 732         int ret;
 733
 734         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 735                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 736                                 pf->main_vsi_seid, 0,
 737                                 TRUE, NULL, NULL);
 738         if (ret)
 739                 PMD_INIT_LOG(ERR,
 740                         "Failed to add filter to drop flow control frames from VSIs.");
 741 }
 742
 743 static int
 744 floating_veb_list_handler(__rte_unused const char *key,
 745                           const char *floating_veb_value,
 746                           void *opaque)
 747 {
 748         int idx = 0;
 749         unsigned int count = 0;
 750         char *end = NULL;
 751         int min, max;
 752         bool *vf_floating_veb = opaque;
 753
 754         while (isblank(*floating_veb_value))
 755                 floating_veb_value++;
 756
 757         /* Reset floating VEB configuration for VFs */
 758         for (idx = 0; idx < I40E_MAX_VF; idx++)
 759                 vf_floating_veb[idx] = false;
 760
 761         min = I40E_MAX_VF;
 762         do {
 763                 while (isblank(*floating_veb_value))
 764                         floating_veb_value++;
 765                 if (*floating_veb_value == '\0')
 766                         return -1;
 767                 errno = 0;
 768                 idx = strtoul(floating_veb_value, &end, 10);
 769                 if (errno || end == NULL)
 770                         return -1;
 771                 while (isblank(*end))
 772                         end++;
 773                 if (*end == '-') {
 774                         min = idx;
 775                 } else if ((*end == ';') || (*end == '\0')) {
 776                         max = idx;
 777                         if (min == I40E_MAX_VF)
 778                                 min = idx;
 779                         if (max >= I40E_MAX_VF)
 780                                 max = I40E_MAX_VF - 1;
 781                         for (idx = min; idx <= max; idx++) {
 782                                 vf_floating_veb[idx] = true;
 783                                 count++;
 784                         }
 785                         min = I40E_MAX_VF;
 786                 } else {
 787                         return -1;
 788                 }
 789                 floating_veb_value = end + 1;
 790         } while (*end != '\0');
 791
 792         if (count == 0)
 793                 return -1;
 794
 795         return 0;
 796 }
 797
 798 static void
 799 config_vf_floating_veb(struct rte_devargs *devargs,
 800                        uint16_t floating_veb,
 801                        bool *vf_floating_veb)
 802 {
 803         struct rte_kvargs *kvlist;
 804         int i;
 805         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 806
 807         if (!floating_veb)
 808                 return;
 809         /* All the VFs attach to the floating VEB by default
 810          * when the floating VEB is enabled.
 811          */
 812         for (i = 0; i < I40E_MAX_VF; i++)
 813                 vf_floating_veb[i] = true;
 814
 815         if (devargs == NULL)
 816                 return;
 817
 818         kvlist = rte_kvargs_parse(devargs->args, NULL);
 819         if (kvlist == NULL)
 820                 return;
 821
 822         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 823                 rte_kvargs_free(kvlist);
 824                 return;
 825         }
 826         /* When the floating_veb_list parameter exists, all the VFs
 827          * will attach to the legacy VEB firstly, then configure VFs
 828          * to the floating VEB according to the floating_veb_list.
 829          */
 830         if (rte_kvargs_process(kvlist, floating_veb_list,
 831                                floating_veb_list_handler,
 832                                vf_floating_veb) < 0) {
 833                 rte_kvargs_free(kvlist);
 834                 return;
 835         }
 836         rte_kvargs_free(kvlist);
 837 }
 838
 839 static int
 840 i40e_check_floating_handler(__rte_unused const char *key,
 841                             const char *value,
 842                             __rte_unused void *opaque)
 843 {
 844         if (strcmp(value, "1"))
 845                 return -1;
 846
 847         return 0;
 848 }
 849
 850 static int
 851 is_floating_veb_supported(struct rte_devargs *devargs)
 852 {
 853         struct rte_kvargs *kvlist;
 854         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 855
 856         if (devargs == NULL)
 857                 return 0;
 858
 859         kvlist = rte_kvargs_parse(devargs->args, NULL);
 860         if (kvlist == NULL)
 861                 return 0;
 862
 863         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 864                 rte_kvargs_free(kvlist);
 865                 return 0;
 866         }
 867         /* Floating VEB is enabled when there's key-value:
 868          * enable_floating_veb=1
 869          */
 870         if (rte_kvargs_process(kvlist, floating_veb_key,
 871                                i40e_check_floating_handler, NULL) < 0) {
 872                 rte_kvargs_free(kvlist);
 873                 return 0;
 874         }
 875         rte_kvargs_free(kvlist);
 876
 877         return 1;
 878 }
 879
 880 static void
 881 config_floating_veb(struct rte_eth_dev *dev)
 882 {
 883         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 886
 887         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 888
 889         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 890                 pf->floating_veb =
 891                         is_floating_veb_supported(pci_dev->device.devargs);
 892                 config_vf_floating_veb(pci_dev->device.devargs,
 893                                        pf->floating_veb,
 894                                        pf->floating_veb_list);
 895         } else {
 896                 pf->floating_veb = false;
 897         }
 898 }
 899
 900 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 901 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 902
 903 static int
 904 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 905 {
 906         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 907         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 908         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 909         int ret;
 910
 911         struct rte_hash_parameters ethertype_hash_params = {
 912                 .name = ethertype_hash_name,
 913                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 914                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 915                 .hash_func = rte_hash_crc,
 916                 .hash_func_init_val = 0,
 917                 .socket_id = rte_socket_id(),
 918         };
 919
 920         /* Initialize ethertype filter rule list and hash */
 921         TAILQ_INIT(&ethertype_rule->ethertype_list);
 922         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 923                  "ethertype_%s", dev->device->name);
 924         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 925         if (!ethertype_rule->hash_table) {
 926                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 927                 return -EINVAL;
 928         }
 929         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 930                                        sizeof(struct i40e_ethertype_filter *) *
 931                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 932                                        0);
 933         if (!ethertype_rule->hash_map) {
 934                 PMD_INIT_LOG(ERR,
 935                              "Failed to allocate memory for ethertype hash map!");
 936                 ret = -ENOMEM;
 937                 goto err_ethertype_hash_map_alloc;
 938         }
 939
 940         return 0;
 941
 942 err_ethertype_hash_map_alloc:
 943         rte_hash_free(ethertype_rule->hash_table);
 944
 945         return ret;
 946 }
 947
 948 static int
 949 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 950 {
 951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 952         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 953         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 954         int ret;
 955
 956         struct rte_hash_parameters tunnel_hash_params = {
 957                 .name = tunnel_hash_name,
 958                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 959                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 960                 .hash_func = rte_hash_crc,
 961                 .hash_func_init_val = 0,
 962                 .socket_id = rte_socket_id(),
 963         };
 964
 965         /* Initialize tunnel filter rule list and hash */
 966         TAILQ_INIT(&tunnel_rule->tunnel_list);
 967         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 968                  "tunnel_%s", dev->device->name);
 969         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 970         if (!tunnel_rule->hash_table) {
 971                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 972                 return -EINVAL;
 973         }
 974         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 975                                     sizeof(struct i40e_tunnel_filter *) *
 976                                     I40E_MAX_TUNNEL_FILTER_NUM,
 977                                     0);
 978         if (!tunnel_rule->hash_map) {
 979                 PMD_INIT_LOG(ERR,
 980                              "Failed to allocate memory for tunnel hash map!");
 981                 ret = -ENOMEM;
 982                 goto err_tunnel_hash_map_alloc;
 983         }
 984
 985         return 0;
 986
 987 err_tunnel_hash_map_alloc:
 988         rte_hash_free(tunnel_rule->hash_table);
 989
 990         return ret;
 991 }
 992
 993 static int
 994 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_fdir_info *fdir_info = &pf->fdir;
 998         char fdir_hash_name[RTE_HASH_NAMESIZE];
 999         int ret;
1000
1001         struct rte_hash_parameters fdir_hash_params = {
1002                 .name = fdir_hash_name,
1003                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1004                 .key_len = sizeof(struct rte_eth_fdir_input),
1005                 .hash_func = rte_hash_crc,
1006                 .hash_func_init_val = 0,
1007                 .socket_id = rte_socket_id(),
1008         };
1009
1010         /* Initialize flow director filter rule list and hash */
1011         TAILQ_INIT(&fdir_info->fdir_list);
1012         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1013                  "fdir_%s", dev->device->name);
1014         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1015         if (!fdir_info->hash_table) {
1016                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1017                 return -EINVAL;
1018         }
1019         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1020                                           sizeof(struct i40e_fdir_filter *) *
1021                                           I40E_MAX_FDIR_FILTER_NUM,
1022                                           0);
1023         if (!fdir_info->hash_map) {
1024                 PMD_INIT_LOG(ERR,
1025                              "Failed to allocate memory for fdir hash map!");
1026                 ret = -ENOMEM;
1027                 goto err_fdir_hash_map_alloc;
1028         }
1029         return 0;
1030
1031 err_fdir_hash_map_alloc:
1032         rte_hash_free(fdir_info->hash_table);
1033
1034         return ret;
1035 }
1036
1037 static int
1038 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 {
1040         struct rte_pci_device *pci_dev;
1041         struct rte_intr_handle *intr_handle;
1042         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1043         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044         struct i40e_vsi *vsi;
1045         int ret;
1046         uint32_t len;
1047         uint8_t aq_fail = 0;
1048
1049         PMD_INIT_FUNC_TRACE();
1050
1051         dev->dev_ops = &i40e_eth_dev_ops;
1052         dev->rx_pkt_burst = i40e_recv_pkts;
1053         dev->tx_pkt_burst = i40e_xmit_pkts;
1054         dev->tx_pkt_prepare = i40e_prep_pkts;
1055
1056         /* for secondary processes, we don't initialise any further as primary
1057          * has already done this work. Only check we don't need a different
1058          * RX function */
1059         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1060                 i40e_set_rx_function(dev);
1061                 i40e_set_tx_function(dev);
1062                 return 0;
1063         }
1064         i40e_set_default_ptype_table(dev);
1065         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1066         intr_handle = &pci_dev->intr_handle;
1067
1068         rte_eth_copy_pci_info(dev, pci_dev);
1069         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070
1071         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072         pf->adapter->eth_dev = dev;
1073         pf->dev_data = dev->data;
1074
1075         hw->back = I40E_PF_TO_ADAPTER(pf);
1076         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1077         if (!hw->hw_addr) {
1078                 PMD_INIT_LOG(ERR,
1079                         "Hardware is not available, as address is NULL");
1080                 return -ENODEV;
1081         }
1082
1083         hw->vendor_id = pci_dev->id.vendor_id;
1084         hw->device_id = pci_dev->id.device_id;
1085         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1086         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1087         hw->bus.device = pci_dev->addr.devid;
1088         hw->bus.func = pci_dev->addr.function;
1089         hw->adapter_stopped = 0;
1090
1091         /* Make sure all is clean before doing PF reset */
1092         i40e_clear_hw(hw);
1093
1094         /* Initialize the hardware */
1095         i40e_hw_init(dev);
1096
1097         /* Reset here to make sure all is clean for each PF */
1098         ret = i40e_pf_reset(hw);
1099         if (ret) {
1100                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1101                 return ret;
1102         }
1103
1104         /* Initialize the shared code (base driver) */
1105         ret = i40e_init_shared_code(hw);
1106         if (ret) {
1107                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1108                 return ret;
1109         }
1110
1111         /*
1112          * To work around the NVM issue, initialize registers
1113          * for flexible payload and packet type of QinQ by
1114          * software. It should be removed once issues are fixed
1115          * in NVM.
1116          */
1117         i40e_GLQF_reg_init(hw);
1118
1119         /* Initialize the input set for filters (hash and fd) to default value */
1120         i40e_filter_input_set_init(pf);
1121
1122         /* Initialize the parameters for adminq */
1123         i40e_init_adminq_parameter(hw);
1124         ret = i40e_init_adminq(hw);
1125         if (ret != I40E_SUCCESS) {
1126                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1127                 return -EIO;
1128         }
1129         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1130                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1131                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1132                      ((hw->nvm.version >> 12) & 0xf),
1133                      ((hw->nvm.version >> 4) & 0xff),
1134                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135
1136         /* initialise the L3_MAP register */
1137         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1138                                    0x00000028,  NULL);
1139         if (ret)
1140                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141
1142         /* Need the special FW version to support floating VEB */
1143         config_floating_veb(dev);
1144         /* Clear PXE mode */
1145         i40e_clear_pxe_mode(hw);
1146         i40e_dev_sync_phy_type(hw);
1147
1148         /*
1149          * On X710, performance number is far from the expectation on recent
1150          * firmware versions. The fix for this issue may not be integrated in
1151          * the following firmware version. So the workaround in software driver
1152          * is needed. It needs to modify the initial values of 3 internal only
1153          * registers. Note that the workaround can be removed when it is fixed
1154          * in firmware in the future.
1155          */
1156         i40e_configure_registers(hw);
1157
1158         /* Get hw capabilities */
1159         ret = i40e_get_cap(hw);
1160         if (ret != I40E_SUCCESS) {
1161                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1162                 goto err_get_capabilities;
1163         }
1164
1165         /* Initialize parameters for PF */
1166         ret = i40e_pf_parameter_init(dev);
1167         if (ret != 0) {
1168                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1169                 goto err_parameter_init;
1170         }
1171
1172         /* Initialize the queue management */
1173         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1174         if (ret < 0) {
1175                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1176                 goto err_qp_pool_init;
1177         }
1178         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1179                                 hw->func_caps.num_msix_vectors - 1);
1180         if (ret < 0) {
1181                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1182                 goto err_msix_pool_init;
1183         }
1184
1185         /* Initialize lan hmc */
1186         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1187                                 hw->func_caps.num_rx_qp, 0, 0);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1190                 goto err_init_lan_hmc;
1191         }
1192
1193         /* Configure lan hmc */
1194         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1197                 goto err_configure_lan_hmc;
1198         }
1199
1200         /* Get and check the mac address */
1201         i40e_get_mac_addr(hw, hw->mac.addr);
1202         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1203                 PMD_INIT_LOG(ERR, "mac address is not valid");
1204                 ret = -EIO;
1205                 goto err_get_mac_addr;
1206         }
1207         /* Copy the permanent MAC address */
1208         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1209                         (struct ether_addr *) hw->mac.perm_addr);
1210
1211         /* Disable flow control */
1212         hw->fc.requested_mode = I40E_FC_NONE;
1213         i40e_set_fc(hw, &aq_fail, TRUE);
1214
1215         /* Set the global registers with default ether type value */
1216         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1217         if (ret != I40E_SUCCESS) {
1218                 PMD_INIT_LOG(ERR,
1219                         "Failed to set the default outer VLAN ether type");
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* PF setup, which includes VSI setup */
1224         ret = i40e_pf_setup(pf);
1225         if (ret) {
1226                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1227                 goto err_setup_pf_switch;
1228         }
1229
1230         /* reset all stats of the device, including pf and main vsi */
1231         i40e_dev_stats_reset(dev);
1232
1233         vsi = pf->main_vsi;
1234
1235         /* Disable double vlan by default */
1236         i40e_vsi_config_double_vlan(vsi, FALSE);
1237
1238         /* Disable S-TAG identification when floating_veb is disabled */
1239         if (!pf->floating_veb) {
1240                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1241                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1242                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1243                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1244                 }
1245         }
1246
1247         if (!vsi->max_macaddrs)
1248                 len = ETHER_ADDR_LEN;
1249         else
1250                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1251
1252         /* Should be after VSI initialized */
1253         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1254         if (!dev->data->mac_addrs) {
1255                 PMD_INIT_LOG(ERR,
1256                         "Failed to allocated memory for storing mac address");
1257                 goto err_mac_alloc;
1258         }
1259         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1260                                         &dev->data->mac_addrs[0]);
1261
1262         /* Init dcb to sw mode by default */
1263         ret = i40e_dcb_init_configure(dev, TRUE);
1264         if (ret != I40E_SUCCESS) {
1265                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1266                 pf->flags &= ~I40E_FLAG_DCB;
1267         }
1268         /* Update HW struct after DCB configuration */
1269         i40e_get_cap(hw);
1270
1271         /* initialize pf host driver to setup SRIOV resource if applicable */
1272         i40e_pf_host_init(dev);
1273
1274         /* register callback func to eal lib */
1275         rte_intr_callback_register(intr_handle,
1276                                    i40e_dev_interrupt_handler, dev);
1277
1278         /* configure and enable device interrupt */
1279         i40e_pf_config_irq0(hw, TRUE);
1280         i40e_pf_enable_irq0(hw);
1281
1282         /* enable uio intr after callback register */
1283         rte_intr_enable(intr_handle);
1284         /*
1285          * Add an ethertype filter to drop all flow control frames transmitted
1286          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1287          * frames to wire.
1288          */
1289         i40e_add_tx_flow_control_drop_filter(pf);
1290
1291         /* Set the max frame size to 0x2600 by default,
1292          * in case other drivers changed the default value.
1293          */
1294         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1295
1296         /* initialize mirror rule list */
1297         TAILQ_INIT(&pf->mirror_list);
1298
1299         /* initialize Traffic Manager configuration */
1300         i40e_tm_conf_init(dev);
1301
1302         ret = i40e_init_ethtype_filter_list(dev);
1303         if (ret < 0)
1304                 goto err_init_ethtype_filter_list;
1305         ret = i40e_init_tunnel_filter_list(dev);
1306         if (ret < 0)
1307                 goto err_init_tunnel_filter_list;
1308         ret = i40e_init_fdir_filter_list(dev);
1309         if (ret < 0)
1310                 goto err_init_fdir_filter_list;
1311
1312         return 0;
1313
1314 err_init_fdir_filter_list:
1315         rte_free(pf->tunnel.hash_table);
1316         rte_free(pf->tunnel.hash_map);
1317 err_init_tunnel_filter_list:
1318         rte_free(pf->ethertype.hash_table);
1319         rte_free(pf->ethertype.hash_map);
1320 err_init_ethtype_filter_list:
1321         rte_free(dev->data->mac_addrs);
1322 err_mac_alloc:
1323         i40e_vsi_release(pf->main_vsi);
1324 err_setup_pf_switch:
1325 err_get_mac_addr:
1326 err_configure_lan_hmc:
1327         (void)i40e_shutdown_lan_hmc(hw);
1328 err_init_lan_hmc:
1329         i40e_res_pool_destroy(&pf->msix_pool);
1330 err_msix_pool_init:
1331         i40e_res_pool_destroy(&pf->qp_pool);
1332 err_qp_pool_init:
1333 err_parameter_init:
1334 err_get_capabilities:
1335         (void)i40e_shutdown_adminq(hw);
1336
1337         return ret;
1338 }
1339
1340 static void
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1342 {
1343         struct i40e_ethertype_filter *p_ethertype;
1344         struct i40e_ethertype_rule *ethertype_rule;
1345
1346         ethertype_rule = &pf->ethertype;
1347         /* Remove all ethertype filter rules and hash */
1348         if (ethertype_rule->hash_map)
1349                 rte_free(ethertype_rule->hash_map);
1350         if (ethertype_rule->hash_table)
1351                 rte_hash_free(ethertype_rule->hash_table);
1352
1353         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1354                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1355                              p_ethertype, rules);
1356                 rte_free(p_ethertype);
1357         }
1358 }
1359
1360 static void
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1362 {
1363         struct i40e_tunnel_filter *p_tunnel;
1364         struct i40e_tunnel_rule *tunnel_rule;
1365
1366         tunnel_rule = &pf->tunnel;
1367         /* Remove all tunnel director rules and hash */
1368         if (tunnel_rule->hash_map)
1369                 rte_free(tunnel_rule->hash_map);
1370         if (tunnel_rule->hash_table)
1371                 rte_hash_free(tunnel_rule->hash_table);
1372
1373         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1375                 rte_free(p_tunnel);
1376         }
1377 }
1378
1379 static void
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_fdir_filter *p_fdir;
1383         struct i40e_fdir_info *fdir_info;
1384
1385         fdir_info = &pf->fdir;
1386         /* Remove all flow director rules and hash */
1387         if (fdir_info->hash_map)
1388                 rte_free(fdir_info->hash_map);
1389         if (fdir_info->hash_table)
1390                 rte_hash_free(fdir_info->hash_table);
1391
1392         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1394                 rte_free(p_fdir);
1395         }
1396 }
1397
1398 static int
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1400 {
1401         struct i40e_pf *pf;
1402         struct rte_pci_device *pci_dev;
1403         struct rte_intr_handle *intr_handle;
1404         struct i40e_hw *hw;
1405         struct i40e_filter_control_settings settings;
1406         struct rte_flow *p_flow;
1407         int ret;
1408         uint8_t aq_fail = 0;
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1413                 return 0;
1414
1415         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1418         intr_handle = &pci_dev->intr_handle;
1419
1420         if (hw->adapter_stopped == 0)
1421                 i40e_dev_close(dev);
1422
1423         dev->dev_ops = NULL;
1424         dev->rx_pkt_burst = NULL;
1425         dev->tx_pkt_burst = NULL;
1426
1427         /* Clear PXE mode */
1428         i40e_clear_pxe_mode(hw);
1429
1430         /* Unconfigure filter control */
1431         memset(&settings, 0, sizeof(settings));
1432         ret = i40e_set_filter_control(hw, &settings);
1433         if (ret)
1434                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1435                                         ret);
1436
1437         /* Disable flow control */
1438         hw->fc.requested_mode = I40E_FC_NONE;
1439         i40e_set_fc(hw, &aq_fail, TRUE);
1440
1441         /* uninitialize pf host driver */
1442         i40e_pf_host_uninit(dev);
1443
1444         rte_free(dev->data->mac_addrs);
1445         dev->data->mac_addrs = NULL;
1446
1447         /* disable uio intr before callback unregister */
1448         rte_intr_disable(intr_handle);
1449
1450         /* register callback func to eal lib */
1451         rte_intr_callback_unregister(intr_handle,
1452                                      i40e_dev_interrupt_handler, dev);
1453
1454         i40e_rm_ethtype_filter_list(pf);
1455         i40e_rm_tunnel_filter_list(pf);
1456         i40e_rm_fdir_filter_list(pf);
1457
1458         /* Remove all flows */
1459         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1461                 rte_free(p_flow);
1462         }
1463
1464         /* Remove all Traffic Manager configuration */
1465         i40e_tm_conf_uninit(dev);
1466
1467         return 0;
1468 }
1469
1470 static int
1471 i40e_dev_configure(struct rte_eth_dev *dev)
1472 {
1473         struct i40e_adapter *ad =
1474                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1475         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1478         int i, ret;
1479
1480         ret = i40e_dev_sync_phy_type(hw);
1481         if (ret)
1482                 return ret;
1483
1484         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1485          * bulk allocation or vector Rx preconditions we will reset it.
1486          */
1487         ad->rx_bulk_alloc_allowed = true;
1488         ad->rx_vec_allowed = true;
1489         ad->tx_simple_allowed = true;
1490         ad->tx_vec_allowed = true;
1491
1492         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1493                 ret = i40e_fdir_setup(pf);
1494                 if (ret != I40E_SUCCESS) {
1495                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1496                         return -ENOTSUP;
1497                 }
1498                 ret = i40e_fdir_configure(dev);
1499                 if (ret < 0) {
1500                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1501                         goto err;
1502                 }
1503         } else
1504                 i40e_fdir_teardown(pf);
1505
1506         ret = i40e_dev_init_vlan(dev);
1507         if (ret < 0)
1508                 goto err;
1509
1510         /* VMDQ setup.
1511          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1512          *  RSS setting have different requirements.
1513          *  General PMD driver call sequence are NIC init, configure,
1514          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1515          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1516          *  applicable. So, VMDQ setting has to be done before
1517          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1518          *  For RSS setting, it will try to calculate actual configured RX queue
1519          *  number, which will be available after rx_queue_setup(). dev_start()
1520          *  function is good to place RSS setup.
1521          */
1522         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1523                 ret = i40e_vmdq_setup(dev);
1524                 if (ret)
1525                         goto err;
1526         }
1527
1528         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1529                 ret = i40e_dcb_setup(dev);
1530                 if (ret) {
1531                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1532                         goto err_dcb;
1533                 }
1534         }
1535
1536         TAILQ_INIT(&pf->flow_list);
1537
1538         return 0;
1539
1540 err_dcb:
1541         /* need to release vmdq resource if exists */
1542         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1543                 i40e_vsi_release(pf->vmdq[i].vsi);
1544                 pf->vmdq[i].vsi = NULL;
1545         }
1546         rte_free(pf->vmdq);
1547         pf->vmdq = NULL;
1548 err:
1549         /* need to release fdir resource if exists */
1550         i40e_fdir_teardown(pf);
1551         return ret;
1552 }
1553
1554 void
1555 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1556 {
1557         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1558         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1559         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1560         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1561         uint16_t msix_vect = vsi->msix_intr;
1562         uint16_t i;
1563
1564         for (i = 0; i < vsi->nb_qps; i++) {
1565                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1566                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1567                 rte_wmb();
1568         }
1569
1570         if (vsi->type != I40E_VSI_SRIOV) {
1571                 if (!rte_intr_allow_others(intr_handle)) {
1572                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1573                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1574                         I40E_WRITE_REG(hw,
1575                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1576                                        0);
1577                 } else {
1578                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1579                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1580                         I40E_WRITE_REG(hw,
1581                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1582                                                        msix_vect - 1), 0);
1583                 }
1584         } else {
1585                 uint32_t reg;
1586                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1587                         vsi->user_param + (msix_vect - 1);
1588
1589                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1590                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1591         }
1592         I40E_WRITE_FLUSH(hw);
1593 }
1594
1595 static void
1596 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1597                        int base_queue, int nb_queue)
1598 {
1599         int i;
1600         uint32_t val;
1601         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1602
1603         /* Bind all RX queues to allocated MSIX interrupt */
1604         for (i = 0; i < nb_queue; i++) {
1605                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1606                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1607                         ((base_queue + i + 1) <<
1608                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1609                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1610                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1611
1612                 if (i == nb_queue - 1)
1613                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1614                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1615         }
1616
1617         /* Write first RX queue to Link list register as the head element */
1618         if (vsi->type != I40E_VSI_SRIOV) {
1619                 uint16_t interval =
1620                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1621
1622                 if (msix_vect == I40E_MISC_VEC_ID) {
1623                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1624                                        (base_queue <<
1625                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1626                                        (0x0 <<
1627                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1628                         I40E_WRITE_REG(hw,
1629                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1630                                        interval);
1631                 } else {
1632                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1633                                        (base_queue <<
1634                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1635                                        (0x0 <<
1636                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1637                         I40E_WRITE_REG(hw,
1638                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1639                                                        msix_vect - 1),
1640                                        interval);
1641                 }
1642         } else {
1643                 uint32_t reg;
1644
1645                 if (msix_vect == I40E_MISC_VEC_ID) {
1646                         I40E_WRITE_REG(hw,
1647                                        I40E_VPINT_LNKLST0(vsi->user_param),
1648                                        (base_queue <<
1649                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1650                                        (0x0 <<
1651                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1652                 } else {
1653                         /* num_msix_vectors_vf needs to minus irq0 */
1654                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1655                                 vsi->user_param + (msix_vect - 1);
1656
1657                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1658                                        (base_queue <<
1659                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1660                                        (0x0 <<
1661                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1662                 }
1663         }
1664
1665         I40E_WRITE_FLUSH(hw);
1666 }
1667
1668 void
1669 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1670 {
1671         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1673         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1674         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1675         uint16_t msix_vect = vsi->msix_intr;
1676         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1677         uint16_t queue_idx = 0;
1678         int record = 0;
1679         uint32_t val;
1680         int i;
1681
1682         for (i = 0; i < vsi->nb_qps; i++) {
1683                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1684                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1685         }
1686
1687         /* INTENA flag is not auto-cleared for interrupt */
1688         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1689         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1690                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1691                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1692         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1693
1694         /* VF bind interrupt */
1695         if (vsi->type == I40E_VSI_SRIOV) {
1696                 __vsi_queues_bind_intr(vsi, msix_vect,
1697                                        vsi->base_queue, vsi->nb_qps);
1698                 return;
1699         }
1700
1701         /* PF & VMDq bind interrupt */
1702         if (rte_intr_dp_is_en(intr_handle)) {
1703                 if (vsi->type == I40E_VSI_MAIN) {
1704                         queue_idx = 0;
1705                         record = 1;
1706                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1707                         struct i40e_vsi *main_vsi =
1708                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1709                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1710                         record = 1;
1711                 }
1712         }
1713
1714         for (i = 0; i < vsi->nb_used_qps; i++) {
1715                 if (nb_msix <= 1) {
1716                         if (!rte_intr_allow_others(intr_handle))
1717                                 /* allow to share MISC_VEC_ID */
1718                                 msix_vect = I40E_MISC_VEC_ID;
1719
1720                         /* no enough msix_vect, map all to one */
1721                         __vsi_queues_bind_intr(vsi, msix_vect,
1722                                                vsi->base_queue + i,
1723                                                vsi->nb_used_qps - i);
1724                         for (; !!record && i < vsi->nb_used_qps; i++)
1725                                 intr_handle->intr_vec[queue_idx + i] =
1726                                         msix_vect;
1727                         break;
1728                 }
1729                 /* 1:1 queue/msix_vect mapping */
1730                 __vsi_queues_bind_intr(vsi, msix_vect,
1731                                        vsi->base_queue + i, 1);
1732                 if (!!record)
1733                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1734
1735                 msix_vect++;
1736                 nb_msix--;
1737         }
1738 }
1739
1740 static void
1741 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1742 {
1743         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1744         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1745         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1746         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1747         uint16_t interval = i40e_calc_itr_interval(\
1748                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1749         uint16_t msix_intr, i;
1750
1751         if (rte_intr_allow_others(intr_handle))
1752                 for (i = 0; i < vsi->nb_msix; i++) {
1753                         msix_intr = vsi->msix_intr + i;
1754                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1755                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1756                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1757                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1758                                 (interval <<
1759                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1760                 }
1761         else
1762                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1763                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1764                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1765                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1766                                (interval <<
1767                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1768
1769         I40E_WRITE_FLUSH(hw);
1770 }
1771
1772 static void
1773 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1774 {
1775         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         uint16_t msix_intr, i;
1780
1781         if (rte_intr_allow_others(intr_handle))
1782                 for (i = 0; i < vsi->nb_msix; i++) {
1783                         msix_intr = vsi->msix_intr + i;
1784                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1785                                        0);
1786                 }
1787         else
1788                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1789
1790         I40E_WRITE_FLUSH(hw);
1791 }
1792
1793 static inline uint8_t
1794 i40e_parse_link_speeds(uint16_t link_speeds)
1795 {
1796         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1797
1798         if (link_speeds & ETH_LINK_SPEED_40G)
1799                 link_speed |= I40E_LINK_SPEED_40GB;
1800         if (link_speeds & ETH_LINK_SPEED_25G)
1801                 link_speed |= I40E_LINK_SPEED_25GB;
1802         if (link_speeds & ETH_LINK_SPEED_20G)
1803                 link_speed |= I40E_LINK_SPEED_20GB;
1804         if (link_speeds & ETH_LINK_SPEED_10G)
1805                 link_speed |= I40E_LINK_SPEED_10GB;
1806         if (link_speeds & ETH_LINK_SPEED_1G)
1807                 link_speed |= I40E_LINK_SPEED_1GB;
1808         if (link_speeds & ETH_LINK_SPEED_100M)
1809                 link_speed |= I40E_LINK_SPEED_100MB;
1810
1811         return link_speed;
1812 }
1813
1814 static int
1815 i40e_phy_conf_link(struct i40e_hw *hw,
1816                    uint8_t abilities,
1817                    uint8_t force_speed)
1818 {
1819         enum i40e_status_code status;
1820         struct i40e_aq_get_phy_abilities_resp phy_ab;
1821         struct i40e_aq_set_phy_config phy_conf;
1822         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1823                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1824                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1825                         I40E_AQ_PHY_FLAG_LOW_POWER;
1826         const uint8_t advt = I40E_LINK_SPEED_40GB |
1827                         I40E_LINK_SPEED_25GB |
1828                         I40E_LINK_SPEED_10GB |
1829                         I40E_LINK_SPEED_1GB |
1830                         I40E_LINK_SPEED_100MB;
1831         int ret = -ENOTSUP;
1832
1833
1834         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1835                                               NULL);
1836         if (status)
1837                 return ret;
1838
1839         memset(&phy_conf, 0, sizeof(phy_conf));
1840
1841         /* bits 0-2 use the values from get_phy_abilities_resp */
1842         abilities &= ~mask;
1843         abilities |= phy_ab.abilities & mask;
1844
1845         /* update ablities and speed */
1846         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1847                 phy_conf.link_speed = advt;
1848         else
1849                 phy_conf.link_speed = force_speed;
1850
1851         phy_conf.abilities = abilities;
1852
1853         /* use get_phy_abilities_resp value for the rest */
1854         phy_conf.phy_type = phy_ab.phy_type;
1855         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1856         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1857         phy_conf.eee_capability = phy_ab.eee_capability;
1858         phy_conf.eeer = phy_ab.eeer_val;
1859         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1860
1861         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1862                     phy_ab.abilities, phy_ab.link_speed);
1863         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1864                     phy_conf.abilities, phy_conf.link_speed);
1865
1866         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1867         if (status)
1868                 return ret;
1869
1870         return I40E_SUCCESS;
1871 }
1872
1873 static int
1874 i40e_apply_link_speed(struct rte_eth_dev *dev)
1875 {
1876         uint8_t speed;
1877         uint8_t abilities = 0;
1878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         struct rte_eth_conf *conf = &dev->data->dev_conf;
1880
1881         speed = i40e_parse_link_speeds(conf->link_speeds);
1882         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1883         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1884                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1885         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1886
1887         /* Skip changing speed on 40G interfaces, FW does not support */
1888         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1889                 speed =  I40E_LINK_SPEED_UNKNOWN;
1890                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1891         }
1892
1893         return i40e_phy_conf_link(hw, abilities, speed);
1894 }
1895
1896 static int
1897 i40e_dev_start(struct rte_eth_dev *dev)
1898 {
1899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         struct i40e_vsi *main_vsi = pf->main_vsi;
1902         int ret, i;
1903         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1904         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1905         uint32_t intr_vector = 0;
1906         struct i40e_vsi *vsi;
1907
1908         hw->adapter_stopped = 0;
1909
1910         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1911                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1912                              dev->data->port_id);
1913                 return -EINVAL;
1914         }
1915
1916         rte_intr_disable(intr_handle);
1917
1918         if ((rte_intr_cap_multiple(intr_handle) ||
1919              !RTE_ETH_DEV_SRIOV(dev).active) &&
1920             dev->data->dev_conf.intr_conf.rxq != 0) {
1921                 intr_vector = dev->data->nb_rx_queues;
1922                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1923                 if (ret)
1924                         return ret;
1925         }
1926
1927         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1928                 intr_handle->intr_vec =
1929                         rte_zmalloc("intr_vec",
1930                                     dev->data->nb_rx_queues * sizeof(int),
1931                                     0);
1932                 if (!intr_handle->intr_vec) {
1933                         PMD_INIT_LOG(ERR,
1934                                 "Failed to allocate %d rx_queues intr_vec",
1935                                 dev->data->nb_rx_queues);
1936                         return -ENOMEM;
1937                 }
1938         }
1939
1940         /* Initialize VSI */
1941         ret = i40e_dev_rxtx_init(pf);
1942         if (ret != I40E_SUCCESS) {
1943                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1944                 goto err_up;
1945         }
1946
1947         /* Map queues with MSIX interrupt */
1948         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1949                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1950         i40e_vsi_queues_bind_intr(main_vsi);
1951         i40e_vsi_enable_queues_intr(main_vsi);
1952
1953         /* Map VMDQ VSI queues with MSIX interrupt */
1954         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1955                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1956                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1957                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1958         }
1959
1960         /* enable FDIR MSIX interrupt */
1961         if (pf->fdir.fdir_vsi) {
1962                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1963                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1964         }
1965
1966         /* Enable all queues which have been configured */
1967         ret = i40e_dev_switch_queues(pf, TRUE);
1968         if (ret != I40E_SUCCESS) {
1969                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1970                 goto err_up;
1971         }
1972
1973         /* Enable receiving broadcast packets */
1974         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1975         if (ret != I40E_SUCCESS)
1976                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1977
1978         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1979                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1980                                                 true, NULL);
1981                 if (ret != I40E_SUCCESS)
1982                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1983         }
1984
1985         /* Enable the VLAN promiscuous mode. */
1986         if (pf->vfs) {
1987                 for (i = 0; i < pf->vf_num; i++) {
1988                         vsi = pf->vfs[i].vsi;
1989                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1990                                                      true, NULL);
1991                 }
1992         }
1993
1994         /* Apply link configure */
1995         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1996                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1997                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1998                                 ETH_LINK_SPEED_40G)) {
1999                 PMD_DRV_LOG(ERR, "Invalid link setting");
2000                 goto err_up;
2001         }
2002         ret = i40e_apply_link_speed(dev);
2003         if (I40E_SUCCESS != ret) {
2004                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2005                 goto err_up;
2006         }
2007
2008         if (!rte_intr_allow_others(intr_handle)) {
2009                 rte_intr_callback_unregister(intr_handle,
2010                                              i40e_dev_interrupt_handler,
2011                                              (void *)dev);
2012                 /* configure and enable device interrupt */
2013                 i40e_pf_config_irq0(hw, FALSE);
2014                 i40e_pf_enable_irq0(hw);
2015
2016                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2017                         PMD_INIT_LOG(INFO,
2018                                 "lsc won't enable because of no intr multiplex");
2019         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2020                 ret = i40e_aq_set_phy_int_mask(hw,
2021                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2022                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2023                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2024                 if (ret != I40E_SUCCESS)
2025                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2026
2027                 /* Call get_link_info aq commond to enable LSE */
2028                 i40e_dev_link_update(dev, 0);
2029         }
2030
2031         /* enable uio intr after callback register */
2032         rte_intr_enable(intr_handle);
2033
2034         i40e_filter_restore(pf);
2035
2036         if (!pf->tm_conf.committed)
2037                 PMD_DRV_LOG(WARNING,
2038                             "please call hierarchy_commit() "
2039                             "before starting the port");
2040
2041         return I40E_SUCCESS;
2042
2043 err_up:
2044         i40e_dev_switch_queues(pf, FALSE);
2045         i40e_dev_clear_queues(dev);
2046
2047         return ret;
2048 }
2049
2050 static void
2051 i40e_dev_stop(struct rte_eth_dev *dev)
2052 {
2053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054         struct i40e_vsi *main_vsi = pf->main_vsi;
2055         struct i40e_mirror_rule *p_mirror;
2056         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058         int i;
2059
2060         /* Disable all queues */
2061         i40e_dev_switch_queues(pf, FALSE);
2062
2063         /* un-map queues with interrupt registers */
2064         i40e_vsi_disable_queues_intr(main_vsi);
2065         i40e_vsi_queues_unbind_intr(main_vsi);
2066
2067         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2068                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2069                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2070         }
2071
2072         if (pf->fdir.fdir_vsi) {
2073                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2074                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2075         }
2076         /* Clear all queues and release memory */
2077         i40e_dev_clear_queues(dev);
2078
2079         /* Set link down */
2080         i40e_dev_set_link_down(dev);
2081
2082         /* Remove all mirror rules */
2083         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2084                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2085                 rte_free(p_mirror);
2086         }
2087         pf->nb_mirror_rule = 0;
2088
2089         if (!rte_intr_allow_others(intr_handle))
2090                 /* resume to the default handler */
2091                 rte_intr_callback_register(intr_handle,
2092                                            i40e_dev_interrupt_handler,
2093                                            (void *)dev);
2094
2095         /* Clean datapath event and queue/vec mapping */
2096         rte_intr_efd_disable(intr_handle);
2097         if (intr_handle->intr_vec) {
2098                 rte_free(intr_handle->intr_vec);
2099                 intr_handle->intr_vec = NULL;
2100         }
2101
2102         /* reset hierarchy commit */
2103         pf->tm_conf.committed = false;
2104 }
2105
2106 static void
2107 i40e_dev_close(struct rte_eth_dev *dev)
2108 {
2109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2112         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2113         uint32_t reg;
2114         int i;
2115
2116         PMD_INIT_FUNC_TRACE();
2117
2118         i40e_dev_stop(dev);
2119         hw->adapter_stopped = 1;
2120         i40e_dev_free_queues(dev);
2121
2122         /* Disable interrupt */
2123         i40e_pf_disable_irq0(hw);
2124         rte_intr_disable(intr_handle);
2125
2126         /* shutdown and destroy the HMC */
2127         i40e_shutdown_lan_hmc(hw);
2128
2129         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2130                 i40e_vsi_release(pf->vmdq[i].vsi);
2131                 pf->vmdq[i].vsi = NULL;
2132         }
2133         rte_free(pf->vmdq);
2134         pf->vmdq = NULL;
2135
2136         /* release all the existing VSIs and VEBs */
2137         i40e_fdir_teardown(pf);
2138         i40e_vsi_release(pf->main_vsi);
2139
2140         /* shutdown the adminq */
2141         i40e_aq_queue_shutdown(hw, true);
2142         i40e_shutdown_adminq(hw);
2143
2144         i40e_res_pool_destroy(&pf->qp_pool);
2145         i40e_res_pool_destroy(&pf->msix_pool);
2146
2147         /* force a PF reset to clean anything leftover */
2148         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2149         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2150                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2151         I40E_WRITE_FLUSH(hw);
2152 }
2153
2154 static void
2155 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2156 {
2157         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159         struct i40e_vsi *vsi = pf->main_vsi;
2160         int status;
2161
2162         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2163                                                      true, NULL, true);
2164         if (status != I40E_SUCCESS)
2165                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2166
2167         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2168                                                         TRUE, NULL);
2169         if (status != I40E_SUCCESS)
2170                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2171
2172 }
2173
2174 static void
2175 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2176 {
2177         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2178         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179         struct i40e_vsi *vsi = pf->main_vsi;
2180         int status;
2181
2182         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2183                                                      false, NULL, true);
2184         if (status != I40E_SUCCESS)
2185                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2186
2187         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2188                                                         false, NULL);
2189         if (status != I40E_SUCCESS)
2190                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2191 }
2192
2193 static void
2194 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2195 {
2196         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2197         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198         struct i40e_vsi *vsi = pf->main_vsi;
2199         int ret;
2200
2201         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2202         if (ret != I40E_SUCCESS)
2203                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2204 }
2205
2206 static void
2207 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2208 {
2209         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2210         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211         struct i40e_vsi *vsi = pf->main_vsi;
2212         int ret;
2213
2214         if (dev->data->promiscuous == 1)
2215                 return; /* must remain in all_multicast mode */
2216
2217         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2218                                 vsi->seid, FALSE, NULL);
2219         if (ret != I40E_SUCCESS)
2220                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2221 }
2222
2223 /*
2224  * Set device link up.
2225  */
2226 static int
2227 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2228 {
2229         /* re-apply link speed setting */
2230         return i40e_apply_link_speed(dev);
2231 }
2232
2233 /*
2234  * Set device link down.
2235  */
2236 static int
2237 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2238 {
2239         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2240         uint8_t abilities = 0;
2241         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242
2243         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2244         return i40e_phy_conf_link(hw, abilities, speed);
2245 }
2246
2247 int
2248 i40e_dev_link_update(struct rte_eth_dev *dev,
2249                      int wait_to_complete)
2250 {
2251 #define CHECK_INTERVAL 100  /* 100ms */
2252 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2253         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2254         struct i40e_link_status link_status;
2255         struct rte_eth_link link, old;
2256         int status;
2257         unsigned rep_cnt = MAX_REPEAT_TIME;
2258         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2259
2260         memset(&link, 0, sizeof(link));
2261         memset(&old, 0, sizeof(old));
2262         memset(&link_status, 0, sizeof(link_status));
2263         rte_i40e_dev_atomic_read_link_status(dev, &old);
2264
2265         do {
2266                 /* Get link status information from hardware */
2267                 status = i40e_aq_get_link_info(hw, enable_lse,
2268                                                 &link_status, NULL);
2269                 if (status != I40E_SUCCESS) {
2270                         link.link_speed = ETH_SPEED_NUM_100M;
2271                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2272                         PMD_DRV_LOG(ERR, "Failed to get link info");
2273                         goto out;
2274                 }
2275
2276                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2277                 if (!wait_to_complete || link.link_status)
2278                         break;
2279
2280                 rte_delay_ms(CHECK_INTERVAL);
2281         } while (--rep_cnt);
2282
2283         if (!link.link_status)
2284                 goto out;
2285
2286         /* i40e uses full duplex only */
2287         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2288
2289         /* Parse the link status */
2290         switch (link_status.link_speed) {
2291         case I40E_LINK_SPEED_100MB:
2292                 link.link_speed = ETH_SPEED_NUM_100M;
2293                 break;
2294         case I40E_LINK_SPEED_1GB:
2295                 link.link_speed = ETH_SPEED_NUM_1G;
2296                 break;
2297         case I40E_LINK_SPEED_10GB:
2298                 link.link_speed = ETH_SPEED_NUM_10G;
2299                 break;
2300         case I40E_LINK_SPEED_20GB:
2301                 link.link_speed = ETH_SPEED_NUM_20G;
2302                 break;
2303         case I40E_LINK_SPEED_25GB:
2304                 link.link_speed = ETH_SPEED_NUM_25G;
2305                 break;
2306         case I40E_LINK_SPEED_40GB:
2307                 link.link_speed = ETH_SPEED_NUM_40G;
2308                 break;
2309         default:
2310                 link.link_speed = ETH_SPEED_NUM_100M;
2311                 break;
2312         }
2313
2314         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2315                         ETH_LINK_SPEED_FIXED);
2316
2317 out:
2318         rte_i40e_dev_atomic_write_link_status(dev, &link);
2319         if (link.link_status == old.link_status)
2320                 return -1;
2321
2322         i40e_notify_all_vfs_link_status(dev);
2323
2324         return 0;
2325 }
2326
2327 /* Get all the statistics of a VSI */
2328 void
2329 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2330 {
2331         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2332         struct i40e_eth_stats *nes = &vsi->eth_stats;
2333         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2334         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2335
2336         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2337                             vsi->offset_loaded, &oes->rx_bytes,
2338                             &nes->rx_bytes);
2339         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2340                             vsi->offset_loaded, &oes->rx_unicast,
2341                             &nes->rx_unicast);
2342         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2343                             vsi->offset_loaded, &oes->rx_multicast,
2344                             &nes->rx_multicast);
2345         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2346                             vsi->offset_loaded, &oes->rx_broadcast,
2347                             &nes->rx_broadcast);
2348         /* exclude CRC bytes */
2349         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2350                 nes->rx_broadcast) * ETHER_CRC_LEN;
2351
2352         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2353                             &oes->rx_discards, &nes->rx_discards);
2354         /* GLV_REPC not supported */
2355         /* GLV_RMPC not supported */
2356         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2357                             &oes->rx_unknown_protocol,
2358                             &nes->rx_unknown_protocol);
2359         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2360                             vsi->offset_loaded, &oes->tx_bytes,
2361                             &nes->tx_bytes);
2362         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2363                             vsi->offset_loaded, &oes->tx_unicast,
2364                             &nes->tx_unicast);
2365         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2366                             vsi->offset_loaded, &oes->tx_multicast,
2367                             &nes->tx_multicast);
2368         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2369                             vsi->offset_loaded,  &oes->tx_broadcast,
2370                             &nes->tx_broadcast);
2371         /* exclude CRC bytes */
2372         nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2373                 nes->tx_broadcast) * ETHER_CRC_LEN;
2374         /* GLV_TDPC not supported */
2375         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2376                             &oes->tx_errors, &nes->tx_errors);
2377         vsi->offset_loaded = true;
2378
2379         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2380                     vsi->vsi_id);
2381         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2382         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2383         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2384         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2385         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2386         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2387                     nes->rx_unknown_protocol);
2388         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2389         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2390         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2391         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2392         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2393         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2394         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2395                     vsi->vsi_id);
2396 }
2397
2398 static void
2399 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2400 {
2401         unsigned int i;
2402         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2403         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2404
2405         /* Get rx/tx bytes of internal transfer packets */
2406         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2407                         I40E_GLV_GORCL(hw->port),
2408                         pf->offset_loaded,
2409                         &pf->internal_stats_offset.rx_bytes,
2410                         &pf->internal_stats.rx_bytes);
2411
2412         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2413                         I40E_GLV_GOTCL(hw->port),
2414                         pf->offset_loaded,
2415                         &pf->internal_stats_offset.tx_bytes,
2416                         &pf->internal_stats.tx_bytes);
2417         /* Get total internal rx packet count */
2418         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2419                             I40E_GLV_UPRCL(hw->port),
2420                             pf->offset_loaded,
2421                             &pf->internal_stats_offset.rx_unicast,
2422                             &pf->internal_stats.rx_unicast);
2423         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2424                             I40E_GLV_MPRCL(hw->port),
2425                             pf->offset_loaded,
2426                             &pf->internal_stats_offset.rx_multicast,
2427                             &pf->internal_stats.rx_multicast);
2428         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2429                             I40E_GLV_BPRCL(hw->port),
2430                             pf->offset_loaded,
2431                             &pf->internal_stats_offset.rx_broadcast,
2432                             &pf->internal_stats.rx_broadcast);
2433
2434         /* exclude CRC size */
2435         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2436                 pf->internal_stats.rx_multicast +
2437                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2438
2439         /* Get statistics of struct i40e_eth_stats */
2440         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2441                             I40E_GLPRT_GORCL(hw->port),
2442                             pf->offset_loaded, &os->eth.rx_bytes,
2443                             &ns->eth.rx_bytes);
2444         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2445                             I40E_GLPRT_UPRCL(hw->port),
2446                             pf->offset_loaded, &os->eth.rx_unicast,
2447                             &ns->eth.rx_unicast);
2448         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2449                             I40E_GLPRT_MPRCL(hw->port),
2450                             pf->offset_loaded, &os->eth.rx_multicast,
2451                             &ns->eth.rx_multicast);
2452         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2453                             I40E_GLPRT_BPRCL(hw->port),
2454                             pf->offset_loaded, &os->eth.rx_broadcast,
2455                             &ns->eth.rx_broadcast);
2456         /* Workaround: CRC size should not be included in byte statistics,
2457          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2458          */
2459         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2460                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2461
2462         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2463          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2464          * value.
2465          */
2466         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2467                 ns->eth.rx_bytes = 0;
2468         /* exlude internal rx bytes */
2469         else
2470                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2471
2472         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2473                             pf->offset_loaded, &os->eth.rx_discards,
2474                             &ns->eth.rx_discards);
2475         /* GLPRT_REPC not supported */
2476         /* GLPRT_RMPC not supported */
2477         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2478                             pf->offset_loaded,
2479                             &os->eth.rx_unknown_protocol,
2480                             &ns->eth.rx_unknown_protocol);
2481         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2482                             I40E_GLPRT_GOTCL(hw->port),
2483                             pf->offset_loaded, &os->eth.tx_bytes,
2484                             &ns->eth.tx_bytes);
2485         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2486                             I40E_GLPRT_UPTCL(hw->port),
2487                             pf->offset_loaded, &os->eth.tx_unicast,
2488                             &ns->eth.tx_unicast);
2489         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2490                             I40E_GLPRT_MPTCL(hw->port),
2491                             pf->offset_loaded, &os->eth.tx_multicast,
2492                             &ns->eth.tx_multicast);
2493         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2494                             I40E_GLPRT_BPTCL(hw->port),
2495                             pf->offset_loaded, &os->eth.tx_broadcast,
2496                             &ns->eth.tx_broadcast);
2497         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2498                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2499
2500         /* exclude internal tx bytes */
2501         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2502                 ns->eth.tx_bytes = 0;
2503         else
2504                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2505
2506         /* GLPRT_TEPC not supported */
2507
2508         /* additional port specific stats */
2509         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2510                             pf->offset_loaded, &os->tx_dropped_link_down,
2511                             &ns->tx_dropped_link_down);
2512         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2513                             pf->offset_loaded, &os->crc_errors,
2514                             &ns->crc_errors);
2515         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2516                             pf->offset_loaded, &os->illegal_bytes,
2517                             &ns->illegal_bytes);
2518         /* GLPRT_ERRBC not supported */
2519         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2520                             pf->offset_loaded, &os->mac_local_faults,
2521                             &ns->mac_local_faults);
2522         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2523                             pf->offset_loaded, &os->mac_remote_faults,
2524                             &ns->mac_remote_faults);
2525         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2526                             pf->offset_loaded, &os->rx_length_errors,
2527                             &ns->rx_length_errors);
2528         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2529                             pf->offset_loaded, &os->link_xon_rx,
2530                             &ns->link_xon_rx);
2531         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2532                             pf->offset_loaded, &os->link_xoff_rx,
2533                             &ns->link_xoff_rx);
2534         for (i = 0; i < 8; i++) {
2535                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2536                                     pf->offset_loaded,
2537                                     &os->priority_xon_rx[i],
2538                                     &ns->priority_xon_rx[i]);
2539                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2540                                     pf->offset_loaded,
2541                                     &os->priority_xoff_rx[i],
2542                                     &ns->priority_xoff_rx[i]);
2543         }
2544         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2545                             pf->offset_loaded, &os->link_xon_tx,
2546                             &ns->link_xon_tx);
2547         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2548                             pf->offset_loaded, &os->link_xoff_tx,
2549                             &ns->link_xoff_tx);
2550         for (i = 0; i < 8; i++) {
2551                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2552                                     pf->offset_loaded,
2553                                     &os->priority_xon_tx[i],
2554                                     &ns->priority_xon_tx[i]);
2555                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2556                                     pf->offset_loaded,
2557                                     &os->priority_xoff_tx[i],
2558                                     &ns->priority_xoff_tx[i]);
2559                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2560                                     pf->offset_loaded,
2561                                     &os->priority_xon_2_xoff[i],
2562                                     &ns->priority_xon_2_xoff[i]);
2563         }
2564         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2565                             I40E_GLPRT_PRC64L(hw->port),
2566                             pf->offset_loaded, &os->rx_size_64,
2567                             &ns->rx_size_64);
2568         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2569                             I40E_GLPRT_PRC127L(hw->port),
2570                             pf->offset_loaded, &os->rx_size_127,
2571                             &ns->rx_size_127);
2572         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2573                             I40E_GLPRT_PRC255L(hw->port),
2574                             pf->offset_loaded, &os->rx_size_255,
2575                             &ns->rx_size_255);
2576         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2577                             I40E_GLPRT_PRC511L(hw->port),
2578                             pf->offset_loaded, &os->rx_size_511,
2579                             &ns->rx_size_511);
2580         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2581                             I40E_GLPRT_PRC1023L(hw->port),
2582                             pf->offset_loaded, &os->rx_size_1023,
2583                             &ns->rx_size_1023);
2584         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2585                             I40E_GLPRT_PRC1522L(hw->port),
2586                             pf->offset_loaded, &os->rx_size_1522,
2587                             &ns->rx_size_1522);
2588         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2589                             I40E_GLPRT_PRC9522L(hw->port),
2590                             pf->offset_loaded, &os->rx_size_big,
2591                             &ns->rx_size_big);
2592         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2593                             pf->offset_loaded, &os->rx_undersize,
2594                             &ns->rx_undersize);
2595         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2596                             pf->offset_loaded, &os->rx_fragments,
2597                             &ns->rx_fragments);
2598         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2599                             pf->offset_loaded, &os->rx_oversize,
2600                             &ns->rx_oversize);
2601         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2602                             pf->offset_loaded, &os->rx_jabber,
2603                             &ns->rx_jabber);
2604         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2605                             I40E_GLPRT_PTC64L(hw->port),
2606                             pf->offset_loaded, &os->tx_size_64,
2607                             &ns->tx_size_64);
2608         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2609                             I40E_GLPRT_PTC127L(hw->port),
2610                             pf->offset_loaded, &os->tx_size_127,
2611                             &ns->tx_size_127);
2612         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2613                             I40E_GLPRT_PTC255L(hw->port),
2614                             pf->offset_loaded, &os->tx_size_255,
2615                             &ns->tx_size_255);
2616         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2617                             I40E_GLPRT_PTC511L(hw->port),
2618                             pf->offset_loaded, &os->tx_size_511,
2619                             &ns->tx_size_511);
2620         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2621                             I40E_GLPRT_PTC1023L(hw->port),
2622                             pf->offset_loaded, &os->tx_size_1023,
2623                             &ns->tx_size_1023);
2624         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2625                             I40E_GLPRT_PTC1522L(hw->port),
2626                             pf->offset_loaded, &os->tx_size_1522,
2627                             &ns->tx_size_1522);
2628         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2629                             I40E_GLPRT_PTC9522L(hw->port),
2630                             pf->offset_loaded, &os->tx_size_big,
2631                             &ns->tx_size_big);
2632         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2633                            pf->offset_loaded,
2634                            &os->fd_sb_match, &ns->fd_sb_match);
2635         /* GLPRT_MSPDC not supported */
2636         /* GLPRT_XEC not supported */
2637
2638         pf->offset_loaded = true;
2639
2640         if (pf->main_vsi)
2641                 i40e_update_vsi_stats(pf->main_vsi);
2642 }
2643
2644 /* Get all statistics of a port */
2645 static void
2646 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2647 {
2648         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2649         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2650         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2651         unsigned i;
2652
2653         /* call read registers - updates values, now write them to struct */
2654         i40e_read_stats_registers(pf, hw);
2655
2656         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2657                         pf->main_vsi->eth_stats.rx_multicast +
2658                         pf->main_vsi->eth_stats.rx_broadcast -
2659                         pf->main_vsi->eth_stats.rx_discards;
2660         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2661                         pf->main_vsi->eth_stats.tx_multicast +
2662                         pf->main_vsi->eth_stats.tx_broadcast;
2663         stats->ibytes   = ns->eth.rx_bytes;
2664         stats->obytes   = ns->eth.tx_bytes;
2665         stats->oerrors  = ns->eth.tx_errors +
2666                         pf->main_vsi->eth_stats.tx_errors;
2667
2668         /* Rx Errors */
2669         stats->imissed  = ns->eth.rx_discards +
2670                         pf->main_vsi->eth_stats.rx_discards;
2671         stats->ierrors  = ns->crc_errors +
2672                         ns->rx_length_errors + ns->rx_undersize +
2673                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2674
2675         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2676         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2677         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2678         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2679         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2680         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2681         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2682                     ns->eth.rx_unknown_protocol);
2683         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2684         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2685         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2686         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2687         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2688         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2689
2690         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2691                     ns->tx_dropped_link_down);
2692         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2693         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2694                     ns->illegal_bytes);
2695         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2696         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2697                     ns->mac_local_faults);
2698         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2699                     ns->mac_remote_faults);
2700         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2701                     ns->rx_length_errors);
2702         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2703         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2704         for (i = 0; i < 8; i++) {
2705                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2706                                 i, ns->priority_xon_rx[i]);
2707                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2708                                 i, ns->priority_xoff_rx[i]);
2709         }
2710         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2711         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2712         for (i = 0; i < 8; i++) {
2713                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2714                                 i, ns->priority_xon_tx[i]);
2715                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2716                                 i, ns->priority_xoff_tx[i]);
2717                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2718                                 i, ns->priority_xon_2_xoff[i]);
2719         }
2720         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2721         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2722         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2723         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2724         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2725         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2726         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2727         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2728         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2729         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2730         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2731         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2732         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2733         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2734         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2735         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2736         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2737         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2738         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2739                         ns->mac_short_packet_dropped);
2740         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2741                     ns->checksum_error);
2742         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2743         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2744 }
2745
2746 /* Reset the statistics */
2747 static void
2748 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2749 {
2750         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2752
2753         /* Mark PF and VSI stats to update the offset, aka "reset" */
2754         pf->offset_loaded = false;
2755         if (pf->main_vsi)
2756                 pf->main_vsi->offset_loaded = false;
2757
2758         /* read the stats, reading current register values into offset */
2759         i40e_read_stats_registers(pf, hw);
2760 }
2761
2762 static uint32_t
2763 i40e_xstats_calc_num(void)
2764 {
2765         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2766                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2767                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2768 }
2769
2770 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2771                                      struct rte_eth_xstat_name *xstats_names,
2772                                      __rte_unused unsigned limit)
2773 {
2774         unsigned count = 0;
2775         unsigned i, prio;
2776
2777         if (xstats_names == NULL)
2778                 return i40e_xstats_calc_num();
2779
2780         /* Note: limit checked in rte_eth_xstats_names() */
2781
2782         /* Get stats from i40e_eth_stats struct */
2783         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2784                 snprintf(xstats_names[count].name,
2785                          sizeof(xstats_names[count].name),
2786                          "%s", rte_i40e_stats_strings[i].name);
2787                 count++;
2788         }
2789
2790         /* Get individiual stats from i40e_hw_port struct */
2791         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2792                 snprintf(xstats_names[count].name,
2793                         sizeof(xstats_names[count].name),
2794                          "%s", rte_i40e_hw_port_strings[i].name);
2795                 count++;
2796         }
2797
2798         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2799                 for (prio = 0; prio < 8; prio++) {
2800                         snprintf(xstats_names[count].name,
2801                                  sizeof(xstats_names[count].name),
2802                                  "rx_priority%u_%s", prio,
2803                                  rte_i40e_rxq_prio_strings[i].name);
2804                         count++;
2805                 }
2806         }
2807
2808         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2809                 for (prio = 0; prio < 8; prio++) {
2810                         snprintf(xstats_names[count].name,
2811                                  sizeof(xstats_names[count].name),
2812                                  "tx_priority%u_%s", prio,
2813                                  rte_i40e_txq_prio_strings[i].name);
2814                         count++;
2815                 }
2816         }
2817         return count;
2818 }
2819
2820 static int
2821 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2822                     unsigned n)
2823 {
2824         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2825         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2826         unsigned i, count, prio;
2827         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2828
2829         count = i40e_xstats_calc_num();
2830         if (n < count)
2831                 return count;
2832
2833         i40e_read_stats_registers(pf, hw);
2834
2835         if (xstats == NULL)
2836                 return 0;
2837
2838         count = 0;
2839
2840         /* Get stats from i40e_eth_stats struct */
2841         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2842                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2843                         rte_i40e_stats_strings[i].offset);
2844                 xstats[count].id = count;
2845                 count++;
2846         }
2847
2848         /* Get individiual stats from i40e_hw_port struct */
2849         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2850                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2851                         rte_i40e_hw_port_strings[i].offset);
2852                 xstats[count].id = count;
2853                 count++;
2854         }
2855
2856         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2857                 for (prio = 0; prio < 8; prio++) {
2858                         xstats[count].value =
2859                                 *(uint64_t *)(((char *)hw_stats) +
2860                                 rte_i40e_rxq_prio_strings[i].offset +
2861                                 (sizeof(uint64_t) * prio));
2862                         xstats[count].id = count;
2863                         count++;
2864                 }
2865         }
2866
2867         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2868                 for (prio = 0; prio < 8; prio++) {
2869                         xstats[count].value =
2870                                 *(uint64_t *)(((char *)hw_stats) +
2871                                 rte_i40e_txq_prio_strings[i].offset +
2872                                 (sizeof(uint64_t) * prio));
2873                         xstats[count].id = count;
2874                         count++;
2875                 }
2876         }
2877
2878         return count;
2879 }
2880
2881 static int
2882 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2883                                  __rte_unused uint16_t queue_id,
2884                                  __rte_unused uint8_t stat_idx,
2885                                  __rte_unused uint8_t is_rx)
2886 {
2887         PMD_INIT_FUNC_TRACE();
2888
2889         return -ENOSYS;
2890 }
2891
2892 static int
2893 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2894 {
2895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896         u32 full_ver;
2897         u8 ver, patch;
2898         u16 build;
2899         int ret;
2900
2901         full_ver = hw->nvm.oem_ver;
2902         ver = (u8)(full_ver >> 24);
2903         build = (u16)((full_ver >> 8) & 0xffff);
2904         patch = (u8)(full_ver & 0xff);
2905
2906         ret = snprintf(fw_version, fw_size,
2907                  "%d.%d%d 0x%08x %d.%d.%d",
2908                  ((hw->nvm.version >> 12) & 0xf),
2909                  ((hw->nvm.version >> 4) & 0xff),
2910                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2911                  ver, build, patch);
2912
2913         ret += 1; /* add the size of '\0' */
2914         if (fw_size < (u32)ret)
2915                 return ret;
2916         else
2917                 return 0;
2918 }
2919
2920 static void
2921 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2922 {
2923         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2924         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2925         struct i40e_vsi *vsi = pf->main_vsi;
2926         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2927
2928         dev_info->pci_dev = pci_dev;
2929         dev_info->max_rx_queues = vsi->nb_qps;
2930         dev_info->max_tx_queues = vsi->nb_qps;
2931         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2932         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2933         dev_info->max_mac_addrs = vsi->max_macaddrs;
2934         dev_info->max_vfs = pci_dev->max_vfs;
2935         dev_info->rx_offload_capa =
2936                 DEV_RX_OFFLOAD_VLAN_STRIP |
2937                 DEV_RX_OFFLOAD_QINQ_STRIP |
2938                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2939                 DEV_RX_OFFLOAD_UDP_CKSUM |
2940                 DEV_RX_OFFLOAD_TCP_CKSUM;
2941         dev_info->tx_offload_capa =
2942                 DEV_TX_OFFLOAD_VLAN_INSERT |
2943                 DEV_TX_OFFLOAD_QINQ_INSERT |
2944                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2945                 DEV_TX_OFFLOAD_UDP_CKSUM |
2946                 DEV_TX_OFFLOAD_TCP_CKSUM |
2947                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2948                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2949                 DEV_TX_OFFLOAD_TCP_TSO |
2950                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2951                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2952                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2953                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2954         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2955                                                 sizeof(uint32_t);
2956         dev_info->reta_size = pf->hash_lut_size;
2957         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2958
2959         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2960                 .rx_thresh = {
2961                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2962                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2963                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2964                 },
2965                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2966                 .rx_drop_en = 0,
2967         };
2968
2969         dev_info->default_txconf = (struct rte_eth_txconf) {
2970                 .tx_thresh = {
2971                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2972                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2973                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2974                 },
2975                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2976                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2977                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2978                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2979         };
2980
2981         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2982                 .nb_max = I40E_MAX_RING_DESC,
2983                 .nb_min = I40E_MIN_RING_DESC,
2984                 .nb_align = I40E_ALIGN_RING_DESC,
2985         };
2986
2987         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2988                 .nb_max = I40E_MAX_RING_DESC,
2989                 .nb_min = I40E_MIN_RING_DESC,
2990                 .nb_align = I40E_ALIGN_RING_DESC,
2991                 .nb_seg_max = I40E_TX_MAX_SEG,
2992                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2993         };
2994
2995         if (pf->flags & I40E_FLAG_VMDQ) {
2996                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2997                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2998                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2999                                                 pf->max_nb_vmdq_vsi;
3000                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3001                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3002                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3003         }
3004
3005         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3006                 /* For XL710 */
3007                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3008         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3009                 /* For XXV710 */
3010                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3011         else
3012                 /* For X710 */
3013                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3014 }
3015
3016 static int
3017 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3018 {
3019         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3020         struct i40e_vsi *vsi = pf->main_vsi;
3021         PMD_INIT_FUNC_TRACE();
3022
3023         if (on)
3024                 return i40e_vsi_add_vlan(vsi, vlan_id);
3025         else
3026                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3027 }
3028
3029 static int
3030 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3031                                 enum rte_vlan_type vlan_type,
3032                                 uint16_t tpid, int qinq)
3033 {
3034         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3035         uint64_t reg_r = 0;
3036         uint64_t reg_w = 0;
3037         uint16_t reg_id = 3;
3038         int ret;
3039
3040         if (qinq) {
3041                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3042                         reg_id = 2;
3043         }
3044
3045         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3046                                           &reg_r, NULL);
3047         if (ret != I40E_SUCCESS) {
3048                 PMD_DRV_LOG(ERR,
3049                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3050                            reg_id);
3051                 return -EIO;
3052         }
3053         PMD_DRV_LOG(DEBUG,
3054                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3055                     reg_id, reg_r);
3056
3057         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3058         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3059         if (reg_r == reg_w) {
3060                 PMD_DRV_LOG(DEBUG, "No need to write");
3061                 return 0;
3062         }
3063
3064         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3065                                            reg_w, NULL);
3066         if (ret != I40E_SUCCESS) {
3067                 PMD_DRV_LOG(ERR,
3068                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3069                             reg_id);
3070                 return -EIO;
3071         }
3072         PMD_DRV_LOG(DEBUG,
3073                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3074                     reg_w, reg_id);
3075
3076         return 0;
3077 }
3078
3079 static int
3080 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3081                    enum rte_vlan_type vlan_type,
3082                    uint16_t tpid)
3083 {
3084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3085         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3086         int ret = 0;
3087
3088         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3089              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3090             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3091                 PMD_DRV_LOG(ERR,
3092                             "Unsupported vlan type.");
3093                 return -EINVAL;
3094         }
3095         /* 802.1ad frames ability is added in NVM API 1.7*/
3096         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3097                 if (qinq) {
3098                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3099                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3100                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3101                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3102                 } else {
3103                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3104                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3105                 }
3106                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3107                 if (ret != I40E_SUCCESS) {
3108                         PMD_DRV_LOG(ERR,
3109                                     "Set switch config failed aq_err: %d",
3110                                     hw->aq.asq_last_status);
3111                         ret = -EIO;
3112                 }
3113         } else
3114                 /* If NVM API < 1.7, keep the register setting */
3115                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3116                                                       tpid, qinq);
3117
3118         return ret;
3119 }
3120
3121 static void
3122 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3123 {
3124         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3125         struct i40e_vsi *vsi = pf->main_vsi;
3126
3127         if (mask & ETH_VLAN_FILTER_MASK) {
3128                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3129                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3130                 else
3131                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3132         }
3133
3134         if (mask & ETH_VLAN_STRIP_MASK) {
3135                 /* Enable or disable VLAN stripping */
3136                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3137                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3138                 else
3139                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3140         }
3141
3142         if (mask & ETH_VLAN_EXTEND_MASK) {
3143                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3144                         i40e_vsi_config_double_vlan(vsi, TRUE);
3145                         /* Set global registers with default ethertype. */
3146                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3147                                            ETHER_TYPE_VLAN);
3148                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3149                                            ETHER_TYPE_VLAN);
3150                 }
3151                 else
3152                         i40e_vsi_config_double_vlan(vsi, FALSE);
3153         }
3154 }
3155
3156 static void
3157 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3158                           __rte_unused uint16_t queue,
3159                           __rte_unused int on)
3160 {
3161         PMD_INIT_FUNC_TRACE();
3162 }
3163
3164 static int
3165 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3166 {
3167         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3168         struct i40e_vsi *vsi = pf->main_vsi;
3169         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3170         struct i40e_vsi_vlan_pvid_info info;
3171
3172         memset(&info, 0, sizeof(info));
3173         info.on = on;
3174         if (info.on)
3175                 info.config.pvid = pvid;
3176         else {
3177                 info.config.reject.tagged =
3178                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3179                 info.config.reject.untagged =
3180                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3181         }
3182
3183         return i40e_vsi_vlan_pvid_set(vsi, &info);
3184 }
3185
3186 static int
3187 i40e_dev_led_on(struct rte_eth_dev *dev)
3188 {
3189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190         uint32_t mode = i40e_led_get(hw);
3191
3192         if (mode == 0)
3193                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3194
3195         return 0;
3196 }
3197
3198 static int
3199 i40e_dev_led_off(struct rte_eth_dev *dev)
3200 {
3201         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3202         uint32_t mode = i40e_led_get(hw);
3203
3204         if (mode != 0)
3205                 i40e_led_set(hw, 0, false);
3206
3207         return 0;
3208 }
3209
3210 static int
3211 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3212 {
3213         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3215
3216         fc_conf->pause_time = pf->fc_conf.pause_time;
3217         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3218         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3219
3220          /* Return current mode according to actual setting*/
3221         switch (hw->fc.current_mode) {
3222         case I40E_FC_FULL:
3223                 fc_conf->mode = RTE_FC_FULL;
3224                 break;
3225         case I40E_FC_TX_PAUSE:
3226                 fc_conf->mode = RTE_FC_TX_PAUSE;
3227                 break;
3228         case I40E_FC_RX_PAUSE:
3229                 fc_conf->mode = RTE_FC_RX_PAUSE;
3230                 break;
3231         case I40E_FC_NONE:
3232         default:
3233                 fc_conf->mode = RTE_FC_NONE;
3234         };
3235
3236         return 0;
3237 }
3238
3239 static int
3240 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3241 {
3242         uint32_t mflcn_reg, fctrl_reg, reg;
3243         uint32_t max_high_water;
3244         uint8_t i, aq_failure;
3245         int err;
3246         struct i40e_hw *hw;
3247         struct i40e_pf *pf;
3248         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3249                 [RTE_FC_NONE] = I40E_FC_NONE,
3250                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3251                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3252                 [RTE_FC_FULL] = I40E_FC_FULL
3253         };
3254
3255         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3256
3257         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3258         if ((fc_conf->high_water > max_high_water) ||
3259                         (fc_conf->high_water < fc_conf->low_water)) {
3260                 PMD_INIT_LOG(ERR,
3261                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3262                         max_high_water);
3263                 return -EINVAL;
3264         }
3265
3266         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3267         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3268         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3269
3270         pf->fc_conf.pause_time = fc_conf->pause_time;
3271         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3272         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3273
3274         PMD_INIT_FUNC_TRACE();
3275
3276         /* All the link flow control related enable/disable register
3277          * configuration is handle by the F/W
3278          */
3279         err = i40e_set_fc(hw, &aq_failure, true);
3280         if (err < 0)
3281                 return -ENOSYS;
3282
3283         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3284                 /* Configure flow control refresh threshold,
3285                  * the value for stat_tx_pause_refresh_timer[8]
3286                  * is used for global pause operation.
3287                  */
3288
3289                 I40E_WRITE_REG(hw,
3290                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3291                                pf->fc_conf.pause_time);
3292
3293                 /* configure the timer value included in transmitted pause
3294                  * frame,
3295                  * the value for stat_tx_pause_quanta[8] is used for global
3296                  * pause operation
3297                  */
3298                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3299                                pf->fc_conf.pause_time);
3300
3301                 fctrl_reg = I40E_READ_REG(hw,
3302                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3303
3304                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3305                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3306                 else
3307                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3308
3309                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3310                                fctrl_reg);
3311         } else {
3312                 /* Configure pause time (2 TCs per register) */
3313                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3314                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3315                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3316
3317                 /* Configure flow control refresh threshold value */
3318                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3319                                pf->fc_conf.pause_time / 2);
3320
3321                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3322
3323                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3324                  *depending on configuration
3325                  */
3326                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3327                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3328                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3329                 } else {
3330                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3331                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3332                 }
3333
3334                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3335         }
3336
3337         /* config the water marker both based on the packets and bytes */
3338         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3339                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3340                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3341         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3342                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3343                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3344         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3345                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3346                        << I40E_KILOSHIFT);
3347         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3348                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3349                        << I40E_KILOSHIFT);
3350
3351         I40E_WRITE_FLUSH(hw);
3352
3353         return 0;
3354 }
3355
3356 static int
3357 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3358                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3359 {
3360         PMD_INIT_FUNC_TRACE();
3361
3362         return -ENOSYS;
3363 }
3364
3365 /* Add a MAC address, and update filters */
3366 static int
3367 i40e_macaddr_add(struct rte_eth_dev *dev,
3368                  struct ether_addr *mac_addr,
3369                  __rte_unused uint32_t index,
3370                  uint32_t pool)
3371 {
3372         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3373         struct i40e_mac_filter_info mac_filter;
3374         struct i40e_vsi *vsi;
3375         int ret;
3376
3377         /* If VMDQ not enabled or configured, return */
3378         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3379                           !pf->nb_cfg_vmdq_vsi)) {
3380                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3381                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3382                         pool);
3383                 return -ENOTSUP;
3384         }
3385
3386         if (pool > pf->nb_cfg_vmdq_vsi) {
3387                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3388                                 pool, pf->nb_cfg_vmdq_vsi);
3389                 return -EINVAL;
3390         }
3391
3392         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3393         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3394                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3395         else
3396                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3397
3398         if (pool == 0)
3399                 vsi = pf->main_vsi;
3400         else
3401                 vsi = pf->vmdq[pool - 1].vsi;
3402
3403         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3404         if (ret != I40E_SUCCESS) {
3405                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3406                 return -ENODEV;
3407         }
3408         return 0;
3409 }
3410
3411 /* Remove a MAC address, and update filters */
3412 static void
3413 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3414 {
3415         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3416         struct i40e_vsi *vsi;
3417         struct rte_eth_dev_data *data = dev->data;
3418         struct ether_addr *macaddr;
3419         int ret;
3420         uint32_t i;
3421         uint64_t pool_sel;
3422
3423         macaddr = &(data->mac_addrs[index]);
3424
3425         pool_sel = dev->data->mac_pool_sel[index];
3426
3427         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3428                 if (pool_sel & (1ULL << i)) {
3429                         if (i == 0)
3430                                 vsi = pf->main_vsi;
3431                         else {
3432                                 /* No VMDQ pool enabled or configured */
3433                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3434                                         (i > pf->nb_cfg_vmdq_vsi)) {
3435                                         PMD_DRV_LOG(ERR,
3436                                                 "No VMDQ pool enabled/configured");
3437                                         return;
3438                                 }
3439                                 vsi = pf->vmdq[i - 1].vsi;
3440                         }
3441                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3442
3443                         if (ret) {
3444                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3445                                 return;
3446                         }
3447                 }
3448         }
3449 }
3450
3451 /* Set perfect match or hash match of MAC and VLAN for a VF */
3452 static int
3453 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3454                  struct rte_eth_mac_filter *filter,
3455                  bool add)
3456 {
3457         struct i40e_hw *hw;
3458         struct i40e_mac_filter_info mac_filter;
3459         struct ether_addr old_mac;
3460         struct ether_addr *new_mac;
3461         struct i40e_pf_vf *vf = NULL;
3462         uint16_t vf_id;
3463         int ret;
3464
3465         if (pf == NULL) {
3466                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3467                 return -EINVAL;
3468         }
3469         hw = I40E_PF_TO_HW(pf);
3470
3471         if (filter == NULL) {
3472                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3473                 return -EINVAL;
3474         }
3475
3476         new_mac = &filter->mac_addr;
3477
3478         if (is_zero_ether_addr(new_mac)) {
3479                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3480                 return -EINVAL;
3481         }
3482
3483         vf_id = filter->dst_id;
3484
3485         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3486                 PMD_DRV_LOG(ERR, "Invalid argument.");
3487                 return -EINVAL;
3488         }
3489         vf = &pf->vfs[vf_id];
3490
3491         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3492                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3493                 return -EINVAL;
3494         }
3495
3496         if (add) {
3497                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3498                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3499                                 ETHER_ADDR_LEN);
3500                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3501                                  ETHER_ADDR_LEN);
3502
3503                 mac_filter.filter_type = filter->filter_type;
3504                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3505                 if (ret != I40E_SUCCESS) {
3506                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3507                         return -1;
3508                 }
3509                 ether_addr_copy(new_mac, &pf->dev_addr);
3510         } else {
3511                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3512                                 ETHER_ADDR_LEN);
3513                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3514                 if (ret != I40E_SUCCESS) {
3515                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3516                         return -1;
3517                 }
3518
3519                 /* Clear device address as it has been removed */
3520                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3521                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3522         }
3523
3524         return 0;
3525 }
3526
3527 /* MAC filter handle */
3528 static int
3529 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3530                 void *arg)
3531 {
3532         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3533         struct rte_eth_mac_filter *filter;
3534         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3535         int ret = I40E_NOT_SUPPORTED;
3536
3537         filter = (struct rte_eth_mac_filter *)(arg);
3538
3539         switch (filter_op) {
3540         case RTE_ETH_FILTER_NOP:
3541                 ret = I40E_SUCCESS;
3542                 break;
3543         case RTE_ETH_FILTER_ADD:
3544                 i40e_pf_disable_irq0(hw);
3545                 if (filter->is_vf)
3546                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3547                 i40e_pf_enable_irq0(hw);
3548                 break;
3549         case RTE_ETH_FILTER_DELETE:
3550                 i40e_pf_disable_irq0(hw);
3551                 if (filter->is_vf)
3552                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3553                 i40e_pf_enable_irq0(hw);
3554                 break;
3555         default:
3556                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3557                 ret = I40E_ERR_PARAM;
3558                 break;
3559         }
3560
3561         return ret;
3562 }
3563
3564 static int
3565 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3566 {
3567         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3568         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3569         int ret;
3570
3571         if (!lut)
3572                 return -EINVAL;
3573
3574         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3575                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3576                                           lut, lut_size);
3577                 if (ret) {
3578                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3579                         return ret;
3580                 }
3581         } else {
3582                 uint32_t *lut_dw = (uint32_t *)lut;
3583                 uint16_t i, lut_size_dw = lut_size / 4;
3584
3585                 for (i = 0; i < lut_size_dw; i++)
3586                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3587         }
3588
3589         return 0;
3590 }
3591
3592 static int
3593 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3594 {
3595         struct i40e_pf *pf;
3596         struct i40e_hw *hw;
3597         int ret;
3598
3599         if (!vsi || !lut)
3600                 return -EINVAL;
3601
3602         pf = I40E_VSI_TO_PF(vsi);
3603         hw = I40E_VSI_TO_HW(vsi);
3604
3605         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3606                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3607                                           lut, lut_size);
3608                 if (ret) {
3609                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3610                         return ret;
3611                 }
3612         } else {
3613                 uint32_t *lut_dw = (uint32_t *)lut;
3614                 uint16_t i, lut_size_dw = lut_size / 4;
3615
3616                 for (i = 0; i < lut_size_dw; i++)
3617                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3618                 I40E_WRITE_FLUSH(hw);
3619         }
3620
3621         return 0;
3622 }
3623
3624 static int
3625 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3626                          struct rte_eth_rss_reta_entry64 *reta_conf,
3627                          uint16_t reta_size)
3628 {
3629         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3630         uint16_t i, lut_size = pf->hash_lut_size;
3631         uint16_t idx, shift;
3632         uint8_t *lut;
3633         int ret;
3634
3635         if (reta_size != lut_size ||
3636                 reta_size > ETH_RSS_RETA_SIZE_512) {
3637                 PMD_DRV_LOG(ERR,
3638                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3639                         reta_size, lut_size);
3640                 return -EINVAL;
3641         }
3642
3643         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3644         if (!lut) {
3645                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3646                 return -ENOMEM;
3647         }
3648         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3649         if (ret)
3650                 goto out;
3651         for (i = 0; i < reta_size; i++) {
3652                 idx = i / RTE_RETA_GROUP_SIZE;
3653                 shift = i % RTE_RETA_GROUP_SIZE;
3654                 if (reta_conf[idx].mask & (1ULL << shift))
3655                         lut[i] = reta_conf[idx].reta[shift];
3656         }
3657         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3658
3659 out:
3660         rte_free(lut);
3661
3662         return ret;
3663 }
3664
3665 static int
3666 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3667                         struct rte_eth_rss_reta_entry64 *reta_conf,
3668                         uint16_t reta_size)
3669 {
3670         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3671         uint16_t i, lut_size = pf->hash_lut_size;
3672         uint16_t idx, shift;
3673         uint8_t *lut;
3674         int ret;
3675
3676         if (reta_size != lut_size ||
3677                 reta_size > ETH_RSS_RETA_SIZE_512) {
3678                 PMD_DRV_LOG(ERR,
3679                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3680                         reta_size, lut_size);
3681                 return -EINVAL;
3682         }
3683
3684         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3685         if (!lut) {
3686                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3687                 return -ENOMEM;
3688         }
3689
3690         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3691         if (ret)
3692                 goto out;
3693         for (i = 0; i < reta_size; i++) {
3694                 idx = i / RTE_RETA_GROUP_SIZE;
3695                 shift = i % RTE_RETA_GROUP_SIZE;
3696                 if (reta_conf[idx].mask & (1ULL << shift))
3697                         reta_conf[idx].reta[shift] = lut[i];
3698         }
3699
3700 out:
3701         rte_free(lut);
3702
3703         return ret;
3704 }
3705
3706 /**
3707  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3708  * @hw:   pointer to the HW structure
3709  * @mem:  pointer to mem struct to fill out
3710  * @size: size of memory requested
3711  * @alignment: what to align the allocation to
3712  **/
3713 enum i40e_status_code
3714 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3715                         struct i40e_dma_mem *mem,
3716                         u64 size,
3717                         u32 alignment)
3718 {
3719         const struct rte_memzone *mz = NULL;
3720         char z_name[RTE_MEMZONE_NAMESIZE];
3721
3722         if (!mem)
3723                 return I40E_ERR_PARAM;
3724
3725         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3726         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3727                                          alignment, RTE_PGSIZE_2M);
3728         if (!mz)
3729                 return I40E_ERR_NO_MEMORY;
3730
3731         mem->size = size;
3732         mem->va = mz->addr;
3733         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3734         mem->zone = (const void *)mz;
3735         PMD_DRV_LOG(DEBUG,
3736                 "memzone %s allocated with physical address: %"PRIu64,
3737                 mz->name, mem->pa);
3738
3739         return I40E_SUCCESS;
3740 }
3741
3742 /**
3743  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3744  * @hw:   pointer to the HW structure
3745  * @mem:  ptr to mem struct to free
3746  **/
3747 enum i40e_status_code
3748 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3749                     struct i40e_dma_mem *mem)
3750 {
3751         if (!mem)
3752                 return I40E_ERR_PARAM;
3753
3754         PMD_DRV_LOG(DEBUG,
3755                 "memzone %s to be freed with physical address: %"PRIu64,
3756                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3757         rte_memzone_free((const struct rte_memzone *)mem->zone);
3758         mem->zone = NULL;
3759         mem->va = NULL;
3760         mem->pa = (u64)0;
3761
3762         return I40E_SUCCESS;
3763 }
3764
3765 /**
3766  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3767  * @hw:   pointer to the HW structure
3768  * @mem:  pointer to mem struct to fill out
3769  * @size: size of memory requested
3770  **/
3771 enum i40e_status_code
3772 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3773                          struct i40e_virt_mem *mem,
3774                          u32 size)
3775 {
3776         if (!mem)
3777                 return I40E_ERR_PARAM;
3778
3779         mem->size = size;
3780         mem->va = rte_zmalloc("i40e", size, 0);
3781
3782         if (mem->va)
3783                 return I40E_SUCCESS;
3784         else
3785                 return I40E_ERR_NO_MEMORY;
3786 }
3787
3788 /**
3789  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3790  * @hw:   pointer to the HW structure
3791  * @mem:  pointer to mem struct to free
3792  **/
3793 enum i40e_status_code
3794 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3795                      struct i40e_virt_mem *mem)
3796 {
3797         if (!mem)
3798                 return I40E_ERR_PARAM;
3799
3800         rte_free(mem->va);
3801         mem->va = NULL;
3802
3803         return I40E_SUCCESS;
3804 }
3805
3806 void
3807 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3808 {
3809         rte_spinlock_init(&sp->spinlock);
3810 }
3811
3812 void
3813 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3814 {
3815         rte_spinlock_lock(&sp->spinlock);
3816 }
3817
3818 void
3819 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3820 {
3821         rte_spinlock_unlock(&sp->spinlock);
3822 }
3823
3824 void
3825 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3826 {
3827         return;
3828 }
3829
3830 /**
3831  * Get the hardware capabilities, which will be parsed
3832  * and saved into struct i40e_hw.
3833  */
3834 static int
3835 i40e_get_cap(struct i40e_hw *hw)
3836 {
3837         struct i40e_aqc_list_capabilities_element_resp *buf;
3838         uint16_t len, size = 0;
3839         int ret;
3840
3841         /* Calculate a huge enough buff for saving response data temporarily */
3842         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3843                                                 I40E_MAX_CAP_ELE_NUM;
3844         buf = rte_zmalloc("i40e", len, 0);
3845         if (!buf) {
3846                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3847                 return I40E_ERR_NO_MEMORY;
3848         }
3849
3850         /* Get, parse the capabilities and save it to hw */
3851         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3852                         i40e_aqc_opc_list_func_capabilities, NULL);
3853         if (ret != I40E_SUCCESS)
3854                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3855
3856         /* Free the temporary buffer after being used */
3857         rte_free(buf);
3858
3859         return ret;
3860 }
3861
3862 static int
3863 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3864 {
3865         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3866         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3867         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3868         uint16_t qp_count = 0, vsi_count = 0;
3869
3870         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3871                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3872                 return -EINVAL;
3873         }
3874         /* Add the parameter init for LFC */
3875         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3876         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3877         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3878
3879         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3880         pf->max_num_vsi = hw->func_caps.num_vsis;
3881         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3882         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3883         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3884
3885         /* FDir queue/VSI allocation */
3886         pf->fdir_qp_offset = 0;
3887         if (hw->func_caps.fd) {
3888                 pf->flags |= I40E_FLAG_FDIR;
3889                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3890         } else {
3891                 pf->fdir_nb_qps = 0;
3892         }
3893         qp_count += pf->fdir_nb_qps;
3894         vsi_count += 1;
3895
3896         /* LAN queue/VSI allocation */
3897         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3898         if (!hw->func_caps.rss) {
3899                 pf->lan_nb_qps = 1;
3900         } else {
3901                 pf->flags |= I40E_FLAG_RSS;
3902                 if (hw->mac.type == I40E_MAC_X722)
3903                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3904                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3905         }
3906         qp_count += pf->lan_nb_qps;
3907         vsi_count += 1;
3908
3909         /* VF queue/VSI allocation */
3910         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3911         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3912                 pf->flags |= I40E_FLAG_SRIOV;
3913                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3914                 pf->vf_num = pci_dev->max_vfs;
3915                 PMD_DRV_LOG(DEBUG,
3916                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3917                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3918         } else {
3919                 pf->vf_nb_qps = 0;
3920                 pf->vf_num = 0;
3921         }
3922         qp_count += pf->vf_nb_qps * pf->vf_num;
3923         vsi_count += pf->vf_num;
3924
3925         /* VMDq queue/VSI allocation */
3926         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3927         pf->vmdq_nb_qps = 0;
3928         pf->max_nb_vmdq_vsi = 0;
3929         if (hw->func_caps.vmdq) {
3930                 if (qp_count < hw->func_caps.num_tx_qp &&
3931                         vsi_count < hw->func_caps.num_vsis) {
3932                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3933                                 qp_count) / pf->vmdq_nb_qp_max;
3934
3935                         /* Limit the maximum number of VMDq vsi to the maximum
3936                          * ethdev can support
3937                          */
3938                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3939                                 hw->func_caps.num_vsis - vsi_count);
3940                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3941                                 ETH_64_POOLS);
3942                         if (pf->max_nb_vmdq_vsi) {
3943                                 pf->flags |= I40E_FLAG_VMDQ;
3944                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3945                                 PMD_DRV_LOG(DEBUG,
3946                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3947                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3948                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3949                         } else {
3950                                 PMD_DRV_LOG(INFO,
3951                                         "No enough queues left for VMDq");
3952                         }
3953                 } else {
3954                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3955                 }
3956         }
3957         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3958         vsi_count += pf->max_nb_vmdq_vsi;
3959
3960         if (hw->func_caps.dcb)
3961                 pf->flags |= I40E_FLAG_DCB;
3962
3963         if (qp_count > hw->func_caps.num_tx_qp) {
3964                 PMD_DRV_LOG(ERR,
3965                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3966                         qp_count, hw->func_caps.num_tx_qp);
3967                 return -EINVAL;
3968         }
3969         if (vsi_count > hw->func_caps.num_vsis) {
3970                 PMD_DRV_LOG(ERR,
3971                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3972                         vsi_count, hw->func_caps.num_vsis);
3973                 return -EINVAL;
3974         }
3975
3976         return 0;
3977 }
3978
3979 static int
3980 i40e_pf_get_switch_config(struct i40e_pf *pf)
3981 {
3982         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3983         struct i40e_aqc_get_switch_config_resp *switch_config;
3984         struct i40e_aqc_switch_config_element_resp *element;
3985         uint16_t start_seid = 0, num_reported;
3986         int ret;
3987
3988         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3989                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3990         if (!switch_config) {
3991                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3992                 return -ENOMEM;
3993         }
3994
3995         /* Get the switch configurations */
3996         ret = i40e_aq_get_switch_config(hw, switch_config,
3997                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3998         if (ret != I40E_SUCCESS) {
3999                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4000                 goto fail;
4001         }
4002         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4003         if (num_reported != 1) { /* The number should be 1 */
4004                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4005                 goto fail;
4006         }
4007
4008         /* Parse the switch configuration elements */
4009         element = &(switch_config->element[0]);
4010         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4011                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4012                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4013         } else
4014                 PMD_DRV_LOG(INFO, "Unknown element type");
4015
4016 fail:
4017         rte_free(switch_config);
4018
4019         return ret;
4020 }
4021
4022 static int
4023 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4024                         uint32_t num)
4025 {
4026         struct pool_entry *entry;
4027
4028         if (pool == NULL || num == 0)
4029                 return -EINVAL;
4030
4031         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4032         if (entry == NULL) {
4033                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4034                 return -ENOMEM;
4035         }
4036
4037         /* queue heap initialize */
4038         pool->num_free = num;
4039         pool->num_alloc = 0;
4040         pool->base = base;
4041         LIST_INIT(&pool->alloc_list);
4042         LIST_INIT(&pool->free_list);
4043
4044         /* Initialize element  */
4045         entry->base = 0;
4046         entry->len = num;
4047
4048         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4049         return 0;
4050 }
4051
4052 static void
4053 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4054 {
4055         struct pool_entry *entry, *next_entry;
4056
4057         if (pool == NULL)
4058                 return;
4059
4060         for (entry = LIST_FIRST(&pool->alloc_list);
4061                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4062                         entry = next_entry) {
4063                 LIST_REMOVE(entry, next);
4064                 rte_free(entry);
4065         }
4066
4067         for (entry = LIST_FIRST(&pool->free_list);
4068                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4069                         entry = next_entry) {
4070                 LIST_REMOVE(entry, next);
4071                 rte_free(entry);
4072         }
4073
4074         pool->num_free = 0;
4075         pool->num_alloc = 0;
4076         pool->base = 0;
4077         LIST_INIT(&pool->alloc_list);
4078         LIST_INIT(&pool->free_list);
4079 }
4080
4081 static int
4082 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4083                        uint32_t base)
4084 {
4085         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4086         uint32_t pool_offset;
4087         int insert;
4088
4089         if (pool == NULL) {
4090                 PMD_DRV_LOG(ERR, "Invalid parameter");
4091                 return -EINVAL;
4092         }
4093
4094         pool_offset = base - pool->base;
4095         /* Lookup in alloc list */
4096         LIST_FOREACH(entry, &pool->alloc_list, next) {
4097                 if (entry->base == pool_offset) {
4098                         valid_entry = entry;
4099                         LIST_REMOVE(entry, next);
4100                         break;
4101                 }
4102         }
4103
4104         /* Not find, return */
4105         if (valid_entry == NULL) {
4106                 PMD_DRV_LOG(ERR, "Failed to find entry");
4107                 return -EINVAL;
4108         }
4109
4110         /**
4111          * Found it, move it to free list  and try to merge.
4112          * In order to make merge easier, always sort it by qbase.
4113          * Find adjacent prev and last entries.
4114          */
4115         prev = next = NULL;
4116         LIST_FOREACH(entry, &pool->free_list, next) {
4117                 if (entry->base > valid_entry->base) {
4118                         next = entry;
4119                         break;
4120                 }
4121                 prev = entry;
4122         }
4123
4124         insert = 0;
4125         /* Try to merge with next one*/
4126         if (next != NULL) {
4127                 /* Merge with next one */
4128                 if (valid_entry->base + valid_entry->len == next->base) {
4129                         next->base = valid_entry->base;
4130                         next->len += valid_entry->len;
4131                         rte_free(valid_entry);
4132                         valid_entry = next;
4133                         insert = 1;
4134                 }
4135         }
4136
4137         if (prev != NULL) {
4138                 /* Merge with previous one */
4139                 if (prev->base + prev->len == valid_entry->base) {
4140                         prev->len += valid_entry->len;
4141                         /* If it merge with next one, remove next node */
4142                         if (insert == 1) {
4143                                 LIST_REMOVE(valid_entry, next);
4144                                 rte_free(valid_entry);
4145                         } else {
4146                                 rte_free(valid_entry);
4147                                 insert = 1;
4148                         }
4149                 }
4150         }
4151
4152         /* Not find any entry to merge, insert */
4153         if (insert == 0) {
4154                 if (prev != NULL)
4155                         LIST_INSERT_AFTER(prev, valid_entry, next);
4156                 else if (next != NULL)
4157                         LIST_INSERT_BEFORE(next, valid_entry, next);
4158                 else /* It's empty list, insert to head */
4159                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4160         }
4161
4162         pool->num_free += valid_entry->len;
4163         pool->num_alloc -= valid_entry->len;
4164
4165         return 0;
4166 }
4167
4168 static int
4169 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4170                        uint16_t num)
4171 {
4172         struct pool_entry *entry, *valid_entry;
4173
4174         if (pool == NULL || num == 0) {
4175                 PMD_DRV_LOG(ERR, "Invalid parameter");
4176                 return -EINVAL;
4177         }
4178
4179         if (pool->num_free < num) {
4180                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4181                             num, pool->num_free);
4182                 return -ENOMEM;
4183         }
4184
4185         valid_entry = NULL;
4186         /* Lookup  in free list and find most fit one */
4187         LIST_FOREACH(entry, &pool->free_list, next) {
4188                 if (entry->len >= num) {
4189                         /* Find best one */
4190                         if (entry->len == num) {
4191                                 valid_entry = entry;
4192                                 break;
4193                         }
4194                         if (valid_entry == NULL || valid_entry->len > entry->len)
4195                                 valid_entry = entry;
4196                 }
4197         }
4198
4199         /* Not find one to satisfy the request, return */
4200         if (valid_entry == NULL) {
4201                 PMD_DRV_LOG(ERR, "No valid entry found");
4202                 return -ENOMEM;
4203         }
4204         /**
4205          * The entry have equal queue number as requested,
4206          * remove it from alloc_list.
4207          */
4208         if (valid_entry->len == num) {
4209                 LIST_REMOVE(valid_entry, next);
4210         } else {
4211                 /**
4212                  * The entry have more numbers than requested,
4213                  * create a new entry for alloc_list and minus its
4214                  * queue base and number in free_list.
4215                  */
4216                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4217                 if (entry == NULL) {
4218                         PMD_DRV_LOG(ERR,
4219                                 "Failed to allocate memory for resource pool");
4220                         return -ENOMEM;
4221                 }
4222                 entry->base = valid_entry->base;
4223                 entry->len = num;
4224                 valid_entry->base += num;
4225                 valid_entry->len -= num;
4226                 valid_entry = entry;
4227         }
4228
4229         /* Insert it into alloc list, not sorted */
4230         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4231
4232         pool->num_free -= valid_entry->len;
4233         pool->num_alloc += valid_entry->len;
4234
4235         return valid_entry->base + pool->base;
4236 }
4237
4238 /**
4239  * bitmap_is_subset - Check whether src2 is subset of src1
4240  **/
4241 static inline int
4242 bitmap_is_subset(uint8_t src1, uint8_t src2)
4243 {
4244         return !((src1 ^ src2) & src2);
4245 }
4246
4247 static enum i40e_status_code
4248 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4249 {
4250         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4251
4252         /* If DCB is not supported, only default TC is supported */
4253         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4254                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4255                 return I40E_NOT_SUPPORTED;
4256         }
4257
4258         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4259                 PMD_DRV_LOG(ERR,
4260                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4261                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4262                 return I40E_NOT_SUPPORTED;
4263         }
4264         return I40E_SUCCESS;
4265 }
4266
4267 int
4268 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4269                                 struct i40e_vsi_vlan_pvid_info *info)
4270 {
4271         struct i40e_hw *hw;
4272         struct i40e_vsi_context ctxt;
4273         uint8_t vlan_flags = 0;
4274         int ret;
4275
4276         if (vsi == NULL || info == NULL) {
4277                 PMD_DRV_LOG(ERR, "invalid parameters");
4278                 return I40E_ERR_PARAM;
4279         }
4280
4281         if (info->on) {
4282                 vsi->info.pvid = info->config.pvid;
4283                 /**
4284                  * If insert pvid is enabled, only tagged pkts are
4285                  * allowed to be sent out.
4286                  */
4287                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4288                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4289         } else {
4290                 vsi->info.pvid = 0;
4291                 if (info->config.reject.tagged == 0)
4292                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4293
4294                 if (info->config.reject.untagged == 0)
4295                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4296         }
4297         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4298                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4299         vsi->info.port_vlan_flags |= vlan_flags;
4300         vsi->info.valid_sections =
4301                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4302         memset(&ctxt, 0, sizeof(ctxt));
4303         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4304         ctxt.seid = vsi->seid;
4305
4306         hw = I40E_VSI_TO_HW(vsi);
4307         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4308         if (ret != I40E_SUCCESS)
4309                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4310
4311         return ret;
4312 }
4313
4314 static int
4315 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4316 {
4317         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4318         int i, ret;
4319         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4320
4321         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4322         if (ret != I40E_SUCCESS)
4323                 return ret;
4324
4325         if (!vsi->seid) {
4326                 PMD_DRV_LOG(ERR, "seid not valid");
4327                 return -EINVAL;
4328         }
4329
4330         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4331         tc_bw_data.tc_valid_bits = enabled_tcmap;
4332         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4333                 tc_bw_data.tc_bw_credits[i] =
4334                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4335
4336         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4337         if (ret != I40E_SUCCESS) {
4338                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4339                 return ret;
4340         }
4341
4342         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4343                                         sizeof(vsi->info.qs_handle));
4344         return I40E_SUCCESS;
4345 }
4346
4347 static enum i40e_status_code
4348 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4349                                  struct i40e_aqc_vsi_properties_data *info,
4350                                  uint8_t enabled_tcmap)
4351 {
4352         enum i40e_status_code ret;
4353         int i, total_tc = 0;
4354         uint16_t qpnum_per_tc, bsf, qp_idx;
4355
4356         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4357         if (ret != I40E_SUCCESS)
4358                 return ret;
4359
4360         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4361                 if (enabled_tcmap & (1 << i))
4362                         total_tc++;
4363         if (total_tc == 0)
4364                 total_tc = 1;
4365         vsi->enabled_tc = enabled_tcmap;
4366
4367         /* Number of queues per enabled TC */
4368         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4369         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4370         bsf = rte_bsf32(qpnum_per_tc);
4371
4372         /* Adjust the queue number to actual queues that can be applied */
4373         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4374                 vsi->nb_qps = qpnum_per_tc * total_tc;
4375
4376         /**
4377          * Configure TC and queue mapping parameters, for enabled TC,
4378          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4379          * default queue will serve it.
4380          */
4381         qp_idx = 0;
4382         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4383                 if (vsi->enabled_tc & (1 << i)) {
4384                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4385                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4386                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4387                         qp_idx += qpnum_per_tc;
4388                 } else
4389                         info->tc_mapping[i] = 0;
4390         }
4391
4392         /* Associate queue number with VSI */
4393         if (vsi->type == I40E_VSI_SRIOV) {
4394                 info->mapping_flags |=
4395                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4396                 for (i = 0; i < vsi->nb_qps; i++)
4397                         info->queue_mapping[i] =
4398                                 rte_cpu_to_le_16(vsi->base_queue + i);
4399         } else {
4400                 info->mapping_flags |=
4401                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4402                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4403         }
4404         info->valid_sections |=
4405                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4406
4407         return I40E_SUCCESS;
4408 }
4409
4410 static int
4411 i40e_veb_release(struct i40e_veb *veb)
4412 {
4413         struct i40e_vsi *vsi;
4414         struct i40e_hw *hw;
4415
4416         if (veb == NULL)
4417                 return -EINVAL;
4418
4419         if (!TAILQ_EMPTY(&veb->head)) {
4420                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4421                 return -EACCES;
4422         }
4423         /* associate_vsi field is NULL for floating VEB */
4424         if (veb->associate_vsi != NULL) {
4425                 vsi = veb->associate_vsi;
4426                 hw = I40E_VSI_TO_HW(vsi);
4427
4428                 vsi->uplink_seid = veb->uplink_seid;
4429                 vsi->veb = NULL;
4430         } else {
4431                 veb->associate_pf->main_vsi->floating_veb = NULL;
4432                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4433         }
4434
4435         i40e_aq_delete_element(hw, veb->seid, NULL);
4436         rte_free(veb);
4437         return I40E_SUCCESS;
4438 }
4439
4440 /* Setup a veb */
4441 static struct i40e_veb *
4442 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4443 {
4444         struct i40e_veb *veb;
4445         int ret;
4446         struct i40e_hw *hw;
4447
4448         if (pf == NULL) {
4449                 PMD_DRV_LOG(ERR,
4450                             "veb setup failed, associated PF shouldn't null");
4451                 return NULL;
4452         }
4453         hw = I40E_PF_TO_HW(pf);
4454
4455         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4456         if (!veb) {
4457                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4458                 goto fail;
4459         }
4460
4461         veb->associate_vsi = vsi;
4462         veb->associate_pf = pf;
4463         TAILQ_INIT(&veb->head);
4464         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4465
4466         /* create floating veb if vsi is NULL */
4467         if (vsi != NULL) {
4468                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4469                                       I40E_DEFAULT_TCMAP, false,
4470                                       &veb->seid, false, NULL);
4471         } else {
4472                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4473                                       true, &veb->seid, false, NULL);
4474         }
4475
4476         if (ret != I40E_SUCCESS) {
4477                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4478                             hw->aq.asq_last_status);
4479                 goto fail;
4480         }
4481         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4482
4483         /* get statistics index */
4484         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4485                                 &veb->stats_idx, NULL, NULL, NULL);
4486         if (ret != I40E_SUCCESS) {
4487                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4488                             hw->aq.asq_last_status);
4489                 goto fail;
4490         }
4491         /* Get VEB bandwidth, to be implemented */
4492         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4493         if (vsi)
4494                 vsi->uplink_seid = veb->seid;
4495
4496         return veb;
4497 fail:
4498         rte_free(veb);
4499         return NULL;
4500 }
4501
4502 int
4503 i40e_vsi_release(struct i40e_vsi *vsi)
4504 {
4505         struct i40e_pf *pf;
4506         struct i40e_hw *hw;
4507         struct i40e_vsi_list *vsi_list;
4508         void *temp;
4509         int ret;
4510         struct i40e_mac_filter *f;
4511         uint16_t user_param;
4512
4513         if (!vsi)
4514                 return I40E_SUCCESS;
4515
4516         if (!vsi->adapter)
4517                 return -EFAULT;
4518
4519         user_param = vsi->user_param;
4520
4521         pf = I40E_VSI_TO_PF(vsi);
4522         hw = I40E_VSI_TO_HW(vsi);
4523
4524         /* VSI has child to attach, release child first */
4525         if (vsi->veb) {
4526                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4527                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4528                                 return -1;
4529                 }
4530                 i40e_veb_release(vsi->veb);
4531         }
4532
4533         if (vsi->floating_veb) {
4534                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4535                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4536                                 return -1;
4537                 }
4538         }
4539
4540         /* Remove all macvlan filters of the VSI */
4541         i40e_vsi_remove_all_macvlan_filter(vsi);
4542         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4543                 rte_free(f);
4544
4545         if (vsi->type != I40E_VSI_MAIN &&
4546             ((vsi->type != I40E_VSI_SRIOV) ||
4547             !pf->floating_veb_list[user_param])) {
4548                 /* Remove vsi from parent's sibling list */
4549                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4550                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4551                         return I40E_ERR_PARAM;
4552                 }
4553                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4554                                 &vsi->sib_vsi_list, list);
4555
4556                 /* Remove all switch element of the VSI */
4557                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4558                 if (ret != I40E_SUCCESS)
4559                         PMD_DRV_LOG(ERR, "Failed to delete element");
4560         }
4561
4562         if ((vsi->type == I40E_VSI_SRIOV) &&
4563             pf->floating_veb_list[user_param]) {
4564                 /* Remove vsi from parent's sibling list */
4565                 if (vsi->parent_vsi == NULL ||
4566                     vsi->parent_vsi->floating_veb == NULL) {
4567                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4568                         return I40E_ERR_PARAM;
4569                 }
4570                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4571                              &vsi->sib_vsi_list, list);
4572
4573                 /* Remove all switch element of the VSI */
4574                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4575                 if (ret != I40E_SUCCESS)
4576                         PMD_DRV_LOG(ERR, "Failed to delete element");
4577         }
4578
4579         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4580
4581         if (vsi->type != I40E_VSI_SRIOV)
4582                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4583         rte_free(vsi);
4584
4585         return I40E_SUCCESS;
4586 }
4587
4588 static int
4589 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4590 {
4591         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4592         struct i40e_aqc_remove_macvlan_element_data def_filter;
4593         struct i40e_mac_filter_info filter;
4594         int ret;
4595
4596         if (vsi->type != I40E_VSI_MAIN)
4597                 return I40E_ERR_CONFIG;
4598         memset(&def_filter, 0, sizeof(def_filter));
4599         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4600                                         ETH_ADDR_LEN);
4601         def_filter.vlan_tag = 0;
4602         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4603                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4604         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4605         if (ret != I40E_SUCCESS) {
4606                 struct i40e_mac_filter *f;
4607                 struct ether_addr *mac;
4608
4609                 PMD_DRV_LOG(DEBUG,
4610                             "Cannot remove the default macvlan filter");
4611                 /* It needs to add the permanent mac into mac list */
4612                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4613                 if (f == NULL) {
4614                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4615                         return I40E_ERR_NO_MEMORY;
4616                 }
4617                 mac = &f->mac_info.mac_addr;
4618                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4619                                 ETH_ADDR_LEN);
4620                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4621                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4622                 vsi->mac_num++;
4623
4624                 return ret;
4625         }
4626         (void)rte_memcpy(&filter.mac_addr,
4627                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4628         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4629         return i40e_vsi_add_mac(vsi, &filter);
4630 }
4631
4632 /*
4633  * i40e_vsi_get_bw_config - Query VSI BW Information
4634  * @vsi: the VSI to be queried
4635  *
4636  * Returns 0 on success, negative value on failure
4637  */
4638 static enum i40e_status_code
4639 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4640 {
4641         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4642         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4643         struct i40e_hw *hw = &vsi->adapter->hw;
4644         i40e_status ret;
4645         int i;
4646         uint32_t bw_max;
4647
4648         memset(&bw_config, 0, sizeof(bw_config));
4649         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4650         if (ret != I40E_SUCCESS) {
4651                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4652                             hw->aq.asq_last_status);
4653                 return ret;
4654         }
4655
4656         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4657         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4658                                         &ets_sla_config, NULL);
4659         if (ret != I40E_SUCCESS) {
4660                 PMD_DRV_LOG(ERR,
4661                         "VSI failed to get TC bandwdith configuration %u",
4662                         hw->aq.asq_last_status);
4663                 return ret;
4664         }
4665
4666         /* store and print out BW info */
4667         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4668         vsi->bw_info.bw_max = bw_config.max_bw;
4669         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4670         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4671         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4672                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4673                      I40E_16_BIT_WIDTH);
4674         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4675                 vsi->bw_info.bw_ets_share_credits[i] =
4676                                 ets_sla_config.share_credits[i];
4677                 vsi->bw_info.bw_ets_credits[i] =
4678                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4679                 /* 4 bits per TC, 4th bit is reserved */
4680                 vsi->bw_info.bw_ets_max[i] =
4681                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4682                                   RTE_LEN2MASK(3, uint8_t));
4683                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4684                             vsi->bw_info.bw_ets_share_credits[i]);
4685                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4686                             vsi->bw_info.bw_ets_credits[i]);
4687                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4688                             vsi->bw_info.bw_ets_max[i]);
4689         }
4690
4691         return I40E_SUCCESS;
4692 }
4693
4694 /* i40e_enable_pf_lb
4695  * @pf: pointer to the pf structure
4696  *
4697  * allow loopback on pf
4698  */
4699 static inline void
4700 i40e_enable_pf_lb(struct i40e_pf *pf)
4701 {
4702         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4703         struct i40e_vsi_context ctxt;
4704         int ret;
4705
4706         /* Use the FW API if FW >= v5.0 */
4707         if (hw->aq.fw_maj_ver < 5) {
4708                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4709                 return;
4710         }
4711
4712         memset(&ctxt, 0, sizeof(ctxt));
4713         ctxt.seid = pf->main_vsi_seid;
4714         ctxt.pf_num = hw->pf_id;
4715         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4716         if (ret) {
4717                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4718                             ret, hw->aq.asq_last_status);
4719                 return;
4720         }
4721         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4722         ctxt.info.valid_sections =
4723                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4724         ctxt.info.switch_id |=
4725                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4726
4727         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4728         if (ret)
4729                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4730                             hw->aq.asq_last_status);
4731 }
4732
4733 /* Setup a VSI */
4734 struct i40e_vsi *
4735 i40e_vsi_setup(struct i40e_pf *pf,
4736                enum i40e_vsi_type type,
4737                struct i40e_vsi *uplink_vsi,
4738                uint16_t user_param)
4739 {
4740         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4741         struct i40e_vsi *vsi;
4742         struct i40e_mac_filter_info filter;
4743         int ret;
4744         struct i40e_vsi_context ctxt;
4745         struct ether_addr broadcast =
4746                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4747
4748         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4749             uplink_vsi == NULL) {
4750                 PMD_DRV_LOG(ERR,
4751                         "VSI setup failed, VSI link shouldn't be NULL");
4752                 return NULL;
4753         }
4754
4755         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4756                 PMD_DRV_LOG(ERR,
4757                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4758                 return NULL;
4759         }
4760
4761         /* two situations
4762          * 1.type is not MAIN and uplink vsi is not NULL
4763          * If uplink vsi didn't setup VEB, create one first under veb field
4764          * 2.type is SRIOV and the uplink is NULL
4765          * If floating VEB is NULL, create one veb under floating veb field
4766          */
4767
4768         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4769             uplink_vsi->veb == NULL) {
4770                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4771
4772                 if (uplink_vsi->veb == NULL) {
4773                         PMD_DRV_LOG(ERR, "VEB setup failed");
4774                         return NULL;
4775                 }
4776                 /* set ALLOWLOOPBACk on pf, when veb is created */
4777                 i40e_enable_pf_lb(pf);
4778         }
4779
4780         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4781             pf->main_vsi->floating_veb == NULL) {
4782                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4783
4784                 if (pf->main_vsi->floating_veb == NULL) {
4785                         PMD_DRV_LOG(ERR, "VEB setup failed");
4786                         return NULL;
4787                 }
4788         }
4789
4790         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4791         if (!vsi) {
4792                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4793                 return NULL;
4794         }
4795         TAILQ_INIT(&vsi->mac_list);
4796         vsi->type = type;
4797         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4798         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4799         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4800         vsi->user_param = user_param;
4801         vsi->vlan_anti_spoof_on = 0;
4802         vsi->vlan_filter_on = 0;
4803         /* Allocate queues */
4804         switch (vsi->type) {
4805         case I40E_VSI_MAIN  :
4806                 vsi->nb_qps = pf->lan_nb_qps;
4807                 break;
4808         case I40E_VSI_SRIOV :
4809                 vsi->nb_qps = pf->vf_nb_qps;
4810                 break;
4811         case I40E_VSI_VMDQ2:
4812                 vsi->nb_qps = pf->vmdq_nb_qps;
4813                 break;
4814         case I40E_VSI_FDIR:
4815                 vsi->nb_qps = pf->fdir_nb_qps;
4816                 break;
4817         default:
4818                 goto fail_mem;
4819         }
4820         /*
4821          * The filter status descriptor is reported in rx queue 0,
4822          * while the tx queue for fdir filter programming has no
4823          * such constraints, can be non-zero queues.
4824          * To simplify it, choose FDIR vsi use queue 0 pair.
4825          * To make sure it will use queue 0 pair, queue allocation
4826          * need be done before this function is called
4827          */
4828         if (type != I40E_VSI_FDIR) {
4829                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4830                         if (ret < 0) {
4831                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4832                                                 vsi->seid, ret);
4833                                 goto fail_mem;
4834                         }
4835                         vsi->base_queue = ret;
4836         } else
4837                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4838
4839         /* VF has MSIX interrupt in VF range, don't allocate here */
4840         if (type == I40E_VSI_MAIN) {
4841                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4842                                           RTE_MIN(vsi->nb_qps,
4843                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4844                 if (ret < 0) {
4845                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4846                                     vsi->seid, ret);
4847                         goto fail_queue_alloc;
4848                 }
4849                 vsi->msix_intr = ret;
4850                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4851         } else if (type != I40E_VSI_SRIOV) {
4852                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4853                 if (ret < 0) {
4854                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4855                         goto fail_queue_alloc;
4856                 }
4857                 vsi->msix_intr = ret;
4858                 vsi->nb_msix = 1;
4859         } else {
4860                 vsi->msix_intr = 0;
4861                 vsi->nb_msix = 0;
4862         }
4863
4864         /* Add VSI */
4865         if (type == I40E_VSI_MAIN) {
4866                 /* For main VSI, no need to add since it's default one */
4867                 vsi->uplink_seid = pf->mac_seid;
4868                 vsi->seid = pf->main_vsi_seid;
4869                 /* Bind queues with specific MSIX interrupt */
4870                 /**
4871                  * Needs 2 interrupt at least, one for misc cause which will
4872                  * enabled from OS side, Another for queues binding the
4873                  * interrupt from device side only.
4874                  */
4875
4876                 /* Get default VSI parameters from hardware */
4877                 memset(&ctxt, 0, sizeof(ctxt));
4878                 ctxt.seid = vsi->seid;
4879                 ctxt.pf_num = hw->pf_id;
4880                 ctxt.uplink_seid = vsi->uplink_seid;
4881                 ctxt.vf_num = 0;
4882                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4883                 if (ret != I40E_SUCCESS) {
4884                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4885                         goto fail_msix_alloc;
4886                 }
4887                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4888                         sizeof(struct i40e_aqc_vsi_properties_data));
4889                 vsi->vsi_id = ctxt.vsi_number;
4890                 vsi->info.valid_sections = 0;
4891
4892                 /* Configure tc, enabled TC0 only */
4893                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4894                         I40E_SUCCESS) {
4895                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4896                         goto fail_msix_alloc;
4897                 }
4898
4899                 /* TC, queue mapping */
4900                 memset(&ctxt, 0, sizeof(ctxt));
4901                 vsi->info.valid_sections |=
4902                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4903                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4904                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4905                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4906                         sizeof(struct i40e_aqc_vsi_properties_data));
4907                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4908                                                 I40E_DEFAULT_TCMAP);
4909                 if (ret != I40E_SUCCESS) {
4910                         PMD_DRV_LOG(ERR,
4911                                 "Failed to configure TC queue mapping");
4912                         goto fail_msix_alloc;
4913                 }
4914                 ctxt.seid = vsi->seid;
4915                 ctxt.pf_num = hw->pf_id;
4916                 ctxt.uplink_seid = vsi->uplink_seid;
4917                 ctxt.vf_num = 0;
4918
4919                 /* Update VSI parameters */
4920                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4921                 if (ret != I40E_SUCCESS) {
4922                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4923                         goto fail_msix_alloc;
4924                 }
4925
4926                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4927                                                 sizeof(vsi->info.tc_mapping));
4928                 (void)rte_memcpy(&vsi->info.queue_mapping,
4929                                 &ctxt.info.queue_mapping,
4930                         sizeof(vsi->info.queue_mapping));
4931                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4932                 vsi->info.valid_sections = 0;
4933
4934                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4935                                 ETH_ADDR_LEN);
4936
4937                 /**
4938                  * Updating default filter settings are necessary to prevent
4939                  * reception of tagged packets.
4940                  * Some old firmware configurations load a default macvlan
4941                  * filter which accepts both tagged and untagged packets.
4942                  * The updating is to use a normal filter instead if needed.
4943                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4944                  * The firmware with correct configurations load the default
4945                  * macvlan filter which is expected and cannot be removed.
4946                  */
4947                 i40e_update_default_filter_setting(vsi);
4948                 i40e_config_qinq(hw, vsi);
4949         } else if (type == I40E_VSI_SRIOV) {
4950                 memset(&ctxt, 0, sizeof(ctxt));
4951                 /**
4952                  * For other VSI, the uplink_seid equals to uplink VSI's
4953                  * uplink_seid since they share same VEB
4954                  */
4955                 if (uplink_vsi == NULL)
4956                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4957                 else
4958                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4959                 ctxt.pf_num = hw->pf_id;
4960                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4961                 ctxt.uplink_seid = vsi->uplink_seid;
4962                 ctxt.connection_type = 0x1;
4963                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4964
4965                 /* Use the VEB configuration if FW >= v5.0 */
4966                 if (hw->aq.fw_maj_ver >= 5) {
4967                         /* Configure switch ID */
4968                         ctxt.info.valid_sections |=
4969                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4970                         ctxt.info.switch_id =
4971                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4972                 }
4973
4974                 /* Configure port/vlan */
4975                 ctxt.info.valid_sections |=
4976                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4977                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4978                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4979                                                 hw->func_caps.enabled_tcmap);
4980                 if (ret != I40E_SUCCESS) {
4981                         PMD_DRV_LOG(ERR,
4982                                 "Failed to configure TC queue mapping");
4983                         goto fail_msix_alloc;
4984                 }
4985
4986                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4987                 ctxt.info.valid_sections |=
4988                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4989                 /**
4990                  * Since VSI is not created yet, only configure parameter,
4991                  * will add vsi below.
4992                  */
4993
4994                 i40e_config_qinq(hw, vsi);
4995         } else if (type == I40E_VSI_VMDQ2) {
4996                 memset(&ctxt, 0, sizeof(ctxt));
4997                 /*
4998                  * For other VSI, the uplink_seid equals to uplink VSI's
4999                  * uplink_seid since they share same VEB
5000                  */
5001                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5002                 ctxt.pf_num = hw->pf_id;
5003                 ctxt.vf_num = 0;
5004                 ctxt.uplink_seid = vsi->uplink_seid;
5005                 ctxt.connection_type = 0x1;
5006                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5007
5008                 ctxt.info.valid_sections |=
5009                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5010                 /* user_param carries flag to enable loop back */
5011                 if (user_param) {
5012                         ctxt.info.switch_id =
5013                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5014                         ctxt.info.switch_id |=
5015                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5016                 }
5017
5018                 /* Configure port/vlan */
5019                 ctxt.info.valid_sections |=
5020                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5021                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5022                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5023                                                 I40E_DEFAULT_TCMAP);
5024                 if (ret != I40E_SUCCESS) {
5025                         PMD_DRV_LOG(ERR,
5026                                 "Failed to configure TC queue mapping");
5027                         goto fail_msix_alloc;
5028                 }
5029                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5030                 ctxt.info.valid_sections |=
5031                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5032         } else if (type == I40E_VSI_FDIR) {
5033                 memset(&ctxt, 0, sizeof(ctxt));
5034                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5035                 ctxt.pf_num = hw->pf_id;
5036                 ctxt.vf_num = 0;
5037                 ctxt.uplink_seid = vsi->uplink_seid;
5038                 ctxt.connection_type = 0x1;     /* regular data port */
5039                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5040                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5041                                                 I40E_DEFAULT_TCMAP);
5042                 if (ret != I40E_SUCCESS) {
5043                         PMD_DRV_LOG(ERR,
5044                                 "Failed to configure TC queue mapping.");
5045                         goto fail_msix_alloc;
5046                 }
5047                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5048                 ctxt.info.valid_sections |=
5049                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5050         } else {
5051                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5052                 goto fail_msix_alloc;
5053         }
5054
5055         if (vsi->type != I40E_VSI_MAIN) {
5056                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5057                 if (ret != I40E_SUCCESS) {
5058                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5059                                     hw->aq.asq_last_status);
5060                         goto fail_msix_alloc;
5061                 }
5062                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5063                 vsi->info.valid_sections = 0;
5064                 vsi->seid = ctxt.seid;
5065                 vsi->vsi_id = ctxt.vsi_number;
5066                 vsi->sib_vsi_list.vsi = vsi;
5067                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5068                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5069                                           &vsi->sib_vsi_list, list);
5070                 } else {
5071                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5072                                           &vsi->sib_vsi_list, list);
5073                 }
5074         }
5075
5076         /* MAC/VLAN configuration */
5077         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5078         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5079
5080         ret = i40e_vsi_add_mac(vsi, &filter);
5081         if (ret != I40E_SUCCESS) {
5082                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5083                 goto fail_msix_alloc;
5084         }
5085
5086         /* Get VSI BW information */
5087         i40e_vsi_get_bw_config(vsi);
5088         return vsi;
5089 fail_msix_alloc:
5090         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5091 fail_queue_alloc:
5092         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5093 fail_mem:
5094         rte_free(vsi);
5095         return NULL;
5096 }
5097
5098 /* Configure vlan filter on or off */
5099 int
5100 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5101 {
5102         int i, num;
5103         struct i40e_mac_filter *f;
5104         void *temp;
5105         struct i40e_mac_filter_info *mac_filter;
5106         enum rte_mac_filter_type desired_filter;
5107         int ret = I40E_SUCCESS;
5108
5109         if (on) {
5110                 /* Filter to match MAC and VLAN */
5111                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5112         } else {
5113                 /* Filter to match only MAC */
5114                 desired_filter = RTE_MAC_PERFECT_MATCH;
5115         }
5116
5117         num = vsi->mac_num;
5118
5119         mac_filter = rte_zmalloc("mac_filter_info_data",
5120                                  num * sizeof(*mac_filter), 0);
5121         if (mac_filter == NULL) {
5122                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5123                 return I40E_ERR_NO_MEMORY;
5124         }
5125
5126         i = 0;
5127
5128         /* Remove all existing mac */
5129         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5130                 mac_filter[i] = f->mac_info;
5131                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5132                 if (ret) {
5133                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5134                                     on ? "enable" : "disable");
5135                         goto DONE;
5136                 }
5137                 i++;
5138         }
5139
5140         /* Override with new filter */
5141         for (i = 0; i < num; i++) {
5142                 mac_filter[i].filter_type = desired_filter;
5143                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5144                 if (ret) {
5145                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5146                                     on ? "enable" : "disable");
5147                         goto DONE;
5148                 }
5149         }
5150
5151 DONE:
5152         rte_free(mac_filter);
5153         return ret;
5154 }
5155
5156 /* Configure vlan stripping on or off */
5157 int
5158 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5159 {
5160         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5161         struct i40e_vsi_context ctxt;
5162         uint8_t vlan_flags;
5163         int ret = I40E_SUCCESS;
5164
5165         /* Check if it has been already on or off */
5166         if (vsi->info.valid_sections &
5167                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5168                 if (on) {
5169                         if ((vsi->info.port_vlan_flags &
5170                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5171                                 return 0; /* already on */
5172                 } else {
5173                         if ((vsi->info.port_vlan_flags &
5174                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5175                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5176                                 return 0; /* already off */
5177                 }
5178         }
5179
5180         if (on)
5181                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5182         else
5183                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5184         vsi->info.valid_sections =
5185                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5186         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5187         vsi->info.port_vlan_flags |= vlan_flags;
5188         ctxt.seid = vsi->seid;
5189         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5190         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5191         if (ret)
5192                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5193                             on ? "enable" : "disable");
5194
5195         return ret;
5196 }
5197
5198 static int
5199 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5200 {
5201         struct rte_eth_dev_data *data = dev->data;
5202         int ret;
5203         int mask = 0;
5204
5205         /* Apply vlan offload setting */
5206         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5207         i40e_vlan_offload_set(dev, mask);
5208
5209         /* Apply double-vlan setting, not implemented yet */
5210
5211         /* Apply pvid setting */
5212         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5213                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5214         if (ret)
5215                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5216
5217         return ret;
5218 }
5219
5220 static int
5221 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5222 {
5223         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5224
5225         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5226 }
5227
5228 static int
5229 i40e_update_flow_control(struct i40e_hw *hw)
5230 {
5231 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5232         struct i40e_link_status link_status;
5233         uint32_t rxfc = 0, txfc = 0, reg;
5234         uint8_t an_info;
5235         int ret;
5236
5237         memset(&link_status, 0, sizeof(link_status));
5238         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5239         if (ret != I40E_SUCCESS) {
5240                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5241                 goto write_reg; /* Disable flow control */
5242         }
5243
5244         an_info = hw->phy.link_info.an_info;
5245         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5246                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5247                 ret = I40E_ERR_NOT_READY;
5248                 goto write_reg; /* Disable flow control */
5249         }
5250         /**
5251          * If link auto negotiation is enabled, flow control needs to
5252          * be configured according to it
5253          */
5254         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5255         case I40E_LINK_PAUSE_RXTX:
5256                 rxfc = 1;
5257                 txfc = 1;
5258                 hw->fc.current_mode = I40E_FC_FULL;
5259                 break;
5260         case I40E_AQ_LINK_PAUSE_RX:
5261                 rxfc = 1;
5262                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5263                 break;
5264         case I40E_AQ_LINK_PAUSE_TX:
5265                 txfc = 1;
5266                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5267                 break;
5268         default:
5269                 hw->fc.current_mode = I40E_FC_NONE;
5270                 break;
5271         }
5272
5273 write_reg:
5274         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5275                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5276         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5277         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5278         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5279         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5280
5281         return ret;
5282 }
5283
5284 /* PF setup */
5285 static int
5286 i40e_pf_setup(struct i40e_pf *pf)
5287 {
5288         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5289         struct i40e_filter_control_settings settings;
5290         struct i40e_vsi *vsi;
5291         int ret;
5292
5293         /* Clear all stats counters */
5294         pf->offset_loaded = FALSE;
5295         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5296         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5297         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5298         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5299
5300         ret = i40e_pf_get_switch_config(pf);
5301         if (ret != I40E_SUCCESS) {
5302                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5303                 return ret;
5304         }
5305         if (pf->flags & I40E_FLAG_FDIR) {
5306                 /* make queue allocated first, let FDIR use queue pair 0*/
5307                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5308                 if (ret != I40E_FDIR_QUEUE_ID) {
5309                         PMD_DRV_LOG(ERR,
5310                                 "queue allocation fails for FDIR: ret =%d",
5311                                 ret);
5312                         pf->flags &= ~I40E_FLAG_FDIR;
5313                 }
5314         }
5315         /*  main VSI setup */
5316         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5317         if (!vsi) {
5318                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5319                 return I40E_ERR_NOT_READY;
5320         }
5321         pf->main_vsi = vsi;
5322
5323         /* Configure filter control */
5324         memset(&settings, 0, sizeof(settings));
5325         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5326                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5327         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5328                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5329         else {
5330                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5331                         hw->func_caps.rss_table_size);
5332                 return I40E_ERR_PARAM;
5333         }
5334         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5335                 hw->func_caps.rss_table_size);
5336         pf->hash_lut_size = hw->func_caps.rss_table_size;
5337
5338         /* Enable ethtype and macvlan filters */
5339         settings.enable_ethtype = TRUE;
5340         settings.enable_macvlan = TRUE;
5341         ret = i40e_set_filter_control(hw, &settings);
5342         if (ret)
5343                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5344                                                                 ret);
5345
5346         /* Update flow control according to the auto negotiation */
5347         i40e_update_flow_control(hw);
5348
5349         return I40E_SUCCESS;
5350 }
5351
5352 int
5353 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5354 {
5355         uint32_t reg;
5356         uint16_t j;
5357
5358         /**
5359          * Set or clear TX Queue Disable flags,
5360          * which is required by hardware.
5361          */
5362         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5363         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5364
5365         /* Wait until the request is finished */
5366         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5367                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5368                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5369                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5370                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5371                                                         & 0x1))) {
5372                         break;
5373                 }
5374         }
5375         if (on) {
5376                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5377                         return I40E_SUCCESS; /* already on, skip next steps */
5378
5379                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5380                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5381         } else {
5382                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5383                         return I40E_SUCCESS; /* already off, skip next steps */
5384                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5385         }
5386         /* Write the register */
5387         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5388         /* Check the result */
5389         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5390                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5391                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5392                 if (on) {
5393                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5394                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5395                                 break;
5396                 } else {
5397                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5398                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5399                                 break;
5400                 }
5401         }
5402         /* Check if it is timeout */
5403         if (j >= I40E_CHK_Q_ENA_COUNT) {
5404                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5405                             (on ? "enable" : "disable"), q_idx);
5406                 return I40E_ERR_TIMEOUT;
5407         }
5408
5409         return I40E_SUCCESS;
5410 }
5411
5412 /* Swith on or off the tx queues */
5413 static int
5414 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5415 {
5416         struct rte_eth_dev_data *dev_data = pf->dev_data;
5417         struct i40e_tx_queue *txq;
5418         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5419         uint16_t i;
5420         int ret;
5421
5422         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5423                 txq = dev_data->tx_queues[i];
5424                 /* Don't operate the queue if not configured or
5425                  * if starting only per queue */
5426                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5427                         continue;
5428                 if (on)
5429                         ret = i40e_dev_tx_queue_start(dev, i);
5430                 else
5431                         ret = i40e_dev_tx_queue_stop(dev, i);
5432                 if ( ret != I40E_SUCCESS)
5433                         return ret;
5434         }
5435
5436         return I40E_SUCCESS;
5437 }
5438
5439 int
5440 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5441 {
5442         uint32_t reg;
5443         uint16_t j;
5444
5445         /* Wait until the request is finished */
5446         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5447                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5448                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5449                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5450                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5451                         break;
5452         }
5453
5454         if (on) {
5455                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5456                         return I40E_SUCCESS; /* Already on, skip next steps */
5457                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5458         } else {
5459                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5460                         return I40E_SUCCESS; /* Already off, skip next steps */
5461                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5462         }
5463
5464         /* Write the register */
5465         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5466         /* Check the result */
5467         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5468                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5469                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5470                 if (on) {
5471                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5472                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5473                                 break;
5474                 } else {
5475                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5476                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5477                                 break;
5478                 }
5479         }
5480
5481         /* Check if it is timeout */
5482         if (j >= I40E_CHK_Q_ENA_COUNT) {
5483                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5484                             (on ? "enable" : "disable"), q_idx);
5485                 return I40E_ERR_TIMEOUT;
5486         }
5487
5488         return I40E_SUCCESS;
5489 }
5490 /* Switch on or off the rx queues */
5491 static int
5492 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5493 {
5494         struct rte_eth_dev_data *dev_data = pf->dev_data;
5495         struct i40e_rx_queue *rxq;
5496         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5497         uint16_t i;
5498         int ret;
5499
5500         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5501                 rxq = dev_data->rx_queues[i];
5502                 /* Don't operate the queue if not configured or
5503                  * if starting only per queue */
5504                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5505                         continue;
5506                 if (on)
5507                         ret = i40e_dev_rx_queue_start(dev, i);
5508                 else
5509                         ret = i40e_dev_rx_queue_stop(dev, i);
5510                 if (ret != I40E_SUCCESS)
5511                         return ret;
5512         }
5513
5514         return I40E_SUCCESS;
5515 }
5516
5517 /* Switch on or off all the rx/tx queues */
5518 int
5519 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5520 {
5521         int ret;
5522
5523         if (on) {
5524                 /* enable rx queues before enabling tx queues */
5525                 ret = i40e_dev_switch_rx_queues(pf, on);
5526                 if (ret) {
5527                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5528                         return ret;
5529                 }
5530                 ret = i40e_dev_switch_tx_queues(pf, on);
5531         } else {
5532                 /* Stop tx queues before stopping rx queues */
5533                 ret = i40e_dev_switch_tx_queues(pf, on);
5534                 if (ret) {
5535                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5536                         return ret;
5537                 }
5538                 ret = i40e_dev_switch_rx_queues(pf, on);
5539         }
5540
5541         return ret;
5542 }
5543
5544 /* Initialize VSI for TX */
5545 static int
5546 i40e_dev_tx_init(struct i40e_pf *pf)
5547 {
5548         struct rte_eth_dev_data *data = pf->dev_data;
5549         uint16_t i;
5550         uint32_t ret = I40E_SUCCESS;
5551         struct i40e_tx_queue *txq;
5552
5553         for (i = 0; i < data->nb_tx_queues; i++) {
5554                 txq = data->tx_queues[i];
5555                 if (!txq || !txq->q_set)
5556                         continue;
5557                 ret = i40e_tx_queue_init(txq);
5558                 if (ret != I40E_SUCCESS)
5559                         break;
5560         }
5561         if (ret == I40E_SUCCESS)
5562                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5563                                      ->eth_dev);
5564
5565         return ret;
5566 }
5567
5568 /* Initialize VSI for RX */
5569 static int
5570 i40e_dev_rx_init(struct i40e_pf *pf)
5571 {
5572         struct rte_eth_dev_data *data = pf->dev_data;
5573         int ret = I40E_SUCCESS;
5574         uint16_t i;
5575         struct i40e_rx_queue *rxq;
5576
5577         i40e_pf_config_mq_rx(pf);
5578         for (i = 0; i < data->nb_rx_queues; i++) {
5579                 rxq = data->rx_queues[i];
5580                 if (!rxq || !rxq->q_set)
5581                         continue;
5582
5583                 ret = i40e_rx_queue_init(rxq);
5584                 if (ret != I40E_SUCCESS) {
5585                         PMD_DRV_LOG(ERR,
5586                                 "Failed to do RX queue initialization");
5587                         break;
5588                 }
5589         }
5590         if (ret == I40E_SUCCESS)
5591                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5592                                      ->eth_dev);
5593
5594         return ret;
5595 }
5596
5597 static int
5598 i40e_dev_rxtx_init(struct i40e_pf *pf)
5599 {
5600         int err;
5601
5602         err = i40e_dev_tx_init(pf);
5603         if (err) {
5604                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5605                 return err;
5606         }
5607         err = i40e_dev_rx_init(pf);
5608         if (err) {
5609                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5610                 return err;
5611         }
5612
5613         return err;
5614 }
5615
5616 static int
5617 i40e_vmdq_setup(struct rte_eth_dev *dev)
5618 {
5619         struct rte_eth_conf *conf = &dev->data->dev_conf;
5620         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5621         int i, err, conf_vsis, j, loop;
5622         struct i40e_vsi *vsi;
5623         struct i40e_vmdq_info *vmdq_info;
5624         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5625         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5626
5627         /*
5628          * Disable interrupt to avoid message from VF. Furthermore, it will
5629          * avoid race condition in VSI creation/destroy.
5630          */
5631         i40e_pf_disable_irq0(hw);
5632
5633         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5634                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5635                 return -ENOTSUP;
5636         }
5637
5638         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5639         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5640                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5641                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5642                         pf->max_nb_vmdq_vsi);
5643                 return -ENOTSUP;
5644         }
5645
5646         if (pf->vmdq != NULL) {
5647                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5648                 return 0;
5649         }
5650
5651         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5652                                 sizeof(*vmdq_info) * conf_vsis, 0);
5653
5654         if (pf->vmdq == NULL) {
5655                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5656                 return -ENOMEM;
5657         }
5658
5659         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5660
5661         /* Create VMDQ VSI */
5662         for (i = 0; i < conf_vsis; i++) {
5663                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5664                                 vmdq_conf->enable_loop_back);
5665                 if (vsi == NULL) {
5666                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5667                         err = -1;
5668                         goto err_vsi_setup;
5669                 }
5670                 vmdq_info = &pf->vmdq[i];
5671                 vmdq_info->pf = pf;
5672                 vmdq_info->vsi = vsi;
5673         }
5674         pf->nb_cfg_vmdq_vsi = conf_vsis;
5675
5676         /* Configure Vlan */
5677         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5678         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5679                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5680                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5681                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5682                                         vmdq_conf->pool_map[i].vlan_id, j);
5683
5684                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5685                                                 vmdq_conf->pool_map[i].vlan_id);
5686                                 if (err) {
5687                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5688                                         err = -1;
5689                                         goto err_vsi_setup;
5690                                 }
5691                         }
5692                 }
5693         }
5694
5695         i40e_pf_enable_irq0(hw);
5696
5697         return 0;
5698
5699 err_vsi_setup:
5700         for (i = 0; i < conf_vsis; i++)
5701                 if (pf->vmdq[i].vsi == NULL)
5702                         break;
5703                 else
5704                         i40e_vsi_release(pf->vmdq[i].vsi);
5705
5706         rte_free(pf->vmdq);
5707         pf->vmdq = NULL;
5708         i40e_pf_enable_irq0(hw);
5709         return err;
5710 }
5711
5712 static void
5713 i40e_stat_update_32(struct i40e_hw *hw,
5714                    uint32_t reg,
5715                    bool offset_loaded,
5716                    uint64_t *offset,
5717                    uint64_t *stat)
5718 {
5719         uint64_t new_data;
5720
5721         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5722         if (!offset_loaded)
5723                 *offset = new_data;
5724
5725         if (new_data >= *offset)
5726                 *stat = (uint64_t)(new_data - *offset);
5727         else
5728                 *stat = (uint64_t)((new_data +
5729                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5730 }
5731
5732 static void
5733 i40e_stat_update_48(struct i40e_hw *hw,
5734                    uint32_t hireg,
5735                    uint32_t loreg,
5736                    bool offset_loaded,
5737                    uint64_t *offset,
5738                    uint64_t *stat)
5739 {
5740         uint64_t new_data;
5741
5742         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5743         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5744                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5745
5746         if (!offset_loaded)
5747                 *offset = new_data;
5748
5749         if (new_data >= *offset)
5750                 *stat = new_data - *offset;
5751         else
5752                 *stat = (uint64_t)((new_data +
5753                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5754
5755         *stat &= I40E_48_BIT_MASK;
5756 }
5757
5758 /* Disable IRQ0 */
5759 void
5760 i40e_pf_disable_irq0(struct i40e_hw *hw)
5761 {
5762         /* Disable all interrupt types */
5763         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5764         I40E_WRITE_FLUSH(hw);
5765 }
5766
5767 /* Enable IRQ0 */
5768 void
5769 i40e_pf_enable_irq0(struct i40e_hw *hw)
5770 {
5771         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5772                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5773                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5774                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5775         I40E_WRITE_FLUSH(hw);
5776 }
5777
5778 static void
5779 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5780 {
5781         /* read pending request and disable first */
5782         i40e_pf_disable_irq0(hw);
5783         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5784         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5785                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5786
5787         if (no_queue)
5788                 /* Link no queues with irq0 */
5789                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5790                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5791 }
5792
5793 static void
5794 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5795 {
5796         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5797         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5798         int i;
5799         uint16_t abs_vf_id;
5800         uint32_t index, offset, val;
5801
5802         if (!pf->vfs)
5803                 return;
5804         /**
5805          * Try to find which VF trigger a reset, use absolute VF id to access
5806          * since the reg is global register.
5807          */
5808         for (i = 0; i < pf->vf_num; i++) {
5809                 abs_vf_id = hw->func_caps.vf_base_id + i;
5810                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5811                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5812                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5813                 /* VFR event occurred */
5814                 if (val & (0x1 << offset)) {
5815                         int ret;
5816
5817                         /* Clear the event first */
5818                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5819                                                         (0x1 << offset));
5820                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5821                         /**
5822                          * Only notify a VF reset event occurred,
5823                          * don't trigger another SW reset
5824                          */
5825                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5826                         if (ret != I40E_SUCCESS)
5827                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5828                 }
5829         }
5830 }
5831
5832 static void
5833 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5834 {
5835         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5836         int i;
5837
5838         for (i = 0; i < pf->vf_num; i++)
5839                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5840 }
5841
5842 static void
5843 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5844 {
5845         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5846         struct i40e_arq_event_info info;
5847         uint16_t pending, opcode;
5848         int ret;
5849
5850         info.buf_len = I40E_AQ_BUF_SZ;
5851         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5852         if (!info.msg_buf) {
5853                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5854                 return;
5855         }
5856
5857         pending = 1;
5858         while (pending) {
5859                 ret = i40e_clean_arq_element(hw, &info, &pending);
5860
5861                 if (ret != I40E_SUCCESS) {
5862                         PMD_DRV_LOG(INFO,
5863                                 "Failed to read msg from AdminQ, aq_err: %u",
5864                                 hw->aq.asq_last_status);
5865                         break;
5866                 }
5867                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5868
5869                 switch (opcode) {
5870                 case i40e_aqc_opc_send_msg_to_pf:
5871                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5872                         i40e_pf_host_handle_vf_msg(dev,
5873                                         rte_le_to_cpu_16(info.desc.retval),
5874                                         rte_le_to_cpu_32(info.desc.cookie_high),
5875                                         rte_le_to_cpu_32(info.desc.cookie_low),
5876                                         info.msg_buf,
5877                                         info.msg_len);
5878                         break;
5879                 case i40e_aqc_opc_get_link_status:
5880                         ret = i40e_dev_link_update(dev, 0);
5881                         if (!ret)
5882                                 _rte_eth_dev_callback_process(dev,
5883                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5884                         break;
5885                 default:
5886                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5887                                     opcode);
5888                         break;
5889                 }
5890         }
5891         rte_free(info.msg_buf);
5892 }
5893
5894 /**
5895  * Interrupt handler triggered by NIC  for handling
5896  * specific interrupt.
5897  *
5898  * @param handle
5899  *  Pointer to interrupt handle.
5900  * @param param
5901  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5902  *
5903  * @return
5904  *  void
5905  */
5906 static void
5907 i40e_dev_interrupt_handler(void *param)
5908 {
5909         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5911         uint32_t icr0;
5912
5913         /* Disable interrupt */
5914         i40e_pf_disable_irq0(hw);
5915
5916         /* read out interrupt causes */
5917         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5918
5919         /* No interrupt event indicated */
5920         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5921                 PMD_DRV_LOG(INFO, "No interrupt event");
5922                 goto done;
5923         }
5924         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5925                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5926         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5927                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5928         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5929                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5930         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5931                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5932         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5933                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5934         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5935                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5936         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5937                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5938
5939         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5940                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5941                 i40e_dev_handle_vfr_event(dev);
5942         }
5943         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5944                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5945                 i40e_dev_handle_aq_msg(dev);
5946         }
5947
5948 done:
5949         /* Enable interrupt */
5950         i40e_pf_enable_irq0(hw);
5951         rte_intr_enable(dev->intr_handle);
5952 }
5953
5954 int
5955 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5956                          struct i40e_macvlan_filter *filter,
5957                          int total)
5958 {
5959         int ele_num, ele_buff_size;
5960         int num, actual_num, i;
5961         uint16_t flags;
5962         int ret = I40E_SUCCESS;
5963         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5964         struct i40e_aqc_add_macvlan_element_data *req_list;
5965
5966         if (filter == NULL  || total == 0)
5967                 return I40E_ERR_PARAM;
5968         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5969         ele_buff_size = hw->aq.asq_buf_size;
5970
5971         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5972         if (req_list == NULL) {
5973                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5974                 return I40E_ERR_NO_MEMORY;
5975         }
5976
5977         num = 0;
5978         do {
5979                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5980                 memset(req_list, 0, ele_buff_size);
5981
5982                 for (i = 0; i < actual_num; i++) {
5983                         (void)rte_memcpy(req_list[i].mac_addr,
5984                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5985                         req_list[i].vlan_tag =
5986                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5987
5988                         switch (filter[num + i].filter_type) {
5989                         case RTE_MAC_PERFECT_MATCH:
5990                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5991                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5992                                 break;
5993                         case RTE_MACVLAN_PERFECT_MATCH:
5994                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5995                                 break;
5996                         case RTE_MAC_HASH_MATCH:
5997                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5998                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5999                                 break;
6000                         case RTE_MACVLAN_HASH_MATCH:
6001                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6002                                 break;
6003                         default:
6004                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6005                                 ret = I40E_ERR_PARAM;
6006                                 goto DONE;
6007                         }
6008
6009                         req_list[i].queue_number = 0;
6010
6011                         req_list[i].flags = rte_cpu_to_le_16(flags);
6012                 }
6013
6014                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6015                                                 actual_num, NULL);
6016                 if (ret != I40E_SUCCESS) {
6017                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6018                         goto DONE;
6019                 }
6020                 num += actual_num;
6021         } while (num < total);
6022
6023 DONE:
6024         rte_free(req_list);
6025         return ret;
6026 }
6027
6028 int
6029 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6030                             struct i40e_macvlan_filter *filter,
6031                             int total)
6032 {
6033         int ele_num, ele_buff_size;
6034         int num, actual_num, i;
6035         uint16_t flags;
6036         int ret = I40E_SUCCESS;
6037         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6038         struct i40e_aqc_remove_macvlan_element_data *req_list;
6039
6040         if (filter == NULL  || total == 0)
6041                 return I40E_ERR_PARAM;
6042
6043         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6044         ele_buff_size = hw->aq.asq_buf_size;
6045
6046         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6047         if (req_list == NULL) {
6048                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6049                 return I40E_ERR_NO_MEMORY;
6050         }
6051
6052         num = 0;
6053         do {
6054                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6055                 memset(req_list, 0, ele_buff_size);
6056
6057                 for (i = 0; i < actual_num; i++) {
6058                         (void)rte_memcpy(req_list[i].mac_addr,
6059                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6060                         req_list[i].vlan_tag =
6061                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6062
6063                         switch (filter[num + i].filter_type) {
6064                         case RTE_MAC_PERFECT_MATCH:
6065                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6066                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6067                                 break;
6068                         case RTE_MACVLAN_PERFECT_MATCH:
6069                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6070                                 break;
6071                         case RTE_MAC_HASH_MATCH:
6072                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6073                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6074                                 break;
6075                         case RTE_MACVLAN_HASH_MATCH:
6076                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6077                                 break;
6078                         default:
6079                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6080                                 ret = I40E_ERR_PARAM;
6081                                 goto DONE;
6082                         }
6083                         req_list[i].flags = rte_cpu_to_le_16(flags);
6084                 }
6085
6086                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6087                                                 actual_num, NULL);
6088                 if (ret != I40E_SUCCESS) {
6089                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6090                         goto DONE;
6091                 }
6092                 num += actual_num;
6093         } while (num < total);
6094
6095 DONE:
6096         rte_free(req_list);
6097         return ret;
6098 }
6099
6100 /* Find out specific MAC filter */
6101 static struct i40e_mac_filter *
6102 i40e_find_mac_filter(struct i40e_vsi *vsi,
6103                          struct ether_addr *macaddr)
6104 {
6105         struct i40e_mac_filter *f;
6106
6107         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6108                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6109                         return f;
6110         }
6111
6112         return NULL;
6113 }
6114
6115 static bool
6116 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6117                          uint16_t vlan_id)
6118 {
6119         uint32_t vid_idx, vid_bit;
6120
6121         if (vlan_id > ETH_VLAN_ID_MAX)
6122                 return 0;
6123
6124         vid_idx = I40E_VFTA_IDX(vlan_id);
6125         vid_bit = I40E_VFTA_BIT(vlan_id);
6126
6127         if (vsi->vfta[vid_idx] & vid_bit)
6128                 return 1;
6129         else
6130                 return 0;
6131 }
6132
6133 static void
6134 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6135                        uint16_t vlan_id, bool on)
6136 {
6137         uint32_t vid_idx, vid_bit;
6138
6139         vid_idx = I40E_VFTA_IDX(vlan_id);
6140         vid_bit = I40E_VFTA_BIT(vlan_id);
6141
6142         if (on)
6143                 vsi->vfta[vid_idx] |= vid_bit;
6144         else
6145                 vsi->vfta[vid_idx] &= ~vid_bit;
6146 }
6147
6148 void
6149 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6150                      uint16_t vlan_id, bool on)
6151 {
6152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6153         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6154         int ret;
6155
6156         if (vlan_id > ETH_VLAN_ID_MAX)
6157                 return;
6158
6159         i40e_store_vlan_filter(vsi, vlan_id, on);
6160
6161         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6162                 return;
6163
6164         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6165
6166         if (on) {
6167                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6168                                        &vlan_data, 1, NULL);
6169                 if (ret != I40E_SUCCESS)
6170                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6171         } else {
6172                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6173                                           &vlan_data, 1, NULL);
6174                 if (ret != I40E_SUCCESS)
6175                         PMD_DRV_LOG(ERR,
6176                                     "Failed to remove vlan filter");
6177         }
6178 }
6179
6180 /**
6181  * Find all vlan options for specific mac addr,
6182  * return with actual vlan found.
6183  */
6184 int
6185 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6186                            struct i40e_macvlan_filter *mv_f,
6187                            int num, struct ether_addr *addr)
6188 {
6189         int i;
6190         uint32_t j, k;
6191
6192         /**
6193          * Not to use i40e_find_vlan_filter to decrease the loop time,
6194          * although the code looks complex.
6195           */
6196         if (num < vsi->vlan_num)
6197                 return I40E_ERR_PARAM;
6198
6199         i = 0;
6200         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6201                 if (vsi->vfta[j]) {
6202                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6203                                 if (vsi->vfta[j] & (1 << k)) {
6204                                         if (i > num - 1) {
6205                                                 PMD_DRV_LOG(ERR,
6206                                                         "vlan number doesn't match");
6207                                                 return I40E_ERR_PARAM;
6208                                         }
6209                                         (void)rte_memcpy(&mv_f[i].macaddr,
6210                                                         addr, ETH_ADDR_LEN);
6211                                         mv_f[i].vlan_id =
6212                                                 j * I40E_UINT32_BIT_SIZE + k;
6213                                         i++;
6214                                 }
6215                         }
6216                 }
6217         }
6218         return I40E_SUCCESS;
6219 }
6220
6221 static inline int
6222 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6223                            struct i40e_macvlan_filter *mv_f,
6224                            int num,
6225                            uint16_t vlan)
6226 {
6227         int i = 0;
6228         struct i40e_mac_filter *f;
6229
6230         if (num < vsi->mac_num)
6231                 return I40E_ERR_PARAM;
6232
6233         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6234                 if (i > num - 1) {
6235                         PMD_DRV_LOG(ERR, "buffer number not match");
6236                         return I40E_ERR_PARAM;
6237                 }
6238                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6239                                 ETH_ADDR_LEN);
6240                 mv_f[i].vlan_id = vlan;
6241                 mv_f[i].filter_type = f->mac_info.filter_type;
6242                 i++;
6243         }
6244
6245         return I40E_SUCCESS;
6246 }
6247
6248 static int
6249 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6250 {
6251         int i, j, num;
6252         struct i40e_mac_filter *f;
6253         struct i40e_macvlan_filter *mv_f;
6254         int ret = I40E_SUCCESS;
6255
6256         if (vsi == NULL || vsi->mac_num == 0)
6257                 return I40E_ERR_PARAM;
6258
6259         /* Case that no vlan is set */
6260         if (vsi->vlan_num == 0)
6261                 num = vsi->mac_num;
6262         else
6263                 num = vsi->mac_num * vsi->vlan_num;
6264
6265         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6266         if (mv_f == NULL) {
6267                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6268                 return I40E_ERR_NO_MEMORY;
6269         }
6270
6271         i = 0;
6272         if (vsi->vlan_num == 0) {
6273                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6274                         (void)rte_memcpy(&mv_f[i].macaddr,
6275                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6276                         mv_f[i].filter_type = f->mac_info.filter_type;
6277                         mv_f[i].vlan_id = 0;
6278                         i++;
6279                 }
6280         } else {
6281                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6282                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6283                                         vsi->vlan_num, &f->mac_info.mac_addr);
6284                         if (ret != I40E_SUCCESS)
6285                                 goto DONE;
6286                         for (j = i; j < i + vsi->vlan_num; j++)
6287                                 mv_f[j].filter_type = f->mac_info.filter_type;
6288                         i += vsi->vlan_num;
6289                 }
6290         }
6291
6292         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6293 DONE:
6294         rte_free(mv_f);
6295
6296         return ret;
6297 }
6298
6299 int
6300 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6301 {
6302         struct i40e_macvlan_filter *mv_f;
6303         int mac_num;
6304         int ret = I40E_SUCCESS;
6305
6306         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6307                 return I40E_ERR_PARAM;
6308
6309         /* If it's already set, just return */
6310         if (i40e_find_vlan_filter(vsi,vlan))
6311                 return I40E_SUCCESS;
6312
6313         mac_num = vsi->mac_num;
6314
6315         if (mac_num == 0) {
6316                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6317                 return I40E_ERR_PARAM;
6318         }
6319
6320         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6321
6322         if (mv_f == NULL) {
6323                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6324                 return I40E_ERR_NO_MEMORY;
6325         }
6326
6327         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6328
6329         if (ret != I40E_SUCCESS)
6330                 goto DONE;
6331
6332         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6333
6334         if (ret != I40E_SUCCESS)
6335                 goto DONE;
6336
6337         i40e_set_vlan_filter(vsi, vlan, 1);
6338
6339         vsi->vlan_num++;
6340         ret = I40E_SUCCESS;
6341 DONE:
6342         rte_free(mv_f);
6343         return ret;
6344 }
6345
6346 int
6347 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6348 {
6349         struct i40e_macvlan_filter *mv_f;
6350         int mac_num;
6351         int ret = I40E_SUCCESS;
6352
6353         /**
6354          * Vlan 0 is the generic filter for untagged packets
6355          * and can't be removed.
6356          */
6357         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6358                 return I40E_ERR_PARAM;
6359
6360         /* If can't find it, just return */
6361         if (!i40e_find_vlan_filter(vsi, vlan))
6362                 return I40E_ERR_PARAM;
6363
6364         mac_num = vsi->mac_num;
6365
6366         if (mac_num == 0) {
6367                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6368                 return I40E_ERR_PARAM;
6369         }
6370
6371         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6372
6373         if (mv_f == NULL) {
6374                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6375                 return I40E_ERR_NO_MEMORY;
6376         }
6377
6378         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6379
6380         if (ret != I40E_SUCCESS)
6381                 goto DONE;
6382
6383         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6384
6385         if (ret != I40E_SUCCESS)
6386                 goto DONE;
6387
6388         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6389         if (vsi->vlan_num == 1) {
6390                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6391                 if (ret != I40E_SUCCESS)
6392                         goto DONE;
6393
6394                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6395                 if (ret != I40E_SUCCESS)
6396                         goto DONE;
6397         }
6398
6399         i40e_set_vlan_filter(vsi, vlan, 0);
6400
6401         vsi->vlan_num--;
6402         ret = I40E_SUCCESS;
6403 DONE:
6404         rte_free(mv_f);
6405         return ret;
6406 }
6407
6408 int
6409 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6410 {
6411         struct i40e_mac_filter *f;
6412         struct i40e_macvlan_filter *mv_f;
6413         int i, vlan_num = 0;
6414         int ret = I40E_SUCCESS;
6415
6416         /* If it's add and we've config it, return */
6417         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6418         if (f != NULL)
6419                 return I40E_SUCCESS;
6420         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6421                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6422
6423                 /**
6424                  * If vlan_num is 0, that's the first time to add mac,
6425                  * set mask for vlan_id 0.
6426                  */
6427                 if (vsi->vlan_num == 0) {
6428                         i40e_set_vlan_filter(vsi, 0, 1);
6429                         vsi->vlan_num = 1;
6430                 }
6431                 vlan_num = vsi->vlan_num;
6432         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6433                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6434                 vlan_num = 1;
6435
6436         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6437         if (mv_f == NULL) {
6438                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6439                 return I40E_ERR_NO_MEMORY;
6440         }
6441
6442         for (i = 0; i < vlan_num; i++) {
6443                 mv_f[i].filter_type = mac_filter->filter_type;
6444                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6445                                 ETH_ADDR_LEN);
6446         }
6447
6448         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6449                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6450                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6451                                         &mac_filter->mac_addr);
6452                 if (ret != I40E_SUCCESS)
6453                         goto DONE;
6454         }
6455
6456         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6457         if (ret != I40E_SUCCESS)
6458                 goto DONE;
6459
6460         /* Add the mac addr into mac list */
6461         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6462         if (f == NULL) {
6463                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6464                 ret = I40E_ERR_NO_MEMORY;
6465                 goto DONE;
6466         }
6467         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6468                         ETH_ADDR_LEN);
6469         f->mac_info.filter_type = mac_filter->filter_type;
6470         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6471         vsi->mac_num++;
6472
6473         ret = I40E_SUCCESS;
6474 DONE:
6475         rte_free(mv_f);
6476
6477         return ret;
6478 }
6479
6480 int
6481 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6482 {
6483         struct i40e_mac_filter *f;
6484         struct i40e_macvlan_filter *mv_f;
6485         int i, vlan_num;
6486         enum rte_mac_filter_type filter_type;
6487         int ret = I40E_SUCCESS;
6488
6489         /* Can't find it, return an error */
6490         f = i40e_find_mac_filter(vsi, addr);
6491         if (f == NULL)
6492                 return I40E_ERR_PARAM;
6493
6494         vlan_num = vsi->vlan_num;
6495         filter_type = f->mac_info.filter_type;
6496         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6497                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6498                 if (vlan_num == 0) {
6499                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6500                         return I40E_ERR_PARAM;
6501                 }
6502         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6503                         filter_type == RTE_MAC_HASH_MATCH)
6504                 vlan_num = 1;
6505
6506         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6507         if (mv_f == NULL) {
6508                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6509                 return I40E_ERR_NO_MEMORY;
6510         }
6511
6512         for (i = 0; i < vlan_num; i++) {
6513                 mv_f[i].filter_type = filter_type;
6514                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6515                                 ETH_ADDR_LEN);
6516         }
6517         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6518                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6519                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6520                 if (ret != I40E_SUCCESS)
6521                         goto DONE;
6522         }
6523
6524         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6525         if (ret != I40E_SUCCESS)
6526                 goto DONE;
6527
6528         /* Remove the mac addr into mac list */
6529         TAILQ_REMOVE(&vsi->mac_list, f, next);
6530         rte_free(f);
6531         vsi->mac_num--;
6532
6533         ret = I40E_SUCCESS;
6534 DONE:
6535         rte_free(mv_f);
6536         return ret;
6537 }
6538
6539 /* Configure hash enable flags for RSS */
6540 uint64_t
6541 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6542 {
6543         uint64_t hena = 0;
6544
6545         if (!flags)
6546                 return hena;
6547
6548         if (flags & ETH_RSS_FRAG_IPV4)
6549                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6550         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6551                 if (type == I40E_MAC_X722) {
6552                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6553                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6554                 } else
6555                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6556         }
6557         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6558                 if (type == I40E_MAC_X722) {
6559                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6560                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6561                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6562                 } else
6563                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6564         }
6565         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6566                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6567         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6568                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6569         if (flags & ETH_RSS_FRAG_IPV6)
6570                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6571         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6572                 if (type == I40E_MAC_X722) {
6573                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6574                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6575                 } else
6576                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6577         }
6578         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6579                 if (type == I40E_MAC_X722) {
6580                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6581                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6582                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6583                 } else
6584                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6585         }
6586         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6587                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6588         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6589                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6590         if (flags & ETH_RSS_L2_PAYLOAD)
6591                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6592
6593         return hena;
6594 }
6595
6596 /* Parse the hash enable flags */
6597 uint64_t
6598 i40e_parse_hena(uint64_t flags)
6599 {
6600         uint64_t rss_hf = 0;
6601
6602         if (!flags)
6603                 return rss_hf;
6604         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6605                 rss_hf |= ETH_RSS_FRAG_IPV4;
6606         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6607                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6608         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6609                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6610         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6611                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6612         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6613                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6614         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6615                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6616         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6617                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6618         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6619                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6620         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6621                 rss_hf |= ETH_RSS_FRAG_IPV6;
6622         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6623                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6624         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6625                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6626         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6627                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6628         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6629                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6630         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6631                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6632         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6633                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6634         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6635                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6636         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6637                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6638
6639         return rss_hf;
6640 }
6641
6642 /* Disable RSS */
6643 static void
6644 i40e_pf_disable_rss(struct i40e_pf *pf)
6645 {
6646         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6647         uint64_t hena;
6648
6649         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6650         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6651         if (hw->mac.type == I40E_MAC_X722)
6652                 hena &= ~I40E_RSS_HENA_ALL_X722;
6653         else
6654                 hena &= ~I40E_RSS_HENA_ALL;
6655         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6656         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6657         I40E_WRITE_FLUSH(hw);
6658 }
6659
6660 static int
6661 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6662 {
6663         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6664         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6665         int ret = 0;
6666
6667         if (!key || key_len == 0) {
6668                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6669                 return 0;
6670         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6671                 sizeof(uint32_t)) {
6672                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6673                 return -EINVAL;
6674         }
6675
6676         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6677                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6678                         (struct i40e_aqc_get_set_rss_key_data *)key;
6679
6680                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6681                 if (ret)
6682                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6683         } else {
6684                 uint32_t *hash_key = (uint32_t *)key;
6685                 uint16_t i;
6686
6687                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6688                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6689                 I40E_WRITE_FLUSH(hw);
6690         }
6691
6692         return ret;
6693 }
6694
6695 static int
6696 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6697 {
6698         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6699         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6700         int ret;
6701
6702         if (!key || !key_len)
6703                 return -EINVAL;
6704
6705         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6706                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6707                         (struct i40e_aqc_get_set_rss_key_data *)key);
6708                 if (ret) {
6709                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6710                         return ret;
6711                 }
6712         } else {
6713                 uint32_t *key_dw = (uint32_t *)key;
6714                 uint16_t i;
6715
6716                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6717                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6718         }
6719         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6720
6721         return 0;
6722 }
6723
6724 static int
6725 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6726 {
6727         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6728         uint64_t rss_hf;
6729         uint64_t hena;
6730         int ret;
6731
6732         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6733                                rss_conf->rss_key_len);
6734         if (ret)
6735                 return ret;
6736
6737         rss_hf = rss_conf->rss_hf;
6738         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6739         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6740         if (hw->mac.type == I40E_MAC_X722)
6741                 hena &= ~I40E_RSS_HENA_ALL_X722;
6742         else
6743                 hena &= ~I40E_RSS_HENA_ALL;
6744         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6745         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6746         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6747         I40E_WRITE_FLUSH(hw);
6748
6749         return 0;
6750 }
6751
6752 static int
6753 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6754                          struct rte_eth_rss_conf *rss_conf)
6755 {
6756         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6757         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6758         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6759         uint64_t hena;
6760
6761         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6762         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6763         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6764                  ? I40E_RSS_HENA_ALL_X722
6765                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6766                 if (rss_hf != 0) /* Enable RSS */
6767                         return -EINVAL;
6768                 return 0; /* Nothing to do */
6769         }
6770         /* RSS enabled */
6771         if (rss_hf == 0) /* Disable RSS */
6772                 return -EINVAL;
6773
6774         return i40e_hw_rss_hash_set(pf, rss_conf);
6775 }
6776
6777 static int
6778 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6779                            struct rte_eth_rss_conf *rss_conf)
6780 {
6781         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783         uint64_t hena;
6784
6785         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6786                          &rss_conf->rss_key_len);
6787
6788         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6789         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6790         rss_conf->rss_hf = i40e_parse_hena(hena);
6791
6792         return 0;
6793 }
6794
6795 static int
6796 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6797 {
6798         switch (filter_type) {
6799         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6800                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6801                 break;
6802         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6803                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6804                 break;
6805         case RTE_TUNNEL_FILTER_IMAC_TENID:
6806                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6807                 break;
6808         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6809                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6810                 break;
6811         case ETH_TUNNEL_FILTER_IMAC:
6812                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6813                 break;
6814         case ETH_TUNNEL_FILTER_OIP:
6815                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6816                 break;
6817         case ETH_TUNNEL_FILTER_IIP:
6818                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6819                 break;
6820         default:
6821                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6822                 return -EINVAL;
6823         }
6824
6825         return 0;
6826 }
6827
6828 /* Convert tunnel filter structure */
6829 static int
6830 i40e_tunnel_filter_convert(
6831         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6832         struct i40e_tunnel_filter *tunnel_filter)
6833 {
6834         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6835                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6836         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6837                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6838         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6839         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6840              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6841             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6842                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6843         else
6844                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6845         tunnel_filter->input.flags = cld_filter->element.flags;
6846         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6847         tunnel_filter->queue = cld_filter->element.queue_number;
6848         rte_memcpy(tunnel_filter->input.general_fields,
6849                    cld_filter->general_fields,
6850                    sizeof(cld_filter->general_fields));
6851
6852         return 0;
6853 }
6854
6855 /* Check if there exists the tunnel filter */
6856 struct i40e_tunnel_filter *
6857 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6858                              const struct i40e_tunnel_filter_input *input)
6859 {
6860         int ret;
6861
6862         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6863         if (ret < 0)
6864                 return NULL;
6865
6866         return tunnel_rule->hash_map[ret];
6867 }
6868
6869 /* Add a tunnel filter into the SW list */
6870 static int
6871 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6872                              struct i40e_tunnel_filter *tunnel_filter)
6873 {
6874         struct i40e_tunnel_rule *rule = &pf->tunnel;
6875         int ret;
6876
6877         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6878         if (ret < 0) {
6879                 PMD_DRV_LOG(ERR,
6880                             "Failed to insert tunnel filter to hash table %d!",
6881                             ret);
6882                 return ret;
6883         }
6884         rule->hash_map[ret] = tunnel_filter;
6885
6886         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6887
6888         return 0;
6889 }
6890
6891 /* Delete a tunnel filter from the SW list */
6892 int
6893 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6894                           struct i40e_tunnel_filter_input *input)
6895 {
6896         struct i40e_tunnel_rule *rule = &pf->tunnel;
6897         struct i40e_tunnel_filter *tunnel_filter;
6898         int ret;
6899
6900         ret = rte_hash_del_key(rule->hash_table, input);
6901         if (ret < 0) {
6902                 PMD_DRV_LOG(ERR,
6903                             "Failed to delete tunnel filter to hash table %d!",
6904                             ret);
6905                 return ret;
6906         }
6907         tunnel_filter = rule->hash_map[ret];
6908         rule->hash_map[ret] = NULL;
6909
6910         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6911         rte_free(tunnel_filter);
6912
6913         return 0;
6914 }
6915
6916 int
6917 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6918                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6919                         uint8_t add)
6920 {
6921         uint16_t ip_type;
6922         uint32_t ipv4_addr;
6923         uint8_t i, tun_type = 0;
6924         /* internal varialbe to convert ipv6 byte order */
6925         uint32_t convert_ipv6[4];
6926         int val, ret = 0;
6927         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6928         struct i40e_vsi *vsi = pf->main_vsi;
6929         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6930         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6931         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6932         struct i40e_tunnel_filter *tunnel, *node;
6933         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6934
6935         cld_filter = rte_zmalloc("tunnel_filter",
6936                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6937         0);
6938
6939         if (NULL == cld_filter) {
6940                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6941                 return -ENOMEM;
6942         }
6943         pfilter = cld_filter;
6944
6945         ether_addr_copy(&tunnel_filter->outer_mac,
6946                         (struct ether_addr *)&pfilter->element.outer_mac);
6947         ether_addr_copy(&tunnel_filter->inner_mac,
6948                         (struct ether_addr *)&pfilter->element.inner_mac);
6949
6950         pfilter->element.inner_vlan =
6951                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6952         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6953                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6954                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6955                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6956                                 &rte_cpu_to_le_32(ipv4_addr),
6957                                 sizeof(pfilter->element.ipaddr.v4.data));
6958         } else {
6959                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6960                 for (i = 0; i < 4; i++) {
6961                         convert_ipv6[i] =
6962                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6963                 }
6964                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6965                            &convert_ipv6,
6966                            sizeof(pfilter->element.ipaddr.v6.data));
6967         }
6968
6969         /* check tunneled type */
6970         switch (tunnel_filter->tunnel_type) {
6971         case RTE_TUNNEL_TYPE_VXLAN:
6972                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6973                 break;
6974         case RTE_TUNNEL_TYPE_NVGRE:
6975                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6976                 break;
6977         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6978                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6979                 break;
6980         default:
6981                 /* Other tunnel types is not supported. */
6982                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6983                 rte_free(cld_filter);
6984                 return -EINVAL;
6985         }
6986
6987         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6988                                        &pfilter->element.flags);
6989         if (val < 0) {
6990                 rte_free(cld_filter);
6991                 return -EINVAL;
6992         }
6993
6994         pfilter->element.flags |= rte_cpu_to_le_16(
6995                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6996                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6997         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6998         pfilter->element.queue_number =
6999                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7000
7001         /* Check if there is the filter in SW list */
7002         memset(&check_filter, 0, sizeof(check_filter));
7003         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7004         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7005         if (add && node) {
7006                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7007                 return -EINVAL;
7008         }
7009
7010         if (!add && !node) {
7011                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7012                 return -EINVAL;
7013         }
7014
7015         if (add) {
7016                 ret = i40e_aq_add_cloud_filters(hw,
7017                                         vsi->seid, &cld_filter->element, 1);
7018                 if (ret < 0) {
7019                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7020                         return -ENOTSUP;
7021                 }
7022                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7023                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7024                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7025         } else {
7026                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7027                                                    &cld_filter->element, 1);
7028                 if (ret < 0) {
7029                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7030                         return -ENOTSUP;
7031                 }
7032                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7033         }
7034
7035         rte_free(cld_filter);
7036         return ret;
7037 }
7038
7039 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7040 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7041 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7042 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7043 #define I40E_TR_GRE_KEY_MASK                    0x400
7044 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7045 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7046
7047 static enum
7048 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7049 {
7050         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7051         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7052         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7053         enum i40e_status_code status = I40E_SUCCESS;
7054
7055         memset(&filter_replace, 0,
7056                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7057         memset(&filter_replace_buf, 0,
7058                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7059
7060         /* create L1 filter */
7061         filter_replace.old_filter_type =
7062                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7063         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7064         filter_replace.tr_bit = 0;
7065
7066         /* Prepare the buffer, 3 entries */
7067         filter_replace_buf.data[0] =
7068                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7069         filter_replace_buf.data[0] |=
7070                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7071         filter_replace_buf.data[2] = 0xFF;
7072         filter_replace_buf.data[3] = 0xFF;
7073         filter_replace_buf.data[4] =
7074                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7075         filter_replace_buf.data[4] |=
7076                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7077         filter_replace_buf.data[7] = 0xF0;
7078         filter_replace_buf.data[8]
7079                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7080         filter_replace_buf.data[8] |=
7081                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7082         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7083                 I40E_TR_GENEVE_KEY_MASK |
7084                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7085         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7086                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7087                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7088
7089         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7090                                                &filter_replace_buf);
7091         return status;
7092 }
7093
7094 static enum
7095 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7096 {
7097         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7098         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7099         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7100         enum i40e_status_code status = I40E_SUCCESS;
7101
7102         /* For MPLSoUDP */
7103         memset(&filter_replace, 0,
7104                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7105         memset(&filter_replace_buf, 0,
7106                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7107         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7108                 I40E_AQC_MIRROR_CLOUD_FILTER;
7109         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7110         filter_replace.new_filter_type =
7111                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7112         /* Prepare the buffer, 2 entries */
7113         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7114         filter_replace_buf.data[0] |=
7115                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7116         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7117         filter_replace_buf.data[4] |=
7118                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7119         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7120                                                &filter_replace_buf);
7121         if (status < 0)
7122                 return status;
7123
7124         /* For MPLSoGRE */
7125         memset(&filter_replace, 0,
7126                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7127         memset(&filter_replace_buf, 0,
7128                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7129
7130         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7131                 I40E_AQC_MIRROR_CLOUD_FILTER;
7132         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7133         filter_replace.new_filter_type =
7134                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7135         /* Prepare the buffer, 2 entries */
7136         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7137         filter_replace_buf.data[0] |=
7138                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7139         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7140         filter_replace_buf.data[4] |=
7141                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7142
7143         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7144                                                &filter_replace_buf);
7145         return status;
7146 }
7147
7148 int
7149 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7150                       struct i40e_tunnel_filter_conf *tunnel_filter,
7151                       uint8_t add)
7152 {
7153         uint16_t ip_type;
7154         uint32_t ipv4_addr;
7155         uint8_t i, tun_type = 0;
7156         /* internal variable to convert ipv6 byte order */
7157         uint32_t convert_ipv6[4];
7158         int val, ret = 0;
7159         struct i40e_pf_vf *vf = NULL;
7160         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7161         struct i40e_vsi *vsi;
7162         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7163         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7164         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7165         struct i40e_tunnel_filter *tunnel, *node;
7166         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7167         uint32_t teid_le;
7168         bool big_buffer = 0;
7169
7170         cld_filter = rte_zmalloc("tunnel_filter",
7171                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7172                          0);
7173
7174         if (cld_filter == NULL) {
7175                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7176                 return -ENOMEM;
7177         }
7178         pfilter = cld_filter;
7179
7180         ether_addr_copy(&tunnel_filter->outer_mac,
7181                         (struct ether_addr *)&pfilter->element.outer_mac);
7182         ether_addr_copy(&tunnel_filter->inner_mac,
7183                         (struct ether_addr *)&pfilter->element.inner_mac);
7184
7185         pfilter->element.inner_vlan =
7186                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7187         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7188                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7189                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7190                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7191                                 &rte_cpu_to_le_32(ipv4_addr),
7192                                 sizeof(pfilter->element.ipaddr.v4.data));
7193         } else {
7194                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7195                 for (i = 0; i < 4; i++) {
7196                         convert_ipv6[i] =
7197                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7198                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7199                 }
7200                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7201                            &convert_ipv6,
7202                            sizeof(pfilter->element.ipaddr.v6.data));
7203         }
7204
7205         /* check tunneled type */
7206         switch (tunnel_filter->tunnel_type) {
7207         case I40E_TUNNEL_TYPE_VXLAN:
7208                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7209                 break;
7210         case I40E_TUNNEL_TYPE_NVGRE:
7211                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7212                 break;
7213         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7214                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7215                 break;
7216         case I40E_TUNNEL_TYPE_MPLSoUDP:
7217                 if (!pf->mpls_replace_flag) {
7218                         i40e_replace_mpls_l1_filter(pf);
7219                         i40e_replace_mpls_cloud_filter(pf);
7220                         pf->mpls_replace_flag = 1;
7221                 }
7222                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7223                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7224                         teid_le >> 4;
7225                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7226                         (teid_le & 0xF) << 12;
7227                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7228                         0x40;
7229                 big_buffer = 1;
7230                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7231                 break;
7232         case I40E_TUNNEL_TYPE_MPLSoGRE:
7233                 if (!pf->mpls_replace_flag) {
7234                         i40e_replace_mpls_l1_filter(pf);
7235                         i40e_replace_mpls_cloud_filter(pf);
7236                         pf->mpls_replace_flag = 1;
7237                 }
7238                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7239                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7240                         teid_le >> 4;
7241                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7242                         (teid_le & 0xF) << 12;
7243                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7244                         0x0;
7245                 big_buffer = 1;
7246                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7247                 break;
7248         case I40E_TUNNEL_TYPE_QINQ:
7249                 if (!pf->qinq_replace_flag) {
7250                         ret = i40e_cloud_filter_qinq_create(pf);
7251                         if (ret < 0)
7252                                 PMD_DRV_LOG(DEBUG,
7253                                             "QinQ tunnel filter already created.");
7254                         pf->qinq_replace_flag = 1;
7255                 }
7256                 /*      Add in the General fields the values of
7257                  *      the Outer and Inner VLAN
7258                  *      Big Buffer should be set, see changes in
7259                  *      i40e_aq_add_cloud_filters
7260                  */
7261                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7262                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7263                 big_buffer = 1;
7264                 break;
7265         default:
7266                 /* Other tunnel types is not supported. */
7267                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7268                 rte_free(cld_filter);
7269                 return -EINVAL;
7270         }
7271
7272         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7273                 pfilter->element.flags =
7274                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7275         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7276                 pfilter->element.flags =
7277                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7278         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7279                 pfilter->element.flags |=
7280                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7281         else {
7282                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7283                                                 &pfilter->element.flags);
7284                 if (val < 0) {
7285                         rte_free(cld_filter);
7286                         return -EINVAL;
7287                 }
7288         }
7289
7290         pfilter->element.flags |= rte_cpu_to_le_16(
7291                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7292                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7293         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7294         pfilter->element.queue_number =
7295                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7296
7297         if (!tunnel_filter->is_to_vf)
7298                 vsi = pf->main_vsi;
7299         else {
7300                 if (tunnel_filter->vf_id >= pf->vf_num) {
7301                         PMD_DRV_LOG(ERR, "Invalid argument.");
7302                         return -EINVAL;
7303                 }
7304                 vf = &pf->vfs[tunnel_filter->vf_id];
7305                 vsi = vf->vsi;
7306         }
7307
7308         /* Check if there is the filter in SW list */
7309         memset(&check_filter, 0, sizeof(check_filter));
7310         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7311         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7312         check_filter.vf_id = tunnel_filter->vf_id;
7313         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7314         if (add && node) {
7315                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7316                 return -EINVAL;
7317         }
7318
7319         if (!add && !node) {
7320                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7321                 return -EINVAL;
7322         }
7323
7324         if (add) {
7325                 if (big_buffer)
7326                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7327                                                    vsi->seid, cld_filter, 1);
7328                 else
7329                         ret = i40e_aq_add_cloud_filters(hw,
7330                                         vsi->seid, &cld_filter->element, 1);
7331                 if (ret < 0) {
7332                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7333                         return -ENOTSUP;
7334                 }
7335                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7336                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7337                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7338         } else {
7339                 if (big_buffer)
7340                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7341                                 hw, vsi->seid, cld_filter, 1);
7342                 else
7343                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7344                                                    &cld_filter->element, 1);
7345                 if (ret < 0) {
7346                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7347                         return -ENOTSUP;
7348                 }
7349                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7350         }
7351
7352         rte_free(cld_filter);
7353         return ret;
7354 }
7355
7356 static int
7357 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7358 {
7359         uint8_t i;
7360
7361         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7362                 if (pf->vxlan_ports[i] == port)
7363                         return i;
7364         }
7365
7366         return -1;
7367 }
7368
7369 static int
7370 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7371 {
7372         int  idx, ret;
7373         uint8_t filter_idx;
7374         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7375
7376         idx = i40e_get_vxlan_port_idx(pf, port);
7377
7378         /* Check if port already exists */
7379         if (idx >= 0) {
7380                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7381                 return -EINVAL;
7382         }
7383
7384         /* Now check if there is space to add the new port */
7385         idx = i40e_get_vxlan_port_idx(pf, 0);
7386         if (idx < 0) {
7387                 PMD_DRV_LOG(ERR,
7388                         "Maximum number of UDP ports reached, not adding port %d",
7389                         port);
7390                 return -ENOSPC;
7391         }
7392
7393         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7394                                         &filter_idx, NULL);
7395         if (ret < 0) {
7396                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7397                 return -1;
7398         }
7399
7400         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7401                          port,  filter_idx);
7402
7403         /* New port: add it and mark its index in the bitmap */
7404         pf->vxlan_ports[idx] = port;
7405         pf->vxlan_bitmap |= (1 << idx);
7406
7407         if (!(pf->flags & I40E_FLAG_VXLAN))
7408                 pf->flags |= I40E_FLAG_VXLAN;
7409
7410         return 0;
7411 }
7412
7413 static int
7414 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7415 {
7416         int idx;
7417         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7418
7419         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7420                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7421                 return -EINVAL;
7422         }
7423
7424         idx = i40e_get_vxlan_port_idx(pf, port);
7425
7426         if (idx < 0) {
7427                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7428                 return -EINVAL;
7429         }
7430
7431         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7432                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7433                 return -1;
7434         }
7435
7436         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7437                         port, idx);
7438
7439         pf->vxlan_ports[idx] = 0;
7440         pf->vxlan_bitmap &= ~(1 << idx);
7441
7442         if (!pf->vxlan_bitmap)
7443                 pf->flags &= ~I40E_FLAG_VXLAN;
7444
7445         return 0;
7446 }
7447
7448 /* Add UDP tunneling port */
7449 static int
7450 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7451                              struct rte_eth_udp_tunnel *udp_tunnel)
7452 {
7453         int ret = 0;
7454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7455
7456         if (udp_tunnel == NULL)
7457                 return -EINVAL;
7458
7459         switch (udp_tunnel->prot_type) {
7460         case RTE_TUNNEL_TYPE_VXLAN:
7461                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7462                 break;
7463
7464         case RTE_TUNNEL_TYPE_GENEVE:
7465         case RTE_TUNNEL_TYPE_TEREDO:
7466                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7467                 ret = -1;
7468                 break;
7469
7470         default:
7471                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7472                 ret = -1;
7473                 break;
7474         }
7475
7476         return ret;
7477 }
7478
7479 /* Remove UDP tunneling port */
7480 static int
7481 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7482                              struct rte_eth_udp_tunnel *udp_tunnel)
7483 {
7484         int ret = 0;
7485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7486
7487         if (udp_tunnel == NULL)
7488                 return -EINVAL;
7489
7490         switch (udp_tunnel->prot_type) {
7491         case RTE_TUNNEL_TYPE_VXLAN:
7492                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7493                 break;
7494         case RTE_TUNNEL_TYPE_GENEVE:
7495         case RTE_TUNNEL_TYPE_TEREDO:
7496                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7497                 ret = -1;
7498                 break;
7499         default:
7500                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7501                 ret = -1;
7502                 break;
7503         }
7504
7505         return ret;
7506 }
7507
7508 /* Calculate the maximum number of contiguous PF queues that are configured */
7509 static int
7510 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7511 {
7512         struct rte_eth_dev_data *data = pf->dev_data;
7513         int i, num;
7514         struct i40e_rx_queue *rxq;
7515
7516         num = 0;
7517         for (i = 0; i < pf->lan_nb_qps; i++) {
7518                 rxq = data->rx_queues[i];
7519                 if (rxq && rxq->q_set)
7520                         num++;
7521                 else
7522                         break;
7523         }
7524
7525         return num;
7526 }
7527
7528 /* Configure RSS */
7529 static int
7530 i40e_pf_config_rss(struct i40e_pf *pf)
7531 {
7532         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7533         struct rte_eth_rss_conf rss_conf;
7534         uint32_t i, lut = 0;
7535         uint16_t j, num;
7536
7537         /*
7538          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7539          * It's necessary to calculate the actual PF queues that are configured.
7540          */
7541         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7542                 num = i40e_pf_calc_configured_queues_num(pf);
7543         else
7544                 num = pf->dev_data->nb_rx_queues;
7545
7546         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7547         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7548                         num);
7549
7550         if (num == 0) {
7551                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7552                 return -ENOTSUP;
7553         }
7554
7555         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7556                 if (j == num)
7557                         j = 0;
7558                 lut = (lut << 8) | (j & ((0x1 <<
7559                         hw->func_caps.rss_table_entry_width) - 1));
7560                 if ((i & 3) == 3)
7561                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7562         }
7563
7564         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7565         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7566                 i40e_pf_disable_rss(pf);
7567                 return 0;
7568         }
7569         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7570                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7571                 /* Random default keys */
7572                 static uint32_t rss_key_default[] = {0x6b793944,
7573                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7574                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7575                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7576
7577                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7578                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7579                                                         sizeof(uint32_t);
7580         }
7581
7582         return i40e_hw_rss_hash_set(pf, &rss_conf);
7583 }
7584
7585 static int
7586 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7587                                struct rte_eth_tunnel_filter_conf *filter)
7588 {
7589         if (pf == NULL || filter == NULL) {
7590                 PMD_DRV_LOG(ERR, "Invalid parameter");
7591                 return -EINVAL;
7592         }
7593
7594         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7595                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7596                 return -EINVAL;
7597         }
7598
7599         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7600                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7601                 return -EINVAL;
7602         }
7603
7604         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7605                 (is_zero_ether_addr(&filter->outer_mac))) {
7606                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7607                 return -EINVAL;
7608         }
7609
7610         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7611                 (is_zero_ether_addr(&filter->inner_mac))) {
7612                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7613                 return -EINVAL;
7614         }
7615
7616         return 0;
7617 }
7618
7619 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7620 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7621 static int
7622 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7623 {
7624         uint32_t val, reg;
7625         int ret = -EINVAL;
7626
7627         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7628         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7629
7630         if (len == 3) {
7631                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7632         } else if (len == 4) {
7633                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7634         } else {
7635                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7636                 return ret;
7637         }
7638
7639         if (reg != val) {
7640                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7641                                                    reg, NULL);
7642                 if (ret != 0)
7643                         return ret;
7644         } else {
7645                 ret = 0;
7646         }
7647         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7648                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7649
7650         return ret;
7651 }
7652
7653 static int
7654 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7655 {
7656         int ret = -EINVAL;
7657
7658         if (!hw || !cfg)
7659                 return -EINVAL;
7660
7661         switch (cfg->cfg_type) {
7662         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7663                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7664                 break;
7665         default:
7666                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7667                 break;
7668         }
7669
7670         return ret;
7671 }
7672
7673 static int
7674 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7675                                enum rte_filter_op filter_op,
7676                                void *arg)
7677 {
7678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7679         int ret = I40E_ERR_PARAM;
7680
7681         switch (filter_op) {
7682         case RTE_ETH_FILTER_SET:
7683                 ret = i40e_dev_global_config_set(hw,
7684                         (struct rte_eth_global_cfg *)arg);
7685                 break;
7686         default:
7687                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7688                 break;
7689         }
7690
7691         return ret;
7692 }
7693
7694 static int
7695 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7696                           enum rte_filter_op filter_op,
7697                           void *arg)
7698 {
7699         struct rte_eth_tunnel_filter_conf *filter;
7700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7701         int ret = I40E_SUCCESS;
7702
7703         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7704
7705         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7706                 return I40E_ERR_PARAM;
7707
7708         switch (filter_op) {
7709         case RTE_ETH_FILTER_NOP:
7710                 if (!(pf->flags & I40E_FLAG_VXLAN))
7711                         ret = I40E_NOT_SUPPORTED;
7712                 break;
7713         case RTE_ETH_FILTER_ADD:
7714                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7715                 break;
7716         case RTE_ETH_FILTER_DELETE:
7717                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7718                 break;
7719         default:
7720                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7721                 ret = I40E_ERR_PARAM;
7722                 break;
7723         }
7724
7725         return ret;
7726 }
7727
7728 static int
7729 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7730 {
7731         int ret = 0;
7732         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7733
7734         /* RSS setup */
7735         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7736                 ret = i40e_pf_config_rss(pf);
7737         else
7738                 i40e_pf_disable_rss(pf);
7739
7740         return ret;
7741 }
7742
7743 /* Get the symmetric hash enable configurations per port */
7744 static void
7745 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7746 {
7747         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7748
7749         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7750 }
7751
7752 /* Set the symmetric hash enable configurations per port */
7753 static void
7754 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7755 {
7756         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7757
7758         if (enable > 0) {
7759                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7760                         PMD_DRV_LOG(INFO,
7761                                 "Symmetric hash has already been enabled");
7762                         return;
7763                 }
7764                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7765         } else {
7766                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7767                         PMD_DRV_LOG(INFO,
7768                                 "Symmetric hash has already been disabled");
7769                         return;
7770                 }
7771                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7772         }
7773         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7774         I40E_WRITE_FLUSH(hw);
7775 }
7776
7777 /*
7778  * Get global configurations of hash function type and symmetric hash enable
7779  * per flow type (pctype). Note that global configuration means it affects all
7780  * the ports on the same NIC.
7781  */
7782 static int
7783 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7784                                    struct rte_eth_hash_global_conf *g_cfg)
7785 {
7786         uint32_t reg, mask = I40E_FLOW_TYPES;
7787         uint16_t i;
7788         enum i40e_filter_pctype pctype;
7789
7790         memset(g_cfg, 0, sizeof(*g_cfg));
7791         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7792         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7793                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7794         else
7795                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7796         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7797                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7798
7799         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7800                 if (!(mask & (1UL << i)))
7801                         continue;
7802                 mask &= ~(1UL << i);
7803                 /* Bit set indicats the coresponding flow type is supported */
7804                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7805                 /* if flowtype is invalid, continue */
7806                 if (!I40E_VALID_FLOW(i))
7807                         continue;
7808                 pctype = i40e_flowtype_to_pctype(i);
7809                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7810                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7811                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7812         }
7813
7814         return 0;
7815 }
7816
7817 static int
7818 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7819 {
7820         uint32_t i;
7821         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7822
7823         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7824                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7825                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7826                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7827                                                 g_cfg->hash_func);
7828                 return -EINVAL;
7829         }
7830
7831         /*
7832          * As i40e supports less than 32 flow types, only first 32 bits need to
7833          * be checked.
7834          */
7835         mask0 = g_cfg->valid_bit_mask[0];
7836         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7837                 if (i == 0) {
7838                         /* Check if any unsupported flow type configured */
7839                         if ((mask0 | i40e_mask) ^ i40e_mask)
7840                                 goto mask_err;
7841                 } else {
7842                         if (g_cfg->valid_bit_mask[i])
7843                                 goto mask_err;
7844                 }
7845         }
7846
7847         return 0;
7848
7849 mask_err:
7850         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7851
7852         return -EINVAL;
7853 }
7854
7855 /*
7856  * Set global configurations of hash function type and symmetric hash enable
7857  * per flow type (pctype). Note any modifying global configuration will affect
7858  * all the ports on the same NIC.
7859  */
7860 static int
7861 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7862                                    struct rte_eth_hash_global_conf *g_cfg)
7863 {
7864         int ret;
7865         uint16_t i;
7866         uint32_t reg;
7867         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7868         enum i40e_filter_pctype pctype;
7869
7870         /* Check the input parameters */
7871         ret = i40e_hash_global_config_check(g_cfg);
7872         if (ret < 0)
7873                 return ret;
7874
7875         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7876                 if (!(mask0 & (1UL << i)))
7877                         continue;
7878                 mask0 &= ~(1UL << i);
7879                 /* if flowtype is invalid, continue */
7880                 if (!I40E_VALID_FLOW(i))
7881                         continue;
7882                 pctype = i40e_flowtype_to_pctype(i);
7883                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7884                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7885                 if (hw->mac.type == I40E_MAC_X722) {
7886                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7887                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7888                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7889                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7890                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7891                                   reg);
7892                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7893                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7894                                   reg);
7895                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7896                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7897                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7898                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7899                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7900                                   reg);
7901                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7902                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7903                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7904                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7905                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7906                                   reg);
7907                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7908                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7909                                   reg);
7910                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7911                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7912                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7913                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7914                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7915                                   reg);
7916                         } else {
7917                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7918                                   reg);
7919                         }
7920                 } else {
7921                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7922                 }
7923         }
7924
7925         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7926         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7927                 /* Toeplitz */
7928                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7929                         PMD_DRV_LOG(DEBUG,
7930                                 "Hash function already set to Toeplitz");
7931                         goto out;
7932                 }
7933                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7934         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7935                 /* Simple XOR */
7936                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7937                         PMD_DRV_LOG(DEBUG,
7938                                 "Hash function already set to Simple XOR");
7939                         goto out;
7940                 }
7941                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7942         } else
7943                 /* Use the default, and keep it as it is */
7944                 goto out;
7945
7946         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7947
7948 out:
7949         I40E_WRITE_FLUSH(hw);
7950
7951         return 0;
7952 }
7953
7954 /**
7955  * Valid input sets for hash and flow director filters per PCTYPE
7956  */
7957 static uint64_t
7958 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7959                 enum rte_filter_type filter)
7960 {
7961         uint64_t valid;
7962
7963         static const uint64_t valid_hash_inset_table[] = {
7964                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7965                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7966                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7967                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7968                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7969                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7970                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7971                         I40E_INSET_FLEX_PAYLOAD,
7972                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7973                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7974                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7975                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7976                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7977                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7978                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7979                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7980                         I40E_INSET_FLEX_PAYLOAD,
7981                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7982                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7983                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7984                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7985                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7986                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7987                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7988                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7989                         I40E_INSET_FLEX_PAYLOAD,
7990                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7991                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7992                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7993                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7994                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7995                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7996                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7997                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7998                         I40E_INSET_FLEX_PAYLOAD,
7999                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8000                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8001                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8002                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8003                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8004                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8005                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8006                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8007                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8008                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8009                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8010                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8011                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8012                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8013                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8014                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8015                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8016                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8017                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8018                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8019                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8020                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8021                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8022                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8023                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8024                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8025                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8026                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8027                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8028                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8029                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8030                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8031                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8032                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8033                         I40E_INSET_FLEX_PAYLOAD,
8034                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8035                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8036                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8037                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8038                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8039                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8040                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8041                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8042                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8043                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8044                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8045                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8046                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8047                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8048                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8049                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8050                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8051                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8052                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8053                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8054                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8055                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8056                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8057                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8058                         I40E_INSET_FLEX_PAYLOAD,
8059                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8060                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8061                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8062                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8063                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8064                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8065                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8066                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8067                         I40E_INSET_FLEX_PAYLOAD,
8068                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8069                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8070                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8071                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8072                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8073                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8074                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8075                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8076                         I40E_INSET_FLEX_PAYLOAD,
8077                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8078                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8079                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8080                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8081                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8082                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8083                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8084                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8085                         I40E_INSET_FLEX_PAYLOAD,
8086                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8087                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8088                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8089                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8090                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8091                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8092                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8093                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8094                         I40E_INSET_FLEX_PAYLOAD,
8095                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8096                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8097                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8098                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8099                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8100                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8101                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8102                         I40E_INSET_FLEX_PAYLOAD,
8103                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8104                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8105                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8106                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8107                         I40E_INSET_FLEX_PAYLOAD,
8108         };
8109
8110         /**
8111          * Flow director supports only fields defined in
8112          * union rte_eth_fdir_flow.
8113          */
8114         static const uint64_t valid_fdir_inset_table[] = {
8115                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8116                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8117                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8118                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8119                 I40E_INSET_IPV4_TTL,
8120                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8121                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8122                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8123                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8124                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8125                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8126                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8127                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8128                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8129                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8130                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8131                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8132                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8133                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8134                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8135                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8136                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8137                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8138                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8139                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8140                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8141                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8142                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8143                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8144                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8145                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8146                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8147                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8148                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8149                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8150                 I40E_INSET_SCTP_VT,
8151                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8152                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8153                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8154                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8155                 I40E_INSET_IPV4_TTL,
8156                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8157                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8158                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8159                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8160                 I40E_INSET_IPV6_HOP_LIMIT,
8161                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8162                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8163                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8164                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8165                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8166                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8167                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8168                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8169                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8170                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8171                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8172                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8173                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8174                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8175                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8176                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8177                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8178                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8179                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8180                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8181                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8182                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8183                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8184                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8185                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8186                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8187                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8188                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8189                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8190                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8191                 I40E_INSET_SCTP_VT,
8192                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8193                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8194                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8195                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8196                 I40E_INSET_IPV6_HOP_LIMIT,
8197                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8198                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8199                 I40E_INSET_LAST_ETHER_TYPE,
8200         };
8201
8202         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8203                 return 0;
8204         if (filter == RTE_ETH_FILTER_HASH)
8205                 valid = valid_hash_inset_table[pctype];
8206         else
8207                 valid = valid_fdir_inset_table[pctype];
8208
8209         return valid;
8210 }
8211
8212 /**
8213  * Validate if the input set is allowed for a specific PCTYPE
8214  */
8215 int
8216 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8217                 enum rte_filter_type filter, uint64_t inset)
8218 {
8219         uint64_t valid;
8220
8221         valid = i40e_get_valid_input_set(pctype, filter);
8222         if (inset & (~valid))
8223                 return -EINVAL;
8224
8225         return 0;
8226 }
8227
8228 /* default input set fields combination per pctype */
8229 uint64_t
8230 i40e_get_default_input_set(uint16_t pctype)
8231 {
8232         static const uint64_t default_inset_table[] = {
8233                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8234                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8235                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8236                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8237                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8238                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8239                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8240                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8241                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8242                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8243                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8244                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8245                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8246                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8247                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8248                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8249                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8250                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8251                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8252                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8253                         I40E_INSET_SCTP_VT,
8254                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8255                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8256                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8257                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8258                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8259                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8260                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8261                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8262                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8263                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8264                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8265                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8266                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8267                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8268                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8269                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8270                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8271                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8272                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8273                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8274                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8275                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8276                         I40E_INSET_SCTP_VT,
8277                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8278                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8279                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8280                         I40E_INSET_LAST_ETHER_TYPE,
8281         };
8282
8283         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8284                 return 0;
8285
8286         return default_inset_table[pctype];
8287 }
8288
8289 /**
8290  * Parse the input set from index to logical bit masks
8291  */
8292 static int
8293 i40e_parse_input_set(uint64_t *inset,
8294                      enum i40e_filter_pctype pctype,
8295                      enum rte_eth_input_set_field *field,
8296                      uint16_t size)
8297 {
8298         uint16_t i, j;
8299         int ret = -EINVAL;
8300
8301         static const struct {
8302                 enum rte_eth_input_set_field field;
8303                 uint64_t inset;
8304         } inset_convert_table[] = {
8305                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8306                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8307                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8308                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8309                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8310                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8311                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8312                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8313                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8314                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8315                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8316                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8317                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8318                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8319                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8320                         I40E_INSET_IPV6_NEXT_HDR},
8321                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8322                         I40E_INSET_IPV6_HOP_LIMIT},
8323                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8324                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8325                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8326                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8327                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8328                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8329                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8330                         I40E_INSET_SCTP_VT},
8331                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8332                         I40E_INSET_TUNNEL_DMAC},
8333                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8334                         I40E_INSET_VLAN_TUNNEL},
8335                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8336                         I40E_INSET_TUNNEL_ID},
8337                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8338                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8339                         I40E_INSET_FLEX_PAYLOAD_W1},
8340                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8341                         I40E_INSET_FLEX_PAYLOAD_W2},
8342                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8343                         I40E_INSET_FLEX_PAYLOAD_W3},
8344                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8345                         I40E_INSET_FLEX_PAYLOAD_W4},
8346                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8347                         I40E_INSET_FLEX_PAYLOAD_W5},
8348                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8349                         I40E_INSET_FLEX_PAYLOAD_W6},
8350                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8351                         I40E_INSET_FLEX_PAYLOAD_W7},
8352                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8353                         I40E_INSET_FLEX_PAYLOAD_W8},
8354         };
8355
8356         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8357                 return ret;
8358
8359         /* Only one item allowed for default or all */
8360         if (size == 1) {
8361                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8362                         *inset = i40e_get_default_input_set(pctype);
8363                         return 0;
8364                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8365                         *inset = I40E_INSET_NONE;
8366                         return 0;
8367                 }
8368         }
8369
8370         for (i = 0, *inset = 0; i < size; i++) {
8371                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8372                         if (field[i] == inset_convert_table[j].field) {
8373                                 *inset |= inset_convert_table[j].inset;
8374                                 break;
8375                         }
8376                 }
8377
8378                 /* It contains unsupported input set, return immediately */
8379                 if (j == RTE_DIM(inset_convert_table))
8380                         return ret;
8381         }
8382
8383         return 0;
8384 }
8385
8386 /**
8387  * Translate the input set from bit masks to register aware bit masks
8388  * and vice versa
8389  */
8390 uint64_t
8391 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8392 {
8393         uint64_t val = 0;
8394         uint16_t i;
8395
8396         struct inset_map {
8397                 uint64_t inset;
8398                 uint64_t inset_reg;
8399         };
8400
8401         static const struct inset_map inset_map_common[] = {
8402                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8403                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8404                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8405                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8406                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8407                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8408                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8409                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8410                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8411                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8412                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8413                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8414                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8415                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8416                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8417                 {I40E_INSET_TUNNEL_DMAC,
8418                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8419                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8420                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8421                 {I40E_INSET_TUNNEL_SRC_PORT,
8422                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8423                 {I40E_INSET_TUNNEL_DST_PORT,
8424                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8425                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8426                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8427                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8428                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8429                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8430                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8431                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8432                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8433                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8434         };
8435
8436     /* some different registers map in x722*/
8437         static const struct inset_map inset_map_diff_x722[] = {
8438                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8439                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8440                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8441                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8442         };
8443
8444         static const struct inset_map inset_map_diff_not_x722[] = {
8445                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8446                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8447                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8448                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8449         };
8450
8451         if (input == 0)
8452                 return val;
8453
8454         /* Translate input set to register aware inset */
8455         if (type == I40E_MAC_X722) {
8456                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8457                         if (input & inset_map_diff_x722[i].inset)
8458                                 val |= inset_map_diff_x722[i].inset_reg;
8459                 }
8460         } else {
8461                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8462                         if (input & inset_map_diff_not_x722[i].inset)
8463                                 val |= inset_map_diff_not_x722[i].inset_reg;
8464                 }
8465         }
8466
8467         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8468                 if (input & inset_map_common[i].inset)
8469                         val |= inset_map_common[i].inset_reg;
8470         }
8471
8472         return val;
8473 }
8474
8475 int
8476 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8477 {
8478         uint8_t i, idx = 0;
8479         uint64_t inset_need_mask = inset;
8480
8481         static const struct {
8482                 uint64_t inset;
8483                 uint32_t mask;
8484         } inset_mask_map[] = {
8485                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8486                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8487                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8488                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8489                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8490                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8491                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8492                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8493         };
8494
8495         if (!inset || !mask || !nb_elem)
8496                 return 0;
8497
8498         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8499                 /* Clear the inset bit, if no MASK is required,
8500                  * for example proto + ttl
8501                  */
8502                 if ((inset & inset_mask_map[i].inset) ==
8503                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8504                         inset_need_mask &= ~inset_mask_map[i].inset;
8505                 if (!inset_need_mask)
8506                         return 0;
8507         }
8508         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8509                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8510                     inset_mask_map[i].inset) {
8511                         if (idx >= nb_elem) {
8512                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8513                                 return -EINVAL;
8514                         }
8515                         mask[idx] = inset_mask_map[i].mask;
8516                         idx++;
8517                 }
8518         }
8519
8520         return idx;
8521 }
8522
8523 void
8524 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8525 {
8526         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8527
8528         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8529         if (reg != val)
8530                 i40e_write_rx_ctl(hw, addr, val);
8531         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8532                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8533 }
8534
8535 static void
8536 i40e_filter_input_set_init(struct i40e_pf *pf)
8537 {
8538         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8539         enum i40e_filter_pctype pctype;
8540         uint64_t input_set, inset_reg;
8541         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8542         int num, i;
8543
8544         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8545              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8546                 if (hw->mac.type == I40E_MAC_X722) {
8547                         if (!I40E_VALID_PCTYPE_X722(pctype))
8548                                 continue;
8549                 } else {
8550                         if (!I40E_VALID_PCTYPE(pctype))
8551                                 continue;
8552                 }
8553
8554                 input_set = i40e_get_default_input_set(pctype);
8555
8556                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8557                                                    I40E_INSET_MASK_NUM_REG);
8558                 if (num < 0)
8559                         return;
8560                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8561                                         input_set);
8562
8563                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8564                                       (uint32_t)(inset_reg & UINT32_MAX));
8565                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8566                                      (uint32_t)((inset_reg >>
8567                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8568                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8569                                       (uint32_t)(inset_reg & UINT32_MAX));
8570                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8571                                      (uint32_t)((inset_reg >>
8572                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8573
8574                 for (i = 0; i < num; i++) {
8575                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8576                                              mask_reg[i]);
8577                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8578                                              mask_reg[i]);
8579                 }
8580                 /*clear unused mask registers of the pctype */
8581                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8582                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8583                                              0);
8584                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8585                                              0);
8586                 }
8587                 I40E_WRITE_FLUSH(hw);
8588
8589                 /* store the default input set */
8590                 pf->hash_input_set[pctype] = input_set;
8591                 pf->fdir.input_set[pctype] = input_set;
8592         }
8593 }
8594
8595 int
8596 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8597                          struct rte_eth_input_set_conf *conf)
8598 {
8599         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8600         enum i40e_filter_pctype pctype;
8601         uint64_t input_set, inset_reg = 0;
8602         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8603         int ret, i, num;
8604
8605         if (!conf) {
8606                 PMD_DRV_LOG(ERR, "Invalid pointer");
8607                 return -EFAULT;
8608         }
8609         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8610             conf->op != RTE_ETH_INPUT_SET_ADD) {
8611                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8612                 return -EINVAL;
8613         }
8614
8615         if (!I40E_VALID_FLOW(conf->flow_type)) {
8616                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8617                 return -EINVAL;
8618         }
8619
8620         if (hw->mac.type == I40E_MAC_X722) {
8621                 /* get translated pctype value in fd pctype register */
8622                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8623                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8624                         conf->flow_type)));
8625         } else
8626                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8627
8628         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8629                                    conf->inset_size);
8630         if (ret) {
8631                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8632                 return -EINVAL;
8633         }
8634         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8635                                     input_set) != 0) {
8636                 PMD_DRV_LOG(ERR, "Invalid input set");
8637                 return -EINVAL;
8638         }
8639         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8640                 /* get inset value in register */
8641                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8642                 inset_reg <<= I40E_32_BIT_WIDTH;
8643                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8644                 input_set |= pf->hash_input_set[pctype];
8645         }
8646         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8647                                            I40E_INSET_MASK_NUM_REG);
8648         if (num < 0)
8649                 return -EINVAL;
8650
8651         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8652
8653         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8654                               (uint32_t)(inset_reg & UINT32_MAX));
8655         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8656                              (uint32_t)((inset_reg >>
8657                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8658
8659         for (i = 0; i < num; i++)
8660                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8661                                      mask_reg[i]);
8662         /*clear unused mask registers of the pctype */
8663         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8664                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8665                                      0);
8666         I40E_WRITE_FLUSH(hw);
8667
8668         pf->hash_input_set[pctype] = input_set;
8669         return 0;
8670 }
8671
8672 int
8673 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8674                          struct rte_eth_input_set_conf *conf)
8675 {
8676         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8677         enum i40e_filter_pctype pctype;
8678         uint64_t input_set, inset_reg = 0;
8679         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8680         int ret, i, num;
8681
8682         if (!hw || !conf) {
8683                 PMD_DRV_LOG(ERR, "Invalid pointer");
8684                 return -EFAULT;
8685         }
8686         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8687             conf->op != RTE_ETH_INPUT_SET_ADD) {
8688                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8689                 return -EINVAL;
8690         }
8691
8692         if (!I40E_VALID_FLOW(conf->flow_type)) {
8693                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8694                 return -EINVAL;
8695         }
8696
8697         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8698
8699         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8700                                    conf->inset_size);
8701         if (ret) {
8702                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8703                 return -EINVAL;
8704         }
8705         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8706                                     input_set) != 0) {
8707                 PMD_DRV_LOG(ERR, "Invalid input set");
8708                 return -EINVAL;
8709         }
8710
8711         /* get inset value in register */
8712         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8713         inset_reg <<= I40E_32_BIT_WIDTH;
8714         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8715
8716         /* Can not change the inset reg for flex payload for fdir,
8717          * it is done by writing I40E_PRTQF_FD_FLXINSET
8718          * in i40e_set_flex_mask_on_pctype.
8719          */
8720         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8721                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8722         else
8723                 input_set |= pf->fdir.input_set[pctype];
8724         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8725                                            I40E_INSET_MASK_NUM_REG);
8726         if (num < 0)
8727                 return -EINVAL;
8728
8729         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8730
8731         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8732                               (uint32_t)(inset_reg & UINT32_MAX));
8733         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8734                              (uint32_t)((inset_reg >>
8735                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8736
8737         for (i = 0; i < num; i++)
8738                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8739                                      mask_reg[i]);
8740         /*clear unused mask registers of the pctype */
8741         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8742                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8743                                      0);
8744         I40E_WRITE_FLUSH(hw);
8745
8746         pf->fdir.input_set[pctype] = input_set;
8747         return 0;
8748 }
8749
8750 static int
8751 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8752 {
8753         int ret = 0;
8754
8755         if (!hw || !info) {
8756                 PMD_DRV_LOG(ERR, "Invalid pointer");
8757                 return -EFAULT;
8758         }
8759
8760         switch (info->info_type) {
8761         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8762                 i40e_get_symmetric_hash_enable_per_port(hw,
8763                                         &(info->info.enable));
8764                 break;
8765         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8766                 ret = i40e_get_hash_filter_global_config(hw,
8767                                 &(info->info.global_conf));
8768                 break;
8769         default:
8770                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8771                                                         info->info_type);
8772                 ret = -EINVAL;
8773                 break;
8774         }
8775
8776         return ret;
8777 }
8778
8779 static int
8780 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8781 {
8782         int ret = 0;
8783
8784         if (!hw || !info) {
8785                 PMD_DRV_LOG(ERR, "Invalid pointer");
8786                 return -EFAULT;
8787         }
8788
8789         switch (info->info_type) {
8790         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8791                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8792                 break;
8793         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8794                 ret = i40e_set_hash_filter_global_config(hw,
8795                                 &(info->info.global_conf));
8796                 break;
8797         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8798                 ret = i40e_hash_filter_inset_select(hw,
8799                                                &(info->info.input_set_conf));
8800                 break;
8801
8802         default:
8803                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8804                                                         info->info_type);
8805                 ret = -EINVAL;
8806                 break;
8807         }
8808
8809         return ret;
8810 }
8811
8812 /* Operations for hash function */
8813 static int
8814 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8815                       enum rte_filter_op filter_op,
8816                       void *arg)
8817 {
8818         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8819         int ret = 0;
8820
8821         switch (filter_op) {
8822         case RTE_ETH_FILTER_NOP:
8823                 break;
8824         case RTE_ETH_FILTER_GET:
8825                 ret = i40e_hash_filter_get(hw,
8826                         (struct rte_eth_hash_filter_info *)arg);
8827                 break;
8828         case RTE_ETH_FILTER_SET:
8829                 ret = i40e_hash_filter_set(hw,
8830                         (struct rte_eth_hash_filter_info *)arg);
8831                 break;
8832         default:
8833                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8834                                                                 filter_op);
8835                 ret = -ENOTSUP;
8836                 break;
8837         }
8838
8839         return ret;
8840 }
8841
8842 /* Convert ethertype filter structure */
8843 static int
8844 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8845                               struct i40e_ethertype_filter *filter)
8846 {
8847         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8848         filter->input.ether_type = input->ether_type;
8849         filter->flags = input->flags;
8850         filter->queue = input->queue;
8851
8852         return 0;
8853 }
8854
8855 /* Check if there exists the ehtertype filter */
8856 struct i40e_ethertype_filter *
8857 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8858                                 const struct i40e_ethertype_filter_input *input)
8859 {
8860         int ret;
8861
8862         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8863         if (ret < 0)
8864                 return NULL;
8865
8866         return ethertype_rule->hash_map[ret];
8867 }
8868
8869 /* Add ethertype filter in SW list */
8870 static int
8871 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8872                                 struct i40e_ethertype_filter *filter)
8873 {
8874         struct i40e_ethertype_rule *rule = &pf->ethertype;
8875         int ret;
8876
8877         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8878         if (ret < 0) {
8879                 PMD_DRV_LOG(ERR,
8880                             "Failed to insert ethertype filter"
8881                             " to hash table %d!",
8882                             ret);
8883                 return ret;
8884         }
8885         rule->hash_map[ret] = filter;
8886
8887         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8888
8889         return 0;
8890 }
8891
8892 /* Delete ethertype filter in SW list */
8893 int
8894 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8895                              struct i40e_ethertype_filter_input *input)
8896 {
8897         struct i40e_ethertype_rule *rule = &pf->ethertype;
8898         struct i40e_ethertype_filter *filter;
8899         int ret;
8900
8901         ret = rte_hash_del_key(rule->hash_table, input);
8902         if (ret < 0) {
8903                 PMD_DRV_LOG(ERR,
8904                             "Failed to delete ethertype filter"
8905                             " to hash table %d!",
8906                             ret);
8907                 return ret;
8908         }
8909         filter = rule->hash_map[ret];
8910         rule->hash_map[ret] = NULL;
8911
8912         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8913         rte_free(filter);
8914
8915         return 0;
8916 }
8917
8918 /*
8919  * Configure ethertype filter, which can director packet by filtering
8920  * with mac address and ether_type or only ether_type
8921  */
8922 int
8923 i40e_ethertype_filter_set(struct i40e_pf *pf,
8924                         struct rte_eth_ethertype_filter *filter,
8925                         bool add)
8926 {
8927         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8928         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8929         struct i40e_ethertype_filter *ethertype_filter, *node;
8930         struct i40e_ethertype_filter check_filter;
8931         struct i40e_control_filter_stats stats;
8932         uint16_t flags = 0;
8933         int ret;
8934
8935         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8936                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8937                 return -EINVAL;
8938         }
8939         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8940                 filter->ether_type == ETHER_TYPE_IPv6) {
8941                 PMD_DRV_LOG(ERR,
8942                         "unsupported ether_type(0x%04x) in control packet filter.",
8943                         filter->ether_type);
8944                 return -EINVAL;
8945         }
8946         if (filter->ether_type == ETHER_TYPE_VLAN)
8947                 PMD_DRV_LOG(WARNING,
8948                         "filter vlan ether_type in first tag is not supported.");
8949
8950         /* Check if there is the filter in SW list */
8951         memset(&check_filter, 0, sizeof(check_filter));
8952         i40e_ethertype_filter_convert(filter, &check_filter);
8953         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8954                                                &check_filter.input);
8955         if (add && node) {
8956                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8957                 return -EINVAL;
8958         }
8959
8960         if (!add && !node) {
8961                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8962                 return -EINVAL;
8963         }
8964
8965         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8966                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8967         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8968                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8969         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8970
8971         memset(&stats, 0, sizeof(stats));
8972         ret = i40e_aq_add_rem_control_packet_filter(hw,
8973                         filter->mac_addr.addr_bytes,
8974                         filter->ether_type, flags,
8975                         pf->main_vsi->seid,
8976                         filter->queue, add, &stats, NULL);
8977
8978         PMD_DRV_LOG(INFO,
8979                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8980                 ret, stats.mac_etype_used, stats.etype_used,
8981                 stats.mac_etype_free, stats.etype_free);
8982         if (ret < 0)
8983                 return -ENOSYS;
8984
8985         /* Add or delete a filter in SW list */
8986         if (add) {
8987                 ethertype_filter = rte_zmalloc("ethertype_filter",
8988                                        sizeof(*ethertype_filter), 0);
8989                 rte_memcpy(ethertype_filter, &check_filter,
8990                            sizeof(check_filter));
8991                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8992         } else {
8993                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8994         }
8995
8996         return ret;
8997 }
8998
8999 /*
9000  * Handle operations for ethertype filter.
9001  */
9002 static int
9003 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9004                                 enum rte_filter_op filter_op,
9005                                 void *arg)
9006 {
9007         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9008         int ret = 0;
9009
9010         if (filter_op == RTE_ETH_FILTER_NOP)
9011                 return ret;
9012
9013         if (arg == NULL) {
9014                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9015                             filter_op);
9016                 return -EINVAL;
9017         }
9018
9019         switch (filter_op) {
9020         case RTE_ETH_FILTER_ADD:
9021                 ret = i40e_ethertype_filter_set(pf,
9022                         (struct rte_eth_ethertype_filter *)arg,
9023                         TRUE);
9024                 break;
9025         case RTE_ETH_FILTER_DELETE:
9026                 ret = i40e_ethertype_filter_set(pf,
9027                         (struct rte_eth_ethertype_filter *)arg,
9028                         FALSE);
9029                 break;
9030         default:
9031                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9032                 ret = -ENOSYS;
9033                 break;
9034         }
9035         return ret;
9036 }
9037
9038 static int
9039 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9040                      enum rte_filter_type filter_type,
9041                      enum rte_filter_op filter_op,
9042                      void *arg)
9043 {
9044         int ret = 0;
9045
9046         if (dev == NULL)
9047                 return -EINVAL;
9048
9049         switch (filter_type) {
9050         case RTE_ETH_FILTER_NONE:
9051                 /* For global configuration */
9052                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9053                 break;
9054         case RTE_ETH_FILTER_HASH:
9055                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9056                 break;
9057         case RTE_ETH_FILTER_MACVLAN:
9058                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9059                 break;
9060         case RTE_ETH_FILTER_ETHERTYPE:
9061                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9062                 break;
9063         case RTE_ETH_FILTER_TUNNEL:
9064                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9065                 break;
9066         case RTE_ETH_FILTER_FDIR:
9067                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9068                 break;
9069         case RTE_ETH_FILTER_GENERIC:
9070                 if (filter_op != RTE_ETH_FILTER_GET)
9071                         return -EINVAL;
9072                 *(const void **)arg = &i40e_flow_ops;
9073                 break;
9074         default:
9075                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9076                                                         filter_type);
9077                 ret = -EINVAL;
9078                 break;
9079         }
9080
9081         return ret;
9082 }
9083
9084 /*
9085  * Check and enable Extended Tag.
9086  * Enabling Extended Tag is important for 40G performance.
9087  */
9088 static void
9089 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9090 {
9091         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9092         uint32_t buf = 0;
9093         int ret;
9094
9095         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9096                                       PCI_DEV_CAP_REG);
9097         if (ret < 0) {
9098                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9099                             PCI_DEV_CAP_REG);
9100                 return;
9101         }
9102         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9103                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9104                 return;
9105         }
9106
9107         buf = 0;
9108         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9109                                       PCI_DEV_CTRL_REG);
9110         if (ret < 0) {
9111                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9112                             PCI_DEV_CTRL_REG);
9113                 return;
9114         }
9115         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9116                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9117                 return;
9118         }
9119         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9120         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9121                                        PCI_DEV_CTRL_REG);
9122         if (ret < 0) {
9123                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9124                             PCI_DEV_CTRL_REG);
9125                 return;
9126         }
9127 }
9128
9129 /*
9130  * As some registers wouldn't be reset unless a global hardware reset,
9131  * hardware initialization is needed to put those registers into an
9132  * expected initial state.
9133  */
9134 static void
9135 i40e_hw_init(struct rte_eth_dev *dev)
9136 {
9137         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9138
9139         i40e_enable_extended_tag(dev);
9140
9141         /* clear the PF Queue Filter control register */
9142         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9143
9144         /* Disable symmetric hash per port */
9145         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9146 }
9147
9148 enum i40e_filter_pctype
9149 i40e_flowtype_to_pctype(uint16_t flow_type)
9150 {
9151         static const enum i40e_filter_pctype pctype_table[] = {
9152                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9153                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9154                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9155                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9156                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9157                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9158                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9159                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9160                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9161                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9162                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9163                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9164                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9165                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9166                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9167                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9168                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9169                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9170                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9171         };
9172
9173         return pctype_table[flow_type];
9174 }
9175
9176 uint16_t
9177 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9178 {
9179         static const uint16_t flowtype_table[] = {
9180                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9181                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9182                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9183                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9184                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9185                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9186                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9187                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9188                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9189                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9190                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9191                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9192                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9193                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9194                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9195                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9196                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9197                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9198                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9199                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9200                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9201                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9202                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9203                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9204                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9205                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9206                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9207                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9208                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9209                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9210                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9211         };
9212
9213         return flowtype_table[pctype];
9214 }
9215
9216 /*
9217  * On X710, performance number is far from the expectation on recent firmware
9218  * versions; on XL710, performance number is also far from the expectation on
9219  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9220  * mode is enabled and port MAC address is equal to the packet destination MAC
9221  * address. The fix for this issue may not be integrated in the following
9222  * firmware version. So the workaround in software driver is needed. It needs
9223  * to modify the initial values of 3 internal only registers for both X710 and
9224  * XL710. Note that the values for X710 or XL710 could be different, and the
9225  * workaround can be removed when it is fixed in firmware in the future.
9226  */
9227
9228 /* For both X710 and XL710 */
9229 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9230 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
9231
9232 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9233 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9234
9235 /* For X722 */
9236 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9237 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9238
9239 /* For X710 */
9240 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9241 /* For XL710 */
9242 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9243 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9244
9245 static int
9246 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9247 {
9248         enum i40e_status_code status;
9249         struct i40e_aq_get_phy_abilities_resp phy_ab;
9250         int ret = -ENOTSUP;
9251
9252         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9253                                               NULL);
9254
9255         if (status) {
9256                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9257                         status);
9258                 return ret;
9259         }
9260
9261         return 0;
9262 }
9263
9264 static void
9265 i40e_configure_registers(struct i40e_hw *hw)
9266 {
9267         static struct {
9268                 uint32_t addr;
9269                 uint64_t val;
9270         } reg_table[] = {
9271                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9272                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9273                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9274         };
9275         uint64_t reg;
9276         uint32_t i;
9277         int ret;
9278
9279         for (i = 0; i < RTE_DIM(reg_table); i++) {
9280                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9281                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9282                                 reg_table[i].val =
9283                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9284                         else /* For X710/XL710/XXV710 */
9285                                 reg_table[i].val =
9286                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9287                 }
9288
9289                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9290                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9291                                 reg_table[i].val =
9292                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9293                         else /* For X710/XL710/XXV710 */
9294                                 reg_table[i].val =
9295                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9296                 }
9297
9298                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9299                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9300                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9301                                 reg_table[i].val =
9302                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9303                         else /* For X710 */
9304                                 reg_table[i].val =
9305                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9306                 }
9307
9308                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9309                                                         &reg, NULL);
9310                 if (ret < 0) {
9311                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9312                                                         reg_table[i].addr);
9313                         break;
9314                 }
9315                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9316                                                 reg_table[i].addr, reg);
9317                 if (reg == reg_table[i].val)
9318                         continue;
9319
9320                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9321                                                 reg_table[i].val, NULL);
9322                 if (ret < 0) {
9323                         PMD_DRV_LOG(ERR,
9324                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9325                                 reg_table[i].val, reg_table[i].addr);
9326                         break;
9327                 }
9328                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9329                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9330         }
9331 }
9332
9333 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9334 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9335 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9336 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9337 static int
9338 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9339 {
9340         uint32_t reg;
9341         int ret;
9342
9343         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9344                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9345                 return -EINVAL;
9346         }
9347
9348         /* Configure for double VLAN RX stripping */
9349         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9350         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9351                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9352                 ret = i40e_aq_debug_write_register(hw,
9353                                                    I40E_VSI_TSR(vsi->vsi_id),
9354                                                    reg, NULL);
9355                 if (ret < 0) {
9356                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9357                                     vsi->vsi_id);
9358                         return I40E_ERR_CONFIG;
9359                 }
9360         }
9361
9362         /* Configure for double VLAN TX insertion */
9363         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9364         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9365                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9366                 ret = i40e_aq_debug_write_register(hw,
9367                                                    I40E_VSI_L2TAGSTXVALID(
9368                                                    vsi->vsi_id), reg, NULL);
9369                 if (ret < 0) {
9370                         PMD_DRV_LOG(ERR,
9371                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9372                                 vsi->vsi_id);
9373                         return I40E_ERR_CONFIG;
9374                 }
9375         }
9376
9377         return 0;
9378 }
9379
9380 /**
9381  * i40e_aq_add_mirror_rule
9382  * @hw: pointer to the hardware structure
9383  * @seid: VEB seid to add mirror rule to
9384  * @dst_id: destination vsi seid
9385  * @entries: Buffer which contains the entities to be mirrored
9386  * @count: number of entities contained in the buffer
9387  * @rule_id:the rule_id of the rule to be added
9388  *
9389  * Add a mirror rule for a given veb.
9390  *
9391  **/
9392 static enum i40e_status_code
9393 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9394                         uint16_t seid, uint16_t dst_id,
9395                         uint16_t rule_type, uint16_t *entries,
9396                         uint16_t count, uint16_t *rule_id)
9397 {
9398         struct i40e_aq_desc desc;
9399         struct i40e_aqc_add_delete_mirror_rule cmd;
9400         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9401                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9402                 &desc.params.raw;
9403         uint16_t buff_len;
9404         enum i40e_status_code status;
9405
9406         i40e_fill_default_direct_cmd_desc(&desc,
9407                                           i40e_aqc_opc_add_mirror_rule);
9408         memset(&cmd, 0, sizeof(cmd));
9409
9410         buff_len = sizeof(uint16_t) * count;
9411         desc.datalen = rte_cpu_to_le_16(buff_len);
9412         if (buff_len > 0)
9413                 desc.flags |= rte_cpu_to_le_16(
9414                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9415         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9416                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9417         cmd.num_entries = rte_cpu_to_le_16(count);
9418         cmd.seid = rte_cpu_to_le_16(seid);
9419         cmd.destination = rte_cpu_to_le_16(dst_id);
9420
9421         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9422         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9423         PMD_DRV_LOG(INFO,
9424                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9425                 hw->aq.asq_last_status, resp->rule_id,
9426                 resp->mirror_rules_used, resp->mirror_rules_free);
9427         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9428
9429         return status;
9430 }
9431
9432 /**
9433  * i40e_aq_del_mirror_rule
9434  * @hw: pointer to the hardware structure
9435  * @seid: VEB seid to add mirror rule to
9436  * @entries: Buffer which contains the entities to be mirrored
9437  * @count: number of entities contained in the buffer
9438  * @rule_id:the rule_id of the rule to be delete
9439  *
9440  * Delete a mirror rule for a given veb.
9441  *
9442  **/
9443 static enum i40e_status_code
9444 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9445                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9446                 uint16_t count, uint16_t rule_id)
9447 {
9448         struct i40e_aq_desc desc;
9449         struct i40e_aqc_add_delete_mirror_rule cmd;
9450         uint16_t buff_len = 0;
9451         enum i40e_status_code status;
9452         void *buff = NULL;
9453
9454         i40e_fill_default_direct_cmd_desc(&desc,
9455                                           i40e_aqc_opc_delete_mirror_rule);
9456         memset(&cmd, 0, sizeof(cmd));
9457         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9458                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9459                                                           I40E_AQ_FLAG_RD));
9460                 cmd.num_entries = count;
9461                 buff_len = sizeof(uint16_t) * count;
9462                 desc.datalen = rte_cpu_to_le_16(buff_len);
9463                 buff = (void *)entries;
9464         } else
9465                 /* rule id is filled in destination field for deleting mirror rule */
9466                 cmd.destination = rte_cpu_to_le_16(rule_id);
9467
9468         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9469                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9470         cmd.seid = rte_cpu_to_le_16(seid);
9471
9472         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9473         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9474
9475         return status;
9476 }
9477
9478 /**
9479  * i40e_mirror_rule_set
9480  * @dev: pointer to the hardware structure
9481  * @mirror_conf: mirror rule info
9482  * @sw_id: mirror rule's sw_id
9483  * @on: enable/disable
9484  *
9485  * set a mirror rule.
9486  *
9487  **/
9488 static int
9489 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9490                         struct rte_eth_mirror_conf *mirror_conf,
9491                         uint8_t sw_id, uint8_t on)
9492 {
9493         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9495         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9496         struct i40e_mirror_rule *parent = NULL;
9497         uint16_t seid, dst_seid, rule_id;
9498         uint16_t i, j = 0;
9499         int ret;
9500
9501         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9502
9503         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9504                 PMD_DRV_LOG(ERR,
9505                         "mirror rule can not be configured without veb or vfs.");
9506                 return -ENOSYS;
9507         }
9508         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9509                 PMD_DRV_LOG(ERR, "mirror table is full.");
9510                 return -ENOSPC;
9511         }
9512         if (mirror_conf->dst_pool > pf->vf_num) {
9513                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9514                                  mirror_conf->dst_pool);
9515                 return -EINVAL;
9516         }
9517
9518         seid = pf->main_vsi->veb->seid;
9519
9520         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9521                 if (sw_id <= it->index) {
9522                         mirr_rule = it;
9523                         break;
9524                 }
9525                 parent = it;
9526         }
9527         if (mirr_rule && sw_id == mirr_rule->index) {
9528                 if (on) {
9529                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9530                         return -EEXIST;
9531                 } else {
9532                         ret = i40e_aq_del_mirror_rule(hw, seid,
9533                                         mirr_rule->rule_type,
9534                                         mirr_rule->entries,
9535                                         mirr_rule->num_entries, mirr_rule->id);
9536                         if (ret < 0) {
9537                                 PMD_DRV_LOG(ERR,
9538                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9539                                         ret, hw->aq.asq_last_status);
9540                                 return -ENOSYS;
9541                         }
9542                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9543                         rte_free(mirr_rule);
9544                         pf->nb_mirror_rule--;
9545                         return 0;
9546                 }
9547         } else if (!on) {
9548                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9549                 return -ENOENT;
9550         }
9551
9552         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9553                                 sizeof(struct i40e_mirror_rule) , 0);
9554         if (!mirr_rule) {
9555                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9556                 return I40E_ERR_NO_MEMORY;
9557         }
9558         switch (mirror_conf->rule_type) {
9559         case ETH_MIRROR_VLAN:
9560                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9561                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9562                                 mirr_rule->entries[j] =
9563                                         mirror_conf->vlan.vlan_id[i];
9564                                 j++;
9565                         }
9566                 }
9567                 if (j == 0) {
9568                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9569                         rte_free(mirr_rule);
9570                         return -EINVAL;
9571                 }
9572                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9573                 break;
9574         case ETH_MIRROR_VIRTUAL_POOL_UP:
9575         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9576                 /* check if the specified pool bit is out of range */
9577                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9578                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9579                         rte_free(mirr_rule);
9580                         return -EINVAL;
9581                 }
9582                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9583                         if (mirror_conf->pool_mask & (1ULL << i)) {
9584                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9585                                 j++;
9586                         }
9587                 }
9588                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9589                         /* add pf vsi to entries */
9590                         mirr_rule->entries[j] = pf->main_vsi_seid;
9591                         j++;
9592                 }
9593                 if (j == 0) {
9594                         PMD_DRV_LOG(ERR, "pool is not specified.");
9595                         rte_free(mirr_rule);
9596                         return -EINVAL;
9597                 }
9598                 /* egress and ingress in aq commands means from switch but not port */
9599                 mirr_rule->rule_type =
9600                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9601                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9602                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9603                 break;
9604         case ETH_MIRROR_UPLINK_PORT:
9605                 /* egress and ingress in aq commands means from switch but not port*/
9606                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9607                 break;
9608         case ETH_MIRROR_DOWNLINK_PORT:
9609                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9610                 break;
9611         default:
9612                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9613                         mirror_conf->rule_type);
9614                 rte_free(mirr_rule);
9615                 return -EINVAL;
9616         }
9617
9618         /* If the dst_pool is equal to vf_num, consider it as PF */
9619         if (mirror_conf->dst_pool == pf->vf_num)
9620                 dst_seid = pf->main_vsi_seid;
9621         else
9622                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9623
9624         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9625                                       mirr_rule->rule_type, mirr_rule->entries,
9626                                       j, &rule_id);
9627         if (ret < 0) {
9628                 PMD_DRV_LOG(ERR,
9629                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9630                         ret, hw->aq.asq_last_status);
9631                 rte_free(mirr_rule);
9632                 return -ENOSYS;
9633         }
9634
9635         mirr_rule->index = sw_id;
9636         mirr_rule->num_entries = j;
9637         mirr_rule->id = rule_id;
9638         mirr_rule->dst_vsi_seid = dst_seid;
9639
9640         if (parent)
9641                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9642         else
9643                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9644
9645         pf->nb_mirror_rule++;
9646         return 0;
9647 }
9648
9649 /**
9650  * i40e_mirror_rule_reset
9651  * @dev: pointer to the device
9652  * @sw_id: mirror rule's sw_id
9653  *
9654  * reset a mirror rule.
9655  *
9656  **/
9657 static int
9658 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9659 {
9660         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9662         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9663         uint16_t seid;
9664         int ret;
9665
9666         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9667
9668         seid = pf->main_vsi->veb->seid;
9669
9670         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9671                 if (sw_id == it->index) {
9672                         mirr_rule = it;
9673                         break;
9674                 }
9675         }
9676         if (mirr_rule) {
9677                 ret = i40e_aq_del_mirror_rule(hw, seid,
9678                                 mirr_rule->rule_type,
9679                                 mirr_rule->entries,
9680                                 mirr_rule->num_entries, mirr_rule->id);
9681                 if (ret < 0) {
9682                         PMD_DRV_LOG(ERR,
9683                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9684                                 ret, hw->aq.asq_last_status);
9685                         return -ENOSYS;
9686                 }
9687                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9688                 rte_free(mirr_rule);
9689                 pf->nb_mirror_rule--;
9690         } else {
9691                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9692                 return -ENOENT;
9693         }
9694         return 0;
9695 }
9696
9697 static uint64_t
9698 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9699 {
9700         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9701         uint64_t systim_cycles;
9702
9703         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9704         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9705                         << 32;
9706
9707         return systim_cycles;
9708 }
9709
9710 static uint64_t
9711 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9712 {
9713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9714         uint64_t rx_tstamp;
9715
9716         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9717         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9718                         << 32;
9719
9720         return rx_tstamp;
9721 }
9722
9723 static uint64_t
9724 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9725 {
9726         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9727         uint64_t tx_tstamp;
9728
9729         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9730         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9731                         << 32;
9732
9733         return tx_tstamp;
9734 }
9735
9736 static void
9737 i40e_start_timecounters(struct rte_eth_dev *dev)
9738 {
9739         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9740         struct i40e_adapter *adapter =
9741                         (struct i40e_adapter *)dev->data->dev_private;
9742         struct rte_eth_link link;
9743         uint32_t tsync_inc_l;
9744         uint32_t tsync_inc_h;
9745
9746         /* Get current link speed. */
9747         memset(&link, 0, sizeof(link));
9748         i40e_dev_link_update(dev, 1);
9749         rte_i40e_dev_atomic_read_link_status(dev, &link);
9750
9751         switch (link.link_speed) {
9752         case ETH_SPEED_NUM_40G:
9753                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9754                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9755                 break;
9756         case ETH_SPEED_NUM_10G:
9757                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9758                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9759                 break;
9760         case ETH_SPEED_NUM_1G:
9761                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9762                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9763                 break;
9764         default:
9765                 tsync_inc_l = 0x0;
9766                 tsync_inc_h = 0x0;
9767         }
9768
9769         /* Set the timesync increment value. */
9770         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9771         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9772
9773         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9774         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9775         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9776
9777         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9778         adapter->systime_tc.cc_shift = 0;
9779         adapter->systime_tc.nsec_mask = 0;
9780
9781         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9782         adapter->rx_tstamp_tc.cc_shift = 0;
9783         adapter->rx_tstamp_tc.nsec_mask = 0;
9784
9785         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9786         adapter->tx_tstamp_tc.cc_shift = 0;
9787         adapter->tx_tstamp_tc.nsec_mask = 0;
9788 }
9789
9790 static int
9791 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9792 {
9793         struct i40e_adapter *adapter =
9794                         (struct i40e_adapter *)dev->data->dev_private;
9795
9796         adapter->systime_tc.nsec += delta;
9797         adapter->rx_tstamp_tc.nsec += delta;
9798         adapter->tx_tstamp_tc.nsec += delta;
9799
9800         return 0;
9801 }
9802
9803 static int
9804 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9805 {
9806         uint64_t ns;
9807         struct i40e_adapter *adapter =
9808                         (struct i40e_adapter *)dev->data->dev_private;
9809
9810         ns = rte_timespec_to_ns(ts);
9811
9812         /* Set the timecounters to a new value. */
9813         adapter->systime_tc.nsec = ns;
9814         adapter->rx_tstamp_tc.nsec = ns;
9815         adapter->tx_tstamp_tc.nsec = ns;
9816
9817         return 0;
9818 }
9819
9820 static int
9821 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9822 {
9823         uint64_t ns, systime_cycles;
9824         struct i40e_adapter *adapter =
9825                         (struct i40e_adapter *)dev->data->dev_private;
9826
9827         systime_cycles = i40e_read_systime_cyclecounter(dev);
9828         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9829         *ts = rte_ns_to_timespec(ns);
9830
9831         return 0;
9832 }
9833
9834 static int
9835 i40e_timesync_enable(struct rte_eth_dev *dev)
9836 {
9837         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9838         uint32_t tsync_ctl_l;
9839         uint32_t tsync_ctl_h;
9840
9841         /* Stop the timesync system time. */
9842         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9843         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9844         /* Reset the timesync system time value. */
9845         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9846         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9847
9848         i40e_start_timecounters(dev);
9849
9850         /* Clear timesync registers. */
9851         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9852         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9853         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9854         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9855         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9856         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9857
9858         /* Enable timestamping of PTP packets. */
9859         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9860         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9861
9862         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9863         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9864         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9865
9866         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9867         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9868
9869         return 0;
9870 }
9871
9872 static int
9873 i40e_timesync_disable(struct rte_eth_dev *dev)
9874 {
9875         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9876         uint32_t tsync_ctl_l;
9877         uint32_t tsync_ctl_h;
9878
9879         /* Disable timestamping of transmitted PTP packets. */
9880         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9881         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9882
9883         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9884         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9885
9886         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9887         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9888
9889         /* Reset the timesync increment value. */
9890         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9891         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9892
9893         return 0;
9894 }
9895
9896 static int
9897 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9898                                 struct timespec *timestamp, uint32_t flags)
9899 {
9900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9901         struct i40e_adapter *adapter =
9902                 (struct i40e_adapter *)dev->data->dev_private;
9903
9904         uint32_t sync_status;
9905         uint32_t index = flags & 0x03;
9906         uint64_t rx_tstamp_cycles;
9907         uint64_t ns;
9908
9909         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9910         if ((sync_status & (1 << index)) == 0)
9911                 return -EINVAL;
9912
9913         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9914         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9915         *timestamp = rte_ns_to_timespec(ns);
9916
9917         return 0;
9918 }
9919
9920 static int
9921 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9922                                 struct timespec *timestamp)
9923 {
9924         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9925         struct i40e_adapter *adapter =
9926                 (struct i40e_adapter *)dev->data->dev_private;
9927
9928         uint32_t sync_status;
9929         uint64_t tx_tstamp_cycles;
9930         uint64_t ns;
9931
9932         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9933         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9934                 return -EINVAL;
9935
9936         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9937         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9938         *timestamp = rte_ns_to_timespec(ns);
9939
9940         return 0;
9941 }
9942
9943 /*
9944  * i40e_parse_dcb_configure - parse dcb configure from user
9945  * @dev: the device being configured
9946  * @dcb_cfg: pointer of the result of parse
9947  * @*tc_map: bit map of enabled traffic classes
9948  *
9949  * Returns 0 on success, negative value on failure
9950  */
9951 static int
9952 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9953                          struct i40e_dcbx_config *dcb_cfg,
9954                          uint8_t *tc_map)
9955 {
9956         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9957         uint8_t i, tc_bw, bw_lf;
9958
9959         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9960
9961         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9962         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9963                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9964                 return -EINVAL;
9965         }
9966
9967         /* assume each tc has the same bw */
9968         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9969         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9970                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9971         /* to ensure the sum of tcbw is equal to 100 */
9972         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9973         for (i = 0; i < bw_lf; i++)
9974                 dcb_cfg->etscfg.tcbwtable[i]++;
9975
9976         /* assume each tc has the same Transmission Selection Algorithm */
9977         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9978                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9979
9980         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9981                 dcb_cfg->etscfg.prioritytable[i] =
9982                                 dcb_rx_conf->dcb_tc[i];
9983
9984         /* FW needs one App to configure HW */
9985         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9986         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9987         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9988         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9989
9990         if (dcb_rx_conf->nb_tcs == 0)
9991                 *tc_map = 1; /* tc0 only */
9992         else
9993                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9994
9995         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9996                 dcb_cfg->pfc.willing = 0;
9997                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9998                 dcb_cfg->pfc.pfcenable = *tc_map;
9999         }
10000         return 0;
10001 }
10002
10003
10004 static enum i40e_status_code
10005 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10006                               struct i40e_aqc_vsi_properties_data *info,
10007                               uint8_t enabled_tcmap)
10008 {
10009         enum i40e_status_code ret;
10010         int i, total_tc = 0;
10011         uint16_t qpnum_per_tc, bsf, qp_idx;
10012         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10013         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10014         uint16_t used_queues;
10015
10016         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10017         if (ret != I40E_SUCCESS)
10018                 return ret;
10019
10020         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10021                 if (enabled_tcmap & (1 << i))
10022                         total_tc++;
10023         }
10024         if (total_tc == 0)
10025                 total_tc = 1;
10026         vsi->enabled_tc = enabled_tcmap;
10027
10028         /* different VSI has different queues assigned */
10029         if (vsi->type == I40E_VSI_MAIN)
10030                 used_queues = dev_data->nb_rx_queues -
10031                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10032         else if (vsi->type == I40E_VSI_VMDQ2)
10033                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10034         else {
10035                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10036                 return I40E_ERR_NO_AVAILABLE_VSI;
10037         }
10038
10039         qpnum_per_tc = used_queues / total_tc;
10040         /* Number of queues per enabled TC */
10041         if (qpnum_per_tc == 0) {
10042                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10043                 return I40E_ERR_INVALID_QP_ID;
10044         }
10045         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10046                                 I40E_MAX_Q_PER_TC);
10047         bsf = rte_bsf32(qpnum_per_tc);
10048
10049         /**
10050          * Configure TC and queue mapping parameters, for enabled TC,
10051          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10052          * default queue will serve it.
10053          */
10054         qp_idx = 0;
10055         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10056                 if (vsi->enabled_tc & (1 << i)) {
10057                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10058                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10059                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10060                         qp_idx += qpnum_per_tc;
10061                 } else
10062                         info->tc_mapping[i] = 0;
10063         }
10064
10065         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10066         if (vsi->type == I40E_VSI_SRIOV) {
10067                 info->mapping_flags |=
10068                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10069                 for (i = 0; i < vsi->nb_qps; i++)
10070                         info->queue_mapping[i] =
10071                                 rte_cpu_to_le_16(vsi->base_queue + i);
10072         } else {
10073                 info->mapping_flags |=
10074                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10075                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10076         }
10077         info->valid_sections |=
10078                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10079
10080         return I40E_SUCCESS;
10081 }
10082
10083 /*
10084  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10085  * @veb: VEB to be configured
10086  * @tc_map: enabled TC bitmap
10087  *
10088  * Returns 0 on success, negative value on failure
10089  */
10090 static enum i40e_status_code
10091 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10092 {
10093         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10094         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10095         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10096         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10097         enum i40e_status_code ret = I40E_SUCCESS;
10098         int i;
10099         uint32_t bw_max;
10100
10101         /* Check if enabled_tc is same as existing or new TCs */
10102         if (veb->enabled_tc == tc_map)
10103                 return ret;
10104
10105         /* configure tc bandwidth */
10106         memset(&veb_bw, 0, sizeof(veb_bw));
10107         veb_bw.tc_valid_bits = tc_map;
10108         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10109         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10110                 if (tc_map & BIT_ULL(i))
10111                         veb_bw.tc_bw_share_credits[i] = 1;
10112         }
10113         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10114                                                    &veb_bw, NULL);
10115         if (ret) {
10116                 PMD_INIT_LOG(ERR,
10117                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10118                         hw->aq.asq_last_status);
10119                 return ret;
10120         }
10121
10122         memset(&ets_query, 0, sizeof(ets_query));
10123         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10124                                                    &ets_query, NULL);
10125         if (ret != I40E_SUCCESS) {
10126                 PMD_DRV_LOG(ERR,
10127                         "Failed to get switch_comp ETS configuration %u",
10128                         hw->aq.asq_last_status);
10129                 return ret;
10130         }
10131         memset(&bw_query, 0, sizeof(bw_query));
10132         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10133                                                   &bw_query, NULL);
10134         if (ret != I40E_SUCCESS) {
10135                 PMD_DRV_LOG(ERR,
10136                         "Failed to get switch_comp bandwidth configuration %u",
10137                         hw->aq.asq_last_status);
10138                 return ret;
10139         }
10140
10141         /* store and print out BW info */
10142         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10143         veb->bw_info.bw_max = ets_query.tc_bw_max;
10144         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10145         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10146         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10147                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10148                      I40E_16_BIT_WIDTH);
10149         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10150                 veb->bw_info.bw_ets_share_credits[i] =
10151                                 bw_query.tc_bw_share_credits[i];
10152                 veb->bw_info.bw_ets_credits[i] =
10153                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10154                 /* 4 bits per TC, 4th bit is reserved */
10155                 veb->bw_info.bw_ets_max[i] =
10156                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10157                                   RTE_LEN2MASK(3, uint8_t));
10158                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10159                             veb->bw_info.bw_ets_share_credits[i]);
10160                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10161                             veb->bw_info.bw_ets_credits[i]);
10162                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10163                             veb->bw_info.bw_ets_max[i]);
10164         }
10165
10166         veb->enabled_tc = tc_map;
10167
10168         return ret;
10169 }
10170
10171
10172 /*
10173  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10174  * @vsi: VSI to be configured
10175  * @tc_map: enabled TC bitmap
10176  *
10177  * Returns 0 on success, negative value on failure
10178  */
10179 static enum i40e_status_code
10180 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10181 {
10182         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10183         struct i40e_vsi_context ctxt;
10184         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10185         enum i40e_status_code ret = I40E_SUCCESS;
10186         int i;
10187
10188         /* Check if enabled_tc is same as existing or new TCs */
10189         if (vsi->enabled_tc == tc_map)
10190                 return ret;
10191
10192         /* configure tc bandwidth */
10193         memset(&bw_data, 0, sizeof(bw_data));
10194         bw_data.tc_valid_bits = tc_map;
10195         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10196         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10197                 if (tc_map & BIT_ULL(i))
10198                         bw_data.tc_bw_credits[i] = 1;
10199         }
10200         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10201         if (ret) {
10202                 PMD_INIT_LOG(ERR,
10203                         "AQ command Config VSI BW allocation per TC failed = %d",
10204                         hw->aq.asq_last_status);
10205                 goto out;
10206         }
10207         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10208                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10209
10210         /* Update Queue Pairs Mapping for currently enabled UPs */
10211         ctxt.seid = vsi->seid;
10212         ctxt.pf_num = hw->pf_id;
10213         ctxt.vf_num = 0;
10214         ctxt.uplink_seid = vsi->uplink_seid;
10215         ctxt.info = vsi->info;
10216         i40e_get_cap(hw);
10217         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10218         if (ret)
10219                 goto out;
10220
10221         /* Update the VSI after updating the VSI queue-mapping information */
10222         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10223         if (ret) {
10224                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10225                         hw->aq.asq_last_status);
10226                 goto out;
10227         }
10228         /* update the local VSI info with updated queue map */
10229         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10230                                         sizeof(vsi->info.tc_mapping));
10231         (void)rte_memcpy(&vsi->info.queue_mapping,
10232                         &ctxt.info.queue_mapping,
10233                 sizeof(vsi->info.queue_mapping));
10234         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10235         vsi->info.valid_sections = 0;
10236
10237         /* query and update current VSI BW information */
10238         ret = i40e_vsi_get_bw_config(vsi);
10239         if (ret) {
10240                 PMD_INIT_LOG(ERR,
10241                          "Failed updating vsi bw info, err %s aq_err %s",
10242                          i40e_stat_str(hw, ret),
10243                          i40e_aq_str(hw, hw->aq.asq_last_status));
10244                 goto out;
10245         }
10246
10247         vsi->enabled_tc = tc_map;
10248
10249 out:
10250         return ret;
10251 }
10252
10253 /*
10254  * i40e_dcb_hw_configure - program the dcb setting to hw
10255  * @pf: pf the configuration is taken on
10256  * @new_cfg: new configuration
10257  * @tc_map: enabled TC bitmap
10258  *
10259  * Returns 0 on success, negative value on failure
10260  */
10261 static enum i40e_status_code
10262 i40e_dcb_hw_configure(struct i40e_pf *pf,
10263                       struct i40e_dcbx_config *new_cfg,
10264                       uint8_t tc_map)
10265 {
10266         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10267         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10268         struct i40e_vsi *main_vsi = pf->main_vsi;
10269         struct i40e_vsi_list *vsi_list;
10270         enum i40e_status_code ret;
10271         int i;
10272         uint32_t val;
10273
10274         /* Use the FW API if FW > v4.4*/
10275         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10276               (hw->aq.fw_maj_ver >= 5))) {
10277                 PMD_INIT_LOG(ERR,
10278                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10279                 return I40E_ERR_FIRMWARE_API_VERSION;
10280         }
10281
10282         /* Check if need reconfiguration */
10283         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10284                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10285                 return I40E_SUCCESS;
10286         }
10287
10288         /* Copy the new config to the current config */
10289         *old_cfg = *new_cfg;
10290         old_cfg->etsrec = old_cfg->etscfg;
10291         ret = i40e_set_dcb_config(hw);
10292         if (ret) {
10293                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10294                          i40e_stat_str(hw, ret),
10295                          i40e_aq_str(hw, hw->aq.asq_last_status));
10296                 return ret;
10297         }
10298         /* set receive Arbiter to RR mode and ETS scheme by default */
10299         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10300                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10301                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10302                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10303                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10304                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10305                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10306                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10307                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10308                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10309                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10310                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10311                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10312         }
10313         /* get local mib to check whether it is configured correctly */
10314         /* IEEE mode */
10315         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10316         /* Get Local DCB Config */
10317         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10318                                      &hw->local_dcbx_config);
10319
10320         /* if Veb is created, need to update TC of it at first */
10321         if (main_vsi->veb) {
10322                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10323                 if (ret)
10324                         PMD_INIT_LOG(WARNING,
10325                                  "Failed configuring TC for VEB seid=%d",
10326                                  main_vsi->veb->seid);
10327         }
10328         /* Update each VSI */
10329         i40e_vsi_config_tc(main_vsi, tc_map);
10330         if (main_vsi->veb) {
10331                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10332                         /* Beside main VSI and VMDQ VSIs, only enable default
10333                          * TC for other VSIs
10334                          */
10335                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10336                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10337                                                          tc_map);
10338                         else
10339                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10340                                                          I40E_DEFAULT_TCMAP);
10341                         if (ret)
10342                                 PMD_INIT_LOG(WARNING,
10343                                         "Failed configuring TC for VSI seid=%d",
10344                                         vsi_list->vsi->seid);
10345                         /* continue */
10346                 }
10347         }
10348         return I40E_SUCCESS;
10349 }
10350
10351 /*
10352  * i40e_dcb_init_configure - initial dcb config
10353  * @dev: device being configured
10354  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10355  *
10356  * Returns 0 on success, negative value on failure
10357  */
10358 static int
10359 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10360 {
10361         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10363         int i, ret = 0;
10364
10365         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10366                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10367                 return -ENOTSUP;
10368         }
10369
10370         /* DCB initialization:
10371          * Update DCB configuration from the Firmware and configure
10372          * LLDP MIB change event.
10373          */
10374         if (sw_dcb == TRUE) {
10375                 ret = i40e_init_dcb(hw);
10376                 /* If lldp agent is stopped, the return value from
10377                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10378                  * adminq status. Otherwise, it should return success.
10379                  */
10380                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10381                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10382                         memset(&hw->local_dcbx_config, 0,
10383                                 sizeof(struct i40e_dcbx_config));
10384                         /* set dcb default configuration */
10385                         hw->local_dcbx_config.etscfg.willing = 0;
10386                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10387                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10388                         hw->local_dcbx_config.etscfg.tsatable[0] =
10389                                                 I40E_IEEE_TSA_ETS;
10390                         /* all UPs mapping to TC0 */
10391                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10392                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10393                         hw->local_dcbx_config.etsrec =
10394                                 hw->local_dcbx_config.etscfg;
10395                         hw->local_dcbx_config.pfc.willing = 0;
10396                         hw->local_dcbx_config.pfc.pfccap =
10397                                                 I40E_MAX_TRAFFIC_CLASS;
10398                         /* FW needs one App to configure HW */
10399                         hw->local_dcbx_config.numapps = 1;
10400                         hw->local_dcbx_config.app[0].selector =
10401                                                 I40E_APP_SEL_ETHTYPE;
10402                         hw->local_dcbx_config.app[0].priority = 3;
10403                         hw->local_dcbx_config.app[0].protocolid =
10404                                                 I40E_APP_PROTOID_FCOE;
10405                         ret = i40e_set_dcb_config(hw);
10406                         if (ret) {
10407                                 PMD_INIT_LOG(ERR,
10408                                         "default dcb config fails. err = %d, aq_err = %d.",
10409                                         ret, hw->aq.asq_last_status);
10410                                 return -ENOSYS;
10411                         }
10412                 } else {
10413                         PMD_INIT_LOG(ERR,
10414                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10415                                 ret, hw->aq.asq_last_status);
10416                         return -ENOTSUP;
10417                 }
10418         } else {
10419                 ret = i40e_aq_start_lldp(hw, NULL);
10420                 if (ret != I40E_SUCCESS)
10421                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10422
10423                 ret = i40e_init_dcb(hw);
10424                 if (!ret) {
10425                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10426                                 PMD_INIT_LOG(ERR,
10427                                         "HW doesn't support DCBX offload.");
10428                                 return -ENOTSUP;
10429                         }
10430                 } else {
10431                         PMD_INIT_LOG(ERR,
10432                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10433                                 ret, hw->aq.asq_last_status);
10434                         return -ENOTSUP;
10435                 }
10436         }
10437         return 0;
10438 }
10439
10440 /*
10441  * i40e_dcb_setup - setup dcb related config
10442  * @dev: device being configured
10443  *
10444  * Returns 0 on success, negative value on failure
10445  */
10446 static int
10447 i40e_dcb_setup(struct rte_eth_dev *dev)
10448 {
10449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10450         struct i40e_dcbx_config dcb_cfg;
10451         uint8_t tc_map = 0;
10452         int ret = 0;
10453
10454         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10455                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10456                 return -ENOTSUP;
10457         }
10458
10459         if (pf->vf_num != 0)
10460                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10461
10462         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10463         if (ret) {
10464                 PMD_INIT_LOG(ERR, "invalid dcb config");
10465                 return -EINVAL;
10466         }
10467         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10468         if (ret) {
10469                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10470                 return -ENOSYS;
10471         }
10472
10473         return 0;
10474 }
10475
10476 static int
10477 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10478                       struct rte_eth_dcb_info *dcb_info)
10479 {
10480         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10481         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10482         struct i40e_vsi *vsi = pf->main_vsi;
10483         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10484         uint16_t bsf, tc_mapping;
10485         int i, j = 0;
10486
10487         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10488                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10489         else
10490                 dcb_info->nb_tcs = 1;
10491         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10492                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10493         for (i = 0; i < dcb_info->nb_tcs; i++)
10494                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10495
10496         /* get queue mapping if vmdq is disabled */
10497         if (!pf->nb_cfg_vmdq_vsi) {
10498                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10499                         if (!(vsi->enabled_tc & (1 << i)))
10500                                 continue;
10501                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10502                         dcb_info->tc_queue.tc_rxq[j][i].base =
10503                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10504                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10505                         dcb_info->tc_queue.tc_txq[j][i].base =
10506                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10507                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10508                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10509                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10510                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10511                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10512                 }
10513                 return 0;
10514         }
10515
10516         /* get queue mapping if vmdq is enabled */
10517         do {
10518                 vsi = pf->vmdq[j].vsi;
10519                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10520                         if (!(vsi->enabled_tc & (1 << i)))
10521                                 continue;
10522                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10523                         dcb_info->tc_queue.tc_rxq[j][i].base =
10524                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10525                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10526                         dcb_info->tc_queue.tc_txq[j][i].base =
10527                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10528                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10529                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10530                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10531                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10532                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10533                 }
10534                 j++;
10535         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10536         return 0;
10537 }
10538
10539 static int
10540 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10541 {
10542         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10543         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10544         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10545         uint16_t interval =
10546                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10547         uint16_t msix_intr;
10548
10549         msix_intr = intr_handle->intr_vec[queue_id];
10550         if (msix_intr == I40E_MISC_VEC_ID)
10551                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10552                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10553                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10554                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10555                                (interval <<
10556                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10557         else
10558                 I40E_WRITE_REG(hw,
10559                                I40E_PFINT_DYN_CTLN(msix_intr -
10560                                                    I40E_RX_VEC_START),
10561                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10562                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10563                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10564                                (interval <<
10565                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10566
10567         I40E_WRITE_FLUSH(hw);
10568         rte_intr_enable(&pci_dev->intr_handle);
10569
10570         return 0;
10571 }
10572
10573 static int
10574 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10575 {
10576         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10577         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10578         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10579         uint16_t msix_intr;
10580
10581         msix_intr = intr_handle->intr_vec[queue_id];
10582         if (msix_intr == I40E_MISC_VEC_ID)
10583                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10584         else
10585                 I40E_WRITE_REG(hw,
10586                                I40E_PFINT_DYN_CTLN(msix_intr -
10587                                                    I40E_RX_VEC_START),
10588                                0);
10589         I40E_WRITE_FLUSH(hw);
10590
10591         return 0;
10592 }
10593
10594 static int i40e_get_regs(struct rte_eth_dev *dev,
10595                          struct rte_dev_reg_info *regs)
10596 {
10597         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10598         uint32_t *ptr_data = regs->data;
10599         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10600         const struct i40e_reg_info *reg_info;
10601
10602         if (ptr_data == NULL) {
10603                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10604                 regs->width = sizeof(uint32_t);
10605                 return 0;
10606         }
10607
10608         /* The first few registers have to be read using AQ operations */
10609         reg_idx = 0;
10610         while (i40e_regs_adminq[reg_idx].name) {
10611                 reg_info = &i40e_regs_adminq[reg_idx++];
10612                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10613                         for (arr_idx2 = 0;
10614                                         arr_idx2 <= reg_info->count2;
10615                                         arr_idx2++) {
10616                                 reg_offset = arr_idx * reg_info->stride1 +
10617                                         arr_idx2 * reg_info->stride2;
10618                                 reg_offset += reg_info->base_addr;
10619                                 ptr_data[reg_offset >> 2] =
10620                                         i40e_read_rx_ctl(hw, reg_offset);
10621                         }
10622         }
10623
10624         /* The remaining registers can be read using primitives */
10625         reg_idx = 0;
10626         while (i40e_regs_others[reg_idx].name) {
10627                 reg_info = &i40e_regs_others[reg_idx++];
10628                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10629                         for (arr_idx2 = 0;
10630                                         arr_idx2 <= reg_info->count2;
10631                                         arr_idx2++) {
10632                                 reg_offset = arr_idx * reg_info->stride1 +
10633                                         arr_idx2 * reg_info->stride2;
10634                                 reg_offset += reg_info->base_addr;
10635                                 ptr_data[reg_offset >> 2] =
10636                                         I40E_READ_REG(hw, reg_offset);
10637                         }
10638         }
10639
10640         return 0;
10641 }
10642
10643 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10644 {
10645         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10646
10647         /* Convert word count to byte count */
10648         return hw->nvm.sr_size << 1;
10649 }
10650
10651 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10652                            struct rte_dev_eeprom_info *eeprom)
10653 {
10654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10655         uint16_t *data = eeprom->data;
10656         uint16_t offset, length, cnt_words;
10657         int ret_code;
10658
10659         offset = eeprom->offset >> 1;
10660         length = eeprom->length >> 1;
10661         cnt_words = length;
10662
10663         if (offset > hw->nvm.sr_size ||
10664                 offset + length > hw->nvm.sr_size) {
10665                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10666                 return -EINVAL;
10667         }
10668
10669         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10670
10671         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10672         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10673                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10674                 return -EIO;
10675         }
10676
10677         return 0;
10678 }
10679
10680 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10681                                       struct ether_addr *mac_addr)
10682 {
10683         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10684
10685         if (!is_valid_assigned_ether_addr(mac_addr)) {
10686                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10687                 return;
10688         }
10689
10690         /* Flags: 0x3 updates port address */
10691         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10692 }
10693
10694 static int
10695 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10696 {
10697         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10698         struct rte_eth_dev_data *dev_data = pf->dev_data;
10699         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10700         int ret = 0;
10701
10702         /* check if mtu is within the allowed range */
10703         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10704                 return -EINVAL;
10705
10706         /* mtu setting is forbidden if port is start */
10707         if (dev_data->dev_started) {
10708                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10709                             dev_data->port_id);
10710                 return -EBUSY;
10711         }
10712
10713         if (frame_size > ETHER_MAX_LEN)
10714                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10715         else
10716                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10717
10718         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10719
10720         return ret;
10721 }
10722
10723 /* Restore ethertype filter */
10724 static void
10725 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10726 {
10727         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10728         struct i40e_ethertype_filter_list
10729                 *ethertype_list = &pf->ethertype.ethertype_list;
10730         struct i40e_ethertype_filter *f;
10731         struct i40e_control_filter_stats stats;
10732         uint16_t flags;
10733
10734         TAILQ_FOREACH(f, ethertype_list, rules) {
10735                 flags = 0;
10736                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10737                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10738                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10739                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10740                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10741
10742                 memset(&stats, 0, sizeof(stats));
10743                 i40e_aq_add_rem_control_packet_filter(hw,
10744                                             f->input.mac_addr.addr_bytes,
10745                                             f->input.ether_type,
10746                                             flags, pf->main_vsi->seid,
10747                                             f->queue, 1, &stats, NULL);
10748         }
10749         PMD_DRV_LOG(INFO, "Ethertype filter:"
10750                     " mac_etype_used = %u, etype_used = %u,"
10751                     " mac_etype_free = %u, etype_free = %u",
10752                     stats.mac_etype_used, stats.etype_used,
10753                     stats.mac_etype_free, stats.etype_free);
10754 }
10755
10756 /* Restore tunnel filter */
10757 static void
10758 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10759 {
10760         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10761         struct i40e_vsi *vsi;
10762         struct i40e_pf_vf *vf;
10763         struct i40e_tunnel_filter_list
10764                 *tunnel_list = &pf->tunnel.tunnel_list;
10765         struct i40e_tunnel_filter *f;
10766         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10767         bool big_buffer = 0;
10768
10769         TAILQ_FOREACH(f, tunnel_list, rules) {
10770                 if (!f->is_to_vf)
10771                         vsi = pf->main_vsi;
10772                 else {
10773                         vf = &pf->vfs[f->vf_id];
10774                         vsi = vf->vsi;
10775                 }
10776                 memset(&cld_filter, 0, sizeof(cld_filter));
10777                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10778                         (struct ether_addr *)&cld_filter.element.outer_mac);
10779                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10780                         (struct ether_addr *)&cld_filter.element.inner_mac);
10781                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10782                 cld_filter.element.flags = f->input.flags;
10783                 cld_filter.element.tenant_id = f->input.tenant_id;
10784                 cld_filter.element.queue_number = f->queue;
10785                 rte_memcpy(cld_filter.general_fields,
10786                            f->input.general_fields,
10787                            sizeof(f->input.general_fields));
10788
10789                 if (((f->input.flags &
10790                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10791                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10792                     ((f->input.flags &
10793                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10794                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10795                     ((f->input.flags &
10796                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10797                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10798                         big_buffer = 1;
10799
10800                 if (big_buffer)
10801                         i40e_aq_add_cloud_filters_big_buffer(hw,
10802                                              vsi->seid, &cld_filter, 1);
10803                 else
10804                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10805                                                   &cld_filter.element, 1);
10806         }
10807 }
10808
10809 static void
10810 i40e_filter_restore(struct i40e_pf *pf)
10811 {
10812         i40e_ethertype_filter_restore(pf);
10813         i40e_tunnel_filter_restore(pf);
10814         i40e_fdir_filter_restore(pf);
10815 }
10816
10817 static bool
10818 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10819 {
10820         if (strcmp(dev->device->driver->name, drv->driver.name))
10821                 return false;
10822
10823         return true;
10824 }
10825
10826 bool
10827 is_i40e_supported(struct rte_eth_dev *dev)
10828 {
10829         return is_device_supported(dev, &rte_i40e_pmd);
10830 }
10831
10832 /* Create a QinQ cloud filter
10833  *
10834  * The Fortville NIC has limited resources for tunnel filters,
10835  * so we can only reuse existing filters.
10836  *
10837  * In step 1 we define which Field Vector fields can be used for
10838  * filter types.
10839  * As we do not have the inner tag defined as a field,
10840  * we have to define it first, by reusing one of L1 entries.
10841  *
10842  * In step 2 we are replacing one of existing filter types with
10843  * a new one for QinQ.
10844  * As we reusing L1 and replacing L2, some of the default filter
10845  * types will disappear,which depends on L1 and L2 entries we reuse.
10846  *
10847  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10848  *
10849  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10850  *              later when we define the cloud filter.
10851  *      a.      Valid_flags.replace_cloud = 0
10852  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10853  *      c.      New_filter = 0x10
10854  *      d.      TR bit = 0xff (optional, not used here)
10855  *      e.      Buffer – 2 entries:
10856  *              i.      Byte 0 = 8 (outer vlan FV index).
10857  *                      Byte 1 = 0 (rsv)
10858  *                      Byte 2-3 = 0x0fff
10859  *              ii.     Byte 0 = 37 (inner vlan FV index).
10860  *                      Byte 1 =0 (rsv)
10861  *                      Byte 2-3 = 0x0fff
10862  *
10863  * Step 2:
10864  * 2.   Create cloud filter using two L1 filters entries: stag and
10865  *              new filter(outer vlan+ inner vlan)
10866  *      a.      Valid_flags.replace_cloud = 1
10867  *      b.      Old_filter = 1 (instead of outer IP)
10868  *      c.      New_filter = 0x10
10869  *      d.      Buffer – 2 entries:
10870  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10871  *                      Byte 1-3 = 0 (rsv)
10872  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10873  *                      Byte 9-11 = 0 (rsv)
10874  */
10875 static int
10876 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10877 {
10878         int ret = -ENOTSUP;
10879         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10880         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10881         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10882
10883         /* Init */
10884         memset(&filter_replace, 0,
10885                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10886         memset(&filter_replace_buf, 0,
10887                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10888
10889         /* create L1 filter */
10890         filter_replace.old_filter_type =
10891                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10892         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10893         filter_replace.tr_bit = 0;
10894
10895         /* Prepare the buffer, 2 entries */
10896         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10897         filter_replace_buf.data[0] |=
10898                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10899         /* Field Vector 12b mask */
10900         filter_replace_buf.data[2] = 0xff;
10901         filter_replace_buf.data[3] = 0x0f;
10902         filter_replace_buf.data[4] =
10903                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10904         filter_replace_buf.data[4] |=
10905                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10906         /* Field Vector 12b mask */
10907         filter_replace_buf.data[6] = 0xff;
10908         filter_replace_buf.data[7] = 0x0f;
10909         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10910                         &filter_replace_buf);
10911         if (ret != I40E_SUCCESS)
10912                 return ret;
10913
10914         /* Apply the second L2 cloud filter */
10915         memset(&filter_replace, 0,
10916                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10917         memset(&filter_replace_buf, 0,
10918                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10919
10920         /* create L2 filter, input for L2 filter will be L1 filter  */
10921         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10922         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10923         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10924
10925         /* Prepare the buffer, 2 entries */
10926         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10927         filter_replace_buf.data[0] |=
10928                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10929         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10930         filter_replace_buf.data[4] |=
10931                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10932         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10933                         &filter_replace_buf);
10934         return ret;
10935 }
10936
10937 RTE_INIT(i40e_init_log);
10938 static void
10939 i40e_init_log(void)
10940 {
10941         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10942         if (i40e_logtype_init >= 0)
10943                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10944         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10945         if (i40e_logtype_driver >= 0)
10946                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10947 }