drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 /* Additional timesync values. */
 129 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 130 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 131 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 132 #define I40E_PRTTSYN_TSYNENA     0x80000000
 133 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 134 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 135
 136 #define I40E_MAX_PERCENT            100
 137 #define I40E_DEFAULT_DCB_APP_NUM    1
 138 #define I40E_DEFAULT_DCB_APP_PRIO   3
 139
 140 #define I40E_INSET_NONE            0x00000000000000000ULL
 141
 142 /* bit0 ~ bit 7 */
 143 #define I40E_INSET_DMAC            0x0000000000000001ULL
 144 #define I40E_INSET_SMAC            0x0000000000000002ULL
 145 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 146 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 147 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 148
 149 /* bit 8 ~ bit 15 */
 150 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 151 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 152 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 153 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 154 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 155 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 156 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 157
 158 /* bit 16 ~ bit 31 */
 159 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 160 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 161 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 162 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 163 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 164 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 165 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 166 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 167
 168 /* bit 32 ~ bit 47, tunnel fields */
 169 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 170 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 171 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 172 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 173 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 174 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 175
 176 /* bit 48 ~ bit 55 */
 177 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 178
 179 /* bit 56 ~ bit 63, Flex Payload */
 180 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 181 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD \
 189         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 190         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 191         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 192         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 193
 194 /**
 195  * Below are values for writing un-exposed registers suggested
 196  * by silicon experts
 197  */
 198 /* Destination MAC address */
 199 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 200 /* Source MAC address */
 201 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 202 /* VLAN tag in the outer L2 header */
 203 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0080000000000000ULL
 204 /* VLAN tag in the inner L2 header */
 205 #define I40E_REG_INSET_L2_INNER_VLAN             0x0100000000000000ULL
 206 /* Source IPv4 address */
 207 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 208 /* Destination IPv4 address */
 209 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 210 /* IPv4 Type of Service (TOS) */
 211 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 212 /* IPv4 Protocol */
 213 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 214 /* Source IPv6 address */
 215 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 216 /* Destination IPv6 address */
 217 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 218 /* IPv6 Traffic Class (TC) */
 219 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 220 /* IPv6 Next Header */
 221 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 222 /* Source L4 port */
 223 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 224 /* Destination L4 port */
 225 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 226 /* SCTP verification tag */
 227 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 228 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 229 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 230 /* Source port of tunneling UDP */
 231 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 232 /* Destination port of tunneling UDP */
 233 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 234 /* UDP Tunneling ID, NVGRE/GRE key */
 235 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 236 /* Last ether type */
 237 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 238 /* Tunneling outer destination IPv4 address */
 239 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 240 /* Tunneling outer destination IPv6 address */
 241 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 242 /* 1st word of flex payload */
 243 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 244 /* 2nd word of flex payload */
 245 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 246 /* 3rd word of flex payload */
 247 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 248 /* 4th word of flex payload */
 249 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 250 /* 5th word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 252 /* 6th word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 254 /* 7th word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 256 /* 8th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 258
 259 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 260
 261 #define I40E_TRANSLATE_INSET 0
 262 #define I40E_TRANSLATE_REG   1
 263
 264 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 265 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 266 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 267 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 268
 269 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 270 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 271 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 272         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 273
 274 /* PCI offset for querying capability */
 275 #define PCI_DEV_CAP_REG            0xA4
 276 /* PCI offset for enabling/disabling Extended Tag */
 277 #define PCI_DEV_CTRL_REG           0xA8
 278 /* Bit mask of Extended Tag capability */
 279 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 280 /* Bit shift of Extended Tag enable/disable */
 281 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 282 /* Bit mask of Extended Tag enable/disable */
 283 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 284
 285 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 286 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 287 static int i40e_dev_configure(struct rte_eth_dev *dev);
 288 static int i40e_dev_start(struct rte_eth_dev *dev);
 289 static void i40e_dev_stop(struct rte_eth_dev *dev);
 290 static void i40e_dev_close(struct rte_eth_dev *dev);
 291 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 292 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 293 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 294 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 295 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 296 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 297 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 298                                struct rte_eth_stats *stats);
 299 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 300                                struct rte_eth_xstats *xstats, unsigned n);
 301 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 302 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 303                                             uint16_t queue_id,
 304                                             uint8_t stat_idx,
 305                                             uint8_t is_rx);
 306 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 307                               struct rte_eth_dev_info *dev_info);
 308 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 309                                 uint16_t vlan_id,
 310                                 int on);
 311 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 312                               enum rte_vlan_type vlan_type,
 313                               uint16_t tpid);
 314 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 315 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 316                                       uint16_t queue,
 317                                       int on);
 318 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 319 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 320 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 321 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 322                               struct rte_eth_fc_conf *fc_conf);
 323 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 324                               struct rte_eth_fc_conf *fc_conf);
 325 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 326                                        struct rte_eth_pfc_conf *pfc_conf);
 327 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 328                           struct ether_addr *mac_addr,
 329                           uint32_t index,
 330                           uint32_t pool);
 331 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 332 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 333                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 334                                     uint16_t reta_size);
 335 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 336                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 337                                    uint16_t reta_size);
 338
 339 static int i40e_get_cap(struct i40e_hw *hw);
 340 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 341 static int i40e_pf_setup(struct i40e_pf *pf);
 342 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 343 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 344 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 345 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 346 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 347                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 348 static void i40e_stat_update_48(struct i40e_hw *hw,
 349                                uint32_t hireg,
 350                                uint32_t loreg,
 351                                bool offset_loaded,
 352                                uint64_t *offset,
 353                                uint64_t *stat);
 354 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 355 static void i40e_dev_interrupt_handler(
 356                 __rte_unused struct rte_intr_handle *handle, void *param);
 357 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 358                                 uint32_t base, uint32_t num);
 359 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 360 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 361                         uint32_t base);
 362 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 363                         uint16_t num);
 364 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 365 static int i40e_veb_release(struct i40e_veb *veb);
 366 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 367                                                 struct i40e_vsi *vsi);
 368 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 369 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 370 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 371                                              struct i40e_macvlan_filter *mv_f,
 372                                              int num,
 373                                              struct ether_addr *addr);
 374 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 375                                              struct i40e_macvlan_filter *mv_f,
 376                                              int num,
 377                                              uint16_t vlan);
 378 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 379 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 380                                     struct rte_eth_rss_conf *rss_conf);
 381 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 382                                       struct rte_eth_rss_conf *rss_conf);
 383 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                         struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                         struct rte_eth_udp_tunnel *udp_tunnel);
 387 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 388                         struct rte_eth_ethertype_filter *filter,
 389                         bool add);
 390 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 391                                 enum rte_filter_op filter_op,
 392                                 void *arg);
 393 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 394                                 enum rte_filter_type filter_type,
 395                                 enum rte_filter_op filter_op,
 396                                 void *arg);
 397 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 398                                   struct rte_eth_dcb_info *dcb_info);
 399 static void i40e_configure_registers(struct i40e_hw *hw);
 400 static void i40e_hw_init(struct rte_eth_dev *dev);
 401 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 402 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 403                         struct rte_eth_mirror_conf *mirror_conf,
 404                         uint8_t sw_id, uint8_t on);
 405 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 406
 407 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 408 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 409 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 410                                            struct timespec *timestamp,
 411                                            uint32_t flags);
 412 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 413                                            struct timespec *timestamp);
 414 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 415
 416 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 417
 418 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 419                                    struct timespec *timestamp);
 420 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 421                                     const struct timespec *timestamp);
 422
 423 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 424                                          uint16_t queue_id);
 425 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 426                                           uint16_t queue_id);
 427
 428
 429 static const struct rte_pci_id pci_id_i40e_map[] = {
 430 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 431 #include "rte_pci_dev_ids.h"
 432 { .vendor_id = 0, /* sentinel */ },
 433 };
 434
 435 static const struct eth_dev_ops i40e_eth_dev_ops = {
 436         .dev_configure                = i40e_dev_configure,
 437         .dev_start                    = i40e_dev_start,
 438         .dev_stop                     = i40e_dev_stop,
 439         .dev_close                    = i40e_dev_close,
 440         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 441         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 442         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 443         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 444         .dev_set_link_up              = i40e_dev_set_link_up,
 445         .dev_set_link_down            = i40e_dev_set_link_down,
 446         .link_update                  = i40e_dev_link_update,
 447         .stats_get                    = i40e_dev_stats_get,
 448         .xstats_get                   = i40e_dev_xstats_get,
 449         .stats_reset                  = i40e_dev_stats_reset,
 450         .xstats_reset                 = i40e_dev_stats_reset,
 451         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 452         .dev_infos_get                = i40e_dev_info_get,
 453         .vlan_filter_set              = i40e_vlan_filter_set,
 454         .vlan_tpid_set                = i40e_vlan_tpid_set,
 455         .vlan_offload_set             = i40e_vlan_offload_set,
 456         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 457         .vlan_pvid_set                = i40e_vlan_pvid_set,
 458         .rx_queue_start               = i40e_dev_rx_queue_start,
 459         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 460         .tx_queue_start               = i40e_dev_tx_queue_start,
 461         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 462         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 463         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 464         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 465         .rx_queue_release             = i40e_dev_rx_queue_release,
 466         .rx_queue_count               = i40e_dev_rx_queue_count,
 467         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 468         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 469         .tx_queue_release             = i40e_dev_tx_queue_release,
 470         .dev_led_on                   = i40e_dev_led_on,
 471         .dev_led_off                  = i40e_dev_led_off,
 472         .flow_ctrl_get                = i40e_flow_ctrl_get,
 473         .flow_ctrl_set                = i40e_flow_ctrl_set,
 474         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 475         .mac_addr_add                 = i40e_macaddr_add,
 476         .mac_addr_remove              = i40e_macaddr_remove,
 477         .reta_update                  = i40e_dev_rss_reta_update,
 478         .reta_query                   = i40e_dev_rss_reta_query,
 479         .rss_hash_update              = i40e_dev_rss_hash_update,
 480         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 481         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 482         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 483         .filter_ctrl                  = i40e_dev_filter_ctrl,
 484         .rxq_info_get                 = i40e_rxq_info_get,
 485         .txq_info_get                 = i40e_txq_info_get,
 486         .mirror_rule_set              = i40e_mirror_rule_set,
 487         .mirror_rule_reset            = i40e_mirror_rule_reset,
 488         .timesync_enable              = i40e_timesync_enable,
 489         .timesync_disable             = i40e_timesync_disable,
 490         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 491         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 492         .get_dcb_info                 = i40e_dev_get_dcb_info,
 493         .timesync_adjust_time         = i40e_timesync_adjust_time,
 494         .timesync_read_time           = i40e_timesync_read_time,
 495         .timesync_write_time          = i40e_timesync_write_time,
 496 };
 497
 498 /* store statistics names and its offset in stats structure */
 499 struct rte_i40e_xstats_name_off {
 500         char name[RTE_ETH_XSTATS_NAME_SIZE];
 501         unsigned offset;
 502 };
 503
 504 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 505         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 506         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 507         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 508         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 509         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 510                 rx_unknown_protocol)},
 511         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 512         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 513         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 514         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 515 };
 516
 517 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 518                 sizeof(rte_i40e_stats_strings[0]))
 519
 520 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 521         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 522                 tx_dropped_link_down)},
 523         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 524         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 525                 illegal_bytes)},
 526         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 527         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 528                 mac_local_faults)},
 529         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 530                 mac_remote_faults)},
 531         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 532                 rx_length_errors)},
 533         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 534         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 535         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 536         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 537         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 538         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 539                 rx_size_127)},
 540         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 541                 rx_size_255)},
 542         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 543                 rx_size_511)},
 544         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 545                 rx_size_1023)},
 546         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 547                 rx_size_1522)},
 548         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 549                 rx_size_big)},
 550         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_undersize)},
 552         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_oversize)},
 554         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 555                 mac_short_packet_dropped)},
 556         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_fragments)},
 558         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 559         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 560         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 tx_size_127)},
 562         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 tx_size_255)},
 564         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 tx_size_511)},
 566         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 tx_size_1023)},
 568         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 tx_size_1522)},
 570         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 tx_size_big)},
 572         {"rx_flow_director_atr_match_packets",
 573                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 574         {"rx_flow_director_sb_match_packets",
 575                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 576         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 577                 tx_lpi_status)},
 578         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 579                 rx_lpi_status)},
 580         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 581                 tx_lpi_count)},
 582         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 583                 rx_lpi_count)},
 584 };
 585
 586 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 587                 sizeof(rte_i40e_hw_port_strings[0]))
 588
 589 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 590         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 591                 priority_xon_rx)},
 592         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 593                 priority_xoff_rx)},
 594 };
 595
 596 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 597                 sizeof(rte_i40e_rxq_prio_strings[0]))
 598
 599 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 600         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 601                 priority_xon_tx)},
 602         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 603                 priority_xoff_tx)},
 604         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 605                 priority_xon_2_xoff)},
 606 };
 607
 608 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 609                 sizeof(rte_i40e_txq_prio_strings[0]))
 610
 611 static struct eth_driver rte_i40e_pmd = {
 612         .pci_drv = {
 613                 .name = "rte_i40e_pmd",
 614                 .id_table = pci_id_i40e_map,
 615                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 616                         RTE_PCI_DRV_DETACHABLE,
 617         },
 618         .eth_dev_init = eth_i40e_dev_init,
 619         .eth_dev_uninit = eth_i40e_dev_uninit,
 620         .dev_private_size = sizeof(struct i40e_adapter),
 621 };
 622
 623 static inline int
 624 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 625                                      struct rte_eth_link *link)
 626 {
 627         struct rte_eth_link *dst = link;
 628         struct rte_eth_link *src = &(dev->data->dev_link);
 629
 630         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 631                                         *(uint64_t *)src) == 0)
 632                 return -1;
 633
 634         return 0;
 635 }
 636
 637 static inline int
 638 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 639                                       struct rte_eth_link *link)
 640 {
 641         struct rte_eth_link *dst = &(dev->data->dev_link);
 642         struct rte_eth_link *src = link;
 643
 644         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 645                                         *(uint64_t *)src) == 0)
 646                 return -1;
 647
 648         return 0;
 649 }
 650
 651 /*
 652  * Driver initialization routine.
 653  * Invoked once at EAL init time.
 654  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 655  */
 656 static int
 657 rte_i40e_pmd_init(const char *name __rte_unused,
 658                   const char *params __rte_unused)
 659 {
 660         PMD_INIT_FUNC_TRACE();
 661         rte_eth_driver_register(&rte_i40e_pmd);
 662
 663         return 0;
 664 }
 665
 666 static struct rte_driver rte_i40e_driver = {
 667         .type = PMD_PDEV,
 668         .init = rte_i40e_pmd_init,
 669 };
 670
 671 PMD_REGISTER_DRIVER(rte_i40e_driver);
 672
 673 /*
 674  * Initialize registers for flexible payload, which should be set by NVM.
 675  * This should be removed from code once it is fixed in NVM.
 676  */
 677 #ifndef I40E_GLQF_ORT
 678 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 679 #endif
 680 #ifndef I40E_GLQF_PIT
 681 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 682 #endif
 683
 684 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 685 {
 686         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 687         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 688         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 696
 697         /* GLQF_PIT Registers */
 698         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 699         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 700 }
 701
 702 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 703
 704 /*
 705  * Add a ethertype filter to drop all flow control frames transmitted
 706  * from VSIs.
 707 */
 708 static void
 709 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 710 {
 711         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 712         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 713                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 714                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 715         int ret;
 716
 717         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 718                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 719                                 pf->main_vsi_seid, 0,
 720                                 TRUE, NULL, NULL);
 721         if (ret)
 722                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 723                                   " frames from VSIs.");
 724 }
 725
 726 static int
 727 eth_i40e_dev_init(struct rte_eth_dev *dev)
 728 {
 729         struct rte_pci_device *pci_dev;
 730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 731         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 732         struct i40e_vsi *vsi;
 733         int ret;
 734         uint32_t len;
 735         uint8_t aq_fail = 0;
 736
 737         PMD_INIT_FUNC_TRACE();
 738
 739         dev->dev_ops = &i40e_eth_dev_ops;
 740         dev->rx_pkt_burst = i40e_recv_pkts;
 741         dev->tx_pkt_burst = i40e_xmit_pkts;
 742
 743         /* for secondary processes, we don't initialise any further as primary
 744          * has already done this work. Only check we don't need a different
 745          * RX function */
 746         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 747                 i40e_set_rx_function(dev);
 748                 i40e_set_tx_function(dev);
 749                 return 0;
 750         }
 751         pci_dev = dev->pci_dev;
 752
 753         rte_eth_copy_pci_info(dev, pci_dev);
 754
 755         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 756         pf->adapter->eth_dev = dev;
 757         pf->dev_data = dev->data;
 758
 759         hw->back = I40E_PF_TO_ADAPTER(pf);
 760         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 761         if (!hw->hw_addr) {
 762                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 763                              "as address is NULL");
 764                 return -ENODEV;
 765         }
 766
 767         hw->vendor_id = pci_dev->id.vendor_id;
 768         hw->device_id = pci_dev->id.device_id;
 769         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 770         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 771         hw->bus.device = pci_dev->addr.devid;
 772         hw->bus.func = pci_dev->addr.function;
 773         hw->adapter_stopped = 0;
 774
 775         /* Make sure all is clean before doing PF reset */
 776         i40e_clear_hw(hw);
 777
 778         /* Initialize the hardware */
 779         i40e_hw_init(dev);
 780
 781         /* Reset here to make sure all is clean for each PF */
 782         ret = i40e_pf_reset(hw);
 783         if (ret) {
 784                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 785                 return ret;
 786         }
 787
 788         /* Initialize the shared code (base driver) */
 789         ret = i40e_init_shared_code(hw);
 790         if (ret) {
 791                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 792                 return ret;
 793         }
 794
 795         /*
 796          * To work around the NVM issue,initialize registers
 797          * for flexible payload by software.
 798          * It should be removed once issues are fixed in NVM.
 799          */
 800         i40e_flex_payload_reg_init(hw);
 801
 802         /* Initialize the parameters for adminq */
 803         i40e_init_adminq_parameter(hw);
 804         ret = i40e_init_adminq(hw);
 805         if (ret != I40E_SUCCESS) {
 806                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 807                 return -EIO;
 808         }
 809         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 810                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 811                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 812                      ((hw->nvm.version >> 12) & 0xf),
 813                      ((hw->nvm.version >> 4) & 0xff),
 814                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 815
 816         /* Clear PXE mode */
 817         i40e_clear_pxe_mode(hw);
 818
 819         /*
 820          * On X710, performance number is far from the expectation on recent
 821          * firmware versions. The fix for this issue may not be integrated in
 822          * the following firmware version. So the workaround in software driver
 823          * is needed. It needs to modify the initial values of 3 internal only
 824          * registers. Note that the workaround can be removed when it is fixed
 825          * in firmware in the future.
 826          */
 827         i40e_configure_registers(hw);
 828
 829         /* Get hw capabilities */
 830         ret = i40e_get_cap(hw);
 831         if (ret != I40E_SUCCESS) {
 832                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 833                 goto err_get_capabilities;
 834         }
 835
 836         /* Initialize parameters for PF */
 837         ret = i40e_pf_parameter_init(dev);
 838         if (ret != 0) {
 839                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 840                 goto err_parameter_init;
 841         }
 842
 843         /* Initialize the queue management */
 844         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 845         if (ret < 0) {
 846                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 847                 goto err_qp_pool_init;
 848         }
 849         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 850                                 hw->func_caps.num_msix_vectors - 1);
 851         if (ret < 0) {
 852                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 853                 goto err_msix_pool_init;
 854         }
 855
 856         /* Initialize lan hmc */
 857         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 858                                 hw->func_caps.num_rx_qp, 0, 0);
 859         if (ret != I40E_SUCCESS) {
 860                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 861                 goto err_init_lan_hmc;
 862         }
 863
 864         /* Configure lan hmc */
 865         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 866         if (ret != I40E_SUCCESS) {
 867                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 868                 goto err_configure_lan_hmc;
 869         }
 870
 871         /* Get and check the mac address */
 872         i40e_get_mac_addr(hw, hw->mac.addr);
 873         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 874                 PMD_INIT_LOG(ERR, "mac address is not valid");
 875                 ret = -EIO;
 876                 goto err_get_mac_addr;
 877         }
 878         /* Copy the permanent MAC address */
 879         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 880                         (struct ether_addr *) hw->mac.perm_addr);
 881
 882         /* Disable flow control */
 883         hw->fc.requested_mode = I40E_FC_NONE;
 884         i40e_set_fc(hw, &aq_fail, TRUE);
 885
 886         /* Set the global registers with default ether type value */
 887         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
 888         if (ret != I40E_SUCCESS) {
 889                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 890                              "VLAN ether type");
 891                 goto err_setup_pf_switch;
 892         }
 893         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
 894         if (ret != I40E_SUCCESS) {
 895                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 896                              "VLAN ether type");
 897                 goto err_setup_pf_switch;
 898         }
 899
 900         /* PF setup, which includes VSI setup */
 901         ret = i40e_pf_setup(pf);
 902         if (ret) {
 903                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 904                 goto err_setup_pf_switch;
 905         }
 906
 907         vsi = pf->main_vsi;
 908
 909         /* Disable double vlan by default */
 910         i40e_vsi_config_double_vlan(vsi, FALSE);
 911
 912         if (!vsi->max_macaddrs)
 913                 len = ETHER_ADDR_LEN;
 914         else
 915                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 916
 917         /* Should be after VSI initialized */
 918         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 919         if (!dev->data->mac_addrs) {
 920                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 921                                         "for storing mac address");
 922                 goto err_mac_alloc;
 923         }
 924         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 925                                         &dev->data->mac_addrs[0]);
 926
 927         /* initialize pf host driver to setup SRIOV resource if applicable */
 928         i40e_pf_host_init(dev);
 929
 930         /* register callback func to eal lib */
 931         rte_intr_callback_register(&(pci_dev->intr_handle),
 932                 i40e_dev_interrupt_handler, (void *)dev);
 933
 934         /* configure and enable device interrupt */
 935         i40e_pf_config_irq0(hw, TRUE);
 936         i40e_pf_enable_irq0(hw);
 937
 938         /* enable uio intr after callback register */
 939         rte_intr_enable(&(pci_dev->intr_handle));
 940         /*
 941          * Add an ethertype filter to drop all flow control frames transmitted
 942          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 943          * frames to wire.
 944          */
 945         i40e_add_tx_flow_control_drop_filter(pf);
 946
 947         /* Set the max frame size to 0x2600 by default,
 948          * in case other drivers changed the default value.
 949          */
 950         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 951
 952         /* initialize mirror rule list */
 953         TAILQ_INIT(&pf->mirror_list);
 954
 955         /* Init dcb to sw mode by default */
 956         ret = i40e_dcb_init_configure(dev, TRUE);
 957         if (ret != I40E_SUCCESS) {
 958                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 959                 pf->flags &= ~I40E_FLAG_DCB;
 960         }
 961
 962         return 0;
 963
 964 err_mac_alloc:
 965         i40e_vsi_release(pf->main_vsi);
 966 err_setup_pf_switch:
 967 err_get_mac_addr:
 968 err_configure_lan_hmc:
 969         (void)i40e_shutdown_lan_hmc(hw);
 970 err_init_lan_hmc:
 971         i40e_res_pool_destroy(&pf->msix_pool);
 972 err_msix_pool_init:
 973         i40e_res_pool_destroy(&pf->qp_pool);
 974 err_qp_pool_init:
 975 err_parameter_init:
 976 err_get_capabilities:
 977         (void)i40e_shutdown_adminq(hw);
 978
 979         return ret;
 980 }
 981
 982 static int
 983 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 984 {
 985         struct rte_pci_device *pci_dev;
 986         struct i40e_hw *hw;
 987         struct i40e_filter_control_settings settings;
 988         int ret;
 989         uint8_t aq_fail = 0;
 990
 991         PMD_INIT_FUNC_TRACE();
 992
 993         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 994                 return 0;
 995
 996         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 997         pci_dev = dev->pci_dev;
 998
 999         if (hw->adapter_stopped == 0)
1000                 i40e_dev_close(dev);
1001
1002         dev->dev_ops = NULL;
1003         dev->rx_pkt_burst = NULL;
1004         dev->tx_pkt_burst = NULL;
1005
1006         /* Disable LLDP */
1007         ret = i40e_aq_stop_lldp(hw, true, NULL);
1008         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1009                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1010
1011         /* Clear PXE mode */
1012         i40e_clear_pxe_mode(hw);
1013
1014         /* Unconfigure filter control */
1015         memset(&settings, 0, sizeof(settings));
1016         ret = i40e_set_filter_control(hw, &settings);
1017         if (ret)
1018                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1019                                         ret);
1020
1021         /* Disable flow control */
1022         hw->fc.requested_mode = I40E_FC_NONE;
1023         i40e_set_fc(hw, &aq_fail, TRUE);
1024
1025         /* uninitialize pf host driver */
1026         i40e_pf_host_uninit(dev);
1027
1028         rte_free(dev->data->mac_addrs);
1029         dev->data->mac_addrs = NULL;
1030
1031         /* disable uio intr before callback unregister */
1032         rte_intr_disable(&(pci_dev->intr_handle));
1033
1034         /* register callback func to eal lib */
1035         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1036                 i40e_dev_interrupt_handler, (void *)dev);
1037
1038         return 0;
1039 }
1040
1041 static int
1042 i40e_dev_configure(struct rte_eth_dev *dev)
1043 {
1044         struct i40e_adapter *ad =
1045                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1046         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1047         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1048         int i, ret;
1049
1050         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1051          * bulk allocation or vector Rx preconditions we will reset it.
1052          */
1053         ad->rx_bulk_alloc_allowed = true;
1054         ad->rx_vec_allowed = true;
1055         ad->tx_simple_allowed = true;
1056         ad->tx_vec_allowed = true;
1057
1058         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1059                 ret = i40e_fdir_setup(pf);
1060                 if (ret != I40E_SUCCESS) {
1061                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1062                         return -ENOTSUP;
1063                 }
1064                 ret = i40e_fdir_configure(dev);
1065                 if (ret < 0) {
1066                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1067                         goto err;
1068                 }
1069         } else
1070                 i40e_fdir_teardown(pf);
1071
1072         ret = i40e_dev_init_vlan(dev);
1073         if (ret < 0)
1074                 goto err;
1075
1076         /* VMDQ setup.
1077          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1078          *  RSS setting have different requirements.
1079          *  General PMD driver call sequence are NIC init, configure,
1080          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1081          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1082          *  applicable. So, VMDQ setting has to be done before
1083          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1084          *  For RSS setting, it will try to calculate actual configured RX queue
1085          *  number, which will be available after rx_queue_setup(). dev_start()
1086          *  function is good to place RSS setup.
1087          */
1088         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1089                 ret = i40e_vmdq_setup(dev);
1090                 if (ret)
1091                         goto err;
1092         }
1093
1094         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1095                 ret = i40e_dcb_setup(dev);
1096                 if (ret) {
1097                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1098                         goto err_dcb;
1099                 }
1100         }
1101
1102         return 0;
1103
1104 err_dcb:
1105         /* need to release vmdq resource if exists */
1106         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1107                 i40e_vsi_release(pf->vmdq[i].vsi);
1108                 pf->vmdq[i].vsi = NULL;
1109         }
1110         rte_free(pf->vmdq);
1111         pf->vmdq = NULL;
1112 err:
1113         /* need to release fdir resource if exists */
1114         i40e_fdir_teardown(pf);
1115         return ret;
1116 }
1117
1118 void
1119 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1120 {
1121         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1122         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1123         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1124         uint16_t msix_vect = vsi->msix_intr;
1125         uint16_t i;
1126
1127         for (i = 0; i < vsi->nb_qps; i++) {
1128                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1129                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1130                 rte_wmb();
1131         }
1132
1133         if (vsi->type != I40E_VSI_SRIOV) {
1134                 if (!rte_intr_allow_others(intr_handle)) {
1135                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1136                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1137                         I40E_WRITE_REG(hw,
1138                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1139                                        0);
1140                 } else {
1141                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1142                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1143                         I40E_WRITE_REG(hw,
1144                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1145                                                        msix_vect - 1), 0);
1146                 }
1147         } else {
1148                 uint32_t reg;
1149                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1150                         vsi->user_param + (msix_vect - 1);
1151
1152                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1153                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1154         }
1155         I40E_WRITE_FLUSH(hw);
1156 }
1157
1158 static void
1159 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1160                        int base_queue, int nb_queue)
1161 {
1162         int i;
1163         uint32_t val;
1164         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1165
1166         /* Bind all RX queues to allocated MSIX interrupt */
1167         for (i = 0; i < nb_queue; i++) {
1168                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1169                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1170                         ((base_queue + i + 1) <<
1171                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1172                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1173                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1174
1175                 if (i == nb_queue - 1)
1176                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1177                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1178         }
1179
1180         /* Write first RX queue to Link list register as the head element */
1181         if (vsi->type != I40E_VSI_SRIOV) {
1182                 uint16_t interval =
1183                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1184
1185                 if (msix_vect == I40E_MISC_VEC_ID) {
1186                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1187                                        (base_queue <<
1188                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1189                                        (0x0 <<
1190                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1191                         I40E_WRITE_REG(hw,
1192                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1193                                        interval);
1194                 } else {
1195                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1196                                        (base_queue <<
1197                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1198                                        (0x0 <<
1199                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1200                         I40E_WRITE_REG(hw,
1201                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1202                                                        msix_vect - 1),
1203                                        interval);
1204                 }
1205         } else {
1206                 uint32_t reg;
1207
1208                 if (msix_vect == I40E_MISC_VEC_ID) {
1209                         I40E_WRITE_REG(hw,
1210                                        I40E_VPINT_LNKLST0(vsi->user_param),
1211                                        (base_queue <<
1212                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1213                                        (0x0 <<
1214                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1215                 } else {
1216                         /* num_msix_vectors_vf needs to minus irq0 */
1217                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1218                                 vsi->user_param + (msix_vect - 1);
1219
1220                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1221                                        (base_queue <<
1222                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1223                                        (0x0 <<
1224                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1225                 }
1226         }
1227
1228         I40E_WRITE_FLUSH(hw);
1229 }
1230
1231 void
1232 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1233 {
1234         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1235         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1236         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1237         uint16_t msix_vect = vsi->msix_intr;
1238         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1239         uint16_t queue_idx = 0;
1240         int record = 0;
1241         uint32_t val;
1242         int i;
1243
1244         for (i = 0; i < vsi->nb_qps; i++) {
1245                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1246                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1247         }
1248
1249         /* INTENA flag is not auto-cleared for interrupt */
1250         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1251         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1252                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1253                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1254         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1255
1256         /* VF bind interrupt */
1257         if (vsi->type == I40E_VSI_SRIOV) {
1258                 __vsi_queues_bind_intr(vsi, msix_vect,
1259                                        vsi->base_queue, vsi->nb_qps);
1260                 return;
1261         }
1262
1263         /* PF & VMDq bind interrupt */
1264         if (rte_intr_dp_is_en(intr_handle)) {
1265                 if (vsi->type == I40E_VSI_MAIN) {
1266                         queue_idx = 0;
1267                         record = 1;
1268                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1269                         struct i40e_vsi *main_vsi =
1270                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1271                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1272                         record = 1;
1273                 }
1274         }
1275
1276         for (i = 0; i < vsi->nb_used_qps; i++) {
1277                 if (nb_msix <= 1) {
1278                         if (!rte_intr_allow_others(intr_handle))
1279                                 /* allow to share MISC_VEC_ID */
1280                                 msix_vect = I40E_MISC_VEC_ID;
1281
1282                         /* no enough msix_vect, map all to one */
1283                         __vsi_queues_bind_intr(vsi, msix_vect,
1284                                                vsi->base_queue + i,
1285                                                vsi->nb_used_qps - i);
1286                         for (; !!record && i < vsi->nb_used_qps; i++)
1287                                 intr_handle->intr_vec[queue_idx + i] =
1288                                         msix_vect;
1289                         break;
1290                 }
1291                 /* 1:1 queue/msix_vect mapping */
1292                 __vsi_queues_bind_intr(vsi, msix_vect,
1293                                        vsi->base_queue + i, 1);
1294                 if (!!record)
1295                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1296
1297                 msix_vect++;
1298                 nb_msix--;
1299         }
1300 }
1301
1302 static void
1303 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1304 {
1305         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1306         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1307         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1308         uint16_t interval = i40e_calc_itr_interval(\
1309                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1310         uint16_t msix_intr, i;
1311
1312         if (rte_intr_allow_others(intr_handle))
1313                 for (i = 0; i < vsi->nb_msix; i++) {
1314                         msix_intr = vsi->msix_intr + i;
1315                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1316                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1317                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1318                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1319                                 (interval <<
1320                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1321                 }
1322         else
1323                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1324                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1325                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1326                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1327                                (interval <<
1328                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1329
1330         I40E_WRITE_FLUSH(hw);
1331 }
1332
1333 static void
1334 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1335 {
1336         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1337         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1338         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1339         uint16_t msix_intr, i;
1340
1341         if (rte_intr_allow_others(intr_handle))
1342                 for (i = 0; i < vsi->nb_msix; i++) {
1343                         msix_intr = vsi->msix_intr + i;
1344                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1345                                        0);
1346                 }
1347         else
1348                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1349
1350         I40E_WRITE_FLUSH(hw);
1351 }
1352
1353 static inline uint8_t
1354 i40e_parse_link_speed(uint16_t eth_link_speed)
1355 {
1356         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1357
1358         switch (eth_link_speed) {
1359         case ETH_LINK_SPEED_40G:
1360                 link_speed = I40E_LINK_SPEED_40GB;
1361                 break;
1362         case ETH_LINK_SPEED_20G:
1363                 link_speed = I40E_LINK_SPEED_20GB;
1364                 break;
1365         case ETH_LINK_SPEED_10G:
1366                 link_speed = I40E_LINK_SPEED_10GB;
1367                 break;
1368         case ETH_LINK_SPEED_1000:
1369                 link_speed = I40E_LINK_SPEED_1GB;
1370                 break;
1371         case ETH_LINK_SPEED_100:
1372                 link_speed = I40E_LINK_SPEED_100MB;
1373                 break;
1374         }
1375
1376         return link_speed;
1377 }
1378
1379 static int
1380 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1381                    __rte_unused uint8_t abilities,
1382                    __rte_unused uint8_t force_speed)
1383 {
1384         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1385          * for the link control limitation of that all link control should be
1386          * handled by firmware. It should follow up if link control will be
1387          * opened to software driver in future firmware versions.
1388          */
1389         return I40E_SUCCESS;
1390 }
1391
1392 static int
1393 i40e_apply_link_speed(struct rte_eth_dev *dev)
1394 {
1395         uint8_t speed;
1396         uint8_t abilities = 0;
1397         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398         struct rte_eth_conf *conf = &dev->data->dev_conf;
1399
1400         speed = i40e_parse_link_speed(conf->link_speed);
1401         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1402         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1403                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1404         else
1405                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1406
1407         return i40e_phy_conf_link(hw, abilities, speed);
1408 }
1409
1410 static int
1411 i40e_dev_start(struct rte_eth_dev *dev)
1412 {
1413         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1414         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415         struct i40e_vsi *main_vsi = pf->main_vsi;
1416         int ret, i;
1417         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1418         uint32_t intr_vector = 0;
1419
1420         hw->adapter_stopped = 0;
1421
1422         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1423                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1424                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1425                              dev->data->dev_conf.link_duplex,
1426                              dev->data->port_id);
1427                 return -EINVAL;
1428         }
1429
1430         rte_intr_disable(intr_handle);
1431
1432         if ((rte_intr_cap_multiple(intr_handle) ||
1433              !RTE_ETH_DEV_SRIOV(dev).active) &&
1434             dev->data->dev_conf.intr_conf.rxq != 0) {
1435                 intr_vector = dev->data->nb_rx_queues;
1436                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1437                         return -1;
1438         }
1439
1440         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1441                 intr_handle->intr_vec =
1442                         rte_zmalloc("intr_vec",
1443                                     dev->data->nb_rx_queues * sizeof(int),
1444                                     0);
1445                 if (!intr_handle->intr_vec) {
1446                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1447                                      " intr_vec\n", dev->data->nb_rx_queues);
1448                         return -ENOMEM;
1449                 }
1450         }
1451
1452         /* Initialize VSI */
1453         ret = i40e_dev_rxtx_init(pf);
1454         if (ret != I40E_SUCCESS) {
1455                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1456                 goto err_up;
1457         }
1458
1459         /* Map queues with MSIX interrupt */
1460         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1461                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1462         i40e_vsi_queues_bind_intr(main_vsi);
1463         i40e_vsi_enable_queues_intr(main_vsi);
1464
1465         /* Map VMDQ VSI queues with MSIX interrupt */
1466         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1467                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1468                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1469                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1470         }
1471
1472         /* enable FDIR MSIX interrupt */
1473         if (pf->fdir.fdir_vsi) {
1474                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1475                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1476         }
1477
1478         /* Enable all queues which have been configured */
1479         ret = i40e_dev_switch_queues(pf, TRUE);
1480         if (ret != I40E_SUCCESS) {
1481                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1482                 goto err_up;
1483         }
1484
1485         /* Enable receiving broadcast packets */
1486         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1487         if (ret != I40E_SUCCESS)
1488                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1489
1490         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1491                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1492                                                 true, NULL);
1493                 if (ret != I40E_SUCCESS)
1494                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1495         }
1496
1497         /* Apply link configure */
1498         ret = i40e_apply_link_speed(dev);
1499         if (I40E_SUCCESS != ret) {
1500                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1501                 goto err_up;
1502         }
1503
1504         if (!rte_intr_allow_others(intr_handle)) {
1505                 rte_intr_callback_unregister(intr_handle,
1506                                              i40e_dev_interrupt_handler,
1507                                              (void *)dev);
1508                 /* configure and enable device interrupt */
1509                 i40e_pf_config_irq0(hw, FALSE);
1510                 i40e_pf_enable_irq0(hw);
1511
1512                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1513                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1514                                      " no intr multiplex\n");
1515         }
1516
1517         /* enable uio intr after callback register */
1518         rte_intr_enable(intr_handle);
1519
1520         return I40E_SUCCESS;
1521
1522 err_up:
1523         i40e_dev_switch_queues(pf, FALSE);
1524         i40e_dev_clear_queues(dev);
1525
1526         return ret;
1527 }
1528
1529 static void
1530 i40e_dev_stop(struct rte_eth_dev *dev)
1531 {
1532         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1533         struct i40e_vsi *main_vsi = pf->main_vsi;
1534         struct i40e_mirror_rule *p_mirror;
1535         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1536         int i;
1537
1538         /* Disable all queues */
1539         i40e_dev_switch_queues(pf, FALSE);
1540
1541         /* un-map queues with interrupt registers */
1542         i40e_vsi_disable_queues_intr(main_vsi);
1543         i40e_vsi_queues_unbind_intr(main_vsi);
1544
1545         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1546                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1547                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1548         }
1549
1550         if (pf->fdir.fdir_vsi) {
1551                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1552                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1553         }
1554         /* Clear all queues and release memory */
1555         i40e_dev_clear_queues(dev);
1556
1557         /* Set link down */
1558         i40e_dev_set_link_down(dev);
1559
1560         /* Remove all mirror rules */
1561         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1562                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1563                 rte_free(p_mirror);
1564         }
1565         pf->nb_mirror_rule = 0;
1566
1567         if (!rte_intr_allow_others(intr_handle))
1568                 /* resume to the default handler */
1569                 rte_intr_callback_register(intr_handle,
1570                                            i40e_dev_interrupt_handler,
1571                                            (void *)dev);
1572
1573         /* Clean datapath event and queue/vec mapping */
1574         rte_intr_efd_disable(intr_handle);
1575         if (intr_handle->intr_vec) {
1576                 rte_free(intr_handle->intr_vec);
1577                 intr_handle->intr_vec = NULL;
1578         }
1579 }
1580
1581 static void
1582 i40e_dev_close(struct rte_eth_dev *dev)
1583 {
1584         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1585         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586         uint32_t reg;
1587         int i;
1588
1589         PMD_INIT_FUNC_TRACE();
1590
1591         i40e_dev_stop(dev);
1592         hw->adapter_stopped = 1;
1593         i40e_dev_free_queues(dev);
1594
1595         /* Disable interrupt */
1596         i40e_pf_disable_irq0(hw);
1597         rte_intr_disable(&(dev->pci_dev->intr_handle));
1598
1599         /* shutdown and destroy the HMC */
1600         i40e_shutdown_lan_hmc(hw);
1601
1602         /* release all the existing VSIs and VEBs */
1603         i40e_fdir_teardown(pf);
1604         i40e_vsi_release(pf->main_vsi);
1605
1606         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1607                 i40e_vsi_release(pf->vmdq[i].vsi);
1608                 pf->vmdq[i].vsi = NULL;
1609         }
1610
1611         rte_free(pf->vmdq);
1612         pf->vmdq = NULL;
1613
1614         /* shutdown the adminq */
1615         i40e_aq_queue_shutdown(hw, true);
1616         i40e_shutdown_adminq(hw);
1617
1618         i40e_res_pool_destroy(&pf->qp_pool);
1619         i40e_res_pool_destroy(&pf->msix_pool);
1620
1621         /* force a PF reset to clean anything leftover */
1622         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1623         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1624                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1625         I40E_WRITE_FLUSH(hw);
1626 }
1627
1628 static void
1629 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1630 {
1631         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         struct i40e_vsi *vsi = pf->main_vsi;
1634         int status;
1635
1636         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1637                                                         true, NULL);
1638         if (status != I40E_SUCCESS)
1639                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1640
1641         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1642                                                         TRUE, NULL);
1643         if (status != I40E_SUCCESS)
1644                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1645
1646 }
1647
1648 static void
1649 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1650 {
1651         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653         struct i40e_vsi *vsi = pf->main_vsi;
1654         int status;
1655
1656         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1657                                                         false, NULL);
1658         if (status != I40E_SUCCESS)
1659                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1660
1661         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1662                                                         false, NULL);
1663         if (status != I40E_SUCCESS)
1664                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1665 }
1666
1667 static void
1668 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1669 {
1670         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1671         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1672         struct i40e_vsi *vsi = pf->main_vsi;
1673         int ret;
1674
1675         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1676         if (ret != I40E_SUCCESS)
1677                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1678 }
1679
1680 static void
1681 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1682 {
1683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         struct i40e_vsi *vsi = pf->main_vsi;
1686         int ret;
1687
1688         if (dev->data->promiscuous == 1)
1689                 return; /* must remain in all_multicast mode */
1690
1691         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1692                                 vsi->seid, FALSE, NULL);
1693         if (ret != I40E_SUCCESS)
1694                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1695 }
1696
1697 /*
1698  * Set device link up.
1699  */
1700 static int
1701 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1702 {
1703         /* re-apply link speed setting */
1704         return i40e_apply_link_speed(dev);
1705 }
1706
1707 /*
1708  * Set device link down.
1709  */
1710 static int
1711 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1712 {
1713         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1714         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1716
1717         return i40e_phy_conf_link(hw, abilities, speed);
1718 }
1719
1720 int
1721 i40e_dev_link_update(struct rte_eth_dev *dev,
1722                      int wait_to_complete)
1723 {
1724 #define CHECK_INTERVAL 100  /* 100ms */
1725 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1726         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727         struct i40e_link_status link_status;
1728         struct rte_eth_link link, old;
1729         int status;
1730         unsigned rep_cnt = MAX_REPEAT_TIME;
1731
1732         memset(&link, 0, sizeof(link));
1733         memset(&old, 0, sizeof(old));
1734         memset(&link_status, 0, sizeof(link_status));
1735         rte_i40e_dev_atomic_read_link_status(dev, &old);
1736
1737         do {
1738                 /* Get link status information from hardware */
1739                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1740                 if (status != I40E_SUCCESS) {
1741                         link.link_speed = ETH_LINK_SPEED_100;
1742                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1743                         PMD_DRV_LOG(ERR, "Failed to get link info");
1744                         goto out;
1745                 }
1746
1747                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1748                 if (!wait_to_complete)
1749                         break;
1750
1751                 rte_delay_ms(CHECK_INTERVAL);
1752         } while (!link.link_status && rep_cnt--);
1753
1754         if (!link.link_status)
1755                 goto out;
1756
1757         /* i40e uses full duplex only */
1758         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1759
1760         /* Parse the link status */
1761         switch (link_status.link_speed) {
1762         case I40E_LINK_SPEED_100MB:
1763                 link.link_speed = ETH_LINK_SPEED_100;
1764                 break;
1765         case I40E_LINK_SPEED_1GB:
1766                 link.link_speed = ETH_LINK_SPEED_1000;
1767                 break;
1768         case I40E_LINK_SPEED_10GB:
1769                 link.link_speed = ETH_LINK_SPEED_10G;
1770                 break;
1771         case I40E_LINK_SPEED_20GB:
1772                 link.link_speed = ETH_LINK_SPEED_20G;
1773                 break;
1774         case I40E_LINK_SPEED_40GB:
1775                 link.link_speed = ETH_LINK_SPEED_40G;
1776                 break;
1777         default:
1778                 link.link_speed = ETH_LINK_SPEED_100;
1779                 break;
1780         }
1781
1782 out:
1783         rte_i40e_dev_atomic_write_link_status(dev, &link);
1784         if (link.link_status == old.link_status)
1785                 return -1;
1786
1787         return 0;
1788 }
1789
1790 /* Get all the statistics of a VSI */
1791 void
1792 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1793 {
1794         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1795         struct i40e_eth_stats *nes = &vsi->eth_stats;
1796         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1797         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1798
1799         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1800                             vsi->offset_loaded, &oes->rx_bytes,
1801                             &nes->rx_bytes);
1802         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1803                             vsi->offset_loaded, &oes->rx_unicast,
1804                             &nes->rx_unicast);
1805         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1806                             vsi->offset_loaded, &oes->rx_multicast,
1807                             &nes->rx_multicast);
1808         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1809                             vsi->offset_loaded, &oes->rx_broadcast,
1810                             &nes->rx_broadcast);
1811         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1812                             &oes->rx_discards, &nes->rx_discards);
1813         /* GLV_REPC not supported */
1814         /* GLV_RMPC not supported */
1815         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1816                             &oes->rx_unknown_protocol,
1817                             &nes->rx_unknown_protocol);
1818         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1819                             vsi->offset_loaded, &oes->tx_bytes,
1820                             &nes->tx_bytes);
1821         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1822                             vsi->offset_loaded, &oes->tx_unicast,
1823                             &nes->tx_unicast);
1824         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1825                             vsi->offset_loaded, &oes->tx_multicast,
1826                             &nes->tx_multicast);
1827         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1828                             vsi->offset_loaded,  &oes->tx_broadcast,
1829                             &nes->tx_broadcast);
1830         /* GLV_TDPC not supported */
1831         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1832                             &oes->tx_errors, &nes->tx_errors);
1833         vsi->offset_loaded = true;
1834
1835         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1836                     vsi->vsi_id);
1837         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1838         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1839         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1840         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1841         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1842         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1843                     nes->rx_unknown_protocol);
1844         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1845         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1846         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1847         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1848         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1849         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1850         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1851                     vsi->vsi_id);
1852 }
1853
1854 static void
1855 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1856 {
1857         unsigned int i;
1858         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1859         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1860
1861         /* Get statistics of struct i40e_eth_stats */
1862         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1863                             I40E_GLPRT_GORCL(hw->port),
1864                             pf->offset_loaded, &os->eth.rx_bytes,
1865                             &ns->eth.rx_bytes);
1866         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1867                             I40E_GLPRT_UPRCL(hw->port),
1868                             pf->offset_loaded, &os->eth.rx_unicast,
1869                             &ns->eth.rx_unicast);
1870         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1871                             I40E_GLPRT_MPRCL(hw->port),
1872                             pf->offset_loaded, &os->eth.rx_multicast,
1873                             &ns->eth.rx_multicast);
1874         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1875                             I40E_GLPRT_BPRCL(hw->port),
1876                             pf->offset_loaded, &os->eth.rx_broadcast,
1877                             &ns->eth.rx_broadcast);
1878         /* Workaround: CRC size should not be included in byte statistics,
1879          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1880          */
1881         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1882                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1883
1884         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1885                             pf->offset_loaded, &os->eth.rx_discards,
1886                             &ns->eth.rx_discards);
1887         /* GLPRT_REPC not supported */
1888         /* GLPRT_RMPC not supported */
1889         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1890                             pf->offset_loaded,
1891                             &os->eth.rx_unknown_protocol,
1892                             &ns->eth.rx_unknown_protocol);
1893         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1894                             I40E_GLPRT_GOTCL(hw->port),
1895                             pf->offset_loaded, &os->eth.tx_bytes,
1896                             &ns->eth.tx_bytes);
1897         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1898                             I40E_GLPRT_UPTCL(hw->port),
1899                             pf->offset_loaded, &os->eth.tx_unicast,
1900                             &ns->eth.tx_unicast);
1901         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1902                             I40E_GLPRT_MPTCL(hw->port),
1903                             pf->offset_loaded, &os->eth.tx_multicast,
1904                             &ns->eth.tx_multicast);
1905         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1906                             I40E_GLPRT_BPTCL(hw->port),
1907                             pf->offset_loaded, &os->eth.tx_broadcast,
1908                             &ns->eth.tx_broadcast);
1909         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1910                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1911         /* GLPRT_TEPC not supported */
1912
1913         /* additional port specific stats */
1914         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1915                             pf->offset_loaded, &os->tx_dropped_link_down,
1916                             &ns->tx_dropped_link_down);
1917         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1918                             pf->offset_loaded, &os->crc_errors,
1919                             &ns->crc_errors);
1920         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1921                             pf->offset_loaded, &os->illegal_bytes,
1922                             &ns->illegal_bytes);
1923         /* GLPRT_ERRBC not supported */
1924         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1925                             pf->offset_loaded, &os->mac_local_faults,
1926                             &ns->mac_local_faults);
1927         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1928                             pf->offset_loaded, &os->mac_remote_faults,
1929                             &ns->mac_remote_faults);
1930         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1931                             pf->offset_loaded, &os->rx_length_errors,
1932                             &ns->rx_length_errors);
1933         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1934                             pf->offset_loaded, &os->link_xon_rx,
1935                             &ns->link_xon_rx);
1936         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1937                             pf->offset_loaded, &os->link_xoff_rx,
1938                             &ns->link_xoff_rx);
1939         for (i = 0; i < 8; i++) {
1940                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1941                                     pf->offset_loaded,
1942                                     &os->priority_xon_rx[i],
1943                                     &ns->priority_xon_rx[i]);
1944                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1945                                     pf->offset_loaded,
1946                                     &os->priority_xoff_rx[i],
1947                                     &ns->priority_xoff_rx[i]);
1948         }
1949         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1950                             pf->offset_loaded, &os->link_xon_tx,
1951                             &ns->link_xon_tx);
1952         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1953                             pf->offset_loaded, &os->link_xoff_tx,
1954                             &ns->link_xoff_tx);
1955         for (i = 0; i < 8; i++) {
1956                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1957                                     pf->offset_loaded,
1958                                     &os->priority_xon_tx[i],
1959                                     &ns->priority_xon_tx[i]);
1960                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1961                                     pf->offset_loaded,
1962                                     &os->priority_xoff_tx[i],
1963                                     &ns->priority_xoff_tx[i]);
1964                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1965                                     pf->offset_loaded,
1966                                     &os->priority_xon_2_xoff[i],
1967                                     &ns->priority_xon_2_xoff[i]);
1968         }
1969         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1970                             I40E_GLPRT_PRC64L(hw->port),
1971                             pf->offset_loaded, &os->rx_size_64,
1972                             &ns->rx_size_64);
1973         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1974                             I40E_GLPRT_PRC127L(hw->port),
1975                             pf->offset_loaded, &os->rx_size_127,
1976                             &ns->rx_size_127);
1977         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1978                             I40E_GLPRT_PRC255L(hw->port),
1979                             pf->offset_loaded, &os->rx_size_255,
1980                             &ns->rx_size_255);
1981         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1982                             I40E_GLPRT_PRC511L(hw->port),
1983                             pf->offset_loaded, &os->rx_size_511,
1984                             &ns->rx_size_511);
1985         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1986                             I40E_GLPRT_PRC1023L(hw->port),
1987                             pf->offset_loaded, &os->rx_size_1023,
1988                             &ns->rx_size_1023);
1989         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1990                             I40E_GLPRT_PRC1522L(hw->port),
1991                             pf->offset_loaded, &os->rx_size_1522,
1992                             &ns->rx_size_1522);
1993         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1994                             I40E_GLPRT_PRC9522L(hw->port),
1995                             pf->offset_loaded, &os->rx_size_big,
1996                             &ns->rx_size_big);
1997         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1998                             pf->offset_loaded, &os->rx_undersize,
1999                             &ns->rx_undersize);
2000         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2001                             pf->offset_loaded, &os->rx_fragments,
2002                             &ns->rx_fragments);
2003         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2004                             pf->offset_loaded, &os->rx_oversize,
2005                             &ns->rx_oversize);
2006         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2007                             pf->offset_loaded, &os->rx_jabber,
2008                             &ns->rx_jabber);
2009         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2010                             I40E_GLPRT_PTC64L(hw->port),
2011                             pf->offset_loaded, &os->tx_size_64,
2012                             &ns->tx_size_64);
2013         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2014                             I40E_GLPRT_PTC127L(hw->port),
2015                             pf->offset_loaded, &os->tx_size_127,
2016                             &ns->tx_size_127);
2017         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2018                             I40E_GLPRT_PTC255L(hw->port),
2019                             pf->offset_loaded, &os->tx_size_255,
2020                             &ns->tx_size_255);
2021         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2022                             I40E_GLPRT_PTC511L(hw->port),
2023                             pf->offset_loaded, &os->tx_size_511,
2024                             &ns->tx_size_511);
2025         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2026                             I40E_GLPRT_PTC1023L(hw->port),
2027                             pf->offset_loaded, &os->tx_size_1023,
2028                             &ns->tx_size_1023);
2029         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2030                             I40E_GLPRT_PTC1522L(hw->port),
2031                             pf->offset_loaded, &os->tx_size_1522,
2032                             &ns->tx_size_1522);
2033         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2034                             I40E_GLPRT_PTC9522L(hw->port),
2035                             pf->offset_loaded, &os->tx_size_big,
2036                             &ns->tx_size_big);
2037         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2038                            pf->offset_loaded,
2039                            &os->fd_sb_match, &ns->fd_sb_match);
2040         /* GLPRT_MSPDC not supported */
2041         /* GLPRT_XEC not supported */
2042
2043         pf->offset_loaded = true;
2044
2045         if (pf->main_vsi)
2046                 i40e_update_vsi_stats(pf->main_vsi);
2047 }
2048
2049 /* Get all statistics of a port */
2050 static void
2051 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2052 {
2053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2056         unsigned i;
2057
2058         /* call read registers - updates values, now write them to struct */
2059         i40e_read_stats_registers(pf, hw);
2060
2061         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2062                         pf->main_vsi->eth_stats.rx_multicast +
2063                         pf->main_vsi->eth_stats.rx_broadcast -
2064                         pf->main_vsi->eth_stats.rx_discards;
2065         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2066                         pf->main_vsi->eth_stats.tx_multicast +
2067                         pf->main_vsi->eth_stats.tx_broadcast;
2068         stats->ibytes   = ns->eth.rx_bytes;
2069         stats->obytes   = ns->eth.tx_bytes;
2070         stats->oerrors  = ns->eth.tx_errors +
2071                         pf->main_vsi->eth_stats.tx_errors;
2072         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2073
2074         /* Rx Errors */
2075         stats->imissed  = ns->eth.rx_discards +
2076                         pf->main_vsi->eth_stats.rx_discards;
2077         stats->ierrors  = ns->crc_errors +
2078                         ns->rx_length_errors + ns->rx_undersize +
2079                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2080                         stats->imissed;
2081
2082         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2083         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2084         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2085         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2086         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2087         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2088         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2089                     ns->eth.rx_unknown_protocol);
2090         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2091         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2092         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2093         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2094         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2095         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2096
2097         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2098                     ns->tx_dropped_link_down);
2099         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2100         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2101                     ns->illegal_bytes);
2102         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2103         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2104                     ns->mac_local_faults);
2105         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2106                     ns->mac_remote_faults);
2107         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2108                     ns->rx_length_errors);
2109         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2110         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2111         for (i = 0; i < 8; i++) {
2112                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2113                                 i, ns->priority_xon_rx[i]);
2114                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2115                                 i, ns->priority_xoff_rx[i]);
2116         }
2117         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2118         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2119         for (i = 0; i < 8; i++) {
2120                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2121                                 i, ns->priority_xon_tx[i]);
2122                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2123                                 i, ns->priority_xoff_tx[i]);
2124                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2125                                 i, ns->priority_xon_2_xoff[i]);
2126         }
2127         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2128         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2129         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2130         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2131         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2132         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2133         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2134         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2135         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2136         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2137         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2138         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2139         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2140         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2141         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2142         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2143         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2144         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2145         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2146                         ns->mac_short_packet_dropped);
2147         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2148                     ns->checksum_error);
2149         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2150         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2151 }
2152
2153 /* Reset the statistics */
2154 static void
2155 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2156 {
2157         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159
2160         /* Mark PF and VSI stats to update the offset, aka "reset" */
2161         pf->offset_loaded = false;
2162         if (pf->main_vsi)
2163                 pf->main_vsi->offset_loaded = false;
2164
2165         /* read the stats, reading current register values into offset */
2166         i40e_read_stats_registers(pf, hw);
2167 }
2168
2169 static uint32_t
2170 i40e_xstats_calc_num(void)
2171 {
2172         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2173                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2174                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2175 }
2176
2177 static int
2178 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2179                     unsigned n)
2180 {
2181         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183         unsigned i, count, prio;
2184         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2185
2186         count = i40e_xstats_calc_num();
2187         if (n < count)
2188                 return count;
2189
2190         i40e_read_stats_registers(pf, hw);
2191
2192         if (xstats == NULL)
2193                 return 0;
2194
2195         count = 0;
2196
2197         /* Get stats from i40e_eth_stats struct */
2198         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2199                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2200                          "%s", rte_i40e_stats_strings[i].name);
2201                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2202                         rte_i40e_stats_strings[i].offset);
2203                 count++;
2204         }
2205
2206         /* Get individiual stats from i40e_hw_port struct */
2207         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2208                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2209                          "%s", rte_i40e_hw_port_strings[i].name);
2210                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2211                                 rte_i40e_hw_port_strings[i].offset);
2212                 count++;
2213         }
2214
2215         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2216                 for (prio = 0; prio < 8; prio++) {
2217                         snprintf(xstats[count].name,
2218                                  sizeof(xstats[count].name),
2219                                  "rx_priority%u_%s", prio,
2220                                  rte_i40e_rxq_prio_strings[i].name);
2221                         xstats[count].value =
2222                                 *(uint64_t *)(((char *)hw_stats) +
2223                                 rte_i40e_rxq_prio_strings[i].offset +
2224                                 (sizeof(uint64_t) * prio));
2225                         count++;
2226                 }
2227         }
2228
2229         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2230                 for (prio = 0; prio < 8; prio++) {
2231                         snprintf(xstats[count].name,
2232                                  sizeof(xstats[count].name),
2233                                  "tx_priority%u_%s", prio,
2234                                  rte_i40e_txq_prio_strings[i].name);
2235                         xstats[count].value =
2236                                 *(uint64_t *)(((char *)hw_stats) +
2237                                 rte_i40e_txq_prio_strings[i].offset +
2238                                 (sizeof(uint64_t) * prio));
2239                         count++;
2240                 }
2241         }
2242
2243         return count;
2244 }
2245
2246 static int
2247 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2248                                  __rte_unused uint16_t queue_id,
2249                                  __rte_unused uint8_t stat_idx,
2250                                  __rte_unused uint8_t is_rx)
2251 {
2252         PMD_INIT_FUNC_TRACE();
2253
2254         return -ENOSYS;
2255 }
2256
2257 static void
2258 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2259 {
2260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2261         struct i40e_vsi *vsi = pf->main_vsi;
2262
2263         dev_info->max_rx_queues = vsi->nb_qps;
2264         dev_info->max_tx_queues = vsi->nb_qps;
2265         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2266         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2267         dev_info->max_mac_addrs = vsi->max_macaddrs;
2268         dev_info->max_vfs = dev->pci_dev->max_vfs;
2269         dev_info->rx_offload_capa =
2270                 DEV_RX_OFFLOAD_VLAN_STRIP |
2271                 DEV_RX_OFFLOAD_QINQ_STRIP |
2272                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2273                 DEV_RX_OFFLOAD_UDP_CKSUM |
2274                 DEV_RX_OFFLOAD_TCP_CKSUM;
2275         dev_info->tx_offload_capa =
2276                 DEV_TX_OFFLOAD_VLAN_INSERT |
2277                 DEV_TX_OFFLOAD_QINQ_INSERT |
2278                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2279                 DEV_TX_OFFLOAD_UDP_CKSUM |
2280                 DEV_TX_OFFLOAD_TCP_CKSUM |
2281                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2282                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2283                 DEV_TX_OFFLOAD_TCP_TSO;
2284         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2285                                                 sizeof(uint32_t);
2286         dev_info->reta_size = pf->hash_lut_size;
2287         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2288
2289         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2290                 .rx_thresh = {
2291                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2292                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2293                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2294                 },
2295                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2296                 .rx_drop_en = 0,
2297         };
2298
2299         dev_info->default_txconf = (struct rte_eth_txconf) {
2300                 .tx_thresh = {
2301                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2302                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2303                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2304                 },
2305                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2306                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2307                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2308                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2309         };
2310
2311         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2312                 .nb_max = I40E_MAX_RING_DESC,
2313                 .nb_min = I40E_MIN_RING_DESC,
2314                 .nb_align = I40E_ALIGN_RING_DESC,
2315         };
2316
2317         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2318                 .nb_max = I40E_MAX_RING_DESC,
2319                 .nb_min = I40E_MIN_RING_DESC,
2320                 .nb_align = I40E_ALIGN_RING_DESC,
2321         };
2322
2323         if (pf->flags & I40E_FLAG_VMDQ) {
2324                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2325                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2326                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2327                                                 pf->max_nb_vmdq_vsi;
2328                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2329                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2330                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2331         }
2332 }
2333
2334 static int
2335 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2336 {
2337         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2338         struct i40e_vsi *vsi = pf->main_vsi;
2339         PMD_INIT_FUNC_TRACE();
2340
2341         if (on)
2342                 return i40e_vsi_add_vlan(vsi, vlan_id);
2343         else
2344                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2345 }
2346
2347 static int
2348 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2349                    enum rte_vlan_type vlan_type,
2350                    uint16_t tpid)
2351 {
2352         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2353         uint64_t reg_r = 0, reg_w = 0;
2354         uint16_t reg_id = 0;
2355         int ret = 0;
2356
2357         switch (vlan_type) {
2358         case ETH_VLAN_TYPE_OUTER:
2359                 reg_id = 2;
2360                 break;
2361         case ETH_VLAN_TYPE_INNER:
2362                 reg_id = 3;
2363                 break;
2364         default:
2365                 ret = -EINVAL;
2366                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2367                 return ret;
2368         }
2369         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2370                                           &reg_r, NULL);
2371         if (ret != I40E_SUCCESS) {
2372                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2373                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2374                 ret = -EIO;
2375                 return ret;
2376         }
2377         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2378                     "0x%08"PRIx64"", reg_id, reg_r);
2379
2380         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2381         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2382         if (reg_r == reg_w) {
2383                 ret = 0;
2384                 PMD_DRV_LOG(DEBUG, "No need to write");
2385                 return ret;
2386         }
2387
2388         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2389                                            reg_w, NULL);
2390         if (ret != I40E_SUCCESS) {
2391                 ret = -EIO;
2392                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2393                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2394                 return ret;
2395         }
2396         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2397                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2398
2399         return ret;
2400 }
2401
2402 static void
2403 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2404 {
2405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2406         struct i40e_vsi *vsi = pf->main_vsi;
2407
2408         if (mask & ETH_VLAN_FILTER_MASK) {
2409                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2410                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2411                 else
2412                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2413         }
2414
2415         if (mask & ETH_VLAN_STRIP_MASK) {
2416                 /* Enable or disable VLAN stripping */
2417                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2418                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2419                 else
2420                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2421         }
2422
2423         if (mask & ETH_VLAN_EXTEND_MASK) {
2424                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2425                         i40e_vsi_config_double_vlan(vsi, TRUE);
2426                 else
2427                         i40e_vsi_config_double_vlan(vsi, FALSE);
2428         }
2429 }
2430
2431 static void
2432 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2433                           __rte_unused uint16_t queue,
2434                           __rte_unused int on)
2435 {
2436         PMD_INIT_FUNC_TRACE();
2437 }
2438
2439 static int
2440 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2441 {
2442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2443         struct i40e_vsi *vsi = pf->main_vsi;
2444         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2445         struct i40e_vsi_vlan_pvid_info info;
2446
2447         memset(&info, 0, sizeof(info));
2448         info.on = on;
2449         if (info.on)
2450                 info.config.pvid = pvid;
2451         else {
2452                 info.config.reject.tagged =
2453                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2454                 info.config.reject.untagged =
2455                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2456         }
2457
2458         return i40e_vsi_vlan_pvid_set(vsi, &info);
2459 }
2460
2461 static int
2462 i40e_dev_led_on(struct rte_eth_dev *dev)
2463 {
2464         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465         uint32_t mode = i40e_led_get(hw);
2466
2467         if (mode == 0)
2468                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2469
2470         return 0;
2471 }
2472
2473 static int
2474 i40e_dev_led_off(struct rte_eth_dev *dev)
2475 {
2476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477         uint32_t mode = i40e_led_get(hw);
2478
2479         if (mode != 0)
2480                 i40e_led_set(hw, 0, false);
2481
2482         return 0;
2483 }
2484
2485 static int
2486 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2487 {
2488         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2490
2491         fc_conf->pause_time = pf->fc_conf.pause_time;
2492         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2493         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2494
2495          /* Return current mode according to actual setting*/
2496         switch (hw->fc.current_mode) {
2497         case I40E_FC_FULL:
2498                 fc_conf->mode = RTE_FC_FULL;
2499                 break;
2500         case I40E_FC_TX_PAUSE:
2501                 fc_conf->mode = RTE_FC_TX_PAUSE;
2502                 break;
2503         case I40E_FC_RX_PAUSE:
2504                 fc_conf->mode = RTE_FC_RX_PAUSE;
2505                 break;
2506         case I40E_FC_NONE:
2507         default:
2508                 fc_conf->mode = RTE_FC_NONE;
2509         };
2510
2511         return 0;
2512 }
2513
2514 static int
2515 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2516 {
2517         uint32_t mflcn_reg, fctrl_reg, reg;
2518         uint32_t max_high_water;
2519         uint8_t i, aq_failure;
2520         int err;
2521         struct i40e_hw *hw;
2522         struct i40e_pf *pf;
2523         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2524                 [RTE_FC_NONE] = I40E_FC_NONE,
2525                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2526                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2527                 [RTE_FC_FULL] = I40E_FC_FULL
2528         };
2529
2530         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2531
2532         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2533         if ((fc_conf->high_water > max_high_water) ||
2534                         (fc_conf->high_water < fc_conf->low_water)) {
2535                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2536                         "High_water must <= %d.", max_high_water);
2537                 return -EINVAL;
2538         }
2539
2540         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2542         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2543
2544         pf->fc_conf.pause_time = fc_conf->pause_time;
2545         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2546         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2547
2548         PMD_INIT_FUNC_TRACE();
2549
2550         /* All the link flow control related enable/disable register
2551          * configuration is handle by the F/W
2552          */
2553         err = i40e_set_fc(hw, &aq_failure, true);
2554         if (err < 0)
2555                 return -ENOSYS;
2556
2557         if (i40e_is_40G_device(hw->device_id)) {
2558                 /* Configure flow control refresh threshold,
2559                  * the value for stat_tx_pause_refresh_timer[8]
2560                  * is used for global pause operation.
2561                  */
2562
2563                 I40E_WRITE_REG(hw,
2564                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2565                                pf->fc_conf.pause_time);
2566
2567                 /* configure the timer value included in transmitted pause
2568                  * frame,
2569                  * the value for stat_tx_pause_quanta[8] is used for global
2570                  * pause operation
2571                  */
2572                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2573                                pf->fc_conf.pause_time);
2574
2575                 fctrl_reg = I40E_READ_REG(hw,
2576                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2577
2578                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2579                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2580                 else
2581                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2582
2583                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2584                                fctrl_reg);
2585         } else {
2586                 /* Configure pause time (2 TCs per register) */
2587                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2588                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2589                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2590
2591                 /* Configure flow control refresh threshold value */
2592                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2593                                pf->fc_conf.pause_time / 2);
2594
2595                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2596
2597                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2598                  *depending on configuration
2599                  */
2600                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2601                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2602                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2603                 } else {
2604                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2605                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2606                 }
2607
2608                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2609         }
2610
2611         /* config the water marker both based on the packets and bytes */
2612         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2613                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2614                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2615         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2616                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2617                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2618         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2619                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2620                        << I40E_KILOSHIFT);
2621         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2622                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2623                        << I40E_KILOSHIFT);
2624
2625         I40E_WRITE_FLUSH(hw);
2626
2627         return 0;
2628 }
2629
2630 static int
2631 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2632                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2633 {
2634         PMD_INIT_FUNC_TRACE();
2635
2636         return -ENOSYS;
2637 }
2638
2639 /* Add a MAC address, and update filters */
2640 static void
2641 i40e_macaddr_add(struct rte_eth_dev *dev,
2642                  struct ether_addr *mac_addr,
2643                  __rte_unused uint32_t index,
2644                  uint32_t pool)
2645 {
2646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2647         struct i40e_mac_filter_info mac_filter;
2648         struct i40e_vsi *vsi;
2649         int ret;
2650
2651         /* If VMDQ not enabled or configured, return */
2652         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2653                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2654                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2655                         pool);
2656                 return;
2657         }
2658
2659         if (pool > pf->nb_cfg_vmdq_vsi) {
2660                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2661                                 pool, pf->nb_cfg_vmdq_vsi);
2662                 return;
2663         }
2664
2665         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2666         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2667                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2668         else
2669                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2670
2671         if (pool == 0)
2672                 vsi = pf->main_vsi;
2673         else
2674                 vsi = pf->vmdq[pool - 1].vsi;
2675
2676         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2677         if (ret != I40E_SUCCESS) {
2678                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2679                 return;
2680         }
2681 }
2682
2683 /* Remove a MAC address, and update filters */
2684 static void
2685 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2686 {
2687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2688         struct i40e_vsi *vsi;
2689         struct rte_eth_dev_data *data = dev->data;
2690         struct ether_addr *macaddr;
2691         int ret;
2692         uint32_t i;
2693         uint64_t pool_sel;
2694
2695         macaddr = &(data->mac_addrs[index]);
2696
2697         pool_sel = dev->data->mac_pool_sel[index];
2698
2699         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2700                 if (pool_sel & (1ULL << i)) {
2701                         if (i == 0)
2702                                 vsi = pf->main_vsi;
2703                         else {
2704                                 /* No VMDQ pool enabled or configured */
2705                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2706                                         (i > pf->nb_cfg_vmdq_vsi)) {
2707                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2708                                                         "/configured");
2709                                         return;
2710                                 }
2711                                 vsi = pf->vmdq[i - 1].vsi;
2712                         }
2713                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2714
2715                         if (ret) {
2716                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2717                                 return;
2718                         }
2719                 }
2720         }
2721 }
2722
2723 /* Set perfect match or hash match of MAC and VLAN for a VF */
2724 static int
2725 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2726                  struct rte_eth_mac_filter *filter,
2727                  bool add)
2728 {
2729         struct i40e_hw *hw;
2730         struct i40e_mac_filter_info mac_filter;
2731         struct ether_addr old_mac;
2732         struct ether_addr *new_mac;
2733         struct i40e_pf_vf *vf = NULL;
2734         uint16_t vf_id;
2735         int ret;
2736
2737         if (pf == NULL) {
2738                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2739                 return -EINVAL;
2740         }
2741         hw = I40E_PF_TO_HW(pf);
2742
2743         if (filter == NULL) {
2744                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2745                 return -EINVAL;
2746         }
2747
2748         new_mac = &filter->mac_addr;
2749
2750         if (is_zero_ether_addr(new_mac)) {
2751                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2752                 return -EINVAL;
2753         }
2754
2755         vf_id = filter->dst_id;
2756
2757         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2758                 PMD_DRV_LOG(ERR, "Invalid argument.");
2759                 return -EINVAL;
2760         }
2761         vf = &pf->vfs[vf_id];
2762
2763         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2764                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2765                 return -EINVAL;
2766         }
2767
2768         if (add) {
2769                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2770                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2771                                 ETHER_ADDR_LEN);
2772                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2773                                  ETHER_ADDR_LEN);
2774
2775                 mac_filter.filter_type = filter->filter_type;
2776                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2777                 if (ret != I40E_SUCCESS) {
2778                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2779                         return -1;
2780                 }
2781                 ether_addr_copy(new_mac, &pf->dev_addr);
2782         } else {
2783                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2784                                 ETHER_ADDR_LEN);
2785                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2786                 if (ret != I40E_SUCCESS) {
2787                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2788                         return -1;
2789                 }
2790
2791                 /* Clear device address as it has been removed */
2792                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2793                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2794         }
2795
2796         return 0;
2797 }
2798
2799 /* MAC filter handle */
2800 static int
2801 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2802                 void *arg)
2803 {
2804         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2805         struct rte_eth_mac_filter *filter;
2806         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2807         int ret = I40E_NOT_SUPPORTED;
2808
2809         filter = (struct rte_eth_mac_filter *)(arg);
2810
2811         switch (filter_op) {
2812         case RTE_ETH_FILTER_NOP:
2813                 ret = I40E_SUCCESS;
2814                 break;
2815         case RTE_ETH_FILTER_ADD:
2816                 i40e_pf_disable_irq0(hw);
2817                 if (filter->is_vf)
2818                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2819                 i40e_pf_enable_irq0(hw);
2820                 break;
2821         case RTE_ETH_FILTER_DELETE:
2822                 i40e_pf_disable_irq0(hw);
2823                 if (filter->is_vf)
2824                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2825                 i40e_pf_enable_irq0(hw);
2826                 break;
2827         default:
2828                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2829                 ret = I40E_ERR_PARAM;
2830                 break;
2831         }
2832
2833         return ret;
2834 }
2835
2836 static int
2837 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2838 {
2839         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2840         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2841         int ret;
2842
2843         if (!lut)
2844                 return -EINVAL;
2845
2846         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2847                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2848                                           lut, lut_size);
2849                 if (ret) {
2850                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2851                         return ret;
2852                 }
2853         } else {
2854                 uint32_t *lut_dw = (uint32_t *)lut;
2855                 uint16_t i, lut_size_dw = lut_size / 4;
2856
2857                 for (i = 0; i < lut_size_dw; i++)
2858                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2859         }
2860
2861         return 0;
2862 }
2863
2864 static int
2865 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2866 {
2867         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2868         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2869         int ret;
2870
2871         if (!vsi || !lut)
2872                 return -EINVAL;
2873
2874         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2875                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2876                                           lut, lut_size);
2877                 if (ret) {
2878                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2879                         return ret;
2880                 }
2881         } else {
2882                 uint32_t *lut_dw = (uint32_t *)lut;
2883                 uint16_t i, lut_size_dw = lut_size / 4;
2884
2885                 for (i = 0; i < lut_size_dw; i++)
2886                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2887                 I40E_WRITE_FLUSH(hw);
2888         }
2889
2890         return 0;
2891 }
2892
2893 static int
2894 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2895                          struct rte_eth_rss_reta_entry64 *reta_conf,
2896                          uint16_t reta_size)
2897 {
2898         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2899         uint16_t i, lut_size = pf->hash_lut_size;
2900         uint16_t idx, shift;
2901         uint8_t *lut;
2902         int ret;
2903
2904         if (reta_size != lut_size ||
2905                 reta_size > ETH_RSS_RETA_SIZE_512) {
2906                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2907                         "(%d) doesn't match the number hardware can supported "
2908                                         "(%d)\n", reta_size, lut_size);
2909                 return -EINVAL;
2910         }
2911
2912         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2913         if (!lut) {
2914                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2915                 return -ENOMEM;
2916         }
2917         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2918         if (ret)
2919                 goto out;
2920         for (i = 0; i < reta_size; i++) {
2921                 idx = i / RTE_RETA_GROUP_SIZE;
2922                 shift = i % RTE_RETA_GROUP_SIZE;
2923                 if (reta_conf[idx].mask & (1ULL << shift))
2924                         lut[i] = reta_conf[idx].reta[shift];
2925         }
2926         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2927
2928 out:
2929         rte_free(lut);
2930
2931         return ret;
2932 }
2933
2934 static int
2935 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2936                         struct rte_eth_rss_reta_entry64 *reta_conf,
2937                         uint16_t reta_size)
2938 {
2939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2940         uint16_t i, lut_size = pf->hash_lut_size;
2941         uint16_t idx, shift;
2942         uint8_t *lut;
2943         int ret;
2944
2945         if (reta_size != lut_size ||
2946                 reta_size > ETH_RSS_RETA_SIZE_512) {
2947                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2948                         "(%d) doesn't match the number hardware can supported "
2949                                         "(%d)\n", reta_size, lut_size);
2950                 return -EINVAL;
2951         }
2952
2953         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2954         if (!lut) {
2955                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2956                 return -ENOMEM;
2957         }
2958
2959         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2960         if (ret)
2961                 goto out;
2962         for (i = 0; i < reta_size; i++) {
2963                 idx = i / RTE_RETA_GROUP_SIZE;
2964                 shift = i % RTE_RETA_GROUP_SIZE;
2965                 if (reta_conf[idx].mask & (1ULL << shift))
2966                         reta_conf[idx].reta[shift] = lut[i];
2967         }
2968
2969 out:
2970         rte_free(lut);
2971
2972         return ret;
2973 }
2974
2975 /**
2976  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2977  * @hw:   pointer to the HW structure
2978  * @mem:  pointer to mem struct to fill out
2979  * @size: size of memory requested
2980  * @alignment: what to align the allocation to
2981  **/
2982 enum i40e_status_code
2983 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2984                         struct i40e_dma_mem *mem,
2985                         u64 size,
2986                         u32 alignment)
2987 {
2988         const struct rte_memzone *mz = NULL;
2989         char z_name[RTE_MEMZONE_NAMESIZE];
2990
2991         if (!mem)
2992                 return I40E_ERR_PARAM;
2993
2994         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2995         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2996                                          alignment, RTE_PGSIZE_2M);
2997         if (!mz)
2998                 return I40E_ERR_NO_MEMORY;
2999
3000         mem->size = size;
3001         mem->va = mz->addr;
3002         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3003         mem->zone = (const void *)mz;
3004         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3005                     "%"PRIu64, mz->name, mem->pa);
3006
3007         return I40E_SUCCESS;
3008 }
3009
3010 /**
3011  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3012  * @hw:   pointer to the HW structure
3013  * @mem:  ptr to mem struct to free
3014  **/
3015 enum i40e_status_code
3016 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3017                     struct i40e_dma_mem *mem)
3018 {
3019         if (!mem)
3020                 return I40E_ERR_PARAM;
3021
3022         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3023                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3024                     mem->pa);
3025         rte_memzone_free((const struct rte_memzone *)mem->zone);
3026         mem->zone = NULL;
3027         mem->va = NULL;
3028         mem->pa = (u64)0;
3029
3030         return I40E_SUCCESS;
3031 }
3032
3033 /**
3034  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3035  * @hw:   pointer to the HW structure
3036  * @mem:  pointer to mem struct to fill out
3037  * @size: size of memory requested
3038  **/
3039 enum i40e_status_code
3040 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3041                          struct i40e_virt_mem *mem,
3042                          u32 size)
3043 {
3044         if (!mem)
3045                 return I40E_ERR_PARAM;
3046
3047         mem->size = size;
3048         mem->va = rte_zmalloc("i40e", size, 0);
3049
3050         if (mem->va)
3051                 return I40E_SUCCESS;
3052         else
3053                 return I40E_ERR_NO_MEMORY;
3054 }
3055
3056 /**
3057  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3058  * @hw:   pointer to the HW structure
3059  * @mem:  pointer to mem struct to free
3060  **/
3061 enum i40e_status_code
3062 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3063                      struct i40e_virt_mem *mem)
3064 {
3065         if (!mem)
3066                 return I40E_ERR_PARAM;
3067
3068         rte_free(mem->va);
3069         mem->va = NULL;
3070
3071         return I40E_SUCCESS;
3072 }
3073
3074 void
3075 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3076 {
3077         rte_spinlock_init(&sp->spinlock);
3078 }
3079
3080 void
3081 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3082 {
3083         rte_spinlock_lock(&sp->spinlock);
3084 }
3085
3086 void
3087 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3088 {
3089         rte_spinlock_unlock(&sp->spinlock);
3090 }
3091
3092 void
3093 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3094 {
3095         return;
3096 }
3097
3098 /**
3099  * Get the hardware capabilities, which will be parsed
3100  * and saved into struct i40e_hw.
3101  */
3102 static int
3103 i40e_get_cap(struct i40e_hw *hw)
3104 {
3105         struct i40e_aqc_list_capabilities_element_resp *buf;
3106         uint16_t len, size = 0;
3107         int ret;
3108
3109         /* Calculate a huge enough buff for saving response data temporarily */
3110         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3111                                                 I40E_MAX_CAP_ELE_NUM;
3112         buf = rte_zmalloc("i40e", len, 0);
3113         if (!buf) {
3114                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3115                 return I40E_ERR_NO_MEMORY;
3116         }
3117
3118         /* Get, parse the capabilities and save it to hw */
3119         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3120                         i40e_aqc_opc_list_func_capabilities, NULL);
3121         if (ret != I40E_SUCCESS)
3122                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3123
3124         /* Free the temporary buffer after being used */
3125         rte_free(buf);
3126
3127         return ret;
3128 }
3129
3130 static int
3131 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3132 {
3133         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3134         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3135         uint16_t qp_count = 0, vsi_count = 0;
3136
3137         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3138                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3139                 return -EINVAL;
3140         }
3141         /* Add the parameter init for LFC */
3142         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3143         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3144         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3145
3146         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3147         pf->max_num_vsi = hw->func_caps.num_vsis;
3148         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3149         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3150         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3151
3152         /* FDir queue/VSI allocation */
3153         pf->fdir_qp_offset = 0;
3154         if (hw->func_caps.fd) {
3155                 pf->flags |= I40E_FLAG_FDIR;
3156                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3157         } else {
3158                 pf->fdir_nb_qps = 0;
3159         }
3160         qp_count += pf->fdir_nb_qps;
3161         vsi_count += 1;
3162
3163         /* LAN queue/VSI allocation */
3164         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3165         if (!hw->func_caps.rss) {
3166                 pf->lan_nb_qps = 1;
3167         } else {
3168                 pf->flags |= I40E_FLAG_RSS;
3169                 if (hw->mac.type == I40E_MAC_X722)
3170                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3171                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3172         }
3173         qp_count += pf->lan_nb_qps;
3174         vsi_count += 1;
3175
3176         /* VF queue/VSI allocation */
3177         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3178         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3179                 pf->flags |= I40E_FLAG_SRIOV;
3180                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3181                 pf->vf_num = dev->pci_dev->max_vfs;
3182                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3183                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3184                             pf->vf_nb_qps * pf->vf_num);
3185         } else {
3186                 pf->vf_nb_qps = 0;
3187                 pf->vf_num = 0;
3188         }
3189         qp_count += pf->vf_nb_qps * pf->vf_num;
3190         vsi_count += pf->vf_num;
3191
3192         /* VMDq queue/VSI allocation */
3193         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3194         pf->vmdq_nb_qps = 0;
3195         pf->max_nb_vmdq_vsi = 0;
3196         if (hw->func_caps.vmdq) {
3197                 if (qp_count < hw->func_caps.num_tx_qp &&
3198                         vsi_count < hw->func_caps.num_vsis) {
3199                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3200                                 qp_count) / pf->vmdq_nb_qp_max;
3201
3202                         /* Limit the maximum number of VMDq vsi to the maximum
3203                          * ethdev can support
3204                          */
3205                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3206                                 hw->func_caps.num_vsis - vsi_count);
3207                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3208                                 ETH_64_POOLS);
3209                         if (pf->max_nb_vmdq_vsi) {
3210                                 pf->flags |= I40E_FLAG_VMDQ;
3211                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3212                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3213                                             "per VMDQ VSI, in total %u queues",
3214                                             pf->max_nb_vmdq_vsi,
3215                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3216                                             pf->max_nb_vmdq_vsi);
3217                         } else {
3218                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3219                                             "VMDq");
3220                         }
3221                 } else {
3222                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3223                 }
3224         }
3225         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3226         vsi_count += pf->max_nb_vmdq_vsi;
3227
3228         if (hw->func_caps.dcb)
3229                 pf->flags |= I40E_FLAG_DCB;
3230
3231         if (qp_count > hw->func_caps.num_tx_qp) {
3232                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3233                             "the hardware maximum %u", qp_count,
3234                             hw->func_caps.num_tx_qp);
3235                 return -EINVAL;
3236         }
3237         if (vsi_count > hw->func_caps.num_vsis) {
3238                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3239                             "the hardware maximum %u", vsi_count,
3240                             hw->func_caps.num_vsis);
3241                 return -EINVAL;
3242         }
3243
3244         return 0;
3245 }
3246
3247 static int
3248 i40e_pf_get_switch_config(struct i40e_pf *pf)
3249 {
3250         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3251         struct i40e_aqc_get_switch_config_resp *switch_config;
3252         struct i40e_aqc_switch_config_element_resp *element;
3253         uint16_t start_seid = 0, num_reported;
3254         int ret;
3255
3256         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3257                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3258         if (!switch_config) {
3259                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3260                 return -ENOMEM;
3261         }
3262
3263         /* Get the switch configurations */
3264         ret = i40e_aq_get_switch_config(hw, switch_config,
3265                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3266         if (ret != I40E_SUCCESS) {
3267                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3268                 goto fail;
3269         }
3270         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3271         if (num_reported != 1) { /* The number should be 1 */
3272                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3273                 goto fail;
3274         }
3275
3276         /* Parse the switch configuration elements */
3277         element = &(switch_config->element[0]);
3278         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3279                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3280                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3281         } else
3282                 PMD_DRV_LOG(INFO, "Unknown element type");
3283
3284 fail:
3285         rte_free(switch_config);
3286
3287         return ret;
3288 }
3289
3290 static int
3291 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3292                         uint32_t num)
3293 {
3294         struct pool_entry *entry;
3295
3296         if (pool == NULL || num == 0)
3297                 return -EINVAL;
3298
3299         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3300         if (entry == NULL) {
3301                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3302                 return -ENOMEM;
3303         }
3304
3305         /* queue heap initialize */
3306         pool->num_free = num;
3307         pool->num_alloc = 0;
3308         pool->base = base;
3309         LIST_INIT(&pool->alloc_list);
3310         LIST_INIT(&pool->free_list);
3311
3312         /* Initialize element  */
3313         entry->base = 0;
3314         entry->len = num;
3315
3316         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3317         return 0;
3318 }
3319
3320 static void
3321 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3322 {
3323         struct pool_entry *entry;
3324
3325         if (pool == NULL)
3326                 return;
3327
3328         LIST_FOREACH(entry, &pool->alloc_list, next) {
3329                 LIST_REMOVE(entry, next);
3330                 rte_free(entry);
3331         }
3332
3333         LIST_FOREACH(entry, &pool->free_list, next) {
3334                 LIST_REMOVE(entry, next);
3335                 rte_free(entry);
3336         }
3337
3338         pool->num_free = 0;
3339         pool->num_alloc = 0;
3340         pool->base = 0;
3341         LIST_INIT(&pool->alloc_list);
3342         LIST_INIT(&pool->free_list);
3343 }
3344
3345 static int
3346 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3347                        uint32_t base)
3348 {
3349         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3350         uint32_t pool_offset;
3351         int insert;
3352
3353         if (pool == NULL) {
3354                 PMD_DRV_LOG(ERR, "Invalid parameter");
3355                 return -EINVAL;
3356         }
3357
3358         pool_offset = base - pool->base;
3359         /* Lookup in alloc list */
3360         LIST_FOREACH(entry, &pool->alloc_list, next) {
3361                 if (entry->base == pool_offset) {
3362                         valid_entry = entry;
3363                         LIST_REMOVE(entry, next);
3364                         break;
3365                 }
3366         }
3367
3368         /* Not find, return */
3369         if (valid_entry == NULL) {
3370                 PMD_DRV_LOG(ERR, "Failed to find entry");
3371                 return -EINVAL;
3372         }
3373
3374         /**
3375          * Found it, move it to free list  and try to merge.
3376          * In order to make merge easier, always sort it by qbase.
3377          * Find adjacent prev and last entries.
3378          */
3379         prev = next = NULL;
3380         LIST_FOREACH(entry, &pool->free_list, next) {
3381                 if (entry->base > valid_entry->base) {
3382                         next = entry;
3383                         break;
3384                 }
3385                 prev = entry;
3386         }
3387
3388         insert = 0;
3389         /* Try to merge with next one*/
3390         if (next != NULL) {
3391                 /* Merge with next one */
3392                 if (valid_entry->base + valid_entry->len == next->base) {
3393                         next->base = valid_entry->base;
3394                         next->len += valid_entry->len;
3395                         rte_free(valid_entry);
3396                         valid_entry = next;
3397                         insert = 1;
3398                 }
3399         }
3400
3401         if (prev != NULL) {
3402                 /* Merge with previous one */
3403                 if (prev->base + prev->len == valid_entry->base) {
3404                         prev->len += valid_entry->len;
3405                         /* If it merge with next one, remove next node */
3406                         if (insert == 1) {
3407                                 LIST_REMOVE(valid_entry, next);
3408                                 rte_free(valid_entry);
3409                         } else {
3410                                 rte_free(valid_entry);
3411                                 insert = 1;
3412                         }
3413                 }
3414         }
3415
3416         /* Not find any entry to merge, insert */
3417         if (insert == 0) {
3418                 if (prev != NULL)
3419                         LIST_INSERT_AFTER(prev, valid_entry, next);
3420                 else if (next != NULL)
3421                         LIST_INSERT_BEFORE(next, valid_entry, next);
3422                 else /* It's empty list, insert to head */
3423                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3424         }
3425
3426         pool->num_free += valid_entry->len;
3427         pool->num_alloc -= valid_entry->len;
3428
3429         return 0;
3430 }
3431
3432 static int
3433 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3434                        uint16_t num)
3435 {
3436         struct pool_entry *entry, *valid_entry;
3437
3438         if (pool == NULL || num == 0) {
3439                 PMD_DRV_LOG(ERR, "Invalid parameter");
3440                 return -EINVAL;
3441         }
3442
3443         if (pool->num_free < num) {
3444                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3445                             num, pool->num_free);
3446                 return -ENOMEM;
3447         }
3448
3449         valid_entry = NULL;
3450         /* Lookup  in free list and find most fit one */
3451         LIST_FOREACH(entry, &pool->free_list, next) {
3452                 if (entry->len >= num) {
3453                         /* Find best one */
3454                         if (entry->len == num) {
3455                                 valid_entry = entry;
3456                                 break;
3457                         }
3458                         if (valid_entry == NULL || valid_entry->len > entry->len)
3459                                 valid_entry = entry;
3460                 }
3461         }
3462
3463         /* Not find one to satisfy the request, return */
3464         if (valid_entry == NULL) {
3465                 PMD_DRV_LOG(ERR, "No valid entry found");
3466                 return -ENOMEM;
3467         }
3468         /**
3469          * The entry have equal queue number as requested,
3470          * remove it from alloc_list.
3471          */
3472         if (valid_entry->len == num) {
3473                 LIST_REMOVE(valid_entry, next);
3474         } else {
3475                 /**
3476                  * The entry have more numbers than requested,
3477                  * create a new entry for alloc_list and minus its
3478                  * queue base and number in free_list.
3479                  */
3480                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3481                 if (entry == NULL) {
3482                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3483                                     "resource pool");
3484                         return -ENOMEM;
3485                 }
3486                 entry->base = valid_entry->base;
3487                 entry->len = num;
3488                 valid_entry->base += num;
3489                 valid_entry->len -= num;
3490                 valid_entry = entry;
3491         }
3492
3493         /* Insert it into alloc list, not sorted */
3494         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3495
3496         pool->num_free -= valid_entry->len;
3497         pool->num_alloc += valid_entry->len;
3498
3499         return valid_entry->base + pool->base;
3500 }
3501
3502 /**
3503  * bitmap_is_subset - Check whether src2 is subset of src1
3504  **/
3505 static inline int
3506 bitmap_is_subset(uint8_t src1, uint8_t src2)
3507 {
3508         return !((src1 ^ src2) & src2);
3509 }
3510
3511 static enum i40e_status_code
3512 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3513 {
3514         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3515
3516         /* If DCB is not supported, only default TC is supported */
3517         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3518                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3519                 return I40E_NOT_SUPPORTED;
3520         }
3521
3522         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3523                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3524                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3525                             enabled_tcmap);
3526                 return I40E_NOT_SUPPORTED;
3527         }
3528         return I40E_SUCCESS;
3529 }
3530
3531 int
3532 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3533                                 struct i40e_vsi_vlan_pvid_info *info)
3534 {
3535         struct i40e_hw *hw;
3536         struct i40e_vsi_context ctxt;
3537         uint8_t vlan_flags = 0;
3538         int ret;
3539
3540         if (vsi == NULL || info == NULL) {
3541                 PMD_DRV_LOG(ERR, "invalid parameters");
3542                 return I40E_ERR_PARAM;
3543         }
3544
3545         if (info->on) {
3546                 vsi->info.pvid = info->config.pvid;
3547                 /**
3548                  * If insert pvid is enabled, only tagged pkts are
3549                  * allowed to be sent out.
3550                  */
3551                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3552                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3553         } else {
3554                 vsi->info.pvid = 0;
3555                 if (info->config.reject.tagged == 0)
3556                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3557
3558                 if (info->config.reject.untagged == 0)
3559                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3560         }
3561         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3562                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3563         vsi->info.port_vlan_flags |= vlan_flags;
3564         vsi->info.valid_sections =
3565                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3566         memset(&ctxt, 0, sizeof(ctxt));
3567         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3568         ctxt.seid = vsi->seid;
3569
3570         hw = I40E_VSI_TO_HW(vsi);
3571         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3572         if (ret != I40E_SUCCESS)
3573                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3574
3575         return ret;
3576 }
3577
3578 static int
3579 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3580 {
3581         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3582         int i, ret;
3583         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3584
3585         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3586         if (ret != I40E_SUCCESS)
3587                 return ret;
3588
3589         if (!vsi->seid) {
3590                 PMD_DRV_LOG(ERR, "seid not valid");
3591                 return -EINVAL;
3592         }
3593
3594         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3595         tc_bw_data.tc_valid_bits = enabled_tcmap;
3596         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3597                 tc_bw_data.tc_bw_credits[i] =
3598                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3599
3600         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3601         if (ret != I40E_SUCCESS) {
3602                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3603                 return ret;
3604         }
3605
3606         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3607                                         sizeof(vsi->info.qs_handle));
3608         return I40E_SUCCESS;
3609 }
3610
3611 static enum i40e_status_code
3612 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3613                                  struct i40e_aqc_vsi_properties_data *info,
3614                                  uint8_t enabled_tcmap)
3615 {
3616         enum i40e_status_code ret;
3617         int i, total_tc = 0;
3618         uint16_t qpnum_per_tc, bsf, qp_idx;
3619
3620         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3621         if (ret != I40E_SUCCESS)
3622                 return ret;
3623
3624         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3625                 if (enabled_tcmap & (1 << i))
3626                         total_tc++;
3627         vsi->enabled_tc = enabled_tcmap;
3628
3629         /* Number of queues per enabled TC */
3630         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3631         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3632         bsf = rte_bsf32(qpnum_per_tc);
3633
3634         /* Adjust the queue number to actual queues that can be applied */
3635         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3636                 vsi->nb_qps = qpnum_per_tc * total_tc;
3637
3638         /**
3639          * Configure TC and queue mapping parameters, for enabled TC,
3640          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3641          * default queue will serve it.
3642          */
3643         qp_idx = 0;
3644         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3645                 if (vsi->enabled_tc & (1 << i)) {
3646                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3647                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3648                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3649                         qp_idx += qpnum_per_tc;
3650                 } else
3651                         info->tc_mapping[i] = 0;
3652         }
3653
3654         /* Associate queue number with VSI */
3655         if (vsi->type == I40E_VSI_SRIOV) {
3656                 info->mapping_flags |=
3657                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3658                 for (i = 0; i < vsi->nb_qps; i++)
3659                         info->queue_mapping[i] =
3660                                 rte_cpu_to_le_16(vsi->base_queue + i);
3661         } else {
3662                 info->mapping_flags |=
3663                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3664                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3665         }
3666         info->valid_sections |=
3667                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3668
3669         return I40E_SUCCESS;
3670 }
3671
3672 static int
3673 i40e_veb_release(struct i40e_veb *veb)
3674 {
3675         struct i40e_vsi *vsi;
3676         struct i40e_hw *hw;
3677
3678         if (veb == NULL || veb->associate_vsi == NULL)
3679                 return -EINVAL;
3680
3681         if (!TAILQ_EMPTY(&veb->head)) {
3682                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3683                 return -EACCES;
3684         }
3685
3686         vsi = veb->associate_vsi;
3687         hw = I40E_VSI_TO_HW(vsi);
3688
3689         vsi->uplink_seid = veb->uplink_seid;
3690         i40e_aq_delete_element(hw, veb->seid, NULL);
3691         rte_free(veb);
3692         vsi->veb = NULL;
3693         return I40E_SUCCESS;
3694 }
3695
3696 /* Setup a veb */
3697 static struct i40e_veb *
3698 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3699 {
3700         struct i40e_veb *veb;
3701         int ret;
3702         struct i40e_hw *hw;
3703
3704         if (NULL == pf || vsi == NULL) {
3705                 PMD_DRV_LOG(ERR, "veb setup failed, "
3706                             "associated VSI shouldn't null");
3707                 return NULL;
3708         }
3709         hw = I40E_PF_TO_HW(pf);
3710
3711         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3712         if (!veb) {
3713                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3714                 goto fail;
3715         }
3716
3717         veb->associate_vsi = vsi;
3718         TAILQ_INIT(&veb->head);
3719         veb->uplink_seid = vsi->uplink_seid;
3720
3721         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3722                 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3723
3724         if (ret != I40E_SUCCESS) {
3725                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3726                             hw->aq.asq_last_status);
3727                 goto fail;
3728         }
3729
3730         /* get statistics index */
3731         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3732                                 &veb->stats_idx, NULL, NULL, NULL);
3733         if (ret != I40E_SUCCESS) {
3734                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3735                             hw->aq.asq_last_status);
3736                 goto fail;
3737         }
3738
3739         /* Get VEB bandwidth, to be implemented */
3740         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3741         vsi->uplink_seid = veb->seid;
3742
3743         return veb;
3744 fail:
3745         rte_free(veb);
3746         return NULL;
3747 }
3748
3749 int
3750 i40e_vsi_release(struct i40e_vsi *vsi)
3751 {
3752         struct i40e_pf *pf;
3753         struct i40e_hw *hw;
3754         struct i40e_vsi_list *vsi_list;
3755         int ret;
3756         struct i40e_mac_filter *f;
3757
3758         if (!vsi)
3759                 return I40E_SUCCESS;
3760
3761         pf = I40E_VSI_TO_PF(vsi);
3762         hw = I40E_VSI_TO_HW(vsi);
3763
3764         /* VSI has child to attach, release child first */
3765         if (vsi->veb) {
3766                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3767                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3768                                 return -1;
3769                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3770                 }
3771                 i40e_veb_release(vsi->veb);
3772         }
3773
3774         /* Remove all macvlan filters of the VSI */
3775         i40e_vsi_remove_all_macvlan_filter(vsi);
3776         TAILQ_FOREACH(f, &vsi->mac_list, next)
3777                 rte_free(f);
3778
3779         if (vsi->type != I40E_VSI_MAIN) {
3780                 /* Remove vsi from parent's sibling list */
3781                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3782                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3783                         return I40E_ERR_PARAM;
3784                 }
3785                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3786                                 &vsi->sib_vsi_list, list);
3787
3788                 /* Remove all switch element of the VSI */
3789                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3790                 if (ret != I40E_SUCCESS)
3791                         PMD_DRV_LOG(ERR, "Failed to delete element");
3792         }
3793         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3794
3795         if (vsi->type != I40E_VSI_SRIOV)
3796                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3797         rte_free(vsi);
3798
3799         return I40E_SUCCESS;
3800 }
3801
3802 static int
3803 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3804 {
3805         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3806         struct i40e_aqc_remove_macvlan_element_data def_filter;
3807         struct i40e_mac_filter_info filter;
3808         int ret;
3809
3810         if (vsi->type != I40E_VSI_MAIN)
3811                 return I40E_ERR_CONFIG;
3812         memset(&def_filter, 0, sizeof(def_filter));
3813         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3814                                         ETH_ADDR_LEN);
3815         def_filter.vlan_tag = 0;
3816         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3817                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3818         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3819         if (ret != I40E_SUCCESS) {
3820                 struct i40e_mac_filter *f;
3821                 struct ether_addr *mac;
3822
3823                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3824                             "macvlan filter");
3825                 /* It needs to add the permanent mac into mac list */
3826                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3827                 if (f == NULL) {
3828                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3829                         return I40E_ERR_NO_MEMORY;
3830                 }
3831                 mac = &f->mac_info.mac_addr;
3832                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3833                                 ETH_ADDR_LEN);
3834                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3835                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3836                 vsi->mac_num++;
3837
3838                 return ret;
3839         }
3840         (void)rte_memcpy(&filter.mac_addr,
3841                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3842         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3843         return i40e_vsi_add_mac(vsi, &filter);
3844 }
3845
3846 #define I40E_3_BIT_MASK     0x7
3847 /*
3848  * i40e_vsi_get_bw_config - Query VSI BW Information
3849  * @vsi: the VSI to be queried
3850  *
3851  * Returns 0 on success, negative value on failure
3852  */
3853 static enum i40e_status_code
3854 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3855 {
3856         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3857         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3858         struct i40e_hw *hw = &vsi->adapter->hw;
3859         i40e_status ret;
3860         int i;
3861         uint32_t bw_max;
3862
3863         memset(&bw_config, 0, sizeof(bw_config));
3864         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3865         if (ret != I40E_SUCCESS) {
3866                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3867                             hw->aq.asq_last_status);
3868                 return ret;
3869         }
3870
3871         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3872         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3873                                         &ets_sla_config, NULL);
3874         if (ret != I40E_SUCCESS) {
3875                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3876                             "configuration %u", hw->aq.asq_last_status);
3877                 return ret;
3878         }
3879
3880         /* store and print out BW info */
3881         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3882         vsi->bw_info.bw_max = bw_config.max_bw;
3883         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3884         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3885         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3886                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3887                      I40E_16_BIT_WIDTH);
3888         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3889                 vsi->bw_info.bw_ets_share_credits[i] =
3890                                 ets_sla_config.share_credits[i];
3891                 vsi->bw_info.bw_ets_credits[i] =
3892                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3893                 /* 4 bits per TC, 4th bit is reserved */
3894                 vsi->bw_info.bw_ets_max[i] =
3895                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3896                                   I40E_3_BIT_MASK);
3897                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3898                             vsi->bw_info.bw_ets_share_credits[i]);
3899                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3900                             vsi->bw_info.bw_ets_credits[i]);
3901                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3902                             vsi->bw_info.bw_ets_max[i]);
3903         }
3904
3905         return I40E_SUCCESS;
3906 }
3907
3908 /* Setup a VSI */
3909 struct i40e_vsi *
3910 i40e_vsi_setup(struct i40e_pf *pf,
3911                enum i40e_vsi_type type,
3912                struct i40e_vsi *uplink_vsi,
3913                uint16_t user_param)
3914 {
3915         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3916         struct i40e_vsi *vsi;
3917         struct i40e_mac_filter_info filter;
3918         int ret;
3919         struct i40e_vsi_context ctxt;
3920         struct ether_addr broadcast =
3921                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3922
3923         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3924                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3925                             "VSI link shouldn't be NULL");
3926                 return NULL;
3927         }
3928
3929         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3930                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3931                             "uplink VSI should be NULL");
3932                 return NULL;
3933         }
3934
3935         /* If uplink vsi didn't setup VEB, create one first */
3936         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3937                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3938
3939                 if (NULL == uplink_vsi->veb) {
3940                         PMD_DRV_LOG(ERR, "VEB setup failed");
3941                         return NULL;
3942                 }
3943         }
3944
3945         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3946         if (!vsi) {
3947                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3948                 return NULL;
3949         }
3950         TAILQ_INIT(&vsi->mac_list);
3951         vsi->type = type;
3952         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3953         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3954         vsi->parent_vsi = uplink_vsi;
3955         vsi->user_param = user_param;
3956         /* Allocate queues */
3957         switch (vsi->type) {
3958         case I40E_VSI_MAIN  :
3959                 vsi->nb_qps = pf->lan_nb_qps;
3960                 break;
3961         case I40E_VSI_SRIOV :
3962                 vsi->nb_qps = pf->vf_nb_qps;
3963                 break;
3964         case I40E_VSI_VMDQ2:
3965                 vsi->nb_qps = pf->vmdq_nb_qps;
3966                 break;
3967         case I40E_VSI_FDIR:
3968                 vsi->nb_qps = pf->fdir_nb_qps;
3969                 break;
3970         default:
3971                 goto fail_mem;
3972         }
3973         /*
3974          * The filter status descriptor is reported in rx queue 0,
3975          * while the tx queue for fdir filter programming has no
3976          * such constraints, can be non-zero queues.
3977          * To simplify it, choose FDIR vsi use queue 0 pair.
3978          * To make sure it will use queue 0 pair, queue allocation
3979          * need be done before this function is called
3980          */
3981         if (type != I40E_VSI_FDIR) {
3982                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3983                         if (ret < 0) {
3984                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3985                                                 vsi->seid, ret);
3986                                 goto fail_mem;
3987                         }
3988                         vsi->base_queue = ret;
3989         } else
3990                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3991
3992         /* VF has MSIX interrupt in VF range, don't allocate here */
3993         if (type == I40E_VSI_MAIN) {
3994                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3995                                           RTE_MIN(vsi->nb_qps,
3996                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3997                 if (ret < 0) {
3998                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3999                                     vsi->seid, ret);
4000                         goto fail_queue_alloc;
4001                 }
4002                 vsi->msix_intr = ret;
4003                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4004         } else if (type != I40E_VSI_SRIOV) {
4005                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4006                 if (ret < 0) {
4007                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4008                         goto fail_queue_alloc;
4009                 }
4010                 vsi->msix_intr = ret;
4011                 vsi->nb_msix = 1;
4012         } else {
4013                 vsi->msix_intr = 0;
4014                 vsi->nb_msix = 0;
4015         }
4016
4017         /* Add VSI */
4018         if (type == I40E_VSI_MAIN) {
4019                 /* For main VSI, no need to add since it's default one */
4020                 vsi->uplink_seid = pf->mac_seid;
4021                 vsi->seid = pf->main_vsi_seid;
4022                 /* Bind queues with specific MSIX interrupt */
4023                 /**
4024                  * Needs 2 interrupt at least, one for misc cause which will
4025                  * enabled from OS side, Another for queues binding the
4026                  * interrupt from device side only.
4027                  */
4028
4029                 /* Get default VSI parameters from hardware */
4030                 memset(&ctxt, 0, sizeof(ctxt));
4031                 ctxt.seid = vsi->seid;
4032                 ctxt.pf_num = hw->pf_id;
4033                 ctxt.uplink_seid = vsi->uplink_seid;
4034                 ctxt.vf_num = 0;
4035                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4036                 if (ret != I40E_SUCCESS) {
4037                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4038                         goto fail_msix_alloc;
4039                 }
4040                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4041                         sizeof(struct i40e_aqc_vsi_properties_data));
4042                 vsi->vsi_id = ctxt.vsi_number;
4043                 vsi->info.valid_sections = 0;
4044
4045                 /* Configure tc, enabled TC0 only */
4046                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4047                         I40E_SUCCESS) {
4048                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4049                         goto fail_msix_alloc;
4050                 }
4051
4052                 /* TC, queue mapping */
4053                 memset(&ctxt, 0, sizeof(ctxt));
4054                 vsi->info.valid_sections |=
4055                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4056                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4057                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4058                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4059                         sizeof(struct i40e_aqc_vsi_properties_data));
4060                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4061                                                 I40E_DEFAULT_TCMAP);
4062                 if (ret != I40E_SUCCESS) {
4063                         PMD_DRV_LOG(ERR, "Failed to configure "
4064                                     "TC queue mapping");
4065                         goto fail_msix_alloc;
4066                 }
4067                 ctxt.seid = vsi->seid;
4068                 ctxt.pf_num = hw->pf_id;
4069                 ctxt.uplink_seid = vsi->uplink_seid;
4070                 ctxt.vf_num = 0;
4071
4072                 /* Update VSI parameters */
4073                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4074                 if (ret != I40E_SUCCESS) {
4075                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4076                         goto fail_msix_alloc;
4077                 }
4078
4079                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4080                                                 sizeof(vsi->info.tc_mapping));
4081                 (void)rte_memcpy(&vsi->info.queue_mapping,
4082                                 &ctxt.info.queue_mapping,
4083                         sizeof(vsi->info.queue_mapping));
4084                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4085                 vsi->info.valid_sections = 0;
4086
4087                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4088                                 ETH_ADDR_LEN);
4089
4090                 /**
4091                  * Updating default filter settings are necessary to prevent
4092                  * reception of tagged packets.
4093                  * Some old firmware configurations load a default macvlan
4094                  * filter which accepts both tagged and untagged packets.
4095                  * The updating is to use a normal filter instead if needed.
4096                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4097                  * The firmware with correct configurations load the default
4098                  * macvlan filter which is expected and cannot be removed.
4099                  */
4100                 i40e_update_default_filter_setting(vsi);
4101                 i40e_config_qinq(hw, vsi);
4102         } else if (type == I40E_VSI_SRIOV) {
4103                 memset(&ctxt, 0, sizeof(ctxt));
4104                 /**
4105                  * For other VSI, the uplink_seid equals to uplink VSI's
4106                  * uplink_seid since they share same VEB
4107                  */
4108                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4109                 ctxt.pf_num = hw->pf_id;
4110                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4111                 ctxt.uplink_seid = vsi->uplink_seid;
4112                 ctxt.connection_type = 0x1;
4113                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4114
4115                 /**
4116                  * Do not configure switch ID to enable VEB switch by
4117                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4118                  * if the source mac address of packet sent from VF is not
4119                  * listed in the VEB's mac table, the VEB will switch the
4120                  * packet back to the VF. Need to enable it when HW issue
4121                  * is fixed.
4122                  */
4123
4124                 /* Configure port/vlan */
4125                 ctxt.info.valid_sections |=
4126                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4127                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4128                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4129                                                 I40E_DEFAULT_TCMAP);
4130                 if (ret != I40E_SUCCESS) {
4131                         PMD_DRV_LOG(ERR, "Failed to configure "
4132                                     "TC queue mapping");
4133                         goto fail_msix_alloc;
4134                 }
4135                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4136                 ctxt.info.valid_sections |=
4137                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4138                 /**
4139                  * Since VSI is not created yet, only configure parameter,
4140                  * will add vsi below.
4141                  */
4142
4143                 i40e_config_qinq(hw, vsi);
4144         } else if (type == I40E_VSI_VMDQ2) {
4145                 memset(&ctxt, 0, sizeof(ctxt));
4146                 /*
4147                  * For other VSI, the uplink_seid equals to uplink VSI's
4148                  * uplink_seid since they share same VEB
4149                  */
4150                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4151                 ctxt.pf_num = hw->pf_id;
4152                 ctxt.vf_num = 0;
4153                 ctxt.uplink_seid = vsi->uplink_seid;
4154                 ctxt.connection_type = 0x1;
4155                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4156
4157                 ctxt.info.valid_sections |=
4158                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4159                 /* user_param carries flag to enable loop back */
4160                 if (user_param) {
4161                         ctxt.info.switch_id =
4162                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4163                         ctxt.info.switch_id |=
4164                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4165                 }
4166
4167                 /* Configure port/vlan */
4168                 ctxt.info.valid_sections |=
4169                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4170                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4171                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4172                                                 I40E_DEFAULT_TCMAP);
4173                 if (ret != I40E_SUCCESS) {
4174                         PMD_DRV_LOG(ERR, "Failed to configure "
4175                                         "TC queue mapping");
4176                         goto fail_msix_alloc;
4177                 }
4178                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4179                 ctxt.info.valid_sections |=
4180                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4181         } else if (type == I40E_VSI_FDIR) {
4182                 memset(&ctxt, 0, sizeof(ctxt));
4183                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4184                 ctxt.pf_num = hw->pf_id;
4185                 ctxt.vf_num = 0;
4186                 ctxt.uplink_seid = vsi->uplink_seid;
4187                 ctxt.connection_type = 0x1;     /* regular data port */
4188                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4189                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4190                                                 I40E_DEFAULT_TCMAP);
4191                 if (ret != I40E_SUCCESS) {
4192                         PMD_DRV_LOG(ERR, "Failed to configure "
4193                                         "TC queue mapping.");
4194                         goto fail_msix_alloc;
4195                 }
4196                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4197                 ctxt.info.valid_sections |=
4198                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4199         } else {
4200                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4201                 goto fail_msix_alloc;
4202         }
4203
4204         if (vsi->type != I40E_VSI_MAIN) {
4205                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4206                 if (ret != I40E_SUCCESS) {
4207                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4208                                     hw->aq.asq_last_status);
4209                         goto fail_msix_alloc;
4210                 }
4211                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4212                 vsi->info.valid_sections = 0;
4213                 vsi->seid = ctxt.seid;
4214                 vsi->vsi_id = ctxt.vsi_number;
4215                 vsi->sib_vsi_list.vsi = vsi;
4216                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4217                                 &vsi->sib_vsi_list, list);
4218         }
4219
4220         /* MAC/VLAN configuration */
4221         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4222         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4223
4224         ret = i40e_vsi_add_mac(vsi, &filter);
4225         if (ret != I40E_SUCCESS) {
4226                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4227                 goto fail_msix_alloc;
4228         }
4229
4230         /* Get VSI BW information */
4231         i40e_vsi_get_bw_config(vsi);
4232         return vsi;
4233 fail_msix_alloc:
4234         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4235 fail_queue_alloc:
4236         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4237 fail_mem:
4238         rte_free(vsi);
4239         return NULL;
4240 }
4241
4242 /* Configure vlan filter on or off */
4243 int
4244 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4245 {
4246         int i, num;
4247         struct i40e_mac_filter *f;
4248         struct i40e_mac_filter_info *mac_filter;
4249         enum rte_mac_filter_type desired_filter;
4250         int ret = I40E_SUCCESS;
4251
4252         if (on) {
4253                 /* Filter to match MAC and VLAN */
4254                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4255         } else {
4256                 /* Filter to match only MAC */
4257                 desired_filter = RTE_MAC_PERFECT_MATCH;
4258         }
4259
4260         num = vsi->mac_num;
4261
4262         mac_filter = rte_zmalloc("mac_filter_info_data",
4263                                  num * sizeof(*mac_filter), 0);
4264         if (mac_filter == NULL) {
4265                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4266                 return I40E_ERR_NO_MEMORY;
4267         }
4268
4269         i = 0;
4270
4271         /* Remove all existing mac */
4272         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4273                 mac_filter[i] = f->mac_info;
4274                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4275                 if (ret) {
4276                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4277                                     on ? "enable" : "disable");
4278                         goto DONE;
4279                 }
4280                 i++;
4281         }
4282
4283         /* Override with new filter */
4284         for (i = 0; i < num; i++) {
4285                 mac_filter[i].filter_type = desired_filter;
4286                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4287                 if (ret) {
4288                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4289                                     on ? "enable" : "disable");
4290                         goto DONE;
4291                 }
4292         }
4293
4294 DONE:
4295         rte_free(mac_filter);
4296         return ret;
4297 }
4298
4299 /* Configure vlan stripping on or off */
4300 int
4301 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4302 {
4303         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4304         struct i40e_vsi_context ctxt;
4305         uint8_t vlan_flags;
4306         int ret = I40E_SUCCESS;
4307
4308         /* Check if it has been already on or off */
4309         if (vsi->info.valid_sections &
4310                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4311                 if (on) {
4312                         if ((vsi->info.port_vlan_flags &
4313                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4314                                 return 0; /* already on */
4315                 } else {
4316                         if ((vsi->info.port_vlan_flags &
4317                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4318                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4319                                 return 0; /* already off */
4320                 }
4321         }
4322
4323         if (on)
4324                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4325         else
4326                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4327         vsi->info.valid_sections =
4328                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4329         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4330         vsi->info.port_vlan_flags |= vlan_flags;
4331         ctxt.seid = vsi->seid;
4332         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4333         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4334         if (ret)
4335                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4336                             on ? "enable" : "disable");
4337
4338         return ret;
4339 }
4340
4341 static int
4342 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4343 {
4344         struct rte_eth_dev_data *data = dev->data;
4345         int ret;
4346         int mask = 0;
4347
4348         /* Apply vlan offload setting */
4349         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4350         i40e_vlan_offload_set(dev, mask);
4351
4352         /* Apply double-vlan setting, not implemented yet */
4353
4354         /* Apply pvid setting */
4355         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4356                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4357         if (ret)
4358                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4359
4360         return ret;
4361 }
4362
4363 static int
4364 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4365 {
4366         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4367
4368         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4369 }
4370
4371 static int
4372 i40e_update_flow_control(struct i40e_hw *hw)
4373 {
4374 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4375         struct i40e_link_status link_status;
4376         uint32_t rxfc = 0, txfc = 0, reg;
4377         uint8_t an_info;
4378         int ret;
4379
4380         memset(&link_status, 0, sizeof(link_status));
4381         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4382         if (ret != I40E_SUCCESS) {
4383                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4384                 goto write_reg; /* Disable flow control */
4385         }
4386
4387         an_info = hw->phy.link_info.an_info;
4388         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4389                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4390                 ret = I40E_ERR_NOT_READY;
4391                 goto write_reg; /* Disable flow control */
4392         }
4393         /**
4394          * If link auto negotiation is enabled, flow control needs to
4395          * be configured according to it
4396          */
4397         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4398         case I40E_LINK_PAUSE_RXTX:
4399                 rxfc = 1;
4400                 txfc = 1;
4401                 hw->fc.current_mode = I40E_FC_FULL;
4402                 break;
4403         case I40E_AQ_LINK_PAUSE_RX:
4404                 rxfc = 1;
4405                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4406                 break;
4407         case I40E_AQ_LINK_PAUSE_TX:
4408                 txfc = 1;
4409                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4410                 break;
4411         default:
4412                 hw->fc.current_mode = I40E_FC_NONE;
4413                 break;
4414         }
4415
4416 write_reg:
4417         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4418                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4419         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4420         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4421         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4422         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4423
4424         return ret;
4425 }
4426
4427 /* PF setup */
4428 static int
4429 i40e_pf_setup(struct i40e_pf *pf)
4430 {
4431         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4432         struct i40e_filter_control_settings settings;
4433         struct i40e_vsi *vsi;
4434         int ret;
4435
4436         /* Clear all stats counters */
4437         pf->offset_loaded = FALSE;
4438         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4439         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4440
4441         ret = i40e_pf_get_switch_config(pf);
4442         if (ret != I40E_SUCCESS) {
4443                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4444                 return ret;
4445         }
4446         if (pf->flags & I40E_FLAG_FDIR) {
4447                 /* make queue allocated first, let FDIR use queue pair 0*/
4448                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4449                 if (ret != I40E_FDIR_QUEUE_ID) {
4450                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4451                                     " ret =%d", ret);
4452                         pf->flags &= ~I40E_FLAG_FDIR;
4453                 }
4454         }
4455         /*  main VSI setup */
4456         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4457         if (!vsi) {
4458                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4459                 return I40E_ERR_NOT_READY;
4460         }
4461         pf->main_vsi = vsi;
4462
4463         /* Configure filter control */
4464         memset(&settings, 0, sizeof(settings));
4465         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4466                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4467         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4468                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4469         else {
4470                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4471                                                 hw->func_caps.rss_table_size);
4472                 return I40E_ERR_PARAM;
4473         }
4474         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4475                         "size: %u\n", hw->func_caps.rss_table_size);
4476         pf->hash_lut_size = hw->func_caps.rss_table_size;
4477
4478         /* Enable ethtype and macvlan filters */
4479         settings.enable_ethtype = TRUE;
4480         settings.enable_macvlan = TRUE;
4481         ret = i40e_set_filter_control(hw, &settings);
4482         if (ret)
4483                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4484                                                                 ret);
4485
4486         /* Update flow control according to the auto negotiation */
4487         i40e_update_flow_control(hw);
4488
4489         return I40E_SUCCESS;
4490 }
4491
4492 int
4493 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4494 {
4495         uint32_t reg;
4496         uint16_t j;
4497
4498         /**
4499          * Set or clear TX Queue Disable flags,
4500          * which is required by hardware.
4501          */
4502         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4503         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4504
4505         /* Wait until the request is finished */
4506         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4507                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4508                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4509                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4510                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4511                                                         & 0x1))) {
4512                         break;
4513                 }
4514         }
4515         if (on) {
4516                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4517                         return I40E_SUCCESS; /* already on, skip next steps */
4518
4519                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4520                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4521         } else {
4522                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4523                         return I40E_SUCCESS; /* already off, skip next steps */
4524                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4525         }
4526         /* Write the register */
4527         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4528         /* Check the result */
4529         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4530                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4531                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4532                 if (on) {
4533                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4534                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4535                                 break;
4536                 } else {
4537                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4538                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4539                                 break;
4540                 }
4541         }
4542         /* Check if it is timeout */
4543         if (j >= I40E_CHK_Q_ENA_COUNT) {
4544                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4545                             (on ? "enable" : "disable"), q_idx);
4546                 return I40E_ERR_TIMEOUT;
4547         }
4548
4549         return I40E_SUCCESS;
4550 }
4551
4552 /* Swith on or off the tx queues */
4553 static int
4554 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4555 {
4556         struct rte_eth_dev_data *dev_data = pf->dev_data;
4557         struct i40e_tx_queue *txq;
4558         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4559         uint16_t i;
4560         int ret;
4561
4562         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4563                 txq = dev_data->tx_queues[i];
4564                 /* Don't operate the queue if not configured or
4565                  * if starting only per queue */
4566                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4567                         continue;
4568                 if (on)
4569                         ret = i40e_dev_tx_queue_start(dev, i);
4570                 else
4571                         ret = i40e_dev_tx_queue_stop(dev, i);
4572                 if ( ret != I40E_SUCCESS)
4573                         return ret;
4574         }
4575
4576         return I40E_SUCCESS;
4577 }
4578
4579 int
4580 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4581 {
4582         uint32_t reg;
4583         uint16_t j;
4584
4585         /* Wait until the request is finished */
4586         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4587                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4588                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4589                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4590                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4591                         break;
4592         }
4593
4594         if (on) {
4595                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4596                         return I40E_SUCCESS; /* Already on, skip next steps */
4597                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4598         } else {
4599                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4600                         return I40E_SUCCESS; /* Already off, skip next steps */
4601                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4602         }
4603
4604         /* Write the register */
4605         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4606         /* Check the result */
4607         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4608                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4609                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4610                 if (on) {
4611                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4612                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4613                                 break;
4614                 } else {
4615                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4616                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4617                                 break;
4618                 }
4619         }
4620
4621         /* Check if it is timeout */
4622         if (j >= I40E_CHK_Q_ENA_COUNT) {
4623                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4624                             (on ? "enable" : "disable"), q_idx);
4625                 return I40E_ERR_TIMEOUT;
4626         }
4627
4628         return I40E_SUCCESS;
4629 }
4630 /* Switch on or off the rx queues */
4631 static int
4632 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4633 {
4634         struct rte_eth_dev_data *dev_data = pf->dev_data;
4635         struct i40e_rx_queue *rxq;
4636         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4637         uint16_t i;
4638         int ret;
4639
4640         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4641                 rxq = dev_data->rx_queues[i];
4642                 /* Don't operate the queue if not configured or
4643                  * if starting only per queue */
4644                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4645                         continue;
4646                 if (on)
4647                         ret = i40e_dev_rx_queue_start(dev, i);
4648                 else
4649                         ret = i40e_dev_rx_queue_stop(dev, i);
4650                 if (ret != I40E_SUCCESS)
4651                         return ret;
4652         }
4653
4654         return I40E_SUCCESS;
4655 }
4656
4657 /* Switch on or off all the rx/tx queues */
4658 int
4659 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4660 {
4661         int ret;
4662
4663         if (on) {
4664                 /* enable rx queues before enabling tx queues */
4665                 ret = i40e_dev_switch_rx_queues(pf, on);
4666                 if (ret) {
4667                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4668                         return ret;
4669                 }
4670                 ret = i40e_dev_switch_tx_queues(pf, on);
4671         } else {
4672                 /* Stop tx queues before stopping rx queues */
4673                 ret = i40e_dev_switch_tx_queues(pf, on);
4674                 if (ret) {
4675                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4676                         return ret;
4677                 }
4678                 ret = i40e_dev_switch_rx_queues(pf, on);
4679         }
4680
4681         return ret;
4682 }
4683
4684 /* Initialize VSI for TX */
4685 static int
4686 i40e_dev_tx_init(struct i40e_pf *pf)
4687 {
4688         struct rte_eth_dev_data *data = pf->dev_data;
4689         uint16_t i;
4690         uint32_t ret = I40E_SUCCESS;
4691         struct i40e_tx_queue *txq;
4692
4693         for (i = 0; i < data->nb_tx_queues; i++) {
4694                 txq = data->tx_queues[i];
4695                 if (!txq || !txq->q_set)
4696                         continue;
4697                 ret = i40e_tx_queue_init(txq);
4698                 if (ret != I40E_SUCCESS)
4699                         break;
4700         }
4701         if (ret == I40E_SUCCESS)
4702                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4703                                      ->eth_dev);
4704
4705         return ret;
4706 }
4707
4708 /* Initialize VSI for RX */
4709 static int
4710 i40e_dev_rx_init(struct i40e_pf *pf)
4711 {
4712         struct rte_eth_dev_data *data = pf->dev_data;
4713         int ret = I40E_SUCCESS;
4714         uint16_t i;
4715         struct i40e_rx_queue *rxq;
4716
4717         i40e_pf_config_mq_rx(pf);
4718         for (i = 0; i < data->nb_rx_queues; i++) {
4719                 rxq = data->rx_queues[i];
4720                 if (!rxq || !rxq->q_set)
4721                         continue;
4722
4723                 ret = i40e_rx_queue_init(rxq);
4724                 if (ret != I40E_SUCCESS) {
4725                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4726                                     "initialization");
4727                         break;
4728                 }
4729         }
4730         if (ret == I40E_SUCCESS)
4731                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4732                                      ->eth_dev);
4733
4734         return ret;
4735 }
4736
4737 static int
4738 i40e_dev_rxtx_init(struct i40e_pf *pf)
4739 {
4740         int err;
4741
4742         err = i40e_dev_tx_init(pf);
4743         if (err) {
4744                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4745                 return err;
4746         }
4747         err = i40e_dev_rx_init(pf);
4748         if (err) {
4749                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4750                 return err;
4751         }
4752
4753         return err;
4754 }
4755
4756 static int
4757 i40e_vmdq_setup(struct rte_eth_dev *dev)
4758 {
4759         struct rte_eth_conf *conf = &dev->data->dev_conf;
4760         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4761         int i, err, conf_vsis, j, loop;
4762         struct i40e_vsi *vsi;
4763         struct i40e_vmdq_info *vmdq_info;
4764         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4766
4767         /*
4768          * Disable interrupt to avoid message from VF. Furthermore, it will
4769          * avoid race condition in VSI creation/destroy.
4770          */
4771         i40e_pf_disable_irq0(hw);
4772
4773         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4774                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4775                 return -ENOTSUP;
4776         }
4777
4778         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4779         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4780                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4781                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4782                         pf->max_nb_vmdq_vsi);
4783                 return -ENOTSUP;
4784         }
4785
4786         if (pf->vmdq != NULL) {
4787                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4788                 return 0;
4789         }
4790
4791         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4792                                 sizeof(*vmdq_info) * conf_vsis, 0);
4793
4794         if (pf->vmdq == NULL) {
4795                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4796                 return -ENOMEM;
4797         }
4798
4799         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4800
4801         /* Create VMDQ VSI */
4802         for (i = 0; i < conf_vsis; i++) {
4803                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4804                                 vmdq_conf->enable_loop_back);
4805                 if (vsi == NULL) {
4806                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4807                         err = -1;
4808                         goto err_vsi_setup;
4809                 }
4810                 vmdq_info = &pf->vmdq[i];
4811                 vmdq_info->pf = pf;
4812                 vmdq_info->vsi = vsi;
4813         }
4814         pf->nb_cfg_vmdq_vsi = conf_vsis;
4815
4816         /* Configure Vlan */
4817         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4818         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4819                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4820                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4821                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4822                                         vmdq_conf->pool_map[i].vlan_id, j);
4823
4824                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4825                                                 vmdq_conf->pool_map[i].vlan_id);
4826                                 if (err) {
4827                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4828                                         err = -1;
4829                                         goto err_vsi_setup;
4830                                 }
4831                         }
4832                 }
4833         }
4834
4835         i40e_pf_enable_irq0(hw);
4836
4837         return 0;
4838
4839 err_vsi_setup:
4840         for (i = 0; i < conf_vsis; i++)
4841                 if (pf->vmdq[i].vsi == NULL)
4842                         break;
4843                 else
4844                         i40e_vsi_release(pf->vmdq[i].vsi);
4845
4846         rte_free(pf->vmdq);
4847         pf->vmdq = NULL;
4848         i40e_pf_enable_irq0(hw);
4849         return err;
4850 }
4851
4852 static void
4853 i40e_stat_update_32(struct i40e_hw *hw,
4854                    uint32_t reg,
4855                    bool offset_loaded,
4856                    uint64_t *offset,
4857                    uint64_t *stat)
4858 {
4859         uint64_t new_data;
4860
4861         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4862         if (!offset_loaded)
4863                 *offset = new_data;
4864
4865         if (new_data >= *offset)
4866                 *stat = (uint64_t)(new_data - *offset);
4867         else
4868                 *stat = (uint64_t)((new_data +
4869                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4870 }
4871
4872 static void
4873 i40e_stat_update_48(struct i40e_hw *hw,
4874                    uint32_t hireg,
4875                    uint32_t loreg,
4876                    bool offset_loaded,
4877                    uint64_t *offset,
4878                    uint64_t *stat)
4879 {
4880         uint64_t new_data;
4881
4882         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4883         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4884                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4885
4886         if (!offset_loaded)
4887                 *offset = new_data;
4888
4889         if (new_data >= *offset)
4890                 *stat = new_data - *offset;
4891         else
4892                 *stat = (uint64_t)((new_data +
4893                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4894
4895         *stat &= I40E_48_BIT_MASK;
4896 }
4897
4898 /* Disable IRQ0 */
4899 void
4900 i40e_pf_disable_irq0(struct i40e_hw *hw)
4901 {
4902         /* Disable all interrupt types */
4903         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4904         I40E_WRITE_FLUSH(hw);
4905 }
4906
4907 /* Enable IRQ0 */
4908 void
4909 i40e_pf_enable_irq0(struct i40e_hw *hw)
4910 {
4911         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4912                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4913                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4914                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4915         I40E_WRITE_FLUSH(hw);
4916 }
4917
4918 static void
4919 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4920 {
4921         /* read pending request and disable first */
4922         i40e_pf_disable_irq0(hw);
4923         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4924         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4925                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4926
4927         if (no_queue)
4928                 /* Link no queues with irq0 */
4929                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4930                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4931 }
4932
4933 static void
4934 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4935 {
4936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4937         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4938         int i;
4939         uint16_t abs_vf_id;
4940         uint32_t index, offset, val;
4941
4942         if (!pf->vfs)
4943                 return;
4944         /**
4945          * Try to find which VF trigger a reset, use absolute VF id to access
4946          * since the reg is global register.
4947          */
4948         for (i = 0; i < pf->vf_num; i++) {
4949                 abs_vf_id = hw->func_caps.vf_base_id + i;
4950                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4951                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4952                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4953                 /* VFR event occured */
4954                 if (val & (0x1 << offset)) {
4955                         int ret;
4956
4957                         /* Clear the event first */
4958                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4959                                                         (0x1 << offset));
4960                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4961                         /**
4962                          * Only notify a VF reset event occured,
4963                          * don't trigger another SW reset
4964                          */
4965                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4966                         if (ret != I40E_SUCCESS)
4967                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4968                 }
4969         }
4970 }
4971
4972 static void
4973 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4974 {
4975         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         struct i40e_arq_event_info info;
4977         uint16_t pending, opcode;
4978         int ret;
4979
4980         info.buf_len = I40E_AQ_BUF_SZ;
4981         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4982         if (!info.msg_buf) {
4983                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4984                 return;
4985         }
4986
4987         pending = 1;
4988         while (pending) {
4989                 ret = i40e_clean_arq_element(hw, &info, &pending);
4990
4991                 if (ret != I40E_SUCCESS) {
4992                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4993                                     "aq_err: %u", hw->aq.asq_last_status);
4994                         break;
4995                 }
4996                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4997
4998                 switch (opcode) {
4999                 case i40e_aqc_opc_send_msg_to_pf:
5000                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5001                         i40e_pf_host_handle_vf_msg(dev,
5002                                         rte_le_to_cpu_16(info.desc.retval),
5003                                         rte_le_to_cpu_32(info.desc.cookie_high),
5004                                         rte_le_to_cpu_32(info.desc.cookie_low),
5005                                         info.msg_buf,
5006                                         info.msg_len);
5007                         break;
5008                 default:
5009                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5010                                     opcode);
5011                         break;
5012                 }
5013         }
5014         rte_free(info.msg_buf);
5015 }
5016
5017 /*
5018  * Interrupt handler is registered as the alarm callback for handling LSC
5019  * interrupt in a definite of time, in order to wait the NIC into a stable
5020  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5021  * no need for link down interrupt.
5022  */
5023 static void
5024 i40e_dev_interrupt_delayed_handler(void *param)
5025 {
5026         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5027         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5028         uint32_t icr0;
5029
5030         /* read interrupt causes again */
5031         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5032
5033 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5034         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5035                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5036         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5037                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5038         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5039                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5040         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5041                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5042         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5043                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5044                                                                 "state\n");
5045         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5046                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5047         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5048                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5049 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5050
5051         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5052                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5053                 i40e_dev_handle_vfr_event(dev);
5054         }
5055         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5056                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5057                 i40e_dev_handle_aq_msg(dev);
5058         }
5059
5060         /* handle the link up interrupt in an alarm callback */
5061         i40e_dev_link_update(dev, 0);
5062         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5063
5064         i40e_pf_enable_irq0(hw);
5065         rte_intr_enable(&(dev->pci_dev->intr_handle));
5066 }
5067
5068 /**
5069  * Interrupt handler triggered by NIC  for handling
5070  * specific interrupt.
5071  *
5072  * @param handle
5073  *  Pointer to interrupt handle.
5074  * @param param
5075  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5076  *
5077  * @return
5078  *  void
5079  */
5080 static void
5081 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5082                            void *param)
5083 {
5084         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086         uint32_t icr0;
5087
5088         /* Disable interrupt */
5089         i40e_pf_disable_irq0(hw);
5090
5091         /* read out interrupt causes */
5092         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5093
5094         /* No interrupt event indicated */
5095         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5096                 PMD_DRV_LOG(INFO, "No interrupt event");
5097                 goto done;
5098         }
5099 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5100         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5101                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5102         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5103                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5104         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5105                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5106         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5107                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5108         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5109                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5110         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5111                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5112         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5113                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5114 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5115
5116         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5117                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5118                 i40e_dev_handle_vfr_event(dev);
5119         }
5120         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5121                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5122                 i40e_dev_handle_aq_msg(dev);
5123         }
5124
5125         /* Link Status Change interrupt */
5126         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5127 #define I40E_US_PER_SECOND 1000000
5128                 struct rte_eth_link link;
5129
5130                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5131                 memset(&link, 0, sizeof(link));
5132                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5133                 i40e_dev_link_update(dev, 0);
5134
5135                 /*
5136                  * For link up interrupt, it needs to wait 1 second to let the
5137                  * hardware be a stable state. Otherwise several consecutive
5138                  * interrupts can be observed.
5139                  * For link down interrupt, no need to wait.
5140                  */
5141                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5142                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5143                         return;
5144                 else
5145                         _rte_eth_dev_callback_process(dev,
5146                                 RTE_ETH_EVENT_INTR_LSC);
5147         }
5148
5149 done:
5150         /* Enable interrupt */
5151         i40e_pf_enable_irq0(hw);
5152         rte_intr_enable(&(dev->pci_dev->intr_handle));
5153 }
5154
5155 static int
5156 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5157                          struct i40e_macvlan_filter *filter,
5158                          int total)
5159 {
5160         int ele_num, ele_buff_size;
5161         int num, actual_num, i;
5162         uint16_t flags;
5163         int ret = I40E_SUCCESS;
5164         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5165         struct i40e_aqc_add_macvlan_element_data *req_list;
5166
5167         if (filter == NULL  || total == 0)
5168                 return I40E_ERR_PARAM;
5169         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5170         ele_buff_size = hw->aq.asq_buf_size;
5171
5172         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5173         if (req_list == NULL) {
5174                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5175                 return I40E_ERR_NO_MEMORY;
5176         }
5177
5178         num = 0;
5179         do {
5180                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5181                 memset(req_list, 0, ele_buff_size);
5182
5183                 for (i = 0; i < actual_num; i++) {
5184                         (void)rte_memcpy(req_list[i].mac_addr,
5185                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5186                         req_list[i].vlan_tag =
5187                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5188
5189                         switch (filter[num + i].filter_type) {
5190                         case RTE_MAC_PERFECT_MATCH:
5191                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5192                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5193                                 break;
5194                         case RTE_MACVLAN_PERFECT_MATCH:
5195                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5196                                 break;
5197                         case RTE_MAC_HASH_MATCH:
5198                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5199                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5200                                 break;
5201                         case RTE_MACVLAN_HASH_MATCH:
5202                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5203                                 break;
5204                         default:
5205                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5206                                 ret = I40E_ERR_PARAM;
5207                                 goto DONE;
5208                         }
5209
5210                         req_list[i].queue_number = 0;
5211
5212                         req_list[i].flags = rte_cpu_to_le_16(flags);
5213                 }
5214
5215                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5216                                                 actual_num, NULL);
5217                 if (ret != I40E_SUCCESS) {
5218                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5219                         goto DONE;
5220                 }
5221                 num += actual_num;
5222         } while (num < total);
5223
5224 DONE:
5225         rte_free(req_list);
5226         return ret;
5227 }
5228
5229 static int
5230 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5231                             struct i40e_macvlan_filter *filter,
5232                             int total)
5233 {
5234         int ele_num, ele_buff_size;
5235         int num, actual_num, i;
5236         uint16_t flags;
5237         int ret = I40E_SUCCESS;
5238         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5239         struct i40e_aqc_remove_macvlan_element_data *req_list;
5240
5241         if (filter == NULL  || total == 0)
5242                 return I40E_ERR_PARAM;
5243
5244         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5245         ele_buff_size = hw->aq.asq_buf_size;
5246
5247         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5248         if (req_list == NULL) {
5249                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5250                 return I40E_ERR_NO_MEMORY;
5251         }
5252
5253         num = 0;
5254         do {
5255                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5256                 memset(req_list, 0, ele_buff_size);
5257
5258                 for (i = 0; i < actual_num; i++) {
5259                         (void)rte_memcpy(req_list[i].mac_addr,
5260                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5261                         req_list[i].vlan_tag =
5262                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5263
5264                         switch (filter[num + i].filter_type) {
5265                         case RTE_MAC_PERFECT_MATCH:
5266                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5267                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5268                                 break;
5269                         case RTE_MACVLAN_PERFECT_MATCH:
5270                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5271                                 break;
5272                         case RTE_MAC_HASH_MATCH:
5273                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5274                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5275                                 break;
5276                         case RTE_MACVLAN_HASH_MATCH:
5277                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5278                                 break;
5279                         default:
5280                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5281                                 ret = I40E_ERR_PARAM;
5282                                 goto DONE;
5283                         }
5284                         req_list[i].flags = rte_cpu_to_le_16(flags);
5285                 }
5286
5287                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5288                                                 actual_num, NULL);
5289                 if (ret != I40E_SUCCESS) {
5290                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5291                         goto DONE;
5292                 }
5293                 num += actual_num;
5294         } while (num < total);
5295
5296 DONE:
5297         rte_free(req_list);
5298         return ret;
5299 }
5300
5301 /* Find out specific MAC filter */
5302 static struct i40e_mac_filter *
5303 i40e_find_mac_filter(struct i40e_vsi *vsi,
5304                          struct ether_addr *macaddr)
5305 {
5306         struct i40e_mac_filter *f;
5307
5308         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5309                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5310                         return f;
5311         }
5312
5313         return NULL;
5314 }
5315
5316 static bool
5317 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5318                          uint16_t vlan_id)
5319 {
5320         uint32_t vid_idx, vid_bit;
5321
5322         if (vlan_id > ETH_VLAN_ID_MAX)
5323                 return 0;
5324
5325         vid_idx = I40E_VFTA_IDX(vlan_id);
5326         vid_bit = I40E_VFTA_BIT(vlan_id);
5327
5328         if (vsi->vfta[vid_idx] & vid_bit)
5329                 return 1;
5330         else
5331                 return 0;
5332 }
5333
5334 static void
5335 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5336                          uint16_t vlan_id, bool on)
5337 {
5338         uint32_t vid_idx, vid_bit;
5339
5340         if (vlan_id > ETH_VLAN_ID_MAX)
5341                 return;
5342
5343         vid_idx = I40E_VFTA_IDX(vlan_id);
5344         vid_bit = I40E_VFTA_BIT(vlan_id);
5345
5346         if (on)
5347                 vsi->vfta[vid_idx] |= vid_bit;
5348         else
5349                 vsi->vfta[vid_idx] &= ~vid_bit;
5350 }
5351
5352 /**
5353  * Find all vlan options for specific mac addr,
5354  * return with actual vlan found.
5355  */
5356 static inline int
5357 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5358                            struct i40e_macvlan_filter *mv_f,
5359                            int num, struct ether_addr *addr)
5360 {
5361         int i;
5362         uint32_t j, k;
5363
5364         /**
5365          * Not to use i40e_find_vlan_filter to decrease the loop time,
5366          * although the code looks complex.
5367           */
5368         if (num < vsi->vlan_num)
5369                 return I40E_ERR_PARAM;
5370
5371         i = 0;
5372         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5373                 if (vsi->vfta[j]) {
5374                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5375                                 if (vsi->vfta[j] & (1 << k)) {
5376                                         if (i > num - 1) {
5377                                                 PMD_DRV_LOG(ERR, "vlan number "
5378                                                             "not match");
5379                                                 return I40E_ERR_PARAM;
5380                                         }
5381                                         (void)rte_memcpy(&mv_f[i].macaddr,
5382                                                         addr, ETH_ADDR_LEN);
5383                                         mv_f[i].vlan_id =
5384                                                 j * I40E_UINT32_BIT_SIZE + k;
5385                                         i++;
5386                                 }
5387                         }
5388                 }
5389         }
5390         return I40E_SUCCESS;
5391 }
5392
5393 static inline int
5394 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5395                            struct i40e_macvlan_filter *mv_f,
5396                            int num,
5397                            uint16_t vlan)
5398 {
5399         int i = 0;
5400         struct i40e_mac_filter *f;
5401
5402         if (num < vsi->mac_num)
5403                 return I40E_ERR_PARAM;
5404
5405         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5406                 if (i > num - 1) {
5407                         PMD_DRV_LOG(ERR, "buffer number not match");
5408                         return I40E_ERR_PARAM;
5409                 }
5410                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5411                                 ETH_ADDR_LEN);
5412                 mv_f[i].vlan_id = vlan;
5413                 mv_f[i].filter_type = f->mac_info.filter_type;
5414                 i++;
5415         }
5416
5417         return I40E_SUCCESS;
5418 }
5419
5420 static int
5421 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5422 {
5423         int i, num;
5424         struct i40e_mac_filter *f;
5425         struct i40e_macvlan_filter *mv_f;
5426         int ret = I40E_SUCCESS;
5427
5428         if (vsi == NULL || vsi->mac_num == 0)
5429                 return I40E_ERR_PARAM;
5430
5431         /* Case that no vlan is set */
5432         if (vsi->vlan_num == 0)
5433                 num = vsi->mac_num;
5434         else
5435                 num = vsi->mac_num * vsi->vlan_num;
5436
5437         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5438         if (mv_f == NULL) {
5439                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5440                 return I40E_ERR_NO_MEMORY;
5441         }
5442
5443         i = 0;
5444         if (vsi->vlan_num == 0) {
5445                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5446                         (void)rte_memcpy(&mv_f[i].macaddr,
5447                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5448                         mv_f[i].vlan_id = 0;
5449                         i++;
5450                 }
5451         } else {
5452                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5453                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5454                                         vsi->vlan_num, &f->mac_info.mac_addr);
5455                         if (ret != I40E_SUCCESS)
5456                                 goto DONE;
5457                         i += vsi->vlan_num;
5458                 }
5459         }
5460
5461         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5462 DONE:
5463         rte_free(mv_f);
5464
5465         return ret;
5466 }
5467
5468 int
5469 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5470 {
5471         struct i40e_macvlan_filter *mv_f;
5472         int mac_num;
5473         int ret = I40E_SUCCESS;
5474
5475         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5476                 return I40E_ERR_PARAM;
5477
5478         /* If it's already set, just return */
5479         if (i40e_find_vlan_filter(vsi,vlan))
5480                 return I40E_SUCCESS;
5481
5482         mac_num = vsi->mac_num;
5483
5484         if (mac_num == 0) {
5485                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5486                 return I40E_ERR_PARAM;
5487         }
5488
5489         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5490
5491         if (mv_f == NULL) {
5492                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5493                 return I40E_ERR_NO_MEMORY;
5494         }
5495
5496         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5497
5498         if (ret != I40E_SUCCESS)
5499                 goto DONE;
5500
5501         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5502
5503         if (ret != I40E_SUCCESS)
5504                 goto DONE;
5505
5506         i40e_set_vlan_filter(vsi, vlan, 1);
5507
5508         vsi->vlan_num++;
5509         ret = I40E_SUCCESS;
5510 DONE:
5511         rte_free(mv_f);
5512         return ret;
5513 }
5514
5515 int
5516 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5517 {
5518         struct i40e_macvlan_filter *mv_f;
5519         int mac_num;
5520         int ret = I40E_SUCCESS;
5521
5522         /**
5523          * Vlan 0 is the generic filter for untagged packets
5524          * and can't be removed.
5525          */
5526         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5527                 return I40E_ERR_PARAM;
5528
5529         /* If can't find it, just return */
5530         if (!i40e_find_vlan_filter(vsi, vlan))
5531                 return I40E_ERR_PARAM;
5532
5533         mac_num = vsi->mac_num;
5534
5535         if (mac_num == 0) {
5536                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5537                 return I40E_ERR_PARAM;
5538         }
5539
5540         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5541
5542         if (mv_f == NULL) {
5543                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5544                 return I40E_ERR_NO_MEMORY;
5545         }
5546
5547         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5548
5549         if (ret != I40E_SUCCESS)
5550                 goto DONE;
5551
5552         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5553
5554         if (ret != I40E_SUCCESS)
5555                 goto DONE;
5556
5557         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5558         if (vsi->vlan_num == 1) {
5559                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5560                 if (ret != I40E_SUCCESS)
5561                         goto DONE;
5562
5563                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5564                 if (ret != I40E_SUCCESS)
5565                         goto DONE;
5566         }
5567
5568         i40e_set_vlan_filter(vsi, vlan, 0);
5569
5570         vsi->vlan_num--;
5571         ret = I40E_SUCCESS;
5572 DONE:
5573         rte_free(mv_f);
5574         return ret;
5575 }
5576
5577 int
5578 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5579 {
5580         struct i40e_mac_filter *f;
5581         struct i40e_macvlan_filter *mv_f;
5582         int i, vlan_num = 0;
5583         int ret = I40E_SUCCESS;
5584
5585         /* If it's add and we've config it, return */
5586         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5587         if (f != NULL)
5588                 return I40E_SUCCESS;
5589         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5590                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5591
5592                 /**
5593                  * If vlan_num is 0, that's the first time to add mac,
5594                  * set mask for vlan_id 0.
5595                  */
5596                 if (vsi->vlan_num == 0) {
5597                         i40e_set_vlan_filter(vsi, 0, 1);
5598                         vsi->vlan_num = 1;
5599                 }
5600                 vlan_num = vsi->vlan_num;
5601         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5602                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5603                 vlan_num = 1;
5604
5605         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5606         if (mv_f == NULL) {
5607                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5608                 return I40E_ERR_NO_MEMORY;
5609         }
5610
5611         for (i = 0; i < vlan_num; i++) {
5612                 mv_f[i].filter_type = mac_filter->filter_type;
5613                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5614                                 ETH_ADDR_LEN);
5615         }
5616
5617         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5618                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5619                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5620                                         &mac_filter->mac_addr);
5621                 if (ret != I40E_SUCCESS)
5622                         goto DONE;
5623         }
5624
5625         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5626         if (ret != I40E_SUCCESS)
5627                 goto DONE;
5628
5629         /* Add the mac addr into mac list */
5630         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5631         if (f == NULL) {
5632                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5633                 ret = I40E_ERR_NO_MEMORY;
5634                 goto DONE;
5635         }
5636         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5637                         ETH_ADDR_LEN);
5638         f->mac_info.filter_type = mac_filter->filter_type;
5639         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5640         vsi->mac_num++;
5641
5642         ret = I40E_SUCCESS;
5643 DONE:
5644         rte_free(mv_f);
5645
5646         return ret;
5647 }
5648
5649 int
5650 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5651 {
5652         struct i40e_mac_filter *f;
5653         struct i40e_macvlan_filter *mv_f;
5654         int i, vlan_num;
5655         enum rte_mac_filter_type filter_type;
5656         int ret = I40E_SUCCESS;
5657
5658         /* Can't find it, return an error */
5659         f = i40e_find_mac_filter(vsi, addr);
5660         if (f == NULL)
5661                 return I40E_ERR_PARAM;
5662
5663         vlan_num = vsi->vlan_num;
5664         filter_type = f->mac_info.filter_type;
5665         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5666                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5667                 if (vlan_num == 0) {
5668                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5669                         return I40E_ERR_PARAM;
5670                 }
5671         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5672                         filter_type == RTE_MAC_HASH_MATCH)
5673                 vlan_num = 1;
5674
5675         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5676         if (mv_f == NULL) {
5677                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5678                 return I40E_ERR_NO_MEMORY;
5679         }
5680
5681         for (i = 0; i < vlan_num; i++) {
5682                 mv_f[i].filter_type = filter_type;
5683                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5684                                 ETH_ADDR_LEN);
5685         }
5686         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5687                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5688                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5689                 if (ret != I40E_SUCCESS)
5690                         goto DONE;
5691         }
5692
5693         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5694         if (ret != I40E_SUCCESS)
5695                 goto DONE;
5696
5697         /* Remove the mac addr into mac list */
5698         TAILQ_REMOVE(&vsi->mac_list, f, next);
5699         rte_free(f);
5700         vsi->mac_num--;
5701
5702         ret = I40E_SUCCESS;
5703 DONE:
5704         rte_free(mv_f);
5705         return ret;
5706 }
5707
5708 /* Configure hash enable flags for RSS */
5709 uint64_t
5710 i40e_config_hena(uint64_t flags)
5711 {
5712         uint64_t hena = 0;
5713
5714         if (!flags)
5715                 return hena;
5716
5717         if (flags & ETH_RSS_FRAG_IPV4)
5718                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5719         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5720                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5721         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5722                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5723         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5724                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5725         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5726                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5727         if (flags & ETH_RSS_FRAG_IPV6)
5728                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5729         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5730                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5731         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5732                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5733         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5734                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5735         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5736                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5737         if (flags & ETH_RSS_L2_PAYLOAD)
5738                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5739
5740         return hena;
5741 }
5742
5743 /* Parse the hash enable flags */
5744 uint64_t
5745 i40e_parse_hena(uint64_t flags)
5746 {
5747         uint64_t rss_hf = 0;
5748
5749         if (!flags)
5750                 return rss_hf;
5751         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5752                 rss_hf |= ETH_RSS_FRAG_IPV4;
5753         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5754                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5755         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5756                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5757         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5758                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5759         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5760                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5761         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5762                 rss_hf |= ETH_RSS_FRAG_IPV6;
5763         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5764                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5765         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5766                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5767         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5768                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5769         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5770                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5771         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5772                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5773
5774         return rss_hf;
5775 }
5776
5777 /* Disable RSS */
5778 static void
5779 i40e_pf_disable_rss(struct i40e_pf *pf)
5780 {
5781         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5782         uint64_t hena;
5783
5784         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5785         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5786         hena &= ~I40E_RSS_HENA_ALL;
5787         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5788         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5789         I40E_WRITE_FLUSH(hw);
5790 }
5791
5792 static int
5793 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5794 {
5795         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5796         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5797         int ret = 0;
5798
5799         if (!key || key_len == 0) {
5800                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5801                 return 0;
5802         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5803                 sizeof(uint32_t)) {
5804                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5805                 return -EINVAL;
5806         }
5807
5808         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5809                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5810                         (struct i40e_aqc_get_set_rss_key_data *)key;
5811
5812                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5813                 if (ret)
5814                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5815                                      "via AQ");
5816         } else {
5817                 uint32_t *hash_key = (uint32_t *)key;
5818                 uint16_t i;
5819
5820                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5821                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5822                 I40E_WRITE_FLUSH(hw);
5823         }
5824
5825         return ret;
5826 }
5827
5828 static int
5829 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5830 {
5831         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5832         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5833         int ret;
5834
5835         if (!key || !key_len)
5836                 return -EINVAL;
5837
5838         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5839                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5840                         (struct i40e_aqc_get_set_rss_key_data *)key);
5841                 if (ret) {
5842                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5843                         return ret;
5844                 }
5845         } else {
5846                 uint32_t *key_dw = (uint32_t *)key;
5847                 uint16_t i;
5848
5849                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5850                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5851         }
5852         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5853
5854         return 0;
5855 }
5856
5857 static int
5858 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5859 {
5860         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5861         uint64_t rss_hf;
5862         uint64_t hena;
5863         int ret;
5864
5865         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5866                                rss_conf->rss_key_len);
5867         if (ret)
5868                 return ret;
5869
5870         rss_hf = rss_conf->rss_hf;
5871         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5872         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5873         hena &= ~I40E_RSS_HENA_ALL;
5874         hena |= i40e_config_hena(rss_hf);
5875         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5876         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5877         I40E_WRITE_FLUSH(hw);
5878
5879         return 0;
5880 }
5881
5882 static int
5883 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5884                          struct rte_eth_rss_conf *rss_conf)
5885 {
5886         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5888         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5889         uint64_t hena;
5890
5891         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5892         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5893         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5894                 if (rss_hf != 0) /* Enable RSS */
5895                         return -EINVAL;
5896                 return 0; /* Nothing to do */
5897         }
5898         /* RSS enabled */
5899         if (rss_hf == 0) /* Disable RSS */
5900                 return -EINVAL;
5901
5902         return i40e_hw_rss_hash_set(pf, rss_conf);
5903 }
5904
5905 static int
5906 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5907                            struct rte_eth_rss_conf *rss_conf)
5908 {
5909         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5911         uint64_t hena;
5912
5913         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5914                          &rss_conf->rss_key_len);
5915
5916         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5917         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5918         rss_conf->rss_hf = i40e_parse_hena(hena);
5919
5920         return 0;
5921 }
5922
5923 static int
5924 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5925 {
5926         switch (filter_type) {
5927         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5928                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5929                 break;
5930         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5931                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5932                 break;
5933         case RTE_TUNNEL_FILTER_IMAC_TENID:
5934                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5935                 break;
5936         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5937                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5938                 break;
5939         case ETH_TUNNEL_FILTER_IMAC:
5940                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5941                 break;
5942         case ETH_TUNNEL_FILTER_OIP:
5943                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
5944                 break;
5945         case ETH_TUNNEL_FILTER_IIP:
5946                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
5947                 break;
5948         default:
5949                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5950                 return -EINVAL;
5951         }
5952
5953         return 0;
5954 }
5955
5956 static int
5957 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5958                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5959                         uint8_t add)
5960 {
5961         uint16_t ip_type;
5962         uint8_t i, tun_type = 0;
5963         /* internal varialbe to convert ipv6 byte order */
5964         uint32_t convert_ipv6[4];
5965         int val, ret = 0;
5966         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5967         struct i40e_vsi *vsi = pf->main_vsi;
5968         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5969         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5970
5971         cld_filter = rte_zmalloc("tunnel_filter",
5972                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5973                 0);
5974
5975         if (NULL == cld_filter) {
5976                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5977                 return -EINVAL;
5978         }
5979         pfilter = cld_filter;
5980
5981         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
5982         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
5983
5984         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
5985         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5986                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5987                 rte_memcpy(&pfilter->ipaddr.v4.data,
5988                                 &rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv4_addr),
5989                                 sizeof(pfilter->ipaddr.v4.data));
5990         } else {
5991                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5992                 for (i = 0; i < 4; i++) {
5993                         convert_ipv6[i] =
5994                         rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv6_addr[i]);
5995                 }
5996                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
5997                                 sizeof(pfilter->ipaddr.v6.data));
5998         }
5999
6000         /* check tunneled type */
6001         switch (tunnel_filter->tunnel_type) {
6002         case RTE_TUNNEL_TYPE_VXLAN:
6003                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6004                 break;
6005         case RTE_TUNNEL_TYPE_NVGRE:
6006                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6007                 break;
6008         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6009                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6010                 break;
6011         default:
6012                 /* Other tunnel types is not supported. */
6013                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6014                 rte_free(cld_filter);
6015                 return -EINVAL;
6016         }
6017
6018         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6019                                                 &pfilter->flags);
6020         if (val < 0) {
6021                 rte_free(cld_filter);
6022                 return -EINVAL;
6023         }
6024
6025         pfilter->flags |= rte_cpu_to_le_16(
6026                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6027                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6028         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6029         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6030
6031         if (add)
6032                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6033         else
6034                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6035                                                 cld_filter, 1);
6036
6037         rte_free(cld_filter);
6038         return ret;
6039 }
6040
6041 static int
6042 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6043 {
6044         uint8_t i;
6045
6046         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6047                 if (pf->vxlan_ports[i] == port)
6048                         return i;
6049         }
6050
6051         return -1;
6052 }
6053
6054 static int
6055 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6056 {
6057         int  idx, ret;
6058         uint8_t filter_idx;
6059         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6060
6061         idx = i40e_get_vxlan_port_idx(pf, port);
6062
6063         /* Check if port already exists */
6064         if (idx >= 0) {
6065                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6066                 return -EINVAL;
6067         }
6068
6069         /* Now check if there is space to add the new port */
6070         idx = i40e_get_vxlan_port_idx(pf, 0);
6071         if (idx < 0) {
6072                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6073                         "not adding port %d", port);
6074                 return -ENOSPC;
6075         }
6076
6077         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6078                                         &filter_idx, NULL);
6079         if (ret < 0) {
6080                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6081                 return -1;
6082         }
6083
6084         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6085                          port,  filter_idx);
6086
6087         /* New port: add it and mark its index in the bitmap */
6088         pf->vxlan_ports[idx] = port;
6089         pf->vxlan_bitmap |= (1 << idx);
6090
6091         if (!(pf->flags & I40E_FLAG_VXLAN))
6092                 pf->flags |= I40E_FLAG_VXLAN;
6093
6094         return 0;
6095 }
6096
6097 static int
6098 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6099 {
6100         int idx;
6101         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6102
6103         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6104                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6105                 return -EINVAL;
6106         }
6107
6108         idx = i40e_get_vxlan_port_idx(pf, port);
6109
6110         if (idx < 0) {
6111                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6112                 return -EINVAL;
6113         }
6114
6115         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6116                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6117                 return -1;
6118         }
6119
6120         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6121                         port, idx);
6122
6123         pf->vxlan_ports[idx] = 0;
6124         pf->vxlan_bitmap &= ~(1 << idx);
6125
6126         if (!pf->vxlan_bitmap)
6127                 pf->flags &= ~I40E_FLAG_VXLAN;
6128
6129         return 0;
6130 }
6131
6132 /* Add UDP tunneling port */
6133 static int
6134 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6135                              struct rte_eth_udp_tunnel *udp_tunnel)
6136 {
6137         int ret = 0;
6138         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6139
6140         if (udp_tunnel == NULL)
6141                 return -EINVAL;
6142
6143         switch (udp_tunnel->prot_type) {
6144         case RTE_TUNNEL_TYPE_VXLAN:
6145                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6146                 break;
6147
6148         case RTE_TUNNEL_TYPE_GENEVE:
6149         case RTE_TUNNEL_TYPE_TEREDO:
6150                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6151                 ret = -1;
6152                 break;
6153
6154         default:
6155                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6156                 ret = -1;
6157                 break;
6158         }
6159
6160         return ret;
6161 }
6162
6163 /* Remove UDP tunneling port */
6164 static int
6165 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6166                              struct rte_eth_udp_tunnel *udp_tunnel)
6167 {
6168         int ret = 0;
6169         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6170
6171         if (udp_tunnel == NULL)
6172                 return -EINVAL;
6173
6174         switch (udp_tunnel->prot_type) {
6175         case RTE_TUNNEL_TYPE_VXLAN:
6176                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6177                 break;
6178         case RTE_TUNNEL_TYPE_GENEVE:
6179         case RTE_TUNNEL_TYPE_TEREDO:
6180                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6181                 ret = -1;
6182                 break;
6183         default:
6184                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6185                 ret = -1;
6186                 break;
6187         }
6188
6189         return ret;
6190 }
6191
6192 /* Calculate the maximum number of contiguous PF queues that are configured */
6193 static int
6194 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6195 {
6196         struct rte_eth_dev_data *data = pf->dev_data;
6197         int i, num;
6198         struct i40e_rx_queue *rxq;
6199
6200         num = 0;
6201         for (i = 0; i < pf->lan_nb_qps; i++) {
6202                 rxq = data->rx_queues[i];
6203                 if (rxq && rxq->q_set)
6204                         num++;
6205                 else
6206                         break;
6207         }
6208
6209         return num;
6210 }
6211
6212 /* Configure RSS */
6213 static int
6214 i40e_pf_config_rss(struct i40e_pf *pf)
6215 {
6216         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6217         struct rte_eth_rss_conf rss_conf;
6218         uint32_t i, lut = 0;
6219         uint16_t j, num;
6220
6221         /*
6222          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6223          * It's necessary to calulate the actual PF queues that are configured.
6224          */
6225         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6226                 num = i40e_pf_calc_configured_queues_num(pf);
6227         else
6228                 num = pf->dev_data->nb_rx_queues;
6229
6230         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6231         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6232                         num);
6233
6234         if (num == 0) {
6235                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6236                 return -ENOTSUP;
6237         }
6238
6239         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6240                 if (j == num)
6241                         j = 0;
6242                 lut = (lut << 8) | (j & ((0x1 <<
6243                         hw->func_caps.rss_table_entry_width) - 1));
6244                 if ((i & 3) == 3)
6245                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6246         }
6247
6248         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6249         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6250                 i40e_pf_disable_rss(pf);
6251                 return 0;
6252         }
6253         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6254                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6255                 /* Random default keys */
6256                 static uint32_t rss_key_default[] = {0x6b793944,
6257                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6258                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6259                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6260
6261                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6262                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6263                                                         sizeof(uint32_t);
6264         }
6265
6266         return i40e_hw_rss_hash_set(pf, &rss_conf);
6267 }
6268
6269 static int
6270 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6271                                struct rte_eth_tunnel_filter_conf *filter)
6272 {
6273         if (pf == NULL || filter == NULL) {
6274                 PMD_DRV_LOG(ERR, "Invalid parameter");
6275                 return -EINVAL;
6276         }
6277
6278         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6279                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6280                 return -EINVAL;
6281         }
6282
6283         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6284                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6285                 return -EINVAL;
6286         }
6287
6288         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6289                 (is_zero_ether_addr(&filter->outer_mac))) {
6290                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6291                 return -EINVAL;
6292         }
6293
6294         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6295                 (is_zero_ether_addr(&filter->inner_mac))) {
6296                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6297                 return -EINVAL;
6298         }
6299
6300         return 0;
6301 }
6302
6303 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6304 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6305 static int
6306 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6307 {
6308         uint32_t val, reg;
6309         int ret = -EINVAL;
6310
6311         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6312         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6313
6314         if (len == 3) {
6315                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6316         } else if (len == 4) {
6317                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6318         } else {
6319                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6320                 return ret;
6321         }
6322
6323         if (reg != val) {
6324                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6325                                                    reg, NULL);
6326                 if (ret != 0)
6327                         return ret;
6328         } else {
6329                 ret = 0;
6330         }
6331         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6332                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6333
6334         return ret;
6335 }
6336
6337 static int
6338 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6339 {
6340         int ret = -EINVAL;
6341
6342         if (!hw || !cfg)
6343                 return -EINVAL;
6344
6345         switch (cfg->cfg_type) {
6346         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6347                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6348                 break;
6349         default:
6350                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6351                 break;
6352         }
6353
6354         return ret;
6355 }
6356
6357 static int
6358 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6359                                enum rte_filter_op filter_op,
6360                                void *arg)
6361 {
6362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6363         int ret = I40E_ERR_PARAM;
6364
6365         switch (filter_op) {
6366         case RTE_ETH_FILTER_SET:
6367                 ret = i40e_dev_global_config_set(hw,
6368                         (struct rte_eth_global_cfg *)arg);
6369                 break;
6370         default:
6371                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6372                 break;
6373         }
6374
6375         return ret;
6376 }
6377
6378 static int
6379 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6380                           enum rte_filter_op filter_op,
6381                           void *arg)
6382 {
6383         struct rte_eth_tunnel_filter_conf *filter;
6384         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6385         int ret = I40E_SUCCESS;
6386
6387         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6388
6389         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6390                 return I40E_ERR_PARAM;
6391
6392         switch (filter_op) {
6393         case RTE_ETH_FILTER_NOP:
6394                 if (!(pf->flags & I40E_FLAG_VXLAN))
6395                         ret = I40E_NOT_SUPPORTED;
6396                 break;
6397         case RTE_ETH_FILTER_ADD:
6398                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6399                 break;
6400         case RTE_ETH_FILTER_DELETE:
6401                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6402                 break;
6403         default:
6404                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6405                 ret = I40E_ERR_PARAM;
6406                 break;
6407         }
6408
6409         return ret;
6410 }
6411
6412 static int
6413 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6414 {
6415         int ret = 0;
6416         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6417
6418         /* RSS setup */
6419         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6420                 ret = i40e_pf_config_rss(pf);
6421         else
6422                 i40e_pf_disable_rss(pf);
6423
6424         return ret;
6425 }
6426
6427 /* Get the symmetric hash enable configurations per port */
6428 static void
6429 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6430 {
6431         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6432
6433         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6434 }
6435
6436 /* Set the symmetric hash enable configurations per port */
6437 static void
6438 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6439 {
6440         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6441
6442         if (enable > 0) {
6443                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6444                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6445                                                         "been enabled");
6446                         return;
6447                 }
6448                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6449         } else {
6450                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6451                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6452                                                         "been disabled");
6453                         return;
6454                 }
6455                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6456         }
6457         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6458         I40E_WRITE_FLUSH(hw);
6459 }
6460
6461 /*
6462  * Get global configurations of hash function type and symmetric hash enable
6463  * per flow type (pctype). Note that global configuration means it affects all
6464  * the ports on the same NIC.
6465  */
6466 static int
6467 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6468                                    struct rte_eth_hash_global_conf *g_cfg)
6469 {
6470         uint32_t reg, mask = I40E_FLOW_TYPES;
6471         uint16_t i;
6472         enum i40e_filter_pctype pctype;
6473
6474         memset(g_cfg, 0, sizeof(*g_cfg));
6475         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6476         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6477                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6478         else
6479                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6480         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6481                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6482
6483         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6484                 if (!(mask & (1UL << i)))
6485                         continue;
6486                 mask &= ~(1UL << i);
6487                 /* Bit set indicats the coresponding flow type is supported */
6488                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6489                 pctype = i40e_flowtype_to_pctype(i);
6490                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6491                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6492                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6493         }
6494
6495         return 0;
6496 }
6497
6498 static int
6499 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6500 {
6501         uint32_t i;
6502         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6503
6504         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6505                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6506                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6507                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6508                                                 g_cfg->hash_func);
6509                 return -EINVAL;
6510         }
6511
6512         /*
6513          * As i40e supports less than 32 flow types, only first 32 bits need to
6514          * be checked.
6515          */
6516         mask0 = g_cfg->valid_bit_mask[0];
6517         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6518                 if (i == 0) {
6519                         /* Check if any unsupported flow type configured */
6520                         if ((mask0 | i40e_mask) ^ i40e_mask)
6521                                 goto mask_err;
6522                 } else {
6523                         if (g_cfg->valid_bit_mask[i])
6524                                 goto mask_err;
6525                 }
6526         }
6527
6528         return 0;
6529
6530 mask_err:
6531         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6532
6533         return -EINVAL;
6534 }
6535
6536 /*
6537  * Set global configurations of hash function type and symmetric hash enable
6538  * per flow type (pctype). Note any modifying global configuration will affect
6539  * all the ports on the same NIC.
6540  */
6541 static int
6542 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6543                                    struct rte_eth_hash_global_conf *g_cfg)
6544 {
6545         int ret;
6546         uint16_t i;
6547         uint32_t reg;
6548         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6549         enum i40e_filter_pctype pctype;
6550
6551         /* Check the input parameters */
6552         ret = i40e_hash_global_config_check(g_cfg);
6553         if (ret < 0)
6554                 return ret;
6555
6556         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6557                 if (!(mask0 & (1UL << i)))
6558                         continue;
6559                 mask0 &= ~(1UL << i);
6560                 pctype = i40e_flowtype_to_pctype(i);
6561                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6562                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6563                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6564         }
6565
6566         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6567         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6568                 /* Toeplitz */
6569                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6570                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6571                                                                 "Toeplitz");
6572                         goto out;
6573                 }
6574                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6575         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6576                 /* Simple XOR */
6577                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6578                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6579                                                         "Simple XOR");
6580                         goto out;
6581                 }
6582                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6583         } else
6584                 /* Use the default, and keep it as it is */
6585                 goto out;
6586
6587         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6588
6589 out:
6590         I40E_WRITE_FLUSH(hw);
6591
6592         return 0;
6593 }
6594
6595 /**
6596  * Valid input sets for hash and flow director filters per PCTYPE
6597  */
6598 static uint64_t
6599 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6600                 enum rte_filter_type filter)
6601 {
6602         uint64_t valid;
6603
6604         static const uint64_t valid_hash_inset_table[] = {
6605                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6606                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6607                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6608                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6609                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6610                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6611                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6612                         I40E_INSET_FLEX_PAYLOAD,
6613                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6614                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6615                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6616                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6617                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6618                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6619                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6620                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6621                         I40E_INSET_FLEX_PAYLOAD,
6622                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6623                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6624                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6625                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6626                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6627                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6628                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6629                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6630                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6631                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6632                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6633                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6634                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6635                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6636                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6637                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6638                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6639                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6640                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6641                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6642                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6643                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6644                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6645                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6646                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6647                         I40E_INSET_FLEX_PAYLOAD,
6648                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6649                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6650                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6651                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6652                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6653                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6654                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6655                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6656                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6657                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6658                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6659                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6660                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6661                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6662                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6663                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6664                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6665                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6666                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6667                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6668                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6669                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6670                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6671                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6672                         I40E_INSET_FLEX_PAYLOAD,
6673                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6674                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6675                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6676                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6677                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6678                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6679                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6680                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6681                         I40E_INSET_FLEX_PAYLOAD,
6682                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6683                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6684                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6685                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6686                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6687                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6688                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6689                         I40E_INSET_FLEX_PAYLOAD,
6690                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6691                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6692                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6693                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6694                         I40E_INSET_FLEX_PAYLOAD,
6695         };
6696
6697         /**
6698          * Flow director supports only fields defined in
6699          * union rte_eth_fdir_flow.
6700          */
6701         static const uint64_t valid_fdir_inset_table[] = {
6702                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6703                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6704                 I40E_INSET_FLEX_PAYLOAD,
6705                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6706                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6707                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6708                 I40E_INSET_FLEX_PAYLOAD,
6709                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6710                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6711                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6712                 I40E_INSET_FLEX_PAYLOAD,
6713                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6714                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6715                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6716                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6717                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6718                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6719                 I40E_INSET_FLEX_PAYLOAD,
6720                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6721                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6722                 I40E_INSET_FLEX_PAYLOAD,
6723                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6724                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6725                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6726                 I40E_INSET_FLEX_PAYLOAD,
6727                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6728                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6729                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6730                 I40E_INSET_FLEX_PAYLOAD,
6731                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6732                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6733                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6734                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6735                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6736                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6737                 I40E_INSET_FLEX_PAYLOAD,
6738                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6739                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6740         };
6741
6742         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6743                 return 0;
6744         if (filter == RTE_ETH_FILTER_HASH)
6745                 valid = valid_hash_inset_table[pctype];
6746         else
6747                 valid = valid_fdir_inset_table[pctype];
6748
6749         return valid;
6750 }
6751
6752 /**
6753  * Validate if the input set is allowed for a specific PCTYPE
6754  */
6755 static int
6756 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6757                 enum rte_filter_type filter, uint64_t inset)
6758 {
6759         uint64_t valid;
6760
6761         valid = i40e_get_valid_input_set(pctype, filter);
6762         if (inset & (~valid))
6763                 return -EINVAL;
6764
6765         return 0;
6766 }
6767
6768 /* default input set fields combination per pctype */
6769 static uint64_t
6770 i40e_get_default_input_set(uint16_t pctype)
6771 {
6772         static const uint64_t default_inset_table[] = {
6773                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6774                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6775                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6776                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6777                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6778                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6779                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6780                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6781                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6782                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6783                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6784                         I40E_INSET_SCTP_VT,
6785                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6786                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6787                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6788                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6789                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6790                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6791                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6792                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6793                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6794                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6795                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6796                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6797                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6798                         I40E_INSET_SCTP_VT,
6799                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6800                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6801                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6802                         I40E_INSET_LAST_ETHER_TYPE,
6803         };
6804
6805         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6806                 return 0;
6807
6808         return default_inset_table[pctype];
6809 }
6810
6811 /**
6812  * Parse the input set from index to logical bit masks
6813  */
6814 static int
6815 i40e_parse_input_set(uint64_t *inset,
6816                      enum i40e_filter_pctype pctype,
6817                      enum rte_eth_input_set_field *field,
6818                      uint16_t size)
6819 {
6820         uint16_t i, j;
6821         int ret = -EINVAL;
6822
6823         static const struct {
6824                 enum rte_eth_input_set_field field;
6825                 uint64_t inset;
6826         } inset_convert_table[] = {
6827                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6828                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6829                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6830                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6831                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6832                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6833                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6834                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6835                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6836                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6837                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6838                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6839                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6840                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6841                         I40E_INSET_IPV6_NEXT_HDR},
6842                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6843                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6844                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6845                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6846                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6847                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6848                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6849                         I40E_INSET_SCTP_VT},
6850                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6851                         I40E_INSET_TUNNEL_DMAC},
6852                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6853                         I40E_INSET_VLAN_TUNNEL},
6854                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6855                         I40E_INSET_TUNNEL_ID},
6856                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6857                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6858                         I40E_INSET_FLEX_PAYLOAD_W1},
6859                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6860                         I40E_INSET_FLEX_PAYLOAD_W2},
6861                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6862                         I40E_INSET_FLEX_PAYLOAD_W3},
6863                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6864                         I40E_INSET_FLEX_PAYLOAD_W4},
6865                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6866                         I40E_INSET_FLEX_PAYLOAD_W5},
6867                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6868                         I40E_INSET_FLEX_PAYLOAD_W6},
6869                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6870                         I40E_INSET_FLEX_PAYLOAD_W7},
6871                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6872                         I40E_INSET_FLEX_PAYLOAD_W8},
6873         };
6874
6875         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6876                 return ret;
6877
6878         /* Only one item allowed for default or all */
6879         if (size == 1) {
6880                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6881                         *inset = i40e_get_default_input_set(pctype);
6882                         return 0;
6883                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6884                         *inset = I40E_INSET_NONE;
6885                         return 0;
6886                 }
6887         }
6888
6889         for (i = 0, *inset = 0; i < size; i++) {
6890                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6891                         if (field[i] == inset_convert_table[j].field) {
6892                                 *inset |= inset_convert_table[j].inset;
6893                                 break;
6894                         }
6895                 }
6896
6897                 /* It contains unsupported input set, return immediately */
6898                 if (j == RTE_DIM(inset_convert_table))
6899                         return ret;
6900         }
6901
6902         return 0;
6903 }
6904
6905 /**
6906  * Translate the input set from bit masks to register aware bit masks
6907  * and vice versa
6908  */
6909 static uint64_t
6910 i40e_translate_input_set_reg(uint64_t input)
6911 {
6912         uint64_t val = 0;
6913         uint16_t i;
6914
6915         static const struct {
6916                 uint64_t inset;
6917                 uint64_t inset_reg;
6918         } inset_map[] = {
6919                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6920                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6921                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6922                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6923                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6924                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6925                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6926                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6927                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6928                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6929                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6930                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6931                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6932                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6933                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6934                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6935                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6936                 {I40E_INSET_TUNNEL_DMAC,
6937                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6938                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6939                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6940                 {I40E_INSET_TUNNEL_SRC_PORT,
6941                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6942                 {I40E_INSET_TUNNEL_DST_PORT,
6943                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6944                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6945                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6946                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6947                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6948                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6949                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6950                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6951                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6952                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6953         };
6954
6955         if (input == 0)
6956                 return val;
6957
6958         /* Translate input set to register aware inset */
6959         for (i = 0; i < RTE_DIM(inset_map); i++) {
6960                 if (input & inset_map[i].inset)
6961                         val |= inset_map[i].inset_reg;
6962         }
6963
6964         return val;
6965 }
6966
6967 static uint8_t
6968 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6969 {
6970         uint8_t i, idx = 0;
6971
6972         static const struct {
6973                 uint64_t inset;
6974                 uint32_t mask;
6975         } inset_mask_map[] = {
6976                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6977                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6978                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6979                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6980         };
6981
6982         if (!inset || !mask || !nb_elem)
6983                 return 0;
6984
6985         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6986                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6987                         mask[i] = 0;
6988                 return I40E_INSET_MASK_NUM_REG;
6989         }
6990
6991         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6992                 if (idx >= nb_elem)
6993                         break;
6994                 if (inset & inset_mask_map[i].inset) {
6995                         mask[idx] = inset_mask_map[i].mask;
6996                         idx++;
6997                 }
6998         }
6999
7000         return idx;
7001 }
7002
7003 static uint64_t
7004 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
7005                             enum i40e_filter_pctype pctype)
7006 {
7007         uint64_t reg = 0;
7008
7009         if (filter == RTE_ETH_FILTER_HASH) {
7010                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7011                 reg <<= I40E_32_BIT_WIDTH;
7012                 reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7013         } else if (filter == RTE_ETH_FILTER_FDIR) {
7014                 reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7015                 reg <<= I40E_32_BIT_WIDTH;
7016                 reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7017         }
7018
7019         return reg;
7020 }
7021
7022 static void
7023 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7024 {
7025         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7026
7027         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7028         if (reg != val)
7029                 i40e_write_rx_ctl(hw, addr, val);
7030         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7031                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7032 }
7033
7034 static int
7035 i40e_set_hash_inset_mask(struct i40e_hw *hw,
7036                          enum i40e_filter_pctype pctype,
7037                          enum rte_filter_input_set_op op,
7038                          uint32_t *mask_reg,
7039                          uint8_t num)
7040 {
7041         uint32_t reg;
7042         uint8_t i;
7043
7044         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7045                 return -EINVAL;
7046
7047         if (op == RTE_ETH_INPUT_SET_SELECT) {
7048                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7049                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7050                                              0);
7051                         if (i >= num)
7052                                 continue;
7053                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7054                                              mask_reg[i]);
7055                 }
7056         } else if (op == RTE_ETH_INPUT_SET_ADD) {
7057                 uint8_t j, count = 0;
7058
7059                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7060                         reg = i40e_read_rx_ctl(hw,
7061                                                I40E_GLQF_HASH_MSK(i, pctype));
7062                         if (reg & I40E_GLQF_HASH_MSK_MASK_MASK)
7063                                 count++;
7064                 }
7065                 if (count + num > I40E_INSET_MASK_NUM_REG)
7066                         return -EINVAL;
7067
7068                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7069                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7070                                              mask_reg[j]);
7071         }
7072
7073         return 0;
7074 }
7075
7076 static int
7077 i40e_set_fd_inset_mask(struct i40e_hw *hw,
7078                        enum i40e_filter_pctype pctype,
7079                        enum rte_filter_input_set_op op,
7080                        uint32_t *mask_reg,
7081                        uint8_t num)
7082 {
7083         uint32_t reg;
7084         uint8_t i;
7085
7086         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7087                 return -EINVAL;
7088
7089         if (op == RTE_ETH_INPUT_SET_SELECT) {
7090                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7091                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7092                                              0);
7093                         if (i >= num)
7094                                 continue;
7095                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7096                                              mask_reg[i]);
7097                 }
7098         } else if (op == RTE_ETH_INPUT_SET_ADD) {
7099                 uint8_t j, count = 0;
7100
7101                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7102                         reg = i40e_read_rx_ctl(hw,
7103                                                I40E_GLQF_FD_MSK(i, pctype));
7104                         if (reg & I40E_GLQF_FD_MSK_MASK_MASK)
7105                                 count++;
7106                 }
7107                 if (count + num > I40E_INSET_MASK_NUM_REG)
7108                         return -EINVAL;
7109
7110                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7111                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7112                                              mask_reg[j]);
7113         }
7114
7115         return 0;
7116 }
7117
7118 int
7119 i40e_filter_inset_select(struct i40e_hw *hw,
7120                          struct rte_eth_input_set_conf *conf,
7121                          enum rte_filter_type filter)
7122 {
7123         enum i40e_filter_pctype pctype;
7124         uint64_t inset_reg = 0, input_set;
7125         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
7126         uint8_t num;
7127         int ret;
7128
7129         if (!hw || !conf) {
7130                 PMD_DRV_LOG(ERR, "Invalid pointer");
7131                 return -EFAULT;
7132         }
7133
7134         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7135         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7136                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7137                             conf->flow_type);
7138                 return -EINVAL;
7139         }
7140         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
7141                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7142                 return -EINVAL;
7143         }
7144
7145         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7146                                    conf->inset_size);
7147         if (ret) {
7148                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7149                 return -EINVAL;
7150         }
7151         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
7152                 PMD_DRV_LOG(ERR, "Invalid input set");
7153                 return -EINVAL;
7154         }
7155
7156         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7157                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7158         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7159                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7160                 return -EINVAL;
7161         }
7162         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7163                                            I40E_INSET_MASK_NUM_REG);
7164         inset_reg |= i40e_translate_input_set_reg(input_set);
7165
7166         if (filter == RTE_ETH_FILTER_HASH) {
7167                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7168                                                num);
7169                 if (ret)
7170                         return -EINVAL;
7171
7172                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7173                                       (uint32_t)(inset_reg & UINT32_MAX));
7174                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7175                                      (uint32_t)((inset_reg >>
7176                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7177         } else if (filter == RTE_ETH_FILTER_FDIR) {
7178                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7179                                              num);
7180                 if (ret)
7181                         return -EINVAL;
7182
7183                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7184                                       (uint32_t)(inset_reg & UINT32_MAX));
7185                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7186                                      (uint32_t)((inset_reg >>
7187                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7188         } else {
7189                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7190                 return -EINVAL;
7191         }
7192         I40E_WRITE_FLUSH(hw);
7193
7194         return 0;
7195 }
7196
7197 static int
7198 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7199 {
7200         int ret = 0;
7201
7202         if (!hw || !info) {
7203                 PMD_DRV_LOG(ERR, "Invalid pointer");
7204                 return -EFAULT;
7205         }
7206
7207         switch (info->info_type) {
7208         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7209                 i40e_get_symmetric_hash_enable_per_port(hw,
7210                                         &(info->info.enable));
7211                 break;
7212         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7213                 ret = i40e_get_hash_filter_global_config(hw,
7214                                 &(info->info.global_conf));
7215                 break;
7216         default:
7217                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7218                                                         info->info_type);
7219                 ret = -EINVAL;
7220                 break;
7221         }
7222
7223         return ret;
7224 }
7225
7226 static int
7227 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7228 {
7229         int ret = 0;
7230
7231         if (!hw || !info) {
7232                 PMD_DRV_LOG(ERR, "Invalid pointer");
7233                 return -EFAULT;
7234         }
7235
7236         switch (info->info_type) {
7237         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7238                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7239                 break;
7240         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7241                 ret = i40e_set_hash_filter_global_config(hw,
7242                                 &(info->info.global_conf));
7243                 break;
7244         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7245                 ret = i40e_filter_inset_select(hw,
7246                                                &(info->info.input_set_conf),
7247                                                RTE_ETH_FILTER_HASH);
7248                 break;
7249
7250         default:
7251                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7252                                                         info->info_type);
7253                 ret = -EINVAL;
7254                 break;
7255         }
7256
7257         return ret;
7258 }
7259
7260 /* Operations for hash function */
7261 static int
7262 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7263                       enum rte_filter_op filter_op,
7264                       void *arg)
7265 {
7266         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7267         int ret = 0;
7268
7269         switch (filter_op) {
7270         case RTE_ETH_FILTER_NOP:
7271                 break;
7272         case RTE_ETH_FILTER_GET:
7273                 ret = i40e_hash_filter_get(hw,
7274                         (struct rte_eth_hash_filter_info *)arg);
7275                 break;
7276         case RTE_ETH_FILTER_SET:
7277                 ret = i40e_hash_filter_set(hw,
7278                         (struct rte_eth_hash_filter_info *)arg);
7279                 break;
7280         default:
7281                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7282                                                                 filter_op);
7283                 ret = -ENOTSUP;
7284                 break;
7285         }
7286
7287         return ret;
7288 }
7289
7290 /*
7291  * Configure ethertype filter, which can director packet by filtering
7292  * with mac address and ether_type or only ether_type
7293  */
7294 static int
7295 i40e_ethertype_filter_set(struct i40e_pf *pf,
7296                         struct rte_eth_ethertype_filter *filter,
7297                         bool add)
7298 {
7299         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7300         struct i40e_control_filter_stats stats;
7301         uint16_t flags = 0;
7302         int ret;
7303
7304         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7305                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7306                 return -EINVAL;
7307         }
7308         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7309                 filter->ether_type == ETHER_TYPE_IPv6) {
7310                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7311                         " control packet filter.", filter->ether_type);
7312                 return -EINVAL;
7313         }
7314         if (filter->ether_type == ETHER_TYPE_VLAN)
7315                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7316                         " not supported.");
7317
7318         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7319                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7320         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7321                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7322         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7323
7324         memset(&stats, 0, sizeof(stats));
7325         ret = i40e_aq_add_rem_control_packet_filter(hw,
7326                         filter->mac_addr.addr_bytes,
7327                         filter->ether_type, flags,
7328                         pf->main_vsi->seid,
7329                         filter->queue, add, &stats, NULL);
7330
7331         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7332                          " mac_etype_used = %u, etype_used = %u,"
7333                          " mac_etype_free = %u, etype_free = %u\n",
7334                          ret, stats.mac_etype_used, stats.etype_used,
7335                          stats.mac_etype_free, stats.etype_free);
7336         if (ret < 0)
7337                 return -ENOSYS;
7338         return 0;
7339 }
7340
7341 /*
7342  * Handle operations for ethertype filter.
7343  */
7344 static int
7345 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7346                                 enum rte_filter_op filter_op,
7347                                 void *arg)
7348 {
7349         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7350         int ret = 0;
7351
7352         if (filter_op == RTE_ETH_FILTER_NOP)
7353                 return ret;
7354
7355         if (arg == NULL) {
7356                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7357                             filter_op);
7358                 return -EINVAL;
7359         }
7360
7361         switch (filter_op) {
7362         case RTE_ETH_FILTER_ADD:
7363                 ret = i40e_ethertype_filter_set(pf,
7364                         (struct rte_eth_ethertype_filter *)arg,
7365                         TRUE);
7366                 break;
7367         case RTE_ETH_FILTER_DELETE:
7368                 ret = i40e_ethertype_filter_set(pf,
7369                         (struct rte_eth_ethertype_filter *)arg,
7370                         FALSE);
7371                 break;
7372         default:
7373                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7374                 ret = -ENOSYS;
7375                 break;
7376         }
7377         return ret;
7378 }
7379
7380 static int
7381 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7382                      enum rte_filter_type filter_type,
7383                      enum rte_filter_op filter_op,
7384                      void *arg)
7385 {
7386         int ret = 0;
7387
7388         if (dev == NULL)
7389                 return -EINVAL;
7390
7391         switch (filter_type) {
7392         case RTE_ETH_FILTER_NONE:
7393                 /* For global configuration */
7394                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7395                 break;
7396         case RTE_ETH_FILTER_HASH:
7397                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7398                 break;
7399         case RTE_ETH_FILTER_MACVLAN:
7400                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7401                 break;
7402         case RTE_ETH_FILTER_ETHERTYPE:
7403                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7404                 break;
7405         case RTE_ETH_FILTER_TUNNEL:
7406                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7407                 break;
7408         case RTE_ETH_FILTER_FDIR:
7409                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7410                 break;
7411         default:
7412                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7413                                                         filter_type);
7414                 ret = -EINVAL;
7415                 break;
7416         }
7417
7418         return ret;
7419 }
7420
7421 /*
7422  * Check and enable Extended Tag.
7423  * Enabling Extended Tag is important for 40G performance.
7424  */
7425 static void
7426 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7427 {
7428         uint32_t buf = 0;
7429         int ret;
7430
7431         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7432                                       PCI_DEV_CAP_REG);
7433         if (ret < 0) {
7434                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7435                             PCI_DEV_CAP_REG);
7436                 return;
7437         }
7438         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7439                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7440                 return;
7441         }
7442
7443         buf = 0;
7444         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7445                                       PCI_DEV_CTRL_REG);
7446         if (ret < 0) {
7447                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7448                             PCI_DEV_CTRL_REG);
7449                 return;
7450         }
7451         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7452                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7453                 return;
7454         }
7455         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7456         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7457                                        PCI_DEV_CTRL_REG);
7458         if (ret < 0) {
7459                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7460                             PCI_DEV_CTRL_REG);
7461                 return;
7462         }
7463 }
7464
7465 /*
7466  * As some registers wouldn't be reset unless a global hardware reset,
7467  * hardware initialization is needed to put those registers into an
7468  * expected initial state.
7469  */
7470 static void
7471 i40e_hw_init(struct rte_eth_dev *dev)
7472 {
7473         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7474
7475         i40e_enable_extended_tag(dev);
7476
7477         /* clear the PF Queue Filter control register */
7478         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7479
7480         /* Disable symmetric hash per port */
7481         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7482 }
7483
7484 enum i40e_filter_pctype
7485 i40e_flowtype_to_pctype(uint16_t flow_type)
7486 {
7487         static const enum i40e_filter_pctype pctype_table[] = {
7488                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7489                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7490                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7491                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7492                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7493                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7494                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7495                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7496                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7497                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7498                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7499                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7500                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7501                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7502                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7503                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7504                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7505                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7506                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7507         };
7508
7509         return pctype_table[flow_type];
7510 }
7511
7512 uint16_t
7513 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7514 {
7515         static const uint16_t flowtype_table[] = {
7516                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7517                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7518                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7519                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7520                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7521                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7522                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7523                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7524                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7525                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7526                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7527                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7528                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7529                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7530                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7531                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7532                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7533                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7534                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7535         };
7536
7537         return flowtype_table[pctype];
7538 }
7539
7540 /*
7541  * On X710, performance number is far from the expectation on recent firmware
7542  * versions; on XL710, performance number is also far from the expectation on
7543  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7544  * mode is enabled and port MAC address is equal to the packet destination MAC
7545  * address. The fix for this issue may not be integrated in the following
7546  * firmware version. So the workaround in software driver is needed. It needs
7547  * to modify the initial values of 3 internal only registers for both X710 and
7548  * XL710. Note that the values for X710 or XL710 could be different, and the
7549  * workaround can be removed when it is fixed in firmware in the future.
7550  */
7551
7552 /* For both X710 and XL710 */
7553 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7554 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7555
7556 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7557 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7558
7559 /* For X710 */
7560 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7561 /* For XL710 */
7562 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7563 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7564
7565 static void
7566 i40e_configure_registers(struct i40e_hw *hw)
7567 {
7568         static struct {
7569                 uint32_t addr;
7570                 uint64_t val;
7571         } reg_table[] = {
7572                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7573                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7574                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7575         };
7576         uint64_t reg;
7577         uint32_t i;
7578         int ret;
7579
7580         for (i = 0; i < RTE_DIM(reg_table); i++) {
7581                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7582                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7583                                 reg_table[i].val =
7584                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7585                         else /* For X710 */
7586                                 reg_table[i].val =
7587                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7588                 }
7589
7590                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7591                                                         &reg, NULL);
7592                 if (ret < 0) {
7593                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7594                                                         reg_table[i].addr);
7595                         break;
7596                 }
7597                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7598                                                 reg_table[i].addr, reg);
7599                 if (reg == reg_table[i].val)
7600                         continue;
7601
7602                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7603                                                 reg_table[i].val, NULL);
7604                 if (ret < 0) {
7605                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7606                                 "address of 0x%"PRIx32, reg_table[i].val,
7607                                                         reg_table[i].addr);
7608                         break;
7609                 }
7610                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7611                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7612         }
7613 }
7614
7615 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7616 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7617 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7618 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7619 static int
7620 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7621 {
7622         uint32_t reg;
7623         int ret;
7624
7625         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7626                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7627                 return -EINVAL;
7628         }
7629
7630         /* Configure for double VLAN RX stripping */
7631         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7632         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7633                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7634                 ret = i40e_aq_debug_write_register(hw,
7635                                                    I40E_VSI_TSR(vsi->vsi_id),
7636                                                    reg, NULL);
7637                 if (ret < 0) {
7638                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7639                                     vsi->vsi_id);
7640                         return I40E_ERR_CONFIG;
7641                 }
7642         }
7643
7644         /* Configure for double VLAN TX insertion */
7645         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7646         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7647                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7648                 ret = i40e_aq_debug_write_register(hw,
7649                                                    I40E_VSI_L2TAGSTXVALID(
7650                                                    vsi->vsi_id), reg, NULL);
7651                 if (ret < 0) {
7652                         PMD_DRV_LOG(ERR, "Failed to update "
7653                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7654                         return I40E_ERR_CONFIG;
7655                 }
7656         }
7657
7658         return 0;
7659 }
7660
7661 /**
7662  * i40e_aq_add_mirror_rule
7663  * @hw: pointer to the hardware structure
7664  * @seid: VEB seid to add mirror rule to
7665  * @dst_id: destination vsi seid
7666  * @entries: Buffer which contains the entities to be mirrored
7667  * @count: number of entities contained in the buffer
7668  * @rule_id:the rule_id of the rule to be added
7669  *
7670  * Add a mirror rule for a given veb.
7671  *
7672  **/
7673 static enum i40e_status_code
7674 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7675                         uint16_t seid, uint16_t dst_id,
7676                         uint16_t rule_type, uint16_t *entries,
7677                         uint16_t count, uint16_t *rule_id)
7678 {
7679         struct i40e_aq_desc desc;
7680         struct i40e_aqc_add_delete_mirror_rule cmd;
7681         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7682                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7683                 &desc.params.raw;
7684         uint16_t buff_len;
7685         enum i40e_status_code status;
7686
7687         i40e_fill_default_direct_cmd_desc(&desc,
7688                                           i40e_aqc_opc_add_mirror_rule);
7689         memset(&cmd, 0, sizeof(cmd));
7690
7691         buff_len = sizeof(uint16_t) * count;
7692         desc.datalen = rte_cpu_to_le_16(buff_len);
7693         if (buff_len > 0)
7694                 desc.flags |= rte_cpu_to_le_16(
7695                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7696         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7697                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7698         cmd.num_entries = rte_cpu_to_le_16(count);
7699         cmd.seid = rte_cpu_to_le_16(seid);
7700         cmd.destination = rte_cpu_to_le_16(dst_id);
7701
7702         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7703         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7704         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7705                          "rule_id = %u"
7706                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7707                          hw->aq.asq_last_status, resp->rule_id,
7708                          resp->mirror_rules_used, resp->mirror_rules_free);
7709         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7710
7711         return status;
7712 }
7713
7714 /**
7715  * i40e_aq_del_mirror_rule
7716  * @hw: pointer to the hardware structure
7717  * @seid: VEB seid to add mirror rule to
7718  * @entries: Buffer which contains the entities to be mirrored
7719  * @count: number of entities contained in the buffer
7720  * @rule_id:the rule_id of the rule to be delete
7721  *
7722  * Delete a mirror rule for a given veb.
7723  *
7724  **/
7725 static enum i40e_status_code
7726 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7727                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7728                 uint16_t count, uint16_t rule_id)
7729 {
7730         struct i40e_aq_desc desc;
7731         struct i40e_aqc_add_delete_mirror_rule cmd;
7732         uint16_t buff_len = 0;
7733         enum i40e_status_code status;
7734         void *buff = NULL;
7735
7736         i40e_fill_default_direct_cmd_desc(&desc,
7737                                           i40e_aqc_opc_delete_mirror_rule);
7738         memset(&cmd, 0, sizeof(cmd));
7739         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7740                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7741                                                           I40E_AQ_FLAG_RD));
7742                 cmd.num_entries = count;
7743                 buff_len = sizeof(uint16_t) * count;
7744                 desc.datalen = rte_cpu_to_le_16(buff_len);
7745                 buff = (void *)entries;
7746         } else
7747                 /* rule id is filled in destination field for deleting mirror rule */
7748                 cmd.destination = rte_cpu_to_le_16(rule_id);
7749
7750         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7751                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7752         cmd.seid = rte_cpu_to_le_16(seid);
7753
7754         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7755         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7756
7757         return status;
7758 }
7759
7760 /**
7761  * i40e_mirror_rule_set
7762  * @dev: pointer to the hardware structure
7763  * @mirror_conf: mirror rule info
7764  * @sw_id: mirror rule's sw_id
7765  * @on: enable/disable
7766  *
7767  * set a mirror rule.
7768  *
7769  **/
7770 static int
7771 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7772                         struct rte_eth_mirror_conf *mirror_conf,
7773                         uint8_t sw_id, uint8_t on)
7774 {
7775         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7777         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7778         struct i40e_mirror_rule *parent = NULL;
7779         uint16_t seid, dst_seid, rule_id;
7780         uint16_t i, j = 0;
7781         int ret;
7782
7783         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7784
7785         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7786                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7787                         " without veb or vfs.");
7788                 return -ENOSYS;
7789         }
7790         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7791                 PMD_DRV_LOG(ERR, "mirror table is full.");
7792                 return -ENOSPC;
7793         }
7794         if (mirror_conf->dst_pool > pf->vf_num) {
7795                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7796                                  mirror_conf->dst_pool);
7797                 return -EINVAL;
7798         }
7799
7800         seid = pf->main_vsi->veb->seid;
7801
7802         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7803                 if (sw_id <= it->index) {
7804                         mirr_rule = it;
7805                         break;
7806                 }
7807                 parent = it;
7808         }
7809         if (mirr_rule && sw_id == mirr_rule->index) {
7810                 if (on) {
7811                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7812                         return -EEXIST;
7813                 } else {
7814                         ret = i40e_aq_del_mirror_rule(hw, seid,
7815                                         mirr_rule->rule_type,
7816                                         mirr_rule->entries,
7817                                         mirr_rule->num_entries, mirr_rule->id);
7818                         if (ret < 0) {
7819                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7820                                                    " ret = %d, aq_err = %d.",
7821                                                    ret, hw->aq.asq_last_status);
7822                                 return -ENOSYS;
7823                         }
7824                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7825                         rte_free(mirr_rule);
7826                         pf->nb_mirror_rule--;
7827                         return 0;
7828                 }
7829         } else if (!on) {
7830                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7831                 return -ENOENT;
7832         }
7833
7834         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7835                                 sizeof(struct i40e_mirror_rule) , 0);
7836         if (!mirr_rule) {
7837                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7838                 return I40E_ERR_NO_MEMORY;
7839         }
7840         switch (mirror_conf->rule_type) {
7841         case ETH_MIRROR_VLAN:
7842                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7843                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7844                                 mirr_rule->entries[j] =
7845                                         mirror_conf->vlan.vlan_id[i];
7846                                 j++;
7847                         }
7848                 }
7849                 if (j == 0) {
7850                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7851                         rte_free(mirr_rule);
7852                         return -EINVAL;
7853                 }
7854                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7855                 break;
7856         case ETH_MIRROR_VIRTUAL_POOL_UP:
7857         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7858                 /* check if the specified pool bit is out of range */
7859                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7860                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7861                         rte_free(mirr_rule);
7862                         return -EINVAL;
7863                 }
7864                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7865                         if (mirror_conf->pool_mask & (1ULL << i)) {
7866                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7867                                 j++;
7868                         }
7869                 }
7870                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7871                         /* add pf vsi to entries */
7872                         mirr_rule->entries[j] = pf->main_vsi_seid;
7873                         j++;
7874                 }
7875                 if (j == 0) {
7876                         PMD_DRV_LOG(ERR, "pool is not specified.");
7877                         rte_free(mirr_rule);
7878                         return -EINVAL;
7879                 }
7880                 /* egress and ingress in aq commands means from switch but not port */
7881                 mirr_rule->rule_type =
7882                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7883                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7884                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7885                 break;
7886         case ETH_MIRROR_UPLINK_PORT:
7887                 /* egress and ingress in aq commands means from switch but not port*/
7888                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7889                 break;
7890         case ETH_MIRROR_DOWNLINK_PORT:
7891                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7892                 break;
7893         default:
7894                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7895                         mirror_conf->rule_type);
7896                 rte_free(mirr_rule);
7897                 return -EINVAL;
7898         }
7899
7900         /* If the dst_pool is equal to vf_num, consider it as PF */
7901         if (mirror_conf->dst_pool == pf->vf_num)
7902                 dst_seid = pf->main_vsi_seid;
7903         else
7904                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7905
7906         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7907                                       mirr_rule->rule_type, mirr_rule->entries,
7908                                       j, &rule_id);
7909         if (ret < 0) {
7910                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7911                                    " ret = %d, aq_err = %d.",
7912                                    ret, hw->aq.asq_last_status);
7913                 rte_free(mirr_rule);
7914                 return -ENOSYS;
7915         }
7916
7917         mirr_rule->index = sw_id;
7918         mirr_rule->num_entries = j;
7919         mirr_rule->id = rule_id;
7920         mirr_rule->dst_vsi_seid = dst_seid;
7921
7922         if (parent)
7923                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7924         else
7925                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7926
7927         pf->nb_mirror_rule++;
7928         return 0;
7929 }
7930
7931 /**
7932  * i40e_mirror_rule_reset
7933  * @dev: pointer to the device
7934  * @sw_id: mirror rule's sw_id
7935  *
7936  * reset a mirror rule.
7937  *
7938  **/
7939 static int
7940 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7941 {
7942         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7944         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7945         uint16_t seid;
7946         int ret;
7947
7948         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7949
7950         seid = pf->main_vsi->veb->seid;
7951
7952         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7953                 if (sw_id == it->index) {
7954                         mirr_rule = it;
7955                         break;
7956                 }
7957         }
7958         if (mirr_rule) {
7959                 ret = i40e_aq_del_mirror_rule(hw, seid,
7960                                 mirr_rule->rule_type,
7961                                 mirr_rule->entries,
7962                                 mirr_rule->num_entries, mirr_rule->id);
7963                 if (ret < 0) {
7964                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7965                                            " status = %d, aq_err = %d.",
7966                                            ret, hw->aq.asq_last_status);
7967                         return -ENOSYS;
7968                 }
7969                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7970                 rte_free(mirr_rule);
7971                 pf->nb_mirror_rule--;
7972         } else {
7973                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7974                 return -ENOENT;
7975         }
7976         return 0;
7977 }
7978
7979 static uint64_t
7980 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
7981 {
7982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7983         uint64_t systim_cycles;
7984
7985         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
7986         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
7987                         << 32;
7988
7989         return systim_cycles;
7990 }
7991
7992 static uint64_t
7993 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
7994 {
7995         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7996         uint64_t rx_tstamp;
7997
7998         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7999         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8000                         << 32;
8001
8002         return rx_tstamp;
8003 }
8004
8005 static uint64_t
8006 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8007 {
8008         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8009         uint64_t tx_tstamp;
8010
8011         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8012         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8013                         << 32;
8014
8015         return tx_tstamp;
8016 }
8017
8018 static void
8019 i40e_start_timecounters(struct rte_eth_dev *dev)
8020 {
8021         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8022         struct i40e_adapter *adapter =
8023                         (struct i40e_adapter *)dev->data->dev_private;
8024         struct rte_eth_link link;
8025         uint32_t tsync_inc_l;
8026         uint32_t tsync_inc_h;
8027
8028         /* Get current link speed. */
8029         memset(&link, 0, sizeof(link));
8030         i40e_dev_link_update(dev, 1);
8031         rte_i40e_dev_atomic_read_link_status(dev, &link);
8032
8033         switch (link.link_speed) {
8034         case ETH_LINK_SPEED_40G:
8035                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8036                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8037                 break;
8038         case ETH_LINK_SPEED_10G:
8039                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8040                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8041                 break;
8042         case ETH_LINK_SPEED_1000:
8043                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8044                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8045                 break;
8046         default:
8047                 tsync_inc_l = 0x0;
8048                 tsync_inc_h = 0x0;
8049         }
8050
8051         /* Set the timesync increment value. */
8052         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8053         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8054
8055         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8056         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8057         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8058
8059         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8060         adapter->systime_tc.cc_shift = 0;
8061         adapter->systime_tc.nsec_mask = 0;
8062
8063         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8064         adapter->rx_tstamp_tc.cc_shift = 0;
8065         adapter->rx_tstamp_tc.nsec_mask = 0;
8066
8067         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8068         adapter->tx_tstamp_tc.cc_shift = 0;
8069         adapter->tx_tstamp_tc.nsec_mask = 0;
8070 }
8071
8072 static int
8073 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8074 {
8075         struct i40e_adapter *adapter =
8076                         (struct i40e_adapter *)dev->data->dev_private;
8077
8078         adapter->systime_tc.nsec += delta;
8079         adapter->rx_tstamp_tc.nsec += delta;
8080         adapter->tx_tstamp_tc.nsec += delta;
8081
8082         return 0;
8083 }
8084
8085 static int
8086 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8087 {
8088         uint64_t ns;
8089         struct i40e_adapter *adapter =
8090                         (struct i40e_adapter *)dev->data->dev_private;
8091
8092         ns = rte_timespec_to_ns(ts);
8093
8094         /* Set the timecounters to a new value. */
8095         adapter->systime_tc.nsec = ns;
8096         adapter->rx_tstamp_tc.nsec = ns;
8097         adapter->tx_tstamp_tc.nsec = ns;
8098
8099         return 0;
8100 }
8101
8102 static int
8103 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8104 {
8105         uint64_t ns, systime_cycles;
8106         struct i40e_adapter *adapter =
8107                         (struct i40e_adapter *)dev->data->dev_private;
8108
8109         systime_cycles = i40e_read_systime_cyclecounter(dev);
8110         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8111         *ts = rte_ns_to_timespec(ns);
8112
8113         return 0;
8114 }
8115
8116 static int
8117 i40e_timesync_enable(struct rte_eth_dev *dev)
8118 {
8119         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8120         uint32_t tsync_ctl_l;
8121         uint32_t tsync_ctl_h;
8122
8123         /* Stop the timesync system time. */
8124         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8125         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8126         /* Reset the timesync system time value. */
8127         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8128         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8129
8130         i40e_start_timecounters(dev);
8131
8132         /* Clear timesync registers. */
8133         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8134         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8135         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8136         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8137         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8138         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8139
8140         /* Enable timestamping of PTP packets. */
8141         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8142         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8143
8144         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8145         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8146         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8147
8148         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8149         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8150
8151         return 0;
8152 }
8153
8154 static int
8155 i40e_timesync_disable(struct rte_eth_dev *dev)
8156 {
8157         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8158         uint32_t tsync_ctl_l;
8159         uint32_t tsync_ctl_h;
8160
8161         /* Disable timestamping of transmitted PTP packets. */
8162         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8163         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8164
8165         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8166         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8167
8168         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8169         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8170
8171         /* Reset the timesync increment value. */
8172         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8173         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8174
8175         return 0;
8176 }
8177
8178 static int
8179 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8180                                 struct timespec *timestamp, uint32_t flags)
8181 {
8182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8183         struct i40e_adapter *adapter =
8184                 (struct i40e_adapter *)dev->data->dev_private;
8185
8186         uint32_t sync_status;
8187         uint32_t index = flags & 0x03;
8188         uint64_t rx_tstamp_cycles;
8189         uint64_t ns;
8190
8191         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8192         if ((sync_status & (1 << index)) == 0)
8193                 return -EINVAL;
8194
8195         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8196         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8197         *timestamp = rte_ns_to_timespec(ns);
8198
8199         return 0;
8200 }
8201
8202 static int
8203 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8204                                 struct timespec *timestamp)
8205 {
8206         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8207         struct i40e_adapter *adapter =
8208                 (struct i40e_adapter *)dev->data->dev_private;
8209
8210         uint32_t sync_status;
8211         uint64_t tx_tstamp_cycles;
8212         uint64_t ns;
8213
8214         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8215         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8216                 return -EINVAL;
8217
8218         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8219         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8220         *timestamp = rte_ns_to_timespec(ns);
8221
8222         return 0;
8223 }
8224
8225 /*
8226  * i40e_parse_dcb_configure - parse dcb configure from user
8227  * @dev: the device being configured
8228  * @dcb_cfg: pointer of the result of parse
8229  * @*tc_map: bit map of enabled traffic classes
8230  *
8231  * Returns 0 on success, negative value on failure
8232  */
8233 static int
8234 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8235                          struct i40e_dcbx_config *dcb_cfg,
8236                          uint8_t *tc_map)
8237 {
8238         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8239         uint8_t i, tc_bw, bw_lf;
8240
8241         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8242
8243         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8244         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8245                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8246                 return -EINVAL;
8247         }
8248
8249         /* assume each tc has the same bw */
8250         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8251         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8252                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8253         /* to ensure the sum of tcbw is equal to 100 */
8254         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8255         for (i = 0; i < bw_lf; i++)
8256                 dcb_cfg->etscfg.tcbwtable[i]++;
8257
8258         /* assume each tc has the same Transmission Selection Algorithm */
8259         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8260                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8261
8262         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8263                 dcb_cfg->etscfg.prioritytable[i] =
8264                                 dcb_rx_conf->dcb_tc[i];
8265
8266         /* FW needs one App to configure HW */
8267         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8268         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8269         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8270         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8271
8272         if (dcb_rx_conf->nb_tcs == 0)
8273                 *tc_map = 1; /* tc0 only */
8274         else
8275                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8276
8277         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8278                 dcb_cfg->pfc.willing = 0;
8279                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8280                 dcb_cfg->pfc.pfcenable = *tc_map;
8281         }
8282         return 0;
8283 }
8284
8285
8286 static enum i40e_status_code
8287 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8288                               struct i40e_aqc_vsi_properties_data *info,
8289                               uint8_t enabled_tcmap)
8290 {
8291         enum i40e_status_code ret;
8292         int i, total_tc = 0;
8293         uint16_t qpnum_per_tc, bsf, qp_idx;
8294         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8295
8296         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8297         if (ret != I40E_SUCCESS)
8298                 return ret;
8299
8300         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8301                 if (enabled_tcmap & (1 << i))
8302                         total_tc++;
8303         }
8304         if (total_tc == 0)
8305                 total_tc = 1;
8306         vsi->enabled_tc = enabled_tcmap;
8307
8308         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8309         /* Number of queues per enabled TC */
8310         if (qpnum_per_tc == 0) {
8311                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8312                 return I40E_ERR_INVALID_QP_ID;
8313         }
8314         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8315                                 I40E_MAX_Q_PER_TC);
8316         bsf = rte_bsf32(qpnum_per_tc);
8317
8318         /**
8319          * Configure TC and queue mapping parameters, for enabled TC,
8320          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8321          * default queue will serve it.
8322          */
8323         qp_idx = 0;
8324         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8325                 if (vsi->enabled_tc & (1 << i)) {
8326                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8327                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8328                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8329                         qp_idx += qpnum_per_tc;
8330                 } else
8331                         info->tc_mapping[i] = 0;
8332         }
8333
8334         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8335         if (vsi->type == I40E_VSI_SRIOV) {
8336                 info->mapping_flags |=
8337                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8338                 for (i = 0; i < vsi->nb_qps; i++)
8339                         info->queue_mapping[i] =
8340                                 rte_cpu_to_le_16(vsi->base_queue + i);
8341         } else {
8342                 info->mapping_flags |=
8343                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8344                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8345         }
8346         info->valid_sections |=
8347                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8348
8349         return I40E_SUCCESS;
8350 }
8351
8352 /*
8353  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8354  * @vsi: VSI to be configured
8355  * @tc_map: enabled TC bitmap
8356  *
8357  * Returns 0 on success, negative value on failure
8358  */
8359 static enum i40e_status_code
8360 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8361 {
8362         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8363         struct i40e_vsi_context ctxt;
8364         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8365         enum i40e_status_code ret = I40E_SUCCESS;
8366         int i;
8367
8368         /* Check if enabled_tc is same as existing or new TCs */
8369         if (vsi->enabled_tc == tc_map)
8370                 return ret;
8371
8372         /* configure tc bandwidth */
8373         memset(&bw_data, 0, sizeof(bw_data));
8374         bw_data.tc_valid_bits = tc_map;
8375         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8376         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8377                 if (tc_map & BIT_ULL(i))
8378                         bw_data.tc_bw_credits[i] = 1;
8379         }
8380         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8381         if (ret) {
8382                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8383                         " per TC failed = %d",
8384                         hw->aq.asq_last_status);
8385                 goto out;
8386         }
8387         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8388                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8389
8390         /* Update Queue Pairs Mapping for currently enabled UPs */
8391         ctxt.seid = vsi->seid;
8392         ctxt.pf_num = hw->pf_id;
8393         ctxt.vf_num = 0;
8394         ctxt.uplink_seid = vsi->uplink_seid;
8395         ctxt.info = vsi->info;
8396         i40e_get_cap(hw);
8397         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8398         if (ret)
8399                 goto out;
8400
8401         /* Update the VSI after updating the VSI queue-mapping information */
8402         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8403         if (ret) {
8404                 PMD_INIT_LOG(ERR, "Failed to configure "
8405                             "TC queue mapping = %d",
8406                             hw->aq.asq_last_status);
8407                 goto out;
8408         }
8409         /* update the local VSI info with updated queue map */
8410         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8411                                         sizeof(vsi->info.tc_mapping));
8412         (void)rte_memcpy(&vsi->info.queue_mapping,
8413                         &ctxt.info.queue_mapping,
8414                 sizeof(vsi->info.queue_mapping));
8415         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8416         vsi->info.valid_sections = 0;
8417
8418         /* query and update current VSI BW information */
8419         ret = i40e_vsi_get_bw_config(vsi);
8420         if (ret) {
8421                 PMD_INIT_LOG(ERR,
8422                          "Failed updating vsi bw info, err %s aq_err %s",
8423                          i40e_stat_str(hw, ret),
8424                          i40e_aq_str(hw, hw->aq.asq_last_status));
8425                 goto out;
8426         }
8427
8428         vsi->enabled_tc = tc_map;
8429
8430 out:
8431         return ret;
8432 }
8433
8434 /*
8435  * i40e_dcb_hw_configure - program the dcb setting to hw
8436  * @pf: pf the configuration is taken on
8437  * @new_cfg: new configuration
8438  * @tc_map: enabled TC bitmap
8439  *
8440  * Returns 0 on success, negative value on failure
8441  */
8442 static enum i40e_status_code
8443 i40e_dcb_hw_configure(struct i40e_pf *pf,
8444                       struct i40e_dcbx_config *new_cfg,
8445                       uint8_t tc_map)
8446 {
8447         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8448         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8449         struct i40e_vsi *main_vsi = pf->main_vsi;
8450         struct i40e_vsi_list *vsi_list;
8451         enum i40e_status_code ret;
8452         int i;
8453         uint32_t val;
8454
8455         /* Use the FW API if FW > v4.4*/
8456         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8457               (hw->aq.fw_maj_ver >= 5))) {
8458                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8459                                   " to configure DCB");
8460                 return I40E_ERR_FIRMWARE_API_VERSION;
8461         }
8462
8463         /* Check if need reconfiguration */
8464         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8465                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8466                 return I40E_SUCCESS;
8467         }
8468
8469         /* Copy the new config to the current config */
8470         *old_cfg = *new_cfg;
8471         old_cfg->etsrec = old_cfg->etscfg;
8472         ret = i40e_set_dcb_config(hw);
8473         if (ret) {
8474                 PMD_INIT_LOG(ERR,
8475                          "Set DCB Config failed, err %s aq_err %s\n",
8476                          i40e_stat_str(hw, ret),
8477                          i40e_aq_str(hw, hw->aq.asq_last_status));
8478                 return ret;
8479         }
8480         /* set receive Arbiter to RR mode and ETS scheme by default */
8481         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8482                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8483                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8484                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8485                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8486                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8487                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8488                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8489                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8490                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8491                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8492                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8493                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8494         }
8495         /* get local mib to check whether it is configured correctly */
8496         /* IEEE mode */
8497         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8498         /* Get Local DCB Config */
8499         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8500                                      &hw->local_dcbx_config);
8501
8502         /* Update each VSI */
8503         i40e_vsi_config_tc(main_vsi, tc_map);
8504         if (main_vsi->veb) {
8505                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8506                         /* Beside main VSI, only enable default
8507                          * TC for other VSIs
8508                          */
8509                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8510                                                 I40E_DEFAULT_TCMAP);
8511                         if (ret)
8512                                 PMD_INIT_LOG(WARNING,
8513                                          "Failed configuring TC for VSI seid=%d\n",
8514                                          vsi_list->vsi->seid);
8515                         /* continue */
8516                 }
8517         }
8518         return I40E_SUCCESS;
8519 }
8520
8521 /*
8522  * i40e_dcb_init_configure - initial dcb config
8523  * @dev: device being configured
8524  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8525  *
8526  * Returns 0 on success, negative value on failure
8527  */
8528 static int
8529 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8530 {
8531         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8532         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8533         int ret = 0;
8534
8535         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8536                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8537                 return -ENOTSUP;
8538         }
8539
8540         /* DCB initialization:
8541          * Update DCB configuration from the Firmware and configure
8542          * LLDP MIB change event.
8543          */
8544         if (sw_dcb == TRUE) {
8545                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8546                 if (ret != I40E_SUCCESS)
8547                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8548
8549                 ret = i40e_init_dcb(hw);
8550                 /* if sw_dcb, lldp agent is stopped, the return from
8551                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8552                  * adminq status.
8553                  */
8554                 if (ret != I40E_SUCCESS &&
8555                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8556                         memset(&hw->local_dcbx_config, 0,
8557                                 sizeof(struct i40e_dcbx_config));
8558                         /* set dcb default configuration */
8559                         hw->local_dcbx_config.etscfg.willing = 0;
8560                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8561                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8562                         hw->local_dcbx_config.etscfg.tsatable[0] =
8563                                                 I40E_IEEE_TSA_ETS;
8564                         hw->local_dcbx_config.etsrec =
8565                                 hw->local_dcbx_config.etscfg;
8566                         hw->local_dcbx_config.pfc.willing = 0;
8567                         hw->local_dcbx_config.pfc.pfccap =
8568                                                 I40E_MAX_TRAFFIC_CLASS;
8569                         /* FW needs one App to configure HW */
8570                         hw->local_dcbx_config.numapps = 1;
8571                         hw->local_dcbx_config.app[0].selector =
8572                                                 I40E_APP_SEL_ETHTYPE;
8573                         hw->local_dcbx_config.app[0].priority = 3;
8574                         hw->local_dcbx_config.app[0].protocolid =
8575                                                 I40E_APP_PROTOID_FCOE;
8576                         ret = i40e_set_dcb_config(hw);
8577                         if (ret) {
8578                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8579                                         " err = %d, aq_err = %d.", ret,
8580                                           hw->aq.asq_last_status);
8581                                 return -ENOSYS;
8582                         }
8583                 } else {
8584                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8585                                           " aq_err = %d.", ret,
8586                                           hw->aq.asq_last_status);
8587                         return -ENOTSUP;
8588                 }
8589         } else {
8590                 ret = i40e_aq_start_lldp(hw, NULL);
8591                 if (ret != I40E_SUCCESS)
8592                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8593
8594                 ret = i40e_init_dcb(hw);
8595                 if (!ret) {
8596                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8597                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8598                                                   " DCBX offload.");
8599                                 return -ENOTSUP;
8600                         }
8601                 } else {
8602                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8603                                           " aq_err = %d.", ret,
8604                                           hw->aq.asq_last_status);
8605                         return -ENOTSUP;
8606                 }
8607         }
8608         return 0;
8609 }
8610
8611 /*
8612  * i40e_dcb_setup - setup dcb related config
8613  * @dev: device being configured
8614  *
8615  * Returns 0 on success, negative value on failure
8616  */
8617 static int
8618 i40e_dcb_setup(struct rte_eth_dev *dev)
8619 {
8620         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8621         struct i40e_dcbx_config dcb_cfg;
8622         uint8_t tc_map = 0;
8623         int ret = 0;
8624
8625         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8626                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8627                 return -ENOTSUP;
8628         }
8629
8630         if (pf->vf_num != 0 ||
8631             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8632                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8633
8634         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8635         if (ret) {
8636                 PMD_INIT_LOG(ERR, "invalid dcb config");
8637                 return -EINVAL;
8638         }
8639         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8640         if (ret) {
8641                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8642                 return -ENOSYS;
8643         }
8644
8645         return 0;
8646 }
8647
8648 static int
8649 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8650                       struct rte_eth_dcb_info *dcb_info)
8651 {
8652         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8654         struct i40e_vsi *vsi = pf->main_vsi;
8655         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8656         uint16_t bsf, tc_mapping;
8657         int i;
8658
8659         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8660                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8661         else
8662                 dcb_info->nb_tcs = 1;
8663         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8664                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8665         for (i = 0; i < dcb_info->nb_tcs; i++)
8666                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8667
8668         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8669                 if (vsi->enabled_tc & (1 << i)) {
8670                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8671                         /* only main vsi support multi TCs */
8672                         dcb_info->tc_queue.tc_rxq[0][i].base =
8673                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8674                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8675                         dcb_info->tc_queue.tc_txq[0][i].base =
8676                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8677                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8678                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8679                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8680                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8681                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8682                 }
8683         }
8684
8685         return 0;
8686 }
8687
8688 static int
8689 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8690 {
8691         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8693         uint16_t interval =
8694                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8695         uint16_t msix_intr;
8696
8697         msix_intr = intr_handle->intr_vec[queue_id];
8698         if (msix_intr == I40E_MISC_VEC_ID)
8699                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8700                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8701                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8702                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8703                                (interval <<
8704                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8705         else
8706                 I40E_WRITE_REG(hw,
8707                                I40E_PFINT_DYN_CTLN(msix_intr -
8708                                                    I40E_RX_VEC_START),
8709                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8710                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8711                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8712                                (interval <<
8713                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8714
8715         I40E_WRITE_FLUSH(hw);
8716         rte_intr_enable(&dev->pci_dev->intr_handle);
8717
8718         return 0;
8719 }
8720
8721 static int
8722 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8723 {
8724         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8726         uint16_t msix_intr;
8727
8728         msix_intr = intr_handle->intr_vec[queue_id];
8729         if (msix_intr == I40E_MISC_VEC_ID)
8730                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8731         else
8732                 I40E_WRITE_REG(hw,
8733                                I40E_PFINT_DYN_CTLN(msix_intr -
8734                                                    I40E_RX_VEC_START),
8735                                0);
8736         I40E_WRITE_FLUSH(hw);
8737
8738         return 0;
8739 }