drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66 #include "rte_pmd_i40e.h"
  67
  68 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  69 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  70
  71 #define I40E_CLEAR_PXE_WAIT_MS     200
  72
  73 /* Maximun number of capability elements */
  74 #define I40E_MAX_CAP_ELE_NUM       128
  75
  76 /* Wait count and inteval */
  77 #define I40E_CHK_Q_ENA_COUNT       1000
  78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  79
  80 /* Maximun number of VSI */
  81 #define I40E_MAX_NUM_VSIS          (384UL)
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 117
 118 #define I40E_FLOW_TYPES ( \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 129         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 130
 131 /* Additional timesync values. */
 132 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA     0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 137 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 138
 139 #define I40E_MAX_PERCENT            100
 140 #define I40E_DEFAULT_DCB_APP_NUM    1
 141 #define I40E_DEFAULT_DCB_APP_PRIO   3
 142
 143 /**
 144  * Below are values for writing un-exposed registers suggested
 145  * by silicon experts
 146  */
 147 /* Destination MAC address */
 148 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 149 /* Source MAC address */
 150 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 155 /* Single VLAN tag in the inner L2 header */
 156 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 157 /* Source IPv4 address */
 158 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 159 /* Destination IPv4 address */
 160 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 161 /* Source IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 163 /* Destination IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 165 /* IPv4 Protocol for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 167 /* IPv4 Time to Live for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 169 /* IPv4 Type of Service (TOS) */
 170 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 171 /* IPv4 Protocol */
 172 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 173 /* IPv4 Time to Live */
 174 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 175 /* Source IPv6 address */
 176 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 177 /* Destination IPv6 address */
 178 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 179 /* IPv6 Traffic Class (TC) */
 180 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 181 /* IPv6 Next Header */
 182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 183 /* IPv6 Hop Limit */
 184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 185 /* Source L4 port */
 186 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 187 /* Destination L4 port */
 188 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 189 /* SCTP verification tag */
 190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 193 /* Source port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 195 /* Destination port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 197 /* UDP Tunneling ID, NVGRE/GRE key */
 198 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 199 /* Last ether type */
 200 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 201 /* Tunneling outer destination IPv4 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 203 /* Tunneling outer destination IPv6 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 205 /* 1st word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 207 /* 2nd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 209 /* 3rd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 211 /* 4th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 213 /* 5th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 215 /* 6th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 217 /* 7th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 219 /* 8th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 221 /* all 8 words flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 223 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 224
 225 #define I40E_TRANSLATE_INSET 0
 226 #define I40E_TRANSLATE_REG   1
 227
 228 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 229 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 230 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 231 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 233 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 234
 235 /* PCI offset for querying capability */
 236 #define PCI_DEV_CAP_REG            0xA4
 237 /* PCI offset for enabling/disabling Extended Tag */
 238 #define PCI_DEV_CTRL_REG           0xA8
 239 /* Bit mask of Extended Tag capability */
 240 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 241 /* Bit shift of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 243 /* Bit mask of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 245
 246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int i40e_dev_configure(struct rte_eth_dev *dev);
 249 static int i40e_dev_start(struct rte_eth_dev *dev);
 250 static void i40e_dev_stop(struct rte_eth_dev *dev);
 251 static void i40e_dev_close(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_stats *stats);
 260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_xstat *xstats, unsigned n);
 262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 263                                      struct rte_eth_xstat_name *xstats_names,
 264                                      unsigned limit);
 265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id,
 268                                             uint8_t stat_idx,
 269                                             uint8_t is_rx);
 270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 271                                 char *fw_version, size_t fw_size);
 272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 273                               struct rte_eth_dev_info *dev_info);
 274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 275                                 uint16_t vlan_id,
 276                                 int on);
 277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 278                               enum rte_vlan_type vlan_type,
 279                               uint16_t tpid);
 280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 282                                       uint16_t queue,
 283                                       int on);
 284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 288                               struct rte_eth_fc_conf *fc_conf);
 289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 292                                        struct rte_eth_pfc_conf *pfc_conf);
 293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 294                           struct ether_addr *mac_addr,
 295                           uint32_t index,
 296                           uint32_t pool);
 297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 299                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 300                                     uint16_t reta_size);
 301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 302                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                    uint16_t reta_size);
 304
 305 static int i40e_get_cap(struct i40e_hw *hw);
 306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 307 static int i40e_pf_setup(struct i40e_pf *pf);
 308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 313                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 314 static void i40e_stat_update_48(struct i40e_hw *hw,
 315                                uint32_t hireg,
 316                                uint32_t loreg,
 317                                bool offset_loaded,
 318                                uint64_t *offset,
 319                                uint64_t *stat);
 320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 322                                        void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              struct ether_addr *addr);
 340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 341                                              struct i40e_macvlan_filter *mv_f,
 342                                              int num,
 343                                              uint16_t vlan);
 344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 346                                     struct rte_eth_rss_conf *rss_conf);
 347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 348                                       struct rte_eth_rss_conf *rss_conf);
 349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 350                                         struct rte_eth_udp_tunnel *udp_tunnel);
 351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 352                                         struct rte_eth_udp_tunnel *udp_tunnel);
 353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 358                                 enum rte_filter_type filter_type,
 359                                 enum rte_filter_op filter_op,
 360                                 void *arg);
 361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 362                                   struct rte_eth_dcb_info *dcb_info);
 363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 364 static void i40e_configure_registers(struct i40e_hw *hw);
 365 static void i40e_hw_init(struct rte_eth_dev *dev);
 366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 368                         struct rte_eth_mirror_conf *mirror_conf,
 369                         uint8_t sw_id, uint8_t on);
 370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 371
 372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp,
 376                                            uint32_t flags);
 377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 378                                            struct timespec *timestamp);
 379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 380
 381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 382
 383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 384                                    struct timespec *timestamp);
 385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 386                                     const struct timespec *timestamp);
 387
 388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 389                                          uint16_t queue_id);
 390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 391                                           uint16_t queue_id);
 392
 393 static int i40e_get_regs(struct rte_eth_dev *dev,
 394                          struct rte_dev_reg_info *regs);
 395
 396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 397
 398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 399                            struct rte_dev_eeprom_info *eeprom);
 400
 401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 402                                       struct ether_addr *mac_addr);
 403
 404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 405
 406 static int i40e_ethertype_filter_convert(
 407         const struct rte_eth_ethertype_filter *input,
 408         struct i40e_ethertype_filter *filter);
 409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 410                                    struct i40e_ethertype_filter *filter);
 411
 412 static int i40e_tunnel_filter_convert(
 413         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 414         struct i40e_tunnel_filter *tunnel_filter);
 415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 416                                 struct i40e_tunnel_filter *tunnel_filter);
 417
 418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 420 static void i40e_filter_restore(struct i40e_pf *pf);
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { .vendor_id = 0, /* sentinel */ },
 444 };
 445
 446 static const struct eth_dev_ops i40e_eth_dev_ops = {
 447         .dev_configure                = i40e_dev_configure,
 448         .dev_start                    = i40e_dev_start,
 449         .dev_stop                     = i40e_dev_stop,
 450         .dev_close                    = i40e_dev_close,
 451         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 452         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 453         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 454         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 455         .dev_set_link_up              = i40e_dev_set_link_up,
 456         .dev_set_link_down            = i40e_dev_set_link_down,
 457         .link_update                  = i40e_dev_link_update,
 458         .stats_get                    = i40e_dev_stats_get,
 459         .xstats_get                   = i40e_dev_xstats_get,
 460         .xstats_get_names             = i40e_dev_xstats_get_names,
 461         .stats_reset                  = i40e_dev_stats_reset,
 462         .xstats_reset                 = i40e_dev_stats_reset,
 463         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 464         .fw_version_get               = i40e_fw_version_get,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .rx_queue_count               = i40e_dev_rx_queue_count,
 481         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 482         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 483         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 484         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 485         .tx_queue_release             = i40e_dev_tx_queue_release,
 486         .dev_led_on                   = i40e_dev_led_on,
 487         .dev_led_off                  = i40e_dev_led_off,
 488         .flow_ctrl_get                = i40e_flow_ctrl_get,
 489         .flow_ctrl_set                = i40e_flow_ctrl_set,
 490         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 491         .mac_addr_add                 = i40e_macaddr_add,
 492         .mac_addr_remove              = i40e_macaddr_remove,
 493         .reta_update                  = i40e_dev_rss_reta_update,
 494         .reta_query                   = i40e_dev_rss_reta_query,
 495         .rss_hash_update              = i40e_dev_rss_hash_update,
 496         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 497         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 498         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 499         .filter_ctrl                  = i40e_dev_filter_ctrl,
 500         .rxq_info_get                 = i40e_rxq_info_get,
 501         .txq_info_get                 = i40e_txq_info_get,
 502         .mirror_rule_set              = i40e_mirror_rule_set,
 503         .mirror_rule_reset            = i40e_mirror_rule_reset,
 504         .timesync_enable              = i40e_timesync_enable,
 505         .timesync_disable             = i40e_timesync_disable,
 506         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 507         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 508         .get_dcb_info                 = i40e_dev_get_dcb_info,
 509         .timesync_adjust_time         = i40e_timesync_adjust_time,
 510         .timesync_read_time           = i40e_timesync_read_time,
 511         .timesync_write_time          = i40e_timesync_write_time,
 512         .get_reg                      = i40e_get_regs,
 513         .get_eeprom_length            = i40e_get_eeprom_length,
 514         .get_eeprom                   = i40e_get_eeprom,
 515         .mac_addr_set                 = i40e_set_default_mac_addr,
 516         .mtu_set                      = i40e_dev_mtu_set,
 517 };
 518
 519 /* store statistics names and its offset in stats structure */
 520 struct rte_i40e_xstats_name_off {
 521         char name[RTE_ETH_XSTATS_NAME_SIZE];
 522         unsigned offset;
 523 };
 524
 525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 526         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 527         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 528         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 529         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 530         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 531                 rx_unknown_protocol)},
 532         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 533         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 534         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 535         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 536 };
 537
 538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 539                 sizeof(rte_i40e_stats_strings[0]))
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 542         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 543                 tx_dropped_link_down)},
 544         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 545         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 546                 illegal_bytes)},
 547         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 548         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_local_faults)},
 550         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_remote_faults)},
 552         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_length_errors)},
 554         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 555         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 556         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 557         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 558         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 559         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_127)},
 561         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_255)},
 563         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_511)},
 565         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1023)},
 567         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1522)},
 569         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_big)},
 571         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_undersize)},
 573         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_oversize)},
 575         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 576                 mac_short_packet_dropped)},
 577         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_fragments)},
 579         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 580         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 581         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_127)},
 583         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_255)},
 585         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_511)},
 587         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1023)},
 589         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1522)},
 591         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_big)},
 593         {"rx_flow_director_atr_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 595         {"rx_flow_director_sb_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 597         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_status)},
 599         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_status)},
 601         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_count)},
 603         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_count)},
 605 };
 606
 607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 608                 sizeof(rte_i40e_hw_port_strings[0]))
 609
 610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 611         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_rx)},
 613         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xoff_rx)},
 615 };
 616
 617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 618                 sizeof(rte_i40e_rxq_prio_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_tx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_tx)},
 625         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_2_xoff)},
 627 };
 628
 629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 630                 sizeof(rte_i40e_txq_prio_strings[0]))
 631
 632 static struct eth_driver rte_i40e_pmd = {
 633         .pci_drv = {
 634                 .id_table = pci_id_i40e_map,
 635                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 636                 .probe = rte_eth_dev_pci_probe,
 637                 .remove = rte_eth_dev_pci_remove,
 638         },
 639         .eth_dev_init = eth_i40e_dev_init,
 640         .eth_dev_uninit = eth_i40e_dev_uninit,
 641         .dev_private_size = sizeof(struct i40e_adapter),
 642 };
 643
 644 static inline int
 645 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 646                                      struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = link;
 649         struct rte_eth_link *src = &(dev->data->dev_link);
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 static inline int
 659 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 660                                       struct rte_eth_link *link)
 661 {
 662         struct rte_eth_link *dst = &(dev->data->dev_link);
 663         struct rte_eth_link *src = link;
 664
 665         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 666                                         *(uint64_t *)src) == 0)
 667                 return -1;
 668
 669         return 0;
 670 }
 671
 672 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 673 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 674 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 675
 676 #ifndef I40E_GLQF_ORT
 677 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 678 #endif
 679 #ifndef I40E_GLQF_PIT
 680 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 681 #endif
 682
 683 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 684 {
 685         /*
 686          * Initialize registers for flexible payload, which should be set by NVM.
 687          * This should be removed from code once it is fixed in NVM.
 688          */
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 696         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 697         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 698         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 699         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 700         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 701
 702         /* Initialize registers for parsing packet type of QinQ */
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 704         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 705 }
 706
 707 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 708
 709 /*
 710  * Add a ethertype filter to drop all flow control frames transmitted
 711  * from VSIs.
 712 */
 713 static void
 714 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 715 {
 716         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 717         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 718                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 719                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 720         int ret;
 721
 722         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 723                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 724                                 pf->main_vsi_seid, 0,
 725                                 TRUE, NULL, NULL);
 726         if (ret)
 727                 PMD_INIT_LOG(ERR,
 728                         "Failed to add filter to drop flow control frames from VSIs.");
 729 }
 730
 731 static int
 732 floating_veb_list_handler(__rte_unused const char *key,
 733                           const char *floating_veb_value,
 734                           void *opaque)
 735 {
 736         int idx = 0;
 737         unsigned int count = 0;
 738         char *end = NULL;
 739         int min, max;
 740         bool *vf_floating_veb = opaque;
 741
 742         while (isblank(*floating_veb_value))
 743                 floating_veb_value++;
 744
 745         /* Reset floating VEB configuration for VFs */
 746         for (idx = 0; idx < I40E_MAX_VF; idx++)
 747                 vf_floating_veb[idx] = false;
 748
 749         min = I40E_MAX_VF;
 750         do {
 751                 while (isblank(*floating_veb_value))
 752                         floating_veb_value++;
 753                 if (*floating_veb_value == '\0')
 754                         return -1;
 755                 errno = 0;
 756                 idx = strtoul(floating_veb_value, &end, 10);
 757                 if (errno || end == NULL)
 758                         return -1;
 759                 while (isblank(*end))
 760                         end++;
 761                 if (*end == '-') {
 762                         min = idx;
 763                 } else if ((*end == ';') || (*end == '\0')) {
 764                         max = idx;
 765                         if (min == I40E_MAX_VF)
 766                                 min = idx;
 767                         if (max >= I40E_MAX_VF)
 768                                 max = I40E_MAX_VF - 1;
 769                         for (idx = min; idx <= max; idx++) {
 770                                 vf_floating_veb[idx] = true;
 771                                 count++;
 772                         }
 773                         min = I40E_MAX_VF;
 774                 } else {
 775                         return -1;
 776                 }
 777                 floating_veb_value = end + 1;
 778         } while (*end != '\0');
 779
 780         if (count == 0)
 781                 return -1;
 782
 783         return 0;
 784 }
 785
 786 static void
 787 config_vf_floating_veb(struct rte_devargs *devargs,
 788                        uint16_t floating_veb,
 789                        bool *vf_floating_veb)
 790 {
 791         struct rte_kvargs *kvlist;
 792         int i;
 793         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 794
 795         if (!floating_veb)
 796                 return;
 797         /* All the VFs attach to the floating VEB by default
 798          * when the floating VEB is enabled.
 799          */
 800         for (i = 0; i < I40E_MAX_VF; i++)
 801                 vf_floating_veb[i] = true;
 802
 803         if (devargs == NULL)
 804                 return;
 805
 806         kvlist = rte_kvargs_parse(devargs->args, NULL);
 807         if (kvlist == NULL)
 808                 return;
 809
 810         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 811                 rte_kvargs_free(kvlist);
 812                 return;
 813         }
 814         /* When the floating_veb_list parameter exists, all the VFs
 815          * will attach to the legacy VEB firstly, then configure VFs
 816          * to the floating VEB according to the floating_veb_list.
 817          */
 818         if (rte_kvargs_process(kvlist, floating_veb_list,
 819                                floating_veb_list_handler,
 820                                vf_floating_veb) < 0) {
 821                 rte_kvargs_free(kvlist);
 822                 return;
 823         }
 824         rte_kvargs_free(kvlist);
 825 }
 826
 827 static int
 828 i40e_check_floating_handler(__rte_unused const char *key,
 829                             const char *value,
 830                             __rte_unused void *opaque)
 831 {
 832         if (strcmp(value, "1"))
 833                 return -1;
 834
 835         return 0;
 836 }
 837
 838 static int
 839 is_floating_veb_supported(struct rte_devargs *devargs)
 840 {
 841         struct rte_kvargs *kvlist;
 842         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 843
 844         if (devargs == NULL)
 845                 return 0;
 846
 847         kvlist = rte_kvargs_parse(devargs->args, NULL);
 848         if (kvlist == NULL)
 849                 return 0;
 850
 851         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 852                 rte_kvargs_free(kvlist);
 853                 return 0;
 854         }
 855         /* Floating VEB is enabled when there's key-value:
 856          * enable_floating_veb=1
 857          */
 858         if (rte_kvargs_process(kvlist, floating_veb_key,
 859                                i40e_check_floating_handler, NULL) < 0) {
 860                 rte_kvargs_free(kvlist);
 861                 return 0;
 862         }
 863         rte_kvargs_free(kvlist);
 864
 865         return 1;
 866 }
 867
 868 static void
 869 config_floating_veb(struct rte_eth_dev *dev)
 870 {
 871         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 873         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 874
 875         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 876
 877         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 878                 pf->floating_veb =
 879                         is_floating_veb_supported(pci_dev->device.devargs);
 880                 config_vf_floating_veb(pci_dev->device.devargs,
 881                                        pf->floating_veb,
 882                                        pf->floating_veb_list);
 883         } else {
 884                 pf->floating_veb = false;
 885         }
 886 }
 887
 888 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 889 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 890
 891 static int
 892 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 893 {
 894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 895         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 896         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 897         int ret;
 898
 899         struct rte_hash_parameters ethertype_hash_params = {
 900                 .name = ethertype_hash_name,
 901                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 902                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 903                 .hash_func = rte_hash_crc,
 904                 .hash_func_init_val = 0,
 905                 .socket_id = rte_socket_id(),
 906         };
 907
 908         /* Initialize ethertype filter rule list and hash */
 909         TAILQ_INIT(&ethertype_rule->ethertype_list);
 910         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 911                  "ethertype_%s", dev->data->name);
 912         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 913         if (!ethertype_rule->hash_table) {
 914                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 915                 return -EINVAL;
 916         }
 917         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 918                                        sizeof(struct i40e_ethertype_filter *) *
 919                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 920                                        0);
 921         if (!ethertype_rule->hash_map) {
 922                 PMD_INIT_LOG(ERR,
 923                              "Failed to allocate memory for ethertype hash map!");
 924                 ret = -ENOMEM;
 925                 goto err_ethertype_hash_map_alloc;
 926         }
 927
 928         return 0;
 929
 930 err_ethertype_hash_map_alloc:
 931         rte_hash_free(ethertype_rule->hash_table);
 932
 933         return ret;
 934 }
 935
 936 static int
 937 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 938 {
 939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 940         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 941         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 942         int ret;
 943
 944         struct rte_hash_parameters tunnel_hash_params = {
 945                 .name = tunnel_hash_name,
 946                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 947                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 948                 .hash_func = rte_hash_crc,
 949                 .hash_func_init_val = 0,
 950                 .socket_id = rte_socket_id(),
 951         };
 952
 953         /* Initialize tunnel filter rule list and hash */
 954         TAILQ_INIT(&tunnel_rule->tunnel_list);
 955         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 956                  "tunnel_%s", dev->data->name);
 957         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 958         if (!tunnel_rule->hash_table) {
 959                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 960                 return -EINVAL;
 961         }
 962         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 963                                     sizeof(struct i40e_tunnel_filter *) *
 964                                     I40E_MAX_TUNNEL_FILTER_NUM,
 965                                     0);
 966         if (!tunnel_rule->hash_map) {
 967                 PMD_INIT_LOG(ERR,
 968                              "Failed to allocate memory for tunnel hash map!");
 969                 ret = -ENOMEM;
 970                 goto err_tunnel_hash_map_alloc;
 971         }
 972
 973         return 0;
 974
 975 err_tunnel_hash_map_alloc:
 976         rte_hash_free(tunnel_rule->hash_table);
 977
 978         return ret;
 979 }
 980
 981 static int
 982 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 983 {
 984         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 985         struct i40e_fdir_info *fdir_info = &pf->fdir;
 986         char fdir_hash_name[RTE_HASH_NAMESIZE];
 987         int ret;
 988
 989         struct rte_hash_parameters fdir_hash_params = {
 990                 .name = fdir_hash_name,
 991                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 992                 .key_len = sizeof(struct rte_eth_fdir_input),
 993                 .hash_func = rte_hash_crc,
 994                 .hash_func_init_val = 0,
 995                 .socket_id = rte_socket_id(),
 996         };
 997
 998         /* Initialize flow director filter rule list and hash */
 999         TAILQ_INIT(&fdir_info->fdir_list);
1000         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1001                  "fdir_%s", dev->data->name);
1002         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1003         if (!fdir_info->hash_table) {
1004                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1005                 return -EINVAL;
1006         }
1007         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1008                                           sizeof(struct i40e_fdir_filter *) *
1009                                           I40E_MAX_FDIR_FILTER_NUM,
1010                                           0);
1011         if (!fdir_info->hash_map) {
1012                 PMD_INIT_LOG(ERR,
1013                              "Failed to allocate memory for fdir hash map!");
1014                 ret = -ENOMEM;
1015                 goto err_fdir_hash_map_alloc;
1016         }
1017         return 0;
1018
1019 err_fdir_hash_map_alloc:
1020         rte_hash_free(fdir_info->hash_table);
1021
1022         return ret;
1023 }
1024
1025 static int
1026 eth_i40e_dev_init(struct rte_eth_dev *dev)
1027 {
1028         struct rte_pci_device *pci_dev;
1029         struct rte_intr_handle *intr_handle;
1030         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032         struct i40e_vsi *vsi;
1033         int ret;
1034         uint32_t len;
1035         uint8_t aq_fail = 0;
1036
1037         PMD_INIT_FUNC_TRACE();
1038
1039         dev->dev_ops = &i40e_eth_dev_ops;
1040         dev->rx_pkt_burst = i40e_recv_pkts;
1041         dev->tx_pkt_burst = i40e_xmit_pkts;
1042         dev->tx_pkt_prepare = i40e_prep_pkts;
1043
1044         /* for secondary processes, we don't initialise any further as primary
1045          * has already done this work. Only check we don't need a different
1046          * RX function */
1047         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1048                 i40e_set_rx_function(dev);
1049                 i40e_set_tx_function(dev);
1050                 return 0;
1051         }
1052         pci_dev = I40E_DEV_TO_PCI(dev);
1053         intr_handle = &pci_dev->intr_handle;
1054
1055         rte_eth_copy_pci_info(dev, pci_dev);
1056         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1057
1058         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1059         pf->adapter->eth_dev = dev;
1060         pf->dev_data = dev->data;
1061
1062         hw->back = I40E_PF_TO_ADAPTER(pf);
1063         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1064         if (!hw->hw_addr) {
1065                 PMD_INIT_LOG(ERR,
1066                         "Hardware is not available, as address is NULL");
1067                 return -ENODEV;
1068         }
1069
1070         hw->vendor_id = pci_dev->id.vendor_id;
1071         hw->device_id = pci_dev->id.device_id;
1072         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1073         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1074         hw->bus.device = pci_dev->addr.devid;
1075         hw->bus.func = pci_dev->addr.function;
1076         hw->adapter_stopped = 0;
1077
1078         /* Make sure all is clean before doing PF reset */
1079         i40e_clear_hw(hw);
1080
1081         /* Initialize the hardware */
1082         i40e_hw_init(dev);
1083
1084         /* Reset here to make sure all is clean for each PF */
1085         ret = i40e_pf_reset(hw);
1086         if (ret) {
1087                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1088                 return ret;
1089         }
1090
1091         /* Initialize the shared code (base driver) */
1092         ret = i40e_init_shared_code(hw);
1093         if (ret) {
1094                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1095                 return ret;
1096         }
1097
1098         /*
1099          * To work around the NVM issue, initialize registers
1100          * for flexible payload and packet type of QinQ by
1101          * software. It should be removed once issues are fixed
1102          * in NVM.
1103          */
1104         i40e_GLQF_reg_init(hw);
1105
1106         /* Initialize the input set for filters (hash and fd) to default value */
1107         i40e_filter_input_set_init(pf);
1108
1109         /* Initialize the parameters for adminq */
1110         i40e_init_adminq_parameter(hw);
1111         ret = i40e_init_adminq(hw);
1112         if (ret != I40E_SUCCESS) {
1113                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1114                 return -EIO;
1115         }
1116         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1117                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1118                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1119                      ((hw->nvm.version >> 12) & 0xf),
1120                      ((hw->nvm.version >> 4) & 0xff),
1121                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1122
1123         /* Need the special FW version to support floating VEB */
1124         config_floating_veb(dev);
1125         /* Clear PXE mode */
1126         i40e_clear_pxe_mode(hw);
1127         ret = i40e_dev_sync_phy_type(hw);
1128         if (ret) {
1129                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1130                 goto err_sync_phy_type;
1131         }
1132         /*
1133          * On X710, performance number is far from the expectation on recent
1134          * firmware versions. The fix for this issue may not be integrated in
1135          * the following firmware version. So the workaround in software driver
1136          * is needed. It needs to modify the initial values of 3 internal only
1137          * registers. Note that the workaround can be removed when it is fixed
1138          * in firmware in the future.
1139          */
1140         i40e_configure_registers(hw);
1141
1142         /* Get hw capabilities */
1143         ret = i40e_get_cap(hw);
1144         if (ret != I40E_SUCCESS) {
1145                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1146                 goto err_get_capabilities;
1147         }
1148
1149         /* Initialize parameters for PF */
1150         ret = i40e_pf_parameter_init(dev);
1151         if (ret != 0) {
1152                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1153                 goto err_parameter_init;
1154         }
1155
1156         /* Initialize the queue management */
1157         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1158         if (ret < 0) {
1159                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1160                 goto err_qp_pool_init;
1161         }
1162         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1163                                 hw->func_caps.num_msix_vectors - 1);
1164         if (ret < 0) {
1165                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1166                 goto err_msix_pool_init;
1167         }
1168
1169         /* Initialize lan hmc */
1170         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1171                                 hw->func_caps.num_rx_qp, 0, 0);
1172         if (ret != I40E_SUCCESS) {
1173                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1174                 goto err_init_lan_hmc;
1175         }
1176
1177         /* Configure lan hmc */
1178         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1179         if (ret != I40E_SUCCESS) {
1180                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1181                 goto err_configure_lan_hmc;
1182         }
1183
1184         /* Get and check the mac address */
1185         i40e_get_mac_addr(hw, hw->mac.addr);
1186         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1187                 PMD_INIT_LOG(ERR, "mac address is not valid");
1188                 ret = -EIO;
1189                 goto err_get_mac_addr;
1190         }
1191         /* Copy the permanent MAC address */
1192         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1193                         (struct ether_addr *) hw->mac.perm_addr);
1194
1195         /* Disable flow control */
1196         hw->fc.requested_mode = I40E_FC_NONE;
1197         i40e_set_fc(hw, &aq_fail, TRUE);
1198
1199         /* Set the global registers with default ether type value */
1200         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1201         if (ret != I40E_SUCCESS) {
1202                 PMD_INIT_LOG(ERR,
1203                         "Failed to set the default outer VLAN ether type");
1204                 goto err_setup_pf_switch;
1205         }
1206
1207         /* PF setup, which includes VSI setup */
1208         ret = i40e_pf_setup(pf);
1209         if (ret) {
1210                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1211                 goto err_setup_pf_switch;
1212         }
1213
1214         /* reset all stats of the device, including pf and main vsi */
1215         i40e_dev_stats_reset(dev);
1216
1217         vsi = pf->main_vsi;
1218
1219         /* Disable double vlan by default */
1220         i40e_vsi_config_double_vlan(vsi, FALSE);
1221
1222         /* Disable S-TAG identification when floating_veb is disabled */
1223         if (!pf->floating_veb) {
1224                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1225                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1226                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1227                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1228                 }
1229         }
1230
1231         if (!vsi->max_macaddrs)
1232                 len = ETHER_ADDR_LEN;
1233         else
1234                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1235
1236         /* Should be after VSI initialized */
1237         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1238         if (!dev->data->mac_addrs) {
1239                 PMD_INIT_LOG(ERR,
1240                         "Failed to allocated memory for storing mac address");
1241                 goto err_mac_alloc;
1242         }
1243         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1244                                         &dev->data->mac_addrs[0]);
1245
1246         /* Init dcb to sw mode by default */
1247         ret = i40e_dcb_init_configure(dev, TRUE);
1248         if (ret != I40E_SUCCESS) {
1249                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1250                 pf->flags &= ~I40E_FLAG_DCB;
1251         }
1252         /* Update HW struct after DCB configuration */
1253         i40e_get_cap(hw);
1254
1255         /* initialize pf host driver to setup SRIOV resource if applicable */
1256         i40e_pf_host_init(dev);
1257
1258         /* register callback func to eal lib */
1259         rte_intr_callback_register(intr_handle,
1260                                    i40e_dev_interrupt_handler, dev);
1261
1262         /* configure and enable device interrupt */
1263         i40e_pf_config_irq0(hw, TRUE);
1264         i40e_pf_enable_irq0(hw);
1265
1266         /* enable uio intr after callback register */
1267         rte_intr_enable(intr_handle);
1268         /*
1269          * Add an ethertype filter to drop all flow control frames transmitted
1270          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1271          * frames to wire.
1272          */
1273         i40e_add_tx_flow_control_drop_filter(pf);
1274
1275         /* Set the max frame size to 0x2600 by default,
1276          * in case other drivers changed the default value.
1277          */
1278         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1279
1280         /* initialize mirror rule list */
1281         TAILQ_INIT(&pf->mirror_list);
1282
1283         ret = i40e_init_ethtype_filter_list(dev);
1284         if (ret < 0)
1285                 goto err_init_ethtype_filter_list;
1286         ret = i40e_init_tunnel_filter_list(dev);
1287         if (ret < 0)
1288                 goto err_init_tunnel_filter_list;
1289         ret = i40e_init_fdir_filter_list(dev);
1290         if (ret < 0)
1291                 goto err_init_fdir_filter_list;
1292
1293         return 0;
1294
1295 err_init_fdir_filter_list:
1296         rte_free(pf->tunnel.hash_table);
1297         rte_free(pf->tunnel.hash_map);
1298 err_init_tunnel_filter_list:
1299         rte_free(pf->ethertype.hash_table);
1300         rte_free(pf->ethertype.hash_map);
1301 err_init_ethtype_filter_list:
1302         rte_free(dev->data->mac_addrs);
1303 err_mac_alloc:
1304         i40e_vsi_release(pf->main_vsi);
1305 err_setup_pf_switch:
1306 err_get_mac_addr:
1307 err_configure_lan_hmc:
1308         (void)i40e_shutdown_lan_hmc(hw);
1309 err_init_lan_hmc:
1310         i40e_res_pool_destroy(&pf->msix_pool);
1311 err_msix_pool_init:
1312         i40e_res_pool_destroy(&pf->qp_pool);
1313 err_qp_pool_init:
1314 err_parameter_init:
1315 err_get_capabilities:
1316 err_sync_phy_type:
1317         (void)i40e_shutdown_adminq(hw);
1318
1319         return ret;
1320 }
1321
1322 static void
1323 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1324 {
1325         struct i40e_ethertype_filter *p_ethertype;
1326         struct i40e_ethertype_rule *ethertype_rule;
1327
1328         ethertype_rule = &pf->ethertype;
1329         /* Remove all ethertype filter rules and hash */
1330         if (ethertype_rule->hash_map)
1331                 rte_free(ethertype_rule->hash_map);
1332         if (ethertype_rule->hash_table)
1333                 rte_hash_free(ethertype_rule->hash_table);
1334
1335         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1336                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1337                              p_ethertype, rules);
1338                 rte_free(p_ethertype);
1339         }
1340 }
1341
1342 static void
1343 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1344 {
1345         struct i40e_tunnel_filter *p_tunnel;
1346         struct i40e_tunnel_rule *tunnel_rule;
1347
1348         tunnel_rule = &pf->tunnel;
1349         /* Remove all tunnel director rules and hash */
1350         if (tunnel_rule->hash_map)
1351                 rte_free(tunnel_rule->hash_map);
1352         if (tunnel_rule->hash_table)
1353                 rte_hash_free(tunnel_rule->hash_table);
1354
1355         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1356                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1357                 rte_free(p_tunnel);
1358         }
1359 }
1360
1361 static void
1362 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1363 {
1364         struct i40e_fdir_filter *p_fdir;
1365         struct i40e_fdir_info *fdir_info;
1366
1367         fdir_info = &pf->fdir;
1368         /* Remove all flow director rules and hash */
1369         if (fdir_info->hash_map)
1370                 rte_free(fdir_info->hash_map);
1371         if (fdir_info->hash_table)
1372                 rte_hash_free(fdir_info->hash_table);
1373
1374         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1375                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1376                 rte_free(p_fdir);
1377         }
1378 }
1379
1380 static int
1381 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1382 {
1383         struct i40e_pf *pf;
1384         struct rte_pci_device *pci_dev;
1385         struct rte_intr_handle *intr_handle;
1386         struct i40e_hw *hw;
1387         struct i40e_filter_control_settings settings;
1388         struct rte_flow *p_flow;
1389         int ret;
1390         uint8_t aq_fail = 0;
1391
1392         PMD_INIT_FUNC_TRACE();
1393
1394         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1395                 return 0;
1396
1397         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1398         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1399         pci_dev = I40E_DEV_TO_PCI(dev);
1400         intr_handle = &pci_dev->intr_handle;
1401
1402         if (hw->adapter_stopped == 0)
1403                 i40e_dev_close(dev);
1404
1405         dev->dev_ops = NULL;
1406         dev->rx_pkt_burst = NULL;
1407         dev->tx_pkt_burst = NULL;
1408
1409         /* Clear PXE mode */
1410         i40e_clear_pxe_mode(hw);
1411
1412         /* Unconfigure filter control */
1413         memset(&settings, 0, sizeof(settings));
1414         ret = i40e_set_filter_control(hw, &settings);
1415         if (ret)
1416                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1417                                         ret);
1418
1419         /* Disable flow control */
1420         hw->fc.requested_mode = I40E_FC_NONE;
1421         i40e_set_fc(hw, &aq_fail, TRUE);
1422
1423         /* uninitialize pf host driver */
1424         i40e_pf_host_uninit(dev);
1425
1426         rte_free(dev->data->mac_addrs);
1427         dev->data->mac_addrs = NULL;
1428
1429         /* disable uio intr before callback unregister */
1430         rte_intr_disable(intr_handle);
1431
1432         /* register callback func to eal lib */
1433         rte_intr_callback_unregister(intr_handle,
1434                                      i40e_dev_interrupt_handler, dev);
1435
1436         i40e_rm_ethtype_filter_list(pf);
1437         i40e_rm_tunnel_filter_list(pf);
1438         i40e_rm_fdir_filter_list(pf);
1439
1440         /* Remove all flows */
1441         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1442                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1443                 rte_free(p_flow);
1444         }
1445
1446         return 0;
1447 }
1448
1449 static int
1450 i40e_dev_configure(struct rte_eth_dev *dev)
1451 {
1452         struct i40e_adapter *ad =
1453                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1455         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1456         int i, ret;
1457
1458         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1459          * bulk allocation or vector Rx preconditions we will reset it.
1460          */
1461         ad->rx_bulk_alloc_allowed = true;
1462         ad->rx_vec_allowed = true;
1463         ad->tx_simple_allowed = true;
1464         ad->tx_vec_allowed = true;
1465
1466         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1467                 ret = i40e_fdir_setup(pf);
1468                 if (ret != I40E_SUCCESS) {
1469                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1470                         return -ENOTSUP;
1471                 }
1472                 ret = i40e_fdir_configure(dev);
1473                 if (ret < 0) {
1474                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1475                         goto err;
1476                 }
1477         } else
1478                 i40e_fdir_teardown(pf);
1479
1480         ret = i40e_dev_init_vlan(dev);
1481         if (ret < 0)
1482                 goto err;
1483
1484         /* VMDQ setup.
1485          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1486          *  RSS setting have different requirements.
1487          *  General PMD driver call sequence are NIC init, configure,
1488          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1489          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1490          *  applicable. So, VMDQ setting has to be done before
1491          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1492          *  For RSS setting, it will try to calculate actual configured RX queue
1493          *  number, which will be available after rx_queue_setup(). dev_start()
1494          *  function is good to place RSS setup.
1495          */
1496         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1497                 ret = i40e_vmdq_setup(dev);
1498                 if (ret)
1499                         goto err;
1500         }
1501
1502         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1503                 ret = i40e_dcb_setup(dev);
1504                 if (ret) {
1505                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1506                         goto err_dcb;
1507                 }
1508         }
1509
1510         TAILQ_INIT(&pf->flow_list);
1511
1512         return 0;
1513
1514 err_dcb:
1515         /* need to release vmdq resource if exists */
1516         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1517                 i40e_vsi_release(pf->vmdq[i].vsi);
1518                 pf->vmdq[i].vsi = NULL;
1519         }
1520         rte_free(pf->vmdq);
1521         pf->vmdq = NULL;
1522 err:
1523         /* need to release fdir resource if exists */
1524         i40e_fdir_teardown(pf);
1525         return ret;
1526 }
1527
1528 void
1529 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1530 {
1531         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1532         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1533         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1534         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1535         uint16_t msix_vect = vsi->msix_intr;
1536         uint16_t i;
1537
1538         for (i = 0; i < vsi->nb_qps; i++) {
1539                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1540                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1541                 rte_wmb();
1542         }
1543
1544         if (vsi->type != I40E_VSI_SRIOV) {
1545                 if (!rte_intr_allow_others(intr_handle)) {
1546                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1547                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1548                         I40E_WRITE_REG(hw,
1549                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1550                                        0);
1551                 } else {
1552                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1553                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1554                         I40E_WRITE_REG(hw,
1555                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1556                                                        msix_vect - 1), 0);
1557                 }
1558         } else {
1559                 uint32_t reg;
1560                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1561                         vsi->user_param + (msix_vect - 1);
1562
1563                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1564                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1565         }
1566         I40E_WRITE_FLUSH(hw);
1567 }
1568
1569 static void
1570 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1571                        int base_queue, int nb_queue)
1572 {
1573         int i;
1574         uint32_t val;
1575         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1576
1577         /* Bind all RX queues to allocated MSIX interrupt */
1578         for (i = 0; i < nb_queue; i++) {
1579                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1580                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1581                         ((base_queue + i + 1) <<
1582                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1583                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1584                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1585
1586                 if (i == nb_queue - 1)
1587                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1588                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1589         }
1590
1591         /* Write first RX queue to Link list register as the head element */
1592         if (vsi->type != I40E_VSI_SRIOV) {
1593                 uint16_t interval =
1594                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1595
1596                 if (msix_vect == I40E_MISC_VEC_ID) {
1597                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1598                                        (base_queue <<
1599                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1600                                        (0x0 <<
1601                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1602                         I40E_WRITE_REG(hw,
1603                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1604                                        interval);
1605                 } else {
1606                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1607                                        (base_queue <<
1608                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1609                                        (0x0 <<
1610                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1611                         I40E_WRITE_REG(hw,
1612                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1613                                                        msix_vect - 1),
1614                                        interval);
1615                 }
1616         } else {
1617                 uint32_t reg;
1618
1619                 if (msix_vect == I40E_MISC_VEC_ID) {
1620                         I40E_WRITE_REG(hw,
1621                                        I40E_VPINT_LNKLST0(vsi->user_param),
1622                                        (base_queue <<
1623                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1624                                        (0x0 <<
1625                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1626                 } else {
1627                         /* num_msix_vectors_vf needs to minus irq0 */
1628                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1629                                 vsi->user_param + (msix_vect - 1);
1630
1631                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1632                                        (base_queue <<
1633                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1634                                        (0x0 <<
1635                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1636                 }
1637         }
1638
1639         I40E_WRITE_FLUSH(hw);
1640 }
1641
1642 void
1643 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1644 {
1645         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1646         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1647         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1648         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1649         uint16_t msix_vect = vsi->msix_intr;
1650         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1651         uint16_t queue_idx = 0;
1652         int record = 0;
1653         uint32_t val;
1654         int i;
1655
1656         for (i = 0; i < vsi->nb_qps; i++) {
1657                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1658                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1659         }
1660
1661         /* INTENA flag is not auto-cleared for interrupt */
1662         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1663         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1664                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1665                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1666         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1667
1668         /* VF bind interrupt */
1669         if (vsi->type == I40E_VSI_SRIOV) {
1670                 __vsi_queues_bind_intr(vsi, msix_vect,
1671                                        vsi->base_queue, vsi->nb_qps);
1672                 return;
1673         }
1674
1675         /* PF & VMDq bind interrupt */
1676         if (rte_intr_dp_is_en(intr_handle)) {
1677                 if (vsi->type == I40E_VSI_MAIN) {
1678                         queue_idx = 0;
1679                         record = 1;
1680                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1681                         struct i40e_vsi *main_vsi =
1682                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1683                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1684                         record = 1;
1685                 }
1686         }
1687
1688         for (i = 0; i < vsi->nb_used_qps; i++) {
1689                 if (nb_msix <= 1) {
1690                         if (!rte_intr_allow_others(intr_handle))
1691                                 /* allow to share MISC_VEC_ID */
1692                                 msix_vect = I40E_MISC_VEC_ID;
1693
1694                         /* no enough msix_vect, map all to one */
1695                         __vsi_queues_bind_intr(vsi, msix_vect,
1696                                                vsi->base_queue + i,
1697                                                vsi->nb_used_qps - i);
1698                         for (; !!record && i < vsi->nb_used_qps; i++)
1699                                 intr_handle->intr_vec[queue_idx + i] =
1700                                         msix_vect;
1701                         break;
1702                 }
1703                 /* 1:1 queue/msix_vect mapping */
1704                 __vsi_queues_bind_intr(vsi, msix_vect,
1705                                        vsi->base_queue + i, 1);
1706                 if (!!record)
1707                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1708
1709                 msix_vect++;
1710                 nb_msix--;
1711         }
1712 }
1713
1714 static void
1715 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1716 {
1717         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1718         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1719         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1720         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1721         uint16_t interval = i40e_calc_itr_interval(\
1722                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1723         uint16_t msix_intr, i;
1724
1725         if (rte_intr_allow_others(intr_handle))
1726                 for (i = 0; i < vsi->nb_msix; i++) {
1727                         msix_intr = vsi->msix_intr + i;
1728                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1729                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1730                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1731                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1732                                 (interval <<
1733                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1734                 }
1735         else
1736                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1737                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1738                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1739                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1740                                (interval <<
1741                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1742
1743         I40E_WRITE_FLUSH(hw);
1744 }
1745
1746 static void
1747 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1748 {
1749         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1750         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1751         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1752         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1753         uint16_t msix_intr, i;
1754
1755         if (rte_intr_allow_others(intr_handle))
1756                 for (i = 0; i < vsi->nb_msix; i++) {
1757                         msix_intr = vsi->msix_intr + i;
1758                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1759                                        0);
1760                 }
1761         else
1762                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1763
1764         I40E_WRITE_FLUSH(hw);
1765 }
1766
1767 static inline uint8_t
1768 i40e_parse_link_speeds(uint16_t link_speeds)
1769 {
1770         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1771
1772         if (link_speeds & ETH_LINK_SPEED_40G)
1773                 link_speed |= I40E_LINK_SPEED_40GB;
1774         if (link_speeds & ETH_LINK_SPEED_25G)
1775                 link_speed |= I40E_LINK_SPEED_25GB;
1776         if (link_speeds & ETH_LINK_SPEED_20G)
1777                 link_speed |= I40E_LINK_SPEED_20GB;
1778         if (link_speeds & ETH_LINK_SPEED_10G)
1779                 link_speed |= I40E_LINK_SPEED_10GB;
1780         if (link_speeds & ETH_LINK_SPEED_1G)
1781                 link_speed |= I40E_LINK_SPEED_1GB;
1782         if (link_speeds & ETH_LINK_SPEED_100M)
1783                 link_speed |= I40E_LINK_SPEED_100MB;
1784
1785         return link_speed;
1786 }
1787
1788 static int
1789 i40e_phy_conf_link(struct i40e_hw *hw,
1790                    uint8_t abilities,
1791                    uint8_t force_speed)
1792 {
1793         enum i40e_status_code status;
1794         struct i40e_aq_get_phy_abilities_resp phy_ab;
1795         struct i40e_aq_set_phy_config phy_conf;
1796         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1797                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1798                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1799                         I40E_AQ_PHY_FLAG_LOW_POWER;
1800         const uint8_t advt = I40E_LINK_SPEED_40GB |
1801                         I40E_LINK_SPEED_25GB |
1802                         I40E_LINK_SPEED_10GB |
1803                         I40E_LINK_SPEED_1GB |
1804                         I40E_LINK_SPEED_100MB;
1805         int ret = -ENOTSUP;
1806
1807
1808         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1809                                               NULL);
1810         if (status)
1811                 return ret;
1812
1813         memset(&phy_conf, 0, sizeof(phy_conf));
1814
1815         /* bits 0-2 use the values from get_phy_abilities_resp */
1816         abilities &= ~mask;
1817         abilities |= phy_ab.abilities & mask;
1818
1819         /* update ablities and speed */
1820         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1821                 phy_conf.link_speed = advt;
1822         else
1823                 phy_conf.link_speed = force_speed;
1824
1825         phy_conf.abilities = abilities;
1826
1827         /* use get_phy_abilities_resp value for the rest */
1828         phy_conf.phy_type = phy_ab.phy_type;
1829         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1830         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1831         phy_conf.eee_capability = phy_ab.eee_capability;
1832         phy_conf.eeer = phy_ab.eeer_val;
1833         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1834
1835         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1836                     phy_ab.abilities, phy_ab.link_speed);
1837         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1838                     phy_conf.abilities, phy_conf.link_speed);
1839
1840         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1841         if (status)
1842                 return ret;
1843
1844         return I40E_SUCCESS;
1845 }
1846
1847 static int
1848 i40e_apply_link_speed(struct rte_eth_dev *dev)
1849 {
1850         uint8_t speed;
1851         uint8_t abilities = 0;
1852         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         struct rte_eth_conf *conf = &dev->data->dev_conf;
1854
1855         speed = i40e_parse_link_speeds(conf->link_speeds);
1856         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1857         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1858                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1859         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1860
1861         /* Skip changing speed on 40G interfaces, FW does not support */
1862         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1863                 speed =  I40E_LINK_SPEED_UNKNOWN;
1864                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1865         }
1866
1867         return i40e_phy_conf_link(hw, abilities, speed);
1868 }
1869
1870 static int
1871 i40e_dev_start(struct rte_eth_dev *dev)
1872 {
1873         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1874         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1875         struct i40e_vsi *main_vsi = pf->main_vsi;
1876         int ret, i;
1877         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1878         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1879         uint32_t intr_vector = 0;
1880
1881         hw->adapter_stopped = 0;
1882
1883         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1884                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1885                              dev->data->port_id);
1886                 return -EINVAL;
1887         }
1888
1889         rte_intr_disable(intr_handle);
1890
1891         if ((rte_intr_cap_multiple(intr_handle) ||
1892              !RTE_ETH_DEV_SRIOV(dev).active) &&
1893             dev->data->dev_conf.intr_conf.rxq != 0) {
1894                 intr_vector = dev->data->nb_rx_queues;
1895                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1896                 if (ret)
1897                         return ret;
1898         }
1899
1900         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1901                 intr_handle->intr_vec =
1902                         rte_zmalloc("intr_vec",
1903                                     dev->data->nb_rx_queues * sizeof(int),
1904                                     0);
1905                 if (!intr_handle->intr_vec) {
1906                         PMD_INIT_LOG(ERR,
1907                                 "Failed to allocate %d rx_queues intr_vec",
1908                                 dev->data->nb_rx_queues);
1909                         return -ENOMEM;
1910                 }
1911         }
1912
1913         /* Initialize VSI */
1914         ret = i40e_dev_rxtx_init(pf);
1915         if (ret != I40E_SUCCESS) {
1916                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1917                 goto err_up;
1918         }
1919
1920         /* Map queues with MSIX interrupt */
1921         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1922                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1923         i40e_vsi_queues_bind_intr(main_vsi);
1924         i40e_vsi_enable_queues_intr(main_vsi);
1925
1926         /* Map VMDQ VSI queues with MSIX interrupt */
1927         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1928                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1929                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1930                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1931         }
1932
1933         /* enable FDIR MSIX interrupt */
1934         if (pf->fdir.fdir_vsi) {
1935                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1936                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1937         }
1938
1939         /* Enable all queues which have been configured */
1940         ret = i40e_dev_switch_queues(pf, TRUE);
1941         if (ret != I40E_SUCCESS) {
1942                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1943                 goto err_up;
1944         }
1945
1946         /* Enable receiving broadcast packets */
1947         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1948         if (ret != I40E_SUCCESS)
1949                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1950
1951         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1952                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1953                                                 true, NULL);
1954                 if (ret != I40E_SUCCESS)
1955                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1956         }
1957
1958         /* Apply link configure */
1959         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1960                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1961                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1962                                 ETH_LINK_SPEED_40G)) {
1963                 PMD_DRV_LOG(ERR, "Invalid link setting");
1964                 goto err_up;
1965         }
1966         ret = i40e_apply_link_speed(dev);
1967         if (I40E_SUCCESS != ret) {
1968                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1969                 goto err_up;
1970         }
1971
1972         if (!rte_intr_allow_others(intr_handle)) {
1973                 rte_intr_callback_unregister(intr_handle,
1974                                              i40e_dev_interrupt_handler,
1975                                              (void *)dev);
1976                 /* configure and enable device interrupt */
1977                 i40e_pf_config_irq0(hw, FALSE);
1978                 i40e_pf_enable_irq0(hw);
1979
1980                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1981                         PMD_INIT_LOG(INFO,
1982                                 "lsc won't enable because of no intr multiplex");
1983         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1984                 ret = i40e_aq_set_phy_int_mask(hw,
1985                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1986                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1987                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1988                 if (ret != I40E_SUCCESS)
1989                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1990
1991                 /* Call get_link_info aq commond to enable LSE */
1992                 i40e_dev_link_update(dev, 0);
1993         }
1994
1995         /* enable uio intr after callback register */
1996         rte_intr_enable(intr_handle);
1997
1998         i40e_filter_restore(pf);
1999
2000         return I40E_SUCCESS;
2001
2002 err_up:
2003         i40e_dev_switch_queues(pf, FALSE);
2004         i40e_dev_clear_queues(dev);
2005
2006         return ret;
2007 }
2008
2009 static void
2010 i40e_dev_stop(struct rte_eth_dev *dev)
2011 {
2012         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2013         struct i40e_vsi *main_vsi = pf->main_vsi;
2014         struct i40e_mirror_rule *p_mirror;
2015         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2016         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2017         int i;
2018
2019         /* Disable all queues */
2020         i40e_dev_switch_queues(pf, FALSE);
2021
2022         /* un-map queues with interrupt registers */
2023         i40e_vsi_disable_queues_intr(main_vsi);
2024         i40e_vsi_queues_unbind_intr(main_vsi);
2025
2026         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2027                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2028                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2029         }
2030
2031         if (pf->fdir.fdir_vsi) {
2032                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2033                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2034         }
2035         /* Clear all queues and release memory */
2036         i40e_dev_clear_queues(dev);
2037
2038         /* Set link down */
2039         i40e_dev_set_link_down(dev);
2040
2041         /* Remove all mirror rules */
2042         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2043                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2044                 rte_free(p_mirror);
2045         }
2046         pf->nb_mirror_rule = 0;
2047
2048         if (!rte_intr_allow_others(intr_handle))
2049                 /* resume to the default handler */
2050                 rte_intr_callback_register(intr_handle,
2051                                            i40e_dev_interrupt_handler,
2052                                            (void *)dev);
2053
2054         /* Clean datapath event and queue/vec mapping */
2055         rte_intr_efd_disable(intr_handle);
2056         if (intr_handle->intr_vec) {
2057                 rte_free(intr_handle->intr_vec);
2058                 intr_handle->intr_vec = NULL;
2059         }
2060 }
2061
2062 static void
2063 i40e_dev_close(struct rte_eth_dev *dev)
2064 {
2065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2068         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2069         uint32_t reg;
2070         int i;
2071
2072         PMD_INIT_FUNC_TRACE();
2073
2074         i40e_dev_stop(dev);
2075         hw->adapter_stopped = 1;
2076         i40e_dev_free_queues(dev);
2077
2078         /* Disable interrupt */
2079         i40e_pf_disable_irq0(hw);
2080         rte_intr_disable(intr_handle);
2081
2082         /* shutdown and destroy the HMC */
2083         i40e_shutdown_lan_hmc(hw);
2084
2085         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2086                 i40e_vsi_release(pf->vmdq[i].vsi);
2087                 pf->vmdq[i].vsi = NULL;
2088         }
2089         rte_free(pf->vmdq);
2090         pf->vmdq = NULL;
2091
2092         /* release all the existing VSIs and VEBs */
2093         i40e_fdir_teardown(pf);
2094         i40e_vsi_release(pf->main_vsi);
2095
2096         /* shutdown the adminq */
2097         i40e_aq_queue_shutdown(hw, true);
2098         i40e_shutdown_adminq(hw);
2099
2100         i40e_res_pool_destroy(&pf->qp_pool);
2101         i40e_res_pool_destroy(&pf->msix_pool);
2102
2103         /* force a PF reset to clean anything leftover */
2104         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2105         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2106                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2107         I40E_WRITE_FLUSH(hw);
2108 }
2109
2110 static void
2111 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2112 {
2113         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2114         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115         struct i40e_vsi *vsi = pf->main_vsi;
2116         int status;
2117
2118         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2119                                                      true, NULL, true);
2120         if (status != I40E_SUCCESS)
2121                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2122
2123         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2124                                                         TRUE, NULL);
2125         if (status != I40E_SUCCESS)
2126                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2127
2128 }
2129
2130 static void
2131 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2132 {
2133         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2134         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135         struct i40e_vsi *vsi = pf->main_vsi;
2136         int status;
2137
2138         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2139                                                      false, NULL, true);
2140         if (status != I40E_SUCCESS)
2141                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2142
2143         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2144                                                         false, NULL);
2145         if (status != I40E_SUCCESS)
2146                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2147 }
2148
2149 static void
2150 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2151 {
2152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2153         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154         struct i40e_vsi *vsi = pf->main_vsi;
2155         int ret;
2156
2157         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2158         if (ret != I40E_SUCCESS)
2159                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2160 }
2161
2162 static void
2163 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2164 {
2165         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2166         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167         struct i40e_vsi *vsi = pf->main_vsi;
2168         int ret;
2169
2170         if (dev->data->promiscuous == 1)
2171                 return; /* must remain in all_multicast mode */
2172
2173         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2174                                 vsi->seid, FALSE, NULL);
2175         if (ret != I40E_SUCCESS)
2176                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2177 }
2178
2179 /*
2180  * Set device link up.
2181  */
2182 static int
2183 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2184 {
2185         /* re-apply link speed setting */
2186         return i40e_apply_link_speed(dev);
2187 }
2188
2189 /*
2190  * Set device link down.
2191  */
2192 static int
2193 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2194 {
2195         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2196         uint8_t abilities = 0;
2197         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198
2199         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2200         return i40e_phy_conf_link(hw, abilities, speed);
2201 }
2202
2203 int
2204 i40e_dev_link_update(struct rte_eth_dev *dev,
2205                      int wait_to_complete)
2206 {
2207 #define CHECK_INTERVAL 100  /* 100ms */
2208 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2209         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2210         struct i40e_link_status link_status;
2211         struct rte_eth_link link, old;
2212         int status;
2213         unsigned rep_cnt = MAX_REPEAT_TIME;
2214         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2215
2216         memset(&link, 0, sizeof(link));
2217         memset(&old, 0, sizeof(old));
2218         memset(&link_status, 0, sizeof(link_status));
2219         rte_i40e_dev_atomic_read_link_status(dev, &old);
2220
2221         do {
2222                 /* Get link status information from hardware */
2223                 status = i40e_aq_get_link_info(hw, enable_lse,
2224                                                 &link_status, NULL);
2225                 if (status != I40E_SUCCESS) {
2226                         link.link_speed = ETH_SPEED_NUM_100M;
2227                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2228                         PMD_DRV_LOG(ERR, "Failed to get link info");
2229                         goto out;
2230                 }
2231
2232                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2233                 if (!wait_to_complete || link.link_status)
2234                         break;
2235
2236                 rte_delay_ms(CHECK_INTERVAL);
2237         } while (--rep_cnt);
2238
2239         if (!link.link_status)
2240                 goto out;
2241
2242         /* i40e uses full duplex only */
2243         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2244
2245         /* Parse the link status */
2246         switch (link_status.link_speed) {
2247         case I40E_LINK_SPEED_100MB:
2248                 link.link_speed = ETH_SPEED_NUM_100M;
2249                 break;
2250         case I40E_LINK_SPEED_1GB:
2251                 link.link_speed = ETH_SPEED_NUM_1G;
2252                 break;
2253         case I40E_LINK_SPEED_10GB:
2254                 link.link_speed = ETH_SPEED_NUM_10G;
2255                 break;
2256         case I40E_LINK_SPEED_20GB:
2257                 link.link_speed = ETH_SPEED_NUM_20G;
2258                 break;
2259         case I40E_LINK_SPEED_25GB:
2260                 link.link_speed = ETH_SPEED_NUM_25G;
2261                 break;
2262         case I40E_LINK_SPEED_40GB:
2263                 link.link_speed = ETH_SPEED_NUM_40G;
2264                 break;
2265         default:
2266                 link.link_speed = ETH_SPEED_NUM_100M;
2267                 break;
2268         }
2269
2270         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2271                         ETH_LINK_SPEED_FIXED);
2272
2273 out:
2274         rte_i40e_dev_atomic_write_link_status(dev, &link);
2275         if (link.link_status == old.link_status)
2276                 return -1;
2277
2278         return 0;
2279 }
2280
2281 /* Get all the statistics of a VSI */
2282 void
2283 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2284 {
2285         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2286         struct i40e_eth_stats *nes = &vsi->eth_stats;
2287         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2288         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2289
2290         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2291                             vsi->offset_loaded, &oes->rx_bytes,
2292                             &nes->rx_bytes);
2293         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2294                             vsi->offset_loaded, &oes->rx_unicast,
2295                             &nes->rx_unicast);
2296         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2297                             vsi->offset_loaded, &oes->rx_multicast,
2298                             &nes->rx_multicast);
2299         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2300                             vsi->offset_loaded, &oes->rx_broadcast,
2301                             &nes->rx_broadcast);
2302         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2303                             &oes->rx_discards, &nes->rx_discards);
2304         /* GLV_REPC not supported */
2305         /* GLV_RMPC not supported */
2306         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2307                             &oes->rx_unknown_protocol,
2308                             &nes->rx_unknown_protocol);
2309         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2310                             vsi->offset_loaded, &oes->tx_bytes,
2311                             &nes->tx_bytes);
2312         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2313                             vsi->offset_loaded, &oes->tx_unicast,
2314                             &nes->tx_unicast);
2315         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2316                             vsi->offset_loaded, &oes->tx_multicast,
2317                             &nes->tx_multicast);
2318         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2319                             vsi->offset_loaded,  &oes->tx_broadcast,
2320                             &nes->tx_broadcast);
2321         /* GLV_TDPC not supported */
2322         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2323                             &oes->tx_errors, &nes->tx_errors);
2324         vsi->offset_loaded = true;
2325
2326         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2327                     vsi->vsi_id);
2328         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2329         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2330         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2331         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2332         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2333         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2334                     nes->rx_unknown_protocol);
2335         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2336         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2337         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2338         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2339         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2340         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2341         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2342                     vsi->vsi_id);
2343 }
2344
2345 static void
2346 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2347 {
2348         unsigned int i;
2349         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2350         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2351
2352         /* Get statistics of struct i40e_eth_stats */
2353         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2354                             I40E_GLPRT_GORCL(hw->port),
2355                             pf->offset_loaded, &os->eth.rx_bytes,
2356                             &ns->eth.rx_bytes);
2357         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2358                             I40E_GLPRT_UPRCL(hw->port),
2359                             pf->offset_loaded, &os->eth.rx_unicast,
2360                             &ns->eth.rx_unicast);
2361         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2362                             I40E_GLPRT_MPRCL(hw->port),
2363                             pf->offset_loaded, &os->eth.rx_multicast,
2364                             &ns->eth.rx_multicast);
2365         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2366                             I40E_GLPRT_BPRCL(hw->port),
2367                             pf->offset_loaded, &os->eth.rx_broadcast,
2368                             &ns->eth.rx_broadcast);
2369         /* Workaround: CRC size should not be included in byte statistics,
2370          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2371          */
2372         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2373                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2374
2375         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2376                             pf->offset_loaded, &os->eth.rx_discards,
2377                             &ns->eth.rx_discards);
2378         /* GLPRT_REPC not supported */
2379         /* GLPRT_RMPC not supported */
2380         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2381                             pf->offset_loaded,
2382                             &os->eth.rx_unknown_protocol,
2383                             &ns->eth.rx_unknown_protocol);
2384         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2385                             I40E_GLPRT_GOTCL(hw->port),
2386                             pf->offset_loaded, &os->eth.tx_bytes,
2387                             &ns->eth.tx_bytes);
2388         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2389                             I40E_GLPRT_UPTCL(hw->port),
2390                             pf->offset_loaded, &os->eth.tx_unicast,
2391                             &ns->eth.tx_unicast);
2392         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2393                             I40E_GLPRT_MPTCL(hw->port),
2394                             pf->offset_loaded, &os->eth.tx_multicast,
2395                             &ns->eth.tx_multicast);
2396         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2397                             I40E_GLPRT_BPTCL(hw->port),
2398                             pf->offset_loaded, &os->eth.tx_broadcast,
2399                             &ns->eth.tx_broadcast);
2400         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2401                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2402         /* GLPRT_TEPC not supported */
2403
2404         /* additional port specific stats */
2405         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2406                             pf->offset_loaded, &os->tx_dropped_link_down,
2407                             &ns->tx_dropped_link_down);
2408         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2409                             pf->offset_loaded, &os->crc_errors,
2410                             &ns->crc_errors);
2411         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2412                             pf->offset_loaded, &os->illegal_bytes,
2413                             &ns->illegal_bytes);
2414         /* GLPRT_ERRBC not supported */
2415         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2416                             pf->offset_loaded, &os->mac_local_faults,
2417                             &ns->mac_local_faults);
2418         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2419                             pf->offset_loaded, &os->mac_remote_faults,
2420                             &ns->mac_remote_faults);
2421         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2422                             pf->offset_loaded, &os->rx_length_errors,
2423                             &ns->rx_length_errors);
2424         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2425                             pf->offset_loaded, &os->link_xon_rx,
2426                             &ns->link_xon_rx);
2427         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2428                             pf->offset_loaded, &os->link_xoff_rx,
2429                             &ns->link_xoff_rx);
2430         for (i = 0; i < 8; i++) {
2431                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2432                                     pf->offset_loaded,
2433                                     &os->priority_xon_rx[i],
2434                                     &ns->priority_xon_rx[i]);
2435                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2436                                     pf->offset_loaded,
2437                                     &os->priority_xoff_rx[i],
2438                                     &ns->priority_xoff_rx[i]);
2439         }
2440         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2441                             pf->offset_loaded, &os->link_xon_tx,
2442                             &ns->link_xon_tx);
2443         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2444                             pf->offset_loaded, &os->link_xoff_tx,
2445                             &ns->link_xoff_tx);
2446         for (i = 0; i < 8; i++) {
2447                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2448                                     pf->offset_loaded,
2449                                     &os->priority_xon_tx[i],
2450                                     &ns->priority_xon_tx[i]);
2451                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2452                                     pf->offset_loaded,
2453                                     &os->priority_xoff_tx[i],
2454                                     &ns->priority_xoff_tx[i]);
2455                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2456                                     pf->offset_loaded,
2457                                     &os->priority_xon_2_xoff[i],
2458                                     &ns->priority_xon_2_xoff[i]);
2459         }
2460         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2461                             I40E_GLPRT_PRC64L(hw->port),
2462                             pf->offset_loaded, &os->rx_size_64,
2463                             &ns->rx_size_64);
2464         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2465                             I40E_GLPRT_PRC127L(hw->port),
2466                             pf->offset_loaded, &os->rx_size_127,
2467                             &ns->rx_size_127);
2468         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2469                             I40E_GLPRT_PRC255L(hw->port),
2470                             pf->offset_loaded, &os->rx_size_255,
2471                             &ns->rx_size_255);
2472         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2473                             I40E_GLPRT_PRC511L(hw->port),
2474                             pf->offset_loaded, &os->rx_size_511,
2475                             &ns->rx_size_511);
2476         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2477                             I40E_GLPRT_PRC1023L(hw->port),
2478                             pf->offset_loaded, &os->rx_size_1023,
2479                             &ns->rx_size_1023);
2480         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2481                             I40E_GLPRT_PRC1522L(hw->port),
2482                             pf->offset_loaded, &os->rx_size_1522,
2483                             &ns->rx_size_1522);
2484         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2485                             I40E_GLPRT_PRC9522L(hw->port),
2486                             pf->offset_loaded, &os->rx_size_big,
2487                             &ns->rx_size_big);
2488         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2489                             pf->offset_loaded, &os->rx_undersize,
2490                             &ns->rx_undersize);
2491         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2492                             pf->offset_loaded, &os->rx_fragments,
2493                             &ns->rx_fragments);
2494         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2495                             pf->offset_loaded, &os->rx_oversize,
2496                             &ns->rx_oversize);
2497         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2498                             pf->offset_loaded, &os->rx_jabber,
2499                             &ns->rx_jabber);
2500         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2501                             I40E_GLPRT_PTC64L(hw->port),
2502                             pf->offset_loaded, &os->tx_size_64,
2503                             &ns->tx_size_64);
2504         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2505                             I40E_GLPRT_PTC127L(hw->port),
2506                             pf->offset_loaded, &os->tx_size_127,
2507                             &ns->tx_size_127);
2508         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2509                             I40E_GLPRT_PTC255L(hw->port),
2510                             pf->offset_loaded, &os->tx_size_255,
2511                             &ns->tx_size_255);
2512         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2513                             I40E_GLPRT_PTC511L(hw->port),
2514                             pf->offset_loaded, &os->tx_size_511,
2515                             &ns->tx_size_511);
2516         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2517                             I40E_GLPRT_PTC1023L(hw->port),
2518                             pf->offset_loaded, &os->tx_size_1023,
2519                             &ns->tx_size_1023);
2520         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2521                             I40E_GLPRT_PTC1522L(hw->port),
2522                             pf->offset_loaded, &os->tx_size_1522,
2523                             &ns->tx_size_1522);
2524         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2525                             I40E_GLPRT_PTC9522L(hw->port),
2526                             pf->offset_loaded, &os->tx_size_big,
2527                             &ns->tx_size_big);
2528         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2529                            pf->offset_loaded,
2530                            &os->fd_sb_match, &ns->fd_sb_match);
2531         /* GLPRT_MSPDC not supported */
2532         /* GLPRT_XEC not supported */
2533
2534         pf->offset_loaded = true;
2535
2536         if (pf->main_vsi)
2537                 i40e_update_vsi_stats(pf->main_vsi);
2538 }
2539
2540 /* Get all statistics of a port */
2541 static void
2542 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2543 {
2544         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2545         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2546         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2547         unsigned i;
2548
2549         /* call read registers - updates values, now write them to struct */
2550         i40e_read_stats_registers(pf, hw);
2551
2552         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2553                         pf->main_vsi->eth_stats.rx_multicast +
2554                         pf->main_vsi->eth_stats.rx_broadcast -
2555                         pf->main_vsi->eth_stats.rx_discards;
2556         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2557                         pf->main_vsi->eth_stats.tx_multicast +
2558                         pf->main_vsi->eth_stats.tx_broadcast;
2559         stats->ibytes   = ns->eth.rx_bytes;
2560         stats->obytes   = ns->eth.tx_bytes;
2561         stats->oerrors  = ns->eth.tx_errors +
2562                         pf->main_vsi->eth_stats.tx_errors;
2563
2564         /* Rx Errors */
2565         stats->imissed  = ns->eth.rx_discards +
2566                         pf->main_vsi->eth_stats.rx_discards;
2567         stats->ierrors  = ns->crc_errors +
2568                         ns->rx_length_errors + ns->rx_undersize +
2569                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2570
2571         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2572         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2573         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2574         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2575         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2576         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2577         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2578                     ns->eth.rx_unknown_protocol);
2579         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2580         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2581         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2582         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2583         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2584         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2585
2586         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2587                     ns->tx_dropped_link_down);
2588         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2589         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2590                     ns->illegal_bytes);
2591         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2592         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2593                     ns->mac_local_faults);
2594         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2595                     ns->mac_remote_faults);
2596         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2597                     ns->rx_length_errors);
2598         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2599         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2600         for (i = 0; i < 8; i++) {
2601                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2602                                 i, ns->priority_xon_rx[i]);
2603                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2604                                 i, ns->priority_xoff_rx[i]);
2605         }
2606         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2607         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2608         for (i = 0; i < 8; i++) {
2609                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2610                                 i, ns->priority_xon_tx[i]);
2611                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2612                                 i, ns->priority_xoff_tx[i]);
2613                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2614                                 i, ns->priority_xon_2_xoff[i]);
2615         }
2616         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2617         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2618         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2619         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2620         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2621         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2622         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2623         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2624         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2625         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2626         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2627         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2628         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2629         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2630         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2631         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2632         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2633         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2634         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2635                         ns->mac_short_packet_dropped);
2636         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2637                     ns->checksum_error);
2638         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2639         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2640 }
2641
2642 /* Reset the statistics */
2643 static void
2644 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2645 {
2646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2648
2649         /* Mark PF and VSI stats to update the offset, aka "reset" */
2650         pf->offset_loaded = false;
2651         if (pf->main_vsi)
2652                 pf->main_vsi->offset_loaded = false;
2653
2654         /* read the stats, reading current register values into offset */
2655         i40e_read_stats_registers(pf, hw);
2656 }
2657
2658 static uint32_t
2659 i40e_xstats_calc_num(void)
2660 {
2661         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2662                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2663                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2664 }
2665
2666 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2667                                      struct rte_eth_xstat_name *xstats_names,
2668                                      __rte_unused unsigned limit)
2669 {
2670         unsigned count = 0;
2671         unsigned i, prio;
2672
2673         if (xstats_names == NULL)
2674                 return i40e_xstats_calc_num();
2675
2676         /* Note: limit checked in rte_eth_xstats_names() */
2677
2678         /* Get stats from i40e_eth_stats struct */
2679         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2680                 snprintf(xstats_names[count].name,
2681                          sizeof(xstats_names[count].name),
2682                          "%s", rte_i40e_stats_strings[i].name);
2683                 count++;
2684         }
2685
2686         /* Get individiual stats from i40e_hw_port struct */
2687         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2688                 snprintf(xstats_names[count].name,
2689                         sizeof(xstats_names[count].name),
2690                          "%s", rte_i40e_hw_port_strings[i].name);
2691                 count++;
2692         }
2693
2694         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2695                 for (prio = 0; prio < 8; prio++) {
2696                         snprintf(xstats_names[count].name,
2697                                  sizeof(xstats_names[count].name),
2698                                  "rx_priority%u_%s", prio,
2699                                  rte_i40e_rxq_prio_strings[i].name);
2700                         count++;
2701                 }
2702         }
2703
2704         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2705                 for (prio = 0; prio < 8; prio++) {
2706                         snprintf(xstats_names[count].name,
2707                                  sizeof(xstats_names[count].name),
2708                                  "tx_priority%u_%s", prio,
2709                                  rte_i40e_txq_prio_strings[i].name);
2710                         count++;
2711                 }
2712         }
2713         return count;
2714 }
2715
2716 static int
2717 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2718                     unsigned n)
2719 {
2720         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2721         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2722         unsigned i, count, prio;
2723         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2724
2725         count = i40e_xstats_calc_num();
2726         if (n < count)
2727                 return count;
2728
2729         i40e_read_stats_registers(pf, hw);
2730
2731         if (xstats == NULL)
2732                 return 0;
2733
2734         count = 0;
2735
2736         /* Get stats from i40e_eth_stats struct */
2737         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2738                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2739                         rte_i40e_stats_strings[i].offset);
2740                 xstats[count].id = count;
2741                 count++;
2742         }
2743
2744         /* Get individiual stats from i40e_hw_port struct */
2745         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2746                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2747                         rte_i40e_hw_port_strings[i].offset);
2748                 xstats[count].id = count;
2749                 count++;
2750         }
2751
2752         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2753                 for (prio = 0; prio < 8; prio++) {
2754                         xstats[count].value =
2755                                 *(uint64_t *)(((char *)hw_stats) +
2756                                 rte_i40e_rxq_prio_strings[i].offset +
2757                                 (sizeof(uint64_t) * prio));
2758                         xstats[count].id = count;
2759                         count++;
2760                 }
2761         }
2762
2763         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2764                 for (prio = 0; prio < 8; prio++) {
2765                         xstats[count].value =
2766                                 *(uint64_t *)(((char *)hw_stats) +
2767                                 rte_i40e_txq_prio_strings[i].offset +
2768                                 (sizeof(uint64_t) * prio));
2769                         xstats[count].id = count;
2770                         count++;
2771                 }
2772         }
2773
2774         return count;
2775 }
2776
2777 static int
2778 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2779                                  __rte_unused uint16_t queue_id,
2780                                  __rte_unused uint8_t stat_idx,
2781                                  __rte_unused uint8_t is_rx)
2782 {
2783         PMD_INIT_FUNC_TRACE();
2784
2785         return -ENOSYS;
2786 }
2787
2788 static int
2789 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2790 {
2791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792         u32 full_ver;
2793         u8 ver, patch;
2794         u16 build;
2795         int ret;
2796
2797         full_ver = hw->nvm.oem_ver;
2798         ver = (u8)(full_ver >> 24);
2799         build = (u16)((full_ver >> 8) & 0xffff);
2800         patch = (u8)(full_ver & 0xff);
2801
2802         ret = snprintf(fw_version, fw_size,
2803                  "%d.%d%d 0x%08x %d.%d.%d",
2804                  ((hw->nvm.version >> 12) & 0xf),
2805                  ((hw->nvm.version >> 4) & 0xff),
2806                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2807                  ver, build, patch);
2808
2809         ret += 1; /* add the size of '\0' */
2810         if (fw_size < (u32)ret)
2811                 return ret;
2812         else
2813                 return 0;
2814 }
2815
2816 static void
2817 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2818 {
2819         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2820         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2821         struct i40e_vsi *vsi = pf->main_vsi;
2822         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2823
2824         dev_info->pci_dev = pci_dev;
2825         dev_info->max_rx_queues = vsi->nb_qps;
2826         dev_info->max_tx_queues = vsi->nb_qps;
2827         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2828         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2829         dev_info->max_mac_addrs = vsi->max_macaddrs;
2830         dev_info->max_vfs = pci_dev->max_vfs;
2831         dev_info->rx_offload_capa =
2832                 DEV_RX_OFFLOAD_VLAN_STRIP |
2833                 DEV_RX_OFFLOAD_QINQ_STRIP |
2834                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2835                 DEV_RX_OFFLOAD_UDP_CKSUM |
2836                 DEV_RX_OFFLOAD_TCP_CKSUM;
2837         dev_info->tx_offload_capa =
2838                 DEV_TX_OFFLOAD_VLAN_INSERT |
2839                 DEV_TX_OFFLOAD_QINQ_INSERT |
2840                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2841                 DEV_TX_OFFLOAD_UDP_CKSUM |
2842                 DEV_TX_OFFLOAD_TCP_CKSUM |
2843                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2844                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2845                 DEV_TX_OFFLOAD_TCP_TSO |
2846                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2847                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2848                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2849                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2850         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2851                                                 sizeof(uint32_t);
2852         dev_info->reta_size = pf->hash_lut_size;
2853         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2854
2855         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2856                 .rx_thresh = {
2857                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2858                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2859                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2860                 },
2861                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2862                 .rx_drop_en = 0,
2863         };
2864
2865         dev_info->default_txconf = (struct rte_eth_txconf) {
2866                 .tx_thresh = {
2867                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2868                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2869                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2870                 },
2871                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2872                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2873                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2874                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2875         };
2876
2877         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2878                 .nb_max = I40E_MAX_RING_DESC,
2879                 .nb_min = I40E_MIN_RING_DESC,
2880                 .nb_align = I40E_ALIGN_RING_DESC,
2881         };
2882
2883         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2884                 .nb_max = I40E_MAX_RING_DESC,
2885                 .nb_min = I40E_MIN_RING_DESC,
2886                 .nb_align = I40E_ALIGN_RING_DESC,
2887                 .nb_seg_max = I40E_TX_MAX_SEG,
2888                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2889         };
2890
2891         if (pf->flags & I40E_FLAG_VMDQ) {
2892                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2893                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2894                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2895                                                 pf->max_nb_vmdq_vsi;
2896                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2897                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2898                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2899         }
2900
2901         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2902                 /* For XL710 */
2903                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2904         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2905                 /* For XXV710 */
2906                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2907         else
2908                 /* For X710 */
2909                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2910 }
2911
2912 static int
2913 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2914 {
2915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2916         struct i40e_vsi *vsi = pf->main_vsi;
2917         PMD_INIT_FUNC_TRACE();
2918
2919         if (on)
2920                 return i40e_vsi_add_vlan(vsi, vlan_id);
2921         else
2922                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2923 }
2924
2925 static int
2926 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2927                    enum rte_vlan_type vlan_type,
2928                    uint16_t tpid)
2929 {
2930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931         uint64_t reg_r = 0, reg_w = 0;
2932         uint16_t reg_id = 0;
2933         int ret = 0;
2934         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2935
2936         switch (vlan_type) {
2937         case ETH_VLAN_TYPE_OUTER:
2938                 if (qinq)
2939                         reg_id = 2;
2940                 else
2941                         reg_id = 3;
2942                 break;
2943         case ETH_VLAN_TYPE_INNER:
2944                 if (qinq)
2945                         reg_id = 3;
2946                 else {
2947                         ret = -EINVAL;
2948                         PMD_DRV_LOG(ERR,
2949                                 "Unsupported vlan type in single vlan.");
2950                         return ret;
2951                 }
2952                 break;
2953         default:
2954                 ret = -EINVAL;
2955                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2956                 return ret;
2957         }
2958         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2959                                           &reg_r, NULL);
2960         if (ret != I40E_SUCCESS) {
2961                 PMD_DRV_LOG(ERR,
2962                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2963                            reg_id);
2964                 ret = -EIO;
2965                 return ret;
2966         }
2967         PMD_DRV_LOG(DEBUG,
2968                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2969                 reg_id, reg_r);
2970
2971         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2972         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2973         if (reg_r == reg_w) {
2974                 ret = 0;
2975                 PMD_DRV_LOG(DEBUG, "No need to write");
2976                 return ret;
2977         }
2978
2979         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2980                                            reg_w, NULL);
2981         if (ret != I40E_SUCCESS) {
2982                 ret = -EIO;
2983                 PMD_DRV_LOG(ERR,
2984                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2985                         reg_id);
2986                 return ret;
2987         }
2988         PMD_DRV_LOG(DEBUG,
2989                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2990                 reg_w, reg_id);
2991
2992         return ret;
2993 }
2994
2995 static void
2996 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2997 {
2998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2999         struct i40e_vsi *vsi = pf->main_vsi;
3000
3001         if (mask & ETH_VLAN_FILTER_MASK) {
3002                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3003                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3004                 else
3005                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3006         }
3007
3008         if (mask & ETH_VLAN_STRIP_MASK) {
3009                 /* Enable or disable VLAN stripping */
3010                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3011                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3012                 else
3013                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3014         }
3015
3016         if (mask & ETH_VLAN_EXTEND_MASK) {
3017                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3018                         i40e_vsi_config_double_vlan(vsi, TRUE);
3019                         /* Set global registers with default ether type value */
3020                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3021                                            ETHER_TYPE_VLAN);
3022                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3023                                            ETHER_TYPE_VLAN);
3024                 }
3025                 else
3026                         i40e_vsi_config_double_vlan(vsi, FALSE);
3027         }
3028 }
3029
3030 static void
3031 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3032                           __rte_unused uint16_t queue,
3033                           __rte_unused int on)
3034 {
3035         PMD_INIT_FUNC_TRACE();
3036 }
3037
3038 static int
3039 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3040 {
3041         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3042         struct i40e_vsi *vsi = pf->main_vsi;
3043         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3044         struct i40e_vsi_vlan_pvid_info info;
3045
3046         memset(&info, 0, sizeof(info));
3047         info.on = on;
3048         if (info.on)
3049                 info.config.pvid = pvid;
3050         else {
3051                 info.config.reject.tagged =
3052                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3053                 info.config.reject.untagged =
3054                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3055         }
3056
3057         return i40e_vsi_vlan_pvid_set(vsi, &info);
3058 }
3059
3060 static int
3061 i40e_dev_led_on(struct rte_eth_dev *dev)
3062 {
3063         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3064         uint32_t mode = i40e_led_get(hw);
3065
3066         if (mode == 0)
3067                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3068
3069         return 0;
3070 }
3071
3072 static int
3073 i40e_dev_led_off(struct rte_eth_dev *dev)
3074 {
3075         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076         uint32_t mode = i40e_led_get(hw);
3077
3078         if (mode != 0)
3079                 i40e_led_set(hw, 0, false);
3080
3081         return 0;
3082 }
3083
3084 static int
3085 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3086 {
3087         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3088         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3089
3090         fc_conf->pause_time = pf->fc_conf.pause_time;
3091         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3092         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3093
3094          /* Return current mode according to actual setting*/
3095         switch (hw->fc.current_mode) {
3096         case I40E_FC_FULL:
3097                 fc_conf->mode = RTE_FC_FULL;
3098                 break;
3099         case I40E_FC_TX_PAUSE:
3100                 fc_conf->mode = RTE_FC_TX_PAUSE;
3101                 break;
3102         case I40E_FC_RX_PAUSE:
3103                 fc_conf->mode = RTE_FC_RX_PAUSE;
3104                 break;
3105         case I40E_FC_NONE:
3106         default:
3107                 fc_conf->mode = RTE_FC_NONE;
3108         };
3109
3110         return 0;
3111 }
3112
3113 static int
3114 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3115 {
3116         uint32_t mflcn_reg, fctrl_reg, reg;
3117         uint32_t max_high_water;
3118         uint8_t i, aq_failure;
3119         int err;
3120         struct i40e_hw *hw;
3121         struct i40e_pf *pf;
3122         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3123                 [RTE_FC_NONE] = I40E_FC_NONE,
3124                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3125                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3126                 [RTE_FC_FULL] = I40E_FC_FULL
3127         };
3128
3129         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3130
3131         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3132         if ((fc_conf->high_water > max_high_water) ||
3133                         (fc_conf->high_water < fc_conf->low_water)) {
3134                 PMD_INIT_LOG(ERR,
3135                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3136                         max_high_water);
3137                 return -EINVAL;
3138         }
3139
3140         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3141         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3142         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3143
3144         pf->fc_conf.pause_time = fc_conf->pause_time;
3145         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3146         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3147
3148         PMD_INIT_FUNC_TRACE();
3149
3150         /* All the link flow control related enable/disable register
3151          * configuration is handle by the F/W
3152          */
3153         err = i40e_set_fc(hw, &aq_failure, true);
3154         if (err < 0)
3155                 return -ENOSYS;
3156
3157         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3158                 /* Configure flow control refresh threshold,
3159                  * the value for stat_tx_pause_refresh_timer[8]
3160                  * is used for global pause operation.
3161                  */
3162
3163                 I40E_WRITE_REG(hw,
3164                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3165                                pf->fc_conf.pause_time);
3166
3167                 /* configure the timer value included in transmitted pause
3168                  * frame,
3169                  * the value for stat_tx_pause_quanta[8] is used for global
3170                  * pause operation
3171                  */
3172                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3173                                pf->fc_conf.pause_time);
3174
3175                 fctrl_reg = I40E_READ_REG(hw,
3176                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3177
3178                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3179                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3180                 else
3181                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3182
3183                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3184                                fctrl_reg);
3185         } else {
3186                 /* Configure pause time (2 TCs per register) */
3187                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3188                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3189                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3190
3191                 /* Configure flow control refresh threshold value */
3192                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3193                                pf->fc_conf.pause_time / 2);
3194
3195                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3196
3197                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3198                  *depending on configuration
3199                  */
3200                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3201                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3202                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3203                 } else {
3204                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3205                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3206                 }
3207
3208                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3209         }
3210
3211         /* config the water marker both based on the packets and bytes */
3212         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3213                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3214                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3215         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3216                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3217                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3218         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3219                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3220                        << I40E_KILOSHIFT);
3221         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3222                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3223                        << I40E_KILOSHIFT);
3224
3225         I40E_WRITE_FLUSH(hw);
3226
3227         return 0;
3228 }
3229
3230 static int
3231 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3232                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3233 {
3234         PMD_INIT_FUNC_TRACE();
3235
3236         return -ENOSYS;
3237 }
3238
3239 /* Add a MAC address, and update filters */
3240 static void
3241 i40e_macaddr_add(struct rte_eth_dev *dev,
3242                  struct ether_addr *mac_addr,
3243                  __rte_unused uint32_t index,
3244                  uint32_t pool)
3245 {
3246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3247         struct i40e_mac_filter_info mac_filter;
3248         struct i40e_vsi *vsi;
3249         int ret;
3250
3251         /* If VMDQ not enabled or configured, return */
3252         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3253                           !pf->nb_cfg_vmdq_vsi)) {
3254                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3255                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3256                         pool);
3257                 return;
3258         }
3259
3260         if (pool > pf->nb_cfg_vmdq_vsi) {
3261                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3262                                 pool, pf->nb_cfg_vmdq_vsi);
3263                 return;
3264         }
3265
3266         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3267         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3268                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3269         else
3270                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3271
3272         if (pool == 0)
3273                 vsi = pf->main_vsi;
3274         else
3275                 vsi = pf->vmdq[pool - 1].vsi;
3276
3277         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3278         if (ret != I40E_SUCCESS) {
3279                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3280                 return;
3281         }
3282 }
3283
3284 /* Remove a MAC address, and update filters */
3285 static void
3286 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3287 {
3288         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3289         struct i40e_vsi *vsi;
3290         struct rte_eth_dev_data *data = dev->data;
3291         struct ether_addr *macaddr;
3292         int ret;
3293         uint32_t i;
3294         uint64_t pool_sel;
3295
3296         macaddr = &(data->mac_addrs[index]);
3297
3298         pool_sel = dev->data->mac_pool_sel[index];
3299
3300         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3301                 if (pool_sel & (1ULL << i)) {
3302                         if (i == 0)
3303                                 vsi = pf->main_vsi;
3304                         else {
3305                                 /* No VMDQ pool enabled or configured */
3306                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3307                                         (i > pf->nb_cfg_vmdq_vsi)) {
3308                                         PMD_DRV_LOG(ERR,
3309                                                 "No VMDQ pool enabled/configured");
3310                                         return;
3311                                 }
3312                                 vsi = pf->vmdq[i - 1].vsi;
3313                         }
3314                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3315
3316                         if (ret) {
3317                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3318                                 return;
3319                         }
3320                 }
3321         }
3322 }
3323
3324 /* Set perfect match or hash match of MAC and VLAN for a VF */
3325 static int
3326 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3327                  struct rte_eth_mac_filter *filter,
3328                  bool add)
3329 {
3330         struct i40e_hw *hw;
3331         struct i40e_mac_filter_info mac_filter;
3332         struct ether_addr old_mac;
3333         struct ether_addr *new_mac;
3334         struct i40e_pf_vf *vf = NULL;
3335         uint16_t vf_id;
3336         int ret;
3337
3338         if (pf == NULL) {
3339                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3340                 return -EINVAL;
3341         }
3342         hw = I40E_PF_TO_HW(pf);
3343
3344         if (filter == NULL) {
3345                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3346                 return -EINVAL;
3347         }
3348
3349         new_mac = &filter->mac_addr;
3350
3351         if (is_zero_ether_addr(new_mac)) {
3352                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3353                 return -EINVAL;
3354         }
3355
3356         vf_id = filter->dst_id;
3357
3358         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3359                 PMD_DRV_LOG(ERR, "Invalid argument.");
3360                 return -EINVAL;
3361         }
3362         vf = &pf->vfs[vf_id];
3363
3364         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3365                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3366                 return -EINVAL;
3367         }
3368
3369         if (add) {
3370                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3371                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3372                                 ETHER_ADDR_LEN);
3373                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3374                                  ETHER_ADDR_LEN);
3375
3376                 mac_filter.filter_type = filter->filter_type;
3377                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3378                 if (ret != I40E_SUCCESS) {
3379                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3380                         return -1;
3381                 }
3382                 ether_addr_copy(new_mac, &pf->dev_addr);
3383         } else {
3384                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3385                                 ETHER_ADDR_LEN);
3386                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3387                 if (ret != I40E_SUCCESS) {
3388                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3389                         return -1;
3390                 }
3391
3392                 /* Clear device address as it has been removed */
3393                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3394                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3395         }
3396
3397         return 0;
3398 }
3399
3400 /* MAC filter handle */
3401 static int
3402 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3403                 void *arg)
3404 {
3405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3406         struct rte_eth_mac_filter *filter;
3407         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3408         int ret = I40E_NOT_SUPPORTED;
3409
3410         filter = (struct rte_eth_mac_filter *)(arg);
3411
3412         switch (filter_op) {
3413         case RTE_ETH_FILTER_NOP:
3414                 ret = I40E_SUCCESS;
3415                 break;
3416         case RTE_ETH_FILTER_ADD:
3417                 i40e_pf_disable_irq0(hw);
3418                 if (filter->is_vf)
3419                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3420                 i40e_pf_enable_irq0(hw);
3421                 break;
3422         case RTE_ETH_FILTER_DELETE:
3423                 i40e_pf_disable_irq0(hw);
3424                 if (filter->is_vf)
3425                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3426                 i40e_pf_enable_irq0(hw);
3427                 break;
3428         default:
3429                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3430                 ret = I40E_ERR_PARAM;
3431                 break;
3432         }
3433
3434         return ret;
3435 }
3436
3437 static int
3438 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3439 {
3440         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3441         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3442         int ret;
3443
3444         if (!lut)
3445                 return -EINVAL;
3446
3447         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3448                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3449                                           lut, lut_size);
3450                 if (ret) {
3451                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3452                         return ret;
3453                 }
3454         } else {
3455                 uint32_t *lut_dw = (uint32_t *)lut;
3456                 uint16_t i, lut_size_dw = lut_size / 4;
3457
3458                 for (i = 0; i < lut_size_dw; i++)
3459                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3460         }
3461
3462         return 0;
3463 }
3464
3465 static int
3466 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3467 {
3468         struct i40e_pf *pf;
3469         struct i40e_hw *hw;
3470         int ret;
3471
3472         if (!vsi || !lut)
3473                 return -EINVAL;
3474
3475         pf = I40E_VSI_TO_PF(vsi);
3476         hw = I40E_VSI_TO_HW(vsi);
3477
3478         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3479                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3480                                           lut, lut_size);
3481                 if (ret) {
3482                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3483                         return ret;
3484                 }
3485         } else {
3486                 uint32_t *lut_dw = (uint32_t *)lut;
3487                 uint16_t i, lut_size_dw = lut_size / 4;
3488
3489                 for (i = 0; i < lut_size_dw; i++)
3490                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3491                 I40E_WRITE_FLUSH(hw);
3492         }
3493
3494         return 0;
3495 }
3496
3497 static int
3498 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3499                          struct rte_eth_rss_reta_entry64 *reta_conf,
3500                          uint16_t reta_size)
3501 {
3502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3503         uint16_t i, lut_size = pf->hash_lut_size;
3504         uint16_t idx, shift;
3505         uint8_t *lut;
3506         int ret;
3507
3508         if (reta_size != lut_size ||
3509                 reta_size > ETH_RSS_RETA_SIZE_512) {
3510                 PMD_DRV_LOG(ERR,
3511                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3512                         reta_size, lut_size);
3513                 return -EINVAL;
3514         }
3515
3516         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3517         if (!lut) {
3518                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3519                 return -ENOMEM;
3520         }
3521         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3522         if (ret)
3523                 goto out;
3524         for (i = 0; i < reta_size; i++) {
3525                 idx = i / RTE_RETA_GROUP_SIZE;
3526                 shift = i % RTE_RETA_GROUP_SIZE;
3527                 if (reta_conf[idx].mask & (1ULL << shift))
3528                         lut[i] = reta_conf[idx].reta[shift];
3529         }
3530         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3531
3532 out:
3533         rte_free(lut);
3534
3535         return ret;
3536 }
3537
3538 static int
3539 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3540                         struct rte_eth_rss_reta_entry64 *reta_conf,
3541                         uint16_t reta_size)
3542 {
3543         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3544         uint16_t i, lut_size = pf->hash_lut_size;
3545         uint16_t idx, shift;
3546         uint8_t *lut;
3547         int ret;
3548
3549         if (reta_size != lut_size ||
3550                 reta_size > ETH_RSS_RETA_SIZE_512) {
3551                 PMD_DRV_LOG(ERR,
3552                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3553                         reta_size, lut_size);
3554                 return -EINVAL;
3555         }
3556
3557         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3558         if (!lut) {
3559                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3560                 return -ENOMEM;
3561         }
3562
3563         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3564         if (ret)
3565                 goto out;
3566         for (i = 0; i < reta_size; i++) {
3567                 idx = i / RTE_RETA_GROUP_SIZE;
3568                 shift = i % RTE_RETA_GROUP_SIZE;
3569                 if (reta_conf[idx].mask & (1ULL << shift))
3570                         reta_conf[idx].reta[shift] = lut[i];
3571         }
3572
3573 out:
3574         rte_free(lut);
3575
3576         return ret;
3577 }
3578
3579 /**
3580  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3581  * @hw:   pointer to the HW structure
3582  * @mem:  pointer to mem struct to fill out
3583  * @size: size of memory requested
3584  * @alignment: what to align the allocation to
3585  **/
3586 enum i40e_status_code
3587 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3588                         struct i40e_dma_mem *mem,
3589                         u64 size,
3590                         u32 alignment)
3591 {
3592         const struct rte_memzone *mz = NULL;
3593         char z_name[RTE_MEMZONE_NAMESIZE];
3594
3595         if (!mem)
3596                 return I40E_ERR_PARAM;
3597
3598         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3599         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3600                                          alignment, RTE_PGSIZE_2M);
3601         if (!mz)
3602                 return I40E_ERR_NO_MEMORY;
3603
3604         mem->size = size;
3605         mem->va = mz->addr;
3606         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3607         mem->zone = (const void *)mz;
3608         PMD_DRV_LOG(DEBUG,
3609                 "memzone %s allocated with physical address: %"PRIu64,
3610                 mz->name, mem->pa);
3611
3612         return I40E_SUCCESS;
3613 }
3614
3615 /**
3616  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3617  * @hw:   pointer to the HW structure
3618  * @mem:  ptr to mem struct to free
3619  **/
3620 enum i40e_status_code
3621 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3622                     struct i40e_dma_mem *mem)
3623 {
3624         if (!mem)
3625                 return I40E_ERR_PARAM;
3626
3627         PMD_DRV_LOG(DEBUG,
3628                 "memzone %s to be freed with physical address: %"PRIu64,
3629                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3630         rte_memzone_free((const struct rte_memzone *)mem->zone);
3631         mem->zone = NULL;
3632         mem->va = NULL;
3633         mem->pa = (u64)0;
3634
3635         return I40E_SUCCESS;
3636 }
3637
3638 /**
3639  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3640  * @hw:   pointer to the HW structure
3641  * @mem:  pointer to mem struct to fill out
3642  * @size: size of memory requested
3643  **/
3644 enum i40e_status_code
3645 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3646                          struct i40e_virt_mem *mem,
3647                          u32 size)
3648 {
3649         if (!mem)
3650                 return I40E_ERR_PARAM;
3651
3652         mem->size = size;
3653         mem->va = rte_zmalloc("i40e", size, 0);
3654
3655         if (mem->va)
3656                 return I40E_SUCCESS;
3657         else
3658                 return I40E_ERR_NO_MEMORY;
3659 }
3660
3661 /**
3662  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3663  * @hw:   pointer to the HW structure
3664  * @mem:  pointer to mem struct to free
3665  **/
3666 enum i40e_status_code
3667 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3668                      struct i40e_virt_mem *mem)
3669 {
3670         if (!mem)
3671                 return I40E_ERR_PARAM;
3672
3673         rte_free(mem->va);
3674         mem->va = NULL;
3675
3676         return I40E_SUCCESS;
3677 }
3678
3679 void
3680 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3681 {
3682         rte_spinlock_init(&sp->spinlock);
3683 }
3684
3685 void
3686 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3687 {
3688         rte_spinlock_lock(&sp->spinlock);
3689 }
3690
3691 void
3692 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3693 {
3694         rte_spinlock_unlock(&sp->spinlock);
3695 }
3696
3697 void
3698 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3699 {
3700         return;
3701 }
3702
3703 /**
3704  * Get the hardware capabilities, which will be parsed
3705  * and saved into struct i40e_hw.
3706  */
3707 static int
3708 i40e_get_cap(struct i40e_hw *hw)
3709 {
3710         struct i40e_aqc_list_capabilities_element_resp *buf;
3711         uint16_t len, size = 0;
3712         int ret;
3713
3714         /* Calculate a huge enough buff for saving response data temporarily */
3715         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3716                                                 I40E_MAX_CAP_ELE_NUM;
3717         buf = rte_zmalloc("i40e", len, 0);
3718         if (!buf) {
3719                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3720                 return I40E_ERR_NO_MEMORY;
3721         }
3722
3723         /* Get, parse the capabilities and save it to hw */
3724         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3725                         i40e_aqc_opc_list_func_capabilities, NULL);
3726         if (ret != I40E_SUCCESS)
3727                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3728
3729         /* Free the temporary buffer after being used */
3730         rte_free(buf);
3731
3732         return ret;
3733 }
3734
3735 static int
3736 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3737 {
3738         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3739         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3740         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3741         uint16_t qp_count = 0, vsi_count = 0;
3742
3743         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3744                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3745                 return -EINVAL;
3746         }
3747         /* Add the parameter init for LFC */
3748         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3749         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3750         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3751
3752         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3753         pf->max_num_vsi = hw->func_caps.num_vsis;
3754         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3755         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3756         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3757
3758         /* FDir queue/VSI allocation */
3759         pf->fdir_qp_offset = 0;
3760         if (hw->func_caps.fd) {
3761                 pf->flags |= I40E_FLAG_FDIR;
3762                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3763         } else {
3764                 pf->fdir_nb_qps = 0;
3765         }
3766         qp_count += pf->fdir_nb_qps;
3767         vsi_count += 1;
3768
3769         /* LAN queue/VSI allocation */
3770         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3771         if (!hw->func_caps.rss) {
3772                 pf->lan_nb_qps = 1;
3773         } else {
3774                 pf->flags |= I40E_FLAG_RSS;
3775                 if (hw->mac.type == I40E_MAC_X722)
3776                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3777                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3778         }
3779         qp_count += pf->lan_nb_qps;
3780         vsi_count += 1;
3781
3782         /* VF queue/VSI allocation */
3783         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3784         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3785                 pf->flags |= I40E_FLAG_SRIOV;
3786                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3787                 pf->vf_num = pci_dev->max_vfs;
3788                 PMD_DRV_LOG(DEBUG,
3789                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3790                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3791         } else {
3792                 pf->vf_nb_qps = 0;
3793                 pf->vf_num = 0;
3794         }
3795         qp_count += pf->vf_nb_qps * pf->vf_num;
3796         vsi_count += pf->vf_num;
3797
3798         /* VMDq queue/VSI allocation */
3799         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3800         pf->vmdq_nb_qps = 0;
3801         pf->max_nb_vmdq_vsi = 0;
3802         if (hw->func_caps.vmdq) {
3803                 if (qp_count < hw->func_caps.num_tx_qp &&
3804                         vsi_count < hw->func_caps.num_vsis) {
3805                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3806                                 qp_count) / pf->vmdq_nb_qp_max;
3807
3808                         /* Limit the maximum number of VMDq vsi to the maximum
3809                          * ethdev can support
3810                          */
3811                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3812                                 hw->func_caps.num_vsis - vsi_count);
3813                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3814                                 ETH_64_POOLS);
3815                         if (pf->max_nb_vmdq_vsi) {
3816                                 pf->flags |= I40E_FLAG_VMDQ;
3817                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3818                                 PMD_DRV_LOG(DEBUG,
3819                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3820                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3821                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3822                         } else {
3823                                 PMD_DRV_LOG(INFO,
3824                                         "No enough queues left for VMDq");
3825                         }
3826                 } else {
3827                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3828                 }
3829         }
3830         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3831         vsi_count += pf->max_nb_vmdq_vsi;
3832
3833         if (hw->func_caps.dcb)
3834                 pf->flags |= I40E_FLAG_DCB;
3835
3836         if (qp_count > hw->func_caps.num_tx_qp) {
3837                 PMD_DRV_LOG(ERR,
3838                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3839                         qp_count, hw->func_caps.num_tx_qp);
3840                 return -EINVAL;
3841         }
3842         if (vsi_count > hw->func_caps.num_vsis) {
3843                 PMD_DRV_LOG(ERR,
3844                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3845                         vsi_count, hw->func_caps.num_vsis);
3846                 return -EINVAL;
3847         }
3848
3849         return 0;
3850 }
3851
3852 static int
3853 i40e_pf_get_switch_config(struct i40e_pf *pf)
3854 {
3855         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3856         struct i40e_aqc_get_switch_config_resp *switch_config;
3857         struct i40e_aqc_switch_config_element_resp *element;
3858         uint16_t start_seid = 0, num_reported;
3859         int ret;
3860
3861         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3862                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3863         if (!switch_config) {
3864                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3865                 return -ENOMEM;
3866         }
3867
3868         /* Get the switch configurations */
3869         ret = i40e_aq_get_switch_config(hw, switch_config,
3870                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3871         if (ret != I40E_SUCCESS) {
3872                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3873                 goto fail;
3874         }
3875         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3876         if (num_reported != 1) { /* The number should be 1 */
3877                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3878                 goto fail;
3879         }
3880
3881         /* Parse the switch configuration elements */
3882         element = &(switch_config->element[0]);
3883         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3884                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3885                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3886         } else
3887                 PMD_DRV_LOG(INFO, "Unknown element type");
3888
3889 fail:
3890         rte_free(switch_config);
3891
3892         return ret;
3893 }
3894
3895 static int
3896 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3897                         uint32_t num)
3898 {
3899         struct pool_entry *entry;
3900
3901         if (pool == NULL || num == 0)
3902                 return -EINVAL;
3903
3904         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3905         if (entry == NULL) {
3906                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3907                 return -ENOMEM;
3908         }
3909
3910         /* queue heap initialize */
3911         pool->num_free = num;
3912         pool->num_alloc = 0;
3913         pool->base = base;
3914         LIST_INIT(&pool->alloc_list);
3915         LIST_INIT(&pool->free_list);
3916
3917         /* Initialize element  */
3918         entry->base = 0;
3919         entry->len = num;
3920
3921         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3922         return 0;
3923 }
3924
3925 static void
3926 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3927 {
3928         struct pool_entry *entry, *next_entry;
3929
3930         if (pool == NULL)
3931                 return;
3932
3933         for (entry = LIST_FIRST(&pool->alloc_list);
3934                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3935                         entry = next_entry) {
3936                 LIST_REMOVE(entry, next);
3937                 rte_free(entry);
3938         }
3939
3940         for (entry = LIST_FIRST(&pool->free_list);
3941                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3942                         entry = next_entry) {
3943                 LIST_REMOVE(entry, next);
3944                 rte_free(entry);
3945         }
3946
3947         pool->num_free = 0;
3948         pool->num_alloc = 0;
3949         pool->base = 0;
3950         LIST_INIT(&pool->alloc_list);
3951         LIST_INIT(&pool->free_list);
3952 }
3953
3954 static int
3955 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3956                        uint32_t base)
3957 {
3958         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3959         uint32_t pool_offset;
3960         int insert;
3961
3962         if (pool == NULL) {
3963                 PMD_DRV_LOG(ERR, "Invalid parameter");
3964                 return -EINVAL;
3965         }
3966
3967         pool_offset = base - pool->base;
3968         /* Lookup in alloc list */
3969         LIST_FOREACH(entry, &pool->alloc_list, next) {
3970                 if (entry->base == pool_offset) {
3971                         valid_entry = entry;
3972                         LIST_REMOVE(entry, next);
3973                         break;
3974                 }
3975         }
3976
3977         /* Not find, return */
3978         if (valid_entry == NULL) {
3979                 PMD_DRV_LOG(ERR, "Failed to find entry");
3980                 return -EINVAL;
3981         }
3982
3983         /**
3984          * Found it, move it to free list  and try to merge.
3985          * In order to make merge easier, always sort it by qbase.
3986          * Find adjacent prev and last entries.
3987          */
3988         prev = next = NULL;
3989         LIST_FOREACH(entry, &pool->free_list, next) {
3990                 if (entry->base > valid_entry->base) {
3991                         next = entry;
3992                         break;
3993                 }
3994                 prev = entry;
3995         }
3996
3997         insert = 0;
3998         /* Try to merge with next one*/
3999         if (next != NULL) {
4000                 /* Merge with next one */
4001                 if (valid_entry->base + valid_entry->len == next->base) {
4002                         next->base = valid_entry->base;
4003                         next->len += valid_entry->len;
4004                         rte_free(valid_entry);
4005                         valid_entry = next;
4006                         insert = 1;
4007                 }
4008         }
4009
4010         if (prev != NULL) {
4011                 /* Merge with previous one */
4012                 if (prev->base + prev->len == valid_entry->base) {
4013                         prev->len += valid_entry->len;
4014                         /* If it merge with next one, remove next node */
4015                         if (insert == 1) {
4016                                 LIST_REMOVE(valid_entry, next);
4017                                 rte_free(valid_entry);
4018                         } else {
4019                                 rte_free(valid_entry);
4020                                 insert = 1;
4021                         }
4022                 }
4023         }
4024
4025         /* Not find any entry to merge, insert */
4026         if (insert == 0) {
4027                 if (prev != NULL)
4028                         LIST_INSERT_AFTER(prev, valid_entry, next);
4029                 else if (next != NULL)
4030                         LIST_INSERT_BEFORE(next, valid_entry, next);
4031                 else /* It's empty list, insert to head */
4032                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4033         }
4034
4035         pool->num_free += valid_entry->len;
4036         pool->num_alloc -= valid_entry->len;
4037
4038         return 0;
4039 }
4040
4041 static int
4042 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4043                        uint16_t num)
4044 {
4045         struct pool_entry *entry, *valid_entry;
4046
4047         if (pool == NULL || num == 0) {
4048                 PMD_DRV_LOG(ERR, "Invalid parameter");
4049                 return -EINVAL;
4050         }
4051
4052         if (pool->num_free < num) {
4053                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4054                             num, pool->num_free);
4055                 return -ENOMEM;
4056         }
4057
4058         valid_entry = NULL;
4059         /* Lookup  in free list and find most fit one */
4060         LIST_FOREACH(entry, &pool->free_list, next) {
4061                 if (entry->len >= num) {
4062                         /* Find best one */
4063                         if (entry->len == num) {
4064                                 valid_entry = entry;
4065                                 break;
4066                         }
4067                         if (valid_entry == NULL || valid_entry->len > entry->len)
4068                                 valid_entry = entry;
4069                 }
4070         }
4071
4072         /* Not find one to satisfy the request, return */
4073         if (valid_entry == NULL) {
4074                 PMD_DRV_LOG(ERR, "No valid entry found");
4075                 return -ENOMEM;
4076         }
4077         /**
4078          * The entry have equal queue number as requested,
4079          * remove it from alloc_list.
4080          */
4081         if (valid_entry->len == num) {
4082                 LIST_REMOVE(valid_entry, next);
4083         } else {
4084                 /**
4085                  * The entry have more numbers than requested,
4086                  * create a new entry for alloc_list and minus its
4087                  * queue base and number in free_list.
4088                  */
4089                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4090                 if (entry == NULL) {
4091                         PMD_DRV_LOG(ERR,
4092                                 "Failed to allocate memory for resource pool");
4093                         return -ENOMEM;
4094                 }
4095                 entry->base = valid_entry->base;
4096                 entry->len = num;
4097                 valid_entry->base += num;
4098                 valid_entry->len -= num;
4099                 valid_entry = entry;
4100         }
4101
4102         /* Insert it into alloc list, not sorted */
4103         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4104
4105         pool->num_free -= valid_entry->len;
4106         pool->num_alloc += valid_entry->len;
4107
4108         return valid_entry->base + pool->base;
4109 }
4110
4111 /**
4112  * bitmap_is_subset - Check whether src2 is subset of src1
4113  **/
4114 static inline int
4115 bitmap_is_subset(uint8_t src1, uint8_t src2)
4116 {
4117         return !((src1 ^ src2) & src2);
4118 }
4119
4120 static enum i40e_status_code
4121 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4122 {
4123         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4124
4125         /* If DCB is not supported, only default TC is supported */
4126         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4127                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4128                 return I40E_NOT_SUPPORTED;
4129         }
4130
4131         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4132                 PMD_DRV_LOG(ERR,
4133                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4134                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4135                 return I40E_NOT_SUPPORTED;
4136         }
4137         return I40E_SUCCESS;
4138 }
4139
4140 int
4141 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4142                                 struct i40e_vsi_vlan_pvid_info *info)
4143 {
4144         struct i40e_hw *hw;
4145         struct i40e_vsi_context ctxt;
4146         uint8_t vlan_flags = 0;
4147         int ret;
4148
4149         if (vsi == NULL || info == NULL) {
4150                 PMD_DRV_LOG(ERR, "invalid parameters");
4151                 return I40E_ERR_PARAM;
4152         }
4153
4154         if (info->on) {
4155                 vsi->info.pvid = info->config.pvid;
4156                 /**
4157                  * If insert pvid is enabled, only tagged pkts are
4158                  * allowed to be sent out.
4159                  */
4160                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4161                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4162         } else {
4163                 vsi->info.pvid = 0;
4164                 if (info->config.reject.tagged == 0)
4165                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4166
4167                 if (info->config.reject.untagged == 0)
4168                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4169         }
4170         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4171                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4172         vsi->info.port_vlan_flags |= vlan_flags;
4173         vsi->info.valid_sections =
4174                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4175         memset(&ctxt, 0, sizeof(ctxt));
4176         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4177         ctxt.seid = vsi->seid;
4178
4179         hw = I40E_VSI_TO_HW(vsi);
4180         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4181         if (ret != I40E_SUCCESS)
4182                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4183
4184         return ret;
4185 }
4186
4187 static int
4188 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4189 {
4190         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4191         int i, ret;
4192         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4193
4194         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4195         if (ret != I40E_SUCCESS)
4196                 return ret;
4197
4198         if (!vsi->seid) {
4199                 PMD_DRV_LOG(ERR, "seid not valid");
4200                 return -EINVAL;
4201         }
4202
4203         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4204         tc_bw_data.tc_valid_bits = enabled_tcmap;
4205         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4206                 tc_bw_data.tc_bw_credits[i] =
4207                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4208
4209         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4210         if (ret != I40E_SUCCESS) {
4211                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4212                 return ret;
4213         }
4214
4215         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4216                                         sizeof(vsi->info.qs_handle));
4217         return I40E_SUCCESS;
4218 }
4219
4220 static enum i40e_status_code
4221 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4222                                  struct i40e_aqc_vsi_properties_data *info,
4223                                  uint8_t enabled_tcmap)
4224 {
4225         enum i40e_status_code ret;
4226         int i, total_tc = 0;
4227         uint16_t qpnum_per_tc, bsf, qp_idx;
4228
4229         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4230         if (ret != I40E_SUCCESS)
4231                 return ret;
4232
4233         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4234                 if (enabled_tcmap & (1 << i))
4235                         total_tc++;
4236         vsi->enabled_tc = enabled_tcmap;
4237
4238         /* Number of queues per enabled TC */
4239         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4240         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4241         bsf = rte_bsf32(qpnum_per_tc);
4242
4243         /* Adjust the queue number to actual queues that can be applied */
4244         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4245                 vsi->nb_qps = qpnum_per_tc * total_tc;
4246
4247         /**
4248          * Configure TC and queue mapping parameters, for enabled TC,
4249          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4250          * default queue will serve it.
4251          */
4252         qp_idx = 0;
4253         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4254                 if (vsi->enabled_tc & (1 << i)) {
4255                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4256                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4257                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4258                         qp_idx += qpnum_per_tc;
4259                 } else
4260                         info->tc_mapping[i] = 0;
4261         }
4262
4263         /* Associate queue number with VSI */
4264         if (vsi->type == I40E_VSI_SRIOV) {
4265                 info->mapping_flags |=
4266                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4267                 for (i = 0; i < vsi->nb_qps; i++)
4268                         info->queue_mapping[i] =
4269                                 rte_cpu_to_le_16(vsi->base_queue + i);
4270         } else {
4271                 info->mapping_flags |=
4272                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4273                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4274         }
4275         info->valid_sections |=
4276                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4277
4278         return I40E_SUCCESS;
4279 }
4280
4281 static int
4282 i40e_veb_release(struct i40e_veb *veb)
4283 {
4284         struct i40e_vsi *vsi;
4285         struct i40e_hw *hw;
4286
4287         if (veb == NULL)
4288                 return -EINVAL;
4289
4290         if (!TAILQ_EMPTY(&veb->head)) {
4291                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4292                 return -EACCES;
4293         }
4294         /* associate_vsi field is NULL for floating VEB */
4295         if (veb->associate_vsi != NULL) {
4296                 vsi = veb->associate_vsi;
4297                 hw = I40E_VSI_TO_HW(vsi);
4298
4299                 vsi->uplink_seid = veb->uplink_seid;
4300                 vsi->veb = NULL;
4301         } else {
4302                 veb->associate_pf->main_vsi->floating_veb = NULL;
4303                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4304         }
4305
4306         i40e_aq_delete_element(hw, veb->seid, NULL);
4307         rte_free(veb);
4308         return I40E_SUCCESS;
4309 }
4310
4311 /* Setup a veb */
4312 static struct i40e_veb *
4313 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4314 {
4315         struct i40e_veb *veb;
4316         int ret;
4317         struct i40e_hw *hw;
4318
4319         if (pf == NULL) {
4320                 PMD_DRV_LOG(ERR,
4321                             "veb setup failed, associated PF shouldn't null");
4322                 return NULL;
4323         }
4324         hw = I40E_PF_TO_HW(pf);
4325
4326         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4327         if (!veb) {
4328                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4329                 goto fail;
4330         }
4331
4332         veb->associate_vsi = vsi;
4333         veb->associate_pf = pf;
4334         TAILQ_INIT(&veb->head);
4335         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4336
4337         /* create floating veb if vsi is NULL */
4338         if (vsi != NULL) {
4339                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4340                                       I40E_DEFAULT_TCMAP, false,
4341                                       &veb->seid, false, NULL);
4342         } else {
4343                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4344                                       true, &veb->seid, false, NULL);
4345         }
4346
4347         if (ret != I40E_SUCCESS) {
4348                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4349                             hw->aq.asq_last_status);
4350                 goto fail;
4351         }
4352         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4353
4354         /* get statistics index */
4355         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4356                                 &veb->stats_idx, NULL, NULL, NULL);
4357         if (ret != I40E_SUCCESS) {
4358                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4359                             hw->aq.asq_last_status);
4360                 goto fail;
4361         }
4362         /* Get VEB bandwidth, to be implemented */
4363         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4364         if (vsi)
4365                 vsi->uplink_seid = veb->seid;
4366
4367         return veb;
4368 fail:
4369         rte_free(veb);
4370         return NULL;
4371 }
4372
4373 int
4374 i40e_vsi_release(struct i40e_vsi *vsi)
4375 {
4376         struct i40e_pf *pf;
4377         struct i40e_hw *hw;
4378         struct i40e_vsi_list *vsi_list;
4379         void *temp;
4380         int ret;
4381         struct i40e_mac_filter *f;
4382         uint16_t user_param;
4383
4384         if (!vsi)
4385                 return I40E_SUCCESS;
4386
4387         if (!vsi->adapter)
4388                 return -EFAULT;
4389
4390         user_param = vsi->user_param;
4391
4392         pf = I40E_VSI_TO_PF(vsi);
4393         hw = I40E_VSI_TO_HW(vsi);
4394
4395         /* VSI has child to attach, release child first */
4396         if (vsi->veb) {
4397                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4398                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4399                                 return -1;
4400                 }
4401                 i40e_veb_release(vsi->veb);
4402         }
4403
4404         if (vsi->floating_veb) {
4405                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4406                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4407                                 return -1;
4408                 }
4409         }
4410
4411         /* Remove all macvlan filters of the VSI */
4412         i40e_vsi_remove_all_macvlan_filter(vsi);
4413         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4414                 rte_free(f);
4415
4416         if (vsi->type != I40E_VSI_MAIN &&
4417             ((vsi->type != I40E_VSI_SRIOV) ||
4418             !pf->floating_veb_list[user_param])) {
4419                 /* Remove vsi from parent's sibling list */
4420                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4421                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4422                         return I40E_ERR_PARAM;
4423                 }
4424                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4425                                 &vsi->sib_vsi_list, list);
4426
4427                 /* Remove all switch element of the VSI */
4428                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4429                 if (ret != I40E_SUCCESS)
4430                         PMD_DRV_LOG(ERR, "Failed to delete element");
4431         }
4432
4433         if ((vsi->type == I40E_VSI_SRIOV) &&
4434             pf->floating_veb_list[user_param]) {
4435                 /* Remove vsi from parent's sibling list */
4436                 if (vsi->parent_vsi == NULL ||
4437                     vsi->parent_vsi->floating_veb == NULL) {
4438                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4439                         return I40E_ERR_PARAM;
4440                 }
4441                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4442                              &vsi->sib_vsi_list, list);
4443
4444                 /* Remove all switch element of the VSI */
4445                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4446                 if (ret != I40E_SUCCESS)
4447                         PMD_DRV_LOG(ERR, "Failed to delete element");
4448         }
4449
4450         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4451
4452         if (vsi->type != I40E_VSI_SRIOV)
4453                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4454         rte_free(vsi);
4455
4456         return I40E_SUCCESS;
4457 }
4458
4459 static int
4460 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4461 {
4462         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4463         struct i40e_aqc_remove_macvlan_element_data def_filter;
4464         struct i40e_mac_filter_info filter;
4465         int ret;
4466
4467         if (vsi->type != I40E_VSI_MAIN)
4468                 return I40E_ERR_CONFIG;
4469         memset(&def_filter, 0, sizeof(def_filter));
4470         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4471                                         ETH_ADDR_LEN);
4472         def_filter.vlan_tag = 0;
4473         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4474                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4475         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4476         if (ret != I40E_SUCCESS) {
4477                 struct i40e_mac_filter *f;
4478                 struct ether_addr *mac;
4479
4480                 PMD_DRV_LOG(WARNING,
4481                         "Cannot remove the default macvlan filter");
4482                 /* It needs to add the permanent mac into mac list */
4483                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4484                 if (f == NULL) {
4485                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4486                         return I40E_ERR_NO_MEMORY;
4487                 }
4488                 mac = &f->mac_info.mac_addr;
4489                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4490                                 ETH_ADDR_LEN);
4491                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4492                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4493                 vsi->mac_num++;
4494
4495                 return ret;
4496         }
4497         (void)rte_memcpy(&filter.mac_addr,
4498                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4499         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4500         return i40e_vsi_add_mac(vsi, &filter);
4501 }
4502
4503 /*
4504  * i40e_vsi_get_bw_config - Query VSI BW Information
4505  * @vsi: the VSI to be queried
4506  *
4507  * Returns 0 on success, negative value on failure
4508  */
4509 static enum i40e_status_code
4510 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4511 {
4512         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4513         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4514         struct i40e_hw *hw = &vsi->adapter->hw;
4515         i40e_status ret;
4516         int i;
4517         uint32_t bw_max;
4518
4519         memset(&bw_config, 0, sizeof(bw_config));
4520         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4521         if (ret != I40E_SUCCESS) {
4522                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4523                             hw->aq.asq_last_status);
4524                 return ret;
4525         }
4526
4527         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4528         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4529                                         &ets_sla_config, NULL);
4530         if (ret != I40E_SUCCESS) {
4531                 PMD_DRV_LOG(ERR,
4532                         "VSI failed to get TC bandwdith configuration %u",
4533                         hw->aq.asq_last_status);
4534                 return ret;
4535         }
4536
4537         /* store and print out BW info */
4538         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4539         vsi->bw_info.bw_max = bw_config.max_bw;
4540         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4541         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4542         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4543                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4544                      I40E_16_BIT_WIDTH);
4545         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4546                 vsi->bw_info.bw_ets_share_credits[i] =
4547                                 ets_sla_config.share_credits[i];
4548                 vsi->bw_info.bw_ets_credits[i] =
4549                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4550                 /* 4 bits per TC, 4th bit is reserved */
4551                 vsi->bw_info.bw_ets_max[i] =
4552                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4553                                   RTE_LEN2MASK(3, uint8_t));
4554                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4555                             vsi->bw_info.bw_ets_share_credits[i]);
4556                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4557                             vsi->bw_info.bw_ets_credits[i]);
4558                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4559                             vsi->bw_info.bw_ets_max[i]);
4560         }
4561
4562         return I40E_SUCCESS;
4563 }
4564
4565 /* i40e_enable_pf_lb
4566  * @pf: pointer to the pf structure
4567  *
4568  * allow loopback on pf
4569  */
4570 static inline void
4571 i40e_enable_pf_lb(struct i40e_pf *pf)
4572 {
4573         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4574         struct i40e_vsi_context ctxt;
4575         int ret;
4576
4577         /* Use the FW API if FW >= v5.0 */
4578         if (hw->aq.fw_maj_ver < 5) {
4579                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4580                 return;
4581         }
4582
4583         memset(&ctxt, 0, sizeof(ctxt));
4584         ctxt.seid = pf->main_vsi_seid;
4585         ctxt.pf_num = hw->pf_id;
4586         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4587         if (ret) {
4588                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4589                             ret, hw->aq.asq_last_status);
4590                 return;
4591         }
4592         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4593         ctxt.info.valid_sections =
4594                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4595         ctxt.info.switch_id |=
4596                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4597
4598         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4599         if (ret)
4600                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4601                             hw->aq.asq_last_status);
4602 }
4603
4604 /* Setup a VSI */
4605 struct i40e_vsi *
4606 i40e_vsi_setup(struct i40e_pf *pf,
4607                enum i40e_vsi_type type,
4608                struct i40e_vsi *uplink_vsi,
4609                uint16_t user_param)
4610 {
4611         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4612         struct i40e_vsi *vsi;
4613         struct i40e_mac_filter_info filter;
4614         int ret;
4615         struct i40e_vsi_context ctxt;
4616         struct ether_addr broadcast =
4617                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4618
4619         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4620             uplink_vsi == NULL) {
4621                 PMD_DRV_LOG(ERR,
4622                         "VSI setup failed, VSI link shouldn't be NULL");
4623                 return NULL;
4624         }
4625
4626         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4627                 PMD_DRV_LOG(ERR,
4628                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4629                 return NULL;
4630         }
4631
4632         /* two situations
4633          * 1.type is not MAIN and uplink vsi is not NULL
4634          * If uplink vsi didn't setup VEB, create one first under veb field
4635          * 2.type is SRIOV and the uplink is NULL
4636          * If floating VEB is NULL, create one veb under floating veb field
4637          */
4638
4639         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4640             uplink_vsi->veb == NULL) {
4641                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4642
4643                 if (uplink_vsi->veb == NULL) {
4644                         PMD_DRV_LOG(ERR, "VEB setup failed");
4645                         return NULL;
4646                 }
4647                 /* set ALLOWLOOPBACk on pf, when veb is created */
4648                 i40e_enable_pf_lb(pf);
4649         }
4650
4651         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4652             pf->main_vsi->floating_veb == NULL) {
4653                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4654
4655                 if (pf->main_vsi->floating_veb == NULL) {
4656                         PMD_DRV_LOG(ERR, "VEB setup failed");
4657                         return NULL;
4658                 }
4659         }
4660
4661         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4662         if (!vsi) {
4663                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4664                 return NULL;
4665         }
4666         TAILQ_INIT(&vsi->mac_list);
4667         vsi->type = type;
4668         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4669         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4670         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4671         vsi->user_param = user_param;
4672         vsi->vlan_anti_spoof_on = 0;
4673         /* Allocate queues */
4674         switch (vsi->type) {
4675         case I40E_VSI_MAIN  :
4676                 vsi->nb_qps = pf->lan_nb_qps;
4677                 break;
4678         case I40E_VSI_SRIOV :
4679                 vsi->nb_qps = pf->vf_nb_qps;
4680                 break;
4681         case I40E_VSI_VMDQ2:
4682                 vsi->nb_qps = pf->vmdq_nb_qps;
4683                 break;
4684         case I40E_VSI_FDIR:
4685                 vsi->nb_qps = pf->fdir_nb_qps;
4686                 break;
4687         default:
4688                 goto fail_mem;
4689         }
4690         /*
4691          * The filter status descriptor is reported in rx queue 0,
4692          * while the tx queue for fdir filter programming has no
4693          * such constraints, can be non-zero queues.
4694          * To simplify it, choose FDIR vsi use queue 0 pair.
4695          * To make sure it will use queue 0 pair, queue allocation
4696          * need be done before this function is called
4697          */
4698         if (type != I40E_VSI_FDIR) {
4699                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4700                         if (ret < 0) {
4701                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4702                                                 vsi->seid, ret);
4703                                 goto fail_mem;
4704                         }
4705                         vsi->base_queue = ret;
4706         } else
4707                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4708
4709         /* VF has MSIX interrupt in VF range, don't allocate here */
4710         if (type == I40E_VSI_MAIN) {
4711                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4712                                           RTE_MIN(vsi->nb_qps,
4713                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4714                 if (ret < 0) {
4715                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4716                                     vsi->seid, ret);
4717                         goto fail_queue_alloc;
4718                 }
4719                 vsi->msix_intr = ret;
4720                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4721         } else if (type != I40E_VSI_SRIOV) {
4722                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4723                 if (ret < 0) {
4724                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4725                         goto fail_queue_alloc;
4726                 }
4727                 vsi->msix_intr = ret;
4728                 vsi->nb_msix = 1;
4729         } else {
4730                 vsi->msix_intr = 0;
4731                 vsi->nb_msix = 0;
4732         }
4733
4734         /* Add VSI */
4735         if (type == I40E_VSI_MAIN) {
4736                 /* For main VSI, no need to add since it's default one */
4737                 vsi->uplink_seid = pf->mac_seid;
4738                 vsi->seid = pf->main_vsi_seid;
4739                 /* Bind queues with specific MSIX interrupt */
4740                 /**
4741                  * Needs 2 interrupt at least, one for misc cause which will
4742                  * enabled from OS side, Another for queues binding the
4743                  * interrupt from device side only.
4744                  */
4745
4746                 /* Get default VSI parameters from hardware */
4747                 memset(&ctxt, 0, sizeof(ctxt));
4748                 ctxt.seid = vsi->seid;
4749                 ctxt.pf_num = hw->pf_id;
4750                 ctxt.uplink_seid = vsi->uplink_seid;
4751                 ctxt.vf_num = 0;
4752                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4753                 if (ret != I40E_SUCCESS) {
4754                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4755                         goto fail_msix_alloc;
4756                 }
4757                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4758                         sizeof(struct i40e_aqc_vsi_properties_data));
4759                 vsi->vsi_id = ctxt.vsi_number;
4760                 vsi->info.valid_sections = 0;
4761
4762                 /* Configure tc, enabled TC0 only */
4763                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4764                         I40E_SUCCESS) {
4765                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4766                         goto fail_msix_alloc;
4767                 }
4768
4769                 /* TC, queue mapping */
4770                 memset(&ctxt, 0, sizeof(ctxt));
4771                 vsi->info.valid_sections |=
4772                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4773                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4774                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4775                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4776                         sizeof(struct i40e_aqc_vsi_properties_data));
4777                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4778                                                 I40E_DEFAULT_TCMAP);
4779                 if (ret != I40E_SUCCESS) {
4780                         PMD_DRV_LOG(ERR,
4781                                 "Failed to configure TC queue mapping");
4782                         goto fail_msix_alloc;
4783                 }
4784                 ctxt.seid = vsi->seid;
4785                 ctxt.pf_num = hw->pf_id;
4786                 ctxt.uplink_seid = vsi->uplink_seid;
4787                 ctxt.vf_num = 0;
4788
4789                 /* Update VSI parameters */
4790                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4791                 if (ret != I40E_SUCCESS) {
4792                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4793                         goto fail_msix_alloc;
4794                 }
4795
4796                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4797                                                 sizeof(vsi->info.tc_mapping));
4798                 (void)rte_memcpy(&vsi->info.queue_mapping,
4799                                 &ctxt.info.queue_mapping,
4800                         sizeof(vsi->info.queue_mapping));
4801                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4802                 vsi->info.valid_sections = 0;
4803
4804                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4805                                 ETH_ADDR_LEN);
4806
4807                 /**
4808                  * Updating default filter settings are necessary to prevent
4809                  * reception of tagged packets.
4810                  * Some old firmware configurations load a default macvlan
4811                  * filter which accepts both tagged and untagged packets.
4812                  * The updating is to use a normal filter instead if needed.
4813                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4814                  * The firmware with correct configurations load the default
4815                  * macvlan filter which is expected and cannot be removed.
4816                  */
4817                 i40e_update_default_filter_setting(vsi);
4818                 i40e_config_qinq(hw, vsi);
4819         } else if (type == I40E_VSI_SRIOV) {
4820                 memset(&ctxt, 0, sizeof(ctxt));
4821                 /**
4822                  * For other VSI, the uplink_seid equals to uplink VSI's
4823                  * uplink_seid since they share same VEB
4824                  */
4825                 if (uplink_vsi == NULL)
4826                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4827                 else
4828                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4829                 ctxt.pf_num = hw->pf_id;
4830                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4831                 ctxt.uplink_seid = vsi->uplink_seid;
4832                 ctxt.connection_type = 0x1;
4833                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4834
4835                 /* Use the VEB configuration if FW >= v5.0 */
4836                 if (hw->aq.fw_maj_ver >= 5) {
4837                         /* Configure switch ID */
4838                         ctxt.info.valid_sections |=
4839                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4840                         ctxt.info.switch_id =
4841                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4842                 }
4843
4844                 /* Configure port/vlan */
4845                 ctxt.info.valid_sections |=
4846                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4847                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4848                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4849                                                 hw->func_caps.enabled_tcmap);
4850                 if (ret != I40E_SUCCESS) {
4851                         PMD_DRV_LOG(ERR,
4852                                 "Failed to configure TC queue mapping");
4853                         goto fail_msix_alloc;
4854                 }
4855
4856                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4857                 ctxt.info.valid_sections |=
4858                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4859                 /**
4860                  * Since VSI is not created yet, only configure parameter,
4861                  * will add vsi below.
4862                  */
4863
4864                 i40e_config_qinq(hw, vsi);
4865         } else if (type == I40E_VSI_VMDQ2) {
4866                 memset(&ctxt, 0, sizeof(ctxt));
4867                 /*
4868                  * For other VSI, the uplink_seid equals to uplink VSI's
4869                  * uplink_seid since they share same VEB
4870                  */
4871                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4872                 ctxt.pf_num = hw->pf_id;
4873                 ctxt.vf_num = 0;
4874                 ctxt.uplink_seid = vsi->uplink_seid;
4875                 ctxt.connection_type = 0x1;
4876                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4877
4878                 ctxt.info.valid_sections |=
4879                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4880                 /* user_param carries flag to enable loop back */
4881                 if (user_param) {
4882                         ctxt.info.switch_id =
4883                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4884                         ctxt.info.switch_id |=
4885                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4886                 }
4887
4888                 /* Configure port/vlan */
4889                 ctxt.info.valid_sections |=
4890                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4891                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4892                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4893                                                 I40E_DEFAULT_TCMAP);
4894                 if (ret != I40E_SUCCESS) {
4895                         PMD_DRV_LOG(ERR,
4896                                 "Failed to configure TC queue mapping");
4897                         goto fail_msix_alloc;
4898                 }
4899                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4900                 ctxt.info.valid_sections |=
4901                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4902         } else if (type == I40E_VSI_FDIR) {
4903                 memset(&ctxt, 0, sizeof(ctxt));
4904                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4905                 ctxt.pf_num = hw->pf_id;
4906                 ctxt.vf_num = 0;
4907                 ctxt.uplink_seid = vsi->uplink_seid;
4908                 ctxt.connection_type = 0x1;     /* regular data port */
4909                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4910                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4911                                                 I40E_DEFAULT_TCMAP);
4912                 if (ret != I40E_SUCCESS) {
4913                         PMD_DRV_LOG(ERR,
4914                                 "Failed to configure TC queue mapping.");
4915                         goto fail_msix_alloc;
4916                 }
4917                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4918                 ctxt.info.valid_sections |=
4919                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4920         } else {
4921                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4922                 goto fail_msix_alloc;
4923         }
4924
4925         if (vsi->type != I40E_VSI_MAIN) {
4926                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4927                 if (ret != I40E_SUCCESS) {
4928                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4929                                     hw->aq.asq_last_status);
4930                         goto fail_msix_alloc;
4931                 }
4932                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4933                 vsi->info.valid_sections = 0;
4934                 vsi->seid = ctxt.seid;
4935                 vsi->vsi_id = ctxt.vsi_number;
4936                 vsi->sib_vsi_list.vsi = vsi;
4937                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4938                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4939                                           &vsi->sib_vsi_list, list);
4940                 } else {
4941                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4942                                           &vsi->sib_vsi_list, list);
4943                 }
4944         }
4945
4946         /* MAC/VLAN configuration */
4947         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4948         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4949
4950         ret = i40e_vsi_add_mac(vsi, &filter);
4951         if (ret != I40E_SUCCESS) {
4952                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4953                 goto fail_msix_alloc;
4954         }
4955
4956         /* Get VSI BW information */
4957         i40e_vsi_get_bw_config(vsi);
4958         return vsi;
4959 fail_msix_alloc:
4960         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4961 fail_queue_alloc:
4962         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4963 fail_mem:
4964         rte_free(vsi);
4965         return NULL;
4966 }
4967
4968 /* Configure vlan filter on or off */
4969 int
4970 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4971 {
4972         int i, num;
4973         struct i40e_mac_filter *f;
4974         void *temp;
4975         struct i40e_mac_filter_info *mac_filter;
4976         enum rte_mac_filter_type desired_filter;
4977         int ret = I40E_SUCCESS;
4978
4979         if (on) {
4980                 /* Filter to match MAC and VLAN */
4981                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4982         } else {
4983                 /* Filter to match only MAC */
4984                 desired_filter = RTE_MAC_PERFECT_MATCH;
4985         }
4986
4987         num = vsi->mac_num;
4988
4989         mac_filter = rte_zmalloc("mac_filter_info_data",
4990                                  num * sizeof(*mac_filter), 0);
4991         if (mac_filter == NULL) {
4992                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4993                 return I40E_ERR_NO_MEMORY;
4994         }
4995
4996         i = 0;
4997
4998         /* Remove all existing mac */
4999         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5000                 mac_filter[i] = f->mac_info;
5001                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5002                 if (ret) {
5003                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5004                                     on ? "enable" : "disable");
5005                         goto DONE;
5006                 }
5007                 i++;
5008         }
5009
5010         /* Override with new filter */
5011         for (i = 0; i < num; i++) {
5012                 mac_filter[i].filter_type = desired_filter;
5013                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5014                 if (ret) {
5015                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5016                                     on ? "enable" : "disable");
5017                         goto DONE;
5018                 }
5019         }
5020
5021 DONE:
5022         rte_free(mac_filter);
5023         return ret;
5024 }
5025
5026 /* Configure vlan stripping on or off */
5027 int
5028 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5029 {
5030         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5031         struct i40e_vsi_context ctxt;
5032         uint8_t vlan_flags;
5033         int ret = I40E_SUCCESS;
5034
5035         /* Check if it has been already on or off */
5036         if (vsi->info.valid_sections &
5037                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5038                 if (on) {
5039                         if ((vsi->info.port_vlan_flags &
5040                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5041                                 return 0; /* already on */
5042                 } else {
5043                         if ((vsi->info.port_vlan_flags &
5044                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5045                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5046                                 return 0; /* already off */
5047                 }
5048         }
5049
5050         if (on)
5051                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5052         else
5053                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5054         vsi->info.valid_sections =
5055                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5056         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5057         vsi->info.port_vlan_flags |= vlan_flags;
5058         ctxt.seid = vsi->seid;
5059         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5060         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5061         if (ret)
5062                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5063                             on ? "enable" : "disable");
5064
5065         return ret;
5066 }
5067
5068 static int
5069 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5070 {
5071         struct rte_eth_dev_data *data = dev->data;
5072         int ret;
5073         int mask = 0;
5074
5075         /* Apply vlan offload setting */
5076         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5077         i40e_vlan_offload_set(dev, mask);
5078
5079         /* Apply double-vlan setting, not implemented yet */
5080
5081         /* Apply pvid setting */
5082         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5083                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5084         if (ret)
5085                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5086
5087         return ret;
5088 }
5089
5090 static int
5091 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5092 {
5093         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5094
5095         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5096 }
5097
5098 static int
5099 i40e_update_flow_control(struct i40e_hw *hw)
5100 {
5101 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5102         struct i40e_link_status link_status;
5103         uint32_t rxfc = 0, txfc = 0, reg;
5104         uint8_t an_info;
5105         int ret;
5106
5107         memset(&link_status, 0, sizeof(link_status));
5108         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5109         if (ret != I40E_SUCCESS) {
5110                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5111                 goto write_reg; /* Disable flow control */
5112         }
5113
5114         an_info = hw->phy.link_info.an_info;
5115         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5116                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5117                 ret = I40E_ERR_NOT_READY;
5118                 goto write_reg; /* Disable flow control */
5119         }
5120         /**
5121          * If link auto negotiation is enabled, flow control needs to
5122          * be configured according to it
5123          */
5124         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5125         case I40E_LINK_PAUSE_RXTX:
5126                 rxfc = 1;
5127                 txfc = 1;
5128                 hw->fc.current_mode = I40E_FC_FULL;
5129                 break;
5130         case I40E_AQ_LINK_PAUSE_RX:
5131                 rxfc = 1;
5132                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5133                 break;
5134         case I40E_AQ_LINK_PAUSE_TX:
5135                 txfc = 1;
5136                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5137                 break;
5138         default:
5139                 hw->fc.current_mode = I40E_FC_NONE;
5140                 break;
5141         }
5142
5143 write_reg:
5144         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5145                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5146         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5147         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5148         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5149         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5150
5151         return ret;
5152 }
5153
5154 /* PF setup */
5155 static int
5156 i40e_pf_setup(struct i40e_pf *pf)
5157 {
5158         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5159         struct i40e_filter_control_settings settings;
5160         struct i40e_vsi *vsi;
5161         int ret;
5162
5163         /* Clear all stats counters */
5164         pf->offset_loaded = FALSE;
5165         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5166         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5167
5168         ret = i40e_pf_get_switch_config(pf);
5169         if (ret != I40E_SUCCESS) {
5170                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5171                 return ret;
5172         }
5173         if (pf->flags & I40E_FLAG_FDIR) {
5174                 /* make queue allocated first, let FDIR use queue pair 0*/
5175                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5176                 if (ret != I40E_FDIR_QUEUE_ID) {
5177                         PMD_DRV_LOG(ERR,
5178                                 "queue allocation fails for FDIR: ret =%d",
5179                                 ret);
5180                         pf->flags &= ~I40E_FLAG_FDIR;
5181                 }
5182         }
5183         /*  main VSI setup */
5184         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5185         if (!vsi) {
5186                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5187                 return I40E_ERR_NOT_READY;
5188         }
5189         pf->main_vsi = vsi;
5190
5191         /* Configure filter control */
5192         memset(&settings, 0, sizeof(settings));
5193         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5194                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5195         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5196                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5197         else {
5198                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5199                         hw->func_caps.rss_table_size);
5200                 return I40E_ERR_PARAM;
5201         }
5202         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5203                 hw->func_caps.rss_table_size);
5204         pf->hash_lut_size = hw->func_caps.rss_table_size;
5205
5206         /* Enable ethtype and macvlan filters */
5207         settings.enable_ethtype = TRUE;
5208         settings.enable_macvlan = TRUE;
5209         ret = i40e_set_filter_control(hw, &settings);
5210         if (ret)
5211                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5212                                                                 ret);
5213
5214         /* Update flow control according to the auto negotiation */
5215         i40e_update_flow_control(hw);
5216
5217         return I40E_SUCCESS;
5218 }
5219
5220 int
5221 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5222 {
5223         uint32_t reg;
5224         uint16_t j;
5225
5226         /**
5227          * Set or clear TX Queue Disable flags,
5228          * which is required by hardware.
5229          */
5230         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5231         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5232
5233         /* Wait until the request is finished */
5234         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5235                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5236                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5237                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5238                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5239                                                         & 0x1))) {
5240                         break;
5241                 }
5242         }
5243         if (on) {
5244                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5245                         return I40E_SUCCESS; /* already on, skip next steps */
5246
5247                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5248                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5249         } else {
5250                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5251                         return I40E_SUCCESS; /* already off, skip next steps */
5252                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5253         }
5254         /* Write the register */
5255         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5256         /* Check the result */
5257         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5258                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5259                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5260                 if (on) {
5261                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5262                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5263                                 break;
5264                 } else {
5265                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5266                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5267                                 break;
5268                 }
5269         }
5270         /* Check if it is timeout */
5271         if (j >= I40E_CHK_Q_ENA_COUNT) {
5272                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5273                             (on ? "enable" : "disable"), q_idx);
5274                 return I40E_ERR_TIMEOUT;
5275         }
5276
5277         return I40E_SUCCESS;
5278 }
5279
5280 /* Swith on or off the tx queues */
5281 static int
5282 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5283 {
5284         struct rte_eth_dev_data *dev_data = pf->dev_data;
5285         struct i40e_tx_queue *txq;
5286         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5287         uint16_t i;
5288         int ret;
5289
5290         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5291                 txq = dev_data->tx_queues[i];
5292                 /* Don't operate the queue if not configured or
5293                  * if starting only per queue */
5294                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5295                         continue;
5296                 if (on)
5297                         ret = i40e_dev_tx_queue_start(dev, i);
5298                 else
5299                         ret = i40e_dev_tx_queue_stop(dev, i);
5300                 if ( ret != I40E_SUCCESS)
5301                         return ret;
5302         }
5303
5304         return I40E_SUCCESS;
5305 }
5306
5307 int
5308 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5309 {
5310         uint32_t reg;
5311         uint16_t j;
5312
5313         /* Wait until the request is finished */
5314         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5315                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5316                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5317                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5318                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5319                         break;
5320         }
5321
5322         if (on) {
5323                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5324                         return I40E_SUCCESS; /* Already on, skip next steps */
5325                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5326         } else {
5327                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5328                         return I40E_SUCCESS; /* Already off, skip next steps */
5329                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5330         }
5331
5332         /* Write the register */
5333         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5334         /* Check the result */
5335         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5336                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5337                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5338                 if (on) {
5339                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5340                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5341                                 break;
5342                 } else {
5343                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5344                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5345                                 break;
5346                 }
5347         }
5348
5349         /* Check if it is timeout */
5350         if (j >= I40E_CHK_Q_ENA_COUNT) {
5351                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5352                             (on ? "enable" : "disable"), q_idx);
5353                 return I40E_ERR_TIMEOUT;
5354         }
5355
5356         return I40E_SUCCESS;
5357 }
5358 /* Switch on or off the rx queues */
5359 static int
5360 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5361 {
5362         struct rte_eth_dev_data *dev_data = pf->dev_data;
5363         struct i40e_rx_queue *rxq;
5364         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5365         uint16_t i;
5366         int ret;
5367
5368         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5369                 rxq = dev_data->rx_queues[i];
5370                 /* Don't operate the queue if not configured or
5371                  * if starting only per queue */
5372                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5373                         continue;
5374                 if (on)
5375                         ret = i40e_dev_rx_queue_start(dev, i);
5376                 else
5377                         ret = i40e_dev_rx_queue_stop(dev, i);
5378                 if (ret != I40E_SUCCESS)
5379                         return ret;
5380         }
5381
5382         return I40E_SUCCESS;
5383 }
5384
5385 /* Switch on or off all the rx/tx queues */
5386 int
5387 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5388 {
5389         int ret;
5390
5391         if (on) {
5392                 /* enable rx queues before enabling tx queues */
5393                 ret = i40e_dev_switch_rx_queues(pf, on);
5394                 if (ret) {
5395                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5396                         return ret;
5397                 }
5398                 ret = i40e_dev_switch_tx_queues(pf, on);
5399         } else {
5400                 /* Stop tx queues before stopping rx queues */
5401                 ret = i40e_dev_switch_tx_queues(pf, on);
5402                 if (ret) {
5403                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5404                         return ret;
5405                 }
5406                 ret = i40e_dev_switch_rx_queues(pf, on);
5407         }
5408
5409         return ret;
5410 }
5411
5412 /* Initialize VSI for TX */
5413 static int
5414 i40e_dev_tx_init(struct i40e_pf *pf)
5415 {
5416         struct rte_eth_dev_data *data = pf->dev_data;
5417         uint16_t i;
5418         uint32_t ret = I40E_SUCCESS;
5419         struct i40e_tx_queue *txq;
5420
5421         for (i = 0; i < data->nb_tx_queues; i++) {
5422                 txq = data->tx_queues[i];
5423                 if (!txq || !txq->q_set)
5424                         continue;
5425                 ret = i40e_tx_queue_init(txq);
5426                 if (ret != I40E_SUCCESS)
5427                         break;
5428         }
5429         if (ret == I40E_SUCCESS)
5430                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5431                                      ->eth_dev);
5432
5433         return ret;
5434 }
5435
5436 /* Initialize VSI for RX */
5437 static int
5438 i40e_dev_rx_init(struct i40e_pf *pf)
5439 {
5440         struct rte_eth_dev_data *data = pf->dev_data;
5441         int ret = I40E_SUCCESS;
5442         uint16_t i;
5443         struct i40e_rx_queue *rxq;
5444
5445         i40e_pf_config_mq_rx(pf);
5446         for (i = 0; i < data->nb_rx_queues; i++) {
5447                 rxq = data->rx_queues[i];
5448                 if (!rxq || !rxq->q_set)
5449                         continue;
5450
5451                 ret = i40e_rx_queue_init(rxq);
5452                 if (ret != I40E_SUCCESS) {
5453                         PMD_DRV_LOG(ERR,
5454                                 "Failed to do RX queue initialization");
5455                         break;
5456                 }
5457         }
5458         if (ret == I40E_SUCCESS)
5459                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5460                                      ->eth_dev);
5461
5462         return ret;
5463 }
5464
5465 static int
5466 i40e_dev_rxtx_init(struct i40e_pf *pf)
5467 {
5468         int err;
5469
5470         err = i40e_dev_tx_init(pf);
5471         if (err) {
5472                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5473                 return err;
5474         }
5475         err = i40e_dev_rx_init(pf);
5476         if (err) {
5477                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5478                 return err;
5479         }
5480
5481         return err;
5482 }
5483
5484 static int
5485 i40e_vmdq_setup(struct rte_eth_dev *dev)
5486 {
5487         struct rte_eth_conf *conf = &dev->data->dev_conf;
5488         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5489         int i, err, conf_vsis, j, loop;
5490         struct i40e_vsi *vsi;
5491         struct i40e_vmdq_info *vmdq_info;
5492         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5493         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5494
5495         /*
5496          * Disable interrupt to avoid message from VF. Furthermore, it will
5497          * avoid race condition in VSI creation/destroy.
5498          */
5499         i40e_pf_disable_irq0(hw);
5500
5501         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5502                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5503                 return -ENOTSUP;
5504         }
5505
5506         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5507         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5508                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5509                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5510                         pf->max_nb_vmdq_vsi);
5511                 return -ENOTSUP;
5512         }
5513
5514         if (pf->vmdq != NULL) {
5515                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5516                 return 0;
5517         }
5518
5519         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5520                                 sizeof(*vmdq_info) * conf_vsis, 0);
5521
5522         if (pf->vmdq == NULL) {
5523                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5524                 return -ENOMEM;
5525         }
5526
5527         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5528
5529         /* Create VMDQ VSI */
5530         for (i = 0; i < conf_vsis; i++) {
5531                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5532                                 vmdq_conf->enable_loop_back);
5533                 if (vsi == NULL) {
5534                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5535                         err = -1;
5536                         goto err_vsi_setup;
5537                 }
5538                 vmdq_info = &pf->vmdq[i];
5539                 vmdq_info->pf = pf;
5540                 vmdq_info->vsi = vsi;
5541         }
5542         pf->nb_cfg_vmdq_vsi = conf_vsis;
5543
5544         /* Configure Vlan */
5545         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5546         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5547                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5548                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5549                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5550                                         vmdq_conf->pool_map[i].vlan_id, j);
5551
5552                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5553                                                 vmdq_conf->pool_map[i].vlan_id);
5554                                 if (err) {
5555                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5556                                         err = -1;
5557                                         goto err_vsi_setup;
5558                                 }
5559                         }
5560                 }
5561         }
5562
5563         i40e_pf_enable_irq0(hw);
5564
5565         return 0;
5566
5567 err_vsi_setup:
5568         for (i = 0; i < conf_vsis; i++)
5569                 if (pf->vmdq[i].vsi == NULL)
5570                         break;
5571                 else
5572                         i40e_vsi_release(pf->vmdq[i].vsi);
5573
5574         rte_free(pf->vmdq);
5575         pf->vmdq = NULL;
5576         i40e_pf_enable_irq0(hw);
5577         return err;
5578 }
5579
5580 static void
5581 i40e_stat_update_32(struct i40e_hw *hw,
5582                    uint32_t reg,
5583                    bool offset_loaded,
5584                    uint64_t *offset,
5585                    uint64_t *stat)
5586 {
5587         uint64_t new_data;
5588
5589         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5590         if (!offset_loaded)
5591                 *offset = new_data;
5592
5593         if (new_data >= *offset)
5594                 *stat = (uint64_t)(new_data - *offset);
5595         else
5596                 *stat = (uint64_t)((new_data +
5597                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5598 }
5599
5600 static void
5601 i40e_stat_update_48(struct i40e_hw *hw,
5602                    uint32_t hireg,
5603                    uint32_t loreg,
5604                    bool offset_loaded,
5605                    uint64_t *offset,
5606                    uint64_t *stat)
5607 {
5608         uint64_t new_data;
5609
5610         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5611         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5612                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5613
5614         if (!offset_loaded)
5615                 *offset = new_data;
5616
5617         if (new_data >= *offset)
5618                 *stat = new_data - *offset;
5619         else
5620                 *stat = (uint64_t)((new_data +
5621                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5622
5623         *stat &= I40E_48_BIT_MASK;
5624 }
5625
5626 /* Disable IRQ0 */
5627 void
5628 i40e_pf_disable_irq0(struct i40e_hw *hw)
5629 {
5630         /* Disable all interrupt types */
5631         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5632         I40E_WRITE_FLUSH(hw);
5633 }
5634
5635 /* Enable IRQ0 */
5636 void
5637 i40e_pf_enable_irq0(struct i40e_hw *hw)
5638 {
5639         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5640                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5641                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5642                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5643         I40E_WRITE_FLUSH(hw);
5644 }
5645
5646 static void
5647 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5648 {
5649         /* read pending request and disable first */
5650         i40e_pf_disable_irq0(hw);
5651         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5652         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5653                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5654
5655         if (no_queue)
5656                 /* Link no queues with irq0 */
5657                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5658                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5659 }
5660
5661 static void
5662 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5663 {
5664         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5666         int i;
5667         uint16_t abs_vf_id;
5668         uint32_t index, offset, val;
5669
5670         if (!pf->vfs)
5671                 return;
5672         /**
5673          * Try to find which VF trigger a reset, use absolute VF id to access
5674          * since the reg is global register.
5675          */
5676         for (i = 0; i < pf->vf_num; i++) {
5677                 abs_vf_id = hw->func_caps.vf_base_id + i;
5678                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5679                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5680                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5681                 /* VFR event occured */
5682                 if (val & (0x1 << offset)) {
5683                         int ret;
5684
5685                         /* Clear the event first */
5686                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5687                                                         (0x1 << offset));
5688                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5689                         /**
5690                          * Only notify a VF reset event occured,
5691                          * don't trigger another SW reset
5692                          */
5693                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5694                         if (ret != I40E_SUCCESS)
5695                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5696                 }
5697         }
5698 }
5699
5700 static void
5701 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5702 {
5703         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5704         struct i40e_virtchnl_pf_event event;
5705         int i;
5706
5707         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5708         event.event_data.link_event.link_status =
5709                 dev->data->dev_link.link_status;
5710         event.event_data.link_event.link_speed =
5711                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5712
5713         for (i = 0; i < pf->vf_num; i++)
5714                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5715                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5716 }
5717
5718 static void
5719 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5720 {
5721         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5722         struct i40e_arq_event_info info;
5723         uint16_t pending, opcode;
5724         int ret;
5725
5726         info.buf_len = I40E_AQ_BUF_SZ;
5727         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5728         if (!info.msg_buf) {
5729                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5730                 return;
5731         }
5732
5733         pending = 1;
5734         while (pending) {
5735                 ret = i40e_clean_arq_element(hw, &info, &pending);
5736
5737                 if (ret != I40E_SUCCESS) {
5738                         PMD_DRV_LOG(INFO,
5739                                 "Failed to read msg from AdminQ, aq_err: %u",
5740                                 hw->aq.asq_last_status);
5741                         break;
5742                 }
5743                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5744
5745                 switch (opcode) {
5746                 case i40e_aqc_opc_send_msg_to_pf:
5747                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5748                         i40e_pf_host_handle_vf_msg(dev,
5749                                         rte_le_to_cpu_16(info.desc.retval),
5750                                         rte_le_to_cpu_32(info.desc.cookie_high),
5751                                         rte_le_to_cpu_32(info.desc.cookie_low),
5752                                         info.msg_buf,
5753                                         info.msg_len);
5754                         break;
5755                 case i40e_aqc_opc_get_link_status:
5756                         ret = i40e_dev_link_update(dev, 0);
5757                         if (!ret) {
5758                                 i40e_notify_all_vfs_link_status(dev);
5759                                 _rte_eth_dev_callback_process(dev,
5760                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5761                         }
5762                         break;
5763                 default:
5764                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5765                                     opcode);
5766                         break;
5767                 }
5768         }
5769         rte_free(info.msg_buf);
5770 }
5771
5772 /**
5773  * Interrupt handler triggered by NIC  for handling
5774  * specific interrupt.
5775  *
5776  * @param handle
5777  *  Pointer to interrupt handle.
5778  * @param param
5779  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5780  *
5781  * @return
5782  *  void
5783  */
5784 static void
5785 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5786                            void *param)
5787 {
5788         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5790         uint32_t icr0;
5791
5792         /* Disable interrupt */
5793         i40e_pf_disable_irq0(hw);
5794
5795         /* read out interrupt causes */
5796         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5797
5798         /* No interrupt event indicated */
5799         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5800                 PMD_DRV_LOG(INFO, "No interrupt event");
5801                 goto done;
5802         }
5803 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5804         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5805                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5806         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5807                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5808         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5809                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5810         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5811                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5812         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5813                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5814         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5815                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5816         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5817                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5818 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5819
5820         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5821                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5822                 i40e_dev_handle_vfr_event(dev);
5823         }
5824         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5825                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5826                 i40e_dev_handle_aq_msg(dev);
5827         }
5828
5829 done:
5830         /* Enable interrupt */
5831         i40e_pf_enable_irq0(hw);
5832         rte_intr_enable(intr_handle);
5833 }
5834
5835 static int
5836 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5837                          struct i40e_macvlan_filter *filter,
5838                          int total)
5839 {
5840         int ele_num, ele_buff_size;
5841         int num, actual_num, i;
5842         uint16_t flags;
5843         int ret = I40E_SUCCESS;
5844         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5845         struct i40e_aqc_add_macvlan_element_data *req_list;
5846
5847         if (filter == NULL  || total == 0)
5848                 return I40E_ERR_PARAM;
5849         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5850         ele_buff_size = hw->aq.asq_buf_size;
5851
5852         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5853         if (req_list == NULL) {
5854                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5855                 return I40E_ERR_NO_MEMORY;
5856         }
5857
5858         num = 0;
5859         do {
5860                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5861                 memset(req_list, 0, ele_buff_size);
5862
5863                 for (i = 0; i < actual_num; i++) {
5864                         (void)rte_memcpy(req_list[i].mac_addr,
5865                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5866                         req_list[i].vlan_tag =
5867                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5868
5869                         switch (filter[num + i].filter_type) {
5870                         case RTE_MAC_PERFECT_MATCH:
5871                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5872                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5873                                 break;
5874                         case RTE_MACVLAN_PERFECT_MATCH:
5875                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5876                                 break;
5877                         case RTE_MAC_HASH_MATCH:
5878                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5879                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5880                                 break;
5881                         case RTE_MACVLAN_HASH_MATCH:
5882                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5883                                 break;
5884                         default:
5885                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5886                                 ret = I40E_ERR_PARAM;
5887                                 goto DONE;
5888                         }
5889
5890                         req_list[i].queue_number = 0;
5891
5892                         req_list[i].flags = rte_cpu_to_le_16(flags);
5893                 }
5894
5895                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5896                                                 actual_num, NULL);
5897                 if (ret != I40E_SUCCESS) {
5898                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5899                         goto DONE;
5900                 }
5901                 num += actual_num;
5902         } while (num < total);
5903
5904 DONE:
5905         rte_free(req_list);
5906         return ret;
5907 }
5908
5909 static int
5910 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5911                             struct i40e_macvlan_filter *filter,
5912                             int total)
5913 {
5914         int ele_num, ele_buff_size;
5915         int num, actual_num, i;
5916         uint16_t flags;
5917         int ret = I40E_SUCCESS;
5918         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5919         struct i40e_aqc_remove_macvlan_element_data *req_list;
5920
5921         if (filter == NULL  || total == 0)
5922                 return I40E_ERR_PARAM;
5923
5924         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5925         ele_buff_size = hw->aq.asq_buf_size;
5926
5927         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5928         if (req_list == NULL) {
5929                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5930                 return I40E_ERR_NO_MEMORY;
5931         }
5932
5933         num = 0;
5934         do {
5935                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5936                 memset(req_list, 0, ele_buff_size);
5937
5938                 for (i = 0; i < actual_num; i++) {
5939                         (void)rte_memcpy(req_list[i].mac_addr,
5940                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5941                         req_list[i].vlan_tag =
5942                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5943
5944                         switch (filter[num + i].filter_type) {
5945                         case RTE_MAC_PERFECT_MATCH:
5946                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5947                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5948                                 break;
5949                         case RTE_MACVLAN_PERFECT_MATCH:
5950                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5951                                 break;
5952                         case RTE_MAC_HASH_MATCH:
5953                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5954                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5955                                 break;
5956                         case RTE_MACVLAN_HASH_MATCH:
5957                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5958                                 break;
5959                         default:
5960                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5961                                 ret = I40E_ERR_PARAM;
5962                                 goto DONE;
5963                         }
5964                         req_list[i].flags = rte_cpu_to_le_16(flags);
5965                 }
5966
5967                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5968                                                 actual_num, NULL);
5969                 if (ret != I40E_SUCCESS) {
5970                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5971                         goto DONE;
5972                 }
5973                 num += actual_num;
5974         } while (num < total);
5975
5976 DONE:
5977         rte_free(req_list);
5978         return ret;
5979 }
5980
5981 /* Find out specific MAC filter */
5982 static struct i40e_mac_filter *
5983 i40e_find_mac_filter(struct i40e_vsi *vsi,
5984                          struct ether_addr *macaddr)
5985 {
5986         struct i40e_mac_filter *f;
5987
5988         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5989                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5990                         return f;
5991         }
5992
5993         return NULL;
5994 }
5995
5996 static bool
5997 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5998                          uint16_t vlan_id)
5999 {
6000         uint32_t vid_idx, vid_bit;
6001
6002         if (vlan_id > ETH_VLAN_ID_MAX)
6003                 return 0;
6004
6005         vid_idx = I40E_VFTA_IDX(vlan_id);
6006         vid_bit = I40E_VFTA_BIT(vlan_id);
6007
6008         if (vsi->vfta[vid_idx] & vid_bit)
6009                 return 1;
6010         else
6011                 return 0;
6012 }
6013
6014 static void
6015 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6016                        uint16_t vlan_id, bool on)
6017 {
6018         uint32_t vid_idx, vid_bit;
6019
6020         vid_idx = I40E_VFTA_IDX(vlan_id);
6021         vid_bit = I40E_VFTA_BIT(vlan_id);
6022
6023         if (on)
6024                 vsi->vfta[vid_idx] |= vid_bit;
6025         else
6026                 vsi->vfta[vid_idx] &= ~vid_bit;
6027 }
6028
6029 static void
6030 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6031                      uint16_t vlan_id, bool on)
6032 {
6033         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6034         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6035         int ret;
6036
6037         if (vlan_id > ETH_VLAN_ID_MAX)
6038                 return;
6039
6040         i40e_store_vlan_filter(vsi, vlan_id, on);
6041
6042         if (!vsi->vlan_anti_spoof_on || !vlan_id)
6043                 return;
6044
6045         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6046
6047         if (on) {
6048                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6049                                        &vlan_data, 1, NULL);
6050                 if (ret != I40E_SUCCESS)
6051                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6052         } else {
6053                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6054                                           &vlan_data, 1, NULL);
6055                 if (ret != I40E_SUCCESS)
6056                         PMD_DRV_LOG(ERR,
6057                                     "Failed to remove vlan filter");
6058         }
6059 }
6060
6061 /**
6062  * Find all vlan options for specific mac addr,
6063  * return with actual vlan found.
6064  */
6065 static inline int
6066 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6067                            struct i40e_macvlan_filter *mv_f,
6068                            int num, struct ether_addr *addr)
6069 {
6070         int i;
6071         uint32_t j, k;
6072
6073         /**
6074          * Not to use i40e_find_vlan_filter to decrease the loop time,
6075          * although the code looks complex.
6076           */
6077         if (num < vsi->vlan_num)
6078                 return I40E_ERR_PARAM;
6079
6080         i = 0;
6081         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6082                 if (vsi->vfta[j]) {
6083                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6084                                 if (vsi->vfta[j] & (1 << k)) {
6085                                         if (i > num - 1) {
6086                                                 PMD_DRV_LOG(ERR,
6087                                                         "vlan number doesn't match");
6088                                                 return I40E_ERR_PARAM;
6089                                         }
6090                                         (void)rte_memcpy(&mv_f[i].macaddr,
6091                                                         addr, ETH_ADDR_LEN);
6092                                         mv_f[i].vlan_id =
6093                                                 j * I40E_UINT32_BIT_SIZE + k;
6094                                         i++;
6095                                 }
6096                         }
6097                 }
6098         }
6099         return I40E_SUCCESS;
6100 }
6101
6102 static inline int
6103 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6104                            struct i40e_macvlan_filter *mv_f,
6105                            int num,
6106                            uint16_t vlan)
6107 {
6108         int i = 0;
6109         struct i40e_mac_filter *f;
6110
6111         if (num < vsi->mac_num)
6112                 return I40E_ERR_PARAM;
6113
6114         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6115                 if (i > num - 1) {
6116                         PMD_DRV_LOG(ERR, "buffer number not match");
6117                         return I40E_ERR_PARAM;
6118                 }
6119                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6120                                 ETH_ADDR_LEN);
6121                 mv_f[i].vlan_id = vlan;
6122                 mv_f[i].filter_type = f->mac_info.filter_type;
6123                 i++;
6124         }
6125
6126         return I40E_SUCCESS;
6127 }
6128
6129 static int
6130 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6131 {
6132         int i, j, num;
6133         struct i40e_mac_filter *f;
6134         struct i40e_macvlan_filter *mv_f;
6135         int ret = I40E_SUCCESS;
6136
6137         if (vsi == NULL || vsi->mac_num == 0)
6138                 return I40E_ERR_PARAM;
6139
6140         /* Case that no vlan is set */
6141         if (vsi->vlan_num == 0)
6142                 num = vsi->mac_num;
6143         else
6144                 num = vsi->mac_num * vsi->vlan_num;
6145
6146         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6147         if (mv_f == NULL) {
6148                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6149                 return I40E_ERR_NO_MEMORY;
6150         }
6151
6152         i = 0;
6153         if (vsi->vlan_num == 0) {
6154                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6155                         (void)rte_memcpy(&mv_f[i].macaddr,
6156                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6157                         mv_f[i].filter_type = f->mac_info.filter_type;
6158                         mv_f[i].vlan_id = 0;
6159                         i++;
6160                 }
6161         } else {
6162                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6163                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6164                                         vsi->vlan_num, &f->mac_info.mac_addr);
6165                         if (ret != I40E_SUCCESS)
6166                                 goto DONE;
6167                         for (j = i; j < i + vsi->vlan_num; j++)
6168                                 mv_f[j].filter_type = f->mac_info.filter_type;
6169                         i += vsi->vlan_num;
6170                 }
6171         }
6172
6173         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6174 DONE:
6175         rte_free(mv_f);
6176
6177         return ret;
6178 }
6179
6180 int
6181 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6182 {
6183         struct i40e_macvlan_filter *mv_f;
6184         int mac_num;
6185         int ret = I40E_SUCCESS;
6186
6187         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6188                 return I40E_ERR_PARAM;
6189
6190         /* If it's already set, just return */
6191         if (i40e_find_vlan_filter(vsi,vlan))
6192                 return I40E_SUCCESS;
6193
6194         mac_num = vsi->mac_num;
6195
6196         if (mac_num == 0) {
6197                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6198                 return I40E_ERR_PARAM;
6199         }
6200
6201         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6202
6203         if (mv_f == NULL) {
6204                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6205                 return I40E_ERR_NO_MEMORY;
6206         }
6207
6208         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6209
6210         if (ret != I40E_SUCCESS)
6211                 goto DONE;
6212
6213         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6214
6215         if (ret != I40E_SUCCESS)
6216                 goto DONE;
6217
6218         i40e_set_vlan_filter(vsi, vlan, 1);
6219
6220         vsi->vlan_num++;
6221         ret = I40E_SUCCESS;
6222 DONE:
6223         rte_free(mv_f);
6224         return ret;
6225 }
6226
6227 int
6228 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6229 {
6230         struct i40e_macvlan_filter *mv_f;
6231         int mac_num;
6232         int ret = I40E_SUCCESS;
6233
6234         /**
6235          * Vlan 0 is the generic filter for untagged packets
6236          * and can't be removed.
6237          */
6238         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6239                 return I40E_ERR_PARAM;
6240
6241         /* If can't find it, just return */
6242         if (!i40e_find_vlan_filter(vsi, vlan))
6243                 return I40E_ERR_PARAM;
6244
6245         mac_num = vsi->mac_num;
6246
6247         if (mac_num == 0) {
6248                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6249                 return I40E_ERR_PARAM;
6250         }
6251
6252         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6253
6254         if (mv_f == NULL) {
6255                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6256                 return I40E_ERR_NO_MEMORY;
6257         }
6258
6259         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6260
6261         if (ret != I40E_SUCCESS)
6262                 goto DONE;
6263
6264         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6265
6266         if (ret != I40E_SUCCESS)
6267                 goto DONE;
6268
6269         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6270         if (vsi->vlan_num == 1) {
6271                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6272                 if (ret != I40E_SUCCESS)
6273                         goto DONE;
6274
6275                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6276                 if (ret != I40E_SUCCESS)
6277                         goto DONE;
6278         }
6279
6280         i40e_set_vlan_filter(vsi, vlan, 0);
6281
6282         vsi->vlan_num--;
6283         ret = I40E_SUCCESS;
6284 DONE:
6285         rte_free(mv_f);
6286         return ret;
6287 }
6288
6289 int
6290 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6291 {
6292         struct i40e_mac_filter *f;
6293         struct i40e_macvlan_filter *mv_f;
6294         int i, vlan_num = 0;
6295         int ret = I40E_SUCCESS;
6296
6297         /* If it's add and we've config it, return */
6298         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6299         if (f != NULL)
6300                 return I40E_SUCCESS;
6301         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6302                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6303
6304                 /**
6305                  * If vlan_num is 0, that's the first time to add mac,
6306                  * set mask for vlan_id 0.
6307                  */
6308                 if (vsi->vlan_num == 0) {
6309                         i40e_set_vlan_filter(vsi, 0, 1);
6310                         vsi->vlan_num = 1;
6311                 }
6312                 vlan_num = vsi->vlan_num;
6313         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6314                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6315                 vlan_num = 1;
6316
6317         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6318         if (mv_f == NULL) {
6319                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6320                 return I40E_ERR_NO_MEMORY;
6321         }
6322
6323         for (i = 0; i < vlan_num; i++) {
6324                 mv_f[i].filter_type = mac_filter->filter_type;
6325                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6326                                 ETH_ADDR_LEN);
6327         }
6328
6329         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6330                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6331                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6332                                         &mac_filter->mac_addr);
6333                 if (ret != I40E_SUCCESS)
6334                         goto DONE;
6335         }
6336
6337         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6338         if (ret != I40E_SUCCESS)
6339                 goto DONE;
6340
6341         /* Add the mac addr into mac list */
6342         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6343         if (f == NULL) {
6344                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6345                 ret = I40E_ERR_NO_MEMORY;
6346                 goto DONE;
6347         }
6348         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6349                         ETH_ADDR_LEN);
6350         f->mac_info.filter_type = mac_filter->filter_type;
6351         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6352         vsi->mac_num++;
6353
6354         ret = I40E_SUCCESS;
6355 DONE:
6356         rte_free(mv_f);
6357
6358         return ret;
6359 }
6360
6361 int
6362 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6363 {
6364         struct i40e_mac_filter *f;
6365         struct i40e_macvlan_filter *mv_f;
6366         int i, vlan_num;
6367         enum rte_mac_filter_type filter_type;
6368         int ret = I40E_SUCCESS;
6369
6370         /* Can't find it, return an error */
6371         f = i40e_find_mac_filter(vsi, addr);
6372         if (f == NULL)
6373                 return I40E_ERR_PARAM;
6374
6375         vlan_num = vsi->vlan_num;
6376         filter_type = f->mac_info.filter_type;
6377         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6378                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6379                 if (vlan_num == 0) {
6380                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6381                         return I40E_ERR_PARAM;
6382                 }
6383         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6384                         filter_type == RTE_MAC_HASH_MATCH)
6385                 vlan_num = 1;
6386
6387         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6388         if (mv_f == NULL) {
6389                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6390                 return I40E_ERR_NO_MEMORY;
6391         }
6392
6393         for (i = 0; i < vlan_num; i++) {
6394                 mv_f[i].filter_type = filter_type;
6395                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6396                                 ETH_ADDR_LEN);
6397         }
6398         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6399                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6400                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6401                 if (ret != I40E_SUCCESS)
6402                         goto DONE;
6403         }
6404
6405         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6406         if (ret != I40E_SUCCESS)
6407                 goto DONE;
6408
6409         /* Remove the mac addr into mac list */
6410         TAILQ_REMOVE(&vsi->mac_list, f, next);
6411         rte_free(f);
6412         vsi->mac_num--;
6413
6414         ret = I40E_SUCCESS;
6415 DONE:
6416         rte_free(mv_f);
6417         return ret;
6418 }
6419
6420 /* Configure hash enable flags for RSS */
6421 uint64_t
6422 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6423 {
6424         uint64_t hena = 0;
6425
6426         if (!flags)
6427                 return hena;
6428
6429         if (flags & ETH_RSS_FRAG_IPV4)
6430                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6431         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6432                 if (type == I40E_MAC_X722) {
6433                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6434                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6435                 } else
6436                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6437         }
6438         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6439                 if (type == I40E_MAC_X722) {
6440                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6441                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6442                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6443                 } else
6444                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6445         }
6446         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6447                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6448         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6449                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6450         if (flags & ETH_RSS_FRAG_IPV6)
6451                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6452         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6453                 if (type == I40E_MAC_X722) {
6454                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6455                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6456                 } else
6457                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6458         }
6459         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6460                 if (type == I40E_MAC_X722) {
6461                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6462                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6463                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6464                 } else
6465                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6466         }
6467         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6468                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6469         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6470                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6471         if (flags & ETH_RSS_L2_PAYLOAD)
6472                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6473
6474         return hena;
6475 }
6476
6477 /* Parse the hash enable flags */
6478 uint64_t
6479 i40e_parse_hena(uint64_t flags)
6480 {
6481         uint64_t rss_hf = 0;
6482
6483         if (!flags)
6484                 return rss_hf;
6485         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6486                 rss_hf |= ETH_RSS_FRAG_IPV4;
6487         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6488                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6489         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6490                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6491         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6492                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6493         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6494                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6495         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6496                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6497         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6498                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6499         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6500                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6501         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6502                 rss_hf |= ETH_RSS_FRAG_IPV6;
6503         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6504                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6505         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6506                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6507         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6508                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6509         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6510                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6511         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6512                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6513         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6514                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6515         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6516                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6517         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6518                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6519
6520         return rss_hf;
6521 }
6522
6523 /* Disable RSS */
6524 static void
6525 i40e_pf_disable_rss(struct i40e_pf *pf)
6526 {
6527         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6528         uint64_t hena;
6529
6530         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6531         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6532         if (hw->mac.type == I40E_MAC_X722)
6533                 hena &= ~I40E_RSS_HENA_ALL_X722;
6534         else
6535                 hena &= ~I40E_RSS_HENA_ALL;
6536         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6537         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6538         I40E_WRITE_FLUSH(hw);
6539 }
6540
6541 static int
6542 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6543 {
6544         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6545         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6546         int ret = 0;
6547
6548         if (!key || key_len == 0) {
6549                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6550                 return 0;
6551         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6552                 sizeof(uint32_t)) {
6553                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6554                 return -EINVAL;
6555         }
6556
6557         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6558                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6559                         (struct i40e_aqc_get_set_rss_key_data *)key;
6560
6561                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6562                 if (ret)
6563                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6564         } else {
6565                 uint32_t *hash_key = (uint32_t *)key;
6566                 uint16_t i;
6567
6568                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6569                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6570                 I40E_WRITE_FLUSH(hw);
6571         }
6572
6573         return ret;
6574 }
6575
6576 static int
6577 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6578 {
6579         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6580         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6581         int ret;
6582
6583         if (!key || !key_len)
6584                 return -EINVAL;
6585
6586         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6587                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6588                         (struct i40e_aqc_get_set_rss_key_data *)key);
6589                 if (ret) {
6590                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6591                         return ret;
6592                 }
6593         } else {
6594                 uint32_t *key_dw = (uint32_t *)key;
6595                 uint16_t i;
6596
6597                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6598                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6599         }
6600         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6601
6602         return 0;
6603 }
6604
6605 static int
6606 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6607 {
6608         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6609         uint64_t rss_hf;
6610         uint64_t hena;
6611         int ret;
6612
6613         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6614                                rss_conf->rss_key_len);
6615         if (ret)
6616                 return ret;
6617
6618         rss_hf = rss_conf->rss_hf;
6619         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6620         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6621         if (hw->mac.type == I40E_MAC_X722)
6622                 hena &= ~I40E_RSS_HENA_ALL_X722;
6623         else
6624                 hena &= ~I40E_RSS_HENA_ALL;
6625         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6626         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6627         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6628         I40E_WRITE_FLUSH(hw);
6629
6630         return 0;
6631 }
6632
6633 static int
6634 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6635                          struct rte_eth_rss_conf *rss_conf)
6636 {
6637         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6638         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6639         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6640         uint64_t hena;
6641
6642         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6643         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6644         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6645                  ? I40E_RSS_HENA_ALL_X722
6646                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6647                 if (rss_hf != 0) /* Enable RSS */
6648                         return -EINVAL;
6649                 return 0; /* Nothing to do */
6650         }
6651         /* RSS enabled */
6652         if (rss_hf == 0) /* Disable RSS */
6653                 return -EINVAL;
6654
6655         return i40e_hw_rss_hash_set(pf, rss_conf);
6656 }
6657
6658 static int
6659 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6660                            struct rte_eth_rss_conf *rss_conf)
6661 {
6662         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6663         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6664         uint64_t hena;
6665
6666         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6667                          &rss_conf->rss_key_len);
6668
6669         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6670         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6671         rss_conf->rss_hf = i40e_parse_hena(hena);
6672
6673         return 0;
6674 }
6675
6676 static int
6677 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6678 {
6679         switch (filter_type) {
6680         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6681                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6682                 break;
6683         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6684                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6685                 break;
6686         case RTE_TUNNEL_FILTER_IMAC_TENID:
6687                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6688                 break;
6689         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6690                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6691                 break;
6692         case ETH_TUNNEL_FILTER_IMAC:
6693                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6694                 break;
6695         case ETH_TUNNEL_FILTER_OIP:
6696                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6697                 break;
6698         case ETH_TUNNEL_FILTER_IIP:
6699                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6700                 break;
6701         default:
6702                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6703                 return -EINVAL;
6704         }
6705
6706         return 0;
6707 }
6708
6709 /* Convert tunnel filter structure */
6710 static int
6711 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6712                            *cld_filter,
6713                            struct i40e_tunnel_filter *tunnel_filter)
6714 {
6715         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6716                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6717         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6718                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6719         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6720         if ((rte_le_to_cpu_16(cld_filter->flags) &
6721              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6722             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6723                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6724         else
6725                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6726         tunnel_filter->input.flags = cld_filter->flags;
6727         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6728         tunnel_filter->queue = cld_filter->queue_number;
6729
6730         return 0;
6731 }
6732
6733 /* Check if there exists the tunnel filter */
6734 struct i40e_tunnel_filter *
6735 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6736                              const struct i40e_tunnel_filter_input *input)
6737 {
6738         int ret;
6739
6740         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6741         if (ret < 0)
6742                 return NULL;
6743
6744         return tunnel_rule->hash_map[ret];
6745 }
6746
6747 /* Add a tunnel filter into the SW list */
6748 static int
6749 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6750                              struct i40e_tunnel_filter *tunnel_filter)
6751 {
6752         struct i40e_tunnel_rule *rule = &pf->tunnel;
6753         int ret;
6754
6755         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6756         if (ret < 0) {
6757                 PMD_DRV_LOG(ERR,
6758                             "Failed to insert tunnel filter to hash table %d!",
6759                             ret);
6760                 return ret;
6761         }
6762         rule->hash_map[ret] = tunnel_filter;
6763
6764         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6765
6766         return 0;
6767 }
6768
6769 /* Delete a tunnel filter from the SW list */
6770 int
6771 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6772                           struct i40e_tunnel_filter_input *input)
6773 {
6774         struct i40e_tunnel_rule *rule = &pf->tunnel;
6775         struct i40e_tunnel_filter *tunnel_filter;
6776         int ret;
6777
6778         ret = rte_hash_del_key(rule->hash_table, input);
6779         if (ret < 0) {
6780                 PMD_DRV_LOG(ERR,
6781                             "Failed to delete tunnel filter to hash table %d!",
6782                             ret);
6783                 return ret;
6784         }
6785         tunnel_filter = rule->hash_map[ret];
6786         rule->hash_map[ret] = NULL;
6787
6788         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6789         rte_free(tunnel_filter);
6790
6791         return 0;
6792 }
6793
6794 int
6795 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6796                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6797                         uint8_t add)
6798 {
6799         uint16_t ip_type;
6800         uint32_t ipv4_addr;
6801         uint8_t i, tun_type = 0;
6802         /* internal varialbe to convert ipv6 byte order */
6803         uint32_t convert_ipv6[4];
6804         int val, ret = 0;
6805         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6806         struct i40e_vsi *vsi = pf->main_vsi;
6807         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6808         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6809         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6810         struct i40e_tunnel_filter *tunnel, *node;
6811         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6812
6813         cld_filter = rte_zmalloc("tunnel_filter",
6814                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6815                 0);
6816
6817         if (NULL == cld_filter) {
6818                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6819                 return -EINVAL;
6820         }
6821         pfilter = cld_filter;
6822
6823         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6824         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6825
6826         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6827         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6828                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6829                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6830                 rte_memcpy(&pfilter->ipaddr.v4.data,
6831                                 &rte_cpu_to_le_32(ipv4_addr),
6832                                 sizeof(pfilter->ipaddr.v4.data));
6833         } else {
6834                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6835                 for (i = 0; i < 4; i++) {
6836                         convert_ipv6[i] =
6837                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6838                 }
6839                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6840                                 sizeof(pfilter->ipaddr.v6.data));
6841         }
6842
6843         /* check tunneled type */
6844         switch (tunnel_filter->tunnel_type) {
6845         case RTE_TUNNEL_TYPE_VXLAN:
6846                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6847                 break;
6848         case RTE_TUNNEL_TYPE_NVGRE:
6849                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6850                 break;
6851         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6852                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6853                 break;
6854         default:
6855                 /* Other tunnel types is not supported. */
6856                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6857                 rte_free(cld_filter);
6858                 return -EINVAL;
6859         }
6860
6861         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6862                                                 &pfilter->flags);
6863         if (val < 0) {
6864                 rte_free(cld_filter);
6865                 return -EINVAL;
6866         }
6867
6868         pfilter->flags |= rte_cpu_to_le_16(
6869                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6870                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6871         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6872         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6873
6874         /* Check if there is the filter in SW list */
6875         memset(&check_filter, 0, sizeof(check_filter));
6876         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6877         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6878         if (add && node) {
6879                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6880                 return -EINVAL;
6881         }
6882
6883         if (!add && !node) {
6884                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6885                 return -EINVAL;
6886         }
6887
6888         if (add) {
6889                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6890                 if (ret < 0) {
6891                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6892                         return ret;
6893                 }
6894                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6895                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6896                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6897         } else {
6898                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6899                                                    cld_filter, 1);
6900                 if (ret < 0) {
6901                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6902                         return ret;
6903                 }
6904                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6905         }
6906
6907         rte_free(cld_filter);
6908         return ret;
6909 }
6910
6911 static int
6912 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6913 {
6914         uint8_t i;
6915
6916         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6917                 if (pf->vxlan_ports[i] == port)
6918                         return i;
6919         }
6920
6921         return -1;
6922 }
6923
6924 static int
6925 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6926 {
6927         int  idx, ret;
6928         uint8_t filter_idx;
6929         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6930
6931         idx = i40e_get_vxlan_port_idx(pf, port);
6932
6933         /* Check if port already exists */
6934         if (idx >= 0) {
6935                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6936                 return -EINVAL;
6937         }
6938
6939         /* Now check if there is space to add the new port */
6940         idx = i40e_get_vxlan_port_idx(pf, 0);
6941         if (idx < 0) {
6942                 PMD_DRV_LOG(ERR,
6943                         "Maximum number of UDP ports reached, not adding port %d",
6944                         port);
6945                 return -ENOSPC;
6946         }
6947
6948         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6949                                         &filter_idx, NULL);
6950         if (ret < 0) {
6951                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6952                 return -1;
6953         }
6954
6955         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6956                          port,  filter_idx);
6957
6958         /* New port: add it and mark its index in the bitmap */
6959         pf->vxlan_ports[idx] = port;
6960         pf->vxlan_bitmap |= (1 << idx);
6961
6962         if (!(pf->flags & I40E_FLAG_VXLAN))
6963                 pf->flags |= I40E_FLAG_VXLAN;
6964
6965         return 0;
6966 }
6967
6968 static int
6969 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6970 {
6971         int idx;
6972         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6973
6974         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6975                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6976                 return -EINVAL;
6977         }
6978
6979         idx = i40e_get_vxlan_port_idx(pf, port);
6980
6981         if (idx < 0) {
6982                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6983                 return -EINVAL;
6984         }
6985
6986         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6987                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6988                 return -1;
6989         }
6990
6991         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6992                         port, idx);
6993
6994         pf->vxlan_ports[idx] = 0;
6995         pf->vxlan_bitmap &= ~(1 << idx);
6996
6997         if (!pf->vxlan_bitmap)
6998                 pf->flags &= ~I40E_FLAG_VXLAN;
6999
7000         return 0;
7001 }
7002
7003 /* Add UDP tunneling port */
7004 static int
7005 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7006                              struct rte_eth_udp_tunnel *udp_tunnel)
7007 {
7008         int ret = 0;
7009         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7010
7011         if (udp_tunnel == NULL)
7012                 return -EINVAL;
7013
7014         switch (udp_tunnel->prot_type) {
7015         case RTE_TUNNEL_TYPE_VXLAN:
7016                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7017                 break;
7018
7019         case RTE_TUNNEL_TYPE_GENEVE:
7020         case RTE_TUNNEL_TYPE_TEREDO:
7021                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7022                 ret = -1;
7023                 break;
7024
7025         default:
7026                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7027                 ret = -1;
7028                 break;
7029         }
7030
7031         return ret;
7032 }
7033
7034 /* Remove UDP tunneling port */
7035 static int
7036 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7037                              struct rte_eth_udp_tunnel *udp_tunnel)
7038 {
7039         int ret = 0;
7040         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7041
7042         if (udp_tunnel == NULL)
7043                 return -EINVAL;
7044
7045         switch (udp_tunnel->prot_type) {
7046         case RTE_TUNNEL_TYPE_VXLAN:
7047                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7048                 break;
7049         case RTE_TUNNEL_TYPE_GENEVE:
7050         case RTE_TUNNEL_TYPE_TEREDO:
7051                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7052                 ret = -1;
7053                 break;
7054         default:
7055                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7056                 ret = -1;
7057                 break;
7058         }
7059
7060         return ret;
7061 }
7062
7063 /* Calculate the maximum number of contiguous PF queues that are configured */
7064 static int
7065 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7066 {
7067         struct rte_eth_dev_data *data = pf->dev_data;
7068         int i, num;
7069         struct i40e_rx_queue *rxq;
7070
7071         num = 0;
7072         for (i = 0; i < pf->lan_nb_qps; i++) {
7073                 rxq = data->rx_queues[i];
7074                 if (rxq && rxq->q_set)
7075                         num++;
7076                 else
7077                         break;
7078         }
7079
7080         return num;
7081 }
7082
7083 /* Configure RSS */
7084 static int
7085 i40e_pf_config_rss(struct i40e_pf *pf)
7086 {
7087         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7088         struct rte_eth_rss_conf rss_conf;
7089         uint32_t i, lut = 0;
7090         uint16_t j, num;
7091
7092         /*
7093          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7094          * It's necessary to calulate the actual PF queues that are configured.
7095          */
7096         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7097                 num = i40e_pf_calc_configured_queues_num(pf);
7098         else
7099                 num = pf->dev_data->nb_rx_queues;
7100
7101         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7102         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7103                         num);
7104
7105         if (num == 0) {
7106                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7107                 return -ENOTSUP;
7108         }
7109
7110         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7111                 if (j == num)
7112                         j = 0;
7113                 lut = (lut << 8) | (j & ((0x1 <<
7114                         hw->func_caps.rss_table_entry_width) - 1));
7115                 if ((i & 3) == 3)
7116                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7117         }
7118
7119         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7120         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7121                 i40e_pf_disable_rss(pf);
7122                 return 0;
7123         }
7124         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7125                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7126                 /* Random default keys */
7127                 static uint32_t rss_key_default[] = {0x6b793944,
7128                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7129                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7130                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7131
7132                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7133                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7134                                                         sizeof(uint32_t);
7135         }
7136
7137         return i40e_hw_rss_hash_set(pf, &rss_conf);
7138 }
7139
7140 static int
7141 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7142                                struct rte_eth_tunnel_filter_conf *filter)
7143 {
7144         if (pf == NULL || filter == NULL) {
7145                 PMD_DRV_LOG(ERR, "Invalid parameter");
7146                 return -EINVAL;
7147         }
7148
7149         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7150                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7151                 return -EINVAL;
7152         }
7153
7154         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7155                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7156                 return -EINVAL;
7157         }
7158
7159         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7160                 (is_zero_ether_addr(&filter->outer_mac))) {
7161                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7162                 return -EINVAL;
7163         }
7164
7165         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7166                 (is_zero_ether_addr(&filter->inner_mac))) {
7167                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7168                 return -EINVAL;
7169         }
7170
7171         return 0;
7172 }
7173
7174 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7175 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7176 static int
7177 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7178 {
7179         uint32_t val, reg;
7180         int ret = -EINVAL;
7181
7182         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7183         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7184
7185         if (len == 3) {
7186                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7187         } else if (len == 4) {
7188                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7189         } else {
7190                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7191                 return ret;
7192         }
7193
7194         if (reg != val) {
7195                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7196                                                    reg, NULL);
7197                 if (ret != 0)
7198                         return ret;
7199         } else {
7200                 ret = 0;
7201         }
7202         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7203                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7204
7205         return ret;
7206 }
7207
7208 static int
7209 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7210 {
7211         int ret = -EINVAL;
7212
7213         if (!hw || !cfg)
7214                 return -EINVAL;
7215
7216         switch (cfg->cfg_type) {
7217         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7218                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7219                 break;
7220         default:
7221                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7222                 break;
7223         }
7224
7225         return ret;
7226 }
7227
7228 static int
7229 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7230                                enum rte_filter_op filter_op,
7231                                void *arg)
7232 {
7233         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7234         int ret = I40E_ERR_PARAM;
7235
7236         switch (filter_op) {
7237         case RTE_ETH_FILTER_SET:
7238                 ret = i40e_dev_global_config_set(hw,
7239                         (struct rte_eth_global_cfg *)arg);
7240                 break;
7241         default:
7242                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7243                 break;
7244         }
7245
7246         return ret;
7247 }
7248
7249 static int
7250 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7251                           enum rte_filter_op filter_op,
7252                           void *arg)
7253 {
7254         struct rte_eth_tunnel_filter_conf *filter;
7255         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7256         int ret = I40E_SUCCESS;
7257
7258         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7259
7260         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7261                 return I40E_ERR_PARAM;
7262
7263         switch (filter_op) {
7264         case RTE_ETH_FILTER_NOP:
7265                 if (!(pf->flags & I40E_FLAG_VXLAN))
7266                         ret = I40E_NOT_SUPPORTED;
7267                 break;
7268         case RTE_ETH_FILTER_ADD:
7269                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7270                 break;
7271         case RTE_ETH_FILTER_DELETE:
7272                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7273                 break;
7274         default:
7275                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7276                 ret = I40E_ERR_PARAM;
7277                 break;
7278         }
7279
7280         return ret;
7281 }
7282
7283 static int
7284 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7285 {
7286         int ret = 0;
7287         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7288
7289         /* RSS setup */
7290         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7291                 ret = i40e_pf_config_rss(pf);
7292         else
7293                 i40e_pf_disable_rss(pf);
7294
7295         return ret;
7296 }
7297
7298 /* Get the symmetric hash enable configurations per port */
7299 static void
7300 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7301 {
7302         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7303
7304         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7305 }
7306
7307 /* Set the symmetric hash enable configurations per port */
7308 static void
7309 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7310 {
7311         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7312
7313         if (enable > 0) {
7314                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7315                         PMD_DRV_LOG(INFO,
7316                                 "Symmetric hash has already been enabled");
7317                         return;
7318                 }
7319                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7320         } else {
7321                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7322                         PMD_DRV_LOG(INFO,
7323                                 "Symmetric hash has already been disabled");
7324                         return;
7325                 }
7326                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7327         }
7328         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7329         I40E_WRITE_FLUSH(hw);
7330 }
7331
7332 /*
7333  * Get global configurations of hash function type and symmetric hash enable
7334  * per flow type (pctype). Note that global configuration means it affects all
7335  * the ports on the same NIC.
7336  */
7337 static int
7338 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7339                                    struct rte_eth_hash_global_conf *g_cfg)
7340 {
7341         uint32_t reg, mask = I40E_FLOW_TYPES;
7342         uint16_t i;
7343         enum i40e_filter_pctype pctype;
7344
7345         memset(g_cfg, 0, sizeof(*g_cfg));
7346         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7347         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7348                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7349         else
7350                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7351         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7352                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7353
7354         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7355                 if (!(mask & (1UL << i)))
7356                         continue;
7357                 mask &= ~(1UL << i);
7358                 /* Bit set indicats the coresponding flow type is supported */
7359                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7360                 /* if flowtype is invalid, continue */
7361                 if (!I40E_VALID_FLOW(i))
7362                         continue;
7363                 pctype = i40e_flowtype_to_pctype(i);
7364                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7365                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7366                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7367         }
7368
7369         return 0;
7370 }
7371
7372 static int
7373 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7374 {
7375         uint32_t i;
7376         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7377
7378         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7379                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7380                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7381                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7382                                                 g_cfg->hash_func);
7383                 return -EINVAL;
7384         }
7385
7386         /*
7387          * As i40e supports less than 32 flow types, only first 32 bits need to
7388          * be checked.
7389          */
7390         mask0 = g_cfg->valid_bit_mask[0];
7391         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7392                 if (i == 0) {
7393                         /* Check if any unsupported flow type configured */
7394                         if ((mask0 | i40e_mask) ^ i40e_mask)
7395                                 goto mask_err;
7396                 } else {
7397                         if (g_cfg->valid_bit_mask[i])
7398                                 goto mask_err;
7399                 }
7400         }
7401
7402         return 0;
7403
7404 mask_err:
7405         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7406
7407         return -EINVAL;
7408 }
7409
7410 /*
7411  * Set global configurations of hash function type and symmetric hash enable
7412  * per flow type (pctype). Note any modifying global configuration will affect
7413  * all the ports on the same NIC.
7414  */
7415 static int
7416 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7417                                    struct rte_eth_hash_global_conf *g_cfg)
7418 {
7419         int ret;
7420         uint16_t i;
7421         uint32_t reg;
7422         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7423         enum i40e_filter_pctype pctype;
7424
7425         /* Check the input parameters */
7426         ret = i40e_hash_global_config_check(g_cfg);
7427         if (ret < 0)
7428                 return ret;
7429
7430         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7431                 if (!(mask0 & (1UL << i)))
7432                         continue;
7433                 mask0 &= ~(1UL << i);
7434                 /* if flowtype is invalid, continue */
7435                 if (!I40E_VALID_FLOW(i))
7436                         continue;
7437                 pctype = i40e_flowtype_to_pctype(i);
7438                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7439                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7440                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7441         }
7442
7443         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7444         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7445                 /* Toeplitz */
7446                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7447                         PMD_DRV_LOG(DEBUG,
7448                                 "Hash function already set to Toeplitz");
7449                         goto out;
7450                 }
7451                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7452         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7453                 /* Simple XOR */
7454                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7455                         PMD_DRV_LOG(DEBUG,
7456                                 "Hash function already set to Simple XOR");
7457                         goto out;
7458                 }
7459                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7460         } else
7461                 /* Use the default, and keep it as it is */
7462                 goto out;
7463
7464         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7465
7466 out:
7467         I40E_WRITE_FLUSH(hw);
7468
7469         return 0;
7470 }
7471
7472 /**
7473  * Valid input sets for hash and flow director filters per PCTYPE
7474  */
7475 static uint64_t
7476 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7477                 enum rte_filter_type filter)
7478 {
7479         uint64_t valid;
7480
7481         static const uint64_t valid_hash_inset_table[] = {
7482                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7483                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7484                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7485                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7486                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7487                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7488                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7489                         I40E_INSET_FLEX_PAYLOAD,
7490                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7491                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7492                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7493                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7494                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7495                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7496                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7497                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7498                         I40E_INSET_FLEX_PAYLOAD,
7499                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7500                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7501                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7502                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7503                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7504                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7505                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7506                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7507                         I40E_INSET_FLEX_PAYLOAD,
7508                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7509                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7510                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7511                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7512                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7513                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7514                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7515                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7516                         I40E_INSET_FLEX_PAYLOAD,
7517                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7518                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7519                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7520                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7521                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7522                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7523                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7524                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7525                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7526                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7527                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7528                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7529                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7530                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7531                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7532                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7533                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7534                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7535                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7536                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7537                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7538                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7539                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7540                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7541                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7542                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7543                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7544                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7545                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7546                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7547                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7548                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7549                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7550                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7551                         I40E_INSET_FLEX_PAYLOAD,
7552                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7553                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7554                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7555                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7556                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7557                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7558                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7559                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7560                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7561                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7562                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7563                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7564                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7565                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7566                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7567                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7568                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7569                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7570                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7571                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7572                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7573                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7574                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7575                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7576                         I40E_INSET_FLEX_PAYLOAD,
7577                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7578                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7579                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7580                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7581                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7582                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7583                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7584                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7585                         I40E_INSET_FLEX_PAYLOAD,
7586                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7587                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7588                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7589                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7590                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7591                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7592                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7593                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7594                         I40E_INSET_FLEX_PAYLOAD,
7595                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7596                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7597                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7598                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7599                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7600                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7601                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7602                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7603                         I40E_INSET_FLEX_PAYLOAD,
7604                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7605                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7606                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7607                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7608                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7609                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7610                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7611                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7612                         I40E_INSET_FLEX_PAYLOAD,
7613                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7614                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7615                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7616                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7617                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7618                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7619                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7620                         I40E_INSET_FLEX_PAYLOAD,
7621                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7622                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7623                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7624                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7625                         I40E_INSET_FLEX_PAYLOAD,
7626         };
7627
7628         /**
7629          * Flow director supports only fields defined in
7630          * union rte_eth_fdir_flow.
7631          */
7632         static const uint64_t valid_fdir_inset_table[] = {
7633                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7634                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7635                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7636                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7637                 I40E_INSET_IPV4_TTL,
7638                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7639                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7640                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7641                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7642                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7643                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7644                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7645                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7646                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7647                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7648                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7649                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7650                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7651                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7652                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7653                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7654                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7655                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7656                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7657                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7658                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7659                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7660                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7661                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7662                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7663                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7664                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7665                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7666                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7667                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7668                 I40E_INSET_SCTP_VT,
7669                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7670                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7671                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7672                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7673                 I40E_INSET_IPV4_TTL,
7674                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7675                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7676                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7677                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7678                 I40E_INSET_IPV6_HOP_LIMIT,
7679                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7680                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7681                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7682                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7683                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7684                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7685                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7686                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7687                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7688                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7689                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7690                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7691                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7692                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7693                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7694                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7695                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7696                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7697                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7698                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7699                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7700                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7701                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7702                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7703                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7704                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7705                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7706                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7707                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7708                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7709                 I40E_INSET_SCTP_VT,
7710                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7711                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7712                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7713                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7714                 I40E_INSET_IPV6_HOP_LIMIT,
7715                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7716                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7717                 I40E_INSET_LAST_ETHER_TYPE,
7718         };
7719
7720         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7721                 return 0;
7722         if (filter == RTE_ETH_FILTER_HASH)
7723                 valid = valid_hash_inset_table[pctype];
7724         else
7725                 valid = valid_fdir_inset_table[pctype];
7726
7727         return valid;
7728 }
7729
7730 /**
7731  * Validate if the input set is allowed for a specific PCTYPE
7732  */
7733 static int
7734 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7735                 enum rte_filter_type filter, uint64_t inset)
7736 {
7737         uint64_t valid;
7738
7739         valid = i40e_get_valid_input_set(pctype, filter);
7740         if (inset & (~valid))
7741                 return -EINVAL;
7742
7743         return 0;
7744 }
7745
7746 /* default input set fields combination per pctype */
7747 uint64_t
7748 i40e_get_default_input_set(uint16_t pctype)
7749 {
7750         static const uint64_t default_inset_table[] = {
7751                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7752                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7753                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7754                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7755                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7756                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7757                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7758                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7759                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7760                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7761                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7762                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7763                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7764                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7765                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7766                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7767                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7768                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7769                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7770                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7771                         I40E_INSET_SCTP_VT,
7772                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7773                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7774                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7775                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7776                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7777                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7778                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7779                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7780                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7781                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7782                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7783                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7784                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7785                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7786                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7787                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7788                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7789                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7790                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7791                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7792                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7793                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7794                         I40E_INSET_SCTP_VT,
7795                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7796                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7797                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7798                         I40E_INSET_LAST_ETHER_TYPE,
7799         };
7800
7801         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7802                 return 0;
7803
7804         return default_inset_table[pctype];
7805 }
7806
7807 /**
7808  * Parse the input set from index to logical bit masks
7809  */
7810 static int
7811 i40e_parse_input_set(uint64_t *inset,
7812                      enum i40e_filter_pctype pctype,
7813                      enum rte_eth_input_set_field *field,
7814                      uint16_t size)
7815 {
7816         uint16_t i, j;
7817         int ret = -EINVAL;
7818
7819         static const struct {
7820                 enum rte_eth_input_set_field field;
7821                 uint64_t inset;
7822         } inset_convert_table[] = {
7823                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7824                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7825                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7826                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7827                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7828                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7829                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7830                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7831                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7832                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7833                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7834                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7835                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7836                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7837                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7838                         I40E_INSET_IPV6_NEXT_HDR},
7839                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7840                         I40E_INSET_IPV6_HOP_LIMIT},
7841                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7842                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7843                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7844                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7845                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7846                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7847                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7848                         I40E_INSET_SCTP_VT},
7849                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7850                         I40E_INSET_TUNNEL_DMAC},
7851                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7852                         I40E_INSET_VLAN_TUNNEL},
7853                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7854                         I40E_INSET_TUNNEL_ID},
7855                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7856                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7857                         I40E_INSET_FLEX_PAYLOAD_W1},
7858                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7859                         I40E_INSET_FLEX_PAYLOAD_W2},
7860                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7861                         I40E_INSET_FLEX_PAYLOAD_W3},
7862                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7863                         I40E_INSET_FLEX_PAYLOAD_W4},
7864                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7865                         I40E_INSET_FLEX_PAYLOAD_W5},
7866                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7867                         I40E_INSET_FLEX_PAYLOAD_W6},
7868                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7869                         I40E_INSET_FLEX_PAYLOAD_W7},
7870                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7871                         I40E_INSET_FLEX_PAYLOAD_W8},
7872         };
7873
7874         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7875                 return ret;
7876
7877         /* Only one item allowed for default or all */
7878         if (size == 1) {
7879                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7880                         *inset = i40e_get_default_input_set(pctype);
7881                         return 0;
7882                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7883                         *inset = I40E_INSET_NONE;
7884                         return 0;
7885                 }
7886         }
7887
7888         for (i = 0, *inset = 0; i < size; i++) {
7889                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7890                         if (field[i] == inset_convert_table[j].field) {
7891                                 *inset |= inset_convert_table[j].inset;
7892                                 break;
7893                         }
7894                 }
7895
7896                 /* It contains unsupported input set, return immediately */
7897                 if (j == RTE_DIM(inset_convert_table))
7898                         return ret;
7899         }
7900
7901         return 0;
7902 }
7903
7904 /**
7905  * Translate the input set from bit masks to register aware bit masks
7906  * and vice versa
7907  */
7908 static uint64_t
7909 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7910 {
7911         uint64_t val = 0;
7912         uint16_t i;
7913
7914         struct inset_map {
7915                 uint64_t inset;
7916                 uint64_t inset_reg;
7917         };
7918
7919         static const struct inset_map inset_map_common[] = {
7920                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7921                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7922                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7923                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7924                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7925                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7926                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7927                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7928                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7929                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7930                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7931                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7932                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7933                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7934                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7935                 {I40E_INSET_TUNNEL_DMAC,
7936                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7937                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7938                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7939                 {I40E_INSET_TUNNEL_SRC_PORT,
7940                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7941                 {I40E_INSET_TUNNEL_DST_PORT,
7942                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7943                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7944                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7945                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7946                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7947                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7948                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7949                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7950                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7951                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7952         };
7953
7954     /* some different registers map in x722*/
7955         static const struct inset_map inset_map_diff_x722[] = {
7956                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7957                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7958                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7959                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7960         };
7961
7962         static const struct inset_map inset_map_diff_not_x722[] = {
7963                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7964                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7965                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7966                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7967         };
7968
7969         if (input == 0)
7970                 return val;
7971
7972         /* Translate input set to register aware inset */
7973         if (type == I40E_MAC_X722) {
7974                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7975                         if (input & inset_map_diff_x722[i].inset)
7976                                 val |= inset_map_diff_x722[i].inset_reg;
7977                 }
7978         } else {
7979                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7980                         if (input & inset_map_diff_not_x722[i].inset)
7981                                 val |= inset_map_diff_not_x722[i].inset_reg;
7982                 }
7983         }
7984
7985         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7986                 if (input & inset_map_common[i].inset)
7987                         val |= inset_map_common[i].inset_reg;
7988         }
7989
7990         return val;
7991 }
7992
7993 static int
7994 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7995 {
7996         uint8_t i, idx = 0;
7997         uint64_t inset_need_mask = inset;
7998
7999         static const struct {
8000                 uint64_t inset;
8001                 uint32_t mask;
8002         } inset_mask_map[] = {
8003                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8004                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8005                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8006                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8007                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8008                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8009                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8010                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8011         };
8012
8013         if (!inset || !mask || !nb_elem)
8014                 return 0;
8015
8016         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8017                 /* Clear the inset bit, if no MASK is required,
8018                  * for example proto + ttl
8019                  */
8020                 if ((inset & inset_mask_map[i].inset) ==
8021                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8022                         inset_need_mask &= ~inset_mask_map[i].inset;
8023                 if (!inset_need_mask)
8024                         return 0;
8025         }
8026         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8027                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8028                     inset_mask_map[i].inset) {
8029                         if (idx >= nb_elem) {
8030                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8031                                 return -EINVAL;
8032                         }
8033                         mask[idx] = inset_mask_map[i].mask;
8034                         idx++;
8035                 }
8036         }
8037
8038         return idx;
8039 }
8040
8041 static void
8042 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8043 {
8044         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8045
8046         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8047         if (reg != val)
8048                 i40e_write_rx_ctl(hw, addr, val);
8049         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8050                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8051 }
8052
8053 static void
8054 i40e_filter_input_set_init(struct i40e_pf *pf)
8055 {
8056         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8057         enum i40e_filter_pctype pctype;
8058         uint64_t input_set, inset_reg;
8059         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8060         int num, i;
8061
8062         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8063              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8064                 if (hw->mac.type == I40E_MAC_X722) {
8065                         if (!I40E_VALID_PCTYPE_X722(pctype))
8066                                 continue;
8067                 } else {
8068                         if (!I40E_VALID_PCTYPE(pctype))
8069                                 continue;
8070                 }
8071
8072                 input_set = i40e_get_default_input_set(pctype);
8073
8074                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8075                                                    I40E_INSET_MASK_NUM_REG);
8076                 if (num < 0)
8077                         return;
8078                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8079                                         input_set);
8080
8081                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8082                                       (uint32_t)(inset_reg & UINT32_MAX));
8083                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8084                                      (uint32_t)((inset_reg >>
8085                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8086                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8087                                       (uint32_t)(inset_reg & UINT32_MAX));
8088                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8089                                      (uint32_t)((inset_reg >>
8090                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8091
8092                 for (i = 0; i < num; i++) {
8093                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8094                                              mask_reg[i]);
8095                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8096                                              mask_reg[i]);
8097                 }
8098                 /*clear unused mask registers of the pctype */
8099                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8100                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8101                                              0);
8102                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8103                                              0);
8104                 }
8105                 I40E_WRITE_FLUSH(hw);
8106
8107                 /* store the default input set */
8108                 pf->hash_input_set[pctype] = input_set;
8109                 pf->fdir.input_set[pctype] = input_set;
8110         }
8111 }
8112
8113 int
8114 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8115                          struct rte_eth_input_set_conf *conf)
8116 {
8117         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8118         enum i40e_filter_pctype pctype;
8119         uint64_t input_set, inset_reg = 0;
8120         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8121         int ret, i, num;
8122
8123         if (!conf) {
8124                 PMD_DRV_LOG(ERR, "Invalid pointer");
8125                 return -EFAULT;
8126         }
8127         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8128             conf->op != RTE_ETH_INPUT_SET_ADD) {
8129                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8130                 return -EINVAL;
8131         }
8132
8133         if (!I40E_VALID_FLOW(conf->flow_type)) {
8134                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8135                 return -EINVAL;
8136         }
8137
8138         if (hw->mac.type == I40E_MAC_X722) {
8139                 /* get translated pctype value in fd pctype register */
8140                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8141                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8142                         conf->flow_type)));
8143         } else
8144                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8145
8146         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8147                                    conf->inset_size);
8148         if (ret) {
8149                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8150                 return -EINVAL;
8151         }
8152         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8153                                     input_set) != 0) {
8154                 PMD_DRV_LOG(ERR, "Invalid input set");
8155                 return -EINVAL;
8156         }
8157         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8158                 /* get inset value in register */
8159                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8160                 inset_reg <<= I40E_32_BIT_WIDTH;
8161                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8162                 input_set |= pf->hash_input_set[pctype];
8163         }
8164         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8165                                            I40E_INSET_MASK_NUM_REG);
8166         if (num < 0)
8167                 return -EINVAL;
8168
8169         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8170
8171         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8172                               (uint32_t)(inset_reg & UINT32_MAX));
8173         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8174                              (uint32_t)((inset_reg >>
8175                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8176
8177         for (i = 0; i < num; i++)
8178                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8179                                      mask_reg[i]);
8180         /*clear unused mask registers of the pctype */
8181         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8182                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8183                                      0);
8184         I40E_WRITE_FLUSH(hw);
8185
8186         pf->hash_input_set[pctype] = input_set;
8187         return 0;
8188 }
8189
8190 int
8191 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8192                          struct rte_eth_input_set_conf *conf)
8193 {
8194         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8195         enum i40e_filter_pctype pctype;
8196         uint64_t input_set, inset_reg = 0;
8197         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8198         int ret, i, num;
8199
8200         if (!hw || !conf) {
8201                 PMD_DRV_LOG(ERR, "Invalid pointer");
8202                 return -EFAULT;
8203         }
8204         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8205             conf->op != RTE_ETH_INPUT_SET_ADD) {
8206                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8207                 return -EINVAL;
8208         }
8209
8210         if (!I40E_VALID_FLOW(conf->flow_type)) {
8211                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8212                 return -EINVAL;
8213         }
8214
8215         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8216
8217         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8218                                    conf->inset_size);
8219         if (ret) {
8220                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8221                 return -EINVAL;
8222         }
8223         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8224                                     input_set) != 0) {
8225                 PMD_DRV_LOG(ERR, "Invalid input set");
8226                 return -EINVAL;
8227         }
8228
8229         /* get inset value in register */
8230         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8231         inset_reg <<= I40E_32_BIT_WIDTH;
8232         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8233
8234         /* Can not change the inset reg for flex payload for fdir,
8235          * it is done by writing I40E_PRTQF_FD_FLXINSET
8236          * in i40e_set_flex_mask_on_pctype.
8237          */
8238         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8239                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8240         else
8241                 input_set |= pf->fdir.input_set[pctype];
8242         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8243                                            I40E_INSET_MASK_NUM_REG);
8244         if (num < 0)
8245                 return -EINVAL;
8246
8247         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8248
8249         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8250                               (uint32_t)(inset_reg & UINT32_MAX));
8251         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8252                              (uint32_t)((inset_reg >>
8253                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8254
8255         for (i = 0; i < num; i++)
8256                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8257                                      mask_reg[i]);
8258         /*clear unused mask registers of the pctype */
8259         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8260                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8261                                      0);
8262         I40E_WRITE_FLUSH(hw);
8263
8264         pf->fdir.input_set[pctype] = input_set;
8265         return 0;
8266 }
8267
8268 static int
8269 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8270 {
8271         int ret = 0;
8272
8273         if (!hw || !info) {
8274                 PMD_DRV_LOG(ERR, "Invalid pointer");
8275                 return -EFAULT;
8276         }
8277
8278         switch (info->info_type) {
8279         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8280                 i40e_get_symmetric_hash_enable_per_port(hw,
8281                                         &(info->info.enable));
8282                 break;
8283         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8284                 ret = i40e_get_hash_filter_global_config(hw,
8285                                 &(info->info.global_conf));
8286                 break;
8287         default:
8288                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8289                                                         info->info_type);
8290                 ret = -EINVAL;
8291                 break;
8292         }
8293
8294         return ret;
8295 }
8296
8297 static int
8298 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8299 {
8300         int ret = 0;
8301
8302         if (!hw || !info) {
8303                 PMD_DRV_LOG(ERR, "Invalid pointer");
8304                 return -EFAULT;
8305         }
8306
8307         switch (info->info_type) {
8308         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8309                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8310                 break;
8311         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8312                 ret = i40e_set_hash_filter_global_config(hw,
8313                                 &(info->info.global_conf));
8314                 break;
8315         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8316                 ret = i40e_hash_filter_inset_select(hw,
8317                                                &(info->info.input_set_conf));
8318                 break;
8319
8320         default:
8321                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8322                                                         info->info_type);
8323                 ret = -EINVAL;
8324                 break;
8325         }
8326
8327         return ret;
8328 }
8329
8330 /* Operations for hash function */
8331 static int
8332 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8333                       enum rte_filter_op filter_op,
8334                       void *arg)
8335 {
8336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8337         int ret = 0;
8338
8339         switch (filter_op) {
8340         case RTE_ETH_FILTER_NOP:
8341                 break;
8342         case RTE_ETH_FILTER_GET:
8343                 ret = i40e_hash_filter_get(hw,
8344                         (struct rte_eth_hash_filter_info *)arg);
8345                 break;
8346         case RTE_ETH_FILTER_SET:
8347                 ret = i40e_hash_filter_set(hw,
8348                         (struct rte_eth_hash_filter_info *)arg);
8349                 break;
8350         default:
8351                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8352                                                                 filter_op);
8353                 ret = -ENOTSUP;
8354                 break;
8355         }
8356
8357         return ret;
8358 }
8359
8360 /* Convert ethertype filter structure */
8361 static int
8362 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8363                               struct i40e_ethertype_filter *filter)
8364 {
8365         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8366         filter->input.ether_type = input->ether_type;
8367         filter->flags = input->flags;
8368         filter->queue = input->queue;
8369
8370         return 0;
8371 }
8372
8373 /* Check if there exists the ehtertype filter */
8374 struct i40e_ethertype_filter *
8375 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8376                                 const struct i40e_ethertype_filter_input *input)
8377 {
8378         int ret;
8379
8380         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8381         if (ret < 0)
8382                 return NULL;
8383
8384         return ethertype_rule->hash_map[ret];
8385 }
8386
8387 /* Add ethertype filter in SW list */
8388 static int
8389 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8390                                 struct i40e_ethertype_filter *filter)
8391 {
8392         struct i40e_ethertype_rule *rule = &pf->ethertype;
8393         int ret;
8394
8395         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8396         if (ret < 0) {
8397                 PMD_DRV_LOG(ERR,
8398                             "Failed to insert ethertype filter"
8399                             " to hash table %d!",
8400                             ret);
8401                 return ret;
8402         }
8403         rule->hash_map[ret] = filter;
8404
8405         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8406
8407         return 0;
8408 }
8409
8410 /* Delete ethertype filter in SW list */
8411 int
8412 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8413                              struct i40e_ethertype_filter_input *input)
8414 {
8415         struct i40e_ethertype_rule *rule = &pf->ethertype;
8416         struct i40e_ethertype_filter *filter;
8417         int ret;
8418
8419         ret = rte_hash_del_key(rule->hash_table, input);
8420         if (ret < 0) {
8421                 PMD_DRV_LOG(ERR,
8422                             "Failed to delete ethertype filter"
8423                             " to hash table %d!",
8424                             ret);
8425                 return ret;
8426         }
8427         filter = rule->hash_map[ret];
8428         rule->hash_map[ret] = NULL;
8429
8430         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8431         rte_free(filter);
8432
8433         return 0;
8434 }
8435
8436 /*
8437  * Configure ethertype filter, which can director packet by filtering
8438  * with mac address and ether_type or only ether_type
8439  */
8440 int
8441 i40e_ethertype_filter_set(struct i40e_pf *pf,
8442                         struct rte_eth_ethertype_filter *filter,
8443                         bool add)
8444 {
8445         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8446         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8447         struct i40e_ethertype_filter *ethertype_filter, *node;
8448         struct i40e_ethertype_filter check_filter;
8449         struct i40e_control_filter_stats stats;
8450         uint16_t flags = 0;
8451         int ret;
8452
8453         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8454                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8455                 return -EINVAL;
8456         }
8457         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8458                 filter->ether_type == ETHER_TYPE_IPv6) {
8459                 PMD_DRV_LOG(ERR,
8460                         "unsupported ether_type(0x%04x) in control packet filter.",
8461                         filter->ether_type);
8462                 return -EINVAL;
8463         }
8464         if (filter->ether_type == ETHER_TYPE_VLAN)
8465                 PMD_DRV_LOG(WARNING,
8466                         "filter vlan ether_type in first tag is not supported.");
8467
8468         /* Check if there is the filter in SW list */
8469         memset(&check_filter, 0, sizeof(check_filter));
8470         i40e_ethertype_filter_convert(filter, &check_filter);
8471         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8472                                                &check_filter.input);
8473         if (add && node) {
8474                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8475                 return -EINVAL;
8476         }
8477
8478         if (!add && !node) {
8479                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8480                 return -EINVAL;
8481         }
8482
8483         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8484                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8485         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8486                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8487         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8488
8489         memset(&stats, 0, sizeof(stats));
8490         ret = i40e_aq_add_rem_control_packet_filter(hw,
8491                         filter->mac_addr.addr_bytes,
8492                         filter->ether_type, flags,
8493                         pf->main_vsi->seid,
8494                         filter->queue, add, &stats, NULL);
8495
8496         PMD_DRV_LOG(INFO,
8497                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8498                 ret, stats.mac_etype_used, stats.etype_used,
8499                 stats.mac_etype_free, stats.etype_free);
8500         if (ret < 0)
8501                 return -ENOSYS;
8502
8503         /* Add or delete a filter in SW list */
8504         if (add) {
8505                 ethertype_filter = rte_zmalloc("ethertype_filter",
8506                                        sizeof(*ethertype_filter), 0);
8507                 rte_memcpy(ethertype_filter, &check_filter,
8508                            sizeof(check_filter));
8509                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8510         } else {
8511                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8512         }
8513
8514         return ret;
8515 }
8516
8517 /*
8518  * Handle operations for ethertype filter.
8519  */
8520 static int
8521 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8522                                 enum rte_filter_op filter_op,
8523                                 void *arg)
8524 {
8525         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8526         int ret = 0;
8527
8528         if (filter_op == RTE_ETH_FILTER_NOP)
8529                 return ret;
8530
8531         if (arg == NULL) {
8532                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8533                             filter_op);
8534                 return -EINVAL;
8535         }
8536
8537         switch (filter_op) {
8538         case RTE_ETH_FILTER_ADD:
8539                 ret = i40e_ethertype_filter_set(pf,
8540                         (struct rte_eth_ethertype_filter *)arg,
8541                         TRUE);
8542                 break;
8543         case RTE_ETH_FILTER_DELETE:
8544                 ret = i40e_ethertype_filter_set(pf,
8545                         (struct rte_eth_ethertype_filter *)arg,
8546                         FALSE);
8547                 break;
8548         default:
8549                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8550                 ret = -ENOSYS;
8551                 break;
8552         }
8553         return ret;
8554 }
8555
8556 static int
8557 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8558                      enum rte_filter_type filter_type,
8559                      enum rte_filter_op filter_op,
8560                      void *arg)
8561 {
8562         int ret = 0;
8563
8564         if (dev == NULL)
8565                 return -EINVAL;
8566
8567         switch (filter_type) {
8568         case RTE_ETH_FILTER_NONE:
8569                 /* For global configuration */
8570                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8571                 break;
8572         case RTE_ETH_FILTER_HASH:
8573                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8574                 break;
8575         case RTE_ETH_FILTER_MACVLAN:
8576                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8577                 break;
8578         case RTE_ETH_FILTER_ETHERTYPE:
8579                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8580                 break;
8581         case RTE_ETH_FILTER_TUNNEL:
8582                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8583                 break;
8584         case RTE_ETH_FILTER_FDIR:
8585                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8586                 break;
8587         case RTE_ETH_FILTER_GENERIC:
8588                 if (filter_op != RTE_ETH_FILTER_GET)
8589                         return -EINVAL;
8590                 *(const void **)arg = &i40e_flow_ops;
8591                 break;
8592         default:
8593                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8594                                                         filter_type);
8595                 ret = -EINVAL;
8596                 break;
8597         }
8598
8599         return ret;
8600 }
8601
8602 /*
8603  * Check and enable Extended Tag.
8604  * Enabling Extended Tag is important for 40G performance.
8605  */
8606 static void
8607 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8608 {
8609         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8610         uint32_t buf = 0;
8611         int ret;
8612
8613         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8614                                       PCI_DEV_CAP_REG);
8615         if (ret < 0) {
8616                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8617                             PCI_DEV_CAP_REG);
8618                 return;
8619         }
8620         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8621                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8622                 return;
8623         }
8624
8625         buf = 0;
8626         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8627                                       PCI_DEV_CTRL_REG);
8628         if (ret < 0) {
8629                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8630                             PCI_DEV_CTRL_REG);
8631                 return;
8632         }
8633         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8634                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8635                 return;
8636         }
8637         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8638         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8639                                        PCI_DEV_CTRL_REG);
8640         if (ret < 0) {
8641                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8642                             PCI_DEV_CTRL_REG);
8643                 return;
8644         }
8645 }
8646
8647 /*
8648  * As some registers wouldn't be reset unless a global hardware reset,
8649  * hardware initialization is needed to put those registers into an
8650  * expected initial state.
8651  */
8652 static void
8653 i40e_hw_init(struct rte_eth_dev *dev)
8654 {
8655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8656
8657         i40e_enable_extended_tag(dev);
8658
8659         /* clear the PF Queue Filter control register */
8660         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8661
8662         /* Disable symmetric hash per port */
8663         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8664 }
8665
8666 enum i40e_filter_pctype
8667 i40e_flowtype_to_pctype(uint16_t flow_type)
8668 {
8669         static const enum i40e_filter_pctype pctype_table[] = {
8670                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8671                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8672                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8673                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8674                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8675                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8676                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8677                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8678                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8679                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8680                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8681                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8682                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8683                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8684                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8685                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8686                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8687                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8688                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8689         };
8690
8691         return pctype_table[flow_type];
8692 }
8693
8694 uint16_t
8695 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8696 {
8697         static const uint16_t flowtype_table[] = {
8698                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8699                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8700                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8701                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8702                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8703                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8704                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8705                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8706                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8707                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8708                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8709                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8710                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8711                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8712                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8713                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8714                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8715                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8716                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8717                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8718                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8719                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8720                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8721                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8722                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8723                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8724                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8725                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8726                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8727                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8728                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8729         };
8730
8731         return flowtype_table[pctype];
8732 }
8733
8734 /*
8735  * On X710, performance number is far from the expectation on recent firmware
8736  * versions; on XL710, performance number is also far from the expectation on
8737  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8738  * mode is enabled and port MAC address is equal to the packet destination MAC
8739  * address. The fix for this issue may not be integrated in the following
8740  * firmware version. So the workaround in software driver is needed. It needs
8741  * to modify the initial values of 3 internal only registers for both X710 and
8742  * XL710. Note that the values for X710 or XL710 could be different, and the
8743  * workaround can be removed when it is fixed in firmware in the future.
8744  */
8745
8746 /* For both X710 and XL710 */
8747 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8748 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8749
8750 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8751 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8752
8753 /* For X722 */
8754 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8755 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8756
8757 /* For X710 */
8758 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8759 /* For XL710 */
8760 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8761 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8762
8763 static int
8764 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8765 {
8766         enum i40e_status_code status;
8767         struct i40e_aq_get_phy_abilities_resp phy_ab;
8768         int ret = -ENOTSUP;
8769
8770         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8771                                               NULL);
8772
8773         if (status)
8774                 return ret;
8775
8776         return 0;
8777 }
8778
8779 static void
8780 i40e_configure_registers(struct i40e_hw *hw)
8781 {
8782         static struct {
8783                 uint32_t addr;
8784                 uint64_t val;
8785         } reg_table[] = {
8786                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8787                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8788                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8789         };
8790         uint64_t reg;
8791         uint32_t i;
8792         int ret;
8793
8794         for (i = 0; i < RTE_DIM(reg_table); i++) {
8795                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8796                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8797                                 reg_table[i].val =
8798                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8799                         else /* For X710/XL710/XXV710 */
8800                                 reg_table[i].val =
8801                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8802                 }
8803
8804                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8805                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8806                                 reg_table[i].val =
8807                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8808                         else /* For X710/XL710/XXV710 */
8809                                 reg_table[i].val =
8810                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8811                 }
8812
8813                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8814                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8815                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8816                                 reg_table[i].val =
8817                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8818                         else /* For X710 */
8819                                 reg_table[i].val =
8820                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8821                 }
8822
8823                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8824                                                         &reg, NULL);
8825                 if (ret < 0) {
8826                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8827                                                         reg_table[i].addr);
8828                         break;
8829                 }
8830                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8831                                                 reg_table[i].addr, reg);
8832                 if (reg == reg_table[i].val)
8833                         continue;
8834
8835                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8836                                                 reg_table[i].val, NULL);
8837                 if (ret < 0) {
8838                         PMD_DRV_LOG(ERR,
8839                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8840                                 reg_table[i].val, reg_table[i].addr);
8841                         break;
8842                 }
8843                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8844                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8845         }
8846 }
8847
8848 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8849 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8850 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8851 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8852 static int
8853 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8854 {
8855         uint32_t reg;
8856         int ret;
8857
8858         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8859                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8860                 return -EINVAL;
8861         }
8862
8863         /* Configure for double VLAN RX stripping */
8864         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8865         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8866                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8867                 ret = i40e_aq_debug_write_register(hw,
8868                                                    I40E_VSI_TSR(vsi->vsi_id),
8869                                                    reg, NULL);
8870                 if (ret < 0) {
8871                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8872                                     vsi->vsi_id);
8873                         return I40E_ERR_CONFIG;
8874                 }
8875         }
8876
8877         /* Configure for double VLAN TX insertion */
8878         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8879         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8880                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8881                 ret = i40e_aq_debug_write_register(hw,
8882                                                    I40E_VSI_L2TAGSTXVALID(
8883                                                    vsi->vsi_id), reg, NULL);
8884                 if (ret < 0) {
8885                         PMD_DRV_LOG(ERR,
8886                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
8887                                 vsi->vsi_id);
8888                         return I40E_ERR_CONFIG;
8889                 }
8890         }
8891
8892         return 0;
8893 }
8894
8895 /**
8896  * i40e_aq_add_mirror_rule
8897  * @hw: pointer to the hardware structure
8898  * @seid: VEB seid to add mirror rule to
8899  * @dst_id: destination vsi seid
8900  * @entries: Buffer which contains the entities to be mirrored
8901  * @count: number of entities contained in the buffer
8902  * @rule_id:the rule_id of the rule to be added
8903  *
8904  * Add a mirror rule for a given veb.
8905  *
8906  **/
8907 static enum i40e_status_code
8908 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8909                         uint16_t seid, uint16_t dst_id,
8910                         uint16_t rule_type, uint16_t *entries,
8911                         uint16_t count, uint16_t *rule_id)
8912 {
8913         struct i40e_aq_desc desc;
8914         struct i40e_aqc_add_delete_mirror_rule cmd;
8915         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8916                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8917                 &desc.params.raw;
8918         uint16_t buff_len;
8919         enum i40e_status_code status;
8920
8921         i40e_fill_default_direct_cmd_desc(&desc,
8922                                           i40e_aqc_opc_add_mirror_rule);
8923         memset(&cmd, 0, sizeof(cmd));
8924
8925         buff_len = sizeof(uint16_t) * count;
8926         desc.datalen = rte_cpu_to_le_16(buff_len);
8927         if (buff_len > 0)
8928                 desc.flags |= rte_cpu_to_le_16(
8929                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8930         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8931                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8932         cmd.num_entries = rte_cpu_to_le_16(count);
8933         cmd.seid = rte_cpu_to_le_16(seid);
8934         cmd.destination = rte_cpu_to_le_16(dst_id);
8935
8936         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8937         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8938         PMD_DRV_LOG(INFO,
8939                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8940                 hw->aq.asq_last_status, resp->rule_id,
8941                 resp->mirror_rules_used, resp->mirror_rules_free);
8942         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8943
8944         return status;
8945 }
8946
8947 /**
8948  * i40e_aq_del_mirror_rule
8949  * @hw: pointer to the hardware structure
8950  * @seid: VEB seid to add mirror rule to
8951  * @entries: Buffer which contains the entities to be mirrored
8952  * @count: number of entities contained in the buffer
8953  * @rule_id:the rule_id of the rule to be delete
8954  *
8955  * Delete a mirror rule for a given veb.
8956  *
8957  **/
8958 static enum i40e_status_code
8959 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8960                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8961                 uint16_t count, uint16_t rule_id)
8962 {
8963         struct i40e_aq_desc desc;
8964         struct i40e_aqc_add_delete_mirror_rule cmd;
8965         uint16_t buff_len = 0;
8966         enum i40e_status_code status;
8967         void *buff = NULL;
8968
8969         i40e_fill_default_direct_cmd_desc(&desc,
8970                                           i40e_aqc_opc_delete_mirror_rule);
8971         memset(&cmd, 0, sizeof(cmd));
8972         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8973                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8974                                                           I40E_AQ_FLAG_RD));
8975                 cmd.num_entries = count;
8976                 buff_len = sizeof(uint16_t) * count;
8977                 desc.datalen = rte_cpu_to_le_16(buff_len);
8978                 buff = (void *)entries;
8979         } else
8980                 /* rule id is filled in destination field for deleting mirror rule */
8981                 cmd.destination = rte_cpu_to_le_16(rule_id);
8982
8983         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8984                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8985         cmd.seid = rte_cpu_to_le_16(seid);
8986
8987         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8988         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8989
8990         return status;
8991 }
8992
8993 /**
8994  * i40e_mirror_rule_set
8995  * @dev: pointer to the hardware structure
8996  * @mirror_conf: mirror rule info
8997  * @sw_id: mirror rule's sw_id
8998  * @on: enable/disable
8999  *
9000  * set a mirror rule.
9001  *
9002  **/
9003 static int
9004 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9005                         struct rte_eth_mirror_conf *mirror_conf,
9006                         uint8_t sw_id, uint8_t on)
9007 {
9008         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9009         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9010         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9011         struct i40e_mirror_rule *parent = NULL;
9012         uint16_t seid, dst_seid, rule_id;
9013         uint16_t i, j = 0;
9014         int ret;
9015
9016         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9017
9018         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9019                 PMD_DRV_LOG(ERR,
9020                         "mirror rule can not be configured without veb or vfs.");
9021                 return -ENOSYS;
9022         }
9023         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9024                 PMD_DRV_LOG(ERR, "mirror table is full.");
9025                 return -ENOSPC;
9026         }
9027         if (mirror_conf->dst_pool > pf->vf_num) {
9028                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9029                                  mirror_conf->dst_pool);
9030                 return -EINVAL;
9031         }
9032
9033         seid = pf->main_vsi->veb->seid;
9034
9035         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9036                 if (sw_id <= it->index) {
9037                         mirr_rule = it;
9038                         break;
9039                 }
9040                 parent = it;
9041         }
9042         if (mirr_rule && sw_id == mirr_rule->index) {
9043                 if (on) {
9044                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9045                         return -EEXIST;
9046                 } else {
9047                         ret = i40e_aq_del_mirror_rule(hw, seid,
9048                                         mirr_rule->rule_type,
9049                                         mirr_rule->entries,
9050                                         mirr_rule->num_entries, mirr_rule->id);
9051                         if (ret < 0) {
9052                                 PMD_DRV_LOG(ERR,
9053                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9054                                         ret, hw->aq.asq_last_status);
9055                                 return -ENOSYS;
9056                         }
9057                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9058                         rte_free(mirr_rule);
9059                         pf->nb_mirror_rule--;
9060                         return 0;
9061                 }
9062         } else if (!on) {
9063                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9064                 return -ENOENT;
9065         }
9066
9067         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9068                                 sizeof(struct i40e_mirror_rule) , 0);
9069         if (!mirr_rule) {
9070                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9071                 return I40E_ERR_NO_MEMORY;
9072         }
9073         switch (mirror_conf->rule_type) {
9074         case ETH_MIRROR_VLAN:
9075                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9076                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9077                                 mirr_rule->entries[j] =
9078                                         mirror_conf->vlan.vlan_id[i];
9079                                 j++;
9080                         }
9081                 }
9082                 if (j == 0) {
9083                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9084                         rte_free(mirr_rule);
9085                         return -EINVAL;
9086                 }
9087                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9088                 break;
9089         case ETH_MIRROR_VIRTUAL_POOL_UP:
9090         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9091                 /* check if the specified pool bit is out of range */
9092                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9093                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9094                         rte_free(mirr_rule);
9095                         return -EINVAL;
9096                 }
9097                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9098                         if (mirror_conf->pool_mask & (1ULL << i)) {
9099                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9100                                 j++;
9101                         }
9102                 }
9103                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9104                         /* add pf vsi to entries */
9105                         mirr_rule->entries[j] = pf->main_vsi_seid;
9106                         j++;
9107                 }
9108                 if (j == 0) {
9109                         PMD_DRV_LOG(ERR, "pool is not specified.");
9110                         rte_free(mirr_rule);
9111                         return -EINVAL;
9112                 }
9113                 /* egress and ingress in aq commands means from switch but not port */
9114                 mirr_rule->rule_type =
9115                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9116                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9117                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9118                 break;
9119         case ETH_MIRROR_UPLINK_PORT:
9120                 /* egress and ingress in aq commands means from switch but not port*/
9121                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9122                 break;
9123         case ETH_MIRROR_DOWNLINK_PORT:
9124                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9125                 break;
9126         default:
9127                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9128                         mirror_conf->rule_type);
9129                 rte_free(mirr_rule);
9130                 return -EINVAL;
9131         }
9132
9133         /* If the dst_pool is equal to vf_num, consider it as PF */
9134         if (mirror_conf->dst_pool == pf->vf_num)
9135                 dst_seid = pf->main_vsi_seid;
9136         else
9137                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9138
9139         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9140                                       mirr_rule->rule_type, mirr_rule->entries,
9141                                       j, &rule_id);
9142         if (ret < 0) {
9143                 PMD_DRV_LOG(ERR,
9144                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9145                         ret, hw->aq.asq_last_status);
9146                 rte_free(mirr_rule);
9147                 return -ENOSYS;
9148         }
9149
9150         mirr_rule->index = sw_id;
9151         mirr_rule->num_entries = j;
9152         mirr_rule->id = rule_id;
9153         mirr_rule->dst_vsi_seid = dst_seid;
9154
9155         if (parent)
9156                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9157         else
9158                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9159
9160         pf->nb_mirror_rule++;
9161         return 0;
9162 }
9163
9164 /**
9165  * i40e_mirror_rule_reset
9166  * @dev: pointer to the device
9167  * @sw_id: mirror rule's sw_id
9168  *
9169  * reset a mirror rule.
9170  *
9171  **/
9172 static int
9173 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9174 {
9175         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9176         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9177         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9178         uint16_t seid;
9179         int ret;
9180
9181         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9182
9183         seid = pf->main_vsi->veb->seid;
9184
9185         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9186                 if (sw_id == it->index) {
9187                         mirr_rule = it;
9188                         break;
9189                 }
9190         }
9191         if (mirr_rule) {
9192                 ret = i40e_aq_del_mirror_rule(hw, seid,
9193                                 mirr_rule->rule_type,
9194                                 mirr_rule->entries,
9195                                 mirr_rule->num_entries, mirr_rule->id);
9196                 if (ret < 0) {
9197                         PMD_DRV_LOG(ERR,
9198                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9199                                 ret, hw->aq.asq_last_status);
9200                         return -ENOSYS;
9201                 }
9202                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9203                 rte_free(mirr_rule);
9204                 pf->nb_mirror_rule--;
9205         } else {
9206                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9207                 return -ENOENT;
9208         }
9209         return 0;
9210 }
9211
9212 static uint64_t
9213 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9214 {
9215         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9216         uint64_t systim_cycles;
9217
9218         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9219         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9220                         << 32;
9221
9222         return systim_cycles;
9223 }
9224
9225 static uint64_t
9226 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9227 {
9228         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9229         uint64_t rx_tstamp;
9230
9231         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9232         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9233                         << 32;
9234
9235         return rx_tstamp;
9236 }
9237
9238 static uint64_t
9239 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9240 {
9241         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9242         uint64_t tx_tstamp;
9243
9244         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9245         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9246                         << 32;
9247
9248         return tx_tstamp;
9249 }
9250
9251 static void
9252 i40e_start_timecounters(struct rte_eth_dev *dev)
9253 {
9254         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9255         struct i40e_adapter *adapter =
9256                         (struct i40e_adapter *)dev->data->dev_private;
9257         struct rte_eth_link link;
9258         uint32_t tsync_inc_l;
9259         uint32_t tsync_inc_h;
9260
9261         /* Get current link speed. */
9262         memset(&link, 0, sizeof(link));
9263         i40e_dev_link_update(dev, 1);
9264         rte_i40e_dev_atomic_read_link_status(dev, &link);
9265
9266         switch (link.link_speed) {
9267         case ETH_SPEED_NUM_40G:
9268                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9269                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9270                 break;
9271         case ETH_SPEED_NUM_10G:
9272                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9273                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9274                 break;
9275         case ETH_SPEED_NUM_1G:
9276                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9277                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9278                 break;
9279         default:
9280                 tsync_inc_l = 0x0;
9281                 tsync_inc_h = 0x0;
9282         }
9283
9284         /* Set the timesync increment value. */
9285         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9286         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9287
9288         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9289         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9290         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9291
9292         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9293         adapter->systime_tc.cc_shift = 0;
9294         adapter->systime_tc.nsec_mask = 0;
9295
9296         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9297         adapter->rx_tstamp_tc.cc_shift = 0;
9298         adapter->rx_tstamp_tc.nsec_mask = 0;
9299
9300         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9301         adapter->tx_tstamp_tc.cc_shift = 0;
9302         adapter->tx_tstamp_tc.nsec_mask = 0;
9303 }
9304
9305 static int
9306 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9307 {
9308         struct i40e_adapter *adapter =
9309                         (struct i40e_adapter *)dev->data->dev_private;
9310
9311         adapter->systime_tc.nsec += delta;
9312         adapter->rx_tstamp_tc.nsec += delta;
9313         adapter->tx_tstamp_tc.nsec += delta;
9314
9315         return 0;
9316 }
9317
9318 static int
9319 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9320 {
9321         uint64_t ns;
9322         struct i40e_adapter *adapter =
9323                         (struct i40e_adapter *)dev->data->dev_private;
9324
9325         ns = rte_timespec_to_ns(ts);
9326
9327         /* Set the timecounters to a new value. */
9328         adapter->systime_tc.nsec = ns;
9329         adapter->rx_tstamp_tc.nsec = ns;
9330         adapter->tx_tstamp_tc.nsec = ns;
9331
9332         return 0;
9333 }
9334
9335 static int
9336 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9337 {
9338         uint64_t ns, systime_cycles;
9339         struct i40e_adapter *adapter =
9340                         (struct i40e_adapter *)dev->data->dev_private;
9341
9342         systime_cycles = i40e_read_systime_cyclecounter(dev);
9343         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9344         *ts = rte_ns_to_timespec(ns);
9345
9346         return 0;
9347 }
9348
9349 static int
9350 i40e_timesync_enable(struct rte_eth_dev *dev)
9351 {
9352         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9353         uint32_t tsync_ctl_l;
9354         uint32_t tsync_ctl_h;
9355
9356         /* Stop the timesync system time. */
9357         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9358         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9359         /* Reset the timesync system time value. */
9360         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9361         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9362
9363         i40e_start_timecounters(dev);
9364
9365         /* Clear timesync registers. */
9366         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9367         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9368         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9369         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9370         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9371         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9372
9373         /* Enable timestamping of PTP packets. */
9374         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9375         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9376
9377         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9378         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9379         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9380
9381         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9382         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9383
9384         return 0;
9385 }
9386
9387 static int
9388 i40e_timesync_disable(struct rte_eth_dev *dev)
9389 {
9390         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9391         uint32_t tsync_ctl_l;
9392         uint32_t tsync_ctl_h;
9393
9394         /* Disable timestamping of transmitted PTP packets. */
9395         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9396         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9397
9398         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9399         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9400
9401         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9402         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9403
9404         /* Reset the timesync increment value. */
9405         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9406         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9407
9408         return 0;
9409 }
9410
9411 static int
9412 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9413                                 struct timespec *timestamp, uint32_t flags)
9414 {
9415         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9416         struct i40e_adapter *adapter =
9417                 (struct i40e_adapter *)dev->data->dev_private;
9418
9419         uint32_t sync_status;
9420         uint32_t index = flags & 0x03;
9421         uint64_t rx_tstamp_cycles;
9422         uint64_t ns;
9423
9424         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9425         if ((sync_status & (1 << index)) == 0)
9426                 return -EINVAL;
9427
9428         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9429         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9430         *timestamp = rte_ns_to_timespec(ns);
9431
9432         return 0;
9433 }
9434
9435 static int
9436 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9437                                 struct timespec *timestamp)
9438 {
9439         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9440         struct i40e_adapter *adapter =
9441                 (struct i40e_adapter *)dev->data->dev_private;
9442
9443         uint32_t sync_status;
9444         uint64_t tx_tstamp_cycles;
9445         uint64_t ns;
9446
9447         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9448         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9449                 return -EINVAL;
9450
9451         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9452         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9453         *timestamp = rte_ns_to_timespec(ns);
9454
9455         return 0;
9456 }
9457
9458 /*
9459  * i40e_parse_dcb_configure - parse dcb configure from user
9460  * @dev: the device being configured
9461  * @dcb_cfg: pointer of the result of parse
9462  * @*tc_map: bit map of enabled traffic classes
9463  *
9464  * Returns 0 on success, negative value on failure
9465  */
9466 static int
9467 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9468                          struct i40e_dcbx_config *dcb_cfg,
9469                          uint8_t *tc_map)
9470 {
9471         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9472         uint8_t i, tc_bw, bw_lf;
9473
9474         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9475
9476         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9477         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9478                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9479                 return -EINVAL;
9480         }
9481
9482         /* assume each tc has the same bw */
9483         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9484         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9485                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9486         /* to ensure the sum of tcbw is equal to 100 */
9487         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9488         for (i = 0; i < bw_lf; i++)
9489                 dcb_cfg->etscfg.tcbwtable[i]++;
9490
9491         /* assume each tc has the same Transmission Selection Algorithm */
9492         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9493                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9494
9495         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9496                 dcb_cfg->etscfg.prioritytable[i] =
9497                                 dcb_rx_conf->dcb_tc[i];
9498
9499         /* FW needs one App to configure HW */
9500         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9501         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9502         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9503         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9504
9505         if (dcb_rx_conf->nb_tcs == 0)
9506                 *tc_map = 1; /* tc0 only */
9507         else
9508                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9509
9510         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9511                 dcb_cfg->pfc.willing = 0;
9512                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9513                 dcb_cfg->pfc.pfcenable = *tc_map;
9514         }
9515         return 0;
9516 }
9517
9518
9519 static enum i40e_status_code
9520 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9521                               struct i40e_aqc_vsi_properties_data *info,
9522                               uint8_t enabled_tcmap)
9523 {
9524         enum i40e_status_code ret;
9525         int i, total_tc = 0;
9526         uint16_t qpnum_per_tc, bsf, qp_idx;
9527         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9528         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9529         uint16_t used_queues;
9530
9531         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9532         if (ret != I40E_SUCCESS)
9533                 return ret;
9534
9535         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9536                 if (enabled_tcmap & (1 << i))
9537                         total_tc++;
9538         }
9539         if (total_tc == 0)
9540                 total_tc = 1;
9541         vsi->enabled_tc = enabled_tcmap;
9542
9543         /* different VSI has different queues assigned */
9544         if (vsi->type == I40E_VSI_MAIN)
9545                 used_queues = dev_data->nb_rx_queues -
9546                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9547         else if (vsi->type == I40E_VSI_VMDQ2)
9548                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9549         else {
9550                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9551                 return I40E_ERR_NO_AVAILABLE_VSI;
9552         }
9553
9554         qpnum_per_tc = used_queues / total_tc;
9555         /* Number of queues per enabled TC */
9556         if (qpnum_per_tc == 0) {
9557                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9558                 return I40E_ERR_INVALID_QP_ID;
9559         }
9560         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9561                                 I40E_MAX_Q_PER_TC);
9562         bsf = rte_bsf32(qpnum_per_tc);
9563
9564         /**
9565          * Configure TC and queue mapping parameters, for enabled TC,
9566          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9567          * default queue will serve it.
9568          */
9569         qp_idx = 0;
9570         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9571                 if (vsi->enabled_tc & (1 << i)) {
9572                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9573                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9574                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9575                         qp_idx += qpnum_per_tc;
9576                 } else
9577                         info->tc_mapping[i] = 0;
9578         }
9579
9580         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9581         if (vsi->type == I40E_VSI_SRIOV) {
9582                 info->mapping_flags |=
9583                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9584                 for (i = 0; i < vsi->nb_qps; i++)
9585                         info->queue_mapping[i] =
9586                                 rte_cpu_to_le_16(vsi->base_queue + i);
9587         } else {
9588                 info->mapping_flags |=
9589                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9590                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9591         }
9592         info->valid_sections |=
9593                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9594
9595         return I40E_SUCCESS;
9596 }
9597
9598 /*
9599  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9600  * @veb: VEB to be configured
9601  * @tc_map: enabled TC bitmap
9602  *
9603  * Returns 0 on success, negative value on failure
9604  */
9605 static enum i40e_status_code
9606 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9607 {
9608         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9609         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9610         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9611         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9612         enum i40e_status_code ret = I40E_SUCCESS;
9613         int i;
9614         uint32_t bw_max;
9615
9616         /* Check if enabled_tc is same as existing or new TCs */
9617         if (veb->enabled_tc == tc_map)
9618                 return ret;
9619
9620         /* configure tc bandwidth */
9621         memset(&veb_bw, 0, sizeof(veb_bw));
9622         veb_bw.tc_valid_bits = tc_map;
9623         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9624         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9625                 if (tc_map & BIT_ULL(i))
9626                         veb_bw.tc_bw_share_credits[i] = 1;
9627         }
9628         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9629                                                    &veb_bw, NULL);
9630         if (ret) {
9631                 PMD_INIT_LOG(ERR,
9632                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9633                         hw->aq.asq_last_status);
9634                 return ret;
9635         }
9636
9637         memset(&ets_query, 0, sizeof(ets_query));
9638         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9639                                                    &ets_query, NULL);
9640         if (ret != I40E_SUCCESS) {
9641                 PMD_DRV_LOG(ERR,
9642                         "Failed to get switch_comp ETS configuration %u",
9643                         hw->aq.asq_last_status);
9644                 return ret;
9645         }
9646         memset(&bw_query, 0, sizeof(bw_query));
9647         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9648                                                   &bw_query, NULL);
9649         if (ret != I40E_SUCCESS) {
9650                 PMD_DRV_LOG(ERR,
9651                         "Failed to get switch_comp bandwidth configuration %u",
9652                         hw->aq.asq_last_status);
9653                 return ret;
9654         }
9655
9656         /* store and print out BW info */
9657         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9658         veb->bw_info.bw_max = ets_query.tc_bw_max;
9659         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9660         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9661         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9662                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9663                      I40E_16_BIT_WIDTH);
9664         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9665                 veb->bw_info.bw_ets_share_credits[i] =
9666                                 bw_query.tc_bw_share_credits[i];
9667                 veb->bw_info.bw_ets_credits[i] =
9668                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9669                 /* 4 bits per TC, 4th bit is reserved */
9670                 veb->bw_info.bw_ets_max[i] =
9671                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9672                                   RTE_LEN2MASK(3, uint8_t));
9673                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9674                             veb->bw_info.bw_ets_share_credits[i]);
9675                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9676                             veb->bw_info.bw_ets_credits[i]);
9677                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9678                             veb->bw_info.bw_ets_max[i]);
9679         }
9680
9681         veb->enabled_tc = tc_map;
9682
9683         return ret;
9684 }
9685
9686
9687 /*
9688  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9689  * @vsi: VSI to be configured
9690  * @tc_map: enabled TC bitmap
9691  *
9692  * Returns 0 on success, negative value on failure
9693  */
9694 static enum i40e_status_code
9695 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9696 {
9697         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9698         struct i40e_vsi_context ctxt;
9699         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9700         enum i40e_status_code ret = I40E_SUCCESS;
9701         int i;
9702
9703         /* Check if enabled_tc is same as existing or new TCs */
9704         if (vsi->enabled_tc == tc_map)
9705                 return ret;
9706
9707         /* configure tc bandwidth */
9708         memset(&bw_data, 0, sizeof(bw_data));
9709         bw_data.tc_valid_bits = tc_map;
9710         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9711         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9712                 if (tc_map & BIT_ULL(i))
9713                         bw_data.tc_bw_credits[i] = 1;
9714         }
9715         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9716         if (ret) {
9717                 PMD_INIT_LOG(ERR,
9718                         "AQ command Config VSI BW allocation per TC failed = %d",
9719                         hw->aq.asq_last_status);
9720                 goto out;
9721         }
9722         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9723                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9724
9725         /* Update Queue Pairs Mapping for currently enabled UPs */
9726         ctxt.seid = vsi->seid;
9727         ctxt.pf_num = hw->pf_id;
9728         ctxt.vf_num = 0;
9729         ctxt.uplink_seid = vsi->uplink_seid;
9730         ctxt.info = vsi->info;
9731         i40e_get_cap(hw);
9732         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9733         if (ret)
9734                 goto out;
9735
9736         /* Update the VSI after updating the VSI queue-mapping information */
9737         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9738         if (ret) {
9739                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9740                         hw->aq.asq_last_status);
9741                 goto out;
9742         }
9743         /* update the local VSI info with updated queue map */
9744         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9745                                         sizeof(vsi->info.tc_mapping));
9746         (void)rte_memcpy(&vsi->info.queue_mapping,
9747                         &ctxt.info.queue_mapping,
9748                 sizeof(vsi->info.queue_mapping));
9749         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9750         vsi->info.valid_sections = 0;
9751
9752         /* query and update current VSI BW information */
9753         ret = i40e_vsi_get_bw_config(vsi);
9754         if (ret) {
9755                 PMD_INIT_LOG(ERR,
9756                          "Failed updating vsi bw info, err %s aq_err %s",
9757                          i40e_stat_str(hw, ret),
9758                          i40e_aq_str(hw, hw->aq.asq_last_status));
9759                 goto out;
9760         }
9761
9762         vsi->enabled_tc = tc_map;
9763
9764 out:
9765         return ret;
9766 }
9767
9768 /*
9769  * i40e_dcb_hw_configure - program the dcb setting to hw
9770  * @pf: pf the configuration is taken on
9771  * @new_cfg: new configuration
9772  * @tc_map: enabled TC bitmap
9773  *
9774  * Returns 0 on success, negative value on failure
9775  */
9776 static enum i40e_status_code
9777 i40e_dcb_hw_configure(struct i40e_pf *pf,
9778                       struct i40e_dcbx_config *new_cfg,
9779                       uint8_t tc_map)
9780 {
9781         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9782         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9783         struct i40e_vsi *main_vsi = pf->main_vsi;
9784         struct i40e_vsi_list *vsi_list;
9785         enum i40e_status_code ret;
9786         int i;
9787         uint32_t val;
9788
9789         /* Use the FW API if FW > v4.4*/
9790         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9791               (hw->aq.fw_maj_ver >= 5))) {
9792                 PMD_INIT_LOG(ERR,
9793                         "FW < v4.4, can not use FW LLDP API to configure DCB");
9794                 return I40E_ERR_FIRMWARE_API_VERSION;
9795         }
9796
9797         /* Check if need reconfiguration */
9798         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9799                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9800                 return I40E_SUCCESS;
9801         }
9802
9803         /* Copy the new config to the current config */
9804         *old_cfg = *new_cfg;
9805         old_cfg->etsrec = old_cfg->etscfg;
9806         ret = i40e_set_dcb_config(hw);
9807         if (ret) {
9808                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
9809                          i40e_stat_str(hw, ret),
9810                          i40e_aq_str(hw, hw->aq.asq_last_status));
9811                 return ret;
9812         }
9813         /* set receive Arbiter to RR mode and ETS scheme by default */
9814         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9815                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9816                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9817                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9818                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9819                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9820                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9821                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9822                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9823                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9824                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9825                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9826                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9827         }
9828         /* get local mib to check whether it is configured correctly */
9829         /* IEEE mode */
9830         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9831         /* Get Local DCB Config */
9832         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9833                                      &hw->local_dcbx_config);
9834
9835         /* if Veb is created, need to update TC of it at first */
9836         if (main_vsi->veb) {
9837                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9838                 if (ret)
9839                         PMD_INIT_LOG(WARNING,
9840                                  "Failed configuring TC for VEB seid=%d",
9841                                  main_vsi->veb->seid);
9842         }
9843         /* Update each VSI */
9844         i40e_vsi_config_tc(main_vsi, tc_map);
9845         if (main_vsi->veb) {
9846                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9847                         /* Beside main VSI and VMDQ VSIs, only enable default
9848                          * TC for other VSIs
9849                          */
9850                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9851                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9852                                                          tc_map);
9853                         else
9854                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9855                                                          I40E_DEFAULT_TCMAP);
9856                         if (ret)
9857                                 PMD_INIT_LOG(WARNING,
9858                                         "Failed configuring TC for VSI seid=%d",
9859                                         vsi_list->vsi->seid);
9860                         /* continue */
9861                 }
9862         }
9863         return I40E_SUCCESS;
9864 }
9865
9866 /*
9867  * i40e_dcb_init_configure - initial dcb config
9868  * @dev: device being configured
9869  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9870  *
9871  * Returns 0 on success, negative value on failure
9872  */
9873 static int
9874 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9875 {
9876         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9877         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9878         int i, ret = 0;
9879
9880         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9881                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9882                 return -ENOTSUP;
9883         }
9884
9885         /* DCB initialization:
9886          * Update DCB configuration from the Firmware and configure
9887          * LLDP MIB change event.
9888          */
9889         if (sw_dcb == TRUE) {
9890                 ret = i40e_init_dcb(hw);
9891                 /* If lldp agent is stopped, the return value from
9892                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9893                  * adminq status. Otherwise, it should return success.
9894                  */
9895                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9896                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9897                         memset(&hw->local_dcbx_config, 0,
9898                                 sizeof(struct i40e_dcbx_config));
9899                         /* set dcb default configuration */
9900                         hw->local_dcbx_config.etscfg.willing = 0;
9901                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9902                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9903                         hw->local_dcbx_config.etscfg.tsatable[0] =
9904                                                 I40E_IEEE_TSA_ETS;
9905                         /* all UPs mapping to TC0 */
9906                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9907                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
9908                         hw->local_dcbx_config.etsrec =
9909                                 hw->local_dcbx_config.etscfg;
9910                         hw->local_dcbx_config.pfc.willing = 0;
9911                         hw->local_dcbx_config.pfc.pfccap =
9912                                                 I40E_MAX_TRAFFIC_CLASS;
9913                         hw->local_dcbx_config.pfc.pfcenable =
9914                                                 I40E_DEFAULT_TCMAP;
9915                         /* FW needs one App to configure HW */
9916                         hw->local_dcbx_config.numapps = 1;
9917                         hw->local_dcbx_config.app[0].selector =
9918                                                 I40E_APP_SEL_ETHTYPE;
9919                         hw->local_dcbx_config.app[0].priority = 3;
9920                         hw->local_dcbx_config.app[0].protocolid =
9921                                                 I40E_APP_PROTOID_FCOE;
9922                         ret = i40e_set_dcb_config(hw);
9923                         if (ret) {
9924                                 PMD_INIT_LOG(ERR,
9925                                         "default dcb config fails. err = %d, aq_err = %d.",
9926                                         ret, hw->aq.asq_last_status);
9927                                 return -ENOSYS;
9928                         }
9929                 } else {
9930                         PMD_INIT_LOG(ERR,
9931                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9932                                 ret, hw->aq.asq_last_status);
9933                         return -ENOTSUP;
9934                 }
9935         } else {
9936                 ret = i40e_aq_start_lldp(hw, NULL);
9937                 if (ret != I40E_SUCCESS)
9938                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9939
9940                 ret = i40e_init_dcb(hw);
9941                 if (!ret) {
9942                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9943                                 PMD_INIT_LOG(ERR,
9944                                         "HW doesn't support DCBX offload.");
9945                                 return -ENOTSUP;
9946                         }
9947                 } else {
9948                         PMD_INIT_LOG(ERR,
9949                                 "DCBX configuration failed, err = %d, aq_err = %d.",
9950                                 ret, hw->aq.asq_last_status);
9951                         return -ENOTSUP;
9952                 }
9953         }
9954         return 0;
9955 }
9956
9957 /*
9958  * i40e_dcb_setup - setup dcb related config
9959  * @dev: device being configured
9960  *
9961  * Returns 0 on success, negative value on failure
9962  */
9963 static int
9964 i40e_dcb_setup(struct rte_eth_dev *dev)
9965 {
9966         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9967         struct i40e_dcbx_config dcb_cfg;
9968         uint8_t tc_map = 0;
9969         int ret = 0;
9970
9971         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9972                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9973                 return -ENOTSUP;
9974         }
9975
9976         if (pf->vf_num != 0)
9977                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9978
9979         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9980         if (ret) {
9981                 PMD_INIT_LOG(ERR, "invalid dcb config");
9982                 return -EINVAL;
9983         }
9984         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9985         if (ret) {
9986                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9987                 return -ENOSYS;
9988         }
9989
9990         return 0;
9991 }
9992
9993 static int
9994 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9995                       struct rte_eth_dcb_info *dcb_info)
9996 {
9997         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9998         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9999         struct i40e_vsi *vsi = pf->main_vsi;
10000         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10001         uint16_t bsf, tc_mapping;
10002         int i, j = 0;
10003
10004         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10005                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10006         else
10007                 dcb_info->nb_tcs = 1;
10008         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10009                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10010         for (i = 0; i < dcb_info->nb_tcs; i++)
10011                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10012
10013         /* get queue mapping if vmdq is disabled */
10014         if (!pf->nb_cfg_vmdq_vsi) {
10015                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10016                         if (!(vsi->enabled_tc & (1 << i)))
10017                                 continue;
10018                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10019                         dcb_info->tc_queue.tc_rxq[j][i].base =
10020                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10021                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10022                         dcb_info->tc_queue.tc_txq[j][i].base =
10023                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10024                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10025                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10026                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10027                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10028                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10029                 }
10030                 return 0;
10031         }
10032
10033         /* get queue mapping if vmdq is enabled */
10034         do {
10035                 vsi = pf->vmdq[j].vsi;
10036                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10037                         if (!(vsi->enabled_tc & (1 << i)))
10038                                 continue;
10039                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10040                         dcb_info->tc_queue.tc_rxq[j][i].base =
10041                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10042                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10043                         dcb_info->tc_queue.tc_txq[j][i].base =
10044                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10045                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10046                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10047                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10048                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10049                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10050                 }
10051                 j++;
10052         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10053         return 0;
10054 }
10055
10056 static int
10057 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10058 {
10059         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10060         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10061         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10062         uint16_t interval =
10063                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10064         uint16_t msix_intr;
10065
10066         msix_intr = intr_handle->intr_vec[queue_id];
10067         if (msix_intr == I40E_MISC_VEC_ID)
10068                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10069                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10070                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10071                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10072                                (interval <<
10073                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10074         else
10075                 I40E_WRITE_REG(hw,
10076                                I40E_PFINT_DYN_CTLN(msix_intr -
10077                                                    I40E_RX_VEC_START),
10078                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10079                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10080                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10081                                (interval <<
10082                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10083
10084         I40E_WRITE_FLUSH(hw);
10085         rte_intr_enable(&pci_dev->intr_handle);
10086
10087         return 0;
10088 }
10089
10090 static int
10091 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10092 {
10093         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10094         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10095         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10096         uint16_t msix_intr;
10097
10098         msix_intr = intr_handle->intr_vec[queue_id];
10099         if (msix_intr == I40E_MISC_VEC_ID)
10100                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10101         else
10102                 I40E_WRITE_REG(hw,
10103                                I40E_PFINT_DYN_CTLN(msix_intr -
10104                                                    I40E_RX_VEC_START),
10105                                0);
10106         I40E_WRITE_FLUSH(hw);
10107
10108         return 0;
10109 }
10110
10111 static int i40e_get_regs(struct rte_eth_dev *dev,
10112                          struct rte_dev_reg_info *regs)
10113 {
10114         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10115         uint32_t *ptr_data = regs->data;
10116         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10117         const struct i40e_reg_info *reg_info;
10118
10119         if (ptr_data == NULL) {
10120                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10121                 regs->width = sizeof(uint32_t);
10122                 return 0;
10123         }
10124
10125         /* The first few registers have to be read using AQ operations */
10126         reg_idx = 0;
10127         while (i40e_regs_adminq[reg_idx].name) {
10128                 reg_info = &i40e_regs_adminq[reg_idx++];
10129                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10130                         for (arr_idx2 = 0;
10131                                         arr_idx2 <= reg_info->count2;
10132                                         arr_idx2++) {
10133                                 reg_offset = arr_idx * reg_info->stride1 +
10134                                         arr_idx2 * reg_info->stride2;
10135                                 reg_offset += reg_info->base_addr;
10136                                 ptr_data[reg_offset >> 2] =
10137                                         i40e_read_rx_ctl(hw, reg_offset);
10138                         }
10139         }
10140
10141         /* The remaining registers can be read using primitives */
10142         reg_idx = 0;
10143         while (i40e_regs_others[reg_idx].name) {
10144                 reg_info = &i40e_regs_others[reg_idx++];
10145                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10146                         for (arr_idx2 = 0;
10147                                         arr_idx2 <= reg_info->count2;
10148                                         arr_idx2++) {
10149                                 reg_offset = arr_idx * reg_info->stride1 +
10150                                         arr_idx2 * reg_info->stride2;
10151                                 reg_offset += reg_info->base_addr;
10152                                 ptr_data[reg_offset >> 2] =
10153                                         I40E_READ_REG(hw, reg_offset);
10154                         }
10155         }
10156
10157         return 0;
10158 }
10159
10160 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10161 {
10162         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10163
10164         /* Convert word count to byte count */
10165         return hw->nvm.sr_size << 1;
10166 }
10167
10168 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10169                            struct rte_dev_eeprom_info *eeprom)
10170 {
10171         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10172         uint16_t *data = eeprom->data;
10173         uint16_t offset, length, cnt_words;
10174         int ret_code;
10175
10176         offset = eeprom->offset >> 1;
10177         length = eeprom->length >> 1;
10178         cnt_words = length;
10179
10180         if (offset > hw->nvm.sr_size ||
10181                 offset + length > hw->nvm.sr_size) {
10182                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10183                 return -EINVAL;
10184         }
10185
10186         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10187
10188         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10189         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10190                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10191                 return -EIO;
10192         }
10193
10194         return 0;
10195 }
10196
10197 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10198                                       struct ether_addr *mac_addr)
10199 {
10200         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10201
10202         if (!is_valid_assigned_ether_addr(mac_addr)) {
10203                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10204                 return;
10205         }
10206
10207         /* Flags: 0x3 updates port address */
10208         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10209 }
10210
10211 static int
10212 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10213 {
10214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10215         struct rte_eth_dev_data *dev_data = pf->dev_data;
10216         uint32_t frame_size = mtu + ETHER_HDR_LEN
10217                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10218         int ret = 0;
10219
10220         /* check if mtu is within the allowed range */
10221         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10222                 return -EINVAL;
10223
10224         /* mtu setting is forbidden if port is start */
10225         if (dev_data->dev_started) {
10226                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10227                             dev_data->port_id);
10228                 return -EBUSY;
10229         }
10230
10231         if (frame_size > ETHER_MAX_LEN)
10232                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10233         else
10234                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10235
10236         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10237
10238         return ret;
10239 }
10240
10241 /* Restore ethertype filter */
10242 static void
10243 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10244 {
10245         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10246         struct i40e_ethertype_filter_list
10247                 *ethertype_list = &pf->ethertype.ethertype_list;
10248         struct i40e_ethertype_filter *f;
10249         struct i40e_control_filter_stats stats;
10250         uint16_t flags;
10251
10252         TAILQ_FOREACH(f, ethertype_list, rules) {
10253                 flags = 0;
10254                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10255                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10256                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10257                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10258                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10259
10260                 memset(&stats, 0, sizeof(stats));
10261                 i40e_aq_add_rem_control_packet_filter(hw,
10262                                             f->input.mac_addr.addr_bytes,
10263                                             f->input.ether_type,
10264                                             flags, pf->main_vsi->seid,
10265                                             f->queue, 1, &stats, NULL);
10266         }
10267         PMD_DRV_LOG(INFO, "Ethertype filter:"
10268                     " mac_etype_used = %u, etype_used = %u,"
10269                     " mac_etype_free = %u, etype_free = %u",
10270                     stats.mac_etype_used, stats.etype_used,
10271                     stats.mac_etype_free, stats.etype_free);
10272 }
10273
10274 /* Restore tunnel filter */
10275 static void
10276 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10277 {
10278         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10279         struct i40e_vsi *vsi = pf->main_vsi;
10280         struct i40e_tunnel_filter_list
10281                 *tunnel_list = &pf->tunnel.tunnel_list;
10282         struct i40e_tunnel_filter *f;
10283         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10284
10285         TAILQ_FOREACH(f, tunnel_list, rules) {
10286                 memset(&cld_filter, 0, sizeof(cld_filter));
10287                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10288                 cld_filter.queue_number = f->queue;
10289                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10290         }
10291 }
10292
10293 static void
10294 i40e_filter_restore(struct i40e_pf *pf)
10295 {
10296         i40e_ethertype_filter_restore(pf);
10297         i40e_tunnel_filter_restore(pf);
10298         i40e_fdir_filter_restore(pf);
10299 }
10300
10301 static bool
10302 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10303 {
10304         if (strcmp(dev->driver->pci_drv.driver.name,
10305                    drv->pci_drv.driver.name))
10306                 return false;
10307
10308         return true;
10309 }
10310
10311 int
10312 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10313 {
10314         struct rte_eth_dev *dev;
10315         struct i40e_pf *pf;
10316
10317         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10318
10319         dev = &rte_eth_devices[port];
10320
10321         if (!is_device_supported(dev, &rte_i40e_pmd))
10322                 return -ENOTSUP;
10323
10324         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10325
10326         if (vf >= pf->vf_num || !pf->vfs) {
10327                 PMD_DRV_LOG(ERR, "Invalid argument.");
10328                 return -EINVAL;
10329         }
10330
10331         i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10332
10333         return 0;
10334 }
10335
10336 int
10337 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10338 {
10339         struct rte_eth_dev *dev;
10340         struct i40e_pf *pf;
10341         struct i40e_vsi *vsi;
10342         struct i40e_hw *hw;
10343         struct i40e_vsi_context ctxt;
10344         int ret;
10345
10346         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10347
10348         dev = &rte_eth_devices[port];
10349
10350         if (!is_device_supported(dev, &rte_i40e_pmd))
10351                 return -ENOTSUP;
10352
10353         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10354
10355         if (vf_id >= pf->vf_num || !pf->vfs) {
10356                 PMD_DRV_LOG(ERR, "Invalid argument.");
10357                 return -EINVAL;
10358         }
10359
10360         vsi = pf->vfs[vf_id].vsi;
10361         if (!vsi) {
10362                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10363                 return -EINVAL;
10364         }
10365
10366         /* Check if it has been already on or off */
10367         if (vsi->info.valid_sections &
10368                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10369                 if (on) {
10370                         if ((vsi->info.sec_flags &
10371                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10372                             I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10373                                 return 0; /* already on */
10374                 } else {
10375                         if ((vsi->info.sec_flags &
10376                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10377                                 return 0; /* already off */
10378                 }
10379         }
10380
10381         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10382         if (on)
10383                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10384         else
10385                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10386
10387         memset(&ctxt, 0, sizeof(ctxt));
10388         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10389         ctxt.seid = vsi->seid;
10390
10391         hw = I40E_VSI_TO_HW(vsi);
10392         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10393         if (ret != I40E_SUCCESS) {
10394                 ret = -ENOTSUP;
10395                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10396         }
10397
10398         return ret;
10399 }
10400
10401 static int
10402 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10403 {
10404         uint32_t j, k;
10405         uint16_t vlan_id;
10406         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10407         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10408         int ret;
10409
10410         for (j = 0; j < I40E_VFTA_SIZE; j++) {
10411                 if (!vsi->vfta[j])
10412                         continue;
10413
10414                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10415                         if (!(vsi->vfta[j] & (1 << k)))
10416                                 continue;
10417
10418                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10419                         if (!vlan_id)
10420                                 continue;
10421
10422                         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10423                         if (add)
10424                                 ret = i40e_aq_add_vlan(hw, vsi->seid,
10425                                                        &vlan_data, 1, NULL);
10426                         else
10427                                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10428                                                           &vlan_data, 1, NULL);
10429                         if (ret != I40E_SUCCESS) {
10430                                 PMD_DRV_LOG(ERR,
10431                                             "Failed to add/rm vlan filter");
10432                                 return ret;
10433                         }
10434                 }
10435         }
10436
10437         return I40E_SUCCESS;
10438 }
10439
10440 int
10441 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10442 {
10443         struct rte_eth_dev *dev;
10444         struct i40e_pf *pf;
10445         struct i40e_vsi *vsi;
10446         struct i40e_hw *hw;
10447         struct i40e_vsi_context ctxt;
10448         int ret;
10449
10450         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10451
10452         dev = &rte_eth_devices[port];
10453
10454         if (!is_device_supported(dev, &rte_i40e_pmd))
10455                 return -ENOTSUP;
10456
10457         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10458
10459         if (vf_id >= pf->vf_num || !pf->vfs) {
10460                 PMD_DRV_LOG(ERR, "Invalid argument.");
10461                 return -EINVAL;
10462         }
10463
10464         vsi = pf->vfs[vf_id].vsi;
10465         if (!vsi) {
10466                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10467                 return -EINVAL;
10468         }
10469
10470         /* Check if it has been already on or off */
10471         if (vsi->vlan_anti_spoof_on == on)
10472                 return 0; /* already on or off */
10473
10474         vsi->vlan_anti_spoof_on = on;
10475         ret = i40e_add_rm_all_vlan_filter(vsi, on);
10476         if (ret) {
10477                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filters.");
10478                 return -ENOTSUP;
10479         }
10480
10481         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10482         if (on)
10483                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10484         else
10485                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10486
10487         memset(&ctxt, 0, sizeof(ctxt));
10488         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10489         ctxt.seid = vsi->seid;
10490
10491         hw = I40E_VSI_TO_HW(vsi);
10492         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10493         if (ret != I40E_SUCCESS) {
10494                 ret = -ENOTSUP;
10495                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10496         }
10497
10498         return ret;
10499 }
10500
10501 static int
10502 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10503 {
10504         struct i40e_mac_filter *f;
10505         struct i40e_macvlan_filter *mv_f;
10506         int i, vlan_num;
10507         enum rte_mac_filter_type filter_type;
10508         int ret = I40E_SUCCESS;
10509         void *temp;
10510
10511         /* remove all the MACs */
10512         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10513                 vlan_num = vsi->vlan_num;
10514                 filter_type = f->mac_info.filter_type;
10515                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10516                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10517                         if (vlan_num == 0) {
10518                                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10519                                 return I40E_ERR_PARAM;
10520                         }
10521                 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10522                            filter_type == RTE_MAC_HASH_MATCH)
10523                         vlan_num = 1;
10524
10525                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10526                 if (!mv_f) {
10527                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10528                         return I40E_ERR_NO_MEMORY;
10529                 }
10530
10531                 for (i = 0; i < vlan_num; i++) {
10532                         mv_f[i].filter_type = filter_type;
10533                         (void)rte_memcpy(&mv_f[i].macaddr,
10534                                          &f->mac_info.mac_addr,
10535                                          ETH_ADDR_LEN);
10536                 }
10537                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10538                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10539                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10540                                                          &f->mac_info.mac_addr);
10541                         if (ret != I40E_SUCCESS) {
10542                                 rte_free(mv_f);
10543                                 return ret;
10544                         }
10545                 }
10546
10547                 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10548                 if (ret != I40E_SUCCESS) {
10549                         rte_free(mv_f);
10550                         return ret;
10551                 }
10552
10553                 rte_free(mv_f);
10554                 ret = I40E_SUCCESS;
10555         }
10556
10557         return ret;
10558 }
10559
10560 static int
10561 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10562 {
10563         struct i40e_mac_filter *f;
10564         struct i40e_macvlan_filter *mv_f;
10565         int i, vlan_num = 0;
10566         int ret = I40E_SUCCESS;
10567         void *temp;
10568
10569         /* restore all the MACs */
10570         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10571                 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10572                     (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10573                         /**
10574                          * If vlan_num is 0, that's the first time to add mac,
10575                          * set mask for vlan_id 0.
10576                          */
10577                         if (vsi->vlan_num == 0) {
10578                                 i40e_set_vlan_filter(vsi, 0, 1);
10579                                 vsi->vlan_num = 1;
10580                         }
10581                         vlan_num = vsi->vlan_num;
10582                 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10583                            (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10584                         vlan_num = 1;
10585
10586                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10587                 if (!mv_f) {
10588                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10589                         return I40E_ERR_NO_MEMORY;
10590                 }
10591
10592                 for (i = 0; i < vlan_num; i++) {
10593                         mv_f[i].filter_type = f->mac_info.filter_type;
10594                         (void)rte_memcpy(&mv_f[i].macaddr,
10595                                          &f->mac_info.mac_addr,
10596                                          ETH_ADDR_LEN);
10597                 }
10598
10599                 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10600                     f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10601                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10602                                                          &f->mac_info.mac_addr);
10603                         if (ret != I40E_SUCCESS) {
10604                                 rte_free(mv_f);
10605                                 return ret;
10606                         }
10607                 }
10608
10609                 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10610                 if (ret != I40E_SUCCESS) {
10611                         rte_free(mv_f);
10612                         return ret;
10613                 }
10614
10615                 rte_free(mv_f);
10616                 ret = I40E_SUCCESS;
10617         }
10618
10619         return ret;
10620 }
10621
10622 static int
10623 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10624 {
10625         struct i40e_vsi_context ctxt;
10626         struct i40e_hw *hw;
10627         int ret;
10628
10629         if (!vsi)
10630                 return -EINVAL;
10631
10632         hw = I40E_VSI_TO_HW(vsi);
10633
10634         /* Use the FW API if FW >= v5.0 */
10635         if (hw->aq.fw_maj_ver < 5) {
10636                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10637                 return -ENOTSUP;
10638         }
10639
10640         /* Check if it has been already on or off */
10641         if (vsi->info.valid_sections &
10642                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10643                 if (on) {
10644                         if ((vsi->info.switch_id &
10645                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10646                             I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10647                                 return 0; /* already on */
10648                 } else {
10649                         if ((vsi->info.switch_id &
10650                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10651                                 return 0; /* already off */
10652                 }
10653         }
10654
10655         /* remove all the MAC and VLAN first */
10656         ret = i40e_vsi_rm_mac_filter(vsi);
10657         if (ret) {
10658                 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10659                 return ret;
10660         }
10661         if (vsi->vlan_anti_spoof_on) {
10662                 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10663                 if (ret) {
10664                         PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10665                         return ret;
10666                 }
10667         }
10668
10669         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10670         if (on)
10671                 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10672         else
10673                 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10674
10675         memset(&ctxt, 0, sizeof(ctxt));
10676         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10677         ctxt.seid = vsi->seid;
10678
10679         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10680         if (ret != I40E_SUCCESS) {
10681                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10682                 return ret;
10683         }
10684
10685         /* add all the MAC and VLAN back */
10686         ret = i40e_vsi_restore_mac_filter(vsi);
10687         if (ret)
10688                 return ret;
10689         if (vsi->vlan_anti_spoof_on) {
10690                 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10691                 if (ret)
10692                         return ret;
10693         }
10694
10695         return ret;
10696 }
10697
10698 int
10699 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10700 {
10701         struct rte_eth_dev *dev;
10702         struct i40e_pf *pf;
10703         struct i40e_pf_vf *vf;
10704         struct i40e_vsi *vsi;
10705         uint16_t vf_id;
10706         int ret;
10707
10708         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10709
10710         dev = &rte_eth_devices[port];
10711
10712         if (!is_device_supported(dev, &rte_i40e_pmd))
10713                 return -ENOTSUP;
10714
10715         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10716
10717         /* setup PF TX loopback */
10718         vsi = pf->main_vsi;
10719         ret = i40e_vsi_set_tx_loopback(vsi, on);
10720         if (ret)
10721                 return -ENOTSUP;
10722
10723         /* setup TX loopback for all the VFs */
10724         if (!pf->vfs) {
10725                 /* if no VF, do nothing. */
10726                 return 0;
10727         }
10728
10729         for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10730                 vf = &pf->vfs[vf_id];
10731                 vsi = vf->vsi;
10732
10733                 ret = i40e_vsi_set_tx_loopback(vsi, on);
10734                 if (ret)
10735                         return -ENOTSUP;
10736         }
10737
10738         return ret;
10739 }
10740
10741 int
10742 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10743 {
10744         struct rte_eth_dev *dev;
10745         struct i40e_pf *pf;
10746         struct i40e_vsi *vsi;
10747         struct i40e_hw *hw;
10748         int ret;
10749
10750         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10751
10752         dev = &rte_eth_devices[port];
10753
10754         if (!is_device_supported(dev, &rte_i40e_pmd))
10755                 return -ENOTSUP;
10756
10757         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10758
10759         if (vf_id >= pf->vf_num || !pf->vfs) {
10760                 PMD_DRV_LOG(ERR, "Invalid argument.");
10761                 return -EINVAL;
10762         }
10763
10764         vsi = pf->vfs[vf_id].vsi;
10765         if (!vsi) {
10766                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10767                 return -EINVAL;
10768         }
10769
10770         hw = I40E_VSI_TO_HW(vsi);
10771
10772         ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10773                                                   on, NULL, true);
10774         if (ret != I40E_SUCCESS) {
10775                 ret = -ENOTSUP;
10776                 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10777         }
10778
10779         return ret;
10780 }
10781
10782 int
10783 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10784 {
10785         struct rte_eth_dev *dev;
10786         struct i40e_pf *pf;
10787         struct i40e_vsi *vsi;
10788         struct i40e_hw *hw;
10789         int ret;
10790
10791         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10792
10793         dev = &rte_eth_devices[port];
10794
10795         if (!is_device_supported(dev, &rte_i40e_pmd))
10796                 return -ENOTSUP;
10797
10798         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10799
10800         if (vf_id >= pf->vf_num || !pf->vfs) {
10801                 PMD_DRV_LOG(ERR, "Invalid argument.");
10802                 return -EINVAL;
10803         }
10804
10805         vsi = pf->vfs[vf_id].vsi;
10806         if (!vsi) {
10807                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10808                 return -EINVAL;
10809         }
10810
10811         hw = I40E_VSI_TO_HW(vsi);
10812
10813         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10814                                                     on, NULL);
10815         if (ret != I40E_SUCCESS) {
10816                 ret = -ENOTSUP;
10817                 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10818         }
10819
10820         return ret;
10821 }
10822
10823 int
10824 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
10825                              struct ether_addr *mac_addr)
10826 {
10827         struct i40e_mac_filter *f;
10828         struct rte_eth_dev *dev;
10829         struct i40e_pf_vf *vf;
10830         struct i40e_vsi *vsi;
10831         struct i40e_pf *pf;
10832         void *temp;
10833
10834         if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
10835                 return -EINVAL;
10836
10837         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10838
10839         dev = &rte_eth_devices[port];
10840
10841         if (!is_device_supported(dev, &rte_i40e_pmd))
10842                 return -ENOTSUP;
10843
10844         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10845
10846         if (vf_id >= pf->vf_num || !pf->vfs)
10847                 return -EINVAL;
10848
10849         vf = &pf->vfs[vf_id];
10850         vsi = vf->vsi;
10851         if (!vsi) {
10852                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10853                 return -EINVAL;
10854         }
10855
10856         ether_addr_copy(mac_addr, &vf->mac_addr);
10857
10858         /* Remove all existing mac */
10859         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
10860                 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
10861
10862         return 0;
10863 }
10864
10865 /* Set vlan strip on/off for specific VF from host */
10866 int
10867 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
10868 {
10869         struct rte_eth_dev *dev;
10870         struct i40e_pf *pf;
10871         struct i40e_vsi *vsi;
10872         int ret;
10873
10874         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10875
10876         dev = &rte_eth_devices[port];
10877
10878         if (!is_device_supported(dev, &rte_i40e_pmd))
10879                 return -ENOTSUP;
10880
10881         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10882
10883         if (vf_id >= pf->vf_num || !pf->vfs) {
10884                 PMD_DRV_LOG(ERR, "Invalid argument.");
10885                 return -EINVAL;
10886         }
10887
10888         vsi = pf->vfs[vf_id].vsi;
10889
10890         if (!vsi)
10891                 return -EINVAL;
10892
10893         ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
10894         if (ret != I40E_SUCCESS) {
10895                 ret = -ENOTSUP;
10896                 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
10897         }
10898
10899         return ret;
10900 }
10901
10902 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
10903                                     uint16_t vlan_id)
10904 {
10905         struct rte_eth_dev *dev;
10906         struct i40e_pf *pf;
10907         struct i40e_hw *hw;
10908         struct i40e_vsi *vsi;
10909         struct i40e_vsi_context ctxt;
10910         int ret;
10911
10912         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10913
10914         if (vlan_id > ETHER_MAX_VLAN_ID) {
10915                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
10916                 return -EINVAL;
10917         }
10918
10919         dev = &rte_eth_devices[port];
10920
10921         if (!is_device_supported(dev, &rte_i40e_pmd))
10922                 return -ENOTSUP;
10923
10924         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10925         hw = I40E_PF_TO_HW(pf);
10926
10927         /**
10928          * return -ENODEV if SRIOV not enabled, VF number not configured
10929          * or no queue assigned.
10930          */
10931         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10932             pf->vf_nb_qps == 0)
10933                 return -ENODEV;
10934
10935         if (vf_id >= pf->vf_num || !pf->vfs) {
10936                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10937                 return -EINVAL;
10938         }
10939
10940         vsi = pf->vfs[vf_id].vsi;
10941         if (!vsi) {
10942                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10943                 return -EINVAL;
10944         }
10945
10946         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
10947         vsi->info.pvid = vlan_id;
10948         if (vlan_id > 0)
10949                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
10950         else
10951                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
10952
10953         memset(&ctxt, 0, sizeof(ctxt));
10954         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10955         ctxt.seid = vsi->seid;
10956
10957         hw = I40E_VSI_TO_HW(vsi);
10958         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10959         if (ret != I40E_SUCCESS) {
10960                 ret = -ENOTSUP;
10961                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10962         }
10963
10964         return ret;
10965 }
10966
10967 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
10968                                   uint8_t on)
10969 {
10970         struct rte_eth_dev *dev;
10971         struct i40e_pf *pf;
10972         struct i40e_vsi *vsi;
10973         struct i40e_hw *hw;
10974         int ret;
10975
10976         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10977
10978         if (on > 1) {
10979                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
10980                 return -EINVAL;
10981         }
10982
10983         dev = &rte_eth_devices[port];
10984
10985         if (!is_device_supported(dev, &rte_i40e_pmd))
10986                 return -ENOTSUP;
10987
10988         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10989         hw = I40E_PF_TO_HW(pf);
10990
10991         if (vf_id >= pf->vf_num || !pf->vfs) {
10992                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10993                 return -EINVAL;
10994         }
10995
10996         /**
10997          * return -ENODEV if SRIOV not enabled, VF number not configured
10998          * or no queue assigned.
10999          */
11000         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11001             pf->vf_nb_qps == 0) {
11002                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11003                 return -ENODEV;
11004         }
11005
11006         vsi = pf->vfs[vf_id].vsi;
11007         if (!vsi) {
11008                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11009                 return -EINVAL;
11010         }
11011
11012         hw = I40E_VSI_TO_HW(vsi);
11013
11014         ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, on, NULL);
11015         if (ret != I40E_SUCCESS) {
11016                 ret = -ENOTSUP;
11017                 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11018         }
11019
11020         return ret;
11021 }
11022
11023 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11024 {
11025         struct rte_eth_dev *dev;
11026         struct i40e_pf *pf;
11027         struct i40e_hw *hw;
11028         struct i40e_vsi *vsi;
11029         struct i40e_vsi_context ctxt;
11030         int ret;
11031
11032         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11033
11034         if (on > 1) {
11035                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11036                 return -EINVAL;
11037         }
11038
11039         dev = &rte_eth_devices[port];
11040
11041         if (!is_device_supported(dev, &rte_i40e_pmd))
11042                 return -ENOTSUP;
11043
11044         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11045         hw = I40E_PF_TO_HW(pf);
11046
11047         /**
11048          * return -ENODEV if SRIOV not enabled, VF number not configured
11049          * or no queue assigned.
11050          */
11051         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11052             pf->vf_nb_qps == 0) {
11053                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11054                 return -ENODEV;
11055         }
11056
11057         if (vf_id >= pf->vf_num || !pf->vfs) {
11058                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11059                 return -EINVAL;
11060         }
11061
11062         vsi = pf->vfs[vf_id].vsi;
11063         if (!vsi) {
11064                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11065                 return -EINVAL;
11066         }
11067
11068         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11069         if (on) {
11070                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11071                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11072         } else {
11073                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11074                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11075         }
11076
11077         memset(&ctxt, 0, sizeof(ctxt));
11078         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11079         ctxt.seid = vsi->seid;
11080
11081         hw = I40E_VSI_TO_HW(vsi);
11082         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11083         if (ret != I40E_SUCCESS) {
11084                 ret = -ENOTSUP;
11085                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11086         }
11087
11088         return ret;
11089 }
11090
11091 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11092                                     uint64_t vf_mask, uint8_t on)
11093 {
11094         struct rte_eth_dev *dev;
11095         struct i40e_pf *pf;
11096         struct i40e_hw *hw;
11097         uint16_t vf_idx;
11098         int ret = I40E_SUCCESS;
11099
11100         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11101
11102         dev = &rte_eth_devices[port];
11103
11104         if (!is_device_supported(dev, &rte_i40e_pmd))
11105                 return -ENOTSUP;
11106
11107         if (vlan_id > ETHER_MAX_VLAN_ID) {
11108                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11109                 return -EINVAL;
11110         }
11111
11112         if (vf_mask == 0) {
11113                 PMD_DRV_LOG(ERR, "No VF.");
11114                 return -EINVAL;
11115         }
11116
11117         if (on > 1) {
11118                 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11119                 return -EINVAL;
11120         }
11121
11122         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11123         hw = I40E_PF_TO_HW(pf);
11124
11125         /**
11126          * return -ENODEV if SRIOV not enabled, VF number not configured
11127          * or no queue assigned.
11128          */
11129         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11130             pf->vf_nb_qps == 0) {
11131                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11132                 return -ENODEV;
11133         }
11134
11135         for (vf_idx = 0; vf_idx < 64 && ret == I40E_SUCCESS; vf_idx++) {
11136                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11137                         if (on)
11138                                 ret = i40e_vsi_add_vlan(pf->vfs[vf_idx].vsi,
11139                                                         vlan_id);
11140                         else
11141                                 ret = i40e_vsi_delete_vlan(pf->vfs[vf_idx].vsi,
11142                                                            vlan_id);
11143                 }
11144         }
11145
11146         if (ret != I40E_SUCCESS) {
11147                 ret = -ENOTSUP;
11148                 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11149         }
11150
11151         return ret;
11152 }
11153
11154 int
11155 rte_pmd_i40e_get_vf_stats(uint8_t port,
11156                           uint16_t vf_id,
11157                           struct rte_eth_stats *stats)
11158 {
11159         struct rte_eth_dev *dev;
11160         struct i40e_pf *pf;
11161         struct i40e_vsi *vsi;
11162
11163         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11164
11165         dev = &rte_eth_devices[port];
11166
11167         if (!is_device_supported(dev, &rte_i40e_pmd))
11168                 return -ENOTSUP;
11169
11170         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11171
11172         if (vf_id >= pf->vf_num || !pf->vfs) {
11173                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11174                 return -EINVAL;
11175         }
11176
11177         vsi = pf->vfs[vf_id].vsi;
11178         if (!vsi) {
11179                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11180                 return -EINVAL;
11181         }
11182
11183         i40e_update_vsi_stats(vsi);
11184
11185         stats->ipackets = vsi->eth_stats.rx_unicast +
11186                         vsi->eth_stats.rx_multicast +
11187                         vsi->eth_stats.rx_broadcast;
11188         stats->opackets = vsi->eth_stats.tx_unicast +
11189                         vsi->eth_stats.tx_multicast +
11190                         vsi->eth_stats.tx_broadcast;
11191         stats->ibytes   = vsi->eth_stats.rx_bytes;
11192         stats->obytes   = vsi->eth_stats.tx_bytes;
11193         stats->ierrors  = vsi->eth_stats.rx_discards;
11194         stats->oerrors  = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11195
11196         return 0;
11197 }
11198
11199 int
11200 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11201                             uint16_t vf_id)
11202 {
11203         struct rte_eth_dev *dev;
11204         struct i40e_pf *pf;
11205         struct i40e_vsi *vsi;
11206
11207         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11208
11209         dev = &rte_eth_devices[port];
11210
11211         if (!is_device_supported(dev, &rte_i40e_pmd))
11212                 return -ENOTSUP;
11213
11214         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11215
11216         if (vf_id >= pf->vf_num || !pf->vfs) {
11217                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11218                 return -EINVAL;
11219         }
11220
11221         vsi = pf->vfs[vf_id].vsi;
11222         if (!vsi) {
11223                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11224                 return -EINVAL;
11225         }
11226
11227         vsi->offset_loaded = false;
11228         i40e_update_vsi_stats(vsi);
11229
11230         return 0;
11231 }