4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
54 #include <rte_hash_crc.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_adminq_cmd.h"
59 #include "base/i40e_type.h"
60 #include "base/i40e_register.h"
61 #include "base/i40e_dcb.h"
62 #include "i40e_ethdev.h"
63 #include "i40e_rxtx.h"
65 #include "i40e_regs.h"
66 #include "rte_pmd_i40e.h"
68 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
69 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
71 #define I40E_CLEAR_PXE_WAIT_MS 200
73 /* Maximun number of capability elements */
74 #define I40E_MAX_CAP_ELE_NUM 128
76 /* Wait count and inteval */
77 #define I40E_CHK_Q_ENA_COUNT 1000
78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
80 /* Maximun number of VSI */
81 #define I40E_MAX_NUM_VSIS (384UL)
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
114 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
115 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
116 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
118 #define I40E_FLOW_TYPES ( \
119 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
124 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
129 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
131 /* Additional timesync values. */
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
137 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
139 #define I40E_MAX_PERCENT 100
140 #define I40E_DEFAULT_DCB_APP_NUM 1
141 #define I40E_DEFAULT_DCB_APP_PRIO 3
144 * Below are values for writing un-exposed registers suggested
147 /* Destination MAC address */
148 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
149 /* Source MAC address */
150 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
152 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
155 /* Single VLAN tag in the inner L2 header */
156 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
157 /* Source IPv4 address */
158 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
159 /* Destination IPv4 address */
160 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
161 /* Source IPv4 address for X722 */
162 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
163 /* Destination IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
165 /* IPv4 Protocol for X722 */
166 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
167 /* IPv4 Time to Live for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
169 /* IPv4 Type of Service (TOS) */
170 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
172 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
173 /* IPv4 Time to Live */
174 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
175 /* Source IPv6 address */
176 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
177 /* Destination IPv6 address */
178 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
179 /* IPv6 Traffic Class (TC) */
180 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
181 /* IPv6 Next Header */
182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
186 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
187 /* Destination L4 port */
188 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
189 /* SCTP verification tag */
190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
193 /* Source port of tunneling UDP */
194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
195 /* Destination port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
197 /* UDP Tunneling ID, NVGRE/GRE key */
198 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
199 /* Last ether type */
200 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
201 /* Tunneling outer destination IPv4 address */
202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
203 /* Tunneling outer destination IPv6 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
205 /* 1st word of flex payload */
206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
207 /* 2nd word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
209 /* 3rd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
211 /* 4th word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
213 /* 5th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
215 /* 6th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
217 /* 7th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
219 /* 8th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
221 /* all 8 words flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
223 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
225 #define I40E_TRANSLATE_INSET 0
226 #define I40E_TRANSLATE_REG 1
228 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
229 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
230 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
231 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
233 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
235 /* PCI offset for querying capability */
236 #define PCI_DEV_CAP_REG 0xA4
237 /* PCI offset for enabling/disabling Extended Tag */
238 #define PCI_DEV_CTRL_REG 0xA8
239 /* Bit mask of Extended Tag capability */
240 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
241 /* Bit shift of Extended Tag enable/disable */
242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
243 /* Bit mask of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
248 static int i40e_dev_configure(struct rte_eth_dev *dev);
249 static int i40e_dev_start(struct rte_eth_dev *dev);
250 static void i40e_dev_stop(struct rte_eth_dev *dev);
251 static void i40e_dev_close(struct rte_eth_dev *dev);
252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
261 struct rte_eth_xstat *xstats, unsigned n);
262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
263 struct rte_eth_xstat_name *xstats_names,
265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
271 char *fw_version, size_t fw_size);
272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
273 struct rte_eth_dev_info *dev_info);
274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
278 enum rte_vlan_type vlan_type,
280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
288 struct rte_eth_fc_conf *fc_conf);
289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_pfc_conf *pfc_conf);
293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
299 struct rte_eth_rss_reta_entry64 *reta_conf,
301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
305 static int i40e_get_cap(struct i40e_hw *hw);
306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
307 static int i40e_pf_setup(struct i40e_pf *pf);
308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
313 bool offset_loaded, uint64_t *offset, uint64_t *stat);
314 static void i40e_stat_update_48(struct i40e_hw *hw,
320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
339 struct ether_addr *addr);
340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
341 struct i40e_macvlan_filter *mv_f,
344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
346 struct rte_eth_rss_conf *rss_conf);
347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
348 struct rte_eth_rss_conf *rss_conf);
349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
350 struct rte_eth_udp_tunnel *udp_tunnel);
351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
352 struct rte_eth_udp_tunnel *udp_tunnel);
353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
358 enum rte_filter_type filter_type,
359 enum rte_filter_op filter_op,
361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
362 struct rte_eth_dcb_info *dcb_info);
363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
364 static void i40e_configure_registers(struct i40e_hw *hw);
365 static void i40e_hw_init(struct rte_eth_dev *dev);
366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
368 struct rte_eth_mirror_conf *mirror_conf,
369 uint8_t sw_id, uint8_t on);
370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
375 struct timespec *timestamp,
377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
378 struct timespec *timestamp);
379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
384 struct timespec *timestamp);
385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
386 const struct timespec *timestamp);
388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
393 static int i40e_get_regs(struct rte_eth_dev *dev,
394 struct rte_dev_reg_info *regs);
396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
399 struct rte_dev_eeprom_info *eeprom);
401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
402 struct ether_addr *mac_addr);
404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
406 static int i40e_ethertype_filter_convert(
407 const struct rte_eth_ethertype_filter *input,
408 struct i40e_ethertype_filter *filter);
409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
410 struct i40e_ethertype_filter *filter);
412 static int i40e_tunnel_filter_convert(
413 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
414 struct i40e_tunnel_filter *tunnel_filter);
415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
416 struct i40e_tunnel_filter *tunnel_filter);
418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
420 static void i40e_filter_restore(struct i40e_pf *pf);
422 static const struct rte_pci_id pci_id_i40e_map[] = {
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
443 { .vendor_id = 0, /* sentinel */ },
446 static const struct eth_dev_ops i40e_eth_dev_ops = {
447 .dev_configure = i40e_dev_configure,
448 .dev_start = i40e_dev_start,
449 .dev_stop = i40e_dev_stop,
450 .dev_close = i40e_dev_close,
451 .promiscuous_enable = i40e_dev_promiscuous_enable,
452 .promiscuous_disable = i40e_dev_promiscuous_disable,
453 .allmulticast_enable = i40e_dev_allmulticast_enable,
454 .allmulticast_disable = i40e_dev_allmulticast_disable,
455 .dev_set_link_up = i40e_dev_set_link_up,
456 .dev_set_link_down = i40e_dev_set_link_down,
457 .link_update = i40e_dev_link_update,
458 .stats_get = i40e_dev_stats_get,
459 .xstats_get = i40e_dev_xstats_get,
460 .xstats_get_names = i40e_dev_xstats_get_names,
461 .stats_reset = i40e_dev_stats_reset,
462 .xstats_reset = i40e_dev_stats_reset,
463 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
464 .fw_version_get = i40e_fw_version_get,
465 .dev_infos_get = i40e_dev_info_get,
466 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
467 .vlan_filter_set = i40e_vlan_filter_set,
468 .vlan_tpid_set = i40e_vlan_tpid_set,
469 .vlan_offload_set = i40e_vlan_offload_set,
470 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
471 .vlan_pvid_set = i40e_vlan_pvid_set,
472 .rx_queue_start = i40e_dev_rx_queue_start,
473 .rx_queue_stop = i40e_dev_rx_queue_stop,
474 .tx_queue_start = i40e_dev_tx_queue_start,
475 .tx_queue_stop = i40e_dev_tx_queue_stop,
476 .rx_queue_setup = i40e_dev_rx_queue_setup,
477 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
478 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
479 .rx_queue_release = i40e_dev_rx_queue_release,
480 .rx_queue_count = i40e_dev_rx_queue_count,
481 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
482 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
483 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
484 .tx_queue_setup = i40e_dev_tx_queue_setup,
485 .tx_queue_release = i40e_dev_tx_queue_release,
486 .dev_led_on = i40e_dev_led_on,
487 .dev_led_off = i40e_dev_led_off,
488 .flow_ctrl_get = i40e_flow_ctrl_get,
489 .flow_ctrl_set = i40e_flow_ctrl_set,
490 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
491 .mac_addr_add = i40e_macaddr_add,
492 .mac_addr_remove = i40e_macaddr_remove,
493 .reta_update = i40e_dev_rss_reta_update,
494 .reta_query = i40e_dev_rss_reta_query,
495 .rss_hash_update = i40e_dev_rss_hash_update,
496 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
497 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
498 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
499 .filter_ctrl = i40e_dev_filter_ctrl,
500 .rxq_info_get = i40e_rxq_info_get,
501 .txq_info_get = i40e_txq_info_get,
502 .mirror_rule_set = i40e_mirror_rule_set,
503 .mirror_rule_reset = i40e_mirror_rule_reset,
504 .timesync_enable = i40e_timesync_enable,
505 .timesync_disable = i40e_timesync_disable,
506 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
507 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
508 .get_dcb_info = i40e_dev_get_dcb_info,
509 .timesync_adjust_time = i40e_timesync_adjust_time,
510 .timesync_read_time = i40e_timesync_read_time,
511 .timesync_write_time = i40e_timesync_write_time,
512 .get_reg = i40e_get_regs,
513 .get_eeprom_length = i40e_get_eeprom_length,
514 .get_eeprom = i40e_get_eeprom,
515 .mac_addr_set = i40e_set_default_mac_addr,
516 .mtu_set = i40e_dev_mtu_set,
519 /* store statistics names and its offset in stats structure */
520 struct rte_i40e_xstats_name_off {
521 char name[RTE_ETH_XSTATS_NAME_SIZE];
525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
526 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
527 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
528 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
529 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
530 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
531 rx_unknown_protocol)},
532 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
533 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
534 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
535 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
539 sizeof(rte_i40e_stats_strings[0]))
541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
542 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
543 tx_dropped_link_down)},
544 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
545 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
547 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
548 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
550 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
552 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
554 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
555 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
556 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
557 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
558 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
559 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
575 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
576 mac_short_packet_dropped)},
577 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
580 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
581 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
593 {"rx_flow_director_atr_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
595 {"rx_flow_director_sb_match_packets",
596 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
597 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
601 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
603 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
608 sizeof(rte_i40e_hw_port_strings[0]))
610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
611 {"xon_packets", offsetof(struct i40e_hw_port_stats,
613 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
618 sizeof(rte_i40e_rxq_prio_strings[0]))
620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
621 {"xon_packets", offsetof(struct i40e_hw_port_stats,
623 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
625 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
626 priority_xon_2_xoff)},
629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
630 sizeof(rte_i40e_txq_prio_strings[0]))
632 static struct eth_driver rte_i40e_pmd = {
634 .id_table = pci_id_i40e_map,
635 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
636 .probe = rte_eth_dev_pci_probe,
637 .remove = rte_eth_dev_pci_remove,
639 .eth_dev_init = eth_i40e_dev_init,
640 .eth_dev_uninit = eth_i40e_dev_uninit,
641 .dev_private_size = sizeof(struct i40e_adapter),
645 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
646 struct rte_eth_link *link)
648 struct rte_eth_link *dst = link;
649 struct rte_eth_link *src = &(dev->data->dev_link);
651 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
652 *(uint64_t *)src) == 0)
659 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
660 struct rte_eth_link *link)
662 struct rte_eth_link *dst = &(dev->data->dev_link);
663 struct rte_eth_link *src = link;
665 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
666 *(uint64_t *)src) == 0)
672 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
673 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
674 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
676 #ifndef I40E_GLQF_ORT
677 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
679 #ifndef I40E_GLQF_PIT
680 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
683 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
686 * Initialize registers for flexible payload, which should be set by NVM.
687 * This should be removed from code once it is fixed in NVM.
689 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
690 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
691 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
692 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
693 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
694 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
695 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
696 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
697 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
698 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
699 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
700 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
702 /* Initialize registers for parsing packet type of QinQ */
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
704 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
707 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
710 * Add a ethertype filter to drop all flow control frames transmitted
714 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
716 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
717 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
718 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
719 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
722 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
723 I40E_FLOW_CONTROL_ETHERTYPE, flags,
724 pf->main_vsi_seid, 0,
728 "Failed to add filter to drop flow control frames from VSIs.");
732 floating_veb_list_handler(__rte_unused const char *key,
733 const char *floating_veb_value,
737 unsigned int count = 0;
740 bool *vf_floating_veb = opaque;
742 while (isblank(*floating_veb_value))
743 floating_veb_value++;
745 /* Reset floating VEB configuration for VFs */
746 for (idx = 0; idx < I40E_MAX_VF; idx++)
747 vf_floating_veb[idx] = false;
751 while (isblank(*floating_veb_value))
752 floating_veb_value++;
753 if (*floating_veb_value == '\0')
756 idx = strtoul(floating_veb_value, &end, 10);
757 if (errno || end == NULL)
759 while (isblank(*end))
763 } else if ((*end == ';') || (*end == '\0')) {
765 if (min == I40E_MAX_VF)
767 if (max >= I40E_MAX_VF)
768 max = I40E_MAX_VF - 1;
769 for (idx = min; idx <= max; idx++) {
770 vf_floating_veb[idx] = true;
777 floating_veb_value = end + 1;
778 } while (*end != '\0');
787 config_vf_floating_veb(struct rte_devargs *devargs,
788 uint16_t floating_veb,
789 bool *vf_floating_veb)
791 struct rte_kvargs *kvlist;
793 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
797 /* All the VFs attach to the floating VEB by default
798 * when the floating VEB is enabled.
800 for (i = 0; i < I40E_MAX_VF; i++)
801 vf_floating_veb[i] = true;
806 kvlist = rte_kvargs_parse(devargs->args, NULL);
810 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
811 rte_kvargs_free(kvlist);
814 /* When the floating_veb_list parameter exists, all the VFs
815 * will attach to the legacy VEB firstly, then configure VFs
816 * to the floating VEB according to the floating_veb_list.
818 if (rte_kvargs_process(kvlist, floating_veb_list,
819 floating_veb_list_handler,
820 vf_floating_veb) < 0) {
821 rte_kvargs_free(kvlist);
824 rte_kvargs_free(kvlist);
828 i40e_check_floating_handler(__rte_unused const char *key,
830 __rte_unused void *opaque)
832 if (strcmp(value, "1"))
839 is_floating_veb_supported(struct rte_devargs *devargs)
841 struct rte_kvargs *kvlist;
842 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
847 kvlist = rte_kvargs_parse(devargs->args, NULL);
851 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
852 rte_kvargs_free(kvlist);
855 /* Floating VEB is enabled when there's key-value:
856 * enable_floating_veb=1
858 if (rte_kvargs_process(kvlist, floating_veb_key,
859 i40e_check_floating_handler, NULL) < 0) {
860 rte_kvargs_free(kvlist);
863 rte_kvargs_free(kvlist);
869 config_floating_veb(struct rte_eth_dev *dev)
871 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
872 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
873 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
875 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
877 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
879 is_floating_veb_supported(pci_dev->device.devargs);
880 config_vf_floating_veb(pci_dev->device.devargs,
882 pf->floating_veb_list);
884 pf->floating_veb = false;
888 #define I40E_L2_TAGS_S_TAG_SHIFT 1
889 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
892 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
894 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
895 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
896 char ethertype_hash_name[RTE_HASH_NAMESIZE];
899 struct rte_hash_parameters ethertype_hash_params = {
900 .name = ethertype_hash_name,
901 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
902 .key_len = sizeof(struct i40e_ethertype_filter_input),
903 .hash_func = rte_hash_crc,
904 .hash_func_init_val = 0,
905 .socket_id = rte_socket_id(),
908 /* Initialize ethertype filter rule list and hash */
909 TAILQ_INIT(ðertype_rule->ethertype_list);
910 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
911 "ethertype_%s", dev->data->name);
912 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
913 if (!ethertype_rule->hash_table) {
914 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
917 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
918 sizeof(struct i40e_ethertype_filter *) *
919 I40E_MAX_ETHERTYPE_FILTER_NUM,
921 if (!ethertype_rule->hash_map) {
923 "Failed to allocate memory for ethertype hash map!");
925 goto err_ethertype_hash_map_alloc;
930 err_ethertype_hash_map_alloc:
931 rte_hash_free(ethertype_rule->hash_table);
937 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
940 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
941 char tunnel_hash_name[RTE_HASH_NAMESIZE];
944 struct rte_hash_parameters tunnel_hash_params = {
945 .name = tunnel_hash_name,
946 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
947 .key_len = sizeof(struct i40e_tunnel_filter_input),
948 .hash_func = rte_hash_crc,
949 .hash_func_init_val = 0,
950 .socket_id = rte_socket_id(),
953 /* Initialize tunnel filter rule list and hash */
954 TAILQ_INIT(&tunnel_rule->tunnel_list);
955 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
956 "tunnel_%s", dev->data->name);
957 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
958 if (!tunnel_rule->hash_table) {
959 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
962 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
963 sizeof(struct i40e_tunnel_filter *) *
964 I40E_MAX_TUNNEL_FILTER_NUM,
966 if (!tunnel_rule->hash_map) {
968 "Failed to allocate memory for tunnel hash map!");
970 goto err_tunnel_hash_map_alloc;
975 err_tunnel_hash_map_alloc:
976 rte_hash_free(tunnel_rule->hash_table);
982 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
984 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
985 struct i40e_fdir_info *fdir_info = &pf->fdir;
986 char fdir_hash_name[RTE_HASH_NAMESIZE];
989 struct rte_hash_parameters fdir_hash_params = {
990 .name = fdir_hash_name,
991 .entries = I40E_MAX_FDIR_FILTER_NUM,
992 .key_len = sizeof(struct rte_eth_fdir_input),
993 .hash_func = rte_hash_crc,
994 .hash_func_init_val = 0,
995 .socket_id = rte_socket_id(),
998 /* Initialize flow director filter rule list and hash */
999 TAILQ_INIT(&fdir_info->fdir_list);
1000 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1001 "fdir_%s", dev->data->name);
1002 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1003 if (!fdir_info->hash_table) {
1004 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1007 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1008 sizeof(struct i40e_fdir_filter *) *
1009 I40E_MAX_FDIR_FILTER_NUM,
1011 if (!fdir_info->hash_map) {
1013 "Failed to allocate memory for fdir hash map!");
1015 goto err_fdir_hash_map_alloc;
1019 err_fdir_hash_map_alloc:
1020 rte_hash_free(fdir_info->hash_table);
1026 eth_i40e_dev_init(struct rte_eth_dev *dev)
1028 struct rte_pci_device *pci_dev;
1029 struct rte_intr_handle *intr_handle;
1030 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032 struct i40e_vsi *vsi;
1035 uint8_t aq_fail = 0;
1037 PMD_INIT_FUNC_TRACE();
1039 dev->dev_ops = &i40e_eth_dev_ops;
1040 dev->rx_pkt_burst = i40e_recv_pkts;
1041 dev->tx_pkt_burst = i40e_xmit_pkts;
1042 dev->tx_pkt_prepare = i40e_prep_pkts;
1044 /* for secondary processes, we don't initialise any further as primary
1045 * has already done this work. Only check we don't need a different
1047 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1048 i40e_set_rx_function(dev);
1049 i40e_set_tx_function(dev);
1052 pci_dev = I40E_DEV_TO_PCI(dev);
1053 intr_handle = &pci_dev->intr_handle;
1055 rte_eth_copy_pci_info(dev, pci_dev);
1056 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1058 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1059 pf->adapter->eth_dev = dev;
1060 pf->dev_data = dev->data;
1062 hw->back = I40E_PF_TO_ADAPTER(pf);
1063 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1066 "Hardware is not available, as address is NULL");
1070 hw->vendor_id = pci_dev->id.vendor_id;
1071 hw->device_id = pci_dev->id.device_id;
1072 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1073 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1074 hw->bus.device = pci_dev->addr.devid;
1075 hw->bus.func = pci_dev->addr.function;
1076 hw->adapter_stopped = 0;
1078 /* Make sure all is clean before doing PF reset */
1081 /* Initialize the hardware */
1084 /* Reset here to make sure all is clean for each PF */
1085 ret = i40e_pf_reset(hw);
1087 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1091 /* Initialize the shared code (base driver) */
1092 ret = i40e_init_shared_code(hw);
1094 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1099 * To work around the NVM issue, initialize registers
1100 * for flexible payload and packet type of QinQ by
1101 * software. It should be removed once issues are fixed
1104 i40e_GLQF_reg_init(hw);
1106 /* Initialize the input set for filters (hash and fd) to default value */
1107 i40e_filter_input_set_init(pf);
1109 /* Initialize the parameters for adminq */
1110 i40e_init_adminq_parameter(hw);
1111 ret = i40e_init_adminq(hw);
1112 if (ret != I40E_SUCCESS) {
1113 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1116 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1117 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1118 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1119 ((hw->nvm.version >> 12) & 0xf),
1120 ((hw->nvm.version >> 4) & 0xff),
1121 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1123 /* Need the special FW version to support floating VEB */
1124 config_floating_veb(dev);
1125 /* Clear PXE mode */
1126 i40e_clear_pxe_mode(hw);
1127 ret = i40e_dev_sync_phy_type(hw);
1129 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1130 goto err_sync_phy_type;
1133 * On X710, performance number is far from the expectation on recent
1134 * firmware versions. The fix for this issue may not be integrated in
1135 * the following firmware version. So the workaround in software driver
1136 * is needed. It needs to modify the initial values of 3 internal only
1137 * registers. Note that the workaround can be removed when it is fixed
1138 * in firmware in the future.
1140 i40e_configure_registers(hw);
1142 /* Get hw capabilities */
1143 ret = i40e_get_cap(hw);
1144 if (ret != I40E_SUCCESS) {
1145 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1146 goto err_get_capabilities;
1149 /* Initialize parameters for PF */
1150 ret = i40e_pf_parameter_init(dev);
1152 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1153 goto err_parameter_init;
1156 /* Initialize the queue management */
1157 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1159 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1160 goto err_qp_pool_init;
1162 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1163 hw->func_caps.num_msix_vectors - 1);
1165 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1166 goto err_msix_pool_init;
1169 /* Initialize lan hmc */
1170 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1171 hw->func_caps.num_rx_qp, 0, 0);
1172 if (ret != I40E_SUCCESS) {
1173 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1174 goto err_init_lan_hmc;
1177 /* Configure lan hmc */
1178 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1179 if (ret != I40E_SUCCESS) {
1180 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1181 goto err_configure_lan_hmc;
1184 /* Get and check the mac address */
1185 i40e_get_mac_addr(hw, hw->mac.addr);
1186 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1187 PMD_INIT_LOG(ERR, "mac address is not valid");
1189 goto err_get_mac_addr;
1191 /* Copy the permanent MAC address */
1192 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1193 (struct ether_addr *) hw->mac.perm_addr);
1195 /* Disable flow control */
1196 hw->fc.requested_mode = I40E_FC_NONE;
1197 i40e_set_fc(hw, &aq_fail, TRUE);
1199 /* Set the global registers with default ether type value */
1200 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1201 if (ret != I40E_SUCCESS) {
1203 "Failed to set the default outer VLAN ether type");
1204 goto err_setup_pf_switch;
1207 /* PF setup, which includes VSI setup */
1208 ret = i40e_pf_setup(pf);
1210 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1211 goto err_setup_pf_switch;
1214 /* reset all stats of the device, including pf and main vsi */
1215 i40e_dev_stats_reset(dev);
1219 /* Disable double vlan by default */
1220 i40e_vsi_config_double_vlan(vsi, FALSE);
1222 /* Disable S-TAG identification when floating_veb is disabled */
1223 if (!pf->floating_veb) {
1224 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1225 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1226 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1227 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1231 if (!vsi->max_macaddrs)
1232 len = ETHER_ADDR_LEN;
1234 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1236 /* Should be after VSI initialized */
1237 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1238 if (!dev->data->mac_addrs) {
1240 "Failed to allocated memory for storing mac address");
1243 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1244 &dev->data->mac_addrs[0]);
1246 /* Init dcb to sw mode by default */
1247 ret = i40e_dcb_init_configure(dev, TRUE);
1248 if (ret != I40E_SUCCESS) {
1249 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1250 pf->flags &= ~I40E_FLAG_DCB;
1252 /* Update HW struct after DCB configuration */
1255 /* initialize pf host driver to setup SRIOV resource if applicable */
1256 i40e_pf_host_init(dev);
1258 /* register callback func to eal lib */
1259 rte_intr_callback_register(intr_handle,
1260 i40e_dev_interrupt_handler, dev);
1262 /* configure and enable device interrupt */
1263 i40e_pf_config_irq0(hw, TRUE);
1264 i40e_pf_enable_irq0(hw);
1266 /* enable uio intr after callback register */
1267 rte_intr_enable(intr_handle);
1269 * Add an ethertype filter to drop all flow control frames transmitted
1270 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1273 i40e_add_tx_flow_control_drop_filter(pf);
1275 /* Set the max frame size to 0x2600 by default,
1276 * in case other drivers changed the default value.
1278 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1280 /* initialize mirror rule list */
1281 TAILQ_INIT(&pf->mirror_list);
1283 ret = i40e_init_ethtype_filter_list(dev);
1285 goto err_init_ethtype_filter_list;
1286 ret = i40e_init_tunnel_filter_list(dev);
1288 goto err_init_tunnel_filter_list;
1289 ret = i40e_init_fdir_filter_list(dev);
1291 goto err_init_fdir_filter_list;
1295 err_init_fdir_filter_list:
1296 rte_free(pf->tunnel.hash_table);
1297 rte_free(pf->tunnel.hash_map);
1298 err_init_tunnel_filter_list:
1299 rte_free(pf->ethertype.hash_table);
1300 rte_free(pf->ethertype.hash_map);
1301 err_init_ethtype_filter_list:
1302 rte_free(dev->data->mac_addrs);
1304 i40e_vsi_release(pf->main_vsi);
1305 err_setup_pf_switch:
1307 err_configure_lan_hmc:
1308 (void)i40e_shutdown_lan_hmc(hw);
1310 i40e_res_pool_destroy(&pf->msix_pool);
1312 i40e_res_pool_destroy(&pf->qp_pool);
1315 err_get_capabilities:
1317 (void)i40e_shutdown_adminq(hw);
1323 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1325 struct i40e_ethertype_filter *p_ethertype;
1326 struct i40e_ethertype_rule *ethertype_rule;
1328 ethertype_rule = &pf->ethertype;
1329 /* Remove all ethertype filter rules and hash */
1330 if (ethertype_rule->hash_map)
1331 rte_free(ethertype_rule->hash_map);
1332 if (ethertype_rule->hash_table)
1333 rte_hash_free(ethertype_rule->hash_table);
1335 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1336 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1337 p_ethertype, rules);
1338 rte_free(p_ethertype);
1343 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1345 struct i40e_tunnel_filter *p_tunnel;
1346 struct i40e_tunnel_rule *tunnel_rule;
1348 tunnel_rule = &pf->tunnel;
1349 /* Remove all tunnel director rules and hash */
1350 if (tunnel_rule->hash_map)
1351 rte_free(tunnel_rule->hash_map);
1352 if (tunnel_rule->hash_table)
1353 rte_hash_free(tunnel_rule->hash_table);
1355 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1356 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1362 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1364 struct i40e_fdir_filter *p_fdir;
1365 struct i40e_fdir_info *fdir_info;
1367 fdir_info = &pf->fdir;
1368 /* Remove all flow director rules and hash */
1369 if (fdir_info->hash_map)
1370 rte_free(fdir_info->hash_map);
1371 if (fdir_info->hash_table)
1372 rte_hash_free(fdir_info->hash_table);
1374 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1375 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1381 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1384 struct rte_pci_device *pci_dev;
1385 struct rte_intr_handle *intr_handle;
1387 struct i40e_filter_control_settings settings;
1388 struct rte_flow *p_flow;
1390 uint8_t aq_fail = 0;
1392 PMD_INIT_FUNC_TRACE();
1394 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1397 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1398 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1399 pci_dev = I40E_DEV_TO_PCI(dev);
1400 intr_handle = &pci_dev->intr_handle;
1402 if (hw->adapter_stopped == 0)
1403 i40e_dev_close(dev);
1405 dev->dev_ops = NULL;
1406 dev->rx_pkt_burst = NULL;
1407 dev->tx_pkt_burst = NULL;
1409 /* Clear PXE mode */
1410 i40e_clear_pxe_mode(hw);
1412 /* Unconfigure filter control */
1413 memset(&settings, 0, sizeof(settings));
1414 ret = i40e_set_filter_control(hw, &settings);
1416 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1419 /* Disable flow control */
1420 hw->fc.requested_mode = I40E_FC_NONE;
1421 i40e_set_fc(hw, &aq_fail, TRUE);
1423 /* uninitialize pf host driver */
1424 i40e_pf_host_uninit(dev);
1426 rte_free(dev->data->mac_addrs);
1427 dev->data->mac_addrs = NULL;
1429 /* disable uio intr before callback unregister */
1430 rte_intr_disable(intr_handle);
1432 /* register callback func to eal lib */
1433 rte_intr_callback_unregister(intr_handle,
1434 i40e_dev_interrupt_handler, dev);
1436 i40e_rm_ethtype_filter_list(pf);
1437 i40e_rm_tunnel_filter_list(pf);
1438 i40e_rm_fdir_filter_list(pf);
1440 /* Remove all flows */
1441 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1442 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1450 i40e_dev_configure(struct rte_eth_dev *dev)
1452 struct i40e_adapter *ad =
1453 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1454 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1455 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1458 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1459 * bulk allocation or vector Rx preconditions we will reset it.
1461 ad->rx_bulk_alloc_allowed = true;
1462 ad->rx_vec_allowed = true;
1463 ad->tx_simple_allowed = true;
1464 ad->tx_vec_allowed = true;
1466 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1467 ret = i40e_fdir_setup(pf);
1468 if (ret != I40E_SUCCESS) {
1469 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1472 ret = i40e_fdir_configure(dev);
1474 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1478 i40e_fdir_teardown(pf);
1480 ret = i40e_dev_init_vlan(dev);
1485 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1486 * RSS setting have different requirements.
1487 * General PMD driver call sequence are NIC init, configure,
1488 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1489 * will try to lookup the VSI that specific queue belongs to if VMDQ
1490 * applicable. So, VMDQ setting has to be done before
1491 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1492 * For RSS setting, it will try to calculate actual configured RX queue
1493 * number, which will be available after rx_queue_setup(). dev_start()
1494 * function is good to place RSS setup.
1496 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1497 ret = i40e_vmdq_setup(dev);
1502 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1503 ret = i40e_dcb_setup(dev);
1505 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1510 TAILQ_INIT(&pf->flow_list);
1515 /* need to release vmdq resource if exists */
1516 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1517 i40e_vsi_release(pf->vmdq[i].vsi);
1518 pf->vmdq[i].vsi = NULL;
1523 /* need to release fdir resource if exists */
1524 i40e_fdir_teardown(pf);
1529 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1531 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1532 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1533 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1534 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1535 uint16_t msix_vect = vsi->msix_intr;
1538 for (i = 0; i < vsi->nb_qps; i++) {
1539 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1540 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1544 if (vsi->type != I40E_VSI_SRIOV) {
1545 if (!rte_intr_allow_others(intr_handle)) {
1546 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1547 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1549 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1552 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1553 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1555 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1560 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1561 vsi->user_param + (msix_vect - 1);
1563 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1564 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1566 I40E_WRITE_FLUSH(hw);
1570 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1571 int base_queue, int nb_queue)
1575 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1577 /* Bind all RX queues to allocated MSIX interrupt */
1578 for (i = 0; i < nb_queue; i++) {
1579 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1580 I40E_QINT_RQCTL_ITR_INDX_MASK |
1581 ((base_queue + i + 1) <<
1582 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1583 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1584 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1586 if (i == nb_queue - 1)
1587 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1588 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1591 /* Write first RX queue to Link list register as the head element */
1592 if (vsi->type != I40E_VSI_SRIOV) {
1594 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1596 if (msix_vect == I40E_MISC_VEC_ID) {
1597 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1599 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1601 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1603 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1606 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1608 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1610 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1612 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1619 if (msix_vect == I40E_MISC_VEC_ID) {
1621 I40E_VPINT_LNKLST0(vsi->user_param),
1623 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1625 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1627 /* num_msix_vectors_vf needs to minus irq0 */
1628 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1629 vsi->user_param + (msix_vect - 1);
1631 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1633 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1635 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1639 I40E_WRITE_FLUSH(hw);
1643 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1645 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1646 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1647 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1648 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1649 uint16_t msix_vect = vsi->msix_intr;
1650 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1651 uint16_t queue_idx = 0;
1656 for (i = 0; i < vsi->nb_qps; i++) {
1657 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1658 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1661 /* INTENA flag is not auto-cleared for interrupt */
1662 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1663 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1664 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1665 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1666 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1668 /* VF bind interrupt */
1669 if (vsi->type == I40E_VSI_SRIOV) {
1670 __vsi_queues_bind_intr(vsi, msix_vect,
1671 vsi->base_queue, vsi->nb_qps);
1675 /* PF & VMDq bind interrupt */
1676 if (rte_intr_dp_is_en(intr_handle)) {
1677 if (vsi->type == I40E_VSI_MAIN) {
1680 } else if (vsi->type == I40E_VSI_VMDQ2) {
1681 struct i40e_vsi *main_vsi =
1682 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1683 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1688 for (i = 0; i < vsi->nb_used_qps; i++) {
1690 if (!rte_intr_allow_others(intr_handle))
1691 /* allow to share MISC_VEC_ID */
1692 msix_vect = I40E_MISC_VEC_ID;
1694 /* no enough msix_vect, map all to one */
1695 __vsi_queues_bind_intr(vsi, msix_vect,
1696 vsi->base_queue + i,
1697 vsi->nb_used_qps - i);
1698 for (; !!record && i < vsi->nb_used_qps; i++)
1699 intr_handle->intr_vec[queue_idx + i] =
1703 /* 1:1 queue/msix_vect mapping */
1704 __vsi_queues_bind_intr(vsi, msix_vect,
1705 vsi->base_queue + i, 1);
1707 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1715 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1717 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1718 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1719 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1720 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1721 uint16_t interval = i40e_calc_itr_interval(\
1722 RTE_LIBRTE_I40E_ITR_INTERVAL);
1723 uint16_t msix_intr, i;
1725 if (rte_intr_allow_others(intr_handle))
1726 for (i = 0; i < vsi->nb_msix; i++) {
1727 msix_intr = vsi->msix_intr + i;
1728 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1729 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1730 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1731 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1733 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1736 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1737 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1738 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1739 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1741 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1743 I40E_WRITE_FLUSH(hw);
1747 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1749 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1750 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1751 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1752 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1753 uint16_t msix_intr, i;
1755 if (rte_intr_allow_others(intr_handle))
1756 for (i = 0; i < vsi->nb_msix; i++) {
1757 msix_intr = vsi->msix_intr + i;
1758 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1762 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1764 I40E_WRITE_FLUSH(hw);
1767 static inline uint8_t
1768 i40e_parse_link_speeds(uint16_t link_speeds)
1770 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1772 if (link_speeds & ETH_LINK_SPEED_40G)
1773 link_speed |= I40E_LINK_SPEED_40GB;
1774 if (link_speeds & ETH_LINK_SPEED_25G)
1775 link_speed |= I40E_LINK_SPEED_25GB;
1776 if (link_speeds & ETH_LINK_SPEED_20G)
1777 link_speed |= I40E_LINK_SPEED_20GB;
1778 if (link_speeds & ETH_LINK_SPEED_10G)
1779 link_speed |= I40E_LINK_SPEED_10GB;
1780 if (link_speeds & ETH_LINK_SPEED_1G)
1781 link_speed |= I40E_LINK_SPEED_1GB;
1782 if (link_speeds & ETH_LINK_SPEED_100M)
1783 link_speed |= I40E_LINK_SPEED_100MB;
1789 i40e_phy_conf_link(struct i40e_hw *hw,
1791 uint8_t force_speed)
1793 enum i40e_status_code status;
1794 struct i40e_aq_get_phy_abilities_resp phy_ab;
1795 struct i40e_aq_set_phy_config phy_conf;
1796 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1797 I40E_AQ_PHY_FLAG_PAUSE_RX |
1798 I40E_AQ_PHY_FLAG_PAUSE_RX |
1799 I40E_AQ_PHY_FLAG_LOW_POWER;
1800 const uint8_t advt = I40E_LINK_SPEED_40GB |
1801 I40E_LINK_SPEED_25GB |
1802 I40E_LINK_SPEED_10GB |
1803 I40E_LINK_SPEED_1GB |
1804 I40E_LINK_SPEED_100MB;
1808 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1813 memset(&phy_conf, 0, sizeof(phy_conf));
1815 /* bits 0-2 use the values from get_phy_abilities_resp */
1817 abilities |= phy_ab.abilities & mask;
1819 /* update ablities and speed */
1820 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1821 phy_conf.link_speed = advt;
1823 phy_conf.link_speed = force_speed;
1825 phy_conf.abilities = abilities;
1827 /* use get_phy_abilities_resp value for the rest */
1828 phy_conf.phy_type = phy_ab.phy_type;
1829 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1830 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1831 phy_conf.eee_capability = phy_ab.eee_capability;
1832 phy_conf.eeer = phy_ab.eeer_val;
1833 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1835 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1836 phy_ab.abilities, phy_ab.link_speed);
1837 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1838 phy_conf.abilities, phy_conf.link_speed);
1840 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1844 return I40E_SUCCESS;
1848 i40e_apply_link_speed(struct rte_eth_dev *dev)
1851 uint8_t abilities = 0;
1852 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853 struct rte_eth_conf *conf = &dev->data->dev_conf;
1855 speed = i40e_parse_link_speeds(conf->link_speeds);
1856 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1857 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1858 abilities |= I40E_AQ_PHY_AN_ENABLED;
1859 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1861 /* Skip changing speed on 40G interfaces, FW does not support */
1862 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1863 speed = I40E_LINK_SPEED_UNKNOWN;
1864 abilities |= I40E_AQ_PHY_AN_ENABLED;
1867 return i40e_phy_conf_link(hw, abilities, speed);
1871 i40e_dev_start(struct rte_eth_dev *dev)
1873 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1874 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1875 struct i40e_vsi *main_vsi = pf->main_vsi;
1877 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1878 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1879 uint32_t intr_vector = 0;
1881 hw->adapter_stopped = 0;
1883 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1884 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1885 dev->data->port_id);
1889 rte_intr_disable(intr_handle);
1891 if ((rte_intr_cap_multiple(intr_handle) ||
1892 !RTE_ETH_DEV_SRIOV(dev).active) &&
1893 dev->data->dev_conf.intr_conf.rxq != 0) {
1894 intr_vector = dev->data->nb_rx_queues;
1895 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1900 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1901 intr_handle->intr_vec =
1902 rte_zmalloc("intr_vec",
1903 dev->data->nb_rx_queues * sizeof(int),
1905 if (!intr_handle->intr_vec) {
1907 "Failed to allocate %d rx_queues intr_vec",
1908 dev->data->nb_rx_queues);
1913 /* Initialize VSI */
1914 ret = i40e_dev_rxtx_init(pf);
1915 if (ret != I40E_SUCCESS) {
1916 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1920 /* Map queues with MSIX interrupt */
1921 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1922 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1923 i40e_vsi_queues_bind_intr(main_vsi);
1924 i40e_vsi_enable_queues_intr(main_vsi);
1926 /* Map VMDQ VSI queues with MSIX interrupt */
1927 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1928 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1929 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1930 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1933 /* enable FDIR MSIX interrupt */
1934 if (pf->fdir.fdir_vsi) {
1935 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1936 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1939 /* Enable all queues which have been configured */
1940 ret = i40e_dev_switch_queues(pf, TRUE);
1941 if (ret != I40E_SUCCESS) {
1942 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1946 /* Enable receiving broadcast packets */
1947 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1948 if (ret != I40E_SUCCESS)
1949 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1951 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1952 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1954 if (ret != I40E_SUCCESS)
1955 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1958 /* Apply link configure */
1959 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1960 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1961 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1962 ETH_LINK_SPEED_40G)) {
1963 PMD_DRV_LOG(ERR, "Invalid link setting");
1966 ret = i40e_apply_link_speed(dev);
1967 if (I40E_SUCCESS != ret) {
1968 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1972 if (!rte_intr_allow_others(intr_handle)) {
1973 rte_intr_callback_unregister(intr_handle,
1974 i40e_dev_interrupt_handler,
1976 /* configure and enable device interrupt */
1977 i40e_pf_config_irq0(hw, FALSE);
1978 i40e_pf_enable_irq0(hw);
1980 if (dev->data->dev_conf.intr_conf.lsc != 0)
1982 "lsc won't enable because of no intr multiplex");
1983 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1984 ret = i40e_aq_set_phy_int_mask(hw,
1985 ~(I40E_AQ_EVENT_LINK_UPDOWN |
1986 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1987 I40E_AQ_EVENT_MEDIA_NA), NULL);
1988 if (ret != I40E_SUCCESS)
1989 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1991 /* Call get_link_info aq commond to enable LSE */
1992 i40e_dev_link_update(dev, 0);
1995 /* enable uio intr after callback register */
1996 rte_intr_enable(intr_handle);
1998 i40e_filter_restore(pf);
2000 return I40E_SUCCESS;
2003 i40e_dev_switch_queues(pf, FALSE);
2004 i40e_dev_clear_queues(dev);
2010 i40e_dev_stop(struct rte_eth_dev *dev)
2012 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2013 struct i40e_vsi *main_vsi = pf->main_vsi;
2014 struct i40e_mirror_rule *p_mirror;
2015 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2016 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2019 /* Disable all queues */
2020 i40e_dev_switch_queues(pf, FALSE);
2022 /* un-map queues with interrupt registers */
2023 i40e_vsi_disable_queues_intr(main_vsi);
2024 i40e_vsi_queues_unbind_intr(main_vsi);
2026 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2027 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2028 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2031 if (pf->fdir.fdir_vsi) {
2032 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2033 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2035 /* Clear all queues and release memory */
2036 i40e_dev_clear_queues(dev);
2039 i40e_dev_set_link_down(dev);
2041 /* Remove all mirror rules */
2042 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2043 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2046 pf->nb_mirror_rule = 0;
2048 if (!rte_intr_allow_others(intr_handle))
2049 /* resume to the default handler */
2050 rte_intr_callback_register(intr_handle,
2051 i40e_dev_interrupt_handler,
2054 /* Clean datapath event and queue/vec mapping */
2055 rte_intr_efd_disable(intr_handle);
2056 if (intr_handle->intr_vec) {
2057 rte_free(intr_handle->intr_vec);
2058 intr_handle->intr_vec = NULL;
2063 i40e_dev_close(struct rte_eth_dev *dev)
2065 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2068 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2072 PMD_INIT_FUNC_TRACE();
2075 hw->adapter_stopped = 1;
2076 i40e_dev_free_queues(dev);
2078 /* Disable interrupt */
2079 i40e_pf_disable_irq0(hw);
2080 rte_intr_disable(intr_handle);
2082 /* shutdown and destroy the HMC */
2083 i40e_shutdown_lan_hmc(hw);
2085 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2086 i40e_vsi_release(pf->vmdq[i].vsi);
2087 pf->vmdq[i].vsi = NULL;
2092 /* release all the existing VSIs and VEBs */
2093 i40e_fdir_teardown(pf);
2094 i40e_vsi_release(pf->main_vsi);
2096 /* shutdown the adminq */
2097 i40e_aq_queue_shutdown(hw, true);
2098 i40e_shutdown_adminq(hw);
2100 i40e_res_pool_destroy(&pf->qp_pool);
2101 i40e_res_pool_destroy(&pf->msix_pool);
2103 /* force a PF reset to clean anything leftover */
2104 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2105 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2106 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2107 I40E_WRITE_FLUSH(hw);
2111 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2113 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2114 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115 struct i40e_vsi *vsi = pf->main_vsi;
2118 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2120 if (status != I40E_SUCCESS)
2121 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2123 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2125 if (status != I40E_SUCCESS)
2126 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2131 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2133 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2134 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135 struct i40e_vsi *vsi = pf->main_vsi;
2138 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2140 if (status != I40E_SUCCESS)
2141 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2143 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2145 if (status != I40E_SUCCESS)
2146 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2150 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2152 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2153 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154 struct i40e_vsi *vsi = pf->main_vsi;
2157 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2158 if (ret != I40E_SUCCESS)
2159 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2163 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2165 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2166 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2167 struct i40e_vsi *vsi = pf->main_vsi;
2170 if (dev->data->promiscuous == 1)
2171 return; /* must remain in all_multicast mode */
2173 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2174 vsi->seid, FALSE, NULL);
2175 if (ret != I40E_SUCCESS)
2176 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2180 * Set device link up.
2183 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2185 /* re-apply link speed setting */
2186 return i40e_apply_link_speed(dev);
2190 * Set device link down.
2193 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2195 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2196 uint8_t abilities = 0;
2197 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2199 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2200 return i40e_phy_conf_link(hw, abilities, speed);
2204 i40e_dev_link_update(struct rte_eth_dev *dev,
2205 int wait_to_complete)
2207 #define CHECK_INTERVAL 100 /* 100ms */
2208 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2209 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2210 struct i40e_link_status link_status;
2211 struct rte_eth_link link, old;
2213 unsigned rep_cnt = MAX_REPEAT_TIME;
2214 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2216 memset(&link, 0, sizeof(link));
2217 memset(&old, 0, sizeof(old));
2218 memset(&link_status, 0, sizeof(link_status));
2219 rte_i40e_dev_atomic_read_link_status(dev, &old);
2222 /* Get link status information from hardware */
2223 status = i40e_aq_get_link_info(hw, enable_lse,
2224 &link_status, NULL);
2225 if (status != I40E_SUCCESS) {
2226 link.link_speed = ETH_SPEED_NUM_100M;
2227 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2228 PMD_DRV_LOG(ERR, "Failed to get link info");
2232 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2233 if (!wait_to_complete || link.link_status)
2236 rte_delay_ms(CHECK_INTERVAL);
2237 } while (--rep_cnt);
2239 if (!link.link_status)
2242 /* i40e uses full duplex only */
2243 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2245 /* Parse the link status */
2246 switch (link_status.link_speed) {
2247 case I40E_LINK_SPEED_100MB:
2248 link.link_speed = ETH_SPEED_NUM_100M;
2250 case I40E_LINK_SPEED_1GB:
2251 link.link_speed = ETH_SPEED_NUM_1G;
2253 case I40E_LINK_SPEED_10GB:
2254 link.link_speed = ETH_SPEED_NUM_10G;
2256 case I40E_LINK_SPEED_20GB:
2257 link.link_speed = ETH_SPEED_NUM_20G;
2259 case I40E_LINK_SPEED_25GB:
2260 link.link_speed = ETH_SPEED_NUM_25G;
2262 case I40E_LINK_SPEED_40GB:
2263 link.link_speed = ETH_SPEED_NUM_40G;
2266 link.link_speed = ETH_SPEED_NUM_100M;
2270 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2271 ETH_LINK_SPEED_FIXED);
2274 rte_i40e_dev_atomic_write_link_status(dev, &link);
2275 if (link.link_status == old.link_status)
2281 /* Get all the statistics of a VSI */
2283 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2285 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2286 struct i40e_eth_stats *nes = &vsi->eth_stats;
2287 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2288 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2290 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2291 vsi->offset_loaded, &oes->rx_bytes,
2293 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2294 vsi->offset_loaded, &oes->rx_unicast,
2296 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2297 vsi->offset_loaded, &oes->rx_multicast,
2298 &nes->rx_multicast);
2299 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2300 vsi->offset_loaded, &oes->rx_broadcast,
2301 &nes->rx_broadcast);
2302 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2303 &oes->rx_discards, &nes->rx_discards);
2304 /* GLV_REPC not supported */
2305 /* GLV_RMPC not supported */
2306 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2307 &oes->rx_unknown_protocol,
2308 &nes->rx_unknown_protocol);
2309 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2310 vsi->offset_loaded, &oes->tx_bytes,
2312 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2313 vsi->offset_loaded, &oes->tx_unicast,
2315 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2316 vsi->offset_loaded, &oes->tx_multicast,
2317 &nes->tx_multicast);
2318 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2319 vsi->offset_loaded, &oes->tx_broadcast,
2320 &nes->tx_broadcast);
2321 /* GLV_TDPC not supported */
2322 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2323 &oes->tx_errors, &nes->tx_errors);
2324 vsi->offset_loaded = true;
2326 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2328 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2329 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2330 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2331 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2332 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2333 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2334 nes->rx_unknown_protocol);
2335 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2336 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2337 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2338 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2339 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2340 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2341 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2346 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2349 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2350 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2352 /* Get statistics of struct i40e_eth_stats */
2353 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2354 I40E_GLPRT_GORCL(hw->port),
2355 pf->offset_loaded, &os->eth.rx_bytes,
2357 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2358 I40E_GLPRT_UPRCL(hw->port),
2359 pf->offset_loaded, &os->eth.rx_unicast,
2360 &ns->eth.rx_unicast);
2361 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2362 I40E_GLPRT_MPRCL(hw->port),
2363 pf->offset_loaded, &os->eth.rx_multicast,
2364 &ns->eth.rx_multicast);
2365 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2366 I40E_GLPRT_BPRCL(hw->port),
2367 pf->offset_loaded, &os->eth.rx_broadcast,
2368 &ns->eth.rx_broadcast);
2369 /* Workaround: CRC size should not be included in byte statistics,
2370 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2372 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2373 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2375 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2376 pf->offset_loaded, &os->eth.rx_discards,
2377 &ns->eth.rx_discards);
2378 /* GLPRT_REPC not supported */
2379 /* GLPRT_RMPC not supported */
2380 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2382 &os->eth.rx_unknown_protocol,
2383 &ns->eth.rx_unknown_protocol);
2384 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2385 I40E_GLPRT_GOTCL(hw->port),
2386 pf->offset_loaded, &os->eth.tx_bytes,
2388 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2389 I40E_GLPRT_UPTCL(hw->port),
2390 pf->offset_loaded, &os->eth.tx_unicast,
2391 &ns->eth.tx_unicast);
2392 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2393 I40E_GLPRT_MPTCL(hw->port),
2394 pf->offset_loaded, &os->eth.tx_multicast,
2395 &ns->eth.tx_multicast);
2396 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2397 I40E_GLPRT_BPTCL(hw->port),
2398 pf->offset_loaded, &os->eth.tx_broadcast,
2399 &ns->eth.tx_broadcast);
2400 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2401 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2402 /* GLPRT_TEPC not supported */
2404 /* additional port specific stats */
2405 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2406 pf->offset_loaded, &os->tx_dropped_link_down,
2407 &ns->tx_dropped_link_down);
2408 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2409 pf->offset_loaded, &os->crc_errors,
2411 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2412 pf->offset_loaded, &os->illegal_bytes,
2413 &ns->illegal_bytes);
2414 /* GLPRT_ERRBC not supported */
2415 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2416 pf->offset_loaded, &os->mac_local_faults,
2417 &ns->mac_local_faults);
2418 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2419 pf->offset_loaded, &os->mac_remote_faults,
2420 &ns->mac_remote_faults);
2421 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2422 pf->offset_loaded, &os->rx_length_errors,
2423 &ns->rx_length_errors);
2424 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2425 pf->offset_loaded, &os->link_xon_rx,
2427 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2428 pf->offset_loaded, &os->link_xoff_rx,
2430 for (i = 0; i < 8; i++) {
2431 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2433 &os->priority_xon_rx[i],
2434 &ns->priority_xon_rx[i]);
2435 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2437 &os->priority_xoff_rx[i],
2438 &ns->priority_xoff_rx[i]);
2440 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2441 pf->offset_loaded, &os->link_xon_tx,
2443 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2444 pf->offset_loaded, &os->link_xoff_tx,
2446 for (i = 0; i < 8; i++) {
2447 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2449 &os->priority_xon_tx[i],
2450 &ns->priority_xon_tx[i]);
2451 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2453 &os->priority_xoff_tx[i],
2454 &ns->priority_xoff_tx[i]);
2455 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2457 &os->priority_xon_2_xoff[i],
2458 &ns->priority_xon_2_xoff[i]);
2460 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2461 I40E_GLPRT_PRC64L(hw->port),
2462 pf->offset_loaded, &os->rx_size_64,
2464 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2465 I40E_GLPRT_PRC127L(hw->port),
2466 pf->offset_loaded, &os->rx_size_127,
2468 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2469 I40E_GLPRT_PRC255L(hw->port),
2470 pf->offset_loaded, &os->rx_size_255,
2472 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2473 I40E_GLPRT_PRC511L(hw->port),
2474 pf->offset_loaded, &os->rx_size_511,
2476 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2477 I40E_GLPRT_PRC1023L(hw->port),
2478 pf->offset_loaded, &os->rx_size_1023,
2480 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2481 I40E_GLPRT_PRC1522L(hw->port),
2482 pf->offset_loaded, &os->rx_size_1522,
2484 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2485 I40E_GLPRT_PRC9522L(hw->port),
2486 pf->offset_loaded, &os->rx_size_big,
2488 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2489 pf->offset_loaded, &os->rx_undersize,
2491 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2492 pf->offset_loaded, &os->rx_fragments,
2494 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2495 pf->offset_loaded, &os->rx_oversize,
2497 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2498 pf->offset_loaded, &os->rx_jabber,
2500 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2501 I40E_GLPRT_PTC64L(hw->port),
2502 pf->offset_loaded, &os->tx_size_64,
2504 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2505 I40E_GLPRT_PTC127L(hw->port),
2506 pf->offset_loaded, &os->tx_size_127,
2508 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2509 I40E_GLPRT_PTC255L(hw->port),
2510 pf->offset_loaded, &os->tx_size_255,
2512 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2513 I40E_GLPRT_PTC511L(hw->port),
2514 pf->offset_loaded, &os->tx_size_511,
2516 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2517 I40E_GLPRT_PTC1023L(hw->port),
2518 pf->offset_loaded, &os->tx_size_1023,
2520 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2521 I40E_GLPRT_PTC1522L(hw->port),
2522 pf->offset_loaded, &os->tx_size_1522,
2524 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2525 I40E_GLPRT_PTC9522L(hw->port),
2526 pf->offset_loaded, &os->tx_size_big,
2528 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2530 &os->fd_sb_match, &ns->fd_sb_match);
2531 /* GLPRT_MSPDC not supported */
2532 /* GLPRT_XEC not supported */
2534 pf->offset_loaded = true;
2537 i40e_update_vsi_stats(pf->main_vsi);
2540 /* Get all statistics of a port */
2542 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2544 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2545 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2546 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2549 /* call read registers - updates values, now write them to struct */
2550 i40e_read_stats_registers(pf, hw);
2552 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2553 pf->main_vsi->eth_stats.rx_multicast +
2554 pf->main_vsi->eth_stats.rx_broadcast -
2555 pf->main_vsi->eth_stats.rx_discards;
2556 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2557 pf->main_vsi->eth_stats.tx_multicast +
2558 pf->main_vsi->eth_stats.tx_broadcast;
2559 stats->ibytes = ns->eth.rx_bytes;
2560 stats->obytes = ns->eth.tx_bytes;
2561 stats->oerrors = ns->eth.tx_errors +
2562 pf->main_vsi->eth_stats.tx_errors;
2565 stats->imissed = ns->eth.rx_discards +
2566 pf->main_vsi->eth_stats.rx_discards;
2567 stats->ierrors = ns->crc_errors +
2568 ns->rx_length_errors + ns->rx_undersize +
2569 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2571 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2572 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2573 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2574 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2575 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2576 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2577 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2578 ns->eth.rx_unknown_protocol);
2579 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2580 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2581 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2582 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2583 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2584 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2586 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2587 ns->tx_dropped_link_down);
2588 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2589 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2591 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2592 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2593 ns->mac_local_faults);
2594 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2595 ns->mac_remote_faults);
2596 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2597 ns->rx_length_errors);
2598 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2599 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2600 for (i = 0; i < 8; i++) {
2601 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2602 i, ns->priority_xon_rx[i]);
2603 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2604 i, ns->priority_xoff_rx[i]);
2606 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2607 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2608 for (i = 0; i < 8; i++) {
2609 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2610 i, ns->priority_xon_tx[i]);
2611 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2612 i, ns->priority_xoff_tx[i]);
2613 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2614 i, ns->priority_xon_2_xoff[i]);
2616 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2617 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2618 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2619 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2620 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2621 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2622 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2623 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2624 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2625 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2626 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2627 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2628 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2629 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2630 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2631 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2632 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2633 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2634 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2635 ns->mac_short_packet_dropped);
2636 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2637 ns->checksum_error);
2638 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2639 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2642 /* Reset the statistics */
2644 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2646 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2647 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2649 /* Mark PF and VSI stats to update the offset, aka "reset" */
2650 pf->offset_loaded = false;
2652 pf->main_vsi->offset_loaded = false;
2654 /* read the stats, reading current register values into offset */
2655 i40e_read_stats_registers(pf, hw);
2659 i40e_xstats_calc_num(void)
2661 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2662 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2663 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2666 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2667 struct rte_eth_xstat_name *xstats_names,
2668 __rte_unused unsigned limit)
2673 if (xstats_names == NULL)
2674 return i40e_xstats_calc_num();
2676 /* Note: limit checked in rte_eth_xstats_names() */
2678 /* Get stats from i40e_eth_stats struct */
2679 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2680 snprintf(xstats_names[count].name,
2681 sizeof(xstats_names[count].name),
2682 "%s", rte_i40e_stats_strings[i].name);
2686 /* Get individiual stats from i40e_hw_port struct */
2687 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2688 snprintf(xstats_names[count].name,
2689 sizeof(xstats_names[count].name),
2690 "%s", rte_i40e_hw_port_strings[i].name);
2694 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2695 for (prio = 0; prio < 8; prio++) {
2696 snprintf(xstats_names[count].name,
2697 sizeof(xstats_names[count].name),
2698 "rx_priority%u_%s", prio,
2699 rte_i40e_rxq_prio_strings[i].name);
2704 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2705 for (prio = 0; prio < 8; prio++) {
2706 snprintf(xstats_names[count].name,
2707 sizeof(xstats_names[count].name),
2708 "tx_priority%u_%s", prio,
2709 rte_i40e_txq_prio_strings[i].name);
2717 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2720 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2721 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2722 unsigned i, count, prio;
2723 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2725 count = i40e_xstats_calc_num();
2729 i40e_read_stats_registers(pf, hw);
2736 /* Get stats from i40e_eth_stats struct */
2737 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2738 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2739 rte_i40e_stats_strings[i].offset);
2740 xstats[count].id = count;
2744 /* Get individiual stats from i40e_hw_port struct */
2745 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2746 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2747 rte_i40e_hw_port_strings[i].offset);
2748 xstats[count].id = count;
2752 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2753 for (prio = 0; prio < 8; prio++) {
2754 xstats[count].value =
2755 *(uint64_t *)(((char *)hw_stats) +
2756 rte_i40e_rxq_prio_strings[i].offset +
2757 (sizeof(uint64_t) * prio));
2758 xstats[count].id = count;
2763 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2764 for (prio = 0; prio < 8; prio++) {
2765 xstats[count].value =
2766 *(uint64_t *)(((char *)hw_stats) +
2767 rte_i40e_txq_prio_strings[i].offset +
2768 (sizeof(uint64_t) * prio));
2769 xstats[count].id = count;
2778 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2779 __rte_unused uint16_t queue_id,
2780 __rte_unused uint8_t stat_idx,
2781 __rte_unused uint8_t is_rx)
2783 PMD_INIT_FUNC_TRACE();
2789 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2791 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2797 full_ver = hw->nvm.oem_ver;
2798 ver = (u8)(full_ver >> 24);
2799 build = (u16)((full_ver >> 8) & 0xffff);
2800 patch = (u8)(full_ver & 0xff);
2802 ret = snprintf(fw_version, fw_size,
2803 "%d.%d%d 0x%08x %d.%d.%d",
2804 ((hw->nvm.version >> 12) & 0xf),
2805 ((hw->nvm.version >> 4) & 0xff),
2806 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2809 ret += 1; /* add the size of '\0' */
2810 if (fw_size < (u32)ret)
2817 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2819 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2820 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2821 struct i40e_vsi *vsi = pf->main_vsi;
2822 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2824 dev_info->pci_dev = pci_dev;
2825 dev_info->max_rx_queues = vsi->nb_qps;
2826 dev_info->max_tx_queues = vsi->nb_qps;
2827 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2828 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2829 dev_info->max_mac_addrs = vsi->max_macaddrs;
2830 dev_info->max_vfs = pci_dev->max_vfs;
2831 dev_info->rx_offload_capa =
2832 DEV_RX_OFFLOAD_VLAN_STRIP |
2833 DEV_RX_OFFLOAD_QINQ_STRIP |
2834 DEV_RX_OFFLOAD_IPV4_CKSUM |
2835 DEV_RX_OFFLOAD_UDP_CKSUM |
2836 DEV_RX_OFFLOAD_TCP_CKSUM;
2837 dev_info->tx_offload_capa =
2838 DEV_TX_OFFLOAD_VLAN_INSERT |
2839 DEV_TX_OFFLOAD_QINQ_INSERT |
2840 DEV_TX_OFFLOAD_IPV4_CKSUM |
2841 DEV_TX_OFFLOAD_UDP_CKSUM |
2842 DEV_TX_OFFLOAD_TCP_CKSUM |
2843 DEV_TX_OFFLOAD_SCTP_CKSUM |
2844 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2845 DEV_TX_OFFLOAD_TCP_TSO |
2846 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2847 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2848 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2849 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2850 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2852 dev_info->reta_size = pf->hash_lut_size;
2853 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2855 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2857 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2858 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2859 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2861 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2865 dev_info->default_txconf = (struct rte_eth_txconf) {
2867 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2868 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2869 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2871 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2872 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2873 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2874 ETH_TXQ_FLAGS_NOOFFLOADS,
2877 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2878 .nb_max = I40E_MAX_RING_DESC,
2879 .nb_min = I40E_MIN_RING_DESC,
2880 .nb_align = I40E_ALIGN_RING_DESC,
2883 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2884 .nb_max = I40E_MAX_RING_DESC,
2885 .nb_min = I40E_MIN_RING_DESC,
2886 .nb_align = I40E_ALIGN_RING_DESC,
2887 .nb_seg_max = I40E_TX_MAX_SEG,
2888 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2891 if (pf->flags & I40E_FLAG_VMDQ) {
2892 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2893 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2894 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2895 pf->max_nb_vmdq_vsi;
2896 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2897 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2898 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2901 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2903 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2904 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2906 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2909 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2913 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2915 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2916 struct i40e_vsi *vsi = pf->main_vsi;
2917 PMD_INIT_FUNC_TRACE();
2920 return i40e_vsi_add_vlan(vsi, vlan_id);
2922 return i40e_vsi_delete_vlan(vsi, vlan_id);
2926 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2927 enum rte_vlan_type vlan_type,
2930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931 uint64_t reg_r = 0, reg_w = 0;
2932 uint16_t reg_id = 0;
2934 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2936 switch (vlan_type) {
2937 case ETH_VLAN_TYPE_OUTER:
2943 case ETH_VLAN_TYPE_INNER:
2949 "Unsupported vlan type in single vlan.");
2955 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2958 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2960 if (ret != I40E_SUCCESS) {
2962 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2968 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2971 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2972 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2973 if (reg_r == reg_w) {
2975 PMD_DRV_LOG(DEBUG, "No need to write");
2979 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2981 if (ret != I40E_SUCCESS) {
2984 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2989 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2996 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2998 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2999 struct i40e_vsi *vsi = pf->main_vsi;
3001 if (mask & ETH_VLAN_FILTER_MASK) {
3002 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3003 i40e_vsi_config_vlan_filter(vsi, TRUE);
3005 i40e_vsi_config_vlan_filter(vsi, FALSE);
3008 if (mask & ETH_VLAN_STRIP_MASK) {
3009 /* Enable or disable VLAN stripping */
3010 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3011 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3013 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3016 if (mask & ETH_VLAN_EXTEND_MASK) {
3017 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3018 i40e_vsi_config_double_vlan(vsi, TRUE);
3019 /* Set global registers with default ether type value */
3020 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3022 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3026 i40e_vsi_config_double_vlan(vsi, FALSE);
3031 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3032 __rte_unused uint16_t queue,
3033 __rte_unused int on)
3035 PMD_INIT_FUNC_TRACE();
3039 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3042 struct i40e_vsi *vsi = pf->main_vsi;
3043 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3044 struct i40e_vsi_vlan_pvid_info info;
3046 memset(&info, 0, sizeof(info));
3049 info.config.pvid = pvid;
3051 info.config.reject.tagged =
3052 data->dev_conf.txmode.hw_vlan_reject_tagged;
3053 info.config.reject.untagged =
3054 data->dev_conf.txmode.hw_vlan_reject_untagged;
3057 return i40e_vsi_vlan_pvid_set(vsi, &info);
3061 i40e_dev_led_on(struct rte_eth_dev *dev)
3063 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3064 uint32_t mode = i40e_led_get(hw);
3067 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3073 i40e_dev_led_off(struct rte_eth_dev *dev)
3075 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076 uint32_t mode = i40e_led_get(hw);
3079 i40e_led_set(hw, 0, false);
3085 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3087 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3088 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3090 fc_conf->pause_time = pf->fc_conf.pause_time;
3091 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3092 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3094 /* Return current mode according to actual setting*/
3095 switch (hw->fc.current_mode) {
3097 fc_conf->mode = RTE_FC_FULL;
3099 case I40E_FC_TX_PAUSE:
3100 fc_conf->mode = RTE_FC_TX_PAUSE;
3102 case I40E_FC_RX_PAUSE:
3103 fc_conf->mode = RTE_FC_RX_PAUSE;
3107 fc_conf->mode = RTE_FC_NONE;
3114 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3116 uint32_t mflcn_reg, fctrl_reg, reg;
3117 uint32_t max_high_water;
3118 uint8_t i, aq_failure;
3122 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3123 [RTE_FC_NONE] = I40E_FC_NONE,
3124 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3125 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3126 [RTE_FC_FULL] = I40E_FC_FULL
3129 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3131 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3132 if ((fc_conf->high_water > max_high_water) ||
3133 (fc_conf->high_water < fc_conf->low_water)) {
3135 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3140 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3141 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3142 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3144 pf->fc_conf.pause_time = fc_conf->pause_time;
3145 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3146 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3148 PMD_INIT_FUNC_TRACE();
3150 /* All the link flow control related enable/disable register
3151 * configuration is handle by the F/W
3153 err = i40e_set_fc(hw, &aq_failure, true);
3157 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3158 /* Configure flow control refresh threshold,
3159 * the value for stat_tx_pause_refresh_timer[8]
3160 * is used for global pause operation.
3164 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3165 pf->fc_conf.pause_time);
3167 /* configure the timer value included in transmitted pause
3169 * the value for stat_tx_pause_quanta[8] is used for global
3172 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3173 pf->fc_conf.pause_time);
3175 fctrl_reg = I40E_READ_REG(hw,
3176 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3178 if (fc_conf->mac_ctrl_frame_fwd != 0)
3179 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3181 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3183 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3186 /* Configure pause time (2 TCs per register) */
3187 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3188 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3189 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3191 /* Configure flow control refresh threshold value */
3192 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3193 pf->fc_conf.pause_time / 2);
3195 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3197 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3198 *depending on configuration
3200 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3201 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3202 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3204 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3205 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3208 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3211 /* config the water marker both based on the packets and bytes */
3212 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3213 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3214 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3215 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3216 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3217 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3218 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3219 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3221 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3222 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3225 I40E_WRITE_FLUSH(hw);
3231 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3232 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3234 PMD_INIT_FUNC_TRACE();
3239 /* Add a MAC address, and update filters */
3241 i40e_macaddr_add(struct rte_eth_dev *dev,
3242 struct ether_addr *mac_addr,
3243 __rte_unused uint32_t index,
3246 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3247 struct i40e_mac_filter_info mac_filter;
3248 struct i40e_vsi *vsi;
3251 /* If VMDQ not enabled or configured, return */
3252 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3253 !pf->nb_cfg_vmdq_vsi)) {
3254 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3255 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3260 if (pool > pf->nb_cfg_vmdq_vsi) {
3261 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3262 pool, pf->nb_cfg_vmdq_vsi);
3266 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3267 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3268 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3270 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3275 vsi = pf->vmdq[pool - 1].vsi;
3277 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3278 if (ret != I40E_SUCCESS) {
3279 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3284 /* Remove a MAC address, and update filters */
3286 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3288 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3289 struct i40e_vsi *vsi;
3290 struct rte_eth_dev_data *data = dev->data;
3291 struct ether_addr *macaddr;
3296 macaddr = &(data->mac_addrs[index]);
3298 pool_sel = dev->data->mac_pool_sel[index];
3300 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3301 if (pool_sel & (1ULL << i)) {
3305 /* No VMDQ pool enabled or configured */
3306 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3307 (i > pf->nb_cfg_vmdq_vsi)) {
3309 "No VMDQ pool enabled/configured");
3312 vsi = pf->vmdq[i - 1].vsi;
3314 ret = i40e_vsi_delete_mac(vsi, macaddr);
3317 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3324 /* Set perfect match or hash match of MAC and VLAN for a VF */
3326 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3327 struct rte_eth_mac_filter *filter,
3331 struct i40e_mac_filter_info mac_filter;
3332 struct ether_addr old_mac;
3333 struct ether_addr *new_mac;
3334 struct i40e_pf_vf *vf = NULL;
3339 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3342 hw = I40E_PF_TO_HW(pf);
3344 if (filter == NULL) {
3345 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3349 new_mac = &filter->mac_addr;
3351 if (is_zero_ether_addr(new_mac)) {
3352 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3356 vf_id = filter->dst_id;
3358 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3359 PMD_DRV_LOG(ERR, "Invalid argument.");
3362 vf = &pf->vfs[vf_id];
3364 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3365 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3370 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3371 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3373 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3376 mac_filter.filter_type = filter->filter_type;
3377 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3378 if (ret != I40E_SUCCESS) {
3379 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3382 ether_addr_copy(new_mac, &pf->dev_addr);
3384 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3386 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3387 if (ret != I40E_SUCCESS) {
3388 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3392 /* Clear device address as it has been removed */
3393 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3394 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3400 /* MAC filter handle */
3402 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3405 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3406 struct rte_eth_mac_filter *filter;
3407 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3408 int ret = I40E_NOT_SUPPORTED;
3410 filter = (struct rte_eth_mac_filter *)(arg);
3412 switch (filter_op) {
3413 case RTE_ETH_FILTER_NOP:
3416 case RTE_ETH_FILTER_ADD:
3417 i40e_pf_disable_irq0(hw);
3419 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3420 i40e_pf_enable_irq0(hw);
3422 case RTE_ETH_FILTER_DELETE:
3423 i40e_pf_disable_irq0(hw);
3425 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3426 i40e_pf_enable_irq0(hw);
3429 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3430 ret = I40E_ERR_PARAM;
3438 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3440 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3441 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3447 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3448 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3451 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3455 uint32_t *lut_dw = (uint32_t *)lut;
3456 uint16_t i, lut_size_dw = lut_size / 4;
3458 for (i = 0; i < lut_size_dw; i++)
3459 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3466 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3475 pf = I40E_VSI_TO_PF(vsi);
3476 hw = I40E_VSI_TO_HW(vsi);
3478 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3479 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3482 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3486 uint32_t *lut_dw = (uint32_t *)lut;
3487 uint16_t i, lut_size_dw = lut_size / 4;
3489 for (i = 0; i < lut_size_dw; i++)
3490 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3491 I40E_WRITE_FLUSH(hw);
3498 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3499 struct rte_eth_rss_reta_entry64 *reta_conf,
3502 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3503 uint16_t i, lut_size = pf->hash_lut_size;
3504 uint16_t idx, shift;
3508 if (reta_size != lut_size ||
3509 reta_size > ETH_RSS_RETA_SIZE_512) {
3511 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3512 reta_size, lut_size);
3516 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3518 PMD_DRV_LOG(ERR, "No memory can be allocated");
3521 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3524 for (i = 0; i < reta_size; i++) {
3525 idx = i / RTE_RETA_GROUP_SIZE;
3526 shift = i % RTE_RETA_GROUP_SIZE;
3527 if (reta_conf[idx].mask & (1ULL << shift))
3528 lut[i] = reta_conf[idx].reta[shift];
3530 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3539 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3540 struct rte_eth_rss_reta_entry64 *reta_conf,
3543 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3544 uint16_t i, lut_size = pf->hash_lut_size;
3545 uint16_t idx, shift;
3549 if (reta_size != lut_size ||
3550 reta_size > ETH_RSS_RETA_SIZE_512) {
3552 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3553 reta_size, lut_size);
3557 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3559 PMD_DRV_LOG(ERR, "No memory can be allocated");
3563 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3566 for (i = 0; i < reta_size; i++) {
3567 idx = i / RTE_RETA_GROUP_SIZE;
3568 shift = i % RTE_RETA_GROUP_SIZE;
3569 if (reta_conf[idx].mask & (1ULL << shift))
3570 reta_conf[idx].reta[shift] = lut[i];
3580 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3581 * @hw: pointer to the HW structure
3582 * @mem: pointer to mem struct to fill out
3583 * @size: size of memory requested
3584 * @alignment: what to align the allocation to
3586 enum i40e_status_code
3587 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3588 struct i40e_dma_mem *mem,
3592 const struct rte_memzone *mz = NULL;
3593 char z_name[RTE_MEMZONE_NAMESIZE];
3596 return I40E_ERR_PARAM;
3598 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3599 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3600 alignment, RTE_PGSIZE_2M);
3602 return I40E_ERR_NO_MEMORY;
3606 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3607 mem->zone = (const void *)mz;
3609 "memzone %s allocated with physical address: %"PRIu64,
3612 return I40E_SUCCESS;
3616 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3617 * @hw: pointer to the HW structure
3618 * @mem: ptr to mem struct to free
3620 enum i40e_status_code
3621 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3622 struct i40e_dma_mem *mem)
3625 return I40E_ERR_PARAM;
3628 "memzone %s to be freed with physical address: %"PRIu64,
3629 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3630 rte_memzone_free((const struct rte_memzone *)mem->zone);
3635 return I40E_SUCCESS;
3639 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3640 * @hw: pointer to the HW structure
3641 * @mem: pointer to mem struct to fill out
3642 * @size: size of memory requested
3644 enum i40e_status_code
3645 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3646 struct i40e_virt_mem *mem,
3650 return I40E_ERR_PARAM;
3653 mem->va = rte_zmalloc("i40e", size, 0);
3656 return I40E_SUCCESS;
3658 return I40E_ERR_NO_MEMORY;
3662 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3663 * @hw: pointer to the HW structure
3664 * @mem: pointer to mem struct to free
3666 enum i40e_status_code
3667 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3668 struct i40e_virt_mem *mem)
3671 return I40E_ERR_PARAM;
3676 return I40E_SUCCESS;
3680 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3682 rte_spinlock_init(&sp->spinlock);
3686 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3688 rte_spinlock_lock(&sp->spinlock);
3692 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3694 rte_spinlock_unlock(&sp->spinlock);
3698 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3704 * Get the hardware capabilities, which will be parsed
3705 * and saved into struct i40e_hw.
3708 i40e_get_cap(struct i40e_hw *hw)
3710 struct i40e_aqc_list_capabilities_element_resp *buf;
3711 uint16_t len, size = 0;
3714 /* Calculate a huge enough buff for saving response data temporarily */
3715 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3716 I40E_MAX_CAP_ELE_NUM;
3717 buf = rte_zmalloc("i40e", len, 0);
3719 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3720 return I40E_ERR_NO_MEMORY;
3723 /* Get, parse the capabilities and save it to hw */
3724 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3725 i40e_aqc_opc_list_func_capabilities, NULL);
3726 if (ret != I40E_SUCCESS)
3727 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3729 /* Free the temporary buffer after being used */
3736 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3738 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3739 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3740 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3741 uint16_t qp_count = 0, vsi_count = 0;
3743 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3744 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3747 /* Add the parameter init for LFC */
3748 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3749 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3750 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3752 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3753 pf->max_num_vsi = hw->func_caps.num_vsis;
3754 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3755 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3756 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3758 /* FDir queue/VSI allocation */
3759 pf->fdir_qp_offset = 0;
3760 if (hw->func_caps.fd) {
3761 pf->flags |= I40E_FLAG_FDIR;
3762 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3764 pf->fdir_nb_qps = 0;
3766 qp_count += pf->fdir_nb_qps;
3769 /* LAN queue/VSI allocation */
3770 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3771 if (!hw->func_caps.rss) {
3774 pf->flags |= I40E_FLAG_RSS;
3775 if (hw->mac.type == I40E_MAC_X722)
3776 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3777 pf->lan_nb_qps = pf->lan_nb_qp_max;
3779 qp_count += pf->lan_nb_qps;
3782 /* VF queue/VSI allocation */
3783 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3784 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3785 pf->flags |= I40E_FLAG_SRIOV;
3786 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3787 pf->vf_num = pci_dev->max_vfs;
3789 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3790 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3795 qp_count += pf->vf_nb_qps * pf->vf_num;
3796 vsi_count += pf->vf_num;
3798 /* VMDq queue/VSI allocation */
3799 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3800 pf->vmdq_nb_qps = 0;
3801 pf->max_nb_vmdq_vsi = 0;
3802 if (hw->func_caps.vmdq) {
3803 if (qp_count < hw->func_caps.num_tx_qp &&
3804 vsi_count < hw->func_caps.num_vsis) {
3805 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3806 qp_count) / pf->vmdq_nb_qp_max;
3808 /* Limit the maximum number of VMDq vsi to the maximum
3809 * ethdev can support
3811 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3812 hw->func_caps.num_vsis - vsi_count);
3813 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3815 if (pf->max_nb_vmdq_vsi) {
3816 pf->flags |= I40E_FLAG_VMDQ;
3817 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3819 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3820 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3821 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3824 "No enough queues left for VMDq");
3827 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3830 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3831 vsi_count += pf->max_nb_vmdq_vsi;
3833 if (hw->func_caps.dcb)
3834 pf->flags |= I40E_FLAG_DCB;
3836 if (qp_count > hw->func_caps.num_tx_qp) {
3838 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3839 qp_count, hw->func_caps.num_tx_qp);
3842 if (vsi_count > hw->func_caps.num_vsis) {
3844 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3845 vsi_count, hw->func_caps.num_vsis);
3853 i40e_pf_get_switch_config(struct i40e_pf *pf)
3855 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3856 struct i40e_aqc_get_switch_config_resp *switch_config;
3857 struct i40e_aqc_switch_config_element_resp *element;
3858 uint16_t start_seid = 0, num_reported;
3861 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3862 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3863 if (!switch_config) {
3864 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3868 /* Get the switch configurations */
3869 ret = i40e_aq_get_switch_config(hw, switch_config,
3870 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3871 if (ret != I40E_SUCCESS) {
3872 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3875 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3876 if (num_reported != 1) { /* The number should be 1 */
3877 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3881 /* Parse the switch configuration elements */
3882 element = &(switch_config->element[0]);
3883 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3884 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3885 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3887 PMD_DRV_LOG(INFO, "Unknown element type");
3890 rte_free(switch_config);
3896 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3899 struct pool_entry *entry;
3901 if (pool == NULL || num == 0)
3904 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3905 if (entry == NULL) {
3906 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3910 /* queue heap initialize */
3911 pool->num_free = num;
3912 pool->num_alloc = 0;
3914 LIST_INIT(&pool->alloc_list);
3915 LIST_INIT(&pool->free_list);
3917 /* Initialize element */
3921 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3926 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3928 struct pool_entry *entry, *next_entry;
3933 for (entry = LIST_FIRST(&pool->alloc_list);
3934 entry && (next_entry = LIST_NEXT(entry, next), 1);
3935 entry = next_entry) {
3936 LIST_REMOVE(entry, next);
3940 for (entry = LIST_FIRST(&pool->free_list);
3941 entry && (next_entry = LIST_NEXT(entry, next), 1);
3942 entry = next_entry) {
3943 LIST_REMOVE(entry, next);
3948 pool->num_alloc = 0;
3950 LIST_INIT(&pool->alloc_list);
3951 LIST_INIT(&pool->free_list);
3955 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3958 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3959 uint32_t pool_offset;
3963 PMD_DRV_LOG(ERR, "Invalid parameter");
3967 pool_offset = base - pool->base;
3968 /* Lookup in alloc list */
3969 LIST_FOREACH(entry, &pool->alloc_list, next) {
3970 if (entry->base == pool_offset) {
3971 valid_entry = entry;
3972 LIST_REMOVE(entry, next);
3977 /* Not find, return */
3978 if (valid_entry == NULL) {
3979 PMD_DRV_LOG(ERR, "Failed to find entry");
3984 * Found it, move it to free list and try to merge.
3985 * In order to make merge easier, always sort it by qbase.
3986 * Find adjacent prev and last entries.
3989 LIST_FOREACH(entry, &pool->free_list, next) {
3990 if (entry->base > valid_entry->base) {
3998 /* Try to merge with next one*/
4000 /* Merge with next one */
4001 if (valid_entry->base + valid_entry->len == next->base) {
4002 next->base = valid_entry->base;
4003 next->len += valid_entry->len;
4004 rte_free(valid_entry);
4011 /* Merge with previous one */
4012 if (prev->base + prev->len == valid_entry->base) {
4013 prev->len += valid_entry->len;
4014 /* If it merge with next one, remove next node */
4016 LIST_REMOVE(valid_entry, next);
4017 rte_free(valid_entry);
4019 rte_free(valid_entry);
4025 /* Not find any entry to merge, insert */
4028 LIST_INSERT_AFTER(prev, valid_entry, next);
4029 else if (next != NULL)
4030 LIST_INSERT_BEFORE(next, valid_entry, next);
4031 else /* It's empty list, insert to head */
4032 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4035 pool->num_free += valid_entry->len;
4036 pool->num_alloc -= valid_entry->len;
4042 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4045 struct pool_entry *entry, *valid_entry;
4047 if (pool == NULL || num == 0) {
4048 PMD_DRV_LOG(ERR, "Invalid parameter");
4052 if (pool->num_free < num) {
4053 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4054 num, pool->num_free);
4059 /* Lookup in free list and find most fit one */
4060 LIST_FOREACH(entry, &pool->free_list, next) {
4061 if (entry->len >= num) {
4063 if (entry->len == num) {
4064 valid_entry = entry;
4067 if (valid_entry == NULL || valid_entry->len > entry->len)
4068 valid_entry = entry;
4072 /* Not find one to satisfy the request, return */
4073 if (valid_entry == NULL) {
4074 PMD_DRV_LOG(ERR, "No valid entry found");
4078 * The entry have equal queue number as requested,
4079 * remove it from alloc_list.
4081 if (valid_entry->len == num) {
4082 LIST_REMOVE(valid_entry, next);
4085 * The entry have more numbers than requested,
4086 * create a new entry for alloc_list and minus its
4087 * queue base and number in free_list.
4089 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4090 if (entry == NULL) {
4092 "Failed to allocate memory for resource pool");
4095 entry->base = valid_entry->base;
4097 valid_entry->base += num;
4098 valid_entry->len -= num;
4099 valid_entry = entry;
4102 /* Insert it into alloc list, not sorted */
4103 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4105 pool->num_free -= valid_entry->len;
4106 pool->num_alloc += valid_entry->len;
4108 return valid_entry->base + pool->base;
4112 * bitmap_is_subset - Check whether src2 is subset of src1
4115 bitmap_is_subset(uint8_t src1, uint8_t src2)
4117 return !((src1 ^ src2) & src2);
4120 static enum i40e_status_code
4121 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4123 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4125 /* If DCB is not supported, only default TC is supported */
4126 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4127 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4128 return I40E_NOT_SUPPORTED;
4131 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4133 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4134 hw->func_caps.enabled_tcmap, enabled_tcmap);
4135 return I40E_NOT_SUPPORTED;
4137 return I40E_SUCCESS;
4141 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4142 struct i40e_vsi_vlan_pvid_info *info)
4145 struct i40e_vsi_context ctxt;
4146 uint8_t vlan_flags = 0;
4149 if (vsi == NULL || info == NULL) {
4150 PMD_DRV_LOG(ERR, "invalid parameters");
4151 return I40E_ERR_PARAM;
4155 vsi->info.pvid = info->config.pvid;
4157 * If insert pvid is enabled, only tagged pkts are
4158 * allowed to be sent out.
4160 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4161 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4164 if (info->config.reject.tagged == 0)
4165 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4167 if (info->config.reject.untagged == 0)
4168 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4170 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4171 I40E_AQ_VSI_PVLAN_MODE_MASK);
4172 vsi->info.port_vlan_flags |= vlan_flags;
4173 vsi->info.valid_sections =
4174 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4175 memset(&ctxt, 0, sizeof(ctxt));
4176 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4177 ctxt.seid = vsi->seid;
4179 hw = I40E_VSI_TO_HW(vsi);
4180 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4181 if (ret != I40E_SUCCESS)
4182 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4188 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4190 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4192 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4194 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4195 if (ret != I40E_SUCCESS)
4199 PMD_DRV_LOG(ERR, "seid not valid");
4203 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4204 tc_bw_data.tc_valid_bits = enabled_tcmap;
4205 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4206 tc_bw_data.tc_bw_credits[i] =
4207 (enabled_tcmap & (1 << i)) ? 1 : 0;
4209 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4210 if (ret != I40E_SUCCESS) {
4211 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4215 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4216 sizeof(vsi->info.qs_handle));
4217 return I40E_SUCCESS;
4220 static enum i40e_status_code
4221 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4222 struct i40e_aqc_vsi_properties_data *info,
4223 uint8_t enabled_tcmap)
4225 enum i40e_status_code ret;
4226 int i, total_tc = 0;
4227 uint16_t qpnum_per_tc, bsf, qp_idx;
4229 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4230 if (ret != I40E_SUCCESS)
4233 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4234 if (enabled_tcmap & (1 << i))
4236 vsi->enabled_tc = enabled_tcmap;
4238 /* Number of queues per enabled TC */
4239 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4240 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4241 bsf = rte_bsf32(qpnum_per_tc);
4243 /* Adjust the queue number to actual queues that can be applied */
4244 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4245 vsi->nb_qps = qpnum_per_tc * total_tc;
4248 * Configure TC and queue mapping parameters, for enabled TC,
4249 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4250 * default queue will serve it.
4253 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4254 if (vsi->enabled_tc & (1 << i)) {
4255 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4256 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4257 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4258 qp_idx += qpnum_per_tc;
4260 info->tc_mapping[i] = 0;
4263 /* Associate queue number with VSI */
4264 if (vsi->type == I40E_VSI_SRIOV) {
4265 info->mapping_flags |=
4266 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4267 for (i = 0; i < vsi->nb_qps; i++)
4268 info->queue_mapping[i] =
4269 rte_cpu_to_le_16(vsi->base_queue + i);
4271 info->mapping_flags |=
4272 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4273 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4275 info->valid_sections |=
4276 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4278 return I40E_SUCCESS;
4282 i40e_veb_release(struct i40e_veb *veb)
4284 struct i40e_vsi *vsi;
4290 if (!TAILQ_EMPTY(&veb->head)) {
4291 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4294 /* associate_vsi field is NULL for floating VEB */
4295 if (veb->associate_vsi != NULL) {
4296 vsi = veb->associate_vsi;
4297 hw = I40E_VSI_TO_HW(vsi);
4299 vsi->uplink_seid = veb->uplink_seid;
4302 veb->associate_pf->main_vsi->floating_veb = NULL;
4303 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4306 i40e_aq_delete_element(hw, veb->seid, NULL);
4308 return I40E_SUCCESS;
4312 static struct i40e_veb *
4313 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4315 struct i40e_veb *veb;
4321 "veb setup failed, associated PF shouldn't null");
4324 hw = I40E_PF_TO_HW(pf);
4326 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4328 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4332 veb->associate_vsi = vsi;
4333 veb->associate_pf = pf;
4334 TAILQ_INIT(&veb->head);
4335 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4337 /* create floating veb if vsi is NULL */
4339 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4340 I40E_DEFAULT_TCMAP, false,
4341 &veb->seid, false, NULL);
4343 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4344 true, &veb->seid, false, NULL);
4347 if (ret != I40E_SUCCESS) {
4348 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4349 hw->aq.asq_last_status);
4352 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4354 /* get statistics index */
4355 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4356 &veb->stats_idx, NULL, NULL, NULL);
4357 if (ret != I40E_SUCCESS) {
4358 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4359 hw->aq.asq_last_status);
4362 /* Get VEB bandwidth, to be implemented */
4363 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4365 vsi->uplink_seid = veb->seid;
4374 i40e_vsi_release(struct i40e_vsi *vsi)
4378 struct i40e_vsi_list *vsi_list;
4381 struct i40e_mac_filter *f;
4382 uint16_t user_param;
4385 return I40E_SUCCESS;
4390 user_param = vsi->user_param;
4392 pf = I40E_VSI_TO_PF(vsi);
4393 hw = I40E_VSI_TO_HW(vsi);
4395 /* VSI has child to attach, release child first */
4397 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4398 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4401 i40e_veb_release(vsi->veb);
4404 if (vsi->floating_veb) {
4405 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4406 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4411 /* Remove all macvlan filters of the VSI */
4412 i40e_vsi_remove_all_macvlan_filter(vsi);
4413 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4416 if (vsi->type != I40E_VSI_MAIN &&
4417 ((vsi->type != I40E_VSI_SRIOV) ||
4418 !pf->floating_veb_list[user_param])) {
4419 /* Remove vsi from parent's sibling list */
4420 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4421 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4422 return I40E_ERR_PARAM;
4424 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4425 &vsi->sib_vsi_list, list);
4427 /* Remove all switch element of the VSI */
4428 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4429 if (ret != I40E_SUCCESS)
4430 PMD_DRV_LOG(ERR, "Failed to delete element");
4433 if ((vsi->type == I40E_VSI_SRIOV) &&
4434 pf->floating_veb_list[user_param]) {
4435 /* Remove vsi from parent's sibling list */
4436 if (vsi->parent_vsi == NULL ||
4437 vsi->parent_vsi->floating_veb == NULL) {
4438 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4439 return I40E_ERR_PARAM;
4441 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4442 &vsi->sib_vsi_list, list);
4444 /* Remove all switch element of the VSI */
4445 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4446 if (ret != I40E_SUCCESS)
4447 PMD_DRV_LOG(ERR, "Failed to delete element");
4450 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4452 if (vsi->type != I40E_VSI_SRIOV)
4453 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4456 return I40E_SUCCESS;
4460 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4462 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4463 struct i40e_aqc_remove_macvlan_element_data def_filter;
4464 struct i40e_mac_filter_info filter;
4467 if (vsi->type != I40E_VSI_MAIN)
4468 return I40E_ERR_CONFIG;
4469 memset(&def_filter, 0, sizeof(def_filter));
4470 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4472 def_filter.vlan_tag = 0;
4473 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4474 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4475 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4476 if (ret != I40E_SUCCESS) {
4477 struct i40e_mac_filter *f;
4478 struct ether_addr *mac;
4480 PMD_DRV_LOG(WARNING,
4481 "Cannot remove the default macvlan filter");
4482 /* It needs to add the permanent mac into mac list */
4483 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4485 PMD_DRV_LOG(ERR, "failed to allocate memory");
4486 return I40E_ERR_NO_MEMORY;
4488 mac = &f->mac_info.mac_addr;
4489 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4491 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4492 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4497 (void)rte_memcpy(&filter.mac_addr,
4498 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4499 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4500 return i40e_vsi_add_mac(vsi, &filter);
4504 * i40e_vsi_get_bw_config - Query VSI BW Information
4505 * @vsi: the VSI to be queried
4507 * Returns 0 on success, negative value on failure
4509 static enum i40e_status_code
4510 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4512 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4513 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4514 struct i40e_hw *hw = &vsi->adapter->hw;
4519 memset(&bw_config, 0, sizeof(bw_config));
4520 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4521 if (ret != I40E_SUCCESS) {
4522 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4523 hw->aq.asq_last_status);
4527 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4528 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4529 &ets_sla_config, NULL);
4530 if (ret != I40E_SUCCESS) {
4532 "VSI failed to get TC bandwdith configuration %u",
4533 hw->aq.asq_last_status);
4537 /* store and print out BW info */
4538 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4539 vsi->bw_info.bw_max = bw_config.max_bw;
4540 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4541 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4542 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4543 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4545 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4546 vsi->bw_info.bw_ets_share_credits[i] =
4547 ets_sla_config.share_credits[i];
4548 vsi->bw_info.bw_ets_credits[i] =
4549 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4550 /* 4 bits per TC, 4th bit is reserved */
4551 vsi->bw_info.bw_ets_max[i] =
4552 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4553 RTE_LEN2MASK(3, uint8_t));
4554 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4555 vsi->bw_info.bw_ets_share_credits[i]);
4556 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4557 vsi->bw_info.bw_ets_credits[i]);
4558 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4559 vsi->bw_info.bw_ets_max[i]);
4562 return I40E_SUCCESS;
4565 /* i40e_enable_pf_lb
4566 * @pf: pointer to the pf structure
4568 * allow loopback on pf
4571 i40e_enable_pf_lb(struct i40e_pf *pf)
4573 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4574 struct i40e_vsi_context ctxt;
4577 /* Use the FW API if FW >= v5.0 */
4578 if (hw->aq.fw_maj_ver < 5) {
4579 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4583 memset(&ctxt, 0, sizeof(ctxt));
4584 ctxt.seid = pf->main_vsi_seid;
4585 ctxt.pf_num = hw->pf_id;
4586 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4588 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4589 ret, hw->aq.asq_last_status);
4592 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4593 ctxt.info.valid_sections =
4594 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4595 ctxt.info.switch_id |=
4596 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4598 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4600 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4601 hw->aq.asq_last_status);
4606 i40e_vsi_setup(struct i40e_pf *pf,
4607 enum i40e_vsi_type type,
4608 struct i40e_vsi *uplink_vsi,
4609 uint16_t user_param)
4611 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4612 struct i40e_vsi *vsi;
4613 struct i40e_mac_filter_info filter;
4615 struct i40e_vsi_context ctxt;
4616 struct ether_addr broadcast =
4617 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4619 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4620 uplink_vsi == NULL) {
4622 "VSI setup failed, VSI link shouldn't be NULL");
4626 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4628 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4633 * 1.type is not MAIN and uplink vsi is not NULL
4634 * If uplink vsi didn't setup VEB, create one first under veb field
4635 * 2.type is SRIOV and the uplink is NULL
4636 * If floating VEB is NULL, create one veb under floating veb field
4639 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4640 uplink_vsi->veb == NULL) {
4641 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4643 if (uplink_vsi->veb == NULL) {
4644 PMD_DRV_LOG(ERR, "VEB setup failed");
4647 /* set ALLOWLOOPBACk on pf, when veb is created */
4648 i40e_enable_pf_lb(pf);
4651 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4652 pf->main_vsi->floating_veb == NULL) {
4653 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4655 if (pf->main_vsi->floating_veb == NULL) {
4656 PMD_DRV_LOG(ERR, "VEB setup failed");
4661 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4663 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4666 TAILQ_INIT(&vsi->mac_list);
4668 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4669 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4670 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4671 vsi->user_param = user_param;
4672 vsi->vlan_anti_spoof_on = 0;
4673 /* Allocate queues */
4674 switch (vsi->type) {
4675 case I40E_VSI_MAIN :
4676 vsi->nb_qps = pf->lan_nb_qps;
4678 case I40E_VSI_SRIOV :
4679 vsi->nb_qps = pf->vf_nb_qps;
4681 case I40E_VSI_VMDQ2:
4682 vsi->nb_qps = pf->vmdq_nb_qps;
4685 vsi->nb_qps = pf->fdir_nb_qps;
4691 * The filter status descriptor is reported in rx queue 0,
4692 * while the tx queue for fdir filter programming has no
4693 * such constraints, can be non-zero queues.
4694 * To simplify it, choose FDIR vsi use queue 0 pair.
4695 * To make sure it will use queue 0 pair, queue allocation
4696 * need be done before this function is called
4698 if (type != I40E_VSI_FDIR) {
4699 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4701 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4705 vsi->base_queue = ret;
4707 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4709 /* VF has MSIX interrupt in VF range, don't allocate here */
4710 if (type == I40E_VSI_MAIN) {
4711 ret = i40e_res_pool_alloc(&pf->msix_pool,
4712 RTE_MIN(vsi->nb_qps,
4713 RTE_MAX_RXTX_INTR_VEC_ID));
4715 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4717 goto fail_queue_alloc;
4719 vsi->msix_intr = ret;
4720 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4721 } else if (type != I40E_VSI_SRIOV) {
4722 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4724 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4725 goto fail_queue_alloc;
4727 vsi->msix_intr = ret;
4735 if (type == I40E_VSI_MAIN) {
4736 /* For main VSI, no need to add since it's default one */
4737 vsi->uplink_seid = pf->mac_seid;
4738 vsi->seid = pf->main_vsi_seid;
4739 /* Bind queues with specific MSIX interrupt */
4741 * Needs 2 interrupt at least, one for misc cause which will
4742 * enabled from OS side, Another for queues binding the
4743 * interrupt from device side only.
4746 /* Get default VSI parameters from hardware */
4747 memset(&ctxt, 0, sizeof(ctxt));
4748 ctxt.seid = vsi->seid;
4749 ctxt.pf_num = hw->pf_id;
4750 ctxt.uplink_seid = vsi->uplink_seid;
4752 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4753 if (ret != I40E_SUCCESS) {
4754 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4755 goto fail_msix_alloc;
4757 (void)rte_memcpy(&vsi->info, &ctxt.info,
4758 sizeof(struct i40e_aqc_vsi_properties_data));
4759 vsi->vsi_id = ctxt.vsi_number;
4760 vsi->info.valid_sections = 0;
4762 /* Configure tc, enabled TC0 only */
4763 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4765 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4766 goto fail_msix_alloc;
4769 /* TC, queue mapping */
4770 memset(&ctxt, 0, sizeof(ctxt));
4771 vsi->info.valid_sections |=
4772 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4773 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4774 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4775 (void)rte_memcpy(&ctxt.info, &vsi->info,
4776 sizeof(struct i40e_aqc_vsi_properties_data));
4777 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4778 I40E_DEFAULT_TCMAP);
4779 if (ret != I40E_SUCCESS) {
4781 "Failed to configure TC queue mapping");
4782 goto fail_msix_alloc;
4784 ctxt.seid = vsi->seid;
4785 ctxt.pf_num = hw->pf_id;
4786 ctxt.uplink_seid = vsi->uplink_seid;
4789 /* Update VSI parameters */
4790 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4791 if (ret != I40E_SUCCESS) {
4792 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4793 goto fail_msix_alloc;
4796 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4797 sizeof(vsi->info.tc_mapping));
4798 (void)rte_memcpy(&vsi->info.queue_mapping,
4799 &ctxt.info.queue_mapping,
4800 sizeof(vsi->info.queue_mapping));
4801 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4802 vsi->info.valid_sections = 0;
4804 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4808 * Updating default filter settings are necessary to prevent
4809 * reception of tagged packets.
4810 * Some old firmware configurations load a default macvlan
4811 * filter which accepts both tagged and untagged packets.
4812 * The updating is to use a normal filter instead if needed.
4813 * For NVM 4.2.2 or after, the updating is not needed anymore.
4814 * The firmware with correct configurations load the default
4815 * macvlan filter which is expected and cannot be removed.
4817 i40e_update_default_filter_setting(vsi);
4818 i40e_config_qinq(hw, vsi);
4819 } else if (type == I40E_VSI_SRIOV) {
4820 memset(&ctxt, 0, sizeof(ctxt));
4822 * For other VSI, the uplink_seid equals to uplink VSI's
4823 * uplink_seid since they share same VEB
4825 if (uplink_vsi == NULL)
4826 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4828 vsi->uplink_seid = uplink_vsi->uplink_seid;
4829 ctxt.pf_num = hw->pf_id;
4830 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4831 ctxt.uplink_seid = vsi->uplink_seid;
4832 ctxt.connection_type = 0x1;
4833 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4835 /* Use the VEB configuration if FW >= v5.0 */
4836 if (hw->aq.fw_maj_ver >= 5) {
4837 /* Configure switch ID */
4838 ctxt.info.valid_sections |=
4839 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4840 ctxt.info.switch_id =
4841 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4844 /* Configure port/vlan */
4845 ctxt.info.valid_sections |=
4846 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4847 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4848 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4849 hw->func_caps.enabled_tcmap);
4850 if (ret != I40E_SUCCESS) {
4852 "Failed to configure TC queue mapping");
4853 goto fail_msix_alloc;
4856 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4857 ctxt.info.valid_sections |=
4858 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4860 * Since VSI is not created yet, only configure parameter,
4861 * will add vsi below.
4864 i40e_config_qinq(hw, vsi);
4865 } else if (type == I40E_VSI_VMDQ2) {
4866 memset(&ctxt, 0, sizeof(ctxt));
4868 * For other VSI, the uplink_seid equals to uplink VSI's
4869 * uplink_seid since they share same VEB
4871 vsi->uplink_seid = uplink_vsi->uplink_seid;
4872 ctxt.pf_num = hw->pf_id;
4874 ctxt.uplink_seid = vsi->uplink_seid;
4875 ctxt.connection_type = 0x1;
4876 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4878 ctxt.info.valid_sections |=
4879 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4880 /* user_param carries flag to enable loop back */
4882 ctxt.info.switch_id =
4883 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4884 ctxt.info.switch_id |=
4885 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4888 /* Configure port/vlan */
4889 ctxt.info.valid_sections |=
4890 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4891 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4892 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4893 I40E_DEFAULT_TCMAP);
4894 if (ret != I40E_SUCCESS) {
4896 "Failed to configure TC queue mapping");
4897 goto fail_msix_alloc;
4899 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4900 ctxt.info.valid_sections |=
4901 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4902 } else if (type == I40E_VSI_FDIR) {
4903 memset(&ctxt, 0, sizeof(ctxt));
4904 vsi->uplink_seid = uplink_vsi->uplink_seid;
4905 ctxt.pf_num = hw->pf_id;
4907 ctxt.uplink_seid = vsi->uplink_seid;
4908 ctxt.connection_type = 0x1; /* regular data port */
4909 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4910 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4911 I40E_DEFAULT_TCMAP);
4912 if (ret != I40E_SUCCESS) {
4914 "Failed to configure TC queue mapping.");
4915 goto fail_msix_alloc;
4917 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4918 ctxt.info.valid_sections |=
4919 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4921 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4922 goto fail_msix_alloc;
4925 if (vsi->type != I40E_VSI_MAIN) {
4926 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4927 if (ret != I40E_SUCCESS) {
4928 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4929 hw->aq.asq_last_status);
4930 goto fail_msix_alloc;
4932 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4933 vsi->info.valid_sections = 0;
4934 vsi->seid = ctxt.seid;
4935 vsi->vsi_id = ctxt.vsi_number;
4936 vsi->sib_vsi_list.vsi = vsi;
4937 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4938 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4939 &vsi->sib_vsi_list, list);
4941 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4942 &vsi->sib_vsi_list, list);
4946 /* MAC/VLAN configuration */
4947 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4948 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4950 ret = i40e_vsi_add_mac(vsi, &filter);
4951 if (ret != I40E_SUCCESS) {
4952 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4953 goto fail_msix_alloc;
4956 /* Get VSI BW information */
4957 i40e_vsi_get_bw_config(vsi);
4960 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4962 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4968 /* Configure vlan filter on or off */
4970 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4973 struct i40e_mac_filter *f;
4975 struct i40e_mac_filter_info *mac_filter;
4976 enum rte_mac_filter_type desired_filter;
4977 int ret = I40E_SUCCESS;
4980 /* Filter to match MAC and VLAN */
4981 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4983 /* Filter to match only MAC */
4984 desired_filter = RTE_MAC_PERFECT_MATCH;
4989 mac_filter = rte_zmalloc("mac_filter_info_data",
4990 num * sizeof(*mac_filter), 0);
4991 if (mac_filter == NULL) {
4992 PMD_DRV_LOG(ERR, "failed to allocate memory");
4993 return I40E_ERR_NO_MEMORY;
4998 /* Remove all existing mac */
4999 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5000 mac_filter[i] = f->mac_info;
5001 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5003 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5004 on ? "enable" : "disable");
5010 /* Override with new filter */
5011 for (i = 0; i < num; i++) {
5012 mac_filter[i].filter_type = desired_filter;
5013 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5015 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5016 on ? "enable" : "disable");
5022 rte_free(mac_filter);
5026 /* Configure vlan stripping on or off */
5028 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5030 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5031 struct i40e_vsi_context ctxt;
5033 int ret = I40E_SUCCESS;
5035 /* Check if it has been already on or off */
5036 if (vsi->info.valid_sections &
5037 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5039 if ((vsi->info.port_vlan_flags &
5040 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5041 return 0; /* already on */
5043 if ((vsi->info.port_vlan_flags &
5044 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5045 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5046 return 0; /* already off */
5051 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5053 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5054 vsi->info.valid_sections =
5055 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5056 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5057 vsi->info.port_vlan_flags |= vlan_flags;
5058 ctxt.seid = vsi->seid;
5059 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5060 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5062 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5063 on ? "enable" : "disable");
5069 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5071 struct rte_eth_dev_data *data = dev->data;
5075 /* Apply vlan offload setting */
5076 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5077 i40e_vlan_offload_set(dev, mask);
5079 /* Apply double-vlan setting, not implemented yet */
5081 /* Apply pvid setting */
5082 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5083 data->dev_conf.txmode.hw_vlan_insert_pvid);
5085 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5091 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5093 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5095 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5099 i40e_update_flow_control(struct i40e_hw *hw)
5101 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5102 struct i40e_link_status link_status;
5103 uint32_t rxfc = 0, txfc = 0, reg;
5107 memset(&link_status, 0, sizeof(link_status));
5108 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5109 if (ret != I40E_SUCCESS) {
5110 PMD_DRV_LOG(ERR, "Failed to get link status information");
5111 goto write_reg; /* Disable flow control */
5114 an_info = hw->phy.link_info.an_info;
5115 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5116 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5117 ret = I40E_ERR_NOT_READY;
5118 goto write_reg; /* Disable flow control */
5121 * If link auto negotiation is enabled, flow control needs to
5122 * be configured according to it
5124 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5125 case I40E_LINK_PAUSE_RXTX:
5128 hw->fc.current_mode = I40E_FC_FULL;
5130 case I40E_AQ_LINK_PAUSE_RX:
5132 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5134 case I40E_AQ_LINK_PAUSE_TX:
5136 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5139 hw->fc.current_mode = I40E_FC_NONE;
5144 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5145 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5146 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5147 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5148 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5149 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5156 i40e_pf_setup(struct i40e_pf *pf)
5158 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5159 struct i40e_filter_control_settings settings;
5160 struct i40e_vsi *vsi;
5163 /* Clear all stats counters */
5164 pf->offset_loaded = FALSE;
5165 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5166 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5168 ret = i40e_pf_get_switch_config(pf);
5169 if (ret != I40E_SUCCESS) {
5170 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5173 if (pf->flags & I40E_FLAG_FDIR) {
5174 /* make queue allocated first, let FDIR use queue pair 0*/
5175 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5176 if (ret != I40E_FDIR_QUEUE_ID) {
5178 "queue allocation fails for FDIR: ret =%d",
5180 pf->flags &= ~I40E_FLAG_FDIR;
5183 /* main VSI setup */
5184 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5186 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5187 return I40E_ERR_NOT_READY;
5191 /* Configure filter control */
5192 memset(&settings, 0, sizeof(settings));
5193 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5194 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5195 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5196 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5198 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5199 hw->func_caps.rss_table_size);
5200 return I40E_ERR_PARAM;
5202 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5203 hw->func_caps.rss_table_size);
5204 pf->hash_lut_size = hw->func_caps.rss_table_size;
5206 /* Enable ethtype and macvlan filters */
5207 settings.enable_ethtype = TRUE;
5208 settings.enable_macvlan = TRUE;
5209 ret = i40e_set_filter_control(hw, &settings);
5211 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5214 /* Update flow control according to the auto negotiation */
5215 i40e_update_flow_control(hw);
5217 return I40E_SUCCESS;
5221 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5227 * Set or clear TX Queue Disable flags,
5228 * which is required by hardware.
5230 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5231 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5233 /* Wait until the request is finished */
5234 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5235 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5236 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5237 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5238 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5244 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5245 return I40E_SUCCESS; /* already on, skip next steps */
5247 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5248 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5250 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5251 return I40E_SUCCESS; /* already off, skip next steps */
5252 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5254 /* Write the register */
5255 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5256 /* Check the result */
5257 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5258 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5259 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5261 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5262 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5265 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5266 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5270 /* Check if it is timeout */
5271 if (j >= I40E_CHK_Q_ENA_COUNT) {
5272 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5273 (on ? "enable" : "disable"), q_idx);
5274 return I40E_ERR_TIMEOUT;
5277 return I40E_SUCCESS;
5280 /* Swith on or off the tx queues */
5282 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5284 struct rte_eth_dev_data *dev_data = pf->dev_data;
5285 struct i40e_tx_queue *txq;
5286 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5290 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5291 txq = dev_data->tx_queues[i];
5292 /* Don't operate the queue if not configured or
5293 * if starting only per queue */
5294 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5297 ret = i40e_dev_tx_queue_start(dev, i);
5299 ret = i40e_dev_tx_queue_stop(dev, i);
5300 if ( ret != I40E_SUCCESS)
5304 return I40E_SUCCESS;
5308 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5313 /* Wait until the request is finished */
5314 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5315 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5316 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5317 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5318 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5323 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5324 return I40E_SUCCESS; /* Already on, skip next steps */
5325 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5327 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5328 return I40E_SUCCESS; /* Already off, skip next steps */
5329 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5332 /* Write the register */
5333 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5334 /* Check the result */
5335 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5336 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5337 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5339 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5340 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5343 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5344 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5349 /* Check if it is timeout */
5350 if (j >= I40E_CHK_Q_ENA_COUNT) {
5351 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5352 (on ? "enable" : "disable"), q_idx);
5353 return I40E_ERR_TIMEOUT;
5356 return I40E_SUCCESS;
5358 /* Switch on or off the rx queues */
5360 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5362 struct rte_eth_dev_data *dev_data = pf->dev_data;
5363 struct i40e_rx_queue *rxq;
5364 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5368 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5369 rxq = dev_data->rx_queues[i];
5370 /* Don't operate the queue if not configured or
5371 * if starting only per queue */
5372 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5375 ret = i40e_dev_rx_queue_start(dev, i);
5377 ret = i40e_dev_rx_queue_stop(dev, i);
5378 if (ret != I40E_SUCCESS)
5382 return I40E_SUCCESS;
5385 /* Switch on or off all the rx/tx queues */
5387 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5392 /* enable rx queues before enabling tx queues */
5393 ret = i40e_dev_switch_rx_queues(pf, on);
5395 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5398 ret = i40e_dev_switch_tx_queues(pf, on);
5400 /* Stop tx queues before stopping rx queues */
5401 ret = i40e_dev_switch_tx_queues(pf, on);
5403 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5406 ret = i40e_dev_switch_rx_queues(pf, on);
5412 /* Initialize VSI for TX */
5414 i40e_dev_tx_init(struct i40e_pf *pf)
5416 struct rte_eth_dev_data *data = pf->dev_data;
5418 uint32_t ret = I40E_SUCCESS;
5419 struct i40e_tx_queue *txq;
5421 for (i = 0; i < data->nb_tx_queues; i++) {
5422 txq = data->tx_queues[i];
5423 if (!txq || !txq->q_set)
5425 ret = i40e_tx_queue_init(txq);
5426 if (ret != I40E_SUCCESS)
5429 if (ret == I40E_SUCCESS)
5430 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5436 /* Initialize VSI for RX */
5438 i40e_dev_rx_init(struct i40e_pf *pf)
5440 struct rte_eth_dev_data *data = pf->dev_data;
5441 int ret = I40E_SUCCESS;
5443 struct i40e_rx_queue *rxq;
5445 i40e_pf_config_mq_rx(pf);
5446 for (i = 0; i < data->nb_rx_queues; i++) {
5447 rxq = data->rx_queues[i];
5448 if (!rxq || !rxq->q_set)
5451 ret = i40e_rx_queue_init(rxq);
5452 if (ret != I40E_SUCCESS) {
5454 "Failed to do RX queue initialization");
5458 if (ret == I40E_SUCCESS)
5459 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5466 i40e_dev_rxtx_init(struct i40e_pf *pf)
5470 err = i40e_dev_tx_init(pf);
5472 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5475 err = i40e_dev_rx_init(pf);
5477 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5485 i40e_vmdq_setup(struct rte_eth_dev *dev)
5487 struct rte_eth_conf *conf = &dev->data->dev_conf;
5488 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5489 int i, err, conf_vsis, j, loop;
5490 struct i40e_vsi *vsi;
5491 struct i40e_vmdq_info *vmdq_info;
5492 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5493 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5496 * Disable interrupt to avoid message from VF. Furthermore, it will
5497 * avoid race condition in VSI creation/destroy.
5499 i40e_pf_disable_irq0(hw);
5501 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5502 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5506 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5507 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5508 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5509 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5510 pf->max_nb_vmdq_vsi);
5514 if (pf->vmdq != NULL) {
5515 PMD_INIT_LOG(INFO, "VMDQ already configured");
5519 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5520 sizeof(*vmdq_info) * conf_vsis, 0);
5522 if (pf->vmdq == NULL) {
5523 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5527 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5529 /* Create VMDQ VSI */
5530 for (i = 0; i < conf_vsis; i++) {
5531 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5532 vmdq_conf->enable_loop_back);
5534 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5538 vmdq_info = &pf->vmdq[i];
5540 vmdq_info->vsi = vsi;
5542 pf->nb_cfg_vmdq_vsi = conf_vsis;
5544 /* Configure Vlan */
5545 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5546 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5547 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5548 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5549 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5550 vmdq_conf->pool_map[i].vlan_id, j);
5552 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5553 vmdq_conf->pool_map[i].vlan_id);
5555 PMD_INIT_LOG(ERR, "Failed to add vlan");
5563 i40e_pf_enable_irq0(hw);
5568 for (i = 0; i < conf_vsis; i++)
5569 if (pf->vmdq[i].vsi == NULL)
5572 i40e_vsi_release(pf->vmdq[i].vsi);
5576 i40e_pf_enable_irq0(hw);
5581 i40e_stat_update_32(struct i40e_hw *hw,
5589 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5593 if (new_data >= *offset)
5594 *stat = (uint64_t)(new_data - *offset);
5596 *stat = (uint64_t)((new_data +
5597 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5601 i40e_stat_update_48(struct i40e_hw *hw,
5610 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5611 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5612 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5617 if (new_data >= *offset)
5618 *stat = new_data - *offset;
5620 *stat = (uint64_t)((new_data +
5621 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5623 *stat &= I40E_48_BIT_MASK;
5628 i40e_pf_disable_irq0(struct i40e_hw *hw)
5630 /* Disable all interrupt types */
5631 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5632 I40E_WRITE_FLUSH(hw);
5637 i40e_pf_enable_irq0(struct i40e_hw *hw)
5639 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5640 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5641 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5642 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5643 I40E_WRITE_FLUSH(hw);
5647 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5649 /* read pending request and disable first */
5650 i40e_pf_disable_irq0(hw);
5651 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5652 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5653 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5656 /* Link no queues with irq0 */
5657 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5658 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5662 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5665 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5668 uint32_t index, offset, val;
5673 * Try to find which VF trigger a reset, use absolute VF id to access
5674 * since the reg is global register.
5676 for (i = 0; i < pf->vf_num; i++) {
5677 abs_vf_id = hw->func_caps.vf_base_id + i;
5678 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5679 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5680 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5681 /* VFR event occured */
5682 if (val & (0x1 << offset)) {
5685 /* Clear the event first */
5686 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5688 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5690 * Only notify a VF reset event occured,
5691 * don't trigger another SW reset
5693 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5694 if (ret != I40E_SUCCESS)
5695 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5701 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5704 struct i40e_virtchnl_pf_event event;
5707 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5708 event.event_data.link_event.link_status =
5709 dev->data->dev_link.link_status;
5710 event.event_data.link_event.link_speed =
5711 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5713 for (i = 0; i < pf->vf_num; i++)
5714 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5715 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5719 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5721 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5722 struct i40e_arq_event_info info;
5723 uint16_t pending, opcode;
5726 info.buf_len = I40E_AQ_BUF_SZ;
5727 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5728 if (!info.msg_buf) {
5729 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5735 ret = i40e_clean_arq_element(hw, &info, &pending);
5737 if (ret != I40E_SUCCESS) {
5739 "Failed to read msg from AdminQ, aq_err: %u",
5740 hw->aq.asq_last_status);
5743 opcode = rte_le_to_cpu_16(info.desc.opcode);
5746 case i40e_aqc_opc_send_msg_to_pf:
5747 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5748 i40e_pf_host_handle_vf_msg(dev,
5749 rte_le_to_cpu_16(info.desc.retval),
5750 rte_le_to_cpu_32(info.desc.cookie_high),
5751 rte_le_to_cpu_32(info.desc.cookie_low),
5755 case i40e_aqc_opc_get_link_status:
5756 ret = i40e_dev_link_update(dev, 0);
5758 i40e_notify_all_vfs_link_status(dev);
5759 _rte_eth_dev_callback_process(dev,
5760 RTE_ETH_EVENT_INTR_LSC, NULL);
5764 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5769 rte_free(info.msg_buf);
5773 * Interrupt handler triggered by NIC for handling
5774 * specific interrupt.
5777 * Pointer to interrupt handle.
5779 * The address of parameter (struct rte_eth_dev *) regsitered before.
5785 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5788 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5789 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5792 /* Disable interrupt */
5793 i40e_pf_disable_irq0(hw);
5795 /* read out interrupt causes */
5796 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5798 /* No interrupt event indicated */
5799 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5800 PMD_DRV_LOG(INFO, "No interrupt event");
5803 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5804 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5805 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5806 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5807 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5808 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5809 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5810 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5811 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5812 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5813 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5814 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5815 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5816 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5817 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5818 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5820 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5821 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5822 i40e_dev_handle_vfr_event(dev);
5824 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5825 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5826 i40e_dev_handle_aq_msg(dev);
5830 /* Enable interrupt */
5831 i40e_pf_enable_irq0(hw);
5832 rte_intr_enable(intr_handle);
5836 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5837 struct i40e_macvlan_filter *filter,
5840 int ele_num, ele_buff_size;
5841 int num, actual_num, i;
5843 int ret = I40E_SUCCESS;
5844 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5845 struct i40e_aqc_add_macvlan_element_data *req_list;
5847 if (filter == NULL || total == 0)
5848 return I40E_ERR_PARAM;
5849 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5850 ele_buff_size = hw->aq.asq_buf_size;
5852 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5853 if (req_list == NULL) {
5854 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5855 return I40E_ERR_NO_MEMORY;
5860 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5861 memset(req_list, 0, ele_buff_size);
5863 for (i = 0; i < actual_num; i++) {
5864 (void)rte_memcpy(req_list[i].mac_addr,
5865 &filter[num + i].macaddr, ETH_ADDR_LEN);
5866 req_list[i].vlan_tag =
5867 rte_cpu_to_le_16(filter[num + i].vlan_id);
5869 switch (filter[num + i].filter_type) {
5870 case RTE_MAC_PERFECT_MATCH:
5871 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5872 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5874 case RTE_MACVLAN_PERFECT_MATCH:
5875 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5877 case RTE_MAC_HASH_MATCH:
5878 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5879 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5881 case RTE_MACVLAN_HASH_MATCH:
5882 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5885 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5886 ret = I40E_ERR_PARAM;
5890 req_list[i].queue_number = 0;
5892 req_list[i].flags = rte_cpu_to_le_16(flags);
5895 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5897 if (ret != I40E_SUCCESS) {
5898 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5902 } while (num < total);
5910 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5911 struct i40e_macvlan_filter *filter,
5914 int ele_num, ele_buff_size;
5915 int num, actual_num, i;
5917 int ret = I40E_SUCCESS;
5918 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5919 struct i40e_aqc_remove_macvlan_element_data *req_list;
5921 if (filter == NULL || total == 0)
5922 return I40E_ERR_PARAM;
5924 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5925 ele_buff_size = hw->aq.asq_buf_size;
5927 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5928 if (req_list == NULL) {
5929 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5930 return I40E_ERR_NO_MEMORY;
5935 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5936 memset(req_list, 0, ele_buff_size);
5938 for (i = 0; i < actual_num; i++) {
5939 (void)rte_memcpy(req_list[i].mac_addr,
5940 &filter[num + i].macaddr, ETH_ADDR_LEN);
5941 req_list[i].vlan_tag =
5942 rte_cpu_to_le_16(filter[num + i].vlan_id);
5944 switch (filter[num + i].filter_type) {
5945 case RTE_MAC_PERFECT_MATCH:
5946 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5947 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5949 case RTE_MACVLAN_PERFECT_MATCH:
5950 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5952 case RTE_MAC_HASH_MATCH:
5953 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5954 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5956 case RTE_MACVLAN_HASH_MATCH:
5957 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5960 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5961 ret = I40E_ERR_PARAM;
5964 req_list[i].flags = rte_cpu_to_le_16(flags);
5967 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5969 if (ret != I40E_SUCCESS) {
5970 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5974 } while (num < total);
5981 /* Find out specific MAC filter */
5982 static struct i40e_mac_filter *
5983 i40e_find_mac_filter(struct i40e_vsi *vsi,
5984 struct ether_addr *macaddr)
5986 struct i40e_mac_filter *f;
5988 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5989 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5997 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6000 uint32_t vid_idx, vid_bit;
6002 if (vlan_id > ETH_VLAN_ID_MAX)
6005 vid_idx = I40E_VFTA_IDX(vlan_id);
6006 vid_bit = I40E_VFTA_BIT(vlan_id);
6008 if (vsi->vfta[vid_idx] & vid_bit)
6015 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6016 uint16_t vlan_id, bool on)
6018 uint32_t vid_idx, vid_bit;
6020 vid_idx = I40E_VFTA_IDX(vlan_id);
6021 vid_bit = I40E_VFTA_BIT(vlan_id);
6024 vsi->vfta[vid_idx] |= vid_bit;
6026 vsi->vfta[vid_idx] &= ~vid_bit;
6030 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6031 uint16_t vlan_id, bool on)
6033 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6034 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6037 if (vlan_id > ETH_VLAN_ID_MAX)
6040 i40e_store_vlan_filter(vsi, vlan_id, on);
6042 if (!vsi->vlan_anti_spoof_on || !vlan_id)
6045 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6048 ret = i40e_aq_add_vlan(hw, vsi->seid,
6049 &vlan_data, 1, NULL);
6050 if (ret != I40E_SUCCESS)
6051 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6053 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6054 &vlan_data, 1, NULL);
6055 if (ret != I40E_SUCCESS)
6057 "Failed to remove vlan filter");
6062 * Find all vlan options for specific mac addr,
6063 * return with actual vlan found.
6066 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6067 struct i40e_macvlan_filter *mv_f,
6068 int num, struct ether_addr *addr)
6074 * Not to use i40e_find_vlan_filter to decrease the loop time,
6075 * although the code looks complex.
6077 if (num < vsi->vlan_num)
6078 return I40E_ERR_PARAM;
6081 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6083 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6084 if (vsi->vfta[j] & (1 << k)) {
6087 "vlan number doesn't match");
6088 return I40E_ERR_PARAM;
6090 (void)rte_memcpy(&mv_f[i].macaddr,
6091 addr, ETH_ADDR_LEN);
6093 j * I40E_UINT32_BIT_SIZE + k;
6099 return I40E_SUCCESS;
6103 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6104 struct i40e_macvlan_filter *mv_f,
6109 struct i40e_mac_filter *f;
6111 if (num < vsi->mac_num)
6112 return I40E_ERR_PARAM;
6114 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6116 PMD_DRV_LOG(ERR, "buffer number not match");
6117 return I40E_ERR_PARAM;
6119 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6121 mv_f[i].vlan_id = vlan;
6122 mv_f[i].filter_type = f->mac_info.filter_type;
6126 return I40E_SUCCESS;
6130 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6133 struct i40e_mac_filter *f;
6134 struct i40e_macvlan_filter *mv_f;
6135 int ret = I40E_SUCCESS;
6137 if (vsi == NULL || vsi->mac_num == 0)
6138 return I40E_ERR_PARAM;
6140 /* Case that no vlan is set */
6141 if (vsi->vlan_num == 0)
6144 num = vsi->mac_num * vsi->vlan_num;
6146 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6148 PMD_DRV_LOG(ERR, "failed to allocate memory");
6149 return I40E_ERR_NO_MEMORY;
6153 if (vsi->vlan_num == 0) {
6154 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6155 (void)rte_memcpy(&mv_f[i].macaddr,
6156 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6157 mv_f[i].filter_type = f->mac_info.filter_type;
6158 mv_f[i].vlan_id = 0;
6162 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6163 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6164 vsi->vlan_num, &f->mac_info.mac_addr);
6165 if (ret != I40E_SUCCESS)
6167 for (j = i; j < i + vsi->vlan_num; j++)
6168 mv_f[j].filter_type = f->mac_info.filter_type;
6173 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6181 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6183 struct i40e_macvlan_filter *mv_f;
6185 int ret = I40E_SUCCESS;
6187 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6188 return I40E_ERR_PARAM;
6190 /* If it's already set, just return */
6191 if (i40e_find_vlan_filter(vsi,vlan))
6192 return I40E_SUCCESS;
6194 mac_num = vsi->mac_num;
6197 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6198 return I40E_ERR_PARAM;
6201 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6204 PMD_DRV_LOG(ERR, "failed to allocate memory");
6205 return I40E_ERR_NO_MEMORY;
6208 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6210 if (ret != I40E_SUCCESS)
6213 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6215 if (ret != I40E_SUCCESS)
6218 i40e_set_vlan_filter(vsi, vlan, 1);
6228 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6230 struct i40e_macvlan_filter *mv_f;
6232 int ret = I40E_SUCCESS;
6235 * Vlan 0 is the generic filter for untagged packets
6236 * and can't be removed.
6238 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6239 return I40E_ERR_PARAM;
6241 /* If can't find it, just return */
6242 if (!i40e_find_vlan_filter(vsi, vlan))
6243 return I40E_ERR_PARAM;
6245 mac_num = vsi->mac_num;
6248 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6249 return I40E_ERR_PARAM;
6252 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6255 PMD_DRV_LOG(ERR, "failed to allocate memory");
6256 return I40E_ERR_NO_MEMORY;
6259 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6261 if (ret != I40E_SUCCESS)
6264 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6266 if (ret != I40E_SUCCESS)
6269 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6270 if (vsi->vlan_num == 1) {
6271 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6272 if (ret != I40E_SUCCESS)
6275 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6276 if (ret != I40E_SUCCESS)
6280 i40e_set_vlan_filter(vsi, vlan, 0);
6290 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6292 struct i40e_mac_filter *f;
6293 struct i40e_macvlan_filter *mv_f;
6294 int i, vlan_num = 0;
6295 int ret = I40E_SUCCESS;
6297 /* If it's add and we've config it, return */
6298 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6300 return I40E_SUCCESS;
6301 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6302 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6305 * If vlan_num is 0, that's the first time to add mac,
6306 * set mask for vlan_id 0.
6308 if (vsi->vlan_num == 0) {
6309 i40e_set_vlan_filter(vsi, 0, 1);
6312 vlan_num = vsi->vlan_num;
6313 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6314 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6317 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6319 PMD_DRV_LOG(ERR, "failed to allocate memory");
6320 return I40E_ERR_NO_MEMORY;
6323 for (i = 0; i < vlan_num; i++) {
6324 mv_f[i].filter_type = mac_filter->filter_type;
6325 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6329 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6330 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6331 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6332 &mac_filter->mac_addr);
6333 if (ret != I40E_SUCCESS)
6337 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6338 if (ret != I40E_SUCCESS)
6341 /* Add the mac addr into mac list */
6342 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6344 PMD_DRV_LOG(ERR, "failed to allocate memory");
6345 ret = I40E_ERR_NO_MEMORY;
6348 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6350 f->mac_info.filter_type = mac_filter->filter_type;
6351 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6362 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6364 struct i40e_mac_filter *f;
6365 struct i40e_macvlan_filter *mv_f;
6367 enum rte_mac_filter_type filter_type;
6368 int ret = I40E_SUCCESS;
6370 /* Can't find it, return an error */
6371 f = i40e_find_mac_filter(vsi, addr);
6373 return I40E_ERR_PARAM;
6375 vlan_num = vsi->vlan_num;
6376 filter_type = f->mac_info.filter_type;
6377 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6378 filter_type == RTE_MACVLAN_HASH_MATCH) {
6379 if (vlan_num == 0) {
6380 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6381 return I40E_ERR_PARAM;
6383 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6384 filter_type == RTE_MAC_HASH_MATCH)
6387 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6389 PMD_DRV_LOG(ERR, "failed to allocate memory");
6390 return I40E_ERR_NO_MEMORY;
6393 for (i = 0; i < vlan_num; i++) {
6394 mv_f[i].filter_type = filter_type;
6395 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6398 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6399 filter_type == RTE_MACVLAN_HASH_MATCH) {
6400 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6401 if (ret != I40E_SUCCESS)
6405 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6406 if (ret != I40E_SUCCESS)
6409 /* Remove the mac addr into mac list */
6410 TAILQ_REMOVE(&vsi->mac_list, f, next);
6420 /* Configure hash enable flags for RSS */
6422 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6429 if (flags & ETH_RSS_FRAG_IPV4)
6430 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6431 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6432 if (type == I40E_MAC_X722) {
6433 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6434 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6436 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6438 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6439 if (type == I40E_MAC_X722) {
6440 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6441 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6442 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6444 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6446 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6447 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6448 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6449 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6450 if (flags & ETH_RSS_FRAG_IPV6)
6451 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6452 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6453 if (type == I40E_MAC_X722) {
6454 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6455 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6457 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6459 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6460 if (type == I40E_MAC_X722) {
6461 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6462 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6463 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6465 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6467 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6468 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6469 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6470 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6471 if (flags & ETH_RSS_L2_PAYLOAD)
6472 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6477 /* Parse the hash enable flags */
6479 i40e_parse_hena(uint64_t flags)
6481 uint64_t rss_hf = 0;
6485 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6486 rss_hf |= ETH_RSS_FRAG_IPV4;
6487 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6488 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6489 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6490 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6491 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6492 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6493 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6494 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6495 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6496 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6497 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6498 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6499 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6500 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6501 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6502 rss_hf |= ETH_RSS_FRAG_IPV6;
6503 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6504 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6505 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6506 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6507 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6508 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6509 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6510 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6511 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6512 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6513 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6514 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6515 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6516 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6517 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6518 rss_hf |= ETH_RSS_L2_PAYLOAD;
6525 i40e_pf_disable_rss(struct i40e_pf *pf)
6527 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6530 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6531 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6532 if (hw->mac.type == I40E_MAC_X722)
6533 hena &= ~I40E_RSS_HENA_ALL_X722;
6535 hena &= ~I40E_RSS_HENA_ALL;
6536 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6537 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6538 I40E_WRITE_FLUSH(hw);
6542 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6544 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6545 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6548 if (!key || key_len == 0) {
6549 PMD_DRV_LOG(DEBUG, "No key to be configured");
6551 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6553 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6557 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6558 struct i40e_aqc_get_set_rss_key_data *key_dw =
6559 (struct i40e_aqc_get_set_rss_key_data *)key;
6561 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6563 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6565 uint32_t *hash_key = (uint32_t *)key;
6568 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6569 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6570 I40E_WRITE_FLUSH(hw);
6577 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6579 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6580 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6583 if (!key || !key_len)
6586 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6587 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6588 (struct i40e_aqc_get_set_rss_key_data *)key);
6590 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6594 uint32_t *key_dw = (uint32_t *)key;
6597 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6598 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6600 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6606 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6608 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6613 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6614 rss_conf->rss_key_len);
6618 rss_hf = rss_conf->rss_hf;
6619 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6620 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6621 if (hw->mac.type == I40E_MAC_X722)
6622 hena &= ~I40E_RSS_HENA_ALL_X722;
6624 hena &= ~I40E_RSS_HENA_ALL;
6625 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6626 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6627 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6628 I40E_WRITE_FLUSH(hw);
6634 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6635 struct rte_eth_rss_conf *rss_conf)
6637 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6638 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6639 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6642 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6643 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6644 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6645 ? I40E_RSS_HENA_ALL_X722
6646 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6647 if (rss_hf != 0) /* Enable RSS */
6649 return 0; /* Nothing to do */
6652 if (rss_hf == 0) /* Disable RSS */
6655 return i40e_hw_rss_hash_set(pf, rss_conf);
6659 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6660 struct rte_eth_rss_conf *rss_conf)
6662 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6663 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6666 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6667 &rss_conf->rss_key_len);
6669 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6670 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6671 rss_conf->rss_hf = i40e_parse_hena(hena);
6677 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6679 switch (filter_type) {
6680 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6681 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6683 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6684 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6686 case RTE_TUNNEL_FILTER_IMAC_TENID:
6687 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6689 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6690 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6692 case ETH_TUNNEL_FILTER_IMAC:
6693 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6695 case ETH_TUNNEL_FILTER_OIP:
6696 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6698 case ETH_TUNNEL_FILTER_IIP:
6699 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6702 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6709 /* Convert tunnel filter structure */
6711 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6713 struct i40e_tunnel_filter *tunnel_filter)
6715 ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6716 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6717 ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6718 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6719 tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6720 if ((rte_le_to_cpu_16(cld_filter->flags) &
6721 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6722 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6723 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6725 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6726 tunnel_filter->input.flags = cld_filter->flags;
6727 tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6728 tunnel_filter->queue = cld_filter->queue_number;
6733 /* Check if there exists the tunnel filter */
6734 struct i40e_tunnel_filter *
6735 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6736 const struct i40e_tunnel_filter_input *input)
6740 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6744 return tunnel_rule->hash_map[ret];
6747 /* Add a tunnel filter into the SW list */
6749 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6750 struct i40e_tunnel_filter *tunnel_filter)
6752 struct i40e_tunnel_rule *rule = &pf->tunnel;
6755 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6758 "Failed to insert tunnel filter to hash table %d!",
6762 rule->hash_map[ret] = tunnel_filter;
6764 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6769 /* Delete a tunnel filter from the SW list */
6771 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6772 struct i40e_tunnel_filter_input *input)
6774 struct i40e_tunnel_rule *rule = &pf->tunnel;
6775 struct i40e_tunnel_filter *tunnel_filter;
6778 ret = rte_hash_del_key(rule->hash_table, input);
6781 "Failed to delete tunnel filter to hash table %d!",
6785 tunnel_filter = rule->hash_map[ret];
6786 rule->hash_map[ret] = NULL;
6788 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6789 rte_free(tunnel_filter);
6795 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6796 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6801 uint8_t i, tun_type = 0;
6802 /* internal varialbe to convert ipv6 byte order */
6803 uint32_t convert_ipv6[4];
6805 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6806 struct i40e_vsi *vsi = pf->main_vsi;
6807 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6808 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6809 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6810 struct i40e_tunnel_filter *tunnel, *node;
6811 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6813 cld_filter = rte_zmalloc("tunnel_filter",
6814 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6817 if (NULL == cld_filter) {
6818 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6821 pfilter = cld_filter;
6823 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6824 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6826 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6827 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6828 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6829 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6830 rte_memcpy(&pfilter->ipaddr.v4.data,
6831 &rte_cpu_to_le_32(ipv4_addr),
6832 sizeof(pfilter->ipaddr.v4.data));
6834 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6835 for (i = 0; i < 4; i++) {
6837 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6839 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6840 sizeof(pfilter->ipaddr.v6.data));
6843 /* check tunneled type */
6844 switch (tunnel_filter->tunnel_type) {
6845 case RTE_TUNNEL_TYPE_VXLAN:
6846 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6848 case RTE_TUNNEL_TYPE_NVGRE:
6849 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6851 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6852 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6855 /* Other tunnel types is not supported. */
6856 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6857 rte_free(cld_filter);
6861 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6864 rte_free(cld_filter);
6868 pfilter->flags |= rte_cpu_to_le_16(
6869 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6870 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6871 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6872 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6874 /* Check if there is the filter in SW list */
6875 memset(&check_filter, 0, sizeof(check_filter));
6876 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6877 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6879 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6883 if (!add && !node) {
6884 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6889 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6891 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6894 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6895 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6896 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6898 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6901 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6904 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6907 rte_free(cld_filter);
6912 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6916 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6917 if (pf->vxlan_ports[i] == port)
6925 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6929 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6931 idx = i40e_get_vxlan_port_idx(pf, port);
6933 /* Check if port already exists */
6935 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6939 /* Now check if there is space to add the new port */
6940 idx = i40e_get_vxlan_port_idx(pf, 0);
6943 "Maximum number of UDP ports reached, not adding port %d",
6948 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6951 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6955 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6958 /* New port: add it and mark its index in the bitmap */
6959 pf->vxlan_ports[idx] = port;
6960 pf->vxlan_bitmap |= (1 << idx);
6962 if (!(pf->flags & I40E_FLAG_VXLAN))
6963 pf->flags |= I40E_FLAG_VXLAN;
6969 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6972 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6974 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6975 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6979 idx = i40e_get_vxlan_port_idx(pf, port);
6982 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6986 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6987 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6991 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6994 pf->vxlan_ports[idx] = 0;
6995 pf->vxlan_bitmap &= ~(1 << idx);
6997 if (!pf->vxlan_bitmap)
6998 pf->flags &= ~I40E_FLAG_VXLAN;
7003 /* Add UDP tunneling port */
7005 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7006 struct rte_eth_udp_tunnel *udp_tunnel)
7009 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7011 if (udp_tunnel == NULL)
7014 switch (udp_tunnel->prot_type) {
7015 case RTE_TUNNEL_TYPE_VXLAN:
7016 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7019 case RTE_TUNNEL_TYPE_GENEVE:
7020 case RTE_TUNNEL_TYPE_TEREDO:
7021 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7026 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7034 /* Remove UDP tunneling port */
7036 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7037 struct rte_eth_udp_tunnel *udp_tunnel)
7040 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7042 if (udp_tunnel == NULL)
7045 switch (udp_tunnel->prot_type) {
7046 case RTE_TUNNEL_TYPE_VXLAN:
7047 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7049 case RTE_TUNNEL_TYPE_GENEVE:
7050 case RTE_TUNNEL_TYPE_TEREDO:
7051 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7055 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7063 /* Calculate the maximum number of contiguous PF queues that are configured */
7065 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7067 struct rte_eth_dev_data *data = pf->dev_data;
7069 struct i40e_rx_queue *rxq;
7072 for (i = 0; i < pf->lan_nb_qps; i++) {
7073 rxq = data->rx_queues[i];
7074 if (rxq && rxq->q_set)
7085 i40e_pf_config_rss(struct i40e_pf *pf)
7087 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7088 struct rte_eth_rss_conf rss_conf;
7089 uint32_t i, lut = 0;
7093 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7094 * It's necessary to calulate the actual PF queues that are configured.
7096 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7097 num = i40e_pf_calc_configured_queues_num(pf);
7099 num = pf->dev_data->nb_rx_queues;
7101 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7102 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7106 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7110 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7113 lut = (lut << 8) | (j & ((0x1 <<
7114 hw->func_caps.rss_table_entry_width) - 1));
7116 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7119 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7120 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7121 i40e_pf_disable_rss(pf);
7124 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7125 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7126 /* Random default keys */
7127 static uint32_t rss_key_default[] = {0x6b793944,
7128 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7129 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7130 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7132 rss_conf.rss_key = (uint8_t *)rss_key_default;
7133 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7137 return i40e_hw_rss_hash_set(pf, &rss_conf);
7141 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7142 struct rte_eth_tunnel_filter_conf *filter)
7144 if (pf == NULL || filter == NULL) {
7145 PMD_DRV_LOG(ERR, "Invalid parameter");
7149 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7150 PMD_DRV_LOG(ERR, "Invalid queue ID");
7154 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7155 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7159 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7160 (is_zero_ether_addr(&filter->outer_mac))) {
7161 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7165 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7166 (is_zero_ether_addr(&filter->inner_mac))) {
7167 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7174 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7175 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7177 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7182 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7183 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7186 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7187 } else if (len == 4) {
7188 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7190 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7195 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7202 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7203 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7209 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7216 switch (cfg->cfg_type) {
7217 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7218 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7221 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7229 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7230 enum rte_filter_op filter_op,
7233 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7234 int ret = I40E_ERR_PARAM;
7236 switch (filter_op) {
7237 case RTE_ETH_FILTER_SET:
7238 ret = i40e_dev_global_config_set(hw,
7239 (struct rte_eth_global_cfg *)arg);
7242 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7250 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7251 enum rte_filter_op filter_op,
7254 struct rte_eth_tunnel_filter_conf *filter;
7255 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7256 int ret = I40E_SUCCESS;
7258 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7260 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7261 return I40E_ERR_PARAM;
7263 switch (filter_op) {
7264 case RTE_ETH_FILTER_NOP:
7265 if (!(pf->flags & I40E_FLAG_VXLAN))
7266 ret = I40E_NOT_SUPPORTED;
7268 case RTE_ETH_FILTER_ADD:
7269 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7271 case RTE_ETH_FILTER_DELETE:
7272 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7275 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7276 ret = I40E_ERR_PARAM;
7284 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7287 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7290 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7291 ret = i40e_pf_config_rss(pf);
7293 i40e_pf_disable_rss(pf);
7298 /* Get the symmetric hash enable configurations per port */
7300 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7302 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7304 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7307 /* Set the symmetric hash enable configurations per port */
7309 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7311 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7314 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7316 "Symmetric hash has already been enabled");
7319 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7321 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7323 "Symmetric hash has already been disabled");
7326 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7328 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7329 I40E_WRITE_FLUSH(hw);
7333 * Get global configurations of hash function type and symmetric hash enable
7334 * per flow type (pctype). Note that global configuration means it affects all
7335 * the ports on the same NIC.
7338 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7339 struct rte_eth_hash_global_conf *g_cfg)
7341 uint32_t reg, mask = I40E_FLOW_TYPES;
7343 enum i40e_filter_pctype pctype;
7345 memset(g_cfg, 0, sizeof(*g_cfg));
7346 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7347 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7348 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7350 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7351 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7352 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7354 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7355 if (!(mask & (1UL << i)))
7357 mask &= ~(1UL << i);
7358 /* Bit set indicats the coresponding flow type is supported */
7359 g_cfg->valid_bit_mask[0] |= (1UL << i);
7360 /* if flowtype is invalid, continue */
7361 if (!I40E_VALID_FLOW(i))
7363 pctype = i40e_flowtype_to_pctype(i);
7364 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7365 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7366 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7373 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7376 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7378 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7379 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7380 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7381 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7387 * As i40e supports less than 32 flow types, only first 32 bits need to
7390 mask0 = g_cfg->valid_bit_mask[0];
7391 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7393 /* Check if any unsupported flow type configured */
7394 if ((mask0 | i40e_mask) ^ i40e_mask)
7397 if (g_cfg->valid_bit_mask[i])
7405 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7411 * Set global configurations of hash function type and symmetric hash enable
7412 * per flow type (pctype). Note any modifying global configuration will affect
7413 * all the ports on the same NIC.
7416 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7417 struct rte_eth_hash_global_conf *g_cfg)
7422 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7423 enum i40e_filter_pctype pctype;
7425 /* Check the input parameters */
7426 ret = i40e_hash_global_config_check(g_cfg);
7430 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7431 if (!(mask0 & (1UL << i)))
7433 mask0 &= ~(1UL << i);
7434 /* if flowtype is invalid, continue */
7435 if (!I40E_VALID_FLOW(i))
7437 pctype = i40e_flowtype_to_pctype(i);
7438 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7439 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7440 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7443 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7444 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7446 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7448 "Hash function already set to Toeplitz");
7451 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7452 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7454 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7456 "Hash function already set to Simple XOR");
7459 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7461 /* Use the default, and keep it as it is */
7464 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7467 I40E_WRITE_FLUSH(hw);
7473 * Valid input sets for hash and flow director filters per PCTYPE
7476 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7477 enum rte_filter_type filter)
7481 static const uint64_t valid_hash_inset_table[] = {
7482 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7483 I40E_INSET_DMAC | I40E_INSET_SMAC |
7484 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7485 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7486 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7487 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7488 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7489 I40E_INSET_FLEX_PAYLOAD,
7490 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7491 I40E_INSET_DMAC | I40E_INSET_SMAC |
7492 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7493 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7494 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7495 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7496 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7497 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7498 I40E_INSET_FLEX_PAYLOAD,
7499 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7500 I40E_INSET_DMAC | I40E_INSET_SMAC |
7501 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7502 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7503 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7504 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7505 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7506 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7507 I40E_INSET_FLEX_PAYLOAD,
7508 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7509 I40E_INSET_DMAC | I40E_INSET_SMAC |
7510 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7511 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7512 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7513 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7514 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7515 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7516 I40E_INSET_FLEX_PAYLOAD,
7517 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7518 I40E_INSET_DMAC | I40E_INSET_SMAC |
7519 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7520 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7521 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7522 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7523 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7524 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7525 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7526 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7527 I40E_INSET_DMAC | I40E_INSET_SMAC |
7528 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7529 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7530 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7531 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7532 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7533 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7534 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7535 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7536 I40E_INSET_DMAC | I40E_INSET_SMAC |
7537 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7538 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7539 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7540 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7541 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7542 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7543 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7544 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7545 I40E_INSET_DMAC | I40E_INSET_SMAC |
7546 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7547 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7548 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7549 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7550 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7551 I40E_INSET_FLEX_PAYLOAD,
7552 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7553 I40E_INSET_DMAC | I40E_INSET_SMAC |
7554 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7555 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7556 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7557 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7558 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7559 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7560 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7561 I40E_INSET_DMAC | I40E_INSET_SMAC |
7562 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7563 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7564 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7565 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7566 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7567 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7568 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7569 I40E_INSET_DMAC | I40E_INSET_SMAC |
7570 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7571 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7572 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7573 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7574 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7575 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7576 I40E_INSET_FLEX_PAYLOAD,
7577 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7578 I40E_INSET_DMAC | I40E_INSET_SMAC |
7579 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7580 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7581 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7582 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7583 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7584 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7585 I40E_INSET_FLEX_PAYLOAD,
7586 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7587 I40E_INSET_DMAC | I40E_INSET_SMAC |
7588 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7589 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7590 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7591 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7592 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7593 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7594 I40E_INSET_FLEX_PAYLOAD,
7595 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7596 I40E_INSET_DMAC | I40E_INSET_SMAC |
7597 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7598 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7599 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7600 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7601 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7602 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7603 I40E_INSET_FLEX_PAYLOAD,
7604 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7605 I40E_INSET_DMAC | I40E_INSET_SMAC |
7606 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7607 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7608 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7609 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7610 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7611 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7612 I40E_INSET_FLEX_PAYLOAD,
7613 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7614 I40E_INSET_DMAC | I40E_INSET_SMAC |
7615 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7616 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7617 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7618 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7619 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7620 I40E_INSET_FLEX_PAYLOAD,
7621 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7622 I40E_INSET_DMAC | I40E_INSET_SMAC |
7623 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7624 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7625 I40E_INSET_FLEX_PAYLOAD,
7629 * Flow director supports only fields defined in
7630 * union rte_eth_fdir_flow.
7632 static const uint64_t valid_fdir_inset_table[] = {
7633 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7634 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7635 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7636 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7637 I40E_INSET_IPV4_TTL,
7638 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7639 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7640 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7641 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7642 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7643 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7644 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7645 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7646 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7647 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7648 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7649 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7650 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7651 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7652 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7653 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7654 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7655 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7656 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7657 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7658 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7659 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7660 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7661 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7662 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7663 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7664 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7665 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7666 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7667 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7669 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7670 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7671 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7672 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7673 I40E_INSET_IPV4_TTL,
7674 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7675 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7676 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7677 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7678 I40E_INSET_IPV6_HOP_LIMIT,
7679 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7680 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7681 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7682 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7683 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7684 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7685 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7686 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7687 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7688 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7689 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7690 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7691 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7692 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7693 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7694 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7695 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7696 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7697 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7698 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7699 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7700 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7701 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7702 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7703 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7704 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7705 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7706 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7707 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7708 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7710 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7711 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7712 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7713 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7714 I40E_INSET_IPV6_HOP_LIMIT,
7715 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7716 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7717 I40E_INSET_LAST_ETHER_TYPE,
7720 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7722 if (filter == RTE_ETH_FILTER_HASH)
7723 valid = valid_hash_inset_table[pctype];
7725 valid = valid_fdir_inset_table[pctype];
7731 * Validate if the input set is allowed for a specific PCTYPE
7734 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7735 enum rte_filter_type filter, uint64_t inset)
7739 valid = i40e_get_valid_input_set(pctype, filter);
7740 if (inset & (~valid))
7746 /* default input set fields combination per pctype */
7748 i40e_get_default_input_set(uint16_t pctype)
7750 static const uint64_t default_inset_table[] = {
7751 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7752 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7753 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7754 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7755 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7756 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7757 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7758 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7759 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7760 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7761 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7762 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7763 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7764 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7765 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7766 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7767 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7768 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7769 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7770 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7772 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7773 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7774 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7775 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7776 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7777 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7778 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7779 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7780 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7781 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7782 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7783 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7784 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7785 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7786 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7787 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7788 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7789 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7790 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7791 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7792 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7793 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7795 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7796 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7797 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7798 I40E_INSET_LAST_ETHER_TYPE,
7801 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7804 return default_inset_table[pctype];
7808 * Parse the input set from index to logical bit masks
7811 i40e_parse_input_set(uint64_t *inset,
7812 enum i40e_filter_pctype pctype,
7813 enum rte_eth_input_set_field *field,
7819 static const struct {
7820 enum rte_eth_input_set_field field;
7822 } inset_convert_table[] = {
7823 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7824 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7825 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7826 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7827 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7828 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7829 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7830 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7831 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7832 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7833 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7834 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7835 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7836 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7837 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7838 I40E_INSET_IPV6_NEXT_HDR},
7839 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7840 I40E_INSET_IPV6_HOP_LIMIT},
7841 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7842 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7843 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7844 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7845 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7846 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7847 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7848 I40E_INSET_SCTP_VT},
7849 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7850 I40E_INSET_TUNNEL_DMAC},
7851 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7852 I40E_INSET_VLAN_TUNNEL},
7853 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7854 I40E_INSET_TUNNEL_ID},
7855 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7856 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7857 I40E_INSET_FLEX_PAYLOAD_W1},
7858 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7859 I40E_INSET_FLEX_PAYLOAD_W2},
7860 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7861 I40E_INSET_FLEX_PAYLOAD_W3},
7862 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7863 I40E_INSET_FLEX_PAYLOAD_W4},
7864 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7865 I40E_INSET_FLEX_PAYLOAD_W5},
7866 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7867 I40E_INSET_FLEX_PAYLOAD_W6},
7868 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7869 I40E_INSET_FLEX_PAYLOAD_W7},
7870 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7871 I40E_INSET_FLEX_PAYLOAD_W8},
7874 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7877 /* Only one item allowed for default or all */
7879 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7880 *inset = i40e_get_default_input_set(pctype);
7882 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7883 *inset = I40E_INSET_NONE;
7888 for (i = 0, *inset = 0; i < size; i++) {
7889 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7890 if (field[i] == inset_convert_table[j].field) {
7891 *inset |= inset_convert_table[j].inset;
7896 /* It contains unsupported input set, return immediately */
7897 if (j == RTE_DIM(inset_convert_table))
7905 * Translate the input set from bit masks to register aware bit masks
7909 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7919 static const struct inset_map inset_map_common[] = {
7920 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7921 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7922 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7923 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7924 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7925 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7926 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7927 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7928 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7929 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7930 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7931 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7932 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7933 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7934 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7935 {I40E_INSET_TUNNEL_DMAC,
7936 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7937 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7938 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7939 {I40E_INSET_TUNNEL_SRC_PORT,
7940 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7941 {I40E_INSET_TUNNEL_DST_PORT,
7942 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7943 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7944 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7945 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7946 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7947 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7948 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7949 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7950 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7951 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7954 /* some different registers map in x722*/
7955 static const struct inset_map inset_map_diff_x722[] = {
7956 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7957 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7958 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7959 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7962 static const struct inset_map inset_map_diff_not_x722[] = {
7963 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7964 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7965 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7966 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7972 /* Translate input set to register aware inset */
7973 if (type == I40E_MAC_X722) {
7974 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7975 if (input & inset_map_diff_x722[i].inset)
7976 val |= inset_map_diff_x722[i].inset_reg;
7979 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7980 if (input & inset_map_diff_not_x722[i].inset)
7981 val |= inset_map_diff_not_x722[i].inset_reg;
7985 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7986 if (input & inset_map_common[i].inset)
7987 val |= inset_map_common[i].inset_reg;
7994 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7997 uint64_t inset_need_mask = inset;
7999 static const struct {
8002 } inset_mask_map[] = {
8003 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8004 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8005 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8006 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8007 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8008 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8009 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8010 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8013 if (!inset || !mask || !nb_elem)
8016 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8017 /* Clear the inset bit, if no MASK is required,
8018 * for example proto + ttl
8020 if ((inset & inset_mask_map[i].inset) ==
8021 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8022 inset_need_mask &= ~inset_mask_map[i].inset;
8023 if (!inset_need_mask)
8026 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8027 if ((inset_need_mask & inset_mask_map[i].inset) ==
8028 inset_mask_map[i].inset) {
8029 if (idx >= nb_elem) {
8030 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8033 mask[idx] = inset_mask_map[i].mask;
8042 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8044 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8046 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8048 i40e_write_rx_ctl(hw, addr, val);
8049 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8050 (uint32_t)i40e_read_rx_ctl(hw, addr));
8054 i40e_filter_input_set_init(struct i40e_pf *pf)
8056 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8057 enum i40e_filter_pctype pctype;
8058 uint64_t input_set, inset_reg;
8059 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8062 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8063 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8064 if (hw->mac.type == I40E_MAC_X722) {
8065 if (!I40E_VALID_PCTYPE_X722(pctype))
8068 if (!I40E_VALID_PCTYPE(pctype))
8072 input_set = i40e_get_default_input_set(pctype);
8074 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8075 I40E_INSET_MASK_NUM_REG);
8078 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8081 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8082 (uint32_t)(inset_reg & UINT32_MAX));
8083 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8084 (uint32_t)((inset_reg >>
8085 I40E_32_BIT_WIDTH) & UINT32_MAX));
8086 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8087 (uint32_t)(inset_reg & UINT32_MAX));
8088 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8089 (uint32_t)((inset_reg >>
8090 I40E_32_BIT_WIDTH) & UINT32_MAX));
8092 for (i = 0; i < num; i++) {
8093 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8095 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8098 /*clear unused mask registers of the pctype */
8099 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8100 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8102 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8105 I40E_WRITE_FLUSH(hw);
8107 /* store the default input set */
8108 pf->hash_input_set[pctype] = input_set;
8109 pf->fdir.input_set[pctype] = input_set;
8114 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8115 struct rte_eth_input_set_conf *conf)
8117 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8118 enum i40e_filter_pctype pctype;
8119 uint64_t input_set, inset_reg = 0;
8120 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8124 PMD_DRV_LOG(ERR, "Invalid pointer");
8127 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8128 conf->op != RTE_ETH_INPUT_SET_ADD) {
8129 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8133 if (!I40E_VALID_FLOW(conf->flow_type)) {
8134 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8138 if (hw->mac.type == I40E_MAC_X722) {
8139 /* get translated pctype value in fd pctype register */
8140 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8141 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8144 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8146 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8149 PMD_DRV_LOG(ERR, "Failed to parse input set");
8152 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8154 PMD_DRV_LOG(ERR, "Invalid input set");
8157 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8158 /* get inset value in register */
8159 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8160 inset_reg <<= I40E_32_BIT_WIDTH;
8161 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8162 input_set |= pf->hash_input_set[pctype];
8164 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8165 I40E_INSET_MASK_NUM_REG);
8169 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8171 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8172 (uint32_t)(inset_reg & UINT32_MAX));
8173 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8174 (uint32_t)((inset_reg >>
8175 I40E_32_BIT_WIDTH) & UINT32_MAX));
8177 for (i = 0; i < num; i++)
8178 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8180 /*clear unused mask registers of the pctype */
8181 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8182 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8184 I40E_WRITE_FLUSH(hw);
8186 pf->hash_input_set[pctype] = input_set;
8191 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8192 struct rte_eth_input_set_conf *conf)
8194 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8195 enum i40e_filter_pctype pctype;
8196 uint64_t input_set, inset_reg = 0;
8197 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8201 PMD_DRV_LOG(ERR, "Invalid pointer");
8204 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8205 conf->op != RTE_ETH_INPUT_SET_ADD) {
8206 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8210 if (!I40E_VALID_FLOW(conf->flow_type)) {
8211 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8215 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8217 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8220 PMD_DRV_LOG(ERR, "Failed to parse input set");
8223 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8225 PMD_DRV_LOG(ERR, "Invalid input set");
8229 /* get inset value in register */
8230 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8231 inset_reg <<= I40E_32_BIT_WIDTH;
8232 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8234 /* Can not change the inset reg for flex payload for fdir,
8235 * it is done by writing I40E_PRTQF_FD_FLXINSET
8236 * in i40e_set_flex_mask_on_pctype.
8238 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8239 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8241 input_set |= pf->fdir.input_set[pctype];
8242 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8243 I40E_INSET_MASK_NUM_REG);
8247 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8249 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8250 (uint32_t)(inset_reg & UINT32_MAX));
8251 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8252 (uint32_t)((inset_reg >>
8253 I40E_32_BIT_WIDTH) & UINT32_MAX));
8255 for (i = 0; i < num; i++)
8256 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8258 /*clear unused mask registers of the pctype */
8259 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8260 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8262 I40E_WRITE_FLUSH(hw);
8264 pf->fdir.input_set[pctype] = input_set;
8269 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8274 PMD_DRV_LOG(ERR, "Invalid pointer");
8278 switch (info->info_type) {
8279 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8280 i40e_get_symmetric_hash_enable_per_port(hw,
8281 &(info->info.enable));
8283 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8284 ret = i40e_get_hash_filter_global_config(hw,
8285 &(info->info.global_conf));
8288 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8298 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8303 PMD_DRV_LOG(ERR, "Invalid pointer");
8307 switch (info->info_type) {
8308 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8309 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8311 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8312 ret = i40e_set_hash_filter_global_config(hw,
8313 &(info->info.global_conf));
8315 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8316 ret = i40e_hash_filter_inset_select(hw,
8317 &(info->info.input_set_conf));
8321 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8330 /* Operations for hash function */
8332 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8333 enum rte_filter_op filter_op,
8336 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8339 switch (filter_op) {
8340 case RTE_ETH_FILTER_NOP:
8342 case RTE_ETH_FILTER_GET:
8343 ret = i40e_hash_filter_get(hw,
8344 (struct rte_eth_hash_filter_info *)arg);
8346 case RTE_ETH_FILTER_SET:
8347 ret = i40e_hash_filter_set(hw,
8348 (struct rte_eth_hash_filter_info *)arg);
8351 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8360 /* Convert ethertype filter structure */
8362 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8363 struct i40e_ethertype_filter *filter)
8365 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8366 filter->input.ether_type = input->ether_type;
8367 filter->flags = input->flags;
8368 filter->queue = input->queue;
8373 /* Check if there exists the ehtertype filter */
8374 struct i40e_ethertype_filter *
8375 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8376 const struct i40e_ethertype_filter_input *input)
8380 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8384 return ethertype_rule->hash_map[ret];
8387 /* Add ethertype filter in SW list */
8389 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8390 struct i40e_ethertype_filter *filter)
8392 struct i40e_ethertype_rule *rule = &pf->ethertype;
8395 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8398 "Failed to insert ethertype filter"
8399 " to hash table %d!",
8403 rule->hash_map[ret] = filter;
8405 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8410 /* Delete ethertype filter in SW list */
8412 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8413 struct i40e_ethertype_filter_input *input)
8415 struct i40e_ethertype_rule *rule = &pf->ethertype;
8416 struct i40e_ethertype_filter *filter;
8419 ret = rte_hash_del_key(rule->hash_table, input);
8422 "Failed to delete ethertype filter"
8423 " to hash table %d!",
8427 filter = rule->hash_map[ret];
8428 rule->hash_map[ret] = NULL;
8430 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8437 * Configure ethertype filter, which can director packet by filtering
8438 * with mac address and ether_type or only ether_type
8441 i40e_ethertype_filter_set(struct i40e_pf *pf,
8442 struct rte_eth_ethertype_filter *filter,
8445 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8446 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8447 struct i40e_ethertype_filter *ethertype_filter, *node;
8448 struct i40e_ethertype_filter check_filter;
8449 struct i40e_control_filter_stats stats;
8453 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8454 PMD_DRV_LOG(ERR, "Invalid queue ID");
8457 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8458 filter->ether_type == ETHER_TYPE_IPv6) {
8460 "unsupported ether_type(0x%04x) in control packet filter.",
8461 filter->ether_type);
8464 if (filter->ether_type == ETHER_TYPE_VLAN)
8465 PMD_DRV_LOG(WARNING,
8466 "filter vlan ether_type in first tag is not supported.");
8468 /* Check if there is the filter in SW list */
8469 memset(&check_filter, 0, sizeof(check_filter));
8470 i40e_ethertype_filter_convert(filter, &check_filter);
8471 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8472 &check_filter.input);
8474 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8478 if (!add && !node) {
8479 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8483 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8484 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8485 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8486 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8487 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8489 memset(&stats, 0, sizeof(stats));
8490 ret = i40e_aq_add_rem_control_packet_filter(hw,
8491 filter->mac_addr.addr_bytes,
8492 filter->ether_type, flags,
8494 filter->queue, add, &stats, NULL);
8497 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8498 ret, stats.mac_etype_used, stats.etype_used,
8499 stats.mac_etype_free, stats.etype_free);
8503 /* Add or delete a filter in SW list */
8505 ethertype_filter = rte_zmalloc("ethertype_filter",
8506 sizeof(*ethertype_filter), 0);
8507 rte_memcpy(ethertype_filter, &check_filter,
8508 sizeof(check_filter));
8509 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8511 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8518 * Handle operations for ethertype filter.
8521 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8522 enum rte_filter_op filter_op,
8525 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8528 if (filter_op == RTE_ETH_FILTER_NOP)
8532 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8537 switch (filter_op) {
8538 case RTE_ETH_FILTER_ADD:
8539 ret = i40e_ethertype_filter_set(pf,
8540 (struct rte_eth_ethertype_filter *)arg,
8543 case RTE_ETH_FILTER_DELETE:
8544 ret = i40e_ethertype_filter_set(pf,
8545 (struct rte_eth_ethertype_filter *)arg,
8549 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8557 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8558 enum rte_filter_type filter_type,
8559 enum rte_filter_op filter_op,
8567 switch (filter_type) {
8568 case RTE_ETH_FILTER_NONE:
8569 /* For global configuration */
8570 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8572 case RTE_ETH_FILTER_HASH:
8573 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8575 case RTE_ETH_FILTER_MACVLAN:
8576 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8578 case RTE_ETH_FILTER_ETHERTYPE:
8579 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8581 case RTE_ETH_FILTER_TUNNEL:
8582 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8584 case RTE_ETH_FILTER_FDIR:
8585 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8587 case RTE_ETH_FILTER_GENERIC:
8588 if (filter_op != RTE_ETH_FILTER_GET)
8590 *(const void **)arg = &i40e_flow_ops;
8593 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8603 * Check and enable Extended Tag.
8604 * Enabling Extended Tag is important for 40G performance.
8607 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8609 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8613 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8616 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8620 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8621 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8626 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8629 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8633 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8634 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8637 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8638 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8641 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8648 * As some registers wouldn't be reset unless a global hardware reset,
8649 * hardware initialization is needed to put those registers into an
8650 * expected initial state.
8653 i40e_hw_init(struct rte_eth_dev *dev)
8655 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8657 i40e_enable_extended_tag(dev);
8659 /* clear the PF Queue Filter control register */
8660 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8662 /* Disable symmetric hash per port */
8663 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8666 enum i40e_filter_pctype
8667 i40e_flowtype_to_pctype(uint16_t flow_type)
8669 static const enum i40e_filter_pctype pctype_table[] = {
8670 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8671 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8672 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8673 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8674 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8675 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8676 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8677 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8678 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8679 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8680 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8681 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8682 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8683 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8684 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8685 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8686 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8687 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8688 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8691 return pctype_table[flow_type];
8695 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8697 static const uint16_t flowtype_table[] = {
8698 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8699 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8700 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8701 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8702 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8703 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8704 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8705 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8706 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8707 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8708 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8709 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8710 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8711 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8712 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8713 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8714 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8715 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8716 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8717 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8718 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8719 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8720 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8721 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8722 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8723 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8724 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8725 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8726 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8727 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8728 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8731 return flowtype_table[pctype];
8735 * On X710, performance number is far from the expectation on recent firmware
8736 * versions; on XL710, performance number is also far from the expectation on
8737 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8738 * mode is enabled and port MAC address is equal to the packet destination MAC
8739 * address. The fix for this issue may not be integrated in the following
8740 * firmware version. So the workaround in software driver is needed. It needs
8741 * to modify the initial values of 3 internal only registers for both X710 and
8742 * XL710. Note that the values for X710 or XL710 could be different, and the
8743 * workaround can be removed when it is fixed in firmware in the future.
8746 /* For both X710 and XL710 */
8747 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8748 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8750 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8751 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8754 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8755 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8758 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8760 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8761 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8764 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8766 enum i40e_status_code status;
8767 struct i40e_aq_get_phy_abilities_resp phy_ab;
8770 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8780 i40e_configure_registers(struct i40e_hw *hw)
8786 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8787 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8788 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8794 for (i = 0; i < RTE_DIM(reg_table); i++) {
8795 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8796 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8798 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8799 else /* For X710/XL710/XXV710 */
8801 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8804 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8805 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8807 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8808 else /* For X710/XL710/XXV710 */
8810 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8813 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8814 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8815 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8817 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8820 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8823 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8826 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8830 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8831 reg_table[i].addr, reg);
8832 if (reg == reg_table[i].val)
8835 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8836 reg_table[i].val, NULL);
8839 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8840 reg_table[i].val, reg_table[i].addr);
8843 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8844 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8848 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8849 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8850 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8851 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8853 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8858 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8859 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8863 /* Configure for double VLAN RX stripping */
8864 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8865 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8866 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8867 ret = i40e_aq_debug_write_register(hw,
8868 I40E_VSI_TSR(vsi->vsi_id),
8871 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8873 return I40E_ERR_CONFIG;
8877 /* Configure for double VLAN TX insertion */
8878 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8879 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8880 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8881 ret = i40e_aq_debug_write_register(hw,
8882 I40E_VSI_L2TAGSTXVALID(
8883 vsi->vsi_id), reg, NULL);
8886 "Failed to update VSI_L2TAGSTXVALID[%d]",
8888 return I40E_ERR_CONFIG;
8896 * i40e_aq_add_mirror_rule
8897 * @hw: pointer to the hardware structure
8898 * @seid: VEB seid to add mirror rule to
8899 * @dst_id: destination vsi seid
8900 * @entries: Buffer which contains the entities to be mirrored
8901 * @count: number of entities contained in the buffer
8902 * @rule_id:the rule_id of the rule to be added
8904 * Add a mirror rule for a given veb.
8907 static enum i40e_status_code
8908 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8909 uint16_t seid, uint16_t dst_id,
8910 uint16_t rule_type, uint16_t *entries,
8911 uint16_t count, uint16_t *rule_id)
8913 struct i40e_aq_desc desc;
8914 struct i40e_aqc_add_delete_mirror_rule cmd;
8915 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8916 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8919 enum i40e_status_code status;
8921 i40e_fill_default_direct_cmd_desc(&desc,
8922 i40e_aqc_opc_add_mirror_rule);
8923 memset(&cmd, 0, sizeof(cmd));
8925 buff_len = sizeof(uint16_t) * count;
8926 desc.datalen = rte_cpu_to_le_16(buff_len);
8928 desc.flags |= rte_cpu_to_le_16(
8929 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8930 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8931 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8932 cmd.num_entries = rte_cpu_to_le_16(count);
8933 cmd.seid = rte_cpu_to_le_16(seid);
8934 cmd.destination = rte_cpu_to_le_16(dst_id);
8936 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8937 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8939 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8940 hw->aq.asq_last_status, resp->rule_id,
8941 resp->mirror_rules_used, resp->mirror_rules_free);
8942 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8948 * i40e_aq_del_mirror_rule
8949 * @hw: pointer to the hardware structure
8950 * @seid: VEB seid to add mirror rule to
8951 * @entries: Buffer which contains the entities to be mirrored
8952 * @count: number of entities contained in the buffer
8953 * @rule_id:the rule_id of the rule to be delete
8955 * Delete a mirror rule for a given veb.
8958 static enum i40e_status_code
8959 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8960 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8961 uint16_t count, uint16_t rule_id)
8963 struct i40e_aq_desc desc;
8964 struct i40e_aqc_add_delete_mirror_rule cmd;
8965 uint16_t buff_len = 0;
8966 enum i40e_status_code status;
8969 i40e_fill_default_direct_cmd_desc(&desc,
8970 i40e_aqc_opc_delete_mirror_rule);
8971 memset(&cmd, 0, sizeof(cmd));
8972 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8973 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8975 cmd.num_entries = count;
8976 buff_len = sizeof(uint16_t) * count;
8977 desc.datalen = rte_cpu_to_le_16(buff_len);
8978 buff = (void *)entries;
8980 /* rule id is filled in destination field for deleting mirror rule */
8981 cmd.destination = rte_cpu_to_le_16(rule_id);
8983 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8984 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8985 cmd.seid = rte_cpu_to_le_16(seid);
8987 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8988 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8994 * i40e_mirror_rule_set
8995 * @dev: pointer to the hardware structure
8996 * @mirror_conf: mirror rule info
8997 * @sw_id: mirror rule's sw_id
8998 * @on: enable/disable
9000 * set a mirror rule.
9004 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9005 struct rte_eth_mirror_conf *mirror_conf,
9006 uint8_t sw_id, uint8_t on)
9008 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9009 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9010 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9011 struct i40e_mirror_rule *parent = NULL;
9012 uint16_t seid, dst_seid, rule_id;
9016 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9018 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9020 "mirror rule can not be configured without veb or vfs.");
9023 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9024 PMD_DRV_LOG(ERR, "mirror table is full.");
9027 if (mirror_conf->dst_pool > pf->vf_num) {
9028 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9029 mirror_conf->dst_pool);
9033 seid = pf->main_vsi->veb->seid;
9035 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9036 if (sw_id <= it->index) {
9042 if (mirr_rule && sw_id == mirr_rule->index) {
9044 PMD_DRV_LOG(ERR, "mirror rule exists.");
9047 ret = i40e_aq_del_mirror_rule(hw, seid,
9048 mirr_rule->rule_type,
9050 mirr_rule->num_entries, mirr_rule->id);
9053 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9054 ret, hw->aq.asq_last_status);
9057 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9058 rte_free(mirr_rule);
9059 pf->nb_mirror_rule--;
9063 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9067 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9068 sizeof(struct i40e_mirror_rule) , 0);
9070 PMD_DRV_LOG(ERR, "failed to allocate memory");
9071 return I40E_ERR_NO_MEMORY;
9073 switch (mirror_conf->rule_type) {
9074 case ETH_MIRROR_VLAN:
9075 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9076 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9077 mirr_rule->entries[j] =
9078 mirror_conf->vlan.vlan_id[i];
9083 PMD_DRV_LOG(ERR, "vlan is not specified.");
9084 rte_free(mirr_rule);
9087 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9089 case ETH_MIRROR_VIRTUAL_POOL_UP:
9090 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9091 /* check if the specified pool bit is out of range */
9092 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9093 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9094 rte_free(mirr_rule);
9097 for (i = 0, j = 0; i < pf->vf_num; i++) {
9098 if (mirror_conf->pool_mask & (1ULL << i)) {
9099 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9103 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9104 /* add pf vsi to entries */
9105 mirr_rule->entries[j] = pf->main_vsi_seid;
9109 PMD_DRV_LOG(ERR, "pool is not specified.");
9110 rte_free(mirr_rule);
9113 /* egress and ingress in aq commands means from switch but not port */
9114 mirr_rule->rule_type =
9115 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9116 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9117 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9119 case ETH_MIRROR_UPLINK_PORT:
9120 /* egress and ingress in aq commands means from switch but not port*/
9121 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9123 case ETH_MIRROR_DOWNLINK_PORT:
9124 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9127 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9128 mirror_conf->rule_type);
9129 rte_free(mirr_rule);
9133 /* If the dst_pool is equal to vf_num, consider it as PF */
9134 if (mirror_conf->dst_pool == pf->vf_num)
9135 dst_seid = pf->main_vsi_seid;
9137 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9139 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9140 mirr_rule->rule_type, mirr_rule->entries,
9144 "failed to add mirror rule: ret = %d, aq_err = %d.",
9145 ret, hw->aq.asq_last_status);
9146 rte_free(mirr_rule);
9150 mirr_rule->index = sw_id;
9151 mirr_rule->num_entries = j;
9152 mirr_rule->id = rule_id;
9153 mirr_rule->dst_vsi_seid = dst_seid;
9156 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9158 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9160 pf->nb_mirror_rule++;
9165 * i40e_mirror_rule_reset
9166 * @dev: pointer to the device
9167 * @sw_id: mirror rule's sw_id
9169 * reset a mirror rule.
9173 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9175 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9176 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9177 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9181 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9183 seid = pf->main_vsi->veb->seid;
9185 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9186 if (sw_id == it->index) {
9192 ret = i40e_aq_del_mirror_rule(hw, seid,
9193 mirr_rule->rule_type,
9195 mirr_rule->num_entries, mirr_rule->id);
9198 "failed to remove mirror rule: status = %d, aq_err = %d.",
9199 ret, hw->aq.asq_last_status);
9202 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9203 rte_free(mirr_rule);
9204 pf->nb_mirror_rule--;
9206 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9213 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9215 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9216 uint64_t systim_cycles;
9218 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9219 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9222 return systim_cycles;
9226 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9228 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9231 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9232 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9239 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9241 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9244 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9245 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9252 i40e_start_timecounters(struct rte_eth_dev *dev)
9254 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9255 struct i40e_adapter *adapter =
9256 (struct i40e_adapter *)dev->data->dev_private;
9257 struct rte_eth_link link;
9258 uint32_t tsync_inc_l;
9259 uint32_t tsync_inc_h;
9261 /* Get current link speed. */
9262 memset(&link, 0, sizeof(link));
9263 i40e_dev_link_update(dev, 1);
9264 rte_i40e_dev_atomic_read_link_status(dev, &link);
9266 switch (link.link_speed) {
9267 case ETH_SPEED_NUM_40G:
9268 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9269 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9271 case ETH_SPEED_NUM_10G:
9272 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9273 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9275 case ETH_SPEED_NUM_1G:
9276 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9277 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9284 /* Set the timesync increment value. */
9285 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9286 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9288 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9289 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9290 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9292 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9293 adapter->systime_tc.cc_shift = 0;
9294 adapter->systime_tc.nsec_mask = 0;
9296 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9297 adapter->rx_tstamp_tc.cc_shift = 0;
9298 adapter->rx_tstamp_tc.nsec_mask = 0;
9300 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9301 adapter->tx_tstamp_tc.cc_shift = 0;
9302 adapter->tx_tstamp_tc.nsec_mask = 0;
9306 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9308 struct i40e_adapter *adapter =
9309 (struct i40e_adapter *)dev->data->dev_private;
9311 adapter->systime_tc.nsec += delta;
9312 adapter->rx_tstamp_tc.nsec += delta;
9313 adapter->tx_tstamp_tc.nsec += delta;
9319 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9322 struct i40e_adapter *adapter =
9323 (struct i40e_adapter *)dev->data->dev_private;
9325 ns = rte_timespec_to_ns(ts);
9327 /* Set the timecounters to a new value. */
9328 adapter->systime_tc.nsec = ns;
9329 adapter->rx_tstamp_tc.nsec = ns;
9330 adapter->tx_tstamp_tc.nsec = ns;
9336 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9338 uint64_t ns, systime_cycles;
9339 struct i40e_adapter *adapter =
9340 (struct i40e_adapter *)dev->data->dev_private;
9342 systime_cycles = i40e_read_systime_cyclecounter(dev);
9343 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9344 *ts = rte_ns_to_timespec(ns);
9350 i40e_timesync_enable(struct rte_eth_dev *dev)
9352 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9353 uint32_t tsync_ctl_l;
9354 uint32_t tsync_ctl_h;
9356 /* Stop the timesync system time. */
9357 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9358 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9359 /* Reset the timesync system time value. */
9360 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9361 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9363 i40e_start_timecounters(dev);
9365 /* Clear timesync registers. */
9366 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9367 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9368 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9369 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9370 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9371 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9373 /* Enable timestamping of PTP packets. */
9374 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9375 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9377 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9378 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9379 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9381 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9382 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9388 i40e_timesync_disable(struct rte_eth_dev *dev)
9390 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9391 uint32_t tsync_ctl_l;
9392 uint32_t tsync_ctl_h;
9394 /* Disable timestamping of transmitted PTP packets. */
9395 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9396 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9398 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9399 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9401 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9402 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9404 /* Reset the timesync increment value. */
9405 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9406 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9412 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9413 struct timespec *timestamp, uint32_t flags)
9415 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9416 struct i40e_adapter *adapter =
9417 (struct i40e_adapter *)dev->data->dev_private;
9419 uint32_t sync_status;
9420 uint32_t index = flags & 0x03;
9421 uint64_t rx_tstamp_cycles;
9424 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9425 if ((sync_status & (1 << index)) == 0)
9428 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9429 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9430 *timestamp = rte_ns_to_timespec(ns);
9436 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9437 struct timespec *timestamp)
9439 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9440 struct i40e_adapter *adapter =
9441 (struct i40e_adapter *)dev->data->dev_private;
9443 uint32_t sync_status;
9444 uint64_t tx_tstamp_cycles;
9447 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9448 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9451 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9452 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9453 *timestamp = rte_ns_to_timespec(ns);
9459 * i40e_parse_dcb_configure - parse dcb configure from user
9460 * @dev: the device being configured
9461 * @dcb_cfg: pointer of the result of parse
9462 * @*tc_map: bit map of enabled traffic classes
9464 * Returns 0 on success, negative value on failure
9467 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9468 struct i40e_dcbx_config *dcb_cfg,
9471 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9472 uint8_t i, tc_bw, bw_lf;
9474 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9476 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9477 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9478 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9482 /* assume each tc has the same bw */
9483 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9484 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9485 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9486 /* to ensure the sum of tcbw is equal to 100 */
9487 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9488 for (i = 0; i < bw_lf; i++)
9489 dcb_cfg->etscfg.tcbwtable[i]++;
9491 /* assume each tc has the same Transmission Selection Algorithm */
9492 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9493 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9495 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9496 dcb_cfg->etscfg.prioritytable[i] =
9497 dcb_rx_conf->dcb_tc[i];
9499 /* FW needs one App to configure HW */
9500 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9501 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9502 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9503 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9505 if (dcb_rx_conf->nb_tcs == 0)
9506 *tc_map = 1; /* tc0 only */
9508 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9510 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9511 dcb_cfg->pfc.willing = 0;
9512 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9513 dcb_cfg->pfc.pfcenable = *tc_map;
9519 static enum i40e_status_code
9520 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9521 struct i40e_aqc_vsi_properties_data *info,
9522 uint8_t enabled_tcmap)
9524 enum i40e_status_code ret;
9525 int i, total_tc = 0;
9526 uint16_t qpnum_per_tc, bsf, qp_idx;
9527 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9528 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9529 uint16_t used_queues;
9531 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9532 if (ret != I40E_SUCCESS)
9535 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9536 if (enabled_tcmap & (1 << i))
9541 vsi->enabled_tc = enabled_tcmap;
9543 /* different VSI has different queues assigned */
9544 if (vsi->type == I40E_VSI_MAIN)
9545 used_queues = dev_data->nb_rx_queues -
9546 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9547 else if (vsi->type == I40E_VSI_VMDQ2)
9548 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9550 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9551 return I40E_ERR_NO_AVAILABLE_VSI;
9554 qpnum_per_tc = used_queues / total_tc;
9555 /* Number of queues per enabled TC */
9556 if (qpnum_per_tc == 0) {
9557 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9558 return I40E_ERR_INVALID_QP_ID;
9560 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9562 bsf = rte_bsf32(qpnum_per_tc);
9565 * Configure TC and queue mapping parameters, for enabled TC,
9566 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9567 * default queue will serve it.
9570 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9571 if (vsi->enabled_tc & (1 << i)) {
9572 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9573 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9574 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9575 qp_idx += qpnum_per_tc;
9577 info->tc_mapping[i] = 0;
9580 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9581 if (vsi->type == I40E_VSI_SRIOV) {
9582 info->mapping_flags |=
9583 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9584 for (i = 0; i < vsi->nb_qps; i++)
9585 info->queue_mapping[i] =
9586 rte_cpu_to_le_16(vsi->base_queue + i);
9588 info->mapping_flags |=
9589 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9590 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9592 info->valid_sections |=
9593 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9595 return I40E_SUCCESS;
9599 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9600 * @veb: VEB to be configured
9601 * @tc_map: enabled TC bitmap
9603 * Returns 0 on success, negative value on failure
9605 static enum i40e_status_code
9606 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9608 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9609 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9610 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9611 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9612 enum i40e_status_code ret = I40E_SUCCESS;
9616 /* Check if enabled_tc is same as existing or new TCs */
9617 if (veb->enabled_tc == tc_map)
9620 /* configure tc bandwidth */
9621 memset(&veb_bw, 0, sizeof(veb_bw));
9622 veb_bw.tc_valid_bits = tc_map;
9623 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9624 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9625 if (tc_map & BIT_ULL(i))
9626 veb_bw.tc_bw_share_credits[i] = 1;
9628 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9632 "AQ command Config switch_comp BW allocation per TC failed = %d",
9633 hw->aq.asq_last_status);
9637 memset(&ets_query, 0, sizeof(ets_query));
9638 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9640 if (ret != I40E_SUCCESS) {
9642 "Failed to get switch_comp ETS configuration %u",
9643 hw->aq.asq_last_status);
9646 memset(&bw_query, 0, sizeof(bw_query));
9647 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9649 if (ret != I40E_SUCCESS) {
9651 "Failed to get switch_comp bandwidth configuration %u",
9652 hw->aq.asq_last_status);
9656 /* store and print out BW info */
9657 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9658 veb->bw_info.bw_max = ets_query.tc_bw_max;
9659 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9660 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9661 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9662 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9664 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9665 veb->bw_info.bw_ets_share_credits[i] =
9666 bw_query.tc_bw_share_credits[i];
9667 veb->bw_info.bw_ets_credits[i] =
9668 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9669 /* 4 bits per TC, 4th bit is reserved */
9670 veb->bw_info.bw_ets_max[i] =
9671 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9672 RTE_LEN2MASK(3, uint8_t));
9673 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9674 veb->bw_info.bw_ets_share_credits[i]);
9675 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9676 veb->bw_info.bw_ets_credits[i]);
9677 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9678 veb->bw_info.bw_ets_max[i]);
9681 veb->enabled_tc = tc_map;
9688 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9689 * @vsi: VSI to be configured
9690 * @tc_map: enabled TC bitmap
9692 * Returns 0 on success, negative value on failure
9694 static enum i40e_status_code
9695 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9697 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9698 struct i40e_vsi_context ctxt;
9699 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9700 enum i40e_status_code ret = I40E_SUCCESS;
9703 /* Check if enabled_tc is same as existing or new TCs */
9704 if (vsi->enabled_tc == tc_map)
9707 /* configure tc bandwidth */
9708 memset(&bw_data, 0, sizeof(bw_data));
9709 bw_data.tc_valid_bits = tc_map;
9710 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9711 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9712 if (tc_map & BIT_ULL(i))
9713 bw_data.tc_bw_credits[i] = 1;
9715 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9718 "AQ command Config VSI BW allocation per TC failed = %d",
9719 hw->aq.asq_last_status);
9722 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9723 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9725 /* Update Queue Pairs Mapping for currently enabled UPs */
9726 ctxt.seid = vsi->seid;
9727 ctxt.pf_num = hw->pf_id;
9729 ctxt.uplink_seid = vsi->uplink_seid;
9730 ctxt.info = vsi->info;
9732 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9736 /* Update the VSI after updating the VSI queue-mapping information */
9737 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9739 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9740 hw->aq.asq_last_status);
9743 /* update the local VSI info with updated queue map */
9744 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9745 sizeof(vsi->info.tc_mapping));
9746 (void)rte_memcpy(&vsi->info.queue_mapping,
9747 &ctxt.info.queue_mapping,
9748 sizeof(vsi->info.queue_mapping));
9749 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9750 vsi->info.valid_sections = 0;
9752 /* query and update current VSI BW information */
9753 ret = i40e_vsi_get_bw_config(vsi);
9756 "Failed updating vsi bw info, err %s aq_err %s",
9757 i40e_stat_str(hw, ret),
9758 i40e_aq_str(hw, hw->aq.asq_last_status));
9762 vsi->enabled_tc = tc_map;
9769 * i40e_dcb_hw_configure - program the dcb setting to hw
9770 * @pf: pf the configuration is taken on
9771 * @new_cfg: new configuration
9772 * @tc_map: enabled TC bitmap
9774 * Returns 0 on success, negative value on failure
9776 static enum i40e_status_code
9777 i40e_dcb_hw_configure(struct i40e_pf *pf,
9778 struct i40e_dcbx_config *new_cfg,
9781 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9782 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9783 struct i40e_vsi *main_vsi = pf->main_vsi;
9784 struct i40e_vsi_list *vsi_list;
9785 enum i40e_status_code ret;
9789 /* Use the FW API if FW > v4.4*/
9790 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9791 (hw->aq.fw_maj_ver >= 5))) {
9793 "FW < v4.4, can not use FW LLDP API to configure DCB");
9794 return I40E_ERR_FIRMWARE_API_VERSION;
9797 /* Check if need reconfiguration */
9798 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9799 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9800 return I40E_SUCCESS;
9803 /* Copy the new config to the current config */
9804 *old_cfg = *new_cfg;
9805 old_cfg->etsrec = old_cfg->etscfg;
9806 ret = i40e_set_dcb_config(hw);
9808 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
9809 i40e_stat_str(hw, ret),
9810 i40e_aq_str(hw, hw->aq.asq_last_status));
9813 /* set receive Arbiter to RR mode and ETS scheme by default */
9814 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9815 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9816 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9817 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9818 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9819 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9820 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9821 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9822 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9823 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9824 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9825 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9826 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9828 /* get local mib to check whether it is configured correctly */
9830 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9831 /* Get Local DCB Config */
9832 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9833 &hw->local_dcbx_config);
9835 /* if Veb is created, need to update TC of it at first */
9836 if (main_vsi->veb) {
9837 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9839 PMD_INIT_LOG(WARNING,
9840 "Failed configuring TC for VEB seid=%d",
9841 main_vsi->veb->seid);
9843 /* Update each VSI */
9844 i40e_vsi_config_tc(main_vsi, tc_map);
9845 if (main_vsi->veb) {
9846 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9847 /* Beside main VSI and VMDQ VSIs, only enable default
9850 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9851 ret = i40e_vsi_config_tc(vsi_list->vsi,
9854 ret = i40e_vsi_config_tc(vsi_list->vsi,
9855 I40E_DEFAULT_TCMAP);
9857 PMD_INIT_LOG(WARNING,
9858 "Failed configuring TC for VSI seid=%d",
9859 vsi_list->vsi->seid);
9863 return I40E_SUCCESS;
9867 * i40e_dcb_init_configure - initial dcb config
9868 * @dev: device being configured
9869 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9871 * Returns 0 on success, negative value on failure
9874 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9876 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9877 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9880 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9881 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9885 /* DCB initialization:
9886 * Update DCB configuration from the Firmware and configure
9887 * LLDP MIB change event.
9889 if (sw_dcb == TRUE) {
9890 ret = i40e_init_dcb(hw);
9891 /* If lldp agent is stopped, the return value from
9892 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9893 * adminq status. Otherwise, it should return success.
9895 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9896 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9897 memset(&hw->local_dcbx_config, 0,
9898 sizeof(struct i40e_dcbx_config));
9899 /* set dcb default configuration */
9900 hw->local_dcbx_config.etscfg.willing = 0;
9901 hw->local_dcbx_config.etscfg.maxtcs = 0;
9902 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9903 hw->local_dcbx_config.etscfg.tsatable[0] =
9905 /* all UPs mapping to TC0 */
9906 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9907 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
9908 hw->local_dcbx_config.etsrec =
9909 hw->local_dcbx_config.etscfg;
9910 hw->local_dcbx_config.pfc.willing = 0;
9911 hw->local_dcbx_config.pfc.pfccap =
9912 I40E_MAX_TRAFFIC_CLASS;
9913 hw->local_dcbx_config.pfc.pfcenable =
9915 /* FW needs one App to configure HW */
9916 hw->local_dcbx_config.numapps = 1;
9917 hw->local_dcbx_config.app[0].selector =
9918 I40E_APP_SEL_ETHTYPE;
9919 hw->local_dcbx_config.app[0].priority = 3;
9920 hw->local_dcbx_config.app[0].protocolid =
9921 I40E_APP_PROTOID_FCOE;
9922 ret = i40e_set_dcb_config(hw);
9925 "default dcb config fails. err = %d, aq_err = %d.",
9926 ret, hw->aq.asq_last_status);
9931 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9932 ret, hw->aq.asq_last_status);
9936 ret = i40e_aq_start_lldp(hw, NULL);
9937 if (ret != I40E_SUCCESS)
9938 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9940 ret = i40e_init_dcb(hw);
9942 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9944 "HW doesn't support DCBX offload.");
9949 "DCBX configuration failed, err = %d, aq_err = %d.",
9950 ret, hw->aq.asq_last_status);
9958 * i40e_dcb_setup - setup dcb related config
9959 * @dev: device being configured
9961 * Returns 0 on success, negative value on failure
9964 i40e_dcb_setup(struct rte_eth_dev *dev)
9966 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9967 struct i40e_dcbx_config dcb_cfg;
9971 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9972 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9976 if (pf->vf_num != 0)
9977 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9979 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9981 PMD_INIT_LOG(ERR, "invalid dcb config");
9984 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9986 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9994 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9995 struct rte_eth_dcb_info *dcb_info)
9997 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9998 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9999 struct i40e_vsi *vsi = pf->main_vsi;
10000 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10001 uint16_t bsf, tc_mapping;
10004 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10005 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10007 dcb_info->nb_tcs = 1;
10008 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10009 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10010 for (i = 0; i < dcb_info->nb_tcs; i++)
10011 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10013 /* get queue mapping if vmdq is disabled */
10014 if (!pf->nb_cfg_vmdq_vsi) {
10015 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10016 if (!(vsi->enabled_tc & (1 << i)))
10018 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10019 dcb_info->tc_queue.tc_rxq[j][i].base =
10020 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10021 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10022 dcb_info->tc_queue.tc_txq[j][i].base =
10023 dcb_info->tc_queue.tc_rxq[j][i].base;
10024 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10025 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10026 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10027 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10028 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10033 /* get queue mapping if vmdq is enabled */
10035 vsi = pf->vmdq[j].vsi;
10036 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10037 if (!(vsi->enabled_tc & (1 << i)))
10039 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10040 dcb_info->tc_queue.tc_rxq[j][i].base =
10041 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10042 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10043 dcb_info->tc_queue.tc_txq[j][i].base =
10044 dcb_info->tc_queue.tc_rxq[j][i].base;
10045 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10046 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10047 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10048 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10049 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10052 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10057 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10059 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10060 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10061 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10062 uint16_t interval =
10063 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10064 uint16_t msix_intr;
10066 msix_intr = intr_handle->intr_vec[queue_id];
10067 if (msix_intr == I40E_MISC_VEC_ID)
10068 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10069 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10070 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10071 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10073 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10076 I40E_PFINT_DYN_CTLN(msix_intr -
10077 I40E_RX_VEC_START),
10078 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10079 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10080 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10082 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10084 I40E_WRITE_FLUSH(hw);
10085 rte_intr_enable(&pci_dev->intr_handle);
10091 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10093 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10094 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10095 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10096 uint16_t msix_intr;
10098 msix_intr = intr_handle->intr_vec[queue_id];
10099 if (msix_intr == I40E_MISC_VEC_ID)
10100 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10103 I40E_PFINT_DYN_CTLN(msix_intr -
10104 I40E_RX_VEC_START),
10106 I40E_WRITE_FLUSH(hw);
10111 static int i40e_get_regs(struct rte_eth_dev *dev,
10112 struct rte_dev_reg_info *regs)
10114 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10115 uint32_t *ptr_data = regs->data;
10116 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10117 const struct i40e_reg_info *reg_info;
10119 if (ptr_data == NULL) {
10120 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10121 regs->width = sizeof(uint32_t);
10125 /* The first few registers have to be read using AQ operations */
10127 while (i40e_regs_adminq[reg_idx].name) {
10128 reg_info = &i40e_regs_adminq[reg_idx++];
10129 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10131 arr_idx2 <= reg_info->count2;
10133 reg_offset = arr_idx * reg_info->stride1 +
10134 arr_idx2 * reg_info->stride2;
10135 reg_offset += reg_info->base_addr;
10136 ptr_data[reg_offset >> 2] =
10137 i40e_read_rx_ctl(hw, reg_offset);
10141 /* The remaining registers can be read using primitives */
10143 while (i40e_regs_others[reg_idx].name) {
10144 reg_info = &i40e_regs_others[reg_idx++];
10145 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10147 arr_idx2 <= reg_info->count2;
10149 reg_offset = arr_idx * reg_info->stride1 +
10150 arr_idx2 * reg_info->stride2;
10151 reg_offset += reg_info->base_addr;
10152 ptr_data[reg_offset >> 2] =
10153 I40E_READ_REG(hw, reg_offset);
10160 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10162 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10164 /* Convert word count to byte count */
10165 return hw->nvm.sr_size << 1;
10168 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10169 struct rte_dev_eeprom_info *eeprom)
10171 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10172 uint16_t *data = eeprom->data;
10173 uint16_t offset, length, cnt_words;
10176 offset = eeprom->offset >> 1;
10177 length = eeprom->length >> 1;
10178 cnt_words = length;
10180 if (offset > hw->nvm.sr_size ||
10181 offset + length > hw->nvm.sr_size) {
10182 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10186 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10188 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10189 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10190 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10197 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10198 struct ether_addr *mac_addr)
10200 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10202 if (!is_valid_assigned_ether_addr(mac_addr)) {
10203 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10207 /* Flags: 0x3 updates port address */
10208 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10212 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10214 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10215 struct rte_eth_dev_data *dev_data = pf->dev_data;
10216 uint32_t frame_size = mtu + ETHER_HDR_LEN
10217 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10220 /* check if mtu is within the allowed range */
10221 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10224 /* mtu setting is forbidden if port is start */
10225 if (dev_data->dev_started) {
10226 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10227 dev_data->port_id);
10231 if (frame_size > ETHER_MAX_LEN)
10232 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10234 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10236 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10241 /* Restore ethertype filter */
10243 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10245 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10246 struct i40e_ethertype_filter_list
10247 *ethertype_list = &pf->ethertype.ethertype_list;
10248 struct i40e_ethertype_filter *f;
10249 struct i40e_control_filter_stats stats;
10252 TAILQ_FOREACH(f, ethertype_list, rules) {
10254 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10255 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10256 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10257 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10258 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10260 memset(&stats, 0, sizeof(stats));
10261 i40e_aq_add_rem_control_packet_filter(hw,
10262 f->input.mac_addr.addr_bytes,
10263 f->input.ether_type,
10264 flags, pf->main_vsi->seid,
10265 f->queue, 1, &stats, NULL);
10267 PMD_DRV_LOG(INFO, "Ethertype filter:"
10268 " mac_etype_used = %u, etype_used = %u,"
10269 " mac_etype_free = %u, etype_free = %u",
10270 stats.mac_etype_used, stats.etype_used,
10271 stats.mac_etype_free, stats.etype_free);
10274 /* Restore tunnel filter */
10276 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10278 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10279 struct i40e_vsi *vsi = pf->main_vsi;
10280 struct i40e_tunnel_filter_list
10281 *tunnel_list = &pf->tunnel.tunnel_list;
10282 struct i40e_tunnel_filter *f;
10283 struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10285 TAILQ_FOREACH(f, tunnel_list, rules) {
10286 memset(&cld_filter, 0, sizeof(cld_filter));
10287 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10288 cld_filter.queue_number = f->queue;
10289 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10294 i40e_filter_restore(struct i40e_pf *pf)
10296 i40e_ethertype_filter_restore(pf);
10297 i40e_tunnel_filter_restore(pf);
10298 i40e_fdir_filter_restore(pf);
10302 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10304 if (strcmp(dev->driver->pci_drv.driver.name,
10305 drv->pci_drv.driver.name))
10312 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10314 struct rte_eth_dev *dev;
10315 struct i40e_pf *pf;
10317 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10319 dev = &rte_eth_devices[port];
10321 if (!is_device_supported(dev, &rte_i40e_pmd))
10324 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10326 if (vf >= pf->vf_num || !pf->vfs) {
10327 PMD_DRV_LOG(ERR, "Invalid argument.");
10331 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10337 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10339 struct rte_eth_dev *dev;
10340 struct i40e_pf *pf;
10341 struct i40e_vsi *vsi;
10342 struct i40e_hw *hw;
10343 struct i40e_vsi_context ctxt;
10346 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10348 dev = &rte_eth_devices[port];
10350 if (!is_device_supported(dev, &rte_i40e_pmd))
10353 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10355 if (vf_id >= pf->vf_num || !pf->vfs) {
10356 PMD_DRV_LOG(ERR, "Invalid argument.");
10360 vsi = pf->vfs[vf_id].vsi;
10362 PMD_DRV_LOG(ERR, "Invalid VSI.");
10366 /* Check if it has been already on or off */
10367 if (vsi->info.valid_sections &
10368 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10370 if ((vsi->info.sec_flags &
10371 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10372 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10373 return 0; /* already on */
10375 if ((vsi->info.sec_flags &
10376 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10377 return 0; /* already off */
10381 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10383 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10385 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10387 memset(&ctxt, 0, sizeof(ctxt));
10388 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10389 ctxt.seid = vsi->seid;
10391 hw = I40E_VSI_TO_HW(vsi);
10392 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10393 if (ret != I40E_SUCCESS) {
10395 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10402 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10406 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10407 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10410 for (j = 0; j < I40E_VFTA_SIZE; j++) {
10414 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10415 if (!(vsi->vfta[j] & (1 << k)))
10418 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10422 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10424 ret = i40e_aq_add_vlan(hw, vsi->seid,
10425 &vlan_data, 1, NULL);
10427 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10428 &vlan_data, 1, NULL);
10429 if (ret != I40E_SUCCESS) {
10431 "Failed to add/rm vlan filter");
10437 return I40E_SUCCESS;
10441 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10443 struct rte_eth_dev *dev;
10444 struct i40e_pf *pf;
10445 struct i40e_vsi *vsi;
10446 struct i40e_hw *hw;
10447 struct i40e_vsi_context ctxt;
10450 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10452 dev = &rte_eth_devices[port];
10454 if (!is_device_supported(dev, &rte_i40e_pmd))
10457 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10459 if (vf_id >= pf->vf_num || !pf->vfs) {
10460 PMD_DRV_LOG(ERR, "Invalid argument.");
10464 vsi = pf->vfs[vf_id].vsi;
10466 PMD_DRV_LOG(ERR, "Invalid VSI.");
10470 /* Check if it has been already on or off */
10471 if (vsi->vlan_anti_spoof_on == on)
10472 return 0; /* already on or off */
10474 vsi->vlan_anti_spoof_on = on;
10475 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10477 PMD_DRV_LOG(ERR, "Failed to remove VLAN filters.");
10481 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10483 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10485 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10487 memset(&ctxt, 0, sizeof(ctxt));
10488 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10489 ctxt.seid = vsi->seid;
10491 hw = I40E_VSI_TO_HW(vsi);
10492 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10493 if (ret != I40E_SUCCESS) {
10495 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10502 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10504 struct i40e_mac_filter *f;
10505 struct i40e_macvlan_filter *mv_f;
10507 enum rte_mac_filter_type filter_type;
10508 int ret = I40E_SUCCESS;
10511 /* remove all the MACs */
10512 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10513 vlan_num = vsi->vlan_num;
10514 filter_type = f->mac_info.filter_type;
10515 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10516 filter_type == RTE_MACVLAN_HASH_MATCH) {
10517 if (vlan_num == 0) {
10518 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10519 return I40E_ERR_PARAM;
10521 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10522 filter_type == RTE_MAC_HASH_MATCH)
10525 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10527 PMD_DRV_LOG(ERR, "failed to allocate memory");
10528 return I40E_ERR_NO_MEMORY;
10531 for (i = 0; i < vlan_num; i++) {
10532 mv_f[i].filter_type = filter_type;
10533 (void)rte_memcpy(&mv_f[i].macaddr,
10534 &f->mac_info.mac_addr,
10537 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10538 filter_type == RTE_MACVLAN_HASH_MATCH) {
10539 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10540 &f->mac_info.mac_addr);
10541 if (ret != I40E_SUCCESS) {
10547 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10548 if (ret != I40E_SUCCESS) {
10554 ret = I40E_SUCCESS;
10561 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10563 struct i40e_mac_filter *f;
10564 struct i40e_macvlan_filter *mv_f;
10565 int i, vlan_num = 0;
10566 int ret = I40E_SUCCESS;
10569 /* restore all the MACs */
10570 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10571 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10572 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10574 * If vlan_num is 0, that's the first time to add mac,
10575 * set mask for vlan_id 0.
10577 if (vsi->vlan_num == 0) {
10578 i40e_set_vlan_filter(vsi, 0, 1);
10581 vlan_num = vsi->vlan_num;
10582 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10583 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10586 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10588 PMD_DRV_LOG(ERR, "failed to allocate memory");
10589 return I40E_ERR_NO_MEMORY;
10592 for (i = 0; i < vlan_num; i++) {
10593 mv_f[i].filter_type = f->mac_info.filter_type;
10594 (void)rte_memcpy(&mv_f[i].macaddr,
10595 &f->mac_info.mac_addr,
10599 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10600 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10601 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10602 &f->mac_info.mac_addr);
10603 if (ret != I40E_SUCCESS) {
10609 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10610 if (ret != I40E_SUCCESS) {
10616 ret = I40E_SUCCESS;
10623 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10625 struct i40e_vsi_context ctxt;
10626 struct i40e_hw *hw;
10632 hw = I40E_VSI_TO_HW(vsi);
10634 /* Use the FW API if FW >= v5.0 */
10635 if (hw->aq.fw_maj_ver < 5) {
10636 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10640 /* Check if it has been already on or off */
10641 if (vsi->info.valid_sections &
10642 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10644 if ((vsi->info.switch_id &
10645 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10646 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10647 return 0; /* already on */
10649 if ((vsi->info.switch_id &
10650 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10651 return 0; /* already off */
10655 /* remove all the MAC and VLAN first */
10656 ret = i40e_vsi_rm_mac_filter(vsi);
10658 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10661 if (vsi->vlan_anti_spoof_on) {
10662 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10664 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10669 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10671 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10673 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10675 memset(&ctxt, 0, sizeof(ctxt));
10676 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10677 ctxt.seid = vsi->seid;
10679 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10680 if (ret != I40E_SUCCESS) {
10681 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10685 /* add all the MAC and VLAN back */
10686 ret = i40e_vsi_restore_mac_filter(vsi);
10689 if (vsi->vlan_anti_spoof_on) {
10690 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10699 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10701 struct rte_eth_dev *dev;
10702 struct i40e_pf *pf;
10703 struct i40e_pf_vf *vf;
10704 struct i40e_vsi *vsi;
10708 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10710 dev = &rte_eth_devices[port];
10712 if (!is_device_supported(dev, &rte_i40e_pmd))
10715 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10717 /* setup PF TX loopback */
10718 vsi = pf->main_vsi;
10719 ret = i40e_vsi_set_tx_loopback(vsi, on);
10723 /* setup TX loopback for all the VFs */
10725 /* if no VF, do nothing. */
10729 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10730 vf = &pf->vfs[vf_id];
10733 ret = i40e_vsi_set_tx_loopback(vsi, on);
10742 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10744 struct rte_eth_dev *dev;
10745 struct i40e_pf *pf;
10746 struct i40e_vsi *vsi;
10747 struct i40e_hw *hw;
10750 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10752 dev = &rte_eth_devices[port];
10754 if (!is_device_supported(dev, &rte_i40e_pmd))
10757 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10759 if (vf_id >= pf->vf_num || !pf->vfs) {
10760 PMD_DRV_LOG(ERR, "Invalid argument.");
10764 vsi = pf->vfs[vf_id].vsi;
10766 PMD_DRV_LOG(ERR, "Invalid VSI.");
10770 hw = I40E_VSI_TO_HW(vsi);
10772 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10774 if (ret != I40E_SUCCESS) {
10776 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10783 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10785 struct rte_eth_dev *dev;
10786 struct i40e_pf *pf;
10787 struct i40e_vsi *vsi;
10788 struct i40e_hw *hw;
10791 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10793 dev = &rte_eth_devices[port];
10795 if (!is_device_supported(dev, &rte_i40e_pmd))
10798 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10800 if (vf_id >= pf->vf_num || !pf->vfs) {
10801 PMD_DRV_LOG(ERR, "Invalid argument.");
10805 vsi = pf->vfs[vf_id].vsi;
10807 PMD_DRV_LOG(ERR, "Invalid VSI.");
10811 hw = I40E_VSI_TO_HW(vsi);
10813 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10815 if (ret != I40E_SUCCESS) {
10817 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10824 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
10825 struct ether_addr *mac_addr)
10827 struct i40e_mac_filter *f;
10828 struct rte_eth_dev *dev;
10829 struct i40e_pf_vf *vf;
10830 struct i40e_vsi *vsi;
10831 struct i40e_pf *pf;
10834 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
10837 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10839 dev = &rte_eth_devices[port];
10841 if (!is_device_supported(dev, &rte_i40e_pmd))
10844 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10846 if (vf_id >= pf->vf_num || !pf->vfs)
10849 vf = &pf->vfs[vf_id];
10852 PMD_DRV_LOG(ERR, "Invalid VSI.");
10856 ether_addr_copy(mac_addr, &vf->mac_addr);
10858 /* Remove all existing mac */
10859 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
10860 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
10865 /* Set vlan strip on/off for specific VF from host */
10867 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
10869 struct rte_eth_dev *dev;
10870 struct i40e_pf *pf;
10871 struct i40e_vsi *vsi;
10874 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10876 dev = &rte_eth_devices[port];
10878 if (!is_device_supported(dev, &rte_i40e_pmd))
10881 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10883 if (vf_id >= pf->vf_num || !pf->vfs) {
10884 PMD_DRV_LOG(ERR, "Invalid argument.");
10888 vsi = pf->vfs[vf_id].vsi;
10893 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
10894 if (ret != I40E_SUCCESS) {
10896 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
10902 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
10905 struct rte_eth_dev *dev;
10906 struct i40e_pf *pf;
10907 struct i40e_hw *hw;
10908 struct i40e_vsi *vsi;
10909 struct i40e_vsi_context ctxt;
10912 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10914 if (vlan_id > ETHER_MAX_VLAN_ID) {
10915 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
10919 dev = &rte_eth_devices[port];
10921 if (!is_device_supported(dev, &rte_i40e_pmd))
10924 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10925 hw = I40E_PF_TO_HW(pf);
10928 * return -ENODEV if SRIOV not enabled, VF number not configured
10929 * or no queue assigned.
10931 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10932 pf->vf_nb_qps == 0)
10935 if (vf_id >= pf->vf_num || !pf->vfs) {
10936 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10940 vsi = pf->vfs[vf_id].vsi;
10942 PMD_DRV_LOG(ERR, "Invalid VSI.");
10946 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
10947 vsi->info.pvid = vlan_id;
10949 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
10951 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
10953 memset(&ctxt, 0, sizeof(ctxt));
10954 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10955 ctxt.seid = vsi->seid;
10957 hw = I40E_VSI_TO_HW(vsi);
10958 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10959 if (ret != I40E_SUCCESS) {
10961 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10967 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
10970 struct rte_eth_dev *dev;
10971 struct i40e_pf *pf;
10972 struct i40e_vsi *vsi;
10973 struct i40e_hw *hw;
10974 struct i40e_mac_filter_info filter;
10975 struct ether_addr broadcast = {
10976 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
10979 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10982 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
10986 dev = &rte_eth_devices[port];
10988 if (!is_device_supported(dev, &rte_i40e_pmd))
10991 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10992 hw = I40E_PF_TO_HW(pf);
10994 if (vf_id >= pf->vf_num || !pf->vfs) {
10995 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11000 * return -ENODEV if SRIOV not enabled, VF number not configured
11001 * or no queue assigned.
11003 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11004 pf->vf_nb_qps == 0) {
11005 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11009 vsi = pf->vfs[vf_id].vsi;
11011 PMD_DRV_LOG(ERR, "Invalid VSI.");
11016 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
11017 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
11018 ret = i40e_vsi_add_mac(vsi, &filter);
11020 ret = i40e_vsi_delete_mac(vsi, &broadcast);
11023 if (ret != I40E_SUCCESS && ret != I40E_ERR_PARAM) {
11025 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11033 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11035 struct rte_eth_dev *dev;
11036 struct i40e_pf *pf;
11037 struct i40e_hw *hw;
11038 struct i40e_vsi *vsi;
11039 struct i40e_vsi_context ctxt;
11042 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11045 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11049 dev = &rte_eth_devices[port];
11051 if (!is_device_supported(dev, &rte_i40e_pmd))
11054 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11055 hw = I40E_PF_TO_HW(pf);
11058 * return -ENODEV if SRIOV not enabled, VF number not configured
11059 * or no queue assigned.
11061 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11062 pf->vf_nb_qps == 0) {
11063 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11067 if (vf_id >= pf->vf_num || !pf->vfs) {
11068 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11072 vsi = pf->vfs[vf_id].vsi;
11074 PMD_DRV_LOG(ERR, "Invalid VSI.");
11078 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11080 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11081 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11083 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11084 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11087 memset(&ctxt, 0, sizeof(ctxt));
11088 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11089 ctxt.seid = vsi->seid;
11091 hw = I40E_VSI_TO_HW(vsi);
11092 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11093 if (ret != I40E_SUCCESS) {
11095 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11101 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11102 uint64_t vf_mask, uint8_t on)
11104 struct rte_eth_dev *dev;
11105 struct i40e_pf *pf;
11106 struct i40e_hw *hw;
11108 int ret = I40E_SUCCESS;
11110 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11112 dev = &rte_eth_devices[port];
11114 if (!is_device_supported(dev, &rte_i40e_pmd))
11117 if (vlan_id > ETHER_MAX_VLAN_ID) {
11118 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11122 if (vf_mask == 0) {
11123 PMD_DRV_LOG(ERR, "No VF.");
11128 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11132 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11133 hw = I40E_PF_TO_HW(pf);
11136 * return -ENODEV if SRIOV not enabled, VF number not configured
11137 * or no queue assigned.
11139 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11140 pf->vf_nb_qps == 0) {
11141 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11145 for (vf_idx = 0; vf_idx < 64 && ret == I40E_SUCCESS; vf_idx++) {
11146 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11148 ret = i40e_vsi_add_vlan(pf->vfs[vf_idx].vsi,
11151 ret = i40e_vsi_delete_vlan(pf->vfs[vf_idx].vsi,
11156 if (ret != I40E_SUCCESS) {
11158 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11165 rte_pmd_i40e_get_vf_stats(uint8_t port,
11167 struct rte_eth_stats *stats)
11169 struct rte_eth_dev *dev;
11170 struct i40e_pf *pf;
11171 struct i40e_vsi *vsi;
11173 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11175 dev = &rte_eth_devices[port];
11177 if (!is_device_supported(dev, &rte_i40e_pmd))
11180 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11182 if (vf_id >= pf->vf_num || !pf->vfs) {
11183 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11187 vsi = pf->vfs[vf_id].vsi;
11189 PMD_DRV_LOG(ERR, "Invalid VSI.");
11193 i40e_update_vsi_stats(vsi);
11195 stats->ipackets = vsi->eth_stats.rx_unicast +
11196 vsi->eth_stats.rx_multicast +
11197 vsi->eth_stats.rx_broadcast;
11198 stats->opackets = vsi->eth_stats.tx_unicast +
11199 vsi->eth_stats.tx_multicast +
11200 vsi->eth_stats.tx_broadcast;
11201 stats->ibytes = vsi->eth_stats.rx_bytes;
11202 stats->obytes = vsi->eth_stats.tx_bytes;
11203 stats->ierrors = vsi->eth_stats.rx_discards;
11204 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11210 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11213 struct rte_eth_dev *dev;
11214 struct i40e_pf *pf;
11215 struct i40e_vsi *vsi;
11217 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11219 dev = &rte_eth_devices[port];
11221 if (!is_device_supported(dev, &rte_i40e_pmd))
11224 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11226 if (vf_id >= pf->vf_num || !pf->vfs) {
11227 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11231 vsi = pf->vfs[vf_id].vsi;
11233 PMD_DRV_LOG(ERR, "Invalid VSI.");
11237 vsi->offset_loaded = false;
11238 i40e_update_vsi_stats(vsi);