4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
54 #include <rte_hash_crc.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_adminq_cmd.h"
59 #include "base/i40e_type.h"
60 #include "base/i40e_register.h"
61 #include "base/i40e_dcb.h"
62 #include "i40e_ethdev.h"
63 #include "i40e_rxtx.h"
65 #include "i40e_regs.h"
66 #include "rte_pmd_i40e.h"
68 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
69 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
71 #define I40E_CLEAR_PXE_WAIT_MS 200
73 /* Maximun number of capability elements */
74 #define I40E_MAX_CAP_ELE_NUM 128
76 /* Wait count and inteval */
77 #define I40E_CHK_Q_ENA_COUNT 1000
78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
80 /* Maximun number of VSI */
81 #define I40E_MAX_NUM_VSIS (384UL)
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
114 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
115 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
116 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
118 #define I40E_FLOW_TYPES ( \
119 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
124 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
129 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
131 /* Additional timesync values. */
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
137 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
139 #define I40E_MAX_PERCENT 100
140 #define I40E_DEFAULT_DCB_APP_NUM 1
141 #define I40E_DEFAULT_DCB_APP_PRIO 3
144 * Below are values for writing un-exposed registers suggested
147 /* Destination MAC address */
148 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
149 /* Source MAC address */
150 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
152 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
155 /* Single VLAN tag in the inner L2 header */
156 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
157 /* Source IPv4 address */
158 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
159 /* Destination IPv4 address */
160 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
161 /* Source IPv4 address for X722 */
162 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
163 /* Destination IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
165 /* IPv4 Protocol for X722 */
166 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
167 /* IPv4 Time to Live for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
169 /* IPv4 Type of Service (TOS) */
170 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
172 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
173 /* IPv4 Time to Live */
174 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
175 /* Source IPv6 address */
176 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
177 /* Destination IPv6 address */
178 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
179 /* IPv6 Traffic Class (TC) */
180 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
181 /* IPv6 Next Header */
182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
186 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
187 /* Destination L4 port */
188 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
189 /* SCTP verification tag */
190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
193 /* Source port of tunneling UDP */
194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
195 /* Destination port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
197 /* UDP Tunneling ID, NVGRE/GRE key */
198 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
199 /* Last ether type */
200 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
201 /* Tunneling outer destination IPv4 address */
202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
203 /* Tunneling outer destination IPv6 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
205 /* 1st word of flex payload */
206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
207 /* 2nd word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
209 /* 3rd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
211 /* 4th word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
213 /* 5th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
215 /* 6th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
217 /* 7th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
219 /* 8th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
221 /* all 8 words flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
223 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
225 #define I40E_TRANSLATE_INSET 0
226 #define I40E_TRANSLATE_REG 1
228 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
229 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
230 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
231 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
233 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
235 /* PCI offset for querying capability */
236 #define PCI_DEV_CAP_REG 0xA4
237 /* PCI offset for enabling/disabling Extended Tag */
238 #define PCI_DEV_CTRL_REG 0xA8
239 /* Bit mask of Extended Tag capability */
240 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
241 /* Bit shift of Extended Tag enable/disable */
242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
243 /* Bit mask of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
248 static int i40e_dev_configure(struct rte_eth_dev *dev);
249 static int i40e_dev_start(struct rte_eth_dev *dev);
250 static void i40e_dev_stop(struct rte_eth_dev *dev);
251 static void i40e_dev_close(struct rte_eth_dev *dev);
252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
261 struct rte_eth_xstat *xstats, unsigned n);
262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
263 struct rte_eth_xstat_name *xstats_names,
265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
271 char *fw_version, size_t fw_size);
272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
273 struct rte_eth_dev_info *dev_info);
274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
278 enum rte_vlan_type vlan_type,
280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
288 struct rte_eth_fc_conf *fc_conf);
289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_pfc_conf *pfc_conf);
293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
299 struct rte_eth_rss_reta_entry64 *reta_conf,
301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
305 static int i40e_get_cap(struct i40e_hw *hw);
306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
307 static int i40e_pf_setup(struct i40e_pf *pf);
308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
313 bool offset_loaded, uint64_t *offset, uint64_t *stat);
314 static void i40e_stat_update_48(struct i40e_hw *hw,
320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
339 struct ether_addr *addr);
340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
341 struct i40e_macvlan_filter *mv_f,
344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
346 struct rte_eth_rss_conf *rss_conf);
347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
348 struct rte_eth_rss_conf *rss_conf);
349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
350 struct rte_eth_udp_tunnel *udp_tunnel);
351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
352 struct rte_eth_udp_tunnel *udp_tunnel);
353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
358 enum rte_filter_type filter_type,
359 enum rte_filter_op filter_op,
361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
362 struct rte_eth_dcb_info *dcb_info);
363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
364 static void i40e_configure_registers(struct i40e_hw *hw);
365 static void i40e_hw_init(struct rte_eth_dev *dev);
366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
368 struct rte_eth_mirror_conf *mirror_conf,
369 uint8_t sw_id, uint8_t on);
370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
375 struct timespec *timestamp,
377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
378 struct timespec *timestamp);
379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
384 struct timespec *timestamp);
385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
386 const struct timespec *timestamp);
388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
393 static int i40e_get_regs(struct rte_eth_dev *dev,
394 struct rte_dev_reg_info *regs);
396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
399 struct rte_dev_eeprom_info *eeprom);
401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
402 struct ether_addr *mac_addr);
404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
406 static int i40e_ethertype_filter_convert(
407 const struct rte_eth_ethertype_filter *input,
408 struct i40e_ethertype_filter *filter);
409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
410 struct i40e_ethertype_filter *filter);
412 static int i40e_tunnel_filter_convert(
413 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
414 struct i40e_tunnel_filter *tunnel_filter);
415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
416 struct i40e_tunnel_filter *tunnel_filter);
418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
420 static void i40e_filter_restore(struct i40e_pf *pf);
422 static const struct rte_pci_id pci_id_i40e_map[] = {
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
443 { .vendor_id = 0, /* sentinel */ },
446 static const struct eth_dev_ops i40e_eth_dev_ops = {
447 .dev_configure = i40e_dev_configure,
448 .dev_start = i40e_dev_start,
449 .dev_stop = i40e_dev_stop,
450 .dev_close = i40e_dev_close,
451 .promiscuous_enable = i40e_dev_promiscuous_enable,
452 .promiscuous_disable = i40e_dev_promiscuous_disable,
453 .allmulticast_enable = i40e_dev_allmulticast_enable,
454 .allmulticast_disable = i40e_dev_allmulticast_disable,
455 .dev_set_link_up = i40e_dev_set_link_up,
456 .dev_set_link_down = i40e_dev_set_link_down,
457 .link_update = i40e_dev_link_update,
458 .stats_get = i40e_dev_stats_get,
459 .xstats_get = i40e_dev_xstats_get,
460 .xstats_get_names = i40e_dev_xstats_get_names,
461 .stats_reset = i40e_dev_stats_reset,
462 .xstats_reset = i40e_dev_stats_reset,
463 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
464 .fw_version_get = i40e_fw_version_get,
465 .dev_infos_get = i40e_dev_info_get,
466 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
467 .vlan_filter_set = i40e_vlan_filter_set,
468 .vlan_tpid_set = i40e_vlan_tpid_set,
469 .vlan_offload_set = i40e_vlan_offload_set,
470 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
471 .vlan_pvid_set = i40e_vlan_pvid_set,
472 .rx_queue_start = i40e_dev_rx_queue_start,
473 .rx_queue_stop = i40e_dev_rx_queue_stop,
474 .tx_queue_start = i40e_dev_tx_queue_start,
475 .tx_queue_stop = i40e_dev_tx_queue_stop,
476 .rx_queue_setup = i40e_dev_rx_queue_setup,
477 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
478 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
479 .rx_queue_release = i40e_dev_rx_queue_release,
480 .rx_queue_count = i40e_dev_rx_queue_count,
481 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
482 .tx_queue_setup = i40e_dev_tx_queue_setup,
483 .tx_queue_release = i40e_dev_tx_queue_release,
484 .dev_led_on = i40e_dev_led_on,
485 .dev_led_off = i40e_dev_led_off,
486 .flow_ctrl_get = i40e_flow_ctrl_get,
487 .flow_ctrl_set = i40e_flow_ctrl_set,
488 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
489 .mac_addr_add = i40e_macaddr_add,
490 .mac_addr_remove = i40e_macaddr_remove,
491 .reta_update = i40e_dev_rss_reta_update,
492 .reta_query = i40e_dev_rss_reta_query,
493 .rss_hash_update = i40e_dev_rss_hash_update,
494 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
495 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
496 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
497 .filter_ctrl = i40e_dev_filter_ctrl,
498 .rxq_info_get = i40e_rxq_info_get,
499 .txq_info_get = i40e_txq_info_get,
500 .mirror_rule_set = i40e_mirror_rule_set,
501 .mirror_rule_reset = i40e_mirror_rule_reset,
502 .timesync_enable = i40e_timesync_enable,
503 .timesync_disable = i40e_timesync_disable,
504 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
505 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
506 .get_dcb_info = i40e_dev_get_dcb_info,
507 .timesync_adjust_time = i40e_timesync_adjust_time,
508 .timesync_read_time = i40e_timesync_read_time,
509 .timesync_write_time = i40e_timesync_write_time,
510 .get_reg = i40e_get_regs,
511 .get_eeprom_length = i40e_get_eeprom_length,
512 .get_eeprom = i40e_get_eeprom,
513 .mac_addr_set = i40e_set_default_mac_addr,
514 .mtu_set = i40e_dev_mtu_set,
517 /* store statistics names and its offset in stats structure */
518 struct rte_i40e_xstats_name_off {
519 char name[RTE_ETH_XSTATS_NAME_SIZE];
523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
524 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
525 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
526 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
527 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
528 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
529 rx_unknown_protocol)},
530 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
531 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
532 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
533 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
537 sizeof(rte_i40e_stats_strings[0]))
539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
540 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
541 tx_dropped_link_down)},
542 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
543 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
545 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
546 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
548 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
552 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
553 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
554 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
555 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
556 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
557 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
559 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
571 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
574 mac_short_packet_dropped)},
575 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
578 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
579 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
581 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
591 {"rx_flow_director_atr_match_packets",
592 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
593 {"rx_flow_director_sb_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
595 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
597 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
601 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
606 sizeof(rte_i40e_hw_port_strings[0]))
608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
609 {"xon_packets", offsetof(struct i40e_hw_port_stats,
611 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
616 sizeof(rte_i40e_rxq_prio_strings[0]))
618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
619 {"xon_packets", offsetof(struct i40e_hw_port_stats,
621 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
624 priority_xon_2_xoff)},
627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
628 sizeof(rte_i40e_txq_prio_strings[0]))
630 static struct eth_driver rte_i40e_pmd = {
632 .id_table = pci_id_i40e_map,
633 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
634 .probe = rte_eth_dev_pci_probe,
635 .remove = rte_eth_dev_pci_remove,
637 .eth_dev_init = eth_i40e_dev_init,
638 .eth_dev_uninit = eth_i40e_dev_uninit,
639 .dev_private_size = sizeof(struct i40e_adapter),
643 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
644 struct rte_eth_link *link)
646 struct rte_eth_link *dst = link;
647 struct rte_eth_link *src = &(dev->data->dev_link);
649 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
650 *(uint64_t *)src) == 0)
657 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
658 struct rte_eth_link *link)
660 struct rte_eth_link *dst = &(dev->data->dev_link);
661 struct rte_eth_link *src = link;
663 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
664 *(uint64_t *)src) == 0)
670 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
671 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
672 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
674 #ifndef I40E_GLQF_ORT
675 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
677 #ifndef I40E_GLQF_PIT
678 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
681 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
684 * Initialize registers for flexible payload, which should be set by NVM.
685 * This should be removed from code once it is fixed in NVM.
687 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
688 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
689 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
690 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
691 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
692 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
693 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
694 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
695 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
696 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
697 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
698 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
700 /* Initialize registers for parsing packet type of QinQ */
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
702 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
705 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
708 * Add a ethertype filter to drop all flow control frames transmitted
712 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
714 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
715 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
716 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
717 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
720 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
721 I40E_FLOW_CONTROL_ETHERTYPE, flags,
722 pf->main_vsi_seid, 0,
726 "Failed to add filter to drop flow control frames from VSIs.");
730 floating_veb_list_handler(__rte_unused const char *key,
731 const char *floating_veb_value,
735 unsigned int count = 0;
738 bool *vf_floating_veb = opaque;
740 while (isblank(*floating_veb_value))
741 floating_veb_value++;
743 /* Reset floating VEB configuration for VFs */
744 for (idx = 0; idx < I40E_MAX_VF; idx++)
745 vf_floating_veb[idx] = false;
749 while (isblank(*floating_veb_value))
750 floating_veb_value++;
751 if (*floating_veb_value == '\0')
754 idx = strtoul(floating_veb_value, &end, 10);
755 if (errno || end == NULL)
757 while (isblank(*end))
761 } else if ((*end == ';') || (*end == '\0')) {
763 if (min == I40E_MAX_VF)
765 if (max >= I40E_MAX_VF)
766 max = I40E_MAX_VF - 1;
767 for (idx = min; idx <= max; idx++) {
768 vf_floating_veb[idx] = true;
775 floating_veb_value = end + 1;
776 } while (*end != '\0');
785 config_vf_floating_veb(struct rte_devargs *devargs,
786 uint16_t floating_veb,
787 bool *vf_floating_veb)
789 struct rte_kvargs *kvlist;
791 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
795 /* All the VFs attach to the floating VEB by default
796 * when the floating VEB is enabled.
798 for (i = 0; i < I40E_MAX_VF; i++)
799 vf_floating_veb[i] = true;
804 kvlist = rte_kvargs_parse(devargs->args, NULL);
808 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
809 rte_kvargs_free(kvlist);
812 /* When the floating_veb_list parameter exists, all the VFs
813 * will attach to the legacy VEB firstly, then configure VFs
814 * to the floating VEB according to the floating_veb_list.
816 if (rte_kvargs_process(kvlist, floating_veb_list,
817 floating_veb_list_handler,
818 vf_floating_veb) < 0) {
819 rte_kvargs_free(kvlist);
822 rte_kvargs_free(kvlist);
826 i40e_check_floating_handler(__rte_unused const char *key,
828 __rte_unused void *opaque)
830 if (strcmp(value, "1"))
837 is_floating_veb_supported(struct rte_devargs *devargs)
839 struct rte_kvargs *kvlist;
840 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
845 kvlist = rte_kvargs_parse(devargs->args, NULL);
849 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
850 rte_kvargs_free(kvlist);
853 /* Floating VEB is enabled when there's key-value:
854 * enable_floating_veb=1
856 if (rte_kvargs_process(kvlist, floating_veb_key,
857 i40e_check_floating_handler, NULL) < 0) {
858 rte_kvargs_free(kvlist);
861 rte_kvargs_free(kvlist);
867 config_floating_veb(struct rte_eth_dev *dev)
869 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
870 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
873 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
875 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
877 is_floating_veb_supported(pci_dev->device.devargs);
878 config_vf_floating_veb(pci_dev->device.devargs,
880 pf->floating_veb_list);
882 pf->floating_veb = false;
886 #define I40E_L2_TAGS_S_TAG_SHIFT 1
887 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
890 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
893 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
894 char ethertype_hash_name[RTE_HASH_NAMESIZE];
897 struct rte_hash_parameters ethertype_hash_params = {
898 .name = ethertype_hash_name,
899 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
900 .key_len = sizeof(struct i40e_ethertype_filter_input),
901 .hash_func = rte_hash_crc,
904 /* Initialize ethertype filter rule list and hash */
905 TAILQ_INIT(ðertype_rule->ethertype_list);
906 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
907 "ethertype_%s", dev->data->name);
908 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
909 if (!ethertype_rule->hash_table) {
910 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
913 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
914 sizeof(struct i40e_ethertype_filter *) *
915 I40E_MAX_ETHERTYPE_FILTER_NUM,
917 if (!ethertype_rule->hash_map) {
919 "Failed to allocate memory for ethertype hash map!");
921 goto err_ethertype_hash_map_alloc;
926 err_ethertype_hash_map_alloc:
927 rte_hash_free(ethertype_rule->hash_table);
933 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
936 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
937 char tunnel_hash_name[RTE_HASH_NAMESIZE];
940 struct rte_hash_parameters tunnel_hash_params = {
941 .name = tunnel_hash_name,
942 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
943 .key_len = sizeof(struct i40e_tunnel_filter_input),
944 .hash_func = rte_hash_crc,
947 /* Initialize tunnel filter rule list and hash */
948 TAILQ_INIT(&tunnel_rule->tunnel_list);
949 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
950 "tunnel_%s", dev->data->name);
951 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
952 if (!tunnel_rule->hash_table) {
953 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
956 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
957 sizeof(struct i40e_tunnel_filter *) *
958 I40E_MAX_TUNNEL_FILTER_NUM,
960 if (!tunnel_rule->hash_map) {
962 "Failed to allocate memory for tunnel hash map!");
964 goto err_tunnel_hash_map_alloc;
969 err_tunnel_hash_map_alloc:
970 rte_hash_free(tunnel_rule->hash_table);
976 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
978 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
979 struct i40e_fdir_info *fdir_info = &pf->fdir;
980 char fdir_hash_name[RTE_HASH_NAMESIZE];
983 struct rte_hash_parameters fdir_hash_params = {
984 .name = fdir_hash_name,
985 .entries = I40E_MAX_FDIR_FILTER_NUM,
986 .key_len = sizeof(struct rte_eth_fdir_input),
987 .hash_func = rte_hash_crc,
990 /* Initialize flow director filter rule list and hash */
991 TAILQ_INIT(&fdir_info->fdir_list);
992 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
993 "fdir_%s", dev->data->name);
994 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
995 if (!fdir_info->hash_table) {
996 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
999 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1000 sizeof(struct i40e_fdir_filter *) *
1001 I40E_MAX_FDIR_FILTER_NUM,
1003 if (!fdir_info->hash_map) {
1005 "Failed to allocate memory for fdir hash map!");
1007 goto err_fdir_hash_map_alloc;
1011 err_fdir_hash_map_alloc:
1012 rte_hash_free(fdir_info->hash_table);
1018 eth_i40e_dev_init(struct rte_eth_dev *dev)
1020 struct rte_pci_device *pci_dev;
1021 struct rte_intr_handle *intr_handle;
1022 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024 struct i40e_vsi *vsi;
1027 uint8_t aq_fail = 0;
1029 PMD_INIT_FUNC_TRACE();
1031 dev->dev_ops = &i40e_eth_dev_ops;
1032 dev->rx_pkt_burst = i40e_recv_pkts;
1033 dev->tx_pkt_burst = i40e_xmit_pkts;
1034 dev->tx_pkt_prepare = i40e_prep_pkts;
1036 /* for secondary processes, we don't initialise any further as primary
1037 * has already done this work. Only check we don't need a different
1039 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040 i40e_set_rx_function(dev);
1041 i40e_set_tx_function(dev);
1044 pci_dev = I40E_DEV_TO_PCI(dev);
1045 intr_handle = &pci_dev->intr_handle;
1047 rte_eth_copy_pci_info(dev, pci_dev);
1048 dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1050 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1051 pf->adapter->eth_dev = dev;
1052 pf->dev_data = dev->data;
1054 hw->back = I40E_PF_TO_ADAPTER(pf);
1055 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1058 "Hardware is not available, as address is NULL");
1062 hw->vendor_id = pci_dev->id.vendor_id;
1063 hw->device_id = pci_dev->id.device_id;
1064 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1065 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1066 hw->bus.device = pci_dev->addr.devid;
1067 hw->bus.func = pci_dev->addr.function;
1068 hw->adapter_stopped = 0;
1070 /* Make sure all is clean before doing PF reset */
1073 /* Initialize the hardware */
1076 /* Reset here to make sure all is clean for each PF */
1077 ret = i40e_pf_reset(hw);
1079 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1083 /* Initialize the shared code (base driver) */
1084 ret = i40e_init_shared_code(hw);
1086 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1091 * To work around the NVM issue, initialize registers
1092 * for flexible payload and packet type of QinQ by
1093 * software. It should be removed once issues are fixed
1096 i40e_GLQF_reg_init(hw);
1098 /* Initialize the input set for filters (hash and fd) to default value */
1099 i40e_filter_input_set_init(pf);
1101 /* Initialize the parameters for adminq */
1102 i40e_init_adminq_parameter(hw);
1103 ret = i40e_init_adminq(hw);
1104 if (ret != I40E_SUCCESS) {
1105 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1108 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1109 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1110 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1111 ((hw->nvm.version >> 12) & 0xf),
1112 ((hw->nvm.version >> 4) & 0xff),
1113 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1115 /* Need the special FW version to support floating VEB */
1116 config_floating_veb(dev);
1117 /* Clear PXE mode */
1118 i40e_clear_pxe_mode(hw);
1119 ret = i40e_dev_sync_phy_type(hw);
1121 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1122 goto err_sync_phy_type;
1125 * On X710, performance number is far from the expectation on recent
1126 * firmware versions. The fix for this issue may not be integrated in
1127 * the following firmware version. So the workaround in software driver
1128 * is needed. It needs to modify the initial values of 3 internal only
1129 * registers. Note that the workaround can be removed when it is fixed
1130 * in firmware in the future.
1132 i40e_configure_registers(hw);
1134 /* Get hw capabilities */
1135 ret = i40e_get_cap(hw);
1136 if (ret != I40E_SUCCESS) {
1137 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1138 goto err_get_capabilities;
1141 /* Initialize parameters for PF */
1142 ret = i40e_pf_parameter_init(dev);
1144 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1145 goto err_parameter_init;
1148 /* Initialize the queue management */
1149 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1151 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1152 goto err_qp_pool_init;
1154 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1155 hw->func_caps.num_msix_vectors - 1);
1157 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1158 goto err_msix_pool_init;
1161 /* Initialize lan hmc */
1162 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1163 hw->func_caps.num_rx_qp, 0, 0);
1164 if (ret != I40E_SUCCESS) {
1165 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1166 goto err_init_lan_hmc;
1169 /* Configure lan hmc */
1170 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1171 if (ret != I40E_SUCCESS) {
1172 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1173 goto err_configure_lan_hmc;
1176 /* Get and check the mac address */
1177 i40e_get_mac_addr(hw, hw->mac.addr);
1178 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1179 PMD_INIT_LOG(ERR, "mac address is not valid");
1181 goto err_get_mac_addr;
1183 /* Copy the permanent MAC address */
1184 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1185 (struct ether_addr *) hw->mac.perm_addr);
1187 /* Disable flow control */
1188 hw->fc.requested_mode = I40E_FC_NONE;
1189 i40e_set_fc(hw, &aq_fail, TRUE);
1191 /* Set the global registers with default ether type value */
1192 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1193 if (ret != I40E_SUCCESS) {
1195 "Failed to set the default outer VLAN ether type");
1196 goto err_setup_pf_switch;
1199 /* PF setup, which includes VSI setup */
1200 ret = i40e_pf_setup(pf);
1202 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1203 goto err_setup_pf_switch;
1206 /* reset all stats of the device, including pf and main vsi */
1207 i40e_dev_stats_reset(dev);
1211 /* Disable double vlan by default */
1212 i40e_vsi_config_double_vlan(vsi, FALSE);
1214 /* Disable S-TAG identification when floating_veb is disabled */
1215 if (!pf->floating_veb) {
1216 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1217 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1218 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1219 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1223 if (!vsi->max_macaddrs)
1224 len = ETHER_ADDR_LEN;
1226 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1228 /* Should be after VSI initialized */
1229 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1230 if (!dev->data->mac_addrs) {
1232 "Failed to allocated memory for storing mac address");
1235 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1236 &dev->data->mac_addrs[0]);
1238 /* initialize pf host driver to setup SRIOV resource if applicable */
1239 i40e_pf_host_init(dev);
1241 /* register callback func to eal lib */
1242 rte_intr_callback_register(intr_handle,
1243 i40e_dev_interrupt_handler, dev);
1245 /* configure and enable device interrupt */
1246 i40e_pf_config_irq0(hw, TRUE);
1247 i40e_pf_enable_irq0(hw);
1249 /* enable uio intr after callback register */
1250 rte_intr_enable(intr_handle);
1252 * Add an ethertype filter to drop all flow control frames transmitted
1253 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1256 i40e_add_tx_flow_control_drop_filter(pf);
1258 /* Set the max frame size to 0x2600 by default,
1259 * in case other drivers changed the default value.
1261 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1263 /* initialize mirror rule list */
1264 TAILQ_INIT(&pf->mirror_list);
1266 /* Init dcb to sw mode by default */
1267 ret = i40e_dcb_init_configure(dev, TRUE);
1268 if (ret != I40E_SUCCESS) {
1269 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1270 pf->flags &= ~I40E_FLAG_DCB;
1273 ret = i40e_init_ethtype_filter_list(dev);
1275 goto err_init_ethtype_filter_list;
1276 ret = i40e_init_tunnel_filter_list(dev);
1278 goto err_init_tunnel_filter_list;
1279 ret = i40e_init_fdir_filter_list(dev);
1281 goto err_init_fdir_filter_list;
1285 err_init_fdir_filter_list:
1286 rte_free(pf->tunnel.hash_table);
1287 rte_free(pf->tunnel.hash_map);
1288 err_init_tunnel_filter_list:
1289 rte_free(pf->ethertype.hash_table);
1290 rte_free(pf->ethertype.hash_map);
1291 err_init_ethtype_filter_list:
1292 rte_free(dev->data->mac_addrs);
1294 i40e_vsi_release(pf->main_vsi);
1295 err_setup_pf_switch:
1297 err_configure_lan_hmc:
1298 (void)i40e_shutdown_lan_hmc(hw);
1300 i40e_res_pool_destroy(&pf->msix_pool);
1302 i40e_res_pool_destroy(&pf->qp_pool);
1305 err_get_capabilities:
1307 (void)i40e_shutdown_adminq(hw);
1313 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1315 struct i40e_ethertype_filter *p_ethertype;
1316 struct i40e_ethertype_rule *ethertype_rule;
1318 ethertype_rule = &pf->ethertype;
1319 /* Remove all ethertype filter rules and hash */
1320 if (ethertype_rule->hash_map)
1321 rte_free(ethertype_rule->hash_map);
1322 if (ethertype_rule->hash_table)
1323 rte_hash_free(ethertype_rule->hash_table);
1325 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1326 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1327 p_ethertype, rules);
1328 rte_free(p_ethertype);
1333 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1335 struct i40e_tunnel_filter *p_tunnel;
1336 struct i40e_tunnel_rule *tunnel_rule;
1338 tunnel_rule = &pf->tunnel;
1339 /* Remove all tunnel director rules and hash */
1340 if (tunnel_rule->hash_map)
1341 rte_free(tunnel_rule->hash_map);
1342 if (tunnel_rule->hash_table)
1343 rte_hash_free(tunnel_rule->hash_table);
1345 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1346 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1352 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1354 struct i40e_fdir_filter *p_fdir;
1355 struct i40e_fdir_info *fdir_info;
1357 fdir_info = &pf->fdir;
1358 /* Remove all flow director rules and hash */
1359 if (fdir_info->hash_map)
1360 rte_free(fdir_info->hash_map);
1361 if (fdir_info->hash_table)
1362 rte_hash_free(fdir_info->hash_table);
1364 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1365 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1371 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1374 struct rte_pci_device *pci_dev;
1375 struct rte_intr_handle *intr_handle;
1377 struct i40e_filter_control_settings settings;
1378 struct rte_flow *p_flow;
1380 uint8_t aq_fail = 0;
1382 PMD_INIT_FUNC_TRACE();
1384 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1387 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1388 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389 pci_dev = I40E_DEV_TO_PCI(dev);
1390 intr_handle = &pci_dev->intr_handle;
1392 if (hw->adapter_stopped == 0)
1393 i40e_dev_close(dev);
1395 dev->dev_ops = NULL;
1396 dev->rx_pkt_burst = NULL;
1397 dev->tx_pkt_burst = NULL;
1399 /* Clear PXE mode */
1400 i40e_clear_pxe_mode(hw);
1402 /* Unconfigure filter control */
1403 memset(&settings, 0, sizeof(settings));
1404 ret = i40e_set_filter_control(hw, &settings);
1406 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1409 /* Disable flow control */
1410 hw->fc.requested_mode = I40E_FC_NONE;
1411 i40e_set_fc(hw, &aq_fail, TRUE);
1413 /* uninitialize pf host driver */
1414 i40e_pf_host_uninit(dev);
1416 rte_free(dev->data->mac_addrs);
1417 dev->data->mac_addrs = NULL;
1419 /* disable uio intr before callback unregister */
1420 rte_intr_disable(intr_handle);
1422 /* register callback func to eal lib */
1423 rte_intr_callback_unregister(intr_handle,
1424 i40e_dev_interrupt_handler, dev);
1426 i40e_rm_ethtype_filter_list(pf);
1427 i40e_rm_tunnel_filter_list(pf);
1428 i40e_rm_fdir_filter_list(pf);
1430 /* Remove all flows */
1431 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1432 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1440 i40e_dev_configure(struct rte_eth_dev *dev)
1442 struct i40e_adapter *ad =
1443 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1444 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1445 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1448 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1449 * bulk allocation or vector Rx preconditions we will reset it.
1451 ad->rx_bulk_alloc_allowed = true;
1452 ad->rx_vec_allowed = true;
1453 ad->tx_simple_allowed = true;
1454 ad->tx_vec_allowed = true;
1456 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1457 ret = i40e_fdir_setup(pf);
1458 if (ret != I40E_SUCCESS) {
1459 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1462 ret = i40e_fdir_configure(dev);
1464 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1468 i40e_fdir_teardown(pf);
1470 ret = i40e_dev_init_vlan(dev);
1475 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1476 * RSS setting have different requirements.
1477 * General PMD driver call sequence are NIC init, configure,
1478 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1479 * will try to lookup the VSI that specific queue belongs to if VMDQ
1480 * applicable. So, VMDQ setting has to be done before
1481 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1482 * For RSS setting, it will try to calculate actual configured RX queue
1483 * number, which will be available after rx_queue_setup(). dev_start()
1484 * function is good to place RSS setup.
1486 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1487 ret = i40e_vmdq_setup(dev);
1492 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1493 ret = i40e_dcb_setup(dev);
1495 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1500 TAILQ_INIT(&pf->flow_list);
1505 /* need to release vmdq resource if exists */
1506 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1507 i40e_vsi_release(pf->vmdq[i].vsi);
1508 pf->vmdq[i].vsi = NULL;
1513 /* need to release fdir resource if exists */
1514 i40e_fdir_teardown(pf);
1519 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1521 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1522 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1523 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1524 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1525 uint16_t msix_vect = vsi->msix_intr;
1528 for (i = 0; i < vsi->nb_qps; i++) {
1529 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1530 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1534 if (vsi->type != I40E_VSI_SRIOV) {
1535 if (!rte_intr_allow_others(intr_handle)) {
1536 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1537 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1539 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1542 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1543 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1545 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1550 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1551 vsi->user_param + (msix_vect - 1);
1553 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1554 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1556 I40E_WRITE_FLUSH(hw);
1560 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1561 int base_queue, int nb_queue)
1565 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1567 /* Bind all RX queues to allocated MSIX interrupt */
1568 for (i = 0; i < nb_queue; i++) {
1569 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1570 I40E_QINT_RQCTL_ITR_INDX_MASK |
1571 ((base_queue + i + 1) <<
1572 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1573 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1574 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1576 if (i == nb_queue - 1)
1577 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1578 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1581 /* Write first RX queue to Link list register as the head element */
1582 if (vsi->type != I40E_VSI_SRIOV) {
1584 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1586 if (msix_vect == I40E_MISC_VEC_ID) {
1587 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1589 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1591 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1593 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1596 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1598 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1600 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1602 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1609 if (msix_vect == I40E_MISC_VEC_ID) {
1611 I40E_VPINT_LNKLST0(vsi->user_param),
1613 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1615 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1617 /* num_msix_vectors_vf needs to minus irq0 */
1618 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1619 vsi->user_param + (msix_vect - 1);
1621 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1623 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1625 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1629 I40E_WRITE_FLUSH(hw);
1633 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1635 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1636 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1637 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1638 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1639 uint16_t msix_vect = vsi->msix_intr;
1640 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1641 uint16_t queue_idx = 0;
1646 for (i = 0; i < vsi->nb_qps; i++) {
1647 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1648 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1651 /* INTENA flag is not auto-cleared for interrupt */
1652 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1653 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1654 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1655 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1656 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1658 /* VF bind interrupt */
1659 if (vsi->type == I40E_VSI_SRIOV) {
1660 __vsi_queues_bind_intr(vsi, msix_vect,
1661 vsi->base_queue, vsi->nb_qps);
1665 /* PF & VMDq bind interrupt */
1666 if (rte_intr_dp_is_en(intr_handle)) {
1667 if (vsi->type == I40E_VSI_MAIN) {
1670 } else if (vsi->type == I40E_VSI_VMDQ2) {
1671 struct i40e_vsi *main_vsi =
1672 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1673 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1678 for (i = 0; i < vsi->nb_used_qps; i++) {
1680 if (!rte_intr_allow_others(intr_handle))
1681 /* allow to share MISC_VEC_ID */
1682 msix_vect = I40E_MISC_VEC_ID;
1684 /* no enough msix_vect, map all to one */
1685 __vsi_queues_bind_intr(vsi, msix_vect,
1686 vsi->base_queue + i,
1687 vsi->nb_used_qps - i);
1688 for (; !!record && i < vsi->nb_used_qps; i++)
1689 intr_handle->intr_vec[queue_idx + i] =
1693 /* 1:1 queue/msix_vect mapping */
1694 __vsi_queues_bind_intr(vsi, msix_vect,
1695 vsi->base_queue + i, 1);
1697 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1705 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1707 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1708 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1709 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1710 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1711 uint16_t interval = i40e_calc_itr_interval(\
1712 RTE_LIBRTE_I40E_ITR_INTERVAL);
1713 uint16_t msix_intr, i;
1715 if (rte_intr_allow_others(intr_handle))
1716 for (i = 0; i < vsi->nb_msix; i++) {
1717 msix_intr = vsi->msix_intr + i;
1718 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1719 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1720 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1721 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1723 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1726 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1727 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1728 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1729 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1731 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1733 I40E_WRITE_FLUSH(hw);
1737 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1739 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1740 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1741 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1742 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1743 uint16_t msix_intr, i;
1745 if (rte_intr_allow_others(intr_handle))
1746 for (i = 0; i < vsi->nb_msix; i++) {
1747 msix_intr = vsi->msix_intr + i;
1748 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1752 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1754 I40E_WRITE_FLUSH(hw);
1757 static inline uint8_t
1758 i40e_parse_link_speeds(uint16_t link_speeds)
1760 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1762 if (link_speeds & ETH_LINK_SPEED_40G)
1763 link_speed |= I40E_LINK_SPEED_40GB;
1764 if (link_speeds & ETH_LINK_SPEED_25G)
1765 link_speed |= I40E_LINK_SPEED_25GB;
1766 if (link_speeds & ETH_LINK_SPEED_20G)
1767 link_speed |= I40E_LINK_SPEED_20GB;
1768 if (link_speeds & ETH_LINK_SPEED_10G)
1769 link_speed |= I40E_LINK_SPEED_10GB;
1770 if (link_speeds & ETH_LINK_SPEED_1G)
1771 link_speed |= I40E_LINK_SPEED_1GB;
1772 if (link_speeds & ETH_LINK_SPEED_100M)
1773 link_speed |= I40E_LINK_SPEED_100MB;
1779 i40e_phy_conf_link(struct i40e_hw *hw,
1781 uint8_t force_speed)
1783 enum i40e_status_code status;
1784 struct i40e_aq_get_phy_abilities_resp phy_ab;
1785 struct i40e_aq_set_phy_config phy_conf;
1786 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1787 I40E_AQ_PHY_FLAG_PAUSE_RX |
1788 I40E_AQ_PHY_FLAG_PAUSE_RX |
1789 I40E_AQ_PHY_FLAG_LOW_POWER;
1790 const uint8_t advt = I40E_LINK_SPEED_40GB |
1791 I40E_LINK_SPEED_25GB |
1792 I40E_LINK_SPEED_10GB |
1793 I40E_LINK_SPEED_1GB |
1794 I40E_LINK_SPEED_100MB;
1798 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1803 memset(&phy_conf, 0, sizeof(phy_conf));
1805 /* bits 0-2 use the values from get_phy_abilities_resp */
1807 abilities |= phy_ab.abilities & mask;
1809 /* update ablities and speed */
1810 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1811 phy_conf.link_speed = advt;
1813 phy_conf.link_speed = force_speed;
1815 phy_conf.abilities = abilities;
1817 /* use get_phy_abilities_resp value for the rest */
1818 phy_conf.phy_type = phy_ab.phy_type;
1819 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1820 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1821 phy_conf.eee_capability = phy_ab.eee_capability;
1822 phy_conf.eeer = phy_ab.eeer_val;
1823 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1825 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1826 phy_ab.abilities, phy_ab.link_speed);
1827 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1828 phy_conf.abilities, phy_conf.link_speed);
1830 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1834 return I40E_SUCCESS;
1838 i40e_apply_link_speed(struct rte_eth_dev *dev)
1841 uint8_t abilities = 0;
1842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843 struct rte_eth_conf *conf = &dev->data->dev_conf;
1845 speed = i40e_parse_link_speeds(conf->link_speeds);
1846 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1847 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1848 abilities |= I40E_AQ_PHY_AN_ENABLED;
1849 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1851 /* Skip changing speed on 40G interfaces, FW does not support */
1852 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1853 speed = I40E_LINK_SPEED_UNKNOWN;
1854 abilities |= I40E_AQ_PHY_AN_ENABLED;
1857 return i40e_phy_conf_link(hw, abilities, speed);
1861 i40e_dev_start(struct rte_eth_dev *dev)
1863 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865 struct i40e_vsi *main_vsi = pf->main_vsi;
1867 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1868 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1869 uint32_t intr_vector = 0;
1871 hw->adapter_stopped = 0;
1873 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1874 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1875 dev->data->port_id);
1879 rte_intr_disable(intr_handle);
1881 if ((rte_intr_cap_multiple(intr_handle) ||
1882 !RTE_ETH_DEV_SRIOV(dev).active) &&
1883 dev->data->dev_conf.intr_conf.rxq != 0) {
1884 intr_vector = dev->data->nb_rx_queues;
1885 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1890 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1891 intr_handle->intr_vec =
1892 rte_zmalloc("intr_vec",
1893 dev->data->nb_rx_queues * sizeof(int),
1895 if (!intr_handle->intr_vec) {
1897 "Failed to allocate %d rx_queues intr_vec\n",
1898 dev->data->nb_rx_queues);
1903 /* Initialize VSI */
1904 ret = i40e_dev_rxtx_init(pf);
1905 if (ret != I40E_SUCCESS) {
1906 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1910 /* Map queues with MSIX interrupt */
1911 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1912 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1913 i40e_vsi_queues_bind_intr(main_vsi);
1914 i40e_vsi_enable_queues_intr(main_vsi);
1916 /* Map VMDQ VSI queues with MSIX interrupt */
1917 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1918 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1919 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1920 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1923 /* enable FDIR MSIX interrupt */
1924 if (pf->fdir.fdir_vsi) {
1925 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1926 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1929 /* Enable all queues which have been configured */
1930 ret = i40e_dev_switch_queues(pf, TRUE);
1931 if (ret != I40E_SUCCESS) {
1932 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1936 /* Enable receiving broadcast packets */
1937 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1938 if (ret != I40E_SUCCESS)
1939 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1941 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1942 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1944 if (ret != I40E_SUCCESS)
1945 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1948 /* Apply link configure */
1949 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1950 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1951 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1952 ETH_LINK_SPEED_40G)) {
1953 PMD_DRV_LOG(ERR, "Invalid link setting");
1956 ret = i40e_apply_link_speed(dev);
1957 if (I40E_SUCCESS != ret) {
1958 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1962 if (!rte_intr_allow_others(intr_handle)) {
1963 rte_intr_callback_unregister(intr_handle,
1964 i40e_dev_interrupt_handler,
1966 /* configure and enable device interrupt */
1967 i40e_pf_config_irq0(hw, FALSE);
1968 i40e_pf_enable_irq0(hw);
1970 if (dev->data->dev_conf.intr_conf.lsc != 0)
1972 "lsc won't enable because of no intr multiplex\n");
1973 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1974 ret = i40e_aq_set_phy_int_mask(hw,
1975 ~(I40E_AQ_EVENT_LINK_UPDOWN |
1976 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1977 I40E_AQ_EVENT_MEDIA_NA), NULL);
1978 if (ret != I40E_SUCCESS)
1979 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1981 /* Call get_link_info aq commond to enable LSE */
1982 i40e_dev_link_update(dev, 0);
1985 /* enable uio intr after callback register */
1986 rte_intr_enable(intr_handle);
1988 i40e_filter_restore(pf);
1990 return I40E_SUCCESS;
1993 i40e_dev_switch_queues(pf, FALSE);
1994 i40e_dev_clear_queues(dev);
2000 i40e_dev_stop(struct rte_eth_dev *dev)
2002 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2003 struct i40e_vsi *main_vsi = pf->main_vsi;
2004 struct i40e_mirror_rule *p_mirror;
2005 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2006 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2009 /* Disable all queues */
2010 i40e_dev_switch_queues(pf, FALSE);
2012 /* un-map queues with interrupt registers */
2013 i40e_vsi_disable_queues_intr(main_vsi);
2014 i40e_vsi_queues_unbind_intr(main_vsi);
2016 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2017 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2018 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2021 if (pf->fdir.fdir_vsi) {
2022 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2023 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2025 /* Clear all queues and release memory */
2026 i40e_dev_clear_queues(dev);
2029 i40e_dev_set_link_down(dev);
2031 /* Remove all mirror rules */
2032 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2033 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2036 pf->nb_mirror_rule = 0;
2038 if (!rte_intr_allow_others(intr_handle))
2039 /* resume to the default handler */
2040 rte_intr_callback_register(intr_handle,
2041 i40e_dev_interrupt_handler,
2044 /* Clean datapath event and queue/vec mapping */
2045 rte_intr_efd_disable(intr_handle);
2046 if (intr_handle->intr_vec) {
2047 rte_free(intr_handle->intr_vec);
2048 intr_handle->intr_vec = NULL;
2053 i40e_dev_close(struct rte_eth_dev *dev)
2055 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2056 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2058 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2062 PMD_INIT_FUNC_TRACE();
2065 hw->adapter_stopped = 1;
2066 i40e_dev_free_queues(dev);
2068 /* Disable interrupt */
2069 i40e_pf_disable_irq0(hw);
2070 rte_intr_disable(intr_handle);
2072 /* shutdown and destroy the HMC */
2073 i40e_shutdown_lan_hmc(hw);
2075 /* release all the existing VSIs and VEBs */
2076 i40e_fdir_teardown(pf);
2077 i40e_vsi_release(pf->main_vsi);
2079 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2080 i40e_vsi_release(pf->vmdq[i].vsi);
2081 pf->vmdq[i].vsi = NULL;
2087 /* shutdown the adminq */
2088 i40e_aq_queue_shutdown(hw, true);
2089 i40e_shutdown_adminq(hw);
2091 i40e_res_pool_destroy(&pf->qp_pool);
2092 i40e_res_pool_destroy(&pf->msix_pool);
2094 /* force a PF reset to clean anything leftover */
2095 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2096 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2097 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2098 I40E_WRITE_FLUSH(hw);
2102 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2104 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2105 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106 struct i40e_vsi *vsi = pf->main_vsi;
2109 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2111 if (status != I40E_SUCCESS)
2112 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2114 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2116 if (status != I40E_SUCCESS)
2117 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2122 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2124 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2125 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126 struct i40e_vsi *vsi = pf->main_vsi;
2129 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2131 if (status != I40E_SUCCESS)
2132 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2134 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2136 if (status != I40E_SUCCESS)
2137 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2141 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2143 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2144 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145 struct i40e_vsi *vsi = pf->main_vsi;
2148 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2149 if (ret != I40E_SUCCESS)
2150 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2154 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2156 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2157 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158 struct i40e_vsi *vsi = pf->main_vsi;
2161 if (dev->data->promiscuous == 1)
2162 return; /* must remain in all_multicast mode */
2164 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2165 vsi->seid, FALSE, NULL);
2166 if (ret != I40E_SUCCESS)
2167 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2171 * Set device link up.
2174 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2176 /* re-apply link speed setting */
2177 return i40e_apply_link_speed(dev);
2181 * Set device link down.
2184 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2186 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2187 uint8_t abilities = 0;
2188 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2191 return i40e_phy_conf_link(hw, abilities, speed);
2195 i40e_dev_link_update(struct rte_eth_dev *dev,
2196 int wait_to_complete)
2198 #define CHECK_INTERVAL 100 /* 100ms */
2199 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2200 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201 struct i40e_link_status link_status;
2202 struct rte_eth_link link, old;
2204 unsigned rep_cnt = MAX_REPEAT_TIME;
2205 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2207 memset(&link, 0, sizeof(link));
2208 memset(&old, 0, sizeof(old));
2209 memset(&link_status, 0, sizeof(link_status));
2210 rte_i40e_dev_atomic_read_link_status(dev, &old);
2213 /* Get link status information from hardware */
2214 status = i40e_aq_get_link_info(hw, enable_lse,
2215 &link_status, NULL);
2216 if (status != I40E_SUCCESS) {
2217 link.link_speed = ETH_SPEED_NUM_100M;
2218 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2219 PMD_DRV_LOG(ERR, "Failed to get link info");
2223 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2224 if (!wait_to_complete)
2227 rte_delay_ms(CHECK_INTERVAL);
2228 } while (!link.link_status && rep_cnt--);
2230 if (!link.link_status)
2233 /* i40e uses full duplex only */
2234 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2236 /* Parse the link status */
2237 switch (link_status.link_speed) {
2238 case I40E_LINK_SPEED_100MB:
2239 link.link_speed = ETH_SPEED_NUM_100M;
2241 case I40E_LINK_SPEED_1GB:
2242 link.link_speed = ETH_SPEED_NUM_1G;
2244 case I40E_LINK_SPEED_10GB:
2245 link.link_speed = ETH_SPEED_NUM_10G;
2247 case I40E_LINK_SPEED_20GB:
2248 link.link_speed = ETH_SPEED_NUM_20G;
2250 case I40E_LINK_SPEED_25GB:
2251 link.link_speed = ETH_SPEED_NUM_25G;
2253 case I40E_LINK_SPEED_40GB:
2254 link.link_speed = ETH_SPEED_NUM_40G;
2257 link.link_speed = ETH_SPEED_NUM_100M;
2261 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2262 ETH_LINK_SPEED_FIXED);
2265 rte_i40e_dev_atomic_write_link_status(dev, &link);
2266 if (link.link_status == old.link_status)
2272 /* Get all the statistics of a VSI */
2274 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2276 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2277 struct i40e_eth_stats *nes = &vsi->eth_stats;
2278 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2279 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2281 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2282 vsi->offset_loaded, &oes->rx_bytes,
2284 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2285 vsi->offset_loaded, &oes->rx_unicast,
2287 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2288 vsi->offset_loaded, &oes->rx_multicast,
2289 &nes->rx_multicast);
2290 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2291 vsi->offset_loaded, &oes->rx_broadcast,
2292 &nes->rx_broadcast);
2293 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2294 &oes->rx_discards, &nes->rx_discards);
2295 /* GLV_REPC not supported */
2296 /* GLV_RMPC not supported */
2297 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2298 &oes->rx_unknown_protocol,
2299 &nes->rx_unknown_protocol);
2300 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2301 vsi->offset_loaded, &oes->tx_bytes,
2303 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2304 vsi->offset_loaded, &oes->tx_unicast,
2306 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2307 vsi->offset_loaded, &oes->tx_multicast,
2308 &nes->tx_multicast);
2309 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2310 vsi->offset_loaded, &oes->tx_broadcast,
2311 &nes->tx_broadcast);
2312 /* GLV_TDPC not supported */
2313 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2314 &oes->tx_errors, &nes->tx_errors);
2315 vsi->offset_loaded = true;
2317 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2319 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2320 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2321 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2322 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2323 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2324 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2325 nes->rx_unknown_protocol);
2326 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2327 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2328 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2329 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2330 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2331 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2332 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2337 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2340 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2341 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2343 /* Get statistics of struct i40e_eth_stats */
2344 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2345 I40E_GLPRT_GORCL(hw->port),
2346 pf->offset_loaded, &os->eth.rx_bytes,
2348 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2349 I40E_GLPRT_UPRCL(hw->port),
2350 pf->offset_loaded, &os->eth.rx_unicast,
2351 &ns->eth.rx_unicast);
2352 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2353 I40E_GLPRT_MPRCL(hw->port),
2354 pf->offset_loaded, &os->eth.rx_multicast,
2355 &ns->eth.rx_multicast);
2356 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2357 I40E_GLPRT_BPRCL(hw->port),
2358 pf->offset_loaded, &os->eth.rx_broadcast,
2359 &ns->eth.rx_broadcast);
2360 /* Workaround: CRC size should not be included in byte statistics,
2361 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2363 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2364 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2366 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2367 pf->offset_loaded, &os->eth.rx_discards,
2368 &ns->eth.rx_discards);
2369 /* GLPRT_REPC not supported */
2370 /* GLPRT_RMPC not supported */
2371 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2373 &os->eth.rx_unknown_protocol,
2374 &ns->eth.rx_unknown_protocol);
2375 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2376 I40E_GLPRT_GOTCL(hw->port),
2377 pf->offset_loaded, &os->eth.tx_bytes,
2379 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2380 I40E_GLPRT_UPTCL(hw->port),
2381 pf->offset_loaded, &os->eth.tx_unicast,
2382 &ns->eth.tx_unicast);
2383 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2384 I40E_GLPRT_MPTCL(hw->port),
2385 pf->offset_loaded, &os->eth.tx_multicast,
2386 &ns->eth.tx_multicast);
2387 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2388 I40E_GLPRT_BPTCL(hw->port),
2389 pf->offset_loaded, &os->eth.tx_broadcast,
2390 &ns->eth.tx_broadcast);
2391 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2392 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2393 /* GLPRT_TEPC not supported */
2395 /* additional port specific stats */
2396 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2397 pf->offset_loaded, &os->tx_dropped_link_down,
2398 &ns->tx_dropped_link_down);
2399 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2400 pf->offset_loaded, &os->crc_errors,
2402 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2403 pf->offset_loaded, &os->illegal_bytes,
2404 &ns->illegal_bytes);
2405 /* GLPRT_ERRBC not supported */
2406 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2407 pf->offset_loaded, &os->mac_local_faults,
2408 &ns->mac_local_faults);
2409 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2410 pf->offset_loaded, &os->mac_remote_faults,
2411 &ns->mac_remote_faults);
2412 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2413 pf->offset_loaded, &os->rx_length_errors,
2414 &ns->rx_length_errors);
2415 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2416 pf->offset_loaded, &os->link_xon_rx,
2418 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2419 pf->offset_loaded, &os->link_xoff_rx,
2421 for (i = 0; i < 8; i++) {
2422 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2424 &os->priority_xon_rx[i],
2425 &ns->priority_xon_rx[i]);
2426 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2428 &os->priority_xoff_rx[i],
2429 &ns->priority_xoff_rx[i]);
2431 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2432 pf->offset_loaded, &os->link_xon_tx,
2434 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2435 pf->offset_loaded, &os->link_xoff_tx,
2437 for (i = 0; i < 8; i++) {
2438 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2440 &os->priority_xon_tx[i],
2441 &ns->priority_xon_tx[i]);
2442 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2444 &os->priority_xoff_tx[i],
2445 &ns->priority_xoff_tx[i]);
2446 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2448 &os->priority_xon_2_xoff[i],
2449 &ns->priority_xon_2_xoff[i]);
2451 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2452 I40E_GLPRT_PRC64L(hw->port),
2453 pf->offset_loaded, &os->rx_size_64,
2455 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2456 I40E_GLPRT_PRC127L(hw->port),
2457 pf->offset_loaded, &os->rx_size_127,
2459 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2460 I40E_GLPRT_PRC255L(hw->port),
2461 pf->offset_loaded, &os->rx_size_255,
2463 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2464 I40E_GLPRT_PRC511L(hw->port),
2465 pf->offset_loaded, &os->rx_size_511,
2467 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2468 I40E_GLPRT_PRC1023L(hw->port),
2469 pf->offset_loaded, &os->rx_size_1023,
2471 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2472 I40E_GLPRT_PRC1522L(hw->port),
2473 pf->offset_loaded, &os->rx_size_1522,
2475 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2476 I40E_GLPRT_PRC9522L(hw->port),
2477 pf->offset_loaded, &os->rx_size_big,
2479 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2480 pf->offset_loaded, &os->rx_undersize,
2482 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2483 pf->offset_loaded, &os->rx_fragments,
2485 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2486 pf->offset_loaded, &os->rx_oversize,
2488 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2489 pf->offset_loaded, &os->rx_jabber,
2491 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2492 I40E_GLPRT_PTC64L(hw->port),
2493 pf->offset_loaded, &os->tx_size_64,
2495 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2496 I40E_GLPRT_PTC127L(hw->port),
2497 pf->offset_loaded, &os->tx_size_127,
2499 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2500 I40E_GLPRT_PTC255L(hw->port),
2501 pf->offset_loaded, &os->tx_size_255,
2503 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2504 I40E_GLPRT_PTC511L(hw->port),
2505 pf->offset_loaded, &os->tx_size_511,
2507 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2508 I40E_GLPRT_PTC1023L(hw->port),
2509 pf->offset_loaded, &os->tx_size_1023,
2511 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2512 I40E_GLPRT_PTC1522L(hw->port),
2513 pf->offset_loaded, &os->tx_size_1522,
2515 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2516 I40E_GLPRT_PTC9522L(hw->port),
2517 pf->offset_loaded, &os->tx_size_big,
2519 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2521 &os->fd_sb_match, &ns->fd_sb_match);
2522 /* GLPRT_MSPDC not supported */
2523 /* GLPRT_XEC not supported */
2525 pf->offset_loaded = true;
2528 i40e_update_vsi_stats(pf->main_vsi);
2531 /* Get all statistics of a port */
2533 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2535 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2536 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2540 /* call read registers - updates values, now write them to struct */
2541 i40e_read_stats_registers(pf, hw);
2543 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2544 pf->main_vsi->eth_stats.rx_multicast +
2545 pf->main_vsi->eth_stats.rx_broadcast -
2546 pf->main_vsi->eth_stats.rx_discards;
2547 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2548 pf->main_vsi->eth_stats.tx_multicast +
2549 pf->main_vsi->eth_stats.tx_broadcast;
2550 stats->ibytes = ns->eth.rx_bytes;
2551 stats->obytes = ns->eth.tx_bytes;
2552 stats->oerrors = ns->eth.tx_errors +
2553 pf->main_vsi->eth_stats.tx_errors;
2556 stats->imissed = ns->eth.rx_discards +
2557 pf->main_vsi->eth_stats.rx_discards;
2558 stats->ierrors = ns->crc_errors +
2559 ns->rx_length_errors + ns->rx_undersize +
2560 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2562 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2563 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2564 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2565 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2566 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2567 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2568 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2569 ns->eth.rx_unknown_protocol);
2570 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2571 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2572 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2573 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2574 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2575 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2577 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2578 ns->tx_dropped_link_down);
2579 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2580 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2582 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2583 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2584 ns->mac_local_faults);
2585 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2586 ns->mac_remote_faults);
2587 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2588 ns->rx_length_errors);
2589 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2590 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2591 for (i = 0; i < 8; i++) {
2592 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2593 i, ns->priority_xon_rx[i]);
2594 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2595 i, ns->priority_xoff_rx[i]);
2597 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2598 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2599 for (i = 0; i < 8; i++) {
2600 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2601 i, ns->priority_xon_tx[i]);
2602 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2603 i, ns->priority_xoff_tx[i]);
2604 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2605 i, ns->priority_xon_2_xoff[i]);
2607 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2608 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2609 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2610 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2611 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2612 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2613 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2614 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2615 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2616 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2617 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2618 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2619 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2620 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2621 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2622 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2623 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2624 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2625 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2626 ns->mac_short_packet_dropped);
2627 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2628 ns->checksum_error);
2629 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2630 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2633 /* Reset the statistics */
2635 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2637 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2638 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640 /* Mark PF and VSI stats to update the offset, aka "reset" */
2641 pf->offset_loaded = false;
2643 pf->main_vsi->offset_loaded = false;
2645 /* read the stats, reading current register values into offset */
2646 i40e_read_stats_registers(pf, hw);
2650 i40e_xstats_calc_num(void)
2652 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2653 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2654 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2657 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2658 struct rte_eth_xstat_name *xstats_names,
2659 __rte_unused unsigned limit)
2664 if (xstats_names == NULL)
2665 return i40e_xstats_calc_num();
2667 /* Note: limit checked in rte_eth_xstats_names() */
2669 /* Get stats from i40e_eth_stats struct */
2670 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2671 snprintf(xstats_names[count].name,
2672 sizeof(xstats_names[count].name),
2673 "%s", rte_i40e_stats_strings[i].name);
2677 /* Get individiual stats from i40e_hw_port struct */
2678 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2679 snprintf(xstats_names[count].name,
2680 sizeof(xstats_names[count].name),
2681 "%s", rte_i40e_hw_port_strings[i].name);
2685 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2686 for (prio = 0; prio < 8; prio++) {
2687 snprintf(xstats_names[count].name,
2688 sizeof(xstats_names[count].name),
2689 "rx_priority%u_%s", prio,
2690 rte_i40e_rxq_prio_strings[i].name);
2695 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2696 for (prio = 0; prio < 8; prio++) {
2697 snprintf(xstats_names[count].name,
2698 sizeof(xstats_names[count].name),
2699 "tx_priority%u_%s", prio,
2700 rte_i40e_txq_prio_strings[i].name);
2708 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2711 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2712 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713 unsigned i, count, prio;
2714 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2716 count = i40e_xstats_calc_num();
2720 i40e_read_stats_registers(pf, hw);
2727 /* Get stats from i40e_eth_stats struct */
2728 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2729 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2730 rte_i40e_stats_strings[i].offset);
2731 xstats[count].id = count;
2735 /* Get individiual stats from i40e_hw_port struct */
2736 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2737 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2738 rte_i40e_hw_port_strings[i].offset);
2739 xstats[count].id = count;
2743 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2744 for (prio = 0; prio < 8; prio++) {
2745 xstats[count].value =
2746 *(uint64_t *)(((char *)hw_stats) +
2747 rte_i40e_rxq_prio_strings[i].offset +
2748 (sizeof(uint64_t) * prio));
2749 xstats[count].id = count;
2754 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2755 for (prio = 0; prio < 8; prio++) {
2756 xstats[count].value =
2757 *(uint64_t *)(((char *)hw_stats) +
2758 rte_i40e_txq_prio_strings[i].offset +
2759 (sizeof(uint64_t) * prio));
2760 xstats[count].id = count;
2769 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2770 __rte_unused uint16_t queue_id,
2771 __rte_unused uint8_t stat_idx,
2772 __rte_unused uint8_t is_rx)
2774 PMD_INIT_FUNC_TRACE();
2780 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2782 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788 full_ver = hw->nvm.oem_ver;
2789 ver = (u8)(full_ver >> 24);
2790 build = (u16)((full_ver >> 8) & 0xffff);
2791 patch = (u8)(full_ver & 0xff);
2793 ret = snprintf(fw_version, fw_size,
2794 "%d.%d%d 0x%08x %d.%d.%d",
2795 ((hw->nvm.version >> 12) & 0xf),
2796 ((hw->nvm.version >> 4) & 0xff),
2797 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2800 ret += 1; /* add the size of '\0' */
2801 if (fw_size < (u32)ret)
2808 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812 struct i40e_vsi *vsi = pf->main_vsi;
2813 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2815 dev_info->pci_dev = pci_dev;
2816 dev_info->max_rx_queues = vsi->nb_qps;
2817 dev_info->max_tx_queues = vsi->nb_qps;
2818 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2819 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2820 dev_info->max_mac_addrs = vsi->max_macaddrs;
2821 dev_info->max_vfs = pci_dev->max_vfs;
2822 dev_info->rx_offload_capa =
2823 DEV_RX_OFFLOAD_VLAN_STRIP |
2824 DEV_RX_OFFLOAD_QINQ_STRIP |
2825 DEV_RX_OFFLOAD_IPV4_CKSUM |
2826 DEV_RX_OFFLOAD_UDP_CKSUM |
2827 DEV_RX_OFFLOAD_TCP_CKSUM;
2828 dev_info->tx_offload_capa =
2829 DEV_TX_OFFLOAD_VLAN_INSERT |
2830 DEV_TX_OFFLOAD_QINQ_INSERT |
2831 DEV_TX_OFFLOAD_IPV4_CKSUM |
2832 DEV_TX_OFFLOAD_UDP_CKSUM |
2833 DEV_TX_OFFLOAD_TCP_CKSUM |
2834 DEV_TX_OFFLOAD_SCTP_CKSUM |
2835 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2836 DEV_TX_OFFLOAD_TCP_TSO |
2837 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2838 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2839 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2840 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2841 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2843 dev_info->reta_size = pf->hash_lut_size;
2844 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2846 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2848 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2849 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2850 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2852 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2856 dev_info->default_txconf = (struct rte_eth_txconf) {
2858 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2859 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2860 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2862 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2863 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2864 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2865 ETH_TXQ_FLAGS_NOOFFLOADS,
2868 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2869 .nb_max = I40E_MAX_RING_DESC,
2870 .nb_min = I40E_MIN_RING_DESC,
2871 .nb_align = I40E_ALIGN_RING_DESC,
2874 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2875 .nb_max = I40E_MAX_RING_DESC,
2876 .nb_min = I40E_MIN_RING_DESC,
2877 .nb_align = I40E_ALIGN_RING_DESC,
2878 .nb_seg_max = I40E_TX_MAX_SEG,
2879 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2882 if (pf->flags & I40E_FLAG_VMDQ) {
2883 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2884 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2885 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2886 pf->max_nb_vmdq_vsi;
2887 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2888 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2889 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2892 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2894 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2895 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2897 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2900 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2904 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2906 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2907 struct i40e_vsi *vsi = pf->main_vsi;
2908 PMD_INIT_FUNC_TRACE();
2911 return i40e_vsi_add_vlan(vsi, vlan_id);
2913 return i40e_vsi_delete_vlan(vsi, vlan_id);
2917 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2918 enum rte_vlan_type vlan_type,
2921 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922 uint64_t reg_r = 0, reg_w = 0;
2923 uint16_t reg_id = 0;
2925 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2927 switch (vlan_type) {
2928 case ETH_VLAN_TYPE_OUTER:
2934 case ETH_VLAN_TYPE_INNER:
2940 "Unsupported vlan type in single vlan.\n");
2946 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2949 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2951 if (ret != I40E_SUCCESS) {
2953 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2959 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2962 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2963 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2964 if (reg_r == reg_w) {
2966 PMD_DRV_LOG(DEBUG, "No need to write");
2970 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2972 if (ret != I40E_SUCCESS) {
2975 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2980 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2987 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2989 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2990 struct i40e_vsi *vsi = pf->main_vsi;
2992 if (mask & ETH_VLAN_FILTER_MASK) {
2993 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2994 i40e_vsi_config_vlan_filter(vsi, TRUE);
2996 i40e_vsi_config_vlan_filter(vsi, FALSE);
2999 if (mask & ETH_VLAN_STRIP_MASK) {
3000 /* Enable or disable VLAN stripping */
3001 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3002 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3004 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3007 if (mask & ETH_VLAN_EXTEND_MASK) {
3008 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3009 i40e_vsi_config_double_vlan(vsi, TRUE);
3010 /* Set global registers with default ether type value */
3011 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3013 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3017 i40e_vsi_config_double_vlan(vsi, FALSE);
3022 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3023 __rte_unused uint16_t queue,
3024 __rte_unused int on)
3026 PMD_INIT_FUNC_TRACE();
3030 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3032 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3033 struct i40e_vsi *vsi = pf->main_vsi;
3034 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3035 struct i40e_vsi_vlan_pvid_info info;
3037 memset(&info, 0, sizeof(info));
3040 info.config.pvid = pvid;
3042 info.config.reject.tagged =
3043 data->dev_conf.txmode.hw_vlan_reject_tagged;
3044 info.config.reject.untagged =
3045 data->dev_conf.txmode.hw_vlan_reject_untagged;
3048 return i40e_vsi_vlan_pvid_set(vsi, &info);
3052 i40e_dev_led_on(struct rte_eth_dev *dev)
3054 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3055 uint32_t mode = i40e_led_get(hw);
3058 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3064 i40e_dev_led_off(struct rte_eth_dev *dev)
3066 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067 uint32_t mode = i40e_led_get(hw);
3070 i40e_led_set(hw, 0, false);
3076 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3078 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3081 fc_conf->pause_time = pf->fc_conf.pause_time;
3082 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3083 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3085 /* Return current mode according to actual setting*/
3086 switch (hw->fc.current_mode) {
3088 fc_conf->mode = RTE_FC_FULL;
3090 case I40E_FC_TX_PAUSE:
3091 fc_conf->mode = RTE_FC_TX_PAUSE;
3093 case I40E_FC_RX_PAUSE:
3094 fc_conf->mode = RTE_FC_RX_PAUSE;
3098 fc_conf->mode = RTE_FC_NONE;
3105 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3107 uint32_t mflcn_reg, fctrl_reg, reg;
3108 uint32_t max_high_water;
3109 uint8_t i, aq_failure;
3113 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3114 [RTE_FC_NONE] = I40E_FC_NONE,
3115 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3116 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3117 [RTE_FC_FULL] = I40E_FC_FULL
3120 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3122 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3123 if ((fc_conf->high_water > max_high_water) ||
3124 (fc_conf->high_water < fc_conf->low_water)) {
3126 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3131 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3133 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3135 pf->fc_conf.pause_time = fc_conf->pause_time;
3136 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3137 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3139 PMD_INIT_FUNC_TRACE();
3141 /* All the link flow control related enable/disable register
3142 * configuration is handle by the F/W
3144 err = i40e_set_fc(hw, &aq_failure, true);
3148 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3149 /* Configure flow control refresh threshold,
3150 * the value for stat_tx_pause_refresh_timer[8]
3151 * is used for global pause operation.
3155 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3156 pf->fc_conf.pause_time);
3158 /* configure the timer value included in transmitted pause
3160 * the value for stat_tx_pause_quanta[8] is used for global
3163 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3164 pf->fc_conf.pause_time);
3166 fctrl_reg = I40E_READ_REG(hw,
3167 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3169 if (fc_conf->mac_ctrl_frame_fwd != 0)
3170 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3172 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3174 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3177 /* Configure pause time (2 TCs per register) */
3178 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3179 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3180 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3182 /* Configure flow control refresh threshold value */
3183 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3184 pf->fc_conf.pause_time / 2);
3186 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3188 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3189 *depending on configuration
3191 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3192 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3193 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3195 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3196 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3199 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3202 /* config the water marker both based on the packets and bytes */
3203 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3204 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3205 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3206 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3207 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3208 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3209 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3210 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3212 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3213 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3216 I40E_WRITE_FLUSH(hw);
3222 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3223 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3225 PMD_INIT_FUNC_TRACE();
3230 /* Add a MAC address, and update filters */
3232 i40e_macaddr_add(struct rte_eth_dev *dev,
3233 struct ether_addr *mac_addr,
3234 __rte_unused uint32_t index,
3237 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3238 struct i40e_mac_filter_info mac_filter;
3239 struct i40e_vsi *vsi;
3242 /* If VMDQ not enabled or configured, return */
3243 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3244 !pf->nb_cfg_vmdq_vsi)) {
3245 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3246 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3251 if (pool > pf->nb_cfg_vmdq_vsi) {
3252 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3253 pool, pf->nb_cfg_vmdq_vsi);
3257 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3258 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3259 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3261 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3266 vsi = pf->vmdq[pool - 1].vsi;
3268 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3269 if (ret != I40E_SUCCESS) {
3270 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3275 /* Remove a MAC address, and update filters */
3277 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3279 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3280 struct i40e_vsi *vsi;
3281 struct rte_eth_dev_data *data = dev->data;
3282 struct ether_addr *macaddr;
3287 macaddr = &(data->mac_addrs[index]);
3289 pool_sel = dev->data->mac_pool_sel[index];
3291 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3292 if (pool_sel & (1ULL << i)) {
3296 /* No VMDQ pool enabled or configured */
3297 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3298 (i > pf->nb_cfg_vmdq_vsi)) {
3300 "No VMDQ pool enabled/configured");
3303 vsi = pf->vmdq[i - 1].vsi;
3305 ret = i40e_vsi_delete_mac(vsi, macaddr);
3308 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3315 /* Set perfect match or hash match of MAC and VLAN for a VF */
3317 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3318 struct rte_eth_mac_filter *filter,
3322 struct i40e_mac_filter_info mac_filter;
3323 struct ether_addr old_mac;
3324 struct ether_addr *new_mac;
3325 struct i40e_pf_vf *vf = NULL;
3330 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3333 hw = I40E_PF_TO_HW(pf);
3335 if (filter == NULL) {
3336 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3340 new_mac = &filter->mac_addr;
3342 if (is_zero_ether_addr(new_mac)) {
3343 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3347 vf_id = filter->dst_id;
3349 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3350 PMD_DRV_LOG(ERR, "Invalid argument.");
3353 vf = &pf->vfs[vf_id];
3355 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3356 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3361 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3362 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3364 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3367 mac_filter.filter_type = filter->filter_type;
3368 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3369 if (ret != I40E_SUCCESS) {
3370 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3373 ether_addr_copy(new_mac, &pf->dev_addr);
3375 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3377 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3378 if (ret != I40E_SUCCESS) {
3379 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3383 /* Clear device address as it has been removed */
3384 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3385 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3391 /* MAC filter handle */
3393 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3397 struct rte_eth_mac_filter *filter;
3398 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3399 int ret = I40E_NOT_SUPPORTED;
3401 filter = (struct rte_eth_mac_filter *)(arg);
3403 switch (filter_op) {
3404 case RTE_ETH_FILTER_NOP:
3407 case RTE_ETH_FILTER_ADD:
3408 i40e_pf_disable_irq0(hw);
3410 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3411 i40e_pf_enable_irq0(hw);
3413 case RTE_ETH_FILTER_DELETE:
3414 i40e_pf_disable_irq0(hw);
3416 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3417 i40e_pf_enable_irq0(hw);
3420 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3421 ret = I40E_ERR_PARAM;
3429 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3431 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3432 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3438 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3439 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3442 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3446 uint32_t *lut_dw = (uint32_t *)lut;
3447 uint16_t i, lut_size_dw = lut_size / 4;
3449 for (i = 0; i < lut_size_dw; i++)
3450 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3457 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3466 pf = I40E_VSI_TO_PF(vsi);
3467 hw = I40E_VSI_TO_HW(vsi);
3469 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3470 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3473 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3477 uint32_t *lut_dw = (uint32_t *)lut;
3478 uint16_t i, lut_size_dw = lut_size / 4;
3480 for (i = 0; i < lut_size_dw; i++)
3481 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3482 I40E_WRITE_FLUSH(hw);
3489 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3490 struct rte_eth_rss_reta_entry64 *reta_conf,
3493 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3494 uint16_t i, lut_size = pf->hash_lut_size;
3495 uint16_t idx, shift;
3499 if (reta_size != lut_size ||
3500 reta_size > ETH_RSS_RETA_SIZE_512) {
3502 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)\n",
3503 reta_size, lut_size);
3507 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3509 PMD_DRV_LOG(ERR, "No memory can be allocated");
3512 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3515 for (i = 0; i < reta_size; i++) {
3516 idx = i / RTE_RETA_GROUP_SIZE;
3517 shift = i % RTE_RETA_GROUP_SIZE;
3518 if (reta_conf[idx].mask & (1ULL << shift))
3519 lut[i] = reta_conf[idx].reta[shift];
3521 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3530 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3531 struct rte_eth_rss_reta_entry64 *reta_conf,
3534 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3535 uint16_t i, lut_size = pf->hash_lut_size;
3536 uint16_t idx, shift;
3540 if (reta_size != lut_size ||
3541 reta_size > ETH_RSS_RETA_SIZE_512) {
3543 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)\n",
3544 reta_size, lut_size);
3548 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3550 PMD_DRV_LOG(ERR, "No memory can be allocated");
3554 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3557 for (i = 0; i < reta_size; i++) {
3558 idx = i / RTE_RETA_GROUP_SIZE;
3559 shift = i % RTE_RETA_GROUP_SIZE;
3560 if (reta_conf[idx].mask & (1ULL << shift))
3561 reta_conf[idx].reta[shift] = lut[i];
3571 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3572 * @hw: pointer to the HW structure
3573 * @mem: pointer to mem struct to fill out
3574 * @size: size of memory requested
3575 * @alignment: what to align the allocation to
3577 enum i40e_status_code
3578 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3579 struct i40e_dma_mem *mem,
3583 const struct rte_memzone *mz = NULL;
3584 char z_name[RTE_MEMZONE_NAMESIZE];
3587 return I40E_ERR_PARAM;
3589 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3590 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3591 alignment, RTE_PGSIZE_2M);
3593 return I40E_ERR_NO_MEMORY;
3597 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3598 mem->zone = (const void *)mz;
3600 "memzone %s allocated with physical address: %"PRIu64,
3603 return I40E_SUCCESS;
3607 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3608 * @hw: pointer to the HW structure
3609 * @mem: ptr to mem struct to free
3611 enum i40e_status_code
3612 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3613 struct i40e_dma_mem *mem)
3616 return I40E_ERR_PARAM;
3619 "memzone %s to be freed with physical address: %"PRIu64,
3620 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3621 rte_memzone_free((const struct rte_memzone *)mem->zone);
3626 return I40E_SUCCESS;
3630 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3631 * @hw: pointer to the HW structure
3632 * @mem: pointer to mem struct to fill out
3633 * @size: size of memory requested
3635 enum i40e_status_code
3636 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3637 struct i40e_virt_mem *mem,
3641 return I40E_ERR_PARAM;
3644 mem->va = rte_zmalloc("i40e", size, 0);
3647 return I40E_SUCCESS;
3649 return I40E_ERR_NO_MEMORY;
3653 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3654 * @hw: pointer to the HW structure
3655 * @mem: pointer to mem struct to free
3657 enum i40e_status_code
3658 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3659 struct i40e_virt_mem *mem)
3662 return I40E_ERR_PARAM;
3667 return I40E_SUCCESS;
3671 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3673 rte_spinlock_init(&sp->spinlock);
3677 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3679 rte_spinlock_lock(&sp->spinlock);
3683 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3685 rte_spinlock_unlock(&sp->spinlock);
3689 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3695 * Get the hardware capabilities, which will be parsed
3696 * and saved into struct i40e_hw.
3699 i40e_get_cap(struct i40e_hw *hw)
3701 struct i40e_aqc_list_capabilities_element_resp *buf;
3702 uint16_t len, size = 0;
3705 /* Calculate a huge enough buff for saving response data temporarily */
3706 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3707 I40E_MAX_CAP_ELE_NUM;
3708 buf = rte_zmalloc("i40e", len, 0);
3710 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3711 return I40E_ERR_NO_MEMORY;
3714 /* Get, parse the capabilities and save it to hw */
3715 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3716 i40e_aqc_opc_list_func_capabilities, NULL);
3717 if (ret != I40E_SUCCESS)
3718 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3720 /* Free the temporary buffer after being used */
3727 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3729 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3730 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3731 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3732 uint16_t qp_count = 0, vsi_count = 0;
3734 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3735 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3738 /* Add the parameter init for LFC */
3739 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3740 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3741 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3743 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3744 pf->max_num_vsi = hw->func_caps.num_vsis;
3745 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3746 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3747 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3749 /* FDir queue/VSI allocation */
3750 pf->fdir_qp_offset = 0;
3751 if (hw->func_caps.fd) {
3752 pf->flags |= I40E_FLAG_FDIR;
3753 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3755 pf->fdir_nb_qps = 0;
3757 qp_count += pf->fdir_nb_qps;
3760 /* LAN queue/VSI allocation */
3761 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3762 if (!hw->func_caps.rss) {
3765 pf->flags |= I40E_FLAG_RSS;
3766 if (hw->mac.type == I40E_MAC_X722)
3767 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3768 pf->lan_nb_qps = pf->lan_nb_qp_max;
3770 qp_count += pf->lan_nb_qps;
3773 /* VF queue/VSI allocation */
3774 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3775 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3776 pf->flags |= I40E_FLAG_SRIOV;
3777 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3778 pf->vf_num = pci_dev->max_vfs;
3780 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3781 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3786 qp_count += pf->vf_nb_qps * pf->vf_num;
3787 vsi_count += pf->vf_num;
3789 /* VMDq queue/VSI allocation */
3790 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3791 pf->vmdq_nb_qps = 0;
3792 pf->max_nb_vmdq_vsi = 0;
3793 if (hw->func_caps.vmdq) {
3794 if (qp_count < hw->func_caps.num_tx_qp &&
3795 vsi_count < hw->func_caps.num_vsis) {
3796 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3797 qp_count) / pf->vmdq_nb_qp_max;
3799 /* Limit the maximum number of VMDq vsi to the maximum
3800 * ethdev can support
3802 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3803 hw->func_caps.num_vsis - vsi_count);
3804 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3806 if (pf->max_nb_vmdq_vsi) {
3807 pf->flags |= I40E_FLAG_VMDQ;
3808 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3810 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3811 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3812 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3815 "No enough queues left for VMDq");
3818 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3821 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3822 vsi_count += pf->max_nb_vmdq_vsi;
3824 if (hw->func_caps.dcb)
3825 pf->flags |= I40E_FLAG_DCB;
3827 if (qp_count > hw->func_caps.num_tx_qp) {
3829 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3830 qp_count, hw->func_caps.num_tx_qp);
3833 if (vsi_count > hw->func_caps.num_vsis) {
3835 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3836 vsi_count, hw->func_caps.num_vsis);
3844 i40e_pf_get_switch_config(struct i40e_pf *pf)
3846 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3847 struct i40e_aqc_get_switch_config_resp *switch_config;
3848 struct i40e_aqc_switch_config_element_resp *element;
3849 uint16_t start_seid = 0, num_reported;
3852 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3853 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3854 if (!switch_config) {
3855 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3859 /* Get the switch configurations */
3860 ret = i40e_aq_get_switch_config(hw, switch_config,
3861 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3862 if (ret != I40E_SUCCESS) {
3863 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3866 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3867 if (num_reported != 1) { /* The number should be 1 */
3868 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3872 /* Parse the switch configuration elements */
3873 element = &(switch_config->element[0]);
3874 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3875 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3876 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3878 PMD_DRV_LOG(INFO, "Unknown element type");
3881 rte_free(switch_config);
3887 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3890 struct pool_entry *entry;
3892 if (pool == NULL || num == 0)
3895 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3896 if (entry == NULL) {
3897 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3901 /* queue heap initialize */
3902 pool->num_free = num;
3903 pool->num_alloc = 0;
3905 LIST_INIT(&pool->alloc_list);
3906 LIST_INIT(&pool->free_list);
3908 /* Initialize element */
3912 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3917 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3919 struct pool_entry *entry, *next_entry;
3924 for (entry = LIST_FIRST(&pool->alloc_list);
3925 entry && (next_entry = LIST_NEXT(entry, next), 1);
3926 entry = next_entry) {
3927 LIST_REMOVE(entry, next);
3931 for (entry = LIST_FIRST(&pool->free_list);
3932 entry && (next_entry = LIST_NEXT(entry, next), 1);
3933 entry = next_entry) {
3934 LIST_REMOVE(entry, next);
3939 pool->num_alloc = 0;
3941 LIST_INIT(&pool->alloc_list);
3942 LIST_INIT(&pool->free_list);
3946 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3949 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3950 uint32_t pool_offset;
3954 PMD_DRV_LOG(ERR, "Invalid parameter");
3958 pool_offset = base - pool->base;
3959 /* Lookup in alloc list */
3960 LIST_FOREACH(entry, &pool->alloc_list, next) {
3961 if (entry->base == pool_offset) {
3962 valid_entry = entry;
3963 LIST_REMOVE(entry, next);
3968 /* Not find, return */
3969 if (valid_entry == NULL) {
3970 PMD_DRV_LOG(ERR, "Failed to find entry");
3975 * Found it, move it to free list and try to merge.
3976 * In order to make merge easier, always sort it by qbase.
3977 * Find adjacent prev and last entries.
3980 LIST_FOREACH(entry, &pool->free_list, next) {
3981 if (entry->base > valid_entry->base) {
3989 /* Try to merge with next one*/
3991 /* Merge with next one */
3992 if (valid_entry->base + valid_entry->len == next->base) {
3993 next->base = valid_entry->base;
3994 next->len += valid_entry->len;
3995 rte_free(valid_entry);
4002 /* Merge with previous one */
4003 if (prev->base + prev->len == valid_entry->base) {
4004 prev->len += valid_entry->len;
4005 /* If it merge with next one, remove next node */
4007 LIST_REMOVE(valid_entry, next);
4008 rte_free(valid_entry);
4010 rte_free(valid_entry);
4016 /* Not find any entry to merge, insert */
4019 LIST_INSERT_AFTER(prev, valid_entry, next);
4020 else if (next != NULL)
4021 LIST_INSERT_BEFORE(next, valid_entry, next);
4022 else /* It's empty list, insert to head */
4023 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4026 pool->num_free += valid_entry->len;
4027 pool->num_alloc -= valid_entry->len;
4033 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4036 struct pool_entry *entry, *valid_entry;
4038 if (pool == NULL || num == 0) {
4039 PMD_DRV_LOG(ERR, "Invalid parameter");
4043 if (pool->num_free < num) {
4044 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4045 num, pool->num_free);
4050 /* Lookup in free list and find most fit one */
4051 LIST_FOREACH(entry, &pool->free_list, next) {
4052 if (entry->len >= num) {
4054 if (entry->len == num) {
4055 valid_entry = entry;
4058 if (valid_entry == NULL || valid_entry->len > entry->len)
4059 valid_entry = entry;
4063 /* Not find one to satisfy the request, return */
4064 if (valid_entry == NULL) {
4065 PMD_DRV_LOG(ERR, "No valid entry found");
4069 * The entry have equal queue number as requested,
4070 * remove it from alloc_list.
4072 if (valid_entry->len == num) {
4073 LIST_REMOVE(valid_entry, next);
4076 * The entry have more numbers than requested,
4077 * create a new entry for alloc_list and minus its
4078 * queue base and number in free_list.
4080 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4081 if (entry == NULL) {
4083 "Failed to allocate memory for resource pool");
4086 entry->base = valid_entry->base;
4088 valid_entry->base += num;
4089 valid_entry->len -= num;
4090 valid_entry = entry;
4093 /* Insert it into alloc list, not sorted */
4094 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4096 pool->num_free -= valid_entry->len;
4097 pool->num_alloc += valid_entry->len;
4099 return valid_entry->base + pool->base;
4103 * bitmap_is_subset - Check whether src2 is subset of src1
4106 bitmap_is_subset(uint8_t src1, uint8_t src2)
4108 return !((src1 ^ src2) & src2);
4111 static enum i40e_status_code
4112 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4114 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4116 /* If DCB is not supported, only default TC is supported */
4117 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4118 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4119 return I40E_NOT_SUPPORTED;
4122 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4124 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4125 hw->func_caps.enabled_tcmap, enabled_tcmap);
4126 return I40E_NOT_SUPPORTED;
4128 return I40E_SUCCESS;
4132 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4133 struct i40e_vsi_vlan_pvid_info *info)
4136 struct i40e_vsi_context ctxt;
4137 uint8_t vlan_flags = 0;
4140 if (vsi == NULL || info == NULL) {
4141 PMD_DRV_LOG(ERR, "invalid parameters");
4142 return I40E_ERR_PARAM;
4146 vsi->info.pvid = info->config.pvid;
4148 * If insert pvid is enabled, only tagged pkts are
4149 * allowed to be sent out.
4151 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4152 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4155 if (info->config.reject.tagged == 0)
4156 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4158 if (info->config.reject.untagged == 0)
4159 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4161 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4162 I40E_AQ_VSI_PVLAN_MODE_MASK);
4163 vsi->info.port_vlan_flags |= vlan_flags;
4164 vsi->info.valid_sections =
4165 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4166 memset(&ctxt, 0, sizeof(ctxt));
4167 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4168 ctxt.seid = vsi->seid;
4170 hw = I40E_VSI_TO_HW(vsi);
4171 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4172 if (ret != I40E_SUCCESS)
4173 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4179 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4181 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4183 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4185 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4186 if (ret != I40E_SUCCESS)
4190 PMD_DRV_LOG(ERR, "seid not valid");
4194 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4195 tc_bw_data.tc_valid_bits = enabled_tcmap;
4196 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4197 tc_bw_data.tc_bw_credits[i] =
4198 (enabled_tcmap & (1 << i)) ? 1 : 0;
4200 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4201 if (ret != I40E_SUCCESS) {
4202 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4206 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4207 sizeof(vsi->info.qs_handle));
4208 return I40E_SUCCESS;
4211 static enum i40e_status_code
4212 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4213 struct i40e_aqc_vsi_properties_data *info,
4214 uint8_t enabled_tcmap)
4216 enum i40e_status_code ret;
4217 int i, total_tc = 0;
4218 uint16_t qpnum_per_tc, bsf, qp_idx;
4220 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4221 if (ret != I40E_SUCCESS)
4224 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4225 if (enabled_tcmap & (1 << i))
4227 vsi->enabled_tc = enabled_tcmap;
4229 /* Number of queues per enabled TC */
4230 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4231 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4232 bsf = rte_bsf32(qpnum_per_tc);
4234 /* Adjust the queue number to actual queues that can be applied */
4235 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4236 vsi->nb_qps = qpnum_per_tc * total_tc;
4239 * Configure TC and queue mapping parameters, for enabled TC,
4240 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4241 * default queue will serve it.
4244 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4245 if (vsi->enabled_tc & (1 << i)) {
4246 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4247 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4248 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4249 qp_idx += qpnum_per_tc;
4251 info->tc_mapping[i] = 0;
4254 /* Associate queue number with VSI */
4255 if (vsi->type == I40E_VSI_SRIOV) {
4256 info->mapping_flags |=
4257 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4258 for (i = 0; i < vsi->nb_qps; i++)
4259 info->queue_mapping[i] =
4260 rte_cpu_to_le_16(vsi->base_queue + i);
4262 info->mapping_flags |=
4263 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4264 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4266 info->valid_sections |=
4267 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4269 return I40E_SUCCESS;
4273 i40e_veb_release(struct i40e_veb *veb)
4275 struct i40e_vsi *vsi;
4281 if (!TAILQ_EMPTY(&veb->head)) {
4282 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4285 /* associate_vsi field is NULL for floating VEB */
4286 if (veb->associate_vsi != NULL) {
4287 vsi = veb->associate_vsi;
4288 hw = I40E_VSI_TO_HW(vsi);
4290 vsi->uplink_seid = veb->uplink_seid;
4293 veb->associate_pf->main_vsi->floating_veb = NULL;
4294 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4297 i40e_aq_delete_element(hw, veb->seid, NULL);
4299 return I40E_SUCCESS;
4303 static struct i40e_veb *
4304 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4306 struct i40e_veb *veb;
4312 "veb setup failed, associated PF shouldn't null");
4315 hw = I40E_PF_TO_HW(pf);
4317 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4319 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4323 veb->associate_vsi = vsi;
4324 veb->associate_pf = pf;
4325 TAILQ_INIT(&veb->head);
4326 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4328 /* create floating veb if vsi is NULL */
4330 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4331 I40E_DEFAULT_TCMAP, false,
4332 &veb->seid, false, NULL);
4334 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4335 true, &veb->seid, false, NULL);
4338 if (ret != I40E_SUCCESS) {
4339 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4340 hw->aq.asq_last_status);
4344 /* get statistics index */
4345 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4346 &veb->stats_idx, NULL, NULL, NULL);
4347 if (ret != I40E_SUCCESS) {
4348 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4349 hw->aq.asq_last_status);
4352 /* Get VEB bandwidth, to be implemented */
4353 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4355 vsi->uplink_seid = veb->seid;
4364 i40e_vsi_release(struct i40e_vsi *vsi)
4368 struct i40e_vsi_list *vsi_list;
4371 struct i40e_mac_filter *f;
4372 uint16_t user_param;
4375 return I40E_SUCCESS;
4377 user_param = vsi->user_param;
4379 pf = I40E_VSI_TO_PF(vsi);
4380 hw = I40E_VSI_TO_HW(vsi);
4382 /* VSI has child to attach, release child first */
4384 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4385 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4388 i40e_veb_release(vsi->veb);
4391 if (vsi->floating_veb) {
4392 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4393 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4398 /* Remove all macvlan filters of the VSI */
4399 i40e_vsi_remove_all_macvlan_filter(vsi);
4400 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4403 if (vsi->type != I40E_VSI_MAIN &&
4404 ((vsi->type != I40E_VSI_SRIOV) ||
4405 !pf->floating_veb_list[user_param])) {
4406 /* Remove vsi from parent's sibling list */
4407 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4408 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4409 return I40E_ERR_PARAM;
4411 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4412 &vsi->sib_vsi_list, list);
4414 /* Remove all switch element of the VSI */
4415 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4416 if (ret != I40E_SUCCESS)
4417 PMD_DRV_LOG(ERR, "Failed to delete element");
4420 if ((vsi->type == I40E_VSI_SRIOV) &&
4421 pf->floating_veb_list[user_param]) {
4422 /* Remove vsi from parent's sibling list */
4423 if (vsi->parent_vsi == NULL ||
4424 vsi->parent_vsi->floating_veb == NULL) {
4425 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4426 return I40E_ERR_PARAM;
4428 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4429 &vsi->sib_vsi_list, list);
4431 /* Remove all switch element of the VSI */
4432 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4433 if (ret != I40E_SUCCESS)
4434 PMD_DRV_LOG(ERR, "Failed to delete element");
4437 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4439 if (vsi->type != I40E_VSI_SRIOV)
4440 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4443 return I40E_SUCCESS;
4447 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4449 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4450 struct i40e_aqc_remove_macvlan_element_data def_filter;
4451 struct i40e_mac_filter_info filter;
4454 if (vsi->type != I40E_VSI_MAIN)
4455 return I40E_ERR_CONFIG;
4456 memset(&def_filter, 0, sizeof(def_filter));
4457 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4459 def_filter.vlan_tag = 0;
4460 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4461 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4462 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4463 if (ret != I40E_SUCCESS) {
4464 struct i40e_mac_filter *f;
4465 struct ether_addr *mac;
4467 PMD_DRV_LOG(WARNING,
4468 "Cannot remove the default macvlan filter");
4469 /* It needs to add the permanent mac into mac list */
4470 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4472 PMD_DRV_LOG(ERR, "failed to allocate memory");
4473 return I40E_ERR_NO_MEMORY;
4475 mac = &f->mac_info.mac_addr;
4476 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4478 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4479 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4484 (void)rte_memcpy(&filter.mac_addr,
4485 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4486 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4487 return i40e_vsi_add_mac(vsi, &filter);
4491 * i40e_vsi_get_bw_config - Query VSI BW Information
4492 * @vsi: the VSI to be queried
4494 * Returns 0 on success, negative value on failure
4496 static enum i40e_status_code
4497 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4499 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4500 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4501 struct i40e_hw *hw = &vsi->adapter->hw;
4506 memset(&bw_config, 0, sizeof(bw_config));
4507 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4508 if (ret != I40E_SUCCESS) {
4509 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4510 hw->aq.asq_last_status);
4514 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4515 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4516 &ets_sla_config, NULL);
4517 if (ret != I40E_SUCCESS) {
4519 "VSI failed to get TC bandwdith configuration %u",
4520 hw->aq.asq_last_status);
4524 /* store and print out BW info */
4525 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4526 vsi->bw_info.bw_max = bw_config.max_bw;
4527 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4528 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4529 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4530 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4532 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4533 vsi->bw_info.bw_ets_share_credits[i] =
4534 ets_sla_config.share_credits[i];
4535 vsi->bw_info.bw_ets_credits[i] =
4536 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4537 /* 4 bits per TC, 4th bit is reserved */
4538 vsi->bw_info.bw_ets_max[i] =
4539 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4540 RTE_LEN2MASK(3, uint8_t));
4541 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4542 vsi->bw_info.bw_ets_share_credits[i]);
4543 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4544 vsi->bw_info.bw_ets_credits[i]);
4545 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4546 vsi->bw_info.bw_ets_max[i]);
4549 return I40E_SUCCESS;
4552 /* i40e_enable_pf_lb
4553 * @pf: pointer to the pf structure
4555 * allow loopback on pf
4558 i40e_enable_pf_lb(struct i40e_pf *pf)
4560 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4561 struct i40e_vsi_context ctxt;
4564 /* Use the FW API if FW >= v5.0 */
4565 if (hw->aq.fw_maj_ver < 5) {
4566 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4570 memset(&ctxt, 0, sizeof(ctxt));
4571 ctxt.seid = pf->main_vsi_seid;
4572 ctxt.pf_num = hw->pf_id;
4573 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4575 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4576 ret, hw->aq.asq_last_status);
4579 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4580 ctxt.info.valid_sections =
4581 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4582 ctxt.info.switch_id |=
4583 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4585 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4587 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4588 hw->aq.asq_last_status);
4593 i40e_vsi_setup(struct i40e_pf *pf,
4594 enum i40e_vsi_type type,
4595 struct i40e_vsi *uplink_vsi,
4596 uint16_t user_param)
4598 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4599 struct i40e_vsi *vsi;
4600 struct i40e_mac_filter_info filter;
4602 struct i40e_vsi_context ctxt;
4603 struct ether_addr broadcast =
4604 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4606 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4607 uplink_vsi == NULL) {
4609 "VSI setup failed, VSI link shouldn't be NULL");
4613 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4615 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4620 * 1.type is not MAIN and uplink vsi is not NULL
4621 * If uplink vsi didn't setup VEB, create one first under veb field
4622 * 2.type is SRIOV and the uplink is NULL
4623 * If floating VEB is NULL, create one veb under floating veb field
4626 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4627 uplink_vsi->veb == NULL) {
4628 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4630 if (uplink_vsi->veb == NULL) {
4631 PMD_DRV_LOG(ERR, "VEB setup failed");
4634 /* set ALLOWLOOPBACk on pf, when veb is created */
4635 i40e_enable_pf_lb(pf);
4638 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4639 pf->main_vsi->floating_veb == NULL) {
4640 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4642 if (pf->main_vsi->floating_veb == NULL) {
4643 PMD_DRV_LOG(ERR, "VEB setup failed");
4648 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4650 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4653 TAILQ_INIT(&vsi->mac_list);
4655 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4656 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4657 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4658 vsi->user_param = user_param;
4659 vsi->vlan_anti_spoof_on = 0;
4660 /* Allocate queues */
4661 switch (vsi->type) {
4662 case I40E_VSI_MAIN :
4663 vsi->nb_qps = pf->lan_nb_qps;
4665 case I40E_VSI_SRIOV :
4666 vsi->nb_qps = pf->vf_nb_qps;
4668 case I40E_VSI_VMDQ2:
4669 vsi->nb_qps = pf->vmdq_nb_qps;
4672 vsi->nb_qps = pf->fdir_nb_qps;
4678 * The filter status descriptor is reported in rx queue 0,
4679 * while the tx queue for fdir filter programming has no
4680 * such constraints, can be non-zero queues.
4681 * To simplify it, choose FDIR vsi use queue 0 pair.
4682 * To make sure it will use queue 0 pair, queue allocation
4683 * need be done before this function is called
4685 if (type != I40E_VSI_FDIR) {
4686 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4688 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4692 vsi->base_queue = ret;
4694 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4696 /* VF has MSIX interrupt in VF range, don't allocate here */
4697 if (type == I40E_VSI_MAIN) {
4698 ret = i40e_res_pool_alloc(&pf->msix_pool,
4699 RTE_MIN(vsi->nb_qps,
4700 RTE_MAX_RXTX_INTR_VEC_ID));
4702 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4704 goto fail_queue_alloc;
4706 vsi->msix_intr = ret;
4707 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4708 } else if (type != I40E_VSI_SRIOV) {
4709 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4711 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4712 goto fail_queue_alloc;
4714 vsi->msix_intr = ret;
4722 if (type == I40E_VSI_MAIN) {
4723 /* For main VSI, no need to add since it's default one */
4724 vsi->uplink_seid = pf->mac_seid;
4725 vsi->seid = pf->main_vsi_seid;
4726 /* Bind queues with specific MSIX interrupt */
4728 * Needs 2 interrupt at least, one for misc cause which will
4729 * enabled from OS side, Another for queues binding the
4730 * interrupt from device side only.
4733 /* Get default VSI parameters from hardware */
4734 memset(&ctxt, 0, sizeof(ctxt));
4735 ctxt.seid = vsi->seid;
4736 ctxt.pf_num = hw->pf_id;
4737 ctxt.uplink_seid = vsi->uplink_seid;
4739 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4740 if (ret != I40E_SUCCESS) {
4741 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4742 goto fail_msix_alloc;
4744 (void)rte_memcpy(&vsi->info, &ctxt.info,
4745 sizeof(struct i40e_aqc_vsi_properties_data));
4746 vsi->vsi_id = ctxt.vsi_number;
4747 vsi->info.valid_sections = 0;
4749 /* Configure tc, enabled TC0 only */
4750 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4752 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4753 goto fail_msix_alloc;
4756 /* TC, queue mapping */
4757 memset(&ctxt, 0, sizeof(ctxt));
4758 vsi->info.valid_sections |=
4759 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4760 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4761 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4762 (void)rte_memcpy(&ctxt.info, &vsi->info,
4763 sizeof(struct i40e_aqc_vsi_properties_data));
4764 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4765 I40E_DEFAULT_TCMAP);
4766 if (ret != I40E_SUCCESS) {
4768 "Failed to configure TC queue mapping");
4769 goto fail_msix_alloc;
4771 ctxt.seid = vsi->seid;
4772 ctxt.pf_num = hw->pf_id;
4773 ctxt.uplink_seid = vsi->uplink_seid;
4776 /* Update VSI parameters */
4777 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4778 if (ret != I40E_SUCCESS) {
4779 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4780 goto fail_msix_alloc;
4783 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4784 sizeof(vsi->info.tc_mapping));
4785 (void)rte_memcpy(&vsi->info.queue_mapping,
4786 &ctxt.info.queue_mapping,
4787 sizeof(vsi->info.queue_mapping));
4788 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4789 vsi->info.valid_sections = 0;
4791 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4795 * Updating default filter settings are necessary to prevent
4796 * reception of tagged packets.
4797 * Some old firmware configurations load a default macvlan
4798 * filter which accepts both tagged and untagged packets.
4799 * The updating is to use a normal filter instead if needed.
4800 * For NVM 4.2.2 or after, the updating is not needed anymore.
4801 * The firmware with correct configurations load the default
4802 * macvlan filter which is expected and cannot be removed.
4804 i40e_update_default_filter_setting(vsi);
4805 i40e_config_qinq(hw, vsi);
4806 } else if (type == I40E_VSI_SRIOV) {
4807 memset(&ctxt, 0, sizeof(ctxt));
4809 * For other VSI, the uplink_seid equals to uplink VSI's
4810 * uplink_seid since they share same VEB
4812 if (uplink_vsi == NULL)
4813 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4815 vsi->uplink_seid = uplink_vsi->uplink_seid;
4816 ctxt.pf_num = hw->pf_id;
4817 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4818 ctxt.uplink_seid = vsi->uplink_seid;
4819 ctxt.connection_type = 0x1;
4820 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4822 /* Use the VEB configuration if FW >= v5.0 */
4823 if (hw->aq.fw_maj_ver >= 5) {
4824 /* Configure switch ID */
4825 ctxt.info.valid_sections |=
4826 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4827 ctxt.info.switch_id =
4828 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4831 /* Configure port/vlan */
4832 ctxt.info.valid_sections |=
4833 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4834 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4835 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4836 I40E_DEFAULT_TCMAP);
4837 if (ret != I40E_SUCCESS) {
4839 "Failed to configure TC queue mapping");
4840 goto fail_msix_alloc;
4842 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4843 ctxt.info.valid_sections |=
4844 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4846 * Since VSI is not created yet, only configure parameter,
4847 * will add vsi below.
4850 i40e_config_qinq(hw, vsi);
4851 } else if (type == I40E_VSI_VMDQ2) {
4852 memset(&ctxt, 0, sizeof(ctxt));
4854 * For other VSI, the uplink_seid equals to uplink VSI's
4855 * uplink_seid since they share same VEB
4857 vsi->uplink_seid = uplink_vsi->uplink_seid;
4858 ctxt.pf_num = hw->pf_id;
4860 ctxt.uplink_seid = vsi->uplink_seid;
4861 ctxt.connection_type = 0x1;
4862 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4864 ctxt.info.valid_sections |=
4865 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4866 /* user_param carries flag to enable loop back */
4868 ctxt.info.switch_id =
4869 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4870 ctxt.info.switch_id |=
4871 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4874 /* Configure port/vlan */
4875 ctxt.info.valid_sections |=
4876 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4877 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4878 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4879 I40E_DEFAULT_TCMAP);
4880 if (ret != I40E_SUCCESS) {
4882 "Failed to configure TC queue mapping");
4883 goto fail_msix_alloc;
4885 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4886 ctxt.info.valid_sections |=
4887 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4888 } else if (type == I40E_VSI_FDIR) {
4889 memset(&ctxt, 0, sizeof(ctxt));
4890 vsi->uplink_seid = uplink_vsi->uplink_seid;
4891 ctxt.pf_num = hw->pf_id;
4893 ctxt.uplink_seid = vsi->uplink_seid;
4894 ctxt.connection_type = 0x1; /* regular data port */
4895 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4896 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4897 I40E_DEFAULT_TCMAP);
4898 if (ret != I40E_SUCCESS) {
4900 "Failed to configure TC queue mapping.");
4901 goto fail_msix_alloc;
4903 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4904 ctxt.info.valid_sections |=
4905 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4907 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4908 goto fail_msix_alloc;
4911 if (vsi->type != I40E_VSI_MAIN) {
4912 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4913 if (ret != I40E_SUCCESS) {
4914 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4915 hw->aq.asq_last_status);
4916 goto fail_msix_alloc;
4918 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4919 vsi->info.valid_sections = 0;
4920 vsi->seid = ctxt.seid;
4921 vsi->vsi_id = ctxt.vsi_number;
4922 vsi->sib_vsi_list.vsi = vsi;
4923 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4924 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4925 &vsi->sib_vsi_list, list);
4927 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4928 &vsi->sib_vsi_list, list);
4932 /* MAC/VLAN configuration */
4933 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4934 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4936 ret = i40e_vsi_add_mac(vsi, &filter);
4937 if (ret != I40E_SUCCESS) {
4938 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4939 goto fail_msix_alloc;
4942 /* Get VSI BW information */
4943 i40e_vsi_get_bw_config(vsi);
4946 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4948 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4954 /* Configure vlan filter on or off */
4956 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4959 struct i40e_mac_filter *f;
4961 struct i40e_mac_filter_info *mac_filter;
4962 enum rte_mac_filter_type desired_filter;
4963 int ret = I40E_SUCCESS;
4966 /* Filter to match MAC and VLAN */
4967 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4969 /* Filter to match only MAC */
4970 desired_filter = RTE_MAC_PERFECT_MATCH;
4975 mac_filter = rte_zmalloc("mac_filter_info_data",
4976 num * sizeof(*mac_filter), 0);
4977 if (mac_filter == NULL) {
4978 PMD_DRV_LOG(ERR, "failed to allocate memory");
4979 return I40E_ERR_NO_MEMORY;
4984 /* Remove all existing mac */
4985 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4986 mac_filter[i] = f->mac_info;
4987 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4989 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4990 on ? "enable" : "disable");
4996 /* Override with new filter */
4997 for (i = 0; i < num; i++) {
4998 mac_filter[i].filter_type = desired_filter;
4999 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5001 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5002 on ? "enable" : "disable");
5008 rte_free(mac_filter);
5012 /* Configure vlan stripping on or off */
5014 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5016 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5017 struct i40e_vsi_context ctxt;
5019 int ret = I40E_SUCCESS;
5021 /* Check if it has been already on or off */
5022 if (vsi->info.valid_sections &
5023 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5025 if ((vsi->info.port_vlan_flags &
5026 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5027 return 0; /* already on */
5029 if ((vsi->info.port_vlan_flags &
5030 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5031 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5032 return 0; /* already off */
5037 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5039 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5040 vsi->info.valid_sections =
5041 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5042 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5043 vsi->info.port_vlan_flags |= vlan_flags;
5044 ctxt.seid = vsi->seid;
5045 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5046 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5048 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5049 on ? "enable" : "disable");
5055 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5057 struct rte_eth_dev_data *data = dev->data;
5061 /* Apply vlan offload setting */
5062 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5063 i40e_vlan_offload_set(dev, mask);
5065 /* Apply double-vlan setting, not implemented yet */
5067 /* Apply pvid setting */
5068 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5069 data->dev_conf.txmode.hw_vlan_insert_pvid);
5071 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5077 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5079 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5081 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5085 i40e_update_flow_control(struct i40e_hw *hw)
5087 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5088 struct i40e_link_status link_status;
5089 uint32_t rxfc = 0, txfc = 0, reg;
5093 memset(&link_status, 0, sizeof(link_status));
5094 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5095 if (ret != I40E_SUCCESS) {
5096 PMD_DRV_LOG(ERR, "Failed to get link status information");
5097 goto write_reg; /* Disable flow control */
5100 an_info = hw->phy.link_info.an_info;
5101 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5102 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5103 ret = I40E_ERR_NOT_READY;
5104 goto write_reg; /* Disable flow control */
5107 * If link auto negotiation is enabled, flow control needs to
5108 * be configured according to it
5110 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5111 case I40E_LINK_PAUSE_RXTX:
5114 hw->fc.current_mode = I40E_FC_FULL;
5116 case I40E_AQ_LINK_PAUSE_RX:
5118 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5120 case I40E_AQ_LINK_PAUSE_TX:
5122 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5125 hw->fc.current_mode = I40E_FC_NONE;
5130 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5131 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5132 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5133 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5134 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5135 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5142 i40e_pf_setup(struct i40e_pf *pf)
5144 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5145 struct i40e_filter_control_settings settings;
5146 struct i40e_vsi *vsi;
5149 /* Clear all stats counters */
5150 pf->offset_loaded = FALSE;
5151 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5152 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5154 ret = i40e_pf_get_switch_config(pf);
5155 if (ret != I40E_SUCCESS) {
5156 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5159 if (pf->flags & I40E_FLAG_FDIR) {
5160 /* make queue allocated first, let FDIR use queue pair 0*/
5161 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5162 if (ret != I40E_FDIR_QUEUE_ID) {
5164 "queue allocation fails for FDIR: ret =%d",
5166 pf->flags &= ~I40E_FLAG_FDIR;
5169 /* main VSI setup */
5170 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5172 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5173 return I40E_ERR_NOT_READY;
5177 /* Configure filter control */
5178 memset(&settings, 0, sizeof(settings));
5179 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5180 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5181 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5182 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5184 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5185 hw->func_caps.rss_table_size);
5186 return I40E_ERR_PARAM;
5188 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u\n",
5189 hw->func_caps.rss_table_size);
5190 pf->hash_lut_size = hw->func_caps.rss_table_size;
5192 /* Enable ethtype and macvlan filters */
5193 settings.enable_ethtype = TRUE;
5194 settings.enable_macvlan = TRUE;
5195 ret = i40e_set_filter_control(hw, &settings);
5197 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5200 /* Update flow control according to the auto negotiation */
5201 i40e_update_flow_control(hw);
5203 return I40E_SUCCESS;
5207 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5213 * Set or clear TX Queue Disable flags,
5214 * which is required by hardware.
5216 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5217 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5219 /* Wait until the request is finished */
5220 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5221 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5222 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5223 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5224 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5230 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5231 return I40E_SUCCESS; /* already on, skip next steps */
5233 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5234 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5236 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5237 return I40E_SUCCESS; /* already off, skip next steps */
5238 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5240 /* Write the register */
5241 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5242 /* Check the result */
5243 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5244 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5245 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5247 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5248 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5251 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5252 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5256 /* Check if it is timeout */
5257 if (j >= I40E_CHK_Q_ENA_COUNT) {
5258 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5259 (on ? "enable" : "disable"), q_idx);
5260 return I40E_ERR_TIMEOUT;
5263 return I40E_SUCCESS;
5266 /* Swith on or off the tx queues */
5268 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5270 struct rte_eth_dev_data *dev_data = pf->dev_data;
5271 struct i40e_tx_queue *txq;
5272 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5276 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5277 txq = dev_data->tx_queues[i];
5278 /* Don't operate the queue if not configured or
5279 * if starting only per queue */
5280 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5283 ret = i40e_dev_tx_queue_start(dev, i);
5285 ret = i40e_dev_tx_queue_stop(dev, i);
5286 if ( ret != I40E_SUCCESS)
5290 return I40E_SUCCESS;
5294 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5299 /* Wait until the request is finished */
5300 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5301 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5302 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5303 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5304 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5309 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5310 return I40E_SUCCESS; /* Already on, skip next steps */
5311 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5313 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5314 return I40E_SUCCESS; /* Already off, skip next steps */
5315 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5318 /* Write the register */
5319 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5320 /* Check the result */
5321 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5322 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5323 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5325 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5326 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5329 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5330 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5335 /* Check if it is timeout */
5336 if (j >= I40E_CHK_Q_ENA_COUNT) {
5337 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5338 (on ? "enable" : "disable"), q_idx);
5339 return I40E_ERR_TIMEOUT;
5342 return I40E_SUCCESS;
5344 /* Switch on or off the rx queues */
5346 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5348 struct rte_eth_dev_data *dev_data = pf->dev_data;
5349 struct i40e_rx_queue *rxq;
5350 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5354 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5355 rxq = dev_data->rx_queues[i];
5356 /* Don't operate the queue if not configured or
5357 * if starting only per queue */
5358 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5361 ret = i40e_dev_rx_queue_start(dev, i);
5363 ret = i40e_dev_rx_queue_stop(dev, i);
5364 if (ret != I40E_SUCCESS)
5368 return I40E_SUCCESS;
5371 /* Switch on or off all the rx/tx queues */
5373 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5378 /* enable rx queues before enabling tx queues */
5379 ret = i40e_dev_switch_rx_queues(pf, on);
5381 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5384 ret = i40e_dev_switch_tx_queues(pf, on);
5386 /* Stop tx queues before stopping rx queues */
5387 ret = i40e_dev_switch_tx_queues(pf, on);
5389 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5392 ret = i40e_dev_switch_rx_queues(pf, on);
5398 /* Initialize VSI for TX */
5400 i40e_dev_tx_init(struct i40e_pf *pf)
5402 struct rte_eth_dev_data *data = pf->dev_data;
5404 uint32_t ret = I40E_SUCCESS;
5405 struct i40e_tx_queue *txq;
5407 for (i = 0; i < data->nb_tx_queues; i++) {
5408 txq = data->tx_queues[i];
5409 if (!txq || !txq->q_set)
5411 ret = i40e_tx_queue_init(txq);
5412 if (ret != I40E_SUCCESS)
5415 if (ret == I40E_SUCCESS)
5416 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5422 /* Initialize VSI for RX */
5424 i40e_dev_rx_init(struct i40e_pf *pf)
5426 struct rte_eth_dev_data *data = pf->dev_data;
5427 int ret = I40E_SUCCESS;
5429 struct i40e_rx_queue *rxq;
5431 i40e_pf_config_mq_rx(pf);
5432 for (i = 0; i < data->nb_rx_queues; i++) {
5433 rxq = data->rx_queues[i];
5434 if (!rxq || !rxq->q_set)
5437 ret = i40e_rx_queue_init(rxq);
5438 if (ret != I40E_SUCCESS) {
5440 "Failed to do RX queue initialization");
5444 if (ret == I40E_SUCCESS)
5445 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5452 i40e_dev_rxtx_init(struct i40e_pf *pf)
5456 err = i40e_dev_tx_init(pf);
5458 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5461 err = i40e_dev_rx_init(pf);
5463 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5471 i40e_vmdq_setup(struct rte_eth_dev *dev)
5473 struct rte_eth_conf *conf = &dev->data->dev_conf;
5474 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5475 int i, err, conf_vsis, j, loop;
5476 struct i40e_vsi *vsi;
5477 struct i40e_vmdq_info *vmdq_info;
5478 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5479 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5482 * Disable interrupt to avoid message from VF. Furthermore, it will
5483 * avoid race condition in VSI creation/destroy.
5485 i40e_pf_disable_irq0(hw);
5487 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5488 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5492 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5493 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5494 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5495 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5496 pf->max_nb_vmdq_vsi);
5500 if (pf->vmdq != NULL) {
5501 PMD_INIT_LOG(INFO, "VMDQ already configured");
5505 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5506 sizeof(*vmdq_info) * conf_vsis, 0);
5508 if (pf->vmdq == NULL) {
5509 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5513 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5515 /* Create VMDQ VSI */
5516 for (i = 0; i < conf_vsis; i++) {
5517 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5518 vmdq_conf->enable_loop_back);
5520 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5524 vmdq_info = &pf->vmdq[i];
5526 vmdq_info->vsi = vsi;
5528 pf->nb_cfg_vmdq_vsi = conf_vsis;
5530 /* Configure Vlan */
5531 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5532 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5533 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5534 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5535 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5536 vmdq_conf->pool_map[i].vlan_id, j);
5538 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5539 vmdq_conf->pool_map[i].vlan_id);
5541 PMD_INIT_LOG(ERR, "Failed to add vlan");
5549 i40e_pf_enable_irq0(hw);
5554 for (i = 0; i < conf_vsis; i++)
5555 if (pf->vmdq[i].vsi == NULL)
5558 i40e_vsi_release(pf->vmdq[i].vsi);
5562 i40e_pf_enable_irq0(hw);
5567 i40e_stat_update_32(struct i40e_hw *hw,
5575 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5579 if (new_data >= *offset)
5580 *stat = (uint64_t)(new_data - *offset);
5582 *stat = (uint64_t)((new_data +
5583 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5587 i40e_stat_update_48(struct i40e_hw *hw,
5596 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5597 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5598 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5603 if (new_data >= *offset)
5604 *stat = new_data - *offset;
5606 *stat = (uint64_t)((new_data +
5607 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5609 *stat &= I40E_48_BIT_MASK;
5614 i40e_pf_disable_irq0(struct i40e_hw *hw)
5616 /* Disable all interrupt types */
5617 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5618 I40E_WRITE_FLUSH(hw);
5623 i40e_pf_enable_irq0(struct i40e_hw *hw)
5625 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5626 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5627 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5628 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5629 I40E_WRITE_FLUSH(hw);
5633 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5635 /* read pending request and disable first */
5636 i40e_pf_disable_irq0(hw);
5637 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5638 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5639 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5642 /* Link no queues with irq0 */
5643 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5644 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5648 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5650 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5651 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5654 uint32_t index, offset, val;
5659 * Try to find which VF trigger a reset, use absolute VF id to access
5660 * since the reg is global register.
5662 for (i = 0; i < pf->vf_num; i++) {
5663 abs_vf_id = hw->func_caps.vf_base_id + i;
5664 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5665 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5666 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5667 /* VFR event occured */
5668 if (val & (0x1 << offset)) {
5671 /* Clear the event first */
5672 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5674 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5676 * Only notify a VF reset event occured,
5677 * don't trigger another SW reset
5679 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5680 if (ret != I40E_SUCCESS)
5681 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5687 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5689 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5690 struct i40e_virtchnl_pf_event event;
5693 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5694 event.event_data.link_event.link_status =
5695 dev->data->dev_link.link_status;
5696 event.event_data.link_event.link_speed =
5697 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5699 for (i = 0; i < pf->vf_num; i++)
5700 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5701 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5705 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5707 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5708 struct i40e_arq_event_info info;
5709 uint16_t pending, opcode;
5712 info.buf_len = I40E_AQ_BUF_SZ;
5713 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5714 if (!info.msg_buf) {
5715 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5721 ret = i40e_clean_arq_element(hw, &info, &pending);
5723 if (ret != I40E_SUCCESS) {
5725 "Failed to read msg from AdminQ, aq_err: %u",
5726 hw->aq.asq_last_status);
5729 opcode = rte_le_to_cpu_16(info.desc.opcode);
5732 case i40e_aqc_opc_send_msg_to_pf:
5733 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5734 i40e_pf_host_handle_vf_msg(dev,
5735 rte_le_to_cpu_16(info.desc.retval),
5736 rte_le_to_cpu_32(info.desc.cookie_high),
5737 rte_le_to_cpu_32(info.desc.cookie_low),
5741 case i40e_aqc_opc_get_link_status:
5742 ret = i40e_dev_link_update(dev, 0);
5744 i40e_notify_all_vfs_link_status(dev);
5745 _rte_eth_dev_callback_process(dev,
5746 RTE_ETH_EVENT_INTR_LSC, NULL);
5750 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5755 rte_free(info.msg_buf);
5759 * Interrupt handler triggered by NIC for handling
5760 * specific interrupt.
5763 * Pointer to interrupt handle.
5765 * The address of parameter (struct rte_eth_dev *) regsitered before.
5771 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5774 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5775 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5778 /* Disable interrupt */
5779 i40e_pf_disable_irq0(hw);
5781 /* read out interrupt causes */
5782 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5784 /* No interrupt event indicated */
5785 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5786 PMD_DRV_LOG(INFO, "No interrupt event");
5789 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5790 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5791 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5792 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5793 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5794 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5795 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5796 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5797 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5798 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5799 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5800 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5801 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5802 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5803 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5804 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5806 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5807 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5808 i40e_dev_handle_vfr_event(dev);
5810 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5811 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5812 i40e_dev_handle_aq_msg(dev);
5816 /* Enable interrupt */
5817 i40e_pf_enable_irq0(hw);
5818 rte_intr_enable(intr_handle);
5822 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5823 struct i40e_macvlan_filter *filter,
5826 int ele_num, ele_buff_size;
5827 int num, actual_num, i;
5829 int ret = I40E_SUCCESS;
5830 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5831 struct i40e_aqc_add_macvlan_element_data *req_list;
5833 if (filter == NULL || total == 0)
5834 return I40E_ERR_PARAM;
5835 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5836 ele_buff_size = hw->aq.asq_buf_size;
5838 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5839 if (req_list == NULL) {
5840 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5841 return I40E_ERR_NO_MEMORY;
5846 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5847 memset(req_list, 0, ele_buff_size);
5849 for (i = 0; i < actual_num; i++) {
5850 (void)rte_memcpy(req_list[i].mac_addr,
5851 &filter[num + i].macaddr, ETH_ADDR_LEN);
5852 req_list[i].vlan_tag =
5853 rte_cpu_to_le_16(filter[num + i].vlan_id);
5855 switch (filter[num + i].filter_type) {
5856 case RTE_MAC_PERFECT_MATCH:
5857 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5858 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5860 case RTE_MACVLAN_PERFECT_MATCH:
5861 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5863 case RTE_MAC_HASH_MATCH:
5864 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5865 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5867 case RTE_MACVLAN_HASH_MATCH:
5868 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5871 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5872 ret = I40E_ERR_PARAM;
5876 req_list[i].queue_number = 0;
5878 req_list[i].flags = rte_cpu_to_le_16(flags);
5881 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5883 if (ret != I40E_SUCCESS) {
5884 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5888 } while (num < total);
5896 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5897 struct i40e_macvlan_filter *filter,
5900 int ele_num, ele_buff_size;
5901 int num, actual_num, i;
5903 int ret = I40E_SUCCESS;
5904 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5905 struct i40e_aqc_remove_macvlan_element_data *req_list;
5907 if (filter == NULL || total == 0)
5908 return I40E_ERR_PARAM;
5910 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5911 ele_buff_size = hw->aq.asq_buf_size;
5913 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5914 if (req_list == NULL) {
5915 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5916 return I40E_ERR_NO_MEMORY;
5921 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5922 memset(req_list, 0, ele_buff_size);
5924 for (i = 0; i < actual_num; i++) {
5925 (void)rte_memcpy(req_list[i].mac_addr,
5926 &filter[num + i].macaddr, ETH_ADDR_LEN);
5927 req_list[i].vlan_tag =
5928 rte_cpu_to_le_16(filter[num + i].vlan_id);
5930 switch (filter[num + i].filter_type) {
5931 case RTE_MAC_PERFECT_MATCH:
5932 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5933 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5935 case RTE_MACVLAN_PERFECT_MATCH:
5936 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5938 case RTE_MAC_HASH_MATCH:
5939 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5940 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5942 case RTE_MACVLAN_HASH_MATCH:
5943 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5946 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5947 ret = I40E_ERR_PARAM;
5950 req_list[i].flags = rte_cpu_to_le_16(flags);
5953 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5955 if (ret != I40E_SUCCESS) {
5956 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5960 } while (num < total);
5967 /* Find out specific MAC filter */
5968 static struct i40e_mac_filter *
5969 i40e_find_mac_filter(struct i40e_vsi *vsi,
5970 struct ether_addr *macaddr)
5972 struct i40e_mac_filter *f;
5974 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5975 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5983 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5986 uint32_t vid_idx, vid_bit;
5988 if (vlan_id > ETH_VLAN_ID_MAX)
5991 vid_idx = I40E_VFTA_IDX(vlan_id);
5992 vid_bit = I40E_VFTA_BIT(vlan_id);
5994 if (vsi->vfta[vid_idx] & vid_bit)
6001 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6002 uint16_t vlan_id, bool on)
6004 uint32_t vid_idx, vid_bit;
6006 vid_idx = I40E_VFTA_IDX(vlan_id);
6007 vid_bit = I40E_VFTA_BIT(vlan_id);
6010 vsi->vfta[vid_idx] |= vid_bit;
6012 vsi->vfta[vid_idx] &= ~vid_bit;
6016 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6017 uint16_t vlan_id, bool on)
6019 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6020 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6023 if (vlan_id > ETH_VLAN_ID_MAX)
6026 i40e_store_vlan_filter(vsi, vlan_id, on);
6028 if (!vsi->vlan_anti_spoof_on || !vlan_id)
6031 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6034 ret = i40e_aq_add_vlan(hw, vsi->seid,
6035 &vlan_data, 1, NULL);
6036 if (ret != I40E_SUCCESS)
6037 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6039 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6040 &vlan_data, 1, NULL);
6041 if (ret != I40E_SUCCESS)
6043 "Failed to remove vlan filter");
6048 * Find all vlan options for specific mac addr,
6049 * return with actual vlan found.
6052 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6053 struct i40e_macvlan_filter *mv_f,
6054 int num, struct ether_addr *addr)
6060 * Not to use i40e_find_vlan_filter to decrease the loop time,
6061 * although the code looks complex.
6063 if (num < vsi->vlan_num)
6064 return I40E_ERR_PARAM;
6067 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6069 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6070 if (vsi->vfta[j] & (1 << k)) {
6073 "vlan number doesn't match");
6074 return I40E_ERR_PARAM;
6076 (void)rte_memcpy(&mv_f[i].macaddr,
6077 addr, ETH_ADDR_LEN);
6079 j * I40E_UINT32_BIT_SIZE + k;
6085 return I40E_SUCCESS;
6089 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6090 struct i40e_macvlan_filter *mv_f,
6095 struct i40e_mac_filter *f;
6097 if (num < vsi->mac_num)
6098 return I40E_ERR_PARAM;
6100 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6102 PMD_DRV_LOG(ERR, "buffer number not match");
6103 return I40E_ERR_PARAM;
6105 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6107 mv_f[i].vlan_id = vlan;
6108 mv_f[i].filter_type = f->mac_info.filter_type;
6112 return I40E_SUCCESS;
6116 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6119 struct i40e_mac_filter *f;
6120 struct i40e_macvlan_filter *mv_f;
6121 int ret = I40E_SUCCESS;
6123 if (vsi == NULL || vsi->mac_num == 0)
6124 return I40E_ERR_PARAM;
6126 /* Case that no vlan is set */
6127 if (vsi->vlan_num == 0)
6130 num = vsi->mac_num * vsi->vlan_num;
6132 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6134 PMD_DRV_LOG(ERR, "failed to allocate memory");
6135 return I40E_ERR_NO_MEMORY;
6139 if (vsi->vlan_num == 0) {
6140 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6141 (void)rte_memcpy(&mv_f[i].macaddr,
6142 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6143 mv_f[i].filter_type = f->mac_info.filter_type;
6144 mv_f[i].vlan_id = 0;
6148 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6149 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6150 vsi->vlan_num, &f->mac_info.mac_addr);
6151 if (ret != I40E_SUCCESS)
6153 for (j = i; j < i + vsi->vlan_num; j++)
6154 mv_f[j].filter_type = f->mac_info.filter_type;
6159 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6167 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6169 struct i40e_macvlan_filter *mv_f;
6171 int ret = I40E_SUCCESS;
6173 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6174 return I40E_ERR_PARAM;
6176 /* If it's already set, just return */
6177 if (i40e_find_vlan_filter(vsi,vlan))
6178 return I40E_SUCCESS;
6180 mac_num = vsi->mac_num;
6183 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6184 return I40E_ERR_PARAM;
6187 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6190 PMD_DRV_LOG(ERR, "failed to allocate memory");
6191 return I40E_ERR_NO_MEMORY;
6194 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6196 if (ret != I40E_SUCCESS)
6199 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6201 if (ret != I40E_SUCCESS)
6204 i40e_set_vlan_filter(vsi, vlan, 1);
6214 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6216 struct i40e_macvlan_filter *mv_f;
6218 int ret = I40E_SUCCESS;
6221 * Vlan 0 is the generic filter for untagged packets
6222 * and can't be removed.
6224 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6225 return I40E_ERR_PARAM;
6227 /* If can't find it, just return */
6228 if (!i40e_find_vlan_filter(vsi, vlan))
6229 return I40E_ERR_PARAM;
6231 mac_num = vsi->mac_num;
6234 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6235 return I40E_ERR_PARAM;
6238 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6241 PMD_DRV_LOG(ERR, "failed to allocate memory");
6242 return I40E_ERR_NO_MEMORY;
6245 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6247 if (ret != I40E_SUCCESS)
6250 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6252 if (ret != I40E_SUCCESS)
6255 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6256 if (vsi->vlan_num == 1) {
6257 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6258 if (ret != I40E_SUCCESS)
6261 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6262 if (ret != I40E_SUCCESS)
6266 i40e_set_vlan_filter(vsi, vlan, 0);
6276 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6278 struct i40e_mac_filter *f;
6279 struct i40e_macvlan_filter *mv_f;
6280 int i, vlan_num = 0;
6281 int ret = I40E_SUCCESS;
6283 /* If it's add and we've config it, return */
6284 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6286 return I40E_SUCCESS;
6287 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6288 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6291 * If vlan_num is 0, that's the first time to add mac,
6292 * set mask for vlan_id 0.
6294 if (vsi->vlan_num == 0) {
6295 i40e_set_vlan_filter(vsi, 0, 1);
6298 vlan_num = vsi->vlan_num;
6299 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6300 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6303 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6305 PMD_DRV_LOG(ERR, "failed to allocate memory");
6306 return I40E_ERR_NO_MEMORY;
6309 for (i = 0; i < vlan_num; i++) {
6310 mv_f[i].filter_type = mac_filter->filter_type;
6311 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6315 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6316 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6317 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6318 &mac_filter->mac_addr);
6319 if (ret != I40E_SUCCESS)
6323 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6324 if (ret != I40E_SUCCESS)
6327 /* Add the mac addr into mac list */
6328 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6330 PMD_DRV_LOG(ERR, "failed to allocate memory");
6331 ret = I40E_ERR_NO_MEMORY;
6334 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6336 f->mac_info.filter_type = mac_filter->filter_type;
6337 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6348 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6350 struct i40e_mac_filter *f;
6351 struct i40e_macvlan_filter *mv_f;
6353 enum rte_mac_filter_type filter_type;
6354 int ret = I40E_SUCCESS;
6356 /* Can't find it, return an error */
6357 f = i40e_find_mac_filter(vsi, addr);
6359 return I40E_ERR_PARAM;
6361 vlan_num = vsi->vlan_num;
6362 filter_type = f->mac_info.filter_type;
6363 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6364 filter_type == RTE_MACVLAN_HASH_MATCH) {
6365 if (vlan_num == 0) {
6366 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6367 return I40E_ERR_PARAM;
6369 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6370 filter_type == RTE_MAC_HASH_MATCH)
6373 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6375 PMD_DRV_LOG(ERR, "failed to allocate memory");
6376 return I40E_ERR_NO_MEMORY;
6379 for (i = 0; i < vlan_num; i++) {
6380 mv_f[i].filter_type = filter_type;
6381 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6384 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6385 filter_type == RTE_MACVLAN_HASH_MATCH) {
6386 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6387 if (ret != I40E_SUCCESS)
6391 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6392 if (ret != I40E_SUCCESS)
6395 /* Remove the mac addr into mac list */
6396 TAILQ_REMOVE(&vsi->mac_list, f, next);
6406 /* Configure hash enable flags for RSS */
6408 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6415 if (flags & ETH_RSS_FRAG_IPV4)
6416 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6417 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6418 if (type == I40E_MAC_X722) {
6419 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6420 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6422 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6424 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6425 if (type == I40E_MAC_X722) {
6426 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6427 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6428 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6430 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6432 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6433 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6434 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6435 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6436 if (flags & ETH_RSS_FRAG_IPV6)
6437 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6438 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6439 if (type == I40E_MAC_X722) {
6440 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6441 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6443 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6445 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6446 if (type == I40E_MAC_X722) {
6447 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6448 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6449 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6451 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6453 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6454 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6455 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6456 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6457 if (flags & ETH_RSS_L2_PAYLOAD)
6458 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6463 /* Parse the hash enable flags */
6465 i40e_parse_hena(uint64_t flags)
6467 uint64_t rss_hf = 0;
6471 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6472 rss_hf |= ETH_RSS_FRAG_IPV4;
6473 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6474 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6475 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6476 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6477 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6478 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6479 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6480 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6481 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6482 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6483 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6484 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6485 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6486 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6487 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6488 rss_hf |= ETH_RSS_FRAG_IPV6;
6489 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6490 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6491 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6492 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6493 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6494 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6495 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6496 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6497 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6498 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6499 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6500 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6501 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6502 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6503 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6504 rss_hf |= ETH_RSS_L2_PAYLOAD;
6511 i40e_pf_disable_rss(struct i40e_pf *pf)
6513 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6516 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6517 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6518 if (hw->mac.type == I40E_MAC_X722)
6519 hena &= ~I40E_RSS_HENA_ALL_X722;
6521 hena &= ~I40E_RSS_HENA_ALL;
6522 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6523 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6524 I40E_WRITE_FLUSH(hw);
6528 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6530 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6531 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6534 if (!key || key_len == 0) {
6535 PMD_DRV_LOG(DEBUG, "No key to be configured");
6537 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6539 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6543 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6544 struct i40e_aqc_get_set_rss_key_data *key_dw =
6545 (struct i40e_aqc_get_set_rss_key_data *)key;
6547 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6549 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6551 uint32_t *hash_key = (uint32_t *)key;
6554 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6555 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6556 I40E_WRITE_FLUSH(hw);
6563 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6565 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6566 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6569 if (!key || !key_len)
6572 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6573 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6574 (struct i40e_aqc_get_set_rss_key_data *)key);
6576 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6580 uint32_t *key_dw = (uint32_t *)key;
6583 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6584 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6586 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6592 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6594 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6599 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6600 rss_conf->rss_key_len);
6604 rss_hf = rss_conf->rss_hf;
6605 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6606 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6607 if (hw->mac.type == I40E_MAC_X722)
6608 hena &= ~I40E_RSS_HENA_ALL_X722;
6610 hena &= ~I40E_RSS_HENA_ALL;
6611 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6612 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6613 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6614 I40E_WRITE_FLUSH(hw);
6620 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6621 struct rte_eth_rss_conf *rss_conf)
6623 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6624 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6625 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6628 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6629 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6630 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6631 ? I40E_RSS_HENA_ALL_X722
6632 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6633 if (rss_hf != 0) /* Enable RSS */
6635 return 0; /* Nothing to do */
6638 if (rss_hf == 0) /* Disable RSS */
6641 return i40e_hw_rss_hash_set(pf, rss_conf);
6645 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6646 struct rte_eth_rss_conf *rss_conf)
6648 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6649 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6652 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6653 &rss_conf->rss_key_len);
6655 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6656 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6657 rss_conf->rss_hf = i40e_parse_hena(hena);
6663 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6665 switch (filter_type) {
6666 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6667 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6669 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6670 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6672 case RTE_TUNNEL_FILTER_IMAC_TENID:
6673 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6675 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6676 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6678 case ETH_TUNNEL_FILTER_IMAC:
6679 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6681 case ETH_TUNNEL_FILTER_OIP:
6682 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6684 case ETH_TUNNEL_FILTER_IIP:
6685 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6688 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6695 /* Convert tunnel filter structure */
6697 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6699 struct i40e_tunnel_filter *tunnel_filter)
6701 ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6702 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6703 ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6704 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6705 tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6706 tunnel_filter->input.flags = cld_filter->flags;
6707 tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6708 tunnel_filter->queue = cld_filter->queue_number;
6713 /* Check if there exists the tunnel filter */
6714 struct i40e_tunnel_filter *
6715 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6716 const struct i40e_tunnel_filter_input *input)
6720 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6724 return tunnel_rule->hash_map[ret];
6727 /* Add a tunnel filter into the SW list */
6729 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6730 struct i40e_tunnel_filter *tunnel_filter)
6732 struct i40e_tunnel_rule *rule = &pf->tunnel;
6735 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6738 "Failed to insert tunnel filter to hash table %d!",
6742 rule->hash_map[ret] = tunnel_filter;
6744 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6749 /* Delete a tunnel filter from the SW list */
6751 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6752 struct i40e_tunnel_filter_input *input)
6754 struct i40e_tunnel_rule *rule = &pf->tunnel;
6755 struct i40e_tunnel_filter *tunnel_filter;
6758 ret = rte_hash_del_key(rule->hash_table, input);
6761 "Failed to delete tunnel filter to hash table %d!",
6765 tunnel_filter = rule->hash_map[ret];
6766 rule->hash_map[ret] = NULL;
6768 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6769 rte_free(tunnel_filter);
6775 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6776 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6781 uint8_t i, tun_type = 0;
6782 /* internal varialbe to convert ipv6 byte order */
6783 uint32_t convert_ipv6[4];
6785 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6786 struct i40e_vsi *vsi = pf->main_vsi;
6787 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6788 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6789 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6790 struct i40e_tunnel_filter *tunnel, *node;
6791 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6793 cld_filter = rte_zmalloc("tunnel_filter",
6794 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6797 if (NULL == cld_filter) {
6798 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6801 pfilter = cld_filter;
6803 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6804 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6806 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6807 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6808 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6809 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6810 rte_memcpy(&pfilter->ipaddr.v4.data,
6811 &rte_cpu_to_le_32(ipv4_addr),
6812 sizeof(pfilter->ipaddr.v4.data));
6814 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6815 for (i = 0; i < 4; i++) {
6817 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6819 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6820 sizeof(pfilter->ipaddr.v6.data));
6823 /* check tunneled type */
6824 switch (tunnel_filter->tunnel_type) {
6825 case RTE_TUNNEL_TYPE_VXLAN:
6826 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6828 case RTE_TUNNEL_TYPE_NVGRE:
6829 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6831 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6832 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6835 /* Other tunnel types is not supported. */
6836 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6837 rte_free(cld_filter);
6841 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6844 rte_free(cld_filter);
6848 pfilter->flags |= rte_cpu_to_le_16(
6849 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6850 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6851 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6852 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6854 /* Check if there is the filter in SW list */
6855 memset(&check_filter, 0, sizeof(check_filter));
6856 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6857 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6859 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6863 if (!add && !node) {
6864 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6869 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6871 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6874 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6875 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6876 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6878 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6881 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6884 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6887 rte_free(cld_filter);
6892 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6896 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6897 if (pf->vxlan_ports[i] == port)
6905 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6909 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6911 idx = i40e_get_vxlan_port_idx(pf, port);
6913 /* Check if port already exists */
6915 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6919 /* Now check if there is space to add the new port */
6920 idx = i40e_get_vxlan_port_idx(pf, 0);
6923 "Maximum number of UDP ports reached, not adding port %d",
6928 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6931 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6935 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6938 /* New port: add it and mark its index in the bitmap */
6939 pf->vxlan_ports[idx] = port;
6940 pf->vxlan_bitmap |= (1 << idx);
6942 if (!(pf->flags & I40E_FLAG_VXLAN))
6943 pf->flags |= I40E_FLAG_VXLAN;
6949 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6952 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6954 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6955 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6959 idx = i40e_get_vxlan_port_idx(pf, port);
6962 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6966 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6967 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6971 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6974 pf->vxlan_ports[idx] = 0;
6975 pf->vxlan_bitmap &= ~(1 << idx);
6977 if (!pf->vxlan_bitmap)
6978 pf->flags &= ~I40E_FLAG_VXLAN;
6983 /* Add UDP tunneling port */
6985 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6986 struct rte_eth_udp_tunnel *udp_tunnel)
6989 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6991 if (udp_tunnel == NULL)
6994 switch (udp_tunnel->prot_type) {
6995 case RTE_TUNNEL_TYPE_VXLAN:
6996 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6999 case RTE_TUNNEL_TYPE_GENEVE:
7000 case RTE_TUNNEL_TYPE_TEREDO:
7001 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7006 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7014 /* Remove UDP tunneling port */
7016 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7017 struct rte_eth_udp_tunnel *udp_tunnel)
7020 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7022 if (udp_tunnel == NULL)
7025 switch (udp_tunnel->prot_type) {
7026 case RTE_TUNNEL_TYPE_VXLAN:
7027 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7029 case RTE_TUNNEL_TYPE_GENEVE:
7030 case RTE_TUNNEL_TYPE_TEREDO:
7031 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7035 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7043 /* Calculate the maximum number of contiguous PF queues that are configured */
7045 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7047 struct rte_eth_dev_data *data = pf->dev_data;
7049 struct i40e_rx_queue *rxq;
7052 for (i = 0; i < pf->lan_nb_qps; i++) {
7053 rxq = data->rx_queues[i];
7054 if (rxq && rxq->q_set)
7065 i40e_pf_config_rss(struct i40e_pf *pf)
7067 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7068 struct rte_eth_rss_conf rss_conf;
7069 uint32_t i, lut = 0;
7073 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7074 * It's necessary to calulate the actual PF queues that are configured.
7076 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7077 num = i40e_pf_calc_configured_queues_num(pf);
7079 num = pf->dev_data->nb_rx_queues;
7081 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7082 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7086 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7090 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7093 lut = (lut << 8) | (j & ((0x1 <<
7094 hw->func_caps.rss_table_entry_width) - 1));
7096 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7099 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7100 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7101 i40e_pf_disable_rss(pf);
7104 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7105 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7106 /* Random default keys */
7107 static uint32_t rss_key_default[] = {0x6b793944,
7108 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7109 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7110 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7112 rss_conf.rss_key = (uint8_t *)rss_key_default;
7113 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7117 return i40e_hw_rss_hash_set(pf, &rss_conf);
7121 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7122 struct rte_eth_tunnel_filter_conf *filter)
7124 if (pf == NULL || filter == NULL) {
7125 PMD_DRV_LOG(ERR, "Invalid parameter");
7129 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7130 PMD_DRV_LOG(ERR, "Invalid queue ID");
7134 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7135 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7139 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7140 (is_zero_ether_addr(&filter->outer_mac))) {
7141 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7145 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7146 (is_zero_ether_addr(&filter->inner_mac))) {
7147 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7154 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7155 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7157 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7162 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7163 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7166 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7167 } else if (len == 4) {
7168 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7170 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7175 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7182 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7183 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7189 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7196 switch (cfg->cfg_type) {
7197 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7198 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7201 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7209 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7210 enum rte_filter_op filter_op,
7213 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7214 int ret = I40E_ERR_PARAM;
7216 switch (filter_op) {
7217 case RTE_ETH_FILTER_SET:
7218 ret = i40e_dev_global_config_set(hw,
7219 (struct rte_eth_global_cfg *)arg);
7222 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7230 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7231 enum rte_filter_op filter_op,
7234 struct rte_eth_tunnel_filter_conf *filter;
7235 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7236 int ret = I40E_SUCCESS;
7238 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7240 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7241 return I40E_ERR_PARAM;
7243 switch (filter_op) {
7244 case RTE_ETH_FILTER_NOP:
7245 if (!(pf->flags & I40E_FLAG_VXLAN))
7246 ret = I40E_NOT_SUPPORTED;
7248 case RTE_ETH_FILTER_ADD:
7249 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7251 case RTE_ETH_FILTER_DELETE:
7252 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7255 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7256 ret = I40E_ERR_PARAM;
7264 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7267 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7270 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7271 ret = i40e_pf_config_rss(pf);
7273 i40e_pf_disable_rss(pf);
7278 /* Get the symmetric hash enable configurations per port */
7280 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7282 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7284 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7287 /* Set the symmetric hash enable configurations per port */
7289 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7291 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7294 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7296 "Symmetric hash has already been enabled");
7299 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7301 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7303 "Symmetric hash has already been disabled");
7306 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7308 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7309 I40E_WRITE_FLUSH(hw);
7313 * Get global configurations of hash function type and symmetric hash enable
7314 * per flow type (pctype). Note that global configuration means it affects all
7315 * the ports on the same NIC.
7318 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7319 struct rte_eth_hash_global_conf *g_cfg)
7321 uint32_t reg, mask = I40E_FLOW_TYPES;
7323 enum i40e_filter_pctype pctype;
7325 memset(g_cfg, 0, sizeof(*g_cfg));
7326 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7327 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7328 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7330 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7331 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7332 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7334 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7335 if (!(mask & (1UL << i)))
7337 mask &= ~(1UL << i);
7338 /* Bit set indicats the coresponding flow type is supported */
7339 g_cfg->valid_bit_mask[0] |= (1UL << i);
7340 /* if flowtype is invalid, continue */
7341 if (!I40E_VALID_FLOW(i))
7343 pctype = i40e_flowtype_to_pctype(i);
7344 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7345 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7346 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7353 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7356 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7358 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7359 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7360 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7361 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7367 * As i40e supports less than 32 flow types, only first 32 bits need to
7370 mask0 = g_cfg->valid_bit_mask[0];
7371 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7373 /* Check if any unsupported flow type configured */
7374 if ((mask0 | i40e_mask) ^ i40e_mask)
7377 if (g_cfg->valid_bit_mask[i])
7385 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7391 * Set global configurations of hash function type and symmetric hash enable
7392 * per flow type (pctype). Note any modifying global configuration will affect
7393 * all the ports on the same NIC.
7396 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7397 struct rte_eth_hash_global_conf *g_cfg)
7402 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7403 enum i40e_filter_pctype pctype;
7405 /* Check the input parameters */
7406 ret = i40e_hash_global_config_check(g_cfg);
7410 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7411 if (!(mask0 & (1UL << i)))
7413 mask0 &= ~(1UL << i);
7414 /* if flowtype is invalid, continue */
7415 if (!I40E_VALID_FLOW(i))
7417 pctype = i40e_flowtype_to_pctype(i);
7418 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7419 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7420 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7423 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7424 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7426 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7428 "Hash function already set to Toeplitz");
7431 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7432 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7434 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7436 "Hash function already set to Simple XOR");
7439 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7441 /* Use the default, and keep it as it is */
7444 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7447 I40E_WRITE_FLUSH(hw);
7453 * Valid input sets for hash and flow director filters per PCTYPE
7456 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7457 enum rte_filter_type filter)
7461 static const uint64_t valid_hash_inset_table[] = {
7462 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7463 I40E_INSET_DMAC | I40E_INSET_SMAC |
7464 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7465 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7466 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7467 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7468 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7469 I40E_INSET_FLEX_PAYLOAD,
7470 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7471 I40E_INSET_DMAC | I40E_INSET_SMAC |
7472 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7473 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7474 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7475 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7476 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7477 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7478 I40E_INSET_FLEX_PAYLOAD,
7479 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7480 I40E_INSET_DMAC | I40E_INSET_SMAC |
7481 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7482 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7483 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7484 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7485 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7486 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7487 I40E_INSET_FLEX_PAYLOAD,
7488 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7489 I40E_INSET_DMAC | I40E_INSET_SMAC |
7490 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7491 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7492 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7493 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7494 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7495 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7496 I40E_INSET_FLEX_PAYLOAD,
7497 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7498 I40E_INSET_DMAC | I40E_INSET_SMAC |
7499 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7500 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7501 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7502 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7503 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7504 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7505 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7506 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7507 I40E_INSET_DMAC | I40E_INSET_SMAC |
7508 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7509 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7510 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7511 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7512 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7513 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7514 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7515 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7516 I40E_INSET_DMAC | I40E_INSET_SMAC |
7517 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7518 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7519 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7520 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7521 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7522 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7523 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7524 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7525 I40E_INSET_DMAC | I40E_INSET_SMAC |
7526 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7527 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7528 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7529 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7530 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7531 I40E_INSET_FLEX_PAYLOAD,
7532 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7533 I40E_INSET_DMAC | I40E_INSET_SMAC |
7534 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7535 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7536 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7537 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7538 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7539 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7540 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7541 I40E_INSET_DMAC | I40E_INSET_SMAC |
7542 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7543 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7544 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7545 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7546 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7547 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7548 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7549 I40E_INSET_DMAC | I40E_INSET_SMAC |
7550 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7551 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7552 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7553 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7554 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7555 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7556 I40E_INSET_FLEX_PAYLOAD,
7557 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7558 I40E_INSET_DMAC | I40E_INSET_SMAC |
7559 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7560 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7561 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7562 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7563 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7564 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7565 I40E_INSET_FLEX_PAYLOAD,
7566 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7567 I40E_INSET_DMAC | I40E_INSET_SMAC |
7568 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7569 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7570 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7571 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7572 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7573 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7574 I40E_INSET_FLEX_PAYLOAD,
7575 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7576 I40E_INSET_DMAC | I40E_INSET_SMAC |
7577 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7578 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7579 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7580 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7581 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7582 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7583 I40E_INSET_FLEX_PAYLOAD,
7584 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7585 I40E_INSET_DMAC | I40E_INSET_SMAC |
7586 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7587 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7588 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7589 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7590 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7591 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7592 I40E_INSET_FLEX_PAYLOAD,
7593 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7594 I40E_INSET_DMAC | I40E_INSET_SMAC |
7595 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7596 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7597 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7598 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7599 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7600 I40E_INSET_FLEX_PAYLOAD,
7601 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7602 I40E_INSET_DMAC | I40E_INSET_SMAC |
7603 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7604 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7605 I40E_INSET_FLEX_PAYLOAD,
7609 * Flow director supports only fields defined in
7610 * union rte_eth_fdir_flow.
7612 static const uint64_t valid_fdir_inset_table[] = {
7613 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7614 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7615 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7616 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7617 I40E_INSET_IPV4_TTL,
7618 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7619 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7620 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7621 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7622 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7623 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7624 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7625 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7626 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7627 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7628 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7629 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7630 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7631 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7632 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7633 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7634 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7635 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7636 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7637 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7638 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7639 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7640 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7641 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7642 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7643 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7644 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7645 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7646 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7647 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7649 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7650 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7651 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7652 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7653 I40E_INSET_IPV4_TTL,
7654 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7655 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7656 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7657 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7658 I40E_INSET_IPV6_HOP_LIMIT,
7659 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7660 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7661 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7662 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7663 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7664 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7665 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7666 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7667 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7668 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7669 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7670 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7671 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7672 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7673 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7674 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7675 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7676 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7677 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7678 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7679 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7680 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7681 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7682 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7683 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7684 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7685 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7686 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7687 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7688 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7690 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7691 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7692 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7693 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7694 I40E_INSET_IPV6_HOP_LIMIT,
7695 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7696 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7697 I40E_INSET_LAST_ETHER_TYPE,
7700 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7702 if (filter == RTE_ETH_FILTER_HASH)
7703 valid = valid_hash_inset_table[pctype];
7705 valid = valid_fdir_inset_table[pctype];
7711 * Validate if the input set is allowed for a specific PCTYPE
7714 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7715 enum rte_filter_type filter, uint64_t inset)
7719 valid = i40e_get_valid_input_set(pctype, filter);
7720 if (inset & (~valid))
7726 /* default input set fields combination per pctype */
7728 i40e_get_default_input_set(uint16_t pctype)
7730 static const uint64_t default_inset_table[] = {
7731 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7732 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7733 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7734 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7735 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7736 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7737 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7738 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7739 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7740 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7741 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7742 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7743 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7744 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7745 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7746 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7747 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7748 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7749 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7750 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7752 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7753 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7754 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7755 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7756 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7757 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7758 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7759 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7760 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7761 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7762 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7763 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7764 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7765 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7766 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7767 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7768 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7769 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7770 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7771 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7772 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7773 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7775 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7776 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7777 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7778 I40E_INSET_LAST_ETHER_TYPE,
7781 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7784 return default_inset_table[pctype];
7788 * Parse the input set from index to logical bit masks
7791 i40e_parse_input_set(uint64_t *inset,
7792 enum i40e_filter_pctype pctype,
7793 enum rte_eth_input_set_field *field,
7799 static const struct {
7800 enum rte_eth_input_set_field field;
7802 } inset_convert_table[] = {
7803 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7804 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7805 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7806 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7807 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7808 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7809 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7810 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7811 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7812 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7813 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7814 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7815 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7816 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7817 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7818 I40E_INSET_IPV6_NEXT_HDR},
7819 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7820 I40E_INSET_IPV6_HOP_LIMIT},
7821 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7822 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7823 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7824 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7825 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7826 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7827 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7828 I40E_INSET_SCTP_VT},
7829 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7830 I40E_INSET_TUNNEL_DMAC},
7831 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7832 I40E_INSET_VLAN_TUNNEL},
7833 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7834 I40E_INSET_TUNNEL_ID},
7835 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7836 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7837 I40E_INSET_FLEX_PAYLOAD_W1},
7838 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7839 I40E_INSET_FLEX_PAYLOAD_W2},
7840 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7841 I40E_INSET_FLEX_PAYLOAD_W3},
7842 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7843 I40E_INSET_FLEX_PAYLOAD_W4},
7844 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7845 I40E_INSET_FLEX_PAYLOAD_W5},
7846 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7847 I40E_INSET_FLEX_PAYLOAD_W6},
7848 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7849 I40E_INSET_FLEX_PAYLOAD_W7},
7850 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7851 I40E_INSET_FLEX_PAYLOAD_W8},
7854 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7857 /* Only one item allowed for default or all */
7859 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7860 *inset = i40e_get_default_input_set(pctype);
7862 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7863 *inset = I40E_INSET_NONE;
7868 for (i = 0, *inset = 0; i < size; i++) {
7869 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7870 if (field[i] == inset_convert_table[j].field) {
7871 *inset |= inset_convert_table[j].inset;
7876 /* It contains unsupported input set, return immediately */
7877 if (j == RTE_DIM(inset_convert_table))
7885 * Translate the input set from bit masks to register aware bit masks
7889 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7899 static const struct inset_map inset_map_common[] = {
7900 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7901 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7902 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7903 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7904 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7905 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7906 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7907 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7908 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7909 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7910 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7911 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7912 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7913 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7914 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7915 {I40E_INSET_TUNNEL_DMAC,
7916 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7917 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7918 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7919 {I40E_INSET_TUNNEL_SRC_PORT,
7920 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7921 {I40E_INSET_TUNNEL_DST_PORT,
7922 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7923 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7924 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7925 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7926 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7927 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7928 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7929 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7930 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7931 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7934 /* some different registers map in x722*/
7935 static const struct inset_map inset_map_diff_x722[] = {
7936 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7937 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7938 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7939 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7942 static const struct inset_map inset_map_diff_not_x722[] = {
7943 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7944 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7945 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7946 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7952 /* Translate input set to register aware inset */
7953 if (type == I40E_MAC_X722) {
7954 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7955 if (input & inset_map_diff_x722[i].inset)
7956 val |= inset_map_diff_x722[i].inset_reg;
7959 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7960 if (input & inset_map_diff_not_x722[i].inset)
7961 val |= inset_map_diff_not_x722[i].inset_reg;
7965 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7966 if (input & inset_map_common[i].inset)
7967 val |= inset_map_common[i].inset_reg;
7974 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7977 uint64_t inset_need_mask = inset;
7979 static const struct {
7982 } inset_mask_map[] = {
7983 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7984 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7985 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7986 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7987 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7988 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7989 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7990 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7993 if (!inset || !mask || !nb_elem)
7996 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7997 /* Clear the inset bit, if no MASK is required,
7998 * for example proto + ttl
8000 if ((inset & inset_mask_map[i].inset) ==
8001 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8002 inset_need_mask &= ~inset_mask_map[i].inset;
8003 if (!inset_need_mask)
8006 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8007 if ((inset_need_mask & inset_mask_map[i].inset) ==
8008 inset_mask_map[i].inset) {
8009 if (idx >= nb_elem) {
8010 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8013 mask[idx] = inset_mask_map[i].mask;
8022 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8024 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8026 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
8028 i40e_write_rx_ctl(hw, addr, val);
8029 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
8030 (uint32_t)i40e_read_rx_ctl(hw, addr));
8034 i40e_filter_input_set_init(struct i40e_pf *pf)
8036 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8037 enum i40e_filter_pctype pctype;
8038 uint64_t input_set, inset_reg;
8039 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8042 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8043 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8044 if (hw->mac.type == I40E_MAC_X722) {
8045 if (!I40E_VALID_PCTYPE_X722(pctype))
8048 if (!I40E_VALID_PCTYPE(pctype))
8052 input_set = i40e_get_default_input_set(pctype);
8054 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8055 I40E_INSET_MASK_NUM_REG);
8058 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8061 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8062 (uint32_t)(inset_reg & UINT32_MAX));
8063 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8064 (uint32_t)((inset_reg >>
8065 I40E_32_BIT_WIDTH) & UINT32_MAX));
8066 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8067 (uint32_t)(inset_reg & UINT32_MAX));
8068 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8069 (uint32_t)((inset_reg >>
8070 I40E_32_BIT_WIDTH) & UINT32_MAX));
8072 for (i = 0; i < num; i++) {
8073 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8075 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8078 /*clear unused mask registers of the pctype */
8079 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8080 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8082 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8085 I40E_WRITE_FLUSH(hw);
8087 /* store the default input set */
8088 pf->hash_input_set[pctype] = input_set;
8089 pf->fdir.input_set[pctype] = input_set;
8094 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8095 struct rte_eth_input_set_conf *conf)
8097 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8098 enum i40e_filter_pctype pctype;
8099 uint64_t input_set, inset_reg = 0;
8100 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8104 PMD_DRV_LOG(ERR, "Invalid pointer");
8107 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8108 conf->op != RTE_ETH_INPUT_SET_ADD) {
8109 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8113 if (!I40E_VALID_FLOW(conf->flow_type)) {
8114 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8118 if (hw->mac.type == I40E_MAC_X722) {
8119 /* get translated pctype value in fd pctype register */
8120 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8121 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8124 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8126 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8129 PMD_DRV_LOG(ERR, "Failed to parse input set");
8132 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8134 PMD_DRV_LOG(ERR, "Invalid input set");
8137 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8138 /* get inset value in register */
8139 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8140 inset_reg <<= I40E_32_BIT_WIDTH;
8141 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8142 input_set |= pf->hash_input_set[pctype];
8144 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8145 I40E_INSET_MASK_NUM_REG);
8149 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8151 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8152 (uint32_t)(inset_reg & UINT32_MAX));
8153 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8154 (uint32_t)((inset_reg >>
8155 I40E_32_BIT_WIDTH) & UINT32_MAX));
8157 for (i = 0; i < num; i++)
8158 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8160 /*clear unused mask registers of the pctype */
8161 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8162 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8164 I40E_WRITE_FLUSH(hw);
8166 pf->hash_input_set[pctype] = input_set;
8171 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8172 struct rte_eth_input_set_conf *conf)
8174 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8175 enum i40e_filter_pctype pctype;
8176 uint64_t input_set, inset_reg = 0;
8177 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8181 PMD_DRV_LOG(ERR, "Invalid pointer");
8184 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8185 conf->op != RTE_ETH_INPUT_SET_ADD) {
8186 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8190 if (!I40E_VALID_FLOW(conf->flow_type)) {
8191 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8195 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8197 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8200 PMD_DRV_LOG(ERR, "Failed to parse input set");
8203 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8205 PMD_DRV_LOG(ERR, "Invalid input set");
8209 /* get inset value in register */
8210 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8211 inset_reg <<= I40E_32_BIT_WIDTH;
8212 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8214 /* Can not change the inset reg for flex payload for fdir,
8215 * it is done by writing I40E_PRTQF_FD_FLXINSET
8216 * in i40e_set_flex_mask_on_pctype.
8218 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8219 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8221 input_set |= pf->fdir.input_set[pctype];
8222 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8223 I40E_INSET_MASK_NUM_REG);
8227 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8229 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8230 (uint32_t)(inset_reg & UINT32_MAX));
8231 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8232 (uint32_t)((inset_reg >>
8233 I40E_32_BIT_WIDTH) & UINT32_MAX));
8235 for (i = 0; i < num; i++)
8236 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8238 /*clear unused mask registers of the pctype */
8239 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8240 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8242 I40E_WRITE_FLUSH(hw);
8244 pf->fdir.input_set[pctype] = input_set;
8249 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8254 PMD_DRV_LOG(ERR, "Invalid pointer");
8258 switch (info->info_type) {
8259 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8260 i40e_get_symmetric_hash_enable_per_port(hw,
8261 &(info->info.enable));
8263 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8264 ret = i40e_get_hash_filter_global_config(hw,
8265 &(info->info.global_conf));
8268 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8278 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8283 PMD_DRV_LOG(ERR, "Invalid pointer");
8287 switch (info->info_type) {
8288 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8289 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8291 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8292 ret = i40e_set_hash_filter_global_config(hw,
8293 &(info->info.global_conf));
8295 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8296 ret = i40e_hash_filter_inset_select(hw,
8297 &(info->info.input_set_conf));
8301 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8310 /* Operations for hash function */
8312 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8313 enum rte_filter_op filter_op,
8316 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8319 switch (filter_op) {
8320 case RTE_ETH_FILTER_NOP:
8322 case RTE_ETH_FILTER_GET:
8323 ret = i40e_hash_filter_get(hw,
8324 (struct rte_eth_hash_filter_info *)arg);
8326 case RTE_ETH_FILTER_SET:
8327 ret = i40e_hash_filter_set(hw,
8328 (struct rte_eth_hash_filter_info *)arg);
8331 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8340 /* Convert ethertype filter structure */
8342 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8343 struct i40e_ethertype_filter *filter)
8345 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8346 filter->input.ether_type = input->ether_type;
8347 filter->flags = input->flags;
8348 filter->queue = input->queue;
8353 /* Check if there exists the ehtertype filter */
8354 struct i40e_ethertype_filter *
8355 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8356 const struct i40e_ethertype_filter_input *input)
8360 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8364 return ethertype_rule->hash_map[ret];
8367 /* Add ethertype filter in SW list */
8369 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8370 struct i40e_ethertype_filter *filter)
8372 struct i40e_ethertype_rule *rule = &pf->ethertype;
8375 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8378 "Failed to insert ethertype filter"
8379 " to hash table %d!",
8383 rule->hash_map[ret] = filter;
8385 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8390 /* Delete ethertype filter in SW list */
8392 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8393 struct i40e_ethertype_filter_input *input)
8395 struct i40e_ethertype_rule *rule = &pf->ethertype;
8396 struct i40e_ethertype_filter *filter;
8399 ret = rte_hash_del_key(rule->hash_table, input);
8402 "Failed to delete ethertype filter"
8403 " to hash table %d!",
8407 filter = rule->hash_map[ret];
8408 rule->hash_map[ret] = NULL;
8410 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8417 * Configure ethertype filter, which can director packet by filtering
8418 * with mac address and ether_type or only ether_type
8421 i40e_ethertype_filter_set(struct i40e_pf *pf,
8422 struct rte_eth_ethertype_filter *filter,
8425 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8426 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8427 struct i40e_ethertype_filter *ethertype_filter, *node;
8428 struct i40e_ethertype_filter check_filter;
8429 struct i40e_control_filter_stats stats;
8433 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8434 PMD_DRV_LOG(ERR, "Invalid queue ID");
8437 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8438 filter->ether_type == ETHER_TYPE_IPv6) {
8440 "unsupported ether_type(0x%04x) in control packet filter.",
8441 filter->ether_type);
8444 if (filter->ether_type == ETHER_TYPE_VLAN)
8445 PMD_DRV_LOG(WARNING,
8446 "filter vlan ether_type in first tag is not supported.");
8448 /* Check if there is the filter in SW list */
8449 memset(&check_filter, 0, sizeof(check_filter));
8450 i40e_ethertype_filter_convert(filter, &check_filter);
8451 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8452 &check_filter.input);
8454 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8458 if (!add && !node) {
8459 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8463 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8464 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8465 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8466 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8467 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8469 memset(&stats, 0, sizeof(stats));
8470 ret = i40e_aq_add_rem_control_packet_filter(hw,
8471 filter->mac_addr.addr_bytes,
8472 filter->ether_type, flags,
8474 filter->queue, add, &stats, NULL);
8477 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u\n",
8478 ret, stats.mac_etype_used, stats.etype_used,
8479 stats.mac_etype_free, stats.etype_free);
8483 /* Add or delete a filter in SW list */
8485 ethertype_filter = rte_zmalloc("ethertype_filter",
8486 sizeof(*ethertype_filter), 0);
8487 rte_memcpy(ethertype_filter, &check_filter,
8488 sizeof(check_filter));
8489 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8491 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8498 * Handle operations for ethertype filter.
8501 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8502 enum rte_filter_op filter_op,
8505 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8508 if (filter_op == RTE_ETH_FILTER_NOP)
8512 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8517 switch (filter_op) {
8518 case RTE_ETH_FILTER_ADD:
8519 ret = i40e_ethertype_filter_set(pf,
8520 (struct rte_eth_ethertype_filter *)arg,
8523 case RTE_ETH_FILTER_DELETE:
8524 ret = i40e_ethertype_filter_set(pf,
8525 (struct rte_eth_ethertype_filter *)arg,
8529 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8537 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8538 enum rte_filter_type filter_type,
8539 enum rte_filter_op filter_op,
8547 switch (filter_type) {
8548 case RTE_ETH_FILTER_NONE:
8549 /* For global configuration */
8550 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8552 case RTE_ETH_FILTER_HASH:
8553 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8555 case RTE_ETH_FILTER_MACVLAN:
8556 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8558 case RTE_ETH_FILTER_ETHERTYPE:
8559 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8561 case RTE_ETH_FILTER_TUNNEL:
8562 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8564 case RTE_ETH_FILTER_FDIR:
8565 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8567 case RTE_ETH_FILTER_GENERIC:
8568 if (filter_op != RTE_ETH_FILTER_GET)
8570 *(const void **)arg = &i40e_flow_ops;
8573 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8583 * Check and enable Extended Tag.
8584 * Enabling Extended Tag is important for 40G performance.
8587 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8589 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8593 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8596 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8600 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8601 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8606 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8609 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8613 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8614 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8617 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8618 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8621 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8628 * As some registers wouldn't be reset unless a global hardware reset,
8629 * hardware initialization is needed to put those registers into an
8630 * expected initial state.
8633 i40e_hw_init(struct rte_eth_dev *dev)
8635 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8637 i40e_enable_extended_tag(dev);
8639 /* clear the PF Queue Filter control register */
8640 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8642 /* Disable symmetric hash per port */
8643 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8646 enum i40e_filter_pctype
8647 i40e_flowtype_to_pctype(uint16_t flow_type)
8649 static const enum i40e_filter_pctype pctype_table[] = {
8650 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8651 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8652 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8653 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8654 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8655 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8656 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8657 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8658 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8659 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8660 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8661 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8662 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8663 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8664 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8665 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8666 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8667 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8668 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8671 return pctype_table[flow_type];
8675 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8677 static const uint16_t flowtype_table[] = {
8678 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8679 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8680 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8681 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8682 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8683 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8684 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8685 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8686 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8687 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8688 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8689 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8690 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8691 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8692 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8693 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8694 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8695 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8696 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8697 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8698 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8699 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8700 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8701 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8702 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8703 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8704 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8705 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8706 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8707 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8708 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8711 return flowtype_table[pctype];
8715 * On X710, performance number is far from the expectation on recent firmware
8716 * versions; on XL710, performance number is also far from the expectation on
8717 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8718 * mode is enabled and port MAC address is equal to the packet destination MAC
8719 * address. The fix for this issue may not be integrated in the following
8720 * firmware version. So the workaround in software driver is needed. It needs
8721 * to modify the initial values of 3 internal only registers for both X710 and
8722 * XL710. Note that the values for X710 or XL710 could be different, and the
8723 * workaround can be removed when it is fixed in firmware in the future.
8726 /* For both X710 and XL710 */
8727 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8728 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8730 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8731 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8734 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8736 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8737 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8740 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8742 enum i40e_status_code status;
8743 struct i40e_aq_get_phy_abilities_resp phy_ab;
8746 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8757 i40e_configure_registers(struct i40e_hw *hw)
8763 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8764 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8765 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8771 for (i = 0; i < RTE_DIM(reg_table); i++) {
8772 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8773 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8774 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8776 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8779 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8782 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8785 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8789 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8790 reg_table[i].addr, reg);
8791 if (reg == reg_table[i].val)
8794 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8795 reg_table[i].val, NULL);
8798 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8799 reg_table[i].val, reg_table[i].addr);
8802 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8803 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8807 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8808 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8809 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8810 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8812 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8817 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8818 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8822 /* Configure for double VLAN RX stripping */
8823 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8824 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8825 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8826 ret = i40e_aq_debug_write_register(hw,
8827 I40E_VSI_TSR(vsi->vsi_id),
8830 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8832 return I40E_ERR_CONFIG;
8836 /* Configure for double VLAN TX insertion */
8837 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8838 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8839 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8840 ret = i40e_aq_debug_write_register(hw,
8841 I40E_VSI_L2TAGSTXVALID(
8842 vsi->vsi_id), reg, NULL);
8845 "Failed to update VSI_L2TAGSTXVALID[%d]",
8847 return I40E_ERR_CONFIG;
8855 * i40e_aq_add_mirror_rule
8856 * @hw: pointer to the hardware structure
8857 * @seid: VEB seid to add mirror rule to
8858 * @dst_id: destination vsi seid
8859 * @entries: Buffer which contains the entities to be mirrored
8860 * @count: number of entities contained in the buffer
8861 * @rule_id:the rule_id of the rule to be added
8863 * Add a mirror rule for a given veb.
8866 static enum i40e_status_code
8867 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8868 uint16_t seid, uint16_t dst_id,
8869 uint16_t rule_type, uint16_t *entries,
8870 uint16_t count, uint16_t *rule_id)
8872 struct i40e_aq_desc desc;
8873 struct i40e_aqc_add_delete_mirror_rule cmd;
8874 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8875 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8878 enum i40e_status_code status;
8880 i40e_fill_default_direct_cmd_desc(&desc,
8881 i40e_aqc_opc_add_mirror_rule);
8882 memset(&cmd, 0, sizeof(cmd));
8884 buff_len = sizeof(uint16_t) * count;
8885 desc.datalen = rte_cpu_to_le_16(buff_len);
8887 desc.flags |= rte_cpu_to_le_16(
8888 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8889 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8890 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8891 cmd.num_entries = rte_cpu_to_le_16(count);
8892 cmd.seid = rte_cpu_to_le_16(seid);
8893 cmd.destination = rte_cpu_to_le_16(dst_id);
8895 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8896 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8898 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8899 hw->aq.asq_last_status, resp->rule_id,
8900 resp->mirror_rules_used, resp->mirror_rules_free);
8901 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8907 * i40e_aq_del_mirror_rule
8908 * @hw: pointer to the hardware structure
8909 * @seid: VEB seid to add mirror rule to
8910 * @entries: Buffer which contains the entities to be mirrored
8911 * @count: number of entities contained in the buffer
8912 * @rule_id:the rule_id of the rule to be delete
8914 * Delete a mirror rule for a given veb.
8917 static enum i40e_status_code
8918 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8919 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8920 uint16_t count, uint16_t rule_id)
8922 struct i40e_aq_desc desc;
8923 struct i40e_aqc_add_delete_mirror_rule cmd;
8924 uint16_t buff_len = 0;
8925 enum i40e_status_code status;
8928 i40e_fill_default_direct_cmd_desc(&desc,
8929 i40e_aqc_opc_delete_mirror_rule);
8930 memset(&cmd, 0, sizeof(cmd));
8931 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8932 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8934 cmd.num_entries = count;
8935 buff_len = sizeof(uint16_t) * count;
8936 desc.datalen = rte_cpu_to_le_16(buff_len);
8937 buff = (void *)entries;
8939 /* rule id is filled in destination field for deleting mirror rule */
8940 cmd.destination = rte_cpu_to_le_16(rule_id);
8942 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8943 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8944 cmd.seid = rte_cpu_to_le_16(seid);
8946 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8947 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8953 * i40e_mirror_rule_set
8954 * @dev: pointer to the hardware structure
8955 * @mirror_conf: mirror rule info
8956 * @sw_id: mirror rule's sw_id
8957 * @on: enable/disable
8959 * set a mirror rule.
8963 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8964 struct rte_eth_mirror_conf *mirror_conf,
8965 uint8_t sw_id, uint8_t on)
8967 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8968 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8969 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8970 struct i40e_mirror_rule *parent = NULL;
8971 uint16_t seid, dst_seid, rule_id;
8975 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8977 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8979 "mirror rule can not be configured without veb or vfs.");
8982 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8983 PMD_DRV_LOG(ERR, "mirror table is full.");
8986 if (mirror_conf->dst_pool > pf->vf_num) {
8987 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8988 mirror_conf->dst_pool);
8992 seid = pf->main_vsi->veb->seid;
8994 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8995 if (sw_id <= it->index) {
9001 if (mirr_rule && sw_id == mirr_rule->index) {
9003 PMD_DRV_LOG(ERR, "mirror rule exists.");
9006 ret = i40e_aq_del_mirror_rule(hw, seid,
9007 mirr_rule->rule_type,
9009 mirr_rule->num_entries, mirr_rule->id);
9012 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9013 ret, hw->aq.asq_last_status);
9016 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9017 rte_free(mirr_rule);
9018 pf->nb_mirror_rule--;
9022 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9026 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9027 sizeof(struct i40e_mirror_rule) , 0);
9029 PMD_DRV_LOG(ERR, "failed to allocate memory");
9030 return I40E_ERR_NO_MEMORY;
9032 switch (mirror_conf->rule_type) {
9033 case ETH_MIRROR_VLAN:
9034 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9035 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9036 mirr_rule->entries[j] =
9037 mirror_conf->vlan.vlan_id[i];
9042 PMD_DRV_LOG(ERR, "vlan is not specified.");
9043 rte_free(mirr_rule);
9046 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9048 case ETH_MIRROR_VIRTUAL_POOL_UP:
9049 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9050 /* check if the specified pool bit is out of range */
9051 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9052 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9053 rte_free(mirr_rule);
9056 for (i = 0, j = 0; i < pf->vf_num; i++) {
9057 if (mirror_conf->pool_mask & (1ULL << i)) {
9058 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9062 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9063 /* add pf vsi to entries */
9064 mirr_rule->entries[j] = pf->main_vsi_seid;
9068 PMD_DRV_LOG(ERR, "pool is not specified.");
9069 rte_free(mirr_rule);
9072 /* egress and ingress in aq commands means from switch but not port */
9073 mirr_rule->rule_type =
9074 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9075 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9076 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9078 case ETH_MIRROR_UPLINK_PORT:
9079 /* egress and ingress in aq commands means from switch but not port*/
9080 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9082 case ETH_MIRROR_DOWNLINK_PORT:
9083 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9086 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9087 mirror_conf->rule_type);
9088 rte_free(mirr_rule);
9092 /* If the dst_pool is equal to vf_num, consider it as PF */
9093 if (mirror_conf->dst_pool == pf->vf_num)
9094 dst_seid = pf->main_vsi_seid;
9096 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9098 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9099 mirr_rule->rule_type, mirr_rule->entries,
9103 "failed to add mirror rule: ret = %d, aq_err = %d.",
9104 ret, hw->aq.asq_last_status);
9105 rte_free(mirr_rule);
9109 mirr_rule->index = sw_id;
9110 mirr_rule->num_entries = j;
9111 mirr_rule->id = rule_id;
9112 mirr_rule->dst_vsi_seid = dst_seid;
9115 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9117 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9119 pf->nb_mirror_rule++;
9124 * i40e_mirror_rule_reset
9125 * @dev: pointer to the device
9126 * @sw_id: mirror rule's sw_id
9128 * reset a mirror rule.
9132 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9134 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9135 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9136 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9140 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9142 seid = pf->main_vsi->veb->seid;
9144 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9145 if (sw_id == it->index) {
9151 ret = i40e_aq_del_mirror_rule(hw, seid,
9152 mirr_rule->rule_type,
9154 mirr_rule->num_entries, mirr_rule->id);
9157 "failed to remove mirror rule: status = %d, aq_err = %d.",
9158 ret, hw->aq.asq_last_status);
9161 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9162 rte_free(mirr_rule);
9163 pf->nb_mirror_rule--;
9165 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9172 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9174 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9175 uint64_t systim_cycles;
9177 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9178 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9181 return systim_cycles;
9185 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9187 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9190 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9191 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9198 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9200 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9203 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9204 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9211 i40e_start_timecounters(struct rte_eth_dev *dev)
9213 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9214 struct i40e_adapter *adapter =
9215 (struct i40e_adapter *)dev->data->dev_private;
9216 struct rte_eth_link link;
9217 uint32_t tsync_inc_l;
9218 uint32_t tsync_inc_h;
9220 /* Get current link speed. */
9221 memset(&link, 0, sizeof(link));
9222 i40e_dev_link_update(dev, 1);
9223 rte_i40e_dev_atomic_read_link_status(dev, &link);
9225 switch (link.link_speed) {
9226 case ETH_SPEED_NUM_40G:
9227 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9228 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9230 case ETH_SPEED_NUM_10G:
9231 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9232 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9234 case ETH_SPEED_NUM_1G:
9235 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9236 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9243 /* Set the timesync increment value. */
9244 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9245 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9247 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9248 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9249 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9251 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9252 adapter->systime_tc.cc_shift = 0;
9253 adapter->systime_tc.nsec_mask = 0;
9255 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9256 adapter->rx_tstamp_tc.cc_shift = 0;
9257 adapter->rx_tstamp_tc.nsec_mask = 0;
9259 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9260 adapter->tx_tstamp_tc.cc_shift = 0;
9261 adapter->tx_tstamp_tc.nsec_mask = 0;
9265 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9267 struct i40e_adapter *adapter =
9268 (struct i40e_adapter *)dev->data->dev_private;
9270 adapter->systime_tc.nsec += delta;
9271 adapter->rx_tstamp_tc.nsec += delta;
9272 adapter->tx_tstamp_tc.nsec += delta;
9278 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9281 struct i40e_adapter *adapter =
9282 (struct i40e_adapter *)dev->data->dev_private;
9284 ns = rte_timespec_to_ns(ts);
9286 /* Set the timecounters to a new value. */
9287 adapter->systime_tc.nsec = ns;
9288 adapter->rx_tstamp_tc.nsec = ns;
9289 adapter->tx_tstamp_tc.nsec = ns;
9295 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9297 uint64_t ns, systime_cycles;
9298 struct i40e_adapter *adapter =
9299 (struct i40e_adapter *)dev->data->dev_private;
9301 systime_cycles = i40e_read_systime_cyclecounter(dev);
9302 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9303 *ts = rte_ns_to_timespec(ns);
9309 i40e_timesync_enable(struct rte_eth_dev *dev)
9311 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9312 uint32_t tsync_ctl_l;
9313 uint32_t tsync_ctl_h;
9315 /* Stop the timesync system time. */
9316 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9317 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9318 /* Reset the timesync system time value. */
9319 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9320 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9322 i40e_start_timecounters(dev);
9324 /* Clear timesync registers. */
9325 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9326 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9327 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9328 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9329 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9330 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9332 /* Enable timestamping of PTP packets. */
9333 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9334 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9336 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9337 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9338 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9340 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9341 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9347 i40e_timesync_disable(struct rte_eth_dev *dev)
9349 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9350 uint32_t tsync_ctl_l;
9351 uint32_t tsync_ctl_h;
9353 /* Disable timestamping of transmitted PTP packets. */
9354 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9355 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9357 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9358 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9360 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9361 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9363 /* Reset the timesync increment value. */
9364 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9365 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9371 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9372 struct timespec *timestamp, uint32_t flags)
9374 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9375 struct i40e_adapter *adapter =
9376 (struct i40e_adapter *)dev->data->dev_private;
9378 uint32_t sync_status;
9379 uint32_t index = flags & 0x03;
9380 uint64_t rx_tstamp_cycles;
9383 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9384 if ((sync_status & (1 << index)) == 0)
9387 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9388 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9389 *timestamp = rte_ns_to_timespec(ns);
9395 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9396 struct timespec *timestamp)
9398 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9399 struct i40e_adapter *adapter =
9400 (struct i40e_adapter *)dev->data->dev_private;
9402 uint32_t sync_status;
9403 uint64_t tx_tstamp_cycles;
9406 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9407 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9410 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9411 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9412 *timestamp = rte_ns_to_timespec(ns);
9418 * i40e_parse_dcb_configure - parse dcb configure from user
9419 * @dev: the device being configured
9420 * @dcb_cfg: pointer of the result of parse
9421 * @*tc_map: bit map of enabled traffic classes
9423 * Returns 0 on success, negative value on failure
9426 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9427 struct i40e_dcbx_config *dcb_cfg,
9430 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9431 uint8_t i, tc_bw, bw_lf;
9433 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9435 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9436 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9437 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9441 /* assume each tc has the same bw */
9442 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9443 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9444 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9445 /* to ensure the sum of tcbw is equal to 100 */
9446 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9447 for (i = 0; i < bw_lf; i++)
9448 dcb_cfg->etscfg.tcbwtable[i]++;
9450 /* assume each tc has the same Transmission Selection Algorithm */
9451 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9452 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9454 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9455 dcb_cfg->etscfg.prioritytable[i] =
9456 dcb_rx_conf->dcb_tc[i];
9458 /* FW needs one App to configure HW */
9459 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9460 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9461 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9462 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9464 if (dcb_rx_conf->nb_tcs == 0)
9465 *tc_map = 1; /* tc0 only */
9467 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9469 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9470 dcb_cfg->pfc.willing = 0;
9471 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9472 dcb_cfg->pfc.pfcenable = *tc_map;
9478 static enum i40e_status_code
9479 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9480 struct i40e_aqc_vsi_properties_data *info,
9481 uint8_t enabled_tcmap)
9483 enum i40e_status_code ret;
9484 int i, total_tc = 0;
9485 uint16_t qpnum_per_tc, bsf, qp_idx;
9486 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9487 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9488 uint16_t used_queues;
9490 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9491 if (ret != I40E_SUCCESS)
9494 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9495 if (enabled_tcmap & (1 << i))
9500 vsi->enabled_tc = enabled_tcmap;
9502 /* different VSI has different queues assigned */
9503 if (vsi->type == I40E_VSI_MAIN)
9504 used_queues = dev_data->nb_rx_queues -
9505 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9506 else if (vsi->type == I40E_VSI_VMDQ2)
9507 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9509 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9510 return I40E_ERR_NO_AVAILABLE_VSI;
9513 qpnum_per_tc = used_queues / total_tc;
9514 /* Number of queues per enabled TC */
9515 if (qpnum_per_tc == 0) {
9516 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9517 return I40E_ERR_INVALID_QP_ID;
9519 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9521 bsf = rte_bsf32(qpnum_per_tc);
9524 * Configure TC and queue mapping parameters, for enabled TC,
9525 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9526 * default queue will serve it.
9529 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9530 if (vsi->enabled_tc & (1 << i)) {
9531 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9532 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9533 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9534 qp_idx += qpnum_per_tc;
9536 info->tc_mapping[i] = 0;
9539 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9540 if (vsi->type == I40E_VSI_SRIOV) {
9541 info->mapping_flags |=
9542 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9543 for (i = 0; i < vsi->nb_qps; i++)
9544 info->queue_mapping[i] =
9545 rte_cpu_to_le_16(vsi->base_queue + i);
9547 info->mapping_flags |=
9548 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9549 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9551 info->valid_sections |=
9552 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9554 return I40E_SUCCESS;
9558 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9559 * @veb: VEB to be configured
9560 * @tc_map: enabled TC bitmap
9562 * Returns 0 on success, negative value on failure
9564 static enum i40e_status_code
9565 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9567 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9568 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9569 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9570 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9571 enum i40e_status_code ret = I40E_SUCCESS;
9575 /* Check if enabled_tc is same as existing or new TCs */
9576 if (veb->enabled_tc == tc_map)
9579 /* configure tc bandwidth */
9580 memset(&veb_bw, 0, sizeof(veb_bw));
9581 veb_bw.tc_valid_bits = tc_map;
9582 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9583 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9584 if (tc_map & BIT_ULL(i))
9585 veb_bw.tc_bw_share_credits[i] = 1;
9587 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9591 "AQ command Config switch_comp BW allocation per TC failed = %d",
9592 hw->aq.asq_last_status);
9596 memset(&ets_query, 0, sizeof(ets_query));
9597 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9599 if (ret != I40E_SUCCESS) {
9601 "Failed to get switch_comp ETS configuration %u",
9602 hw->aq.asq_last_status);
9605 memset(&bw_query, 0, sizeof(bw_query));
9606 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9608 if (ret != I40E_SUCCESS) {
9610 "Failed to get switch_comp bandwidth configuration %u",
9611 hw->aq.asq_last_status);
9615 /* store and print out BW info */
9616 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9617 veb->bw_info.bw_max = ets_query.tc_bw_max;
9618 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9619 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9620 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9621 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9623 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9624 veb->bw_info.bw_ets_share_credits[i] =
9625 bw_query.tc_bw_share_credits[i];
9626 veb->bw_info.bw_ets_credits[i] =
9627 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9628 /* 4 bits per TC, 4th bit is reserved */
9629 veb->bw_info.bw_ets_max[i] =
9630 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9631 RTE_LEN2MASK(3, uint8_t));
9632 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9633 veb->bw_info.bw_ets_share_credits[i]);
9634 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9635 veb->bw_info.bw_ets_credits[i]);
9636 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9637 veb->bw_info.bw_ets_max[i]);
9640 veb->enabled_tc = tc_map;
9647 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9648 * @vsi: VSI to be configured
9649 * @tc_map: enabled TC bitmap
9651 * Returns 0 on success, negative value on failure
9653 static enum i40e_status_code
9654 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9656 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9657 struct i40e_vsi_context ctxt;
9658 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9659 enum i40e_status_code ret = I40E_SUCCESS;
9662 /* Check if enabled_tc is same as existing or new TCs */
9663 if (vsi->enabled_tc == tc_map)
9666 /* configure tc bandwidth */
9667 memset(&bw_data, 0, sizeof(bw_data));
9668 bw_data.tc_valid_bits = tc_map;
9669 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9670 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9671 if (tc_map & BIT_ULL(i))
9672 bw_data.tc_bw_credits[i] = 1;
9674 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9677 "AQ command Config VSI BW allocation per TC failed = %d",
9678 hw->aq.asq_last_status);
9681 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9682 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9684 /* Update Queue Pairs Mapping for currently enabled UPs */
9685 ctxt.seid = vsi->seid;
9686 ctxt.pf_num = hw->pf_id;
9688 ctxt.uplink_seid = vsi->uplink_seid;
9689 ctxt.info = vsi->info;
9691 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9695 /* Update the VSI after updating the VSI queue-mapping information */
9696 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9698 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9699 hw->aq.asq_last_status);
9702 /* update the local VSI info with updated queue map */
9703 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9704 sizeof(vsi->info.tc_mapping));
9705 (void)rte_memcpy(&vsi->info.queue_mapping,
9706 &ctxt.info.queue_mapping,
9707 sizeof(vsi->info.queue_mapping));
9708 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9709 vsi->info.valid_sections = 0;
9711 /* query and update current VSI BW information */
9712 ret = i40e_vsi_get_bw_config(vsi);
9715 "Failed updating vsi bw info, err %s aq_err %s",
9716 i40e_stat_str(hw, ret),
9717 i40e_aq_str(hw, hw->aq.asq_last_status));
9721 vsi->enabled_tc = tc_map;
9728 * i40e_dcb_hw_configure - program the dcb setting to hw
9729 * @pf: pf the configuration is taken on
9730 * @new_cfg: new configuration
9731 * @tc_map: enabled TC bitmap
9733 * Returns 0 on success, negative value on failure
9735 static enum i40e_status_code
9736 i40e_dcb_hw_configure(struct i40e_pf *pf,
9737 struct i40e_dcbx_config *new_cfg,
9740 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9741 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9742 struct i40e_vsi *main_vsi = pf->main_vsi;
9743 struct i40e_vsi_list *vsi_list;
9744 enum i40e_status_code ret;
9748 /* Use the FW API if FW > v4.4*/
9749 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9750 (hw->aq.fw_maj_ver >= 5))) {
9752 "FW < v4.4, can not use FW LLDP API to configure DCB");
9753 return I40E_ERR_FIRMWARE_API_VERSION;
9756 /* Check if need reconfiguration */
9757 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9758 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9759 return I40E_SUCCESS;
9762 /* Copy the new config to the current config */
9763 *old_cfg = *new_cfg;
9764 old_cfg->etsrec = old_cfg->etscfg;
9765 ret = i40e_set_dcb_config(hw);
9768 "Set DCB Config failed, err %s aq_err %s\n",
9769 i40e_stat_str(hw, ret),
9770 i40e_aq_str(hw, hw->aq.asq_last_status));
9773 /* set receive Arbiter to RR mode and ETS scheme by default */
9774 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9775 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9776 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9777 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9778 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9779 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9780 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9781 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9782 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9783 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9784 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9785 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9786 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9788 /* get local mib to check whether it is configured correctly */
9790 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9791 /* Get Local DCB Config */
9792 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9793 &hw->local_dcbx_config);
9795 /* if Veb is created, need to update TC of it at first */
9796 if (main_vsi->veb) {
9797 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9799 PMD_INIT_LOG(WARNING,
9800 "Failed configuring TC for VEB seid=%d\n",
9801 main_vsi->veb->seid);
9803 /* Update each VSI */
9804 i40e_vsi_config_tc(main_vsi, tc_map);
9805 if (main_vsi->veb) {
9806 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9807 /* Beside main VSI and VMDQ VSIs, only enable default
9810 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9811 ret = i40e_vsi_config_tc(vsi_list->vsi,
9814 ret = i40e_vsi_config_tc(vsi_list->vsi,
9815 I40E_DEFAULT_TCMAP);
9817 PMD_INIT_LOG(WARNING,
9818 "Failed configuring TC for VSI seid=%d\n",
9819 vsi_list->vsi->seid);
9823 return I40E_SUCCESS;
9827 * i40e_dcb_init_configure - initial dcb config
9828 * @dev: device being configured
9829 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9831 * Returns 0 on success, negative value on failure
9834 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9836 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9837 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9840 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9841 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9845 /* DCB initialization:
9846 * Update DCB configuration from the Firmware and configure
9847 * LLDP MIB change event.
9849 if (sw_dcb == TRUE) {
9850 ret = i40e_init_dcb(hw);
9851 /* If lldp agent is stopped, the return value from
9852 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9853 * adminq status. Otherwise, it should return success.
9855 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9856 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9857 memset(&hw->local_dcbx_config, 0,
9858 sizeof(struct i40e_dcbx_config));
9859 /* set dcb default configuration */
9860 hw->local_dcbx_config.etscfg.willing = 0;
9861 hw->local_dcbx_config.etscfg.maxtcs = 0;
9862 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9863 hw->local_dcbx_config.etscfg.tsatable[0] =
9865 hw->local_dcbx_config.etsrec =
9866 hw->local_dcbx_config.etscfg;
9867 hw->local_dcbx_config.pfc.willing = 0;
9868 hw->local_dcbx_config.pfc.pfccap =
9869 I40E_MAX_TRAFFIC_CLASS;
9870 /* FW needs one App to configure HW */
9871 hw->local_dcbx_config.numapps = 1;
9872 hw->local_dcbx_config.app[0].selector =
9873 I40E_APP_SEL_ETHTYPE;
9874 hw->local_dcbx_config.app[0].priority = 3;
9875 hw->local_dcbx_config.app[0].protocolid =
9876 I40E_APP_PROTOID_FCOE;
9877 ret = i40e_set_dcb_config(hw);
9880 "default dcb config fails. err = %d, aq_err = %d.",
9881 ret, hw->aq.asq_last_status);
9886 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9887 ret, hw->aq.asq_last_status);
9891 ret = i40e_aq_start_lldp(hw, NULL);
9892 if (ret != I40E_SUCCESS)
9893 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9895 ret = i40e_init_dcb(hw);
9897 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9899 "HW doesn't support DCBX offload.");
9904 "DCBX configuration failed, err = %d, aq_err = %d.",
9905 ret, hw->aq.asq_last_status);
9913 * i40e_dcb_setup - setup dcb related config
9914 * @dev: device being configured
9916 * Returns 0 on success, negative value on failure
9919 i40e_dcb_setup(struct rte_eth_dev *dev)
9921 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9922 struct i40e_dcbx_config dcb_cfg;
9926 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9927 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9931 if (pf->vf_num != 0)
9932 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9934 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9936 PMD_INIT_LOG(ERR, "invalid dcb config");
9939 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9941 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9949 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9950 struct rte_eth_dcb_info *dcb_info)
9952 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9953 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9954 struct i40e_vsi *vsi = pf->main_vsi;
9955 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9956 uint16_t bsf, tc_mapping;
9959 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9960 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9962 dcb_info->nb_tcs = 1;
9963 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9964 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9965 for (i = 0; i < dcb_info->nb_tcs; i++)
9966 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9968 /* get queue mapping if vmdq is disabled */
9969 if (!pf->nb_cfg_vmdq_vsi) {
9970 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9971 if (!(vsi->enabled_tc & (1 << i)))
9973 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9974 dcb_info->tc_queue.tc_rxq[j][i].base =
9975 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9976 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9977 dcb_info->tc_queue.tc_txq[j][i].base =
9978 dcb_info->tc_queue.tc_rxq[j][i].base;
9979 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9980 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9981 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9982 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9983 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9988 /* get queue mapping if vmdq is enabled */
9990 vsi = pf->vmdq[j].vsi;
9991 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9992 if (!(vsi->enabled_tc & (1 << i)))
9994 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9995 dcb_info->tc_queue.tc_rxq[j][i].base =
9996 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9997 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9998 dcb_info->tc_queue.tc_txq[j][i].base =
9999 dcb_info->tc_queue.tc_rxq[j][i].base;
10000 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10001 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10002 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10003 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10004 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10007 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10012 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10014 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10015 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10016 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10017 uint16_t interval =
10018 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10019 uint16_t msix_intr;
10021 msix_intr = intr_handle->intr_vec[queue_id];
10022 if (msix_intr == I40E_MISC_VEC_ID)
10023 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10024 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10025 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10026 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10028 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10031 I40E_PFINT_DYN_CTLN(msix_intr -
10032 I40E_RX_VEC_START),
10033 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10034 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10035 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10037 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10039 I40E_WRITE_FLUSH(hw);
10040 rte_intr_enable(&pci_dev->intr_handle);
10046 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10048 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10049 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10050 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10051 uint16_t msix_intr;
10053 msix_intr = intr_handle->intr_vec[queue_id];
10054 if (msix_intr == I40E_MISC_VEC_ID)
10055 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10058 I40E_PFINT_DYN_CTLN(msix_intr -
10059 I40E_RX_VEC_START),
10061 I40E_WRITE_FLUSH(hw);
10066 static int i40e_get_regs(struct rte_eth_dev *dev,
10067 struct rte_dev_reg_info *regs)
10069 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10070 uint32_t *ptr_data = regs->data;
10071 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10072 const struct i40e_reg_info *reg_info;
10074 if (ptr_data == NULL) {
10075 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10076 regs->width = sizeof(uint32_t);
10080 /* The first few registers have to be read using AQ operations */
10082 while (i40e_regs_adminq[reg_idx].name) {
10083 reg_info = &i40e_regs_adminq[reg_idx++];
10084 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10086 arr_idx2 <= reg_info->count2;
10088 reg_offset = arr_idx * reg_info->stride1 +
10089 arr_idx2 * reg_info->stride2;
10090 reg_offset += reg_info->base_addr;
10091 ptr_data[reg_offset >> 2] =
10092 i40e_read_rx_ctl(hw, reg_offset);
10096 /* The remaining registers can be read using primitives */
10098 while (i40e_regs_others[reg_idx].name) {
10099 reg_info = &i40e_regs_others[reg_idx++];
10100 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10102 arr_idx2 <= reg_info->count2;
10104 reg_offset = arr_idx * reg_info->stride1 +
10105 arr_idx2 * reg_info->stride2;
10106 reg_offset += reg_info->base_addr;
10107 ptr_data[reg_offset >> 2] =
10108 I40E_READ_REG(hw, reg_offset);
10115 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10117 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10119 /* Convert word count to byte count */
10120 return hw->nvm.sr_size << 1;
10123 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10124 struct rte_dev_eeprom_info *eeprom)
10126 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10127 uint16_t *data = eeprom->data;
10128 uint16_t offset, length, cnt_words;
10131 offset = eeprom->offset >> 1;
10132 length = eeprom->length >> 1;
10133 cnt_words = length;
10135 if (offset > hw->nvm.sr_size ||
10136 offset + length > hw->nvm.sr_size) {
10137 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10141 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10143 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10144 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10145 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10152 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10153 struct ether_addr *mac_addr)
10155 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10157 if (!is_valid_assigned_ether_addr(mac_addr)) {
10158 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10162 /* Flags: 0x3 updates port address */
10163 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10167 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10169 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10170 struct rte_eth_dev_data *dev_data = pf->dev_data;
10171 uint32_t frame_size = mtu + ETHER_HDR_LEN
10172 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10175 /* check if mtu is within the allowed range */
10176 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10179 /* mtu setting is forbidden if port is start */
10180 if (dev_data->dev_started) {
10182 "port %d must be stopped before configuration\n",
10183 dev_data->port_id);
10187 if (frame_size > ETHER_MAX_LEN)
10188 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10190 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10192 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10197 /* Restore ethertype filter */
10199 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10201 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10202 struct i40e_ethertype_filter_list
10203 *ethertype_list = &pf->ethertype.ethertype_list;
10204 struct i40e_ethertype_filter *f;
10205 struct i40e_control_filter_stats stats;
10208 TAILQ_FOREACH(f, ethertype_list, rules) {
10210 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10211 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10212 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10213 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10214 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10216 memset(&stats, 0, sizeof(stats));
10217 i40e_aq_add_rem_control_packet_filter(hw,
10218 f->input.mac_addr.addr_bytes,
10219 f->input.ether_type,
10220 flags, pf->main_vsi->seid,
10221 f->queue, 1, &stats, NULL);
10223 PMD_DRV_LOG(INFO, "Ethertype filter:"
10224 " mac_etype_used = %u, etype_used = %u,"
10225 " mac_etype_free = %u, etype_free = %u\n",
10226 stats.mac_etype_used, stats.etype_used,
10227 stats.mac_etype_free, stats.etype_free);
10230 /* Restore tunnel filter */
10232 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10234 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10235 struct i40e_vsi *vsi = pf->main_vsi;
10236 struct i40e_tunnel_filter_list
10237 *tunnel_list = &pf->tunnel.tunnel_list;
10238 struct i40e_tunnel_filter *f;
10239 struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10241 TAILQ_FOREACH(f, tunnel_list, rules) {
10242 memset(&cld_filter, 0, sizeof(cld_filter));
10243 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10244 cld_filter.queue_number = f->queue;
10245 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10250 i40e_filter_restore(struct i40e_pf *pf)
10252 i40e_ethertype_filter_restore(pf);
10253 i40e_tunnel_filter_restore(pf);
10254 i40e_fdir_filter_restore(pf);
10258 is_i40e_pmd(const char *driver_name)
10260 if (!strstr(driver_name, "i40e"))
10263 if (strstr(driver_name, "i40e_vf"))
10270 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10272 struct rte_eth_dev *dev;
10273 struct i40e_pf *pf;
10275 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10277 dev = &rte_eth_devices[port];
10279 if (is_i40e_pmd(dev->data->drv_name))
10282 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10284 if (vf >= pf->vf_num || !pf->vfs) {
10285 PMD_DRV_LOG(ERR, "Invalid argument.");
10289 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10295 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10297 struct rte_eth_dev *dev;
10298 struct i40e_pf *pf;
10299 struct i40e_vsi *vsi;
10300 struct i40e_hw *hw;
10301 struct i40e_vsi_context ctxt;
10304 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10306 dev = &rte_eth_devices[port];
10308 if (is_i40e_pmd(dev->data->drv_name))
10311 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10313 if (vf_id >= pf->vf_num || !pf->vfs) {
10314 PMD_DRV_LOG(ERR, "Invalid argument.");
10318 vsi = pf->vfs[vf_id].vsi;
10320 PMD_DRV_LOG(ERR, "Invalid VSI.");
10324 /* Check if it has been already on or off */
10325 if (vsi->info.valid_sections &
10326 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10328 if ((vsi->info.sec_flags &
10329 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10330 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10331 return 0; /* already on */
10333 if ((vsi->info.sec_flags &
10334 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10335 return 0; /* already off */
10339 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10341 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10343 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10345 memset(&ctxt, 0, sizeof(ctxt));
10346 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10347 ctxt.seid = vsi->seid;
10349 hw = I40E_VSI_TO_HW(vsi);
10350 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10351 if (ret != I40E_SUCCESS) {
10353 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10360 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10364 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10365 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10368 for (j = 0; j < I40E_VFTA_SIZE; j++) {
10372 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10373 if (!(vsi->vfta[j] & (1 << k)))
10376 vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10380 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10382 ret = i40e_aq_add_vlan(hw, vsi->seid,
10383 &vlan_data, 1, NULL);
10385 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10386 &vlan_data, 1, NULL);
10387 if (ret != I40E_SUCCESS) {
10389 "Failed to add/rm vlan filter");
10395 return I40E_SUCCESS;
10399 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10401 struct rte_eth_dev *dev;
10402 struct i40e_pf *pf;
10403 struct i40e_vsi *vsi;
10404 struct i40e_hw *hw;
10405 struct i40e_vsi_context ctxt;
10408 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10410 dev = &rte_eth_devices[port];
10412 if (is_i40e_pmd(dev->data->drv_name))
10415 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10417 if (vf_id >= pf->vf_num || !pf->vfs) {
10418 PMD_DRV_LOG(ERR, "Invalid argument.");
10422 vsi = pf->vfs[vf_id].vsi;
10424 PMD_DRV_LOG(ERR, "Invalid VSI.");
10428 /* Check if it has been already on or off */
10429 if (vsi->vlan_anti_spoof_on == on)
10430 return 0; /* already on or off */
10432 vsi->vlan_anti_spoof_on = on;
10433 ret = i40e_add_rm_all_vlan_filter(vsi, on);
10435 PMD_DRV_LOG(ERR, "Failed to remove VLAN filters.");
10439 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10441 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10443 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10445 memset(&ctxt, 0, sizeof(ctxt));
10446 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10447 ctxt.seid = vsi->seid;
10449 hw = I40E_VSI_TO_HW(vsi);
10450 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10451 if (ret != I40E_SUCCESS) {
10453 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10460 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10462 struct i40e_mac_filter *f;
10463 struct i40e_macvlan_filter *mv_f;
10465 enum rte_mac_filter_type filter_type;
10466 int ret = I40E_SUCCESS;
10469 /* remove all the MACs */
10470 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10471 vlan_num = vsi->vlan_num;
10472 filter_type = f->mac_info.filter_type;
10473 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10474 filter_type == RTE_MACVLAN_HASH_MATCH) {
10475 if (vlan_num == 0) {
10477 "VLAN number shouldn't be 0\n");
10478 return I40E_ERR_PARAM;
10480 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10481 filter_type == RTE_MAC_HASH_MATCH)
10484 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10486 PMD_DRV_LOG(ERR, "failed to allocate memory");
10487 return I40E_ERR_NO_MEMORY;
10490 for (i = 0; i < vlan_num; i++) {
10491 mv_f[i].filter_type = filter_type;
10492 (void)rte_memcpy(&mv_f[i].macaddr,
10493 &f->mac_info.mac_addr,
10496 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10497 filter_type == RTE_MACVLAN_HASH_MATCH) {
10498 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10499 &f->mac_info.mac_addr);
10500 if (ret != I40E_SUCCESS) {
10506 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10507 if (ret != I40E_SUCCESS) {
10513 ret = I40E_SUCCESS;
10520 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10522 struct i40e_mac_filter *f;
10523 struct i40e_macvlan_filter *mv_f;
10524 int i, vlan_num = 0;
10525 int ret = I40E_SUCCESS;
10528 /* restore all the MACs */
10529 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10530 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10531 (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10533 * If vlan_num is 0, that's the first time to add mac,
10534 * set mask for vlan_id 0.
10536 if (vsi->vlan_num == 0) {
10537 i40e_set_vlan_filter(vsi, 0, 1);
10540 vlan_num = vsi->vlan_num;
10541 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10542 (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10545 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10547 PMD_DRV_LOG(ERR, "failed to allocate memory");
10548 return I40E_ERR_NO_MEMORY;
10551 for (i = 0; i < vlan_num; i++) {
10552 mv_f[i].filter_type = f->mac_info.filter_type;
10553 (void)rte_memcpy(&mv_f[i].macaddr,
10554 &f->mac_info.mac_addr,
10558 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10559 f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10560 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10561 &f->mac_info.mac_addr);
10562 if (ret != I40E_SUCCESS) {
10568 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10569 if (ret != I40E_SUCCESS) {
10575 ret = I40E_SUCCESS;
10582 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10584 struct i40e_vsi_context ctxt;
10585 struct i40e_hw *hw;
10591 hw = I40E_VSI_TO_HW(vsi);
10593 /* Use the FW API if FW >= v5.0 */
10594 if (hw->aq.fw_maj_ver < 5) {
10595 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10599 /* Check if it has been already on or off */
10600 if (vsi->info.valid_sections &
10601 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10603 if ((vsi->info.switch_id &
10604 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10605 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10606 return 0; /* already on */
10608 if ((vsi->info.switch_id &
10609 I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10610 return 0; /* already off */
10614 /* remove all the MAC and VLAN first */
10615 ret = i40e_vsi_rm_mac_filter(vsi);
10617 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10620 if (vsi->vlan_anti_spoof_on) {
10621 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10623 PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10628 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10630 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10632 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10634 memset(&ctxt, 0, sizeof(ctxt));
10635 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10636 ctxt.seid = vsi->seid;
10638 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10639 if (ret != I40E_SUCCESS) {
10640 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10644 /* add all the MAC and VLAN back */
10645 ret = i40e_vsi_restore_mac_filter(vsi);
10648 if (vsi->vlan_anti_spoof_on) {
10649 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10658 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10660 struct rte_eth_dev *dev;
10661 struct i40e_pf *pf;
10662 struct i40e_pf_vf *vf;
10663 struct i40e_vsi *vsi;
10667 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10669 dev = &rte_eth_devices[port];
10671 if (is_i40e_pmd(dev->data->drv_name))
10674 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10676 /* setup PF TX loopback */
10677 vsi = pf->main_vsi;
10678 ret = i40e_vsi_set_tx_loopback(vsi, on);
10682 /* setup TX loopback for all the VFs */
10684 /* if no VF, do nothing. */
10688 for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10689 vf = &pf->vfs[vf_id];
10692 ret = i40e_vsi_set_tx_loopback(vsi, on);
10701 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10703 struct rte_eth_dev *dev;
10704 struct i40e_pf *pf;
10705 struct i40e_vsi *vsi;
10706 struct i40e_hw *hw;
10709 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10711 dev = &rte_eth_devices[port];
10713 if (is_i40e_pmd(dev->data->drv_name))
10716 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10718 if (vf_id >= pf->vf_num || !pf->vfs) {
10719 PMD_DRV_LOG(ERR, "Invalid argument.");
10723 vsi = pf->vfs[vf_id].vsi;
10725 PMD_DRV_LOG(ERR, "Invalid VSI.");
10729 hw = I40E_VSI_TO_HW(vsi);
10731 ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10733 if (ret != I40E_SUCCESS) {
10735 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10742 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10744 struct rte_eth_dev *dev;
10745 struct i40e_pf *pf;
10746 struct i40e_vsi *vsi;
10747 struct i40e_hw *hw;
10750 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10752 dev = &rte_eth_devices[port];
10754 if (is_i40e_pmd(dev->data->drv_name))
10757 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10759 if (vf_id >= pf->vf_num || !pf->vfs) {
10760 PMD_DRV_LOG(ERR, "Invalid argument.");
10764 vsi = pf->vfs[vf_id].vsi;
10766 PMD_DRV_LOG(ERR, "Invalid VSI.");
10770 hw = I40E_VSI_TO_HW(vsi);
10772 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10774 if (ret != I40E_SUCCESS) {
10776 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10783 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
10784 struct ether_addr *mac_addr)
10786 struct i40e_mac_filter *f;
10787 struct rte_eth_dev *dev;
10788 struct i40e_pf_vf *vf;
10789 struct i40e_vsi *vsi;
10790 struct i40e_pf *pf;
10793 if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
10796 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10798 dev = &rte_eth_devices[port];
10800 if (is_i40e_pmd(dev->data->drv_name))
10803 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10805 if (vf_id >= pf->vf_num || !pf->vfs)
10808 vf = &pf->vfs[vf_id];
10811 PMD_DRV_LOG(ERR, "Invalid VSI.");
10815 ether_addr_copy(mac_addr, &vf->mac_addr);
10817 /* Remove all existing mac */
10818 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
10819 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
10824 /* Set vlan strip on/off for specific VF from host */
10826 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
10828 struct rte_eth_dev *dev;
10829 struct i40e_pf *pf;
10830 struct i40e_vsi *vsi;
10833 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10835 dev = &rte_eth_devices[port];
10837 if (is_i40e_pmd(dev->data->drv_name))
10840 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10842 if (vf_id >= pf->vf_num || !pf->vfs) {
10843 PMD_DRV_LOG(ERR, "Invalid argument.");
10847 vsi = pf->vfs[vf_id].vsi;
10852 ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
10853 if (ret != I40E_SUCCESS) {
10855 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
10861 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
10864 struct rte_eth_dev *dev;
10865 struct i40e_pf *pf;
10866 struct i40e_hw *hw;
10867 struct i40e_vsi *vsi;
10868 struct i40e_vsi_context ctxt;
10871 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10873 if (vlan_id > ETHER_MAX_VLAN_ID) {
10874 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
10878 dev = &rte_eth_devices[port];
10880 if (is_i40e_pmd(dev->data->drv_name))
10883 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10884 hw = I40E_PF_TO_HW(pf);
10887 * return -ENODEV if SRIOV not enabled, VF number not configured
10888 * or no queue assigned.
10890 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10891 pf->vf_nb_qps == 0)
10894 if (vf_id >= pf->vf_num || !pf->vfs) {
10895 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10899 vsi = pf->vfs[vf_id].vsi;
10901 PMD_DRV_LOG(ERR, "Invalid VSI.");
10905 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
10906 vsi->info.pvid = vlan_id;
10908 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
10910 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
10912 memset(&ctxt, 0, sizeof(ctxt));
10913 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10914 ctxt.seid = vsi->seid;
10916 hw = I40E_VSI_TO_HW(vsi);
10917 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10918 if (ret != I40E_SUCCESS) {
10920 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10926 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
10929 struct rte_eth_dev *dev;
10930 struct i40e_pf *pf;
10931 struct i40e_vsi *vsi;
10932 struct i40e_hw *hw;
10935 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10938 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
10942 dev = &rte_eth_devices[port];
10944 if (is_i40e_pmd(dev->data->drv_name))
10947 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10948 hw = I40E_PF_TO_HW(pf);
10950 if (vf_id >= pf->vf_num || !pf->vfs) {
10951 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10956 * return -ENODEV if SRIOV not enabled, VF number not configured
10957 * or no queue assigned.
10959 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10960 pf->vf_nb_qps == 0) {
10961 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
10965 vsi = pf->vfs[vf_id].vsi;
10967 PMD_DRV_LOG(ERR, "Invalid VSI.");
10971 hw = I40E_VSI_TO_HW(vsi);
10973 ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, on, NULL);
10974 if (ret != I40E_SUCCESS) {
10976 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
10982 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
10984 struct rte_eth_dev *dev;
10985 struct i40e_pf *pf;
10986 struct i40e_hw *hw;
10987 struct i40e_vsi *vsi;
10988 struct i40e_vsi_context ctxt;
10991 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10994 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
10998 dev = &rte_eth_devices[port];
11000 if (is_i40e_pmd(dev->data->drv_name))
11003 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11004 hw = I40E_PF_TO_HW(pf);
11007 * return -ENODEV if SRIOV not enabled, VF number not configured
11008 * or no queue assigned.
11010 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11011 pf->vf_nb_qps == 0) {
11012 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11016 if (vf_id >= pf->vf_num || !pf->vfs) {
11017 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11021 vsi = pf->vfs[vf_id].vsi;
11023 PMD_DRV_LOG(ERR, "Invalid VSI.");
11027 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11029 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11030 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11032 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11033 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11036 memset(&ctxt, 0, sizeof(ctxt));
11037 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11038 ctxt.seid = vsi->seid;
11040 hw = I40E_VSI_TO_HW(vsi);
11041 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11042 if (ret != I40E_SUCCESS) {
11044 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11050 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11051 uint64_t vf_mask, uint8_t on)
11053 struct rte_eth_dev *dev;
11054 struct i40e_pf *pf;
11055 struct i40e_hw *hw;
11057 int ret = I40E_SUCCESS;
11059 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11061 dev = &rte_eth_devices[port];
11063 if (is_i40e_pmd(dev->data->drv_name))
11066 if (vlan_id > ETHER_MAX_VLAN_ID) {
11067 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11071 if (vf_mask == 0) {
11072 PMD_DRV_LOG(ERR, "No VF.");
11077 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11081 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11082 hw = I40E_PF_TO_HW(pf);
11085 * return -ENODEV if SRIOV not enabled, VF number not configured
11086 * or no queue assigned.
11088 if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11089 pf->vf_nb_qps == 0) {
11090 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11094 for (vf_idx = 0; vf_idx < 64 && ret == I40E_SUCCESS; vf_idx++) {
11095 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11097 ret = i40e_vsi_add_vlan(pf->vfs[vf_idx].vsi,
11100 ret = i40e_vsi_delete_vlan(pf->vfs[vf_idx].vsi,
11105 if (ret != I40E_SUCCESS) {
11107 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11114 rte_pmd_i40e_get_vf_stats(uint8_t port,
11116 struct rte_eth_stats *stats)
11118 struct rte_eth_dev *dev;
11119 struct i40e_pf *pf;
11120 struct i40e_vsi *vsi;
11122 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11124 dev = &rte_eth_devices[port];
11126 if (is_i40e_pmd(dev->data->drv_name))
11129 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11131 if (vf_id >= pf->vf_num || !pf->vfs) {
11132 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11136 vsi = pf->vfs[vf_id].vsi;
11138 PMD_DRV_LOG(ERR, "Invalid VSI.");
11142 i40e_update_vsi_stats(vsi);
11144 stats->ipackets = vsi->eth_stats.rx_unicast +
11145 vsi->eth_stats.rx_multicast +
11146 vsi->eth_stats.rx_broadcast;
11147 stats->opackets = vsi->eth_stats.tx_unicast +
11148 vsi->eth_stats.tx_multicast +
11149 vsi->eth_stats.tx_broadcast;
11150 stats->ibytes = vsi->eth_stats.rx_bytes;
11151 stats->obytes = vsi->eth_stats.tx_bytes;
11152 stats->ierrors = vsi->eth_stats.rx_discards;
11153 stats->oerrors = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11159 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11162 struct rte_eth_dev *dev;
11163 struct i40e_pf *pf;
11164 struct i40e_vsi *vsi;
11166 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11168 dev = &rte_eth_devices[port];
11170 if (is_i40e_pmd(dev->data->drv_name))
11173 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11175 if (vf_id >= pf->vf_num || !pf->vfs) {
11176 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11180 vsi = pf->vfs[vf_id].vsi;
11182 PMD_DRV_LOG(ERR, "Invalid VSI.");
11186 vsi->offset_loaded = false;
11187 i40e_update_vsi_stats(vsi);