1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
15 #include <rte_string_fns.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memzone.h>
22 #include <rte_malloc.h>
23 #include <rte_memcpy.h>
24 #include <rte_alarm.h>
26 #include <rte_eth_ctrl.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "base/i40e_diag.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
46 #define I40E_CLEAR_PXE_WAIT_MS 200
48 /* Maximun number of capability elements */
49 #define I40E_MAX_CAP_ELE_NUM 128
51 /* Wait count and interval */
52 #define I40E_CHK_Q_ENA_COUNT 1000
53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
55 /* Maximun number of VSI */
56 #define I40E_MAX_NUM_VSIS (384UL)
58 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
60 /* Flow control default timer */
61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
63 /* Flow control enable fwd bit */
64 #define I40E_PRTMAC_FWD_CTRL 0x00000001
66 /* Receive Packet Buffer size */
67 #define I40E_RXPBSIZE (968 * 1024)
70 #define I40E_KILOSHIFT 10
72 /* Flow control default high water */
73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
75 /* Flow control default low water */
76 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Receive Average Packet Size in Byte*/
79 #define I40E_PACKET_AVERAGE_SIZE 128
81 /* Mask of PF interrupt causes */
82 #define I40E_PFINT_ICR0_ENA_MASK ( \
83 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
84 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
85 I40E_PFINT_ICR0_ENA_GRST_MASK | \
86 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
87 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
89 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
90 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
91 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
93 #define I40E_FLOW_TYPES ( \
94 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
95 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
96 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
99 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
104 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
106 /* Additional timesync values. */
107 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
108 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
109 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
110 #define I40E_PRTTSYN_TSYNENA 0x80000000
111 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
112 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 * Below are values for writing un-exposed registers suggested
118 /* Destination MAC address */
119 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
120 /* Source MAC address */
121 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
123 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
126 /* Single VLAN tag in the inner L2 header */
127 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
128 /* Source IPv4 address */
129 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
130 /* Destination IPv4 address */
131 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
132 /* Source IPv4 address for X722 */
133 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
134 /* Destination IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
136 /* IPv4 Protocol for X722 */
137 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
138 /* IPv4 Time to Live for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
140 /* IPv4 Type of Service (TOS) */
141 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
143 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
144 /* IPv4 Time to Live */
145 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
146 /* Source IPv6 address */
147 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
148 /* Destination IPv6 address */
149 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
150 /* IPv6 Traffic Class (TC) */
151 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
152 /* IPv6 Next Header */
153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
157 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
158 /* Destination L4 port */
159 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
160 /* SCTP verification tag */
161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
164 /* Source port of tunneling UDP */
165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
166 /* Destination port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
168 /* UDP Tunneling ID, NVGRE/GRE key */
169 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
170 /* Last ether type */
171 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
172 /* Tunneling outer destination IPv4 address */
173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
174 /* Tunneling outer destination IPv6 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
176 /* 1st word of flex payload */
177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
178 /* 2nd word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
180 /* 3rd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
182 /* 4th word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
184 /* 5th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
186 /* 6th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
188 /* 7th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
190 /* 8th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
192 /* all 8 words flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
194 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
196 #define I40E_TRANSLATE_INSET 0
197 #define I40E_TRANSLATE_REG 1
199 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
200 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
201 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
202 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
204 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
206 /* PCI offset for querying capability */
207 #define PCI_DEV_CAP_REG 0xA4
208 /* PCI offset for enabling/disabling Extended Tag */
209 #define PCI_DEV_CTRL_REG 0xA8
210 /* Bit mask of Extended Tag capability */
211 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
212 /* Bit shift of Extended Tag enable/disable */
213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
214 /* Bit mask of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
219 static int i40e_dev_configure(struct rte_eth_dev *dev);
220 static int i40e_dev_start(struct rte_eth_dev *dev);
221 static void i40e_dev_stop(struct rte_eth_dev *dev);
222 static void i40e_dev_close(struct rte_eth_dev *dev);
223 static int i40e_dev_reset(struct rte_eth_dev *dev);
224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
231 struct rte_eth_stats *stats);
232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
233 struct rte_eth_xstat *xstats, unsigned n);
234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
235 struct rte_eth_xstat_name *xstats_names,
237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
243 char *fw_version, size_t fw_size);
244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
245 struct rte_eth_dev_info *dev_info);
246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
250 enum rte_vlan_type vlan_type,
252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_pfc_conf *pfc_conf);
265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
266 struct ether_addr *mac_addr,
269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
271 struct rte_eth_rss_reta_entry64 *reta_conf,
273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
277 static int i40e_get_cap(struct i40e_hw *hw);
278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
279 static int i40e_pf_setup(struct i40e_pf *pf);
280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
284 bool offset_loaded, uint64_t *offset, uint64_t *stat);
285 static void i40e_stat_update_48(struct i40e_hw *hw,
291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
292 static void i40e_dev_interrupt_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
374 struct ether_addr *mac_addr);
376 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
378 static int i40e_ethertype_filter_convert(
379 const struct rte_eth_ethertype_filter *input,
380 struct i40e_ethertype_filter *filter);
381 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
382 struct i40e_ethertype_filter *filter);
384 static int i40e_tunnel_filter_convert(
385 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
386 struct i40e_tunnel_filter *tunnel_filter);
387 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
388 struct i40e_tunnel_filter *tunnel_filter);
389 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
391 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
392 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
393 static void i40e_filter_restore(struct i40e_pf *pf);
394 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
396 int i40e_logtype_init;
397 int i40e_logtype_driver;
399 static const struct rte_pci_id pci_id_i40e_map[] = {
400 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
401 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
402 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
403 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
404 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
405 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
406 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
407 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
408 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
409 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
410 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
420 { .vendor_id = 0, /* sentinel */ },
423 static const struct eth_dev_ops i40e_eth_dev_ops = {
424 .dev_configure = i40e_dev_configure,
425 .dev_start = i40e_dev_start,
426 .dev_stop = i40e_dev_stop,
427 .dev_close = i40e_dev_close,
428 .dev_reset = i40e_dev_reset,
429 .promiscuous_enable = i40e_dev_promiscuous_enable,
430 .promiscuous_disable = i40e_dev_promiscuous_disable,
431 .allmulticast_enable = i40e_dev_allmulticast_enable,
432 .allmulticast_disable = i40e_dev_allmulticast_disable,
433 .dev_set_link_up = i40e_dev_set_link_up,
434 .dev_set_link_down = i40e_dev_set_link_down,
435 .link_update = i40e_dev_link_update,
436 .stats_get = i40e_dev_stats_get,
437 .xstats_get = i40e_dev_xstats_get,
438 .xstats_get_names = i40e_dev_xstats_get_names,
439 .stats_reset = i40e_dev_stats_reset,
440 .xstats_reset = i40e_dev_stats_reset,
441 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
442 .fw_version_get = i40e_fw_version_get,
443 .dev_infos_get = i40e_dev_info_get,
444 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
445 .vlan_filter_set = i40e_vlan_filter_set,
446 .vlan_tpid_set = i40e_vlan_tpid_set,
447 .vlan_offload_set = i40e_vlan_offload_set,
448 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
449 .vlan_pvid_set = i40e_vlan_pvid_set,
450 .rx_queue_start = i40e_dev_rx_queue_start,
451 .rx_queue_stop = i40e_dev_rx_queue_stop,
452 .tx_queue_start = i40e_dev_tx_queue_start,
453 .tx_queue_stop = i40e_dev_tx_queue_stop,
454 .rx_queue_setup = i40e_dev_rx_queue_setup,
455 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
456 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
457 .rx_queue_release = i40e_dev_rx_queue_release,
458 .rx_queue_count = i40e_dev_rx_queue_count,
459 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
460 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
461 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
462 .tx_queue_setup = i40e_dev_tx_queue_setup,
463 .tx_queue_release = i40e_dev_tx_queue_release,
464 .dev_led_on = i40e_dev_led_on,
465 .dev_led_off = i40e_dev_led_off,
466 .flow_ctrl_get = i40e_flow_ctrl_get,
467 .flow_ctrl_set = i40e_flow_ctrl_set,
468 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
469 .mac_addr_add = i40e_macaddr_add,
470 .mac_addr_remove = i40e_macaddr_remove,
471 .reta_update = i40e_dev_rss_reta_update,
472 .reta_query = i40e_dev_rss_reta_query,
473 .rss_hash_update = i40e_dev_rss_hash_update,
474 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
475 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
476 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
477 .filter_ctrl = i40e_dev_filter_ctrl,
478 .rxq_info_get = i40e_rxq_info_get,
479 .txq_info_get = i40e_txq_info_get,
480 .mirror_rule_set = i40e_mirror_rule_set,
481 .mirror_rule_reset = i40e_mirror_rule_reset,
482 .timesync_enable = i40e_timesync_enable,
483 .timesync_disable = i40e_timesync_disable,
484 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
485 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
486 .get_dcb_info = i40e_dev_get_dcb_info,
487 .timesync_adjust_time = i40e_timesync_adjust_time,
488 .timesync_read_time = i40e_timesync_read_time,
489 .timesync_write_time = i40e_timesync_write_time,
490 .get_reg = i40e_get_regs,
491 .get_eeprom_length = i40e_get_eeprom_length,
492 .get_eeprom = i40e_get_eeprom,
493 .mac_addr_set = i40e_set_default_mac_addr,
494 .mtu_set = i40e_dev_mtu_set,
495 .tm_ops_get = i40e_tm_ops_get,
498 /* store statistics names and its offset in stats structure */
499 struct rte_i40e_xstats_name_off {
500 char name[RTE_ETH_XSTATS_NAME_SIZE];
504 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
505 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
506 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
507 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
508 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
509 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
510 rx_unknown_protocol)},
511 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
512 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
513 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
514 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
517 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
518 sizeof(rte_i40e_stats_strings[0]))
520 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
521 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
522 tx_dropped_link_down)},
523 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
524 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
526 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
527 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
529 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
531 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
533 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
534 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
535 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
536 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
537 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
538 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
540 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
542 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
544 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
546 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
548 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
550 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
552 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
554 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
555 mac_short_packet_dropped)},
556 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
558 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
559 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
560 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_flow_director_atr_match_packets",
573 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
574 {"rx_flow_director_sb_match_packets",
575 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
576 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
578 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
580 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
582 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
586 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
587 sizeof(rte_i40e_hw_port_strings[0]))
589 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
590 {"xon_packets", offsetof(struct i40e_hw_port_stats,
592 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
596 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
597 sizeof(rte_i40e_rxq_prio_strings[0]))
599 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
600 {"xon_packets", offsetof(struct i40e_hw_port_stats,
602 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
604 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
605 priority_xon_2_xoff)},
608 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
609 sizeof(rte_i40e_txq_prio_strings[0]))
611 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
612 struct rte_pci_device *pci_dev)
614 return rte_eth_dev_pci_generic_probe(pci_dev,
615 sizeof(struct i40e_adapter), eth_i40e_dev_init);
618 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
620 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
623 static struct rte_pci_driver rte_i40e_pmd = {
624 .id_table = pci_id_i40e_map,
625 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
626 RTE_PCI_DRV_IOVA_AS_VA,
627 .probe = eth_i40e_pci_probe,
628 .remove = eth_i40e_pci_remove,
632 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
633 struct rte_eth_link *link)
635 struct rte_eth_link *dst = link;
636 struct rte_eth_link *src = &(dev->data->dev_link);
638 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
639 *(uint64_t *)src) == 0)
646 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
647 struct rte_eth_link *link)
649 struct rte_eth_link *dst = &(dev->data->dev_link);
650 struct rte_eth_link *src = link;
652 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
653 *(uint64_t *)src) == 0)
659 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
660 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
661 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
663 #ifndef I40E_GLQF_ORT
664 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
666 #ifndef I40E_GLQF_PIT
667 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
669 #ifndef I40E_GLQF_L3_MAP
670 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
673 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
676 * Initialize registers for parsing packet type of QinQ
677 * This should be removed from code once proper
678 * configuration API is added to avoid configuration conflicts
679 * between ports of the same device.
681 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
682 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
685 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
688 * Add a ethertype filter to drop all flow control frames transmitted
692 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
694 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
695 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
696 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
697 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
700 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
701 I40E_FLOW_CONTROL_ETHERTYPE, flags,
702 pf->main_vsi_seid, 0,
706 "Failed to add filter to drop flow control frames from VSIs.");
710 floating_veb_list_handler(__rte_unused const char *key,
711 const char *floating_veb_value,
715 unsigned int count = 0;
718 bool *vf_floating_veb = opaque;
720 while (isblank(*floating_veb_value))
721 floating_veb_value++;
723 /* Reset floating VEB configuration for VFs */
724 for (idx = 0; idx < I40E_MAX_VF; idx++)
725 vf_floating_veb[idx] = false;
729 while (isblank(*floating_veb_value))
730 floating_veb_value++;
731 if (*floating_veb_value == '\0')
734 idx = strtoul(floating_veb_value, &end, 10);
735 if (errno || end == NULL)
737 while (isblank(*end))
741 } else if ((*end == ';') || (*end == '\0')) {
743 if (min == I40E_MAX_VF)
745 if (max >= I40E_MAX_VF)
746 max = I40E_MAX_VF - 1;
747 for (idx = min; idx <= max; idx++) {
748 vf_floating_veb[idx] = true;
755 floating_veb_value = end + 1;
756 } while (*end != '\0');
765 config_vf_floating_veb(struct rte_devargs *devargs,
766 uint16_t floating_veb,
767 bool *vf_floating_veb)
769 struct rte_kvargs *kvlist;
771 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
775 /* All the VFs attach to the floating VEB by default
776 * when the floating VEB is enabled.
778 for (i = 0; i < I40E_MAX_VF; i++)
779 vf_floating_veb[i] = true;
784 kvlist = rte_kvargs_parse(devargs->args, NULL);
788 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
789 rte_kvargs_free(kvlist);
792 /* When the floating_veb_list parameter exists, all the VFs
793 * will attach to the legacy VEB firstly, then configure VFs
794 * to the floating VEB according to the floating_veb_list.
796 if (rte_kvargs_process(kvlist, floating_veb_list,
797 floating_veb_list_handler,
798 vf_floating_veb) < 0) {
799 rte_kvargs_free(kvlist);
802 rte_kvargs_free(kvlist);
806 i40e_check_floating_handler(__rte_unused const char *key,
808 __rte_unused void *opaque)
810 if (strcmp(value, "1"))
817 is_floating_veb_supported(struct rte_devargs *devargs)
819 struct rte_kvargs *kvlist;
820 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
825 kvlist = rte_kvargs_parse(devargs->args, NULL);
829 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
830 rte_kvargs_free(kvlist);
833 /* Floating VEB is enabled when there's key-value:
834 * enable_floating_veb=1
836 if (rte_kvargs_process(kvlist, floating_veb_key,
837 i40e_check_floating_handler, NULL) < 0) {
838 rte_kvargs_free(kvlist);
841 rte_kvargs_free(kvlist);
847 config_floating_veb(struct rte_eth_dev *dev)
849 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
850 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
851 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
853 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
855 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
857 is_floating_veb_supported(pci_dev->device.devargs);
858 config_vf_floating_veb(pci_dev->device.devargs,
860 pf->floating_veb_list);
862 pf->floating_veb = false;
866 #define I40E_L2_TAGS_S_TAG_SHIFT 1
867 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
870 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
872 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
873 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
874 char ethertype_hash_name[RTE_HASH_NAMESIZE];
877 struct rte_hash_parameters ethertype_hash_params = {
878 .name = ethertype_hash_name,
879 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
880 .key_len = sizeof(struct i40e_ethertype_filter_input),
881 .hash_func = rte_hash_crc,
882 .hash_func_init_val = 0,
883 .socket_id = rte_socket_id(),
886 /* Initialize ethertype filter rule list and hash */
887 TAILQ_INIT(ðertype_rule->ethertype_list);
888 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
889 "ethertype_%s", dev->device->name);
890 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
891 if (!ethertype_rule->hash_table) {
892 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
895 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
896 sizeof(struct i40e_ethertype_filter *) *
897 I40E_MAX_ETHERTYPE_FILTER_NUM,
899 if (!ethertype_rule->hash_map) {
901 "Failed to allocate memory for ethertype hash map!");
903 goto err_ethertype_hash_map_alloc;
908 err_ethertype_hash_map_alloc:
909 rte_hash_free(ethertype_rule->hash_table);
915 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
917 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
918 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
919 char tunnel_hash_name[RTE_HASH_NAMESIZE];
922 struct rte_hash_parameters tunnel_hash_params = {
923 .name = tunnel_hash_name,
924 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
925 .key_len = sizeof(struct i40e_tunnel_filter_input),
926 .hash_func = rte_hash_crc,
927 .hash_func_init_val = 0,
928 .socket_id = rte_socket_id(),
931 /* Initialize tunnel filter rule list and hash */
932 TAILQ_INIT(&tunnel_rule->tunnel_list);
933 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
934 "tunnel_%s", dev->device->name);
935 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
936 if (!tunnel_rule->hash_table) {
937 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
940 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
941 sizeof(struct i40e_tunnel_filter *) *
942 I40E_MAX_TUNNEL_FILTER_NUM,
944 if (!tunnel_rule->hash_map) {
946 "Failed to allocate memory for tunnel hash map!");
948 goto err_tunnel_hash_map_alloc;
953 err_tunnel_hash_map_alloc:
954 rte_hash_free(tunnel_rule->hash_table);
960 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
962 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
963 struct i40e_fdir_info *fdir_info = &pf->fdir;
964 char fdir_hash_name[RTE_HASH_NAMESIZE];
967 struct rte_hash_parameters fdir_hash_params = {
968 .name = fdir_hash_name,
969 .entries = I40E_MAX_FDIR_FILTER_NUM,
970 .key_len = sizeof(struct i40e_fdir_input),
971 .hash_func = rte_hash_crc,
972 .hash_func_init_val = 0,
973 .socket_id = rte_socket_id(),
976 /* Initialize flow director filter rule list and hash */
977 TAILQ_INIT(&fdir_info->fdir_list);
978 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
979 "fdir_%s", dev->device->name);
980 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
981 if (!fdir_info->hash_table) {
982 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
985 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
986 sizeof(struct i40e_fdir_filter *) *
987 I40E_MAX_FDIR_FILTER_NUM,
989 if (!fdir_info->hash_map) {
991 "Failed to allocate memory for fdir hash map!");
993 goto err_fdir_hash_map_alloc;
997 err_fdir_hash_map_alloc:
998 rte_hash_free(fdir_info->hash_table);
1004 i40e_init_customized_info(struct i40e_pf *pf)
1008 /* Initialize customized pctype */
1009 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1010 pf->customized_pctype[i].index = i;
1011 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1012 pf->customized_pctype[i].valid = false;
1015 pf->gtp_support = false;
1019 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1021 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023 struct i40e_queue_regions *info = &pf->queue_region;
1026 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1027 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1029 memset(info, 0, sizeof(struct i40e_queue_regions));
1033 eth_i40e_dev_init(struct rte_eth_dev *dev)
1035 struct rte_pci_device *pci_dev;
1036 struct rte_intr_handle *intr_handle;
1037 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1038 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039 struct i40e_vsi *vsi;
1042 uint8_t aq_fail = 0;
1044 PMD_INIT_FUNC_TRACE();
1046 dev->dev_ops = &i40e_eth_dev_ops;
1047 dev->rx_pkt_burst = i40e_recv_pkts;
1048 dev->tx_pkt_burst = i40e_xmit_pkts;
1049 dev->tx_pkt_prepare = i40e_prep_pkts;
1051 /* for secondary processes, we don't initialise any further as primary
1052 * has already done this work. Only check we don't need a different
1054 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1055 i40e_set_rx_function(dev);
1056 i40e_set_tx_function(dev);
1059 i40e_set_default_ptype_table(dev);
1060 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1061 intr_handle = &pci_dev->intr_handle;
1063 rte_eth_copy_pci_info(dev, pci_dev);
1065 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1066 pf->adapter->eth_dev = dev;
1067 pf->dev_data = dev->data;
1069 hw->back = I40E_PF_TO_ADAPTER(pf);
1070 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1073 "Hardware is not available, as address is NULL");
1077 hw->vendor_id = pci_dev->id.vendor_id;
1078 hw->device_id = pci_dev->id.device_id;
1079 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1080 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1081 hw->bus.device = pci_dev->addr.devid;
1082 hw->bus.func = pci_dev->addr.function;
1083 hw->adapter_stopped = 0;
1085 /* Make sure all is clean before doing PF reset */
1088 /* Initialize the hardware */
1091 /* Reset here to make sure all is clean for each PF */
1092 ret = i40e_pf_reset(hw);
1094 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1098 /* Initialize the shared code (base driver) */
1099 ret = i40e_init_shared_code(hw);
1101 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1105 i40e_set_default_pctype_table(dev);
1108 * To work around the NVM issue, initialize registers
1109 * for packet type of QinQ by software.
1110 * It should be removed once issues are fixed in NVM.
1112 i40e_GLQF_reg_init(hw);
1114 /* Initialize the input set for filters (hash and fd) to default value */
1115 i40e_filter_input_set_init(pf);
1117 /* Initialize the parameters for adminq */
1118 i40e_init_adminq_parameter(hw);
1119 ret = i40e_init_adminq(hw);
1120 if (ret != I40E_SUCCESS) {
1121 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1124 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1125 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1126 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1127 ((hw->nvm.version >> 12) & 0xf),
1128 ((hw->nvm.version >> 4) & 0xff),
1129 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1131 /* initialise the L3_MAP register */
1132 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1135 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1137 /* Need the special FW version to support floating VEB */
1138 config_floating_veb(dev);
1139 /* Clear PXE mode */
1140 i40e_clear_pxe_mode(hw);
1141 i40e_dev_sync_phy_type(hw);
1144 * On X710, performance number is far from the expectation on recent
1145 * firmware versions. The fix for this issue may not be integrated in
1146 * the following firmware version. So the workaround in software driver
1147 * is needed. It needs to modify the initial values of 3 internal only
1148 * registers. Note that the workaround can be removed when it is fixed
1149 * in firmware in the future.
1151 i40e_configure_registers(hw);
1153 /* Get hw capabilities */
1154 ret = i40e_get_cap(hw);
1155 if (ret != I40E_SUCCESS) {
1156 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1157 goto err_get_capabilities;
1160 /* Initialize parameters for PF */
1161 ret = i40e_pf_parameter_init(dev);
1163 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1164 goto err_parameter_init;
1167 /* Initialize the queue management */
1168 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1170 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1171 goto err_qp_pool_init;
1173 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1174 hw->func_caps.num_msix_vectors - 1);
1176 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1177 goto err_msix_pool_init;
1180 /* Initialize lan hmc */
1181 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1182 hw->func_caps.num_rx_qp, 0, 0);
1183 if (ret != I40E_SUCCESS) {
1184 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1185 goto err_init_lan_hmc;
1188 /* Configure lan hmc */
1189 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1190 if (ret != I40E_SUCCESS) {
1191 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1192 goto err_configure_lan_hmc;
1195 /* Get and check the mac address */
1196 i40e_get_mac_addr(hw, hw->mac.addr);
1197 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1198 PMD_INIT_LOG(ERR, "mac address is not valid");
1200 goto err_get_mac_addr;
1202 /* Copy the permanent MAC address */
1203 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1204 (struct ether_addr *) hw->mac.perm_addr);
1206 /* Disable flow control */
1207 hw->fc.requested_mode = I40E_FC_NONE;
1208 i40e_set_fc(hw, &aq_fail, TRUE);
1210 /* Set the global registers with default ether type value */
1211 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1212 if (ret != I40E_SUCCESS) {
1214 "Failed to set the default outer VLAN ether type");
1215 goto err_setup_pf_switch;
1218 /* PF setup, which includes VSI setup */
1219 ret = i40e_pf_setup(pf);
1221 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1222 goto err_setup_pf_switch;
1225 /* reset all stats of the device, including pf and main vsi */
1226 i40e_dev_stats_reset(dev);
1230 /* Disable double vlan by default */
1231 i40e_vsi_config_double_vlan(vsi, FALSE);
1233 /* Disable S-TAG identification when floating_veb is disabled */
1234 if (!pf->floating_veb) {
1235 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1236 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1237 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1238 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1242 if (!vsi->max_macaddrs)
1243 len = ETHER_ADDR_LEN;
1245 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1247 /* Should be after VSI initialized */
1248 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1249 if (!dev->data->mac_addrs) {
1251 "Failed to allocated memory for storing mac address");
1254 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1255 &dev->data->mac_addrs[0]);
1257 /* Init dcb to sw mode by default */
1258 ret = i40e_dcb_init_configure(dev, TRUE);
1259 if (ret != I40E_SUCCESS) {
1260 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1261 pf->flags &= ~I40E_FLAG_DCB;
1263 /* Update HW struct after DCB configuration */
1266 /* initialize pf host driver to setup SRIOV resource if applicable */
1267 i40e_pf_host_init(dev);
1269 /* register callback func to eal lib */
1270 rte_intr_callback_register(intr_handle,
1271 i40e_dev_interrupt_handler, dev);
1273 /* configure and enable device interrupt */
1274 i40e_pf_config_irq0(hw, TRUE);
1275 i40e_pf_enable_irq0(hw);
1277 /* enable uio intr after callback register */
1278 rte_intr_enable(intr_handle);
1280 /* By default disable flexible payload in global configuration */
1281 i40e_flex_payload_reg_set_default(hw);
1284 * Add an ethertype filter to drop all flow control frames transmitted
1285 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1288 i40e_add_tx_flow_control_drop_filter(pf);
1290 /* Set the max frame size to 0x2600 by default,
1291 * in case other drivers changed the default value.
1293 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1295 /* initialize mirror rule list */
1296 TAILQ_INIT(&pf->mirror_list);
1298 /* initialize Traffic Manager configuration */
1299 i40e_tm_conf_init(dev);
1301 /* Initialize customized information */
1302 i40e_init_customized_info(pf);
1304 ret = i40e_init_ethtype_filter_list(dev);
1306 goto err_init_ethtype_filter_list;
1307 ret = i40e_init_tunnel_filter_list(dev);
1309 goto err_init_tunnel_filter_list;
1310 ret = i40e_init_fdir_filter_list(dev);
1312 goto err_init_fdir_filter_list;
1314 /* initialize queue region configuration */
1315 i40e_init_queue_region_conf(dev);
1317 /* initialize rss configuration from rte_flow */
1318 memset(&pf->rss_info, 0,
1319 sizeof(struct i40e_rte_flow_rss_conf));
1323 err_init_fdir_filter_list:
1324 rte_free(pf->tunnel.hash_table);
1325 rte_free(pf->tunnel.hash_map);
1326 err_init_tunnel_filter_list:
1327 rte_free(pf->ethertype.hash_table);
1328 rte_free(pf->ethertype.hash_map);
1329 err_init_ethtype_filter_list:
1330 rte_free(dev->data->mac_addrs);
1332 i40e_vsi_release(pf->main_vsi);
1333 err_setup_pf_switch:
1335 err_configure_lan_hmc:
1336 (void)i40e_shutdown_lan_hmc(hw);
1338 i40e_res_pool_destroy(&pf->msix_pool);
1340 i40e_res_pool_destroy(&pf->qp_pool);
1343 err_get_capabilities:
1344 (void)i40e_shutdown_adminq(hw);
1350 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1352 struct i40e_ethertype_filter *p_ethertype;
1353 struct i40e_ethertype_rule *ethertype_rule;
1355 ethertype_rule = &pf->ethertype;
1356 /* Remove all ethertype filter rules and hash */
1357 if (ethertype_rule->hash_map)
1358 rte_free(ethertype_rule->hash_map);
1359 if (ethertype_rule->hash_table)
1360 rte_hash_free(ethertype_rule->hash_table);
1362 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1363 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1364 p_ethertype, rules);
1365 rte_free(p_ethertype);
1370 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1372 struct i40e_tunnel_filter *p_tunnel;
1373 struct i40e_tunnel_rule *tunnel_rule;
1375 tunnel_rule = &pf->tunnel;
1376 /* Remove all tunnel director rules and hash */
1377 if (tunnel_rule->hash_map)
1378 rte_free(tunnel_rule->hash_map);
1379 if (tunnel_rule->hash_table)
1380 rte_hash_free(tunnel_rule->hash_table);
1382 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1383 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1389 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1391 struct i40e_fdir_filter *p_fdir;
1392 struct i40e_fdir_info *fdir_info;
1394 fdir_info = &pf->fdir;
1395 /* Remove all flow director rules and hash */
1396 if (fdir_info->hash_map)
1397 rte_free(fdir_info->hash_map);
1398 if (fdir_info->hash_table)
1399 rte_hash_free(fdir_info->hash_table);
1401 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1402 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1407 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1410 * Disable by default flexible payload
1411 * for corresponding L2/L3/L4 layers.
1413 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1414 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1415 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1419 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1422 struct rte_pci_device *pci_dev;
1423 struct rte_intr_handle *intr_handle;
1425 struct i40e_filter_control_settings settings;
1426 struct rte_flow *p_flow;
1428 uint8_t aq_fail = 0;
1430 PMD_INIT_FUNC_TRACE();
1432 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1435 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1436 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1438 intr_handle = &pci_dev->intr_handle;
1440 if (hw->adapter_stopped == 0)
1441 i40e_dev_close(dev);
1443 dev->dev_ops = NULL;
1444 dev->rx_pkt_burst = NULL;
1445 dev->tx_pkt_burst = NULL;
1447 /* Clear PXE mode */
1448 i40e_clear_pxe_mode(hw);
1450 /* Unconfigure filter control */
1451 memset(&settings, 0, sizeof(settings));
1452 ret = i40e_set_filter_control(hw, &settings);
1454 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1457 /* Disable flow control */
1458 hw->fc.requested_mode = I40E_FC_NONE;
1459 i40e_set_fc(hw, &aq_fail, TRUE);
1461 /* uninitialize pf host driver */
1462 i40e_pf_host_uninit(dev);
1464 rte_free(dev->data->mac_addrs);
1465 dev->data->mac_addrs = NULL;
1467 /* disable uio intr before callback unregister */
1468 rte_intr_disable(intr_handle);
1470 /* register callback func to eal lib */
1471 rte_intr_callback_unregister(intr_handle,
1472 i40e_dev_interrupt_handler, dev);
1474 i40e_rm_ethtype_filter_list(pf);
1475 i40e_rm_tunnel_filter_list(pf);
1476 i40e_rm_fdir_filter_list(pf);
1478 /* Remove all flows */
1479 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1480 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1484 /* Remove all Traffic Manager configuration */
1485 i40e_tm_conf_uninit(dev);
1491 i40e_dev_configure(struct rte_eth_dev *dev)
1493 struct i40e_adapter *ad =
1494 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1495 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1496 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1497 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1500 ret = i40e_dev_sync_phy_type(hw);
1504 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1505 * bulk allocation or vector Rx preconditions we will reset it.
1507 ad->rx_bulk_alloc_allowed = true;
1508 ad->rx_vec_allowed = true;
1509 ad->tx_simple_allowed = true;
1510 ad->tx_vec_allowed = true;
1512 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1513 ret = i40e_fdir_setup(pf);
1514 if (ret != I40E_SUCCESS) {
1515 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1518 ret = i40e_fdir_configure(dev);
1520 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1524 i40e_fdir_teardown(pf);
1526 ret = i40e_dev_init_vlan(dev);
1531 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1532 * RSS setting have different requirements.
1533 * General PMD driver call sequence are NIC init, configure,
1534 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1535 * will try to lookup the VSI that specific queue belongs to if VMDQ
1536 * applicable. So, VMDQ setting has to be done before
1537 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1538 * For RSS setting, it will try to calculate actual configured RX queue
1539 * number, which will be available after rx_queue_setup(). dev_start()
1540 * function is good to place RSS setup.
1542 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1543 ret = i40e_vmdq_setup(dev);
1548 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1549 ret = i40e_dcb_setup(dev);
1551 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1556 TAILQ_INIT(&pf->flow_list);
1561 /* need to release vmdq resource if exists */
1562 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1563 i40e_vsi_release(pf->vmdq[i].vsi);
1564 pf->vmdq[i].vsi = NULL;
1569 /* need to release fdir resource if exists */
1570 i40e_fdir_teardown(pf);
1575 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1577 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1578 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1579 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1580 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1581 uint16_t msix_vect = vsi->msix_intr;
1584 for (i = 0; i < vsi->nb_qps; i++) {
1585 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1586 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1590 if (vsi->type != I40E_VSI_SRIOV) {
1591 if (!rte_intr_allow_others(intr_handle)) {
1592 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1593 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1595 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1598 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1599 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1601 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1606 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1607 vsi->user_param + (msix_vect - 1);
1609 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1610 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1612 I40E_WRITE_FLUSH(hw);
1616 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1617 int base_queue, int nb_queue,
1622 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1624 /* Bind all RX queues to allocated MSIX interrupt */
1625 for (i = 0; i < nb_queue; i++) {
1626 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1627 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1628 ((base_queue + i + 1) <<
1629 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1630 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1631 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1633 if (i == nb_queue - 1)
1634 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1635 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1638 /* Write first RX queue to Link list register as the head element */
1639 if (vsi->type != I40E_VSI_SRIOV) {
1641 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1643 if (msix_vect == I40E_MISC_VEC_ID) {
1644 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1646 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1648 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1650 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1653 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1655 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1657 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1659 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1666 if (msix_vect == I40E_MISC_VEC_ID) {
1668 I40E_VPINT_LNKLST0(vsi->user_param),
1670 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1672 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1674 /* num_msix_vectors_vf needs to minus irq0 */
1675 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1676 vsi->user_param + (msix_vect - 1);
1678 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1680 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1682 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1686 I40E_WRITE_FLUSH(hw);
1690 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1692 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1693 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1694 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1695 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1696 uint16_t msix_vect = vsi->msix_intr;
1697 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1698 uint16_t queue_idx = 0;
1703 for (i = 0; i < vsi->nb_qps; i++) {
1704 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1705 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1708 /* INTENA flag is not auto-cleared for interrupt */
1709 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1710 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1711 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1712 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1713 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1715 /* VF bind interrupt */
1716 if (vsi->type == I40E_VSI_SRIOV) {
1717 __vsi_queues_bind_intr(vsi, msix_vect,
1718 vsi->base_queue, vsi->nb_qps,
1723 /* PF & VMDq bind interrupt */
1724 if (rte_intr_dp_is_en(intr_handle)) {
1725 if (vsi->type == I40E_VSI_MAIN) {
1728 } else if (vsi->type == I40E_VSI_VMDQ2) {
1729 struct i40e_vsi *main_vsi =
1730 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1731 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1736 for (i = 0; i < vsi->nb_used_qps; i++) {
1738 if (!rte_intr_allow_others(intr_handle))
1739 /* allow to share MISC_VEC_ID */
1740 msix_vect = I40E_MISC_VEC_ID;
1742 /* no enough msix_vect, map all to one */
1743 __vsi_queues_bind_intr(vsi, msix_vect,
1744 vsi->base_queue + i,
1745 vsi->nb_used_qps - i,
1747 for (; !!record && i < vsi->nb_used_qps; i++)
1748 intr_handle->intr_vec[queue_idx + i] =
1752 /* 1:1 queue/msix_vect mapping */
1753 __vsi_queues_bind_intr(vsi, msix_vect,
1754 vsi->base_queue + i, 1,
1757 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1765 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1767 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1769 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771 uint16_t interval = i40e_calc_itr_interval(\
1772 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1773 uint16_t msix_intr, i;
1775 if (rte_intr_allow_others(intr_handle))
1776 for (i = 0; i < vsi->nb_msix; i++) {
1777 msix_intr = vsi->msix_intr + i;
1778 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1779 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1780 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1781 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1783 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1786 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1787 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1788 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1789 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1791 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1793 I40E_WRITE_FLUSH(hw);
1797 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1799 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1800 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1801 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1802 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1803 uint16_t msix_intr, i;
1805 if (rte_intr_allow_others(intr_handle))
1806 for (i = 0; i < vsi->nb_msix; i++) {
1807 msix_intr = vsi->msix_intr + i;
1808 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1812 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1814 I40E_WRITE_FLUSH(hw);
1817 static inline uint8_t
1818 i40e_parse_link_speeds(uint16_t link_speeds)
1820 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1822 if (link_speeds & ETH_LINK_SPEED_40G)
1823 link_speed |= I40E_LINK_SPEED_40GB;
1824 if (link_speeds & ETH_LINK_SPEED_25G)
1825 link_speed |= I40E_LINK_SPEED_25GB;
1826 if (link_speeds & ETH_LINK_SPEED_20G)
1827 link_speed |= I40E_LINK_SPEED_20GB;
1828 if (link_speeds & ETH_LINK_SPEED_10G)
1829 link_speed |= I40E_LINK_SPEED_10GB;
1830 if (link_speeds & ETH_LINK_SPEED_1G)
1831 link_speed |= I40E_LINK_SPEED_1GB;
1832 if (link_speeds & ETH_LINK_SPEED_100M)
1833 link_speed |= I40E_LINK_SPEED_100MB;
1839 i40e_phy_conf_link(struct i40e_hw *hw,
1841 uint8_t force_speed,
1844 enum i40e_status_code status;
1845 struct i40e_aq_get_phy_abilities_resp phy_ab;
1846 struct i40e_aq_set_phy_config phy_conf;
1847 enum i40e_aq_phy_type cnt;
1848 uint32_t phy_type_mask = 0;
1850 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1851 I40E_AQ_PHY_FLAG_PAUSE_RX |
1852 I40E_AQ_PHY_FLAG_PAUSE_RX |
1853 I40E_AQ_PHY_FLAG_LOW_POWER;
1854 const uint8_t advt = I40E_LINK_SPEED_40GB |
1855 I40E_LINK_SPEED_25GB |
1856 I40E_LINK_SPEED_10GB |
1857 I40E_LINK_SPEED_1GB |
1858 I40E_LINK_SPEED_100MB;
1862 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1867 /* If link already up, no need to set up again */
1868 if (is_up && phy_ab.phy_type != 0)
1869 return I40E_SUCCESS;
1871 memset(&phy_conf, 0, sizeof(phy_conf));
1873 /* bits 0-2 use the values from get_phy_abilities_resp */
1875 abilities |= phy_ab.abilities & mask;
1877 /* update ablities and speed */
1878 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1879 phy_conf.link_speed = advt;
1881 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1883 phy_conf.abilities = abilities;
1887 /* To enable link, phy_type mask needs to include each type */
1888 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1889 phy_type_mask |= 1 << cnt;
1891 /* use get_phy_abilities_resp value for the rest */
1892 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1893 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1894 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1895 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1896 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1897 phy_conf.eee_capability = phy_ab.eee_capability;
1898 phy_conf.eeer = phy_ab.eeer_val;
1899 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1901 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1902 phy_ab.abilities, phy_ab.link_speed);
1903 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1904 phy_conf.abilities, phy_conf.link_speed);
1906 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1910 return I40E_SUCCESS;
1914 i40e_apply_link_speed(struct rte_eth_dev *dev)
1917 uint8_t abilities = 0;
1918 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1919 struct rte_eth_conf *conf = &dev->data->dev_conf;
1921 speed = i40e_parse_link_speeds(conf->link_speeds);
1922 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1923 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1924 abilities |= I40E_AQ_PHY_AN_ENABLED;
1925 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1927 return i40e_phy_conf_link(hw, abilities, speed, true);
1931 i40e_dev_start(struct rte_eth_dev *dev)
1933 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935 struct i40e_vsi *main_vsi = pf->main_vsi;
1937 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1938 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1939 uint32_t intr_vector = 0;
1940 struct i40e_vsi *vsi;
1942 hw->adapter_stopped = 0;
1944 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1946 "Invalid link_speeds for port %u, autonegotiation disabled",
1947 dev->data->port_id);
1951 rte_intr_disable(intr_handle);
1953 if ((rte_intr_cap_multiple(intr_handle) ||
1954 !RTE_ETH_DEV_SRIOV(dev).active) &&
1955 dev->data->dev_conf.intr_conf.rxq != 0) {
1956 intr_vector = dev->data->nb_rx_queues;
1957 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1962 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1963 intr_handle->intr_vec =
1964 rte_zmalloc("intr_vec",
1965 dev->data->nb_rx_queues * sizeof(int),
1967 if (!intr_handle->intr_vec) {
1969 "Failed to allocate %d rx_queues intr_vec",
1970 dev->data->nb_rx_queues);
1975 /* Initialize VSI */
1976 ret = i40e_dev_rxtx_init(pf);
1977 if (ret != I40E_SUCCESS) {
1978 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1982 /* Map queues with MSIX interrupt */
1983 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1984 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1985 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1986 i40e_vsi_enable_queues_intr(main_vsi);
1988 /* Map VMDQ VSI queues with MSIX interrupt */
1989 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1990 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1991 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1992 I40E_ITR_INDEX_DEFAULT);
1993 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1996 /* enable FDIR MSIX interrupt */
1997 if (pf->fdir.fdir_vsi) {
1998 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1999 I40E_ITR_INDEX_NONE);
2000 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2003 /* Enable all queues which have been configured */
2004 ret = i40e_dev_switch_queues(pf, TRUE);
2006 if (ret != I40E_SUCCESS) {
2007 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2011 /* Enable receiving broadcast packets */
2012 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2013 if (ret != I40E_SUCCESS)
2014 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2016 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2017 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2019 if (ret != I40E_SUCCESS)
2020 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2023 /* Enable the VLAN promiscuous mode. */
2025 for (i = 0; i < pf->vf_num; i++) {
2026 vsi = pf->vfs[i].vsi;
2027 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2032 /* Enable mac loopback mode */
2033 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2034 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2035 ret = i40e_diag_set_loopback(hw, dev->data->dev_conf.lpbk_mode);
2036 if (ret != I40E_SUCCESS) {
2037 PMD_DRV_LOG(ERR, "fail to set loopback link");
2042 /* Apply link configure */
2043 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2044 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2045 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2046 ETH_LINK_SPEED_40G)) {
2047 PMD_DRV_LOG(ERR, "Invalid link setting");
2050 ret = i40e_apply_link_speed(dev);
2051 if (I40E_SUCCESS != ret) {
2052 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2056 if (!rte_intr_allow_others(intr_handle)) {
2057 rte_intr_callback_unregister(intr_handle,
2058 i40e_dev_interrupt_handler,
2060 /* configure and enable device interrupt */
2061 i40e_pf_config_irq0(hw, FALSE);
2062 i40e_pf_enable_irq0(hw);
2064 if (dev->data->dev_conf.intr_conf.lsc != 0)
2066 "lsc won't enable because of no intr multiplex");
2068 ret = i40e_aq_set_phy_int_mask(hw,
2069 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2070 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2071 I40E_AQ_EVENT_MEDIA_NA), NULL);
2072 if (ret != I40E_SUCCESS)
2073 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2075 /* Call get_link_info aq commond to enable/disable LSE */
2076 i40e_dev_link_update(dev, 0);
2079 /* enable uio intr after callback register */
2080 rte_intr_enable(intr_handle);
2082 i40e_filter_restore(pf);
2084 if (pf->tm_conf.root && !pf->tm_conf.committed)
2085 PMD_DRV_LOG(WARNING,
2086 "please call hierarchy_commit() "
2087 "before starting the port");
2089 return I40E_SUCCESS;
2092 i40e_dev_switch_queues(pf, FALSE);
2093 i40e_dev_clear_queues(dev);
2099 i40e_dev_stop(struct rte_eth_dev *dev)
2101 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2102 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103 struct i40e_vsi *main_vsi = pf->main_vsi;
2104 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2105 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2108 if (hw->adapter_stopped == 1)
2110 /* Disable all queues */
2111 i40e_dev_switch_queues(pf, FALSE);
2113 /* un-map queues with interrupt registers */
2114 i40e_vsi_disable_queues_intr(main_vsi);
2115 i40e_vsi_queues_unbind_intr(main_vsi);
2117 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2118 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2119 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2122 if (pf->fdir.fdir_vsi) {
2123 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2124 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2126 /* Clear all queues and release memory */
2127 i40e_dev_clear_queues(dev);
2130 i40e_dev_set_link_down(dev);
2132 if (!rte_intr_allow_others(intr_handle))
2133 /* resume to the default handler */
2134 rte_intr_callback_register(intr_handle,
2135 i40e_dev_interrupt_handler,
2138 /* Clean datapath event and queue/vec mapping */
2139 rte_intr_efd_disable(intr_handle);
2140 if (intr_handle->intr_vec) {
2141 rte_free(intr_handle->intr_vec);
2142 intr_handle->intr_vec = NULL;
2145 /* reset hierarchy commit */
2146 pf->tm_conf.committed = false;
2148 hw->adapter_stopped = 1;
2152 i40e_dev_close(struct rte_eth_dev *dev)
2154 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2155 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2157 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2158 struct i40e_mirror_rule *p_mirror;
2163 PMD_INIT_FUNC_TRACE();
2167 /* Remove all mirror rules */
2168 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2169 ret = i40e_aq_del_mirror_rule(hw,
2170 pf->main_vsi->veb->seid,
2171 p_mirror->rule_type,
2173 p_mirror->num_entries,
2176 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2177 "status = %d, aq_err = %d.", ret,
2178 hw->aq.asq_last_status);
2180 /* remove mirror software resource anyway */
2181 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2183 pf->nb_mirror_rule--;
2186 i40e_dev_free_queues(dev);
2188 /* Disable interrupt */
2189 i40e_pf_disable_irq0(hw);
2190 rte_intr_disable(intr_handle);
2192 /* shutdown and destroy the HMC */
2193 i40e_shutdown_lan_hmc(hw);
2195 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2196 i40e_vsi_release(pf->vmdq[i].vsi);
2197 pf->vmdq[i].vsi = NULL;
2202 /* release all the existing VSIs and VEBs */
2203 i40e_fdir_teardown(pf);
2204 i40e_vsi_release(pf->main_vsi);
2206 /* shutdown the adminq */
2207 i40e_aq_queue_shutdown(hw, true);
2208 i40e_shutdown_adminq(hw);
2210 i40e_res_pool_destroy(&pf->qp_pool);
2211 i40e_res_pool_destroy(&pf->msix_pool);
2213 /* Disable flexible payload in global configuration */
2214 i40e_flex_payload_reg_set_default(hw);
2216 /* force a PF reset to clean anything leftover */
2217 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2218 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2219 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2220 I40E_WRITE_FLUSH(hw);
2224 * Reset PF device only to re-initialize resources in PMD layer
2227 i40e_dev_reset(struct rte_eth_dev *dev)
2231 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2232 * its VF to make them align with it. The detailed notification
2233 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2234 * To avoid unexpected behavior in VF, currently reset of PF with
2235 * SR-IOV activation is not supported. It might be supported later.
2237 if (dev->data->sriov.active)
2240 ret = eth_i40e_dev_uninit(dev);
2244 ret = eth_i40e_dev_init(dev);
2250 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2252 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2253 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2254 struct i40e_vsi *vsi = pf->main_vsi;
2257 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2259 if (status != I40E_SUCCESS)
2260 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2262 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2264 if (status != I40E_SUCCESS)
2265 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2270 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2273 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274 struct i40e_vsi *vsi = pf->main_vsi;
2277 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2279 if (status != I40E_SUCCESS)
2280 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2282 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2284 if (status != I40E_SUCCESS)
2285 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2289 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2291 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2292 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2293 struct i40e_vsi *vsi = pf->main_vsi;
2296 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2297 if (ret != I40E_SUCCESS)
2298 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2302 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2304 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2305 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2306 struct i40e_vsi *vsi = pf->main_vsi;
2309 if (dev->data->promiscuous == 1)
2310 return; /* must remain in all_multicast mode */
2312 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2313 vsi->seid, FALSE, NULL);
2314 if (ret != I40E_SUCCESS)
2315 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2319 * Set device link up.
2322 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2324 /* re-apply link speed setting */
2325 return i40e_apply_link_speed(dev);
2329 * Set device link down.
2332 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2334 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2335 uint8_t abilities = 0;
2336 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2338 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2339 return i40e_phy_conf_link(hw, abilities, speed, false);
2343 i40e_dev_link_update(struct rte_eth_dev *dev,
2344 int wait_to_complete)
2346 #define CHECK_INTERVAL 100 /* 100ms */
2347 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2348 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2349 struct i40e_link_status link_status;
2350 struct rte_eth_link link, old;
2352 unsigned rep_cnt = MAX_REPEAT_TIME;
2353 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2355 memset(&link, 0, sizeof(link));
2356 memset(&old, 0, sizeof(old));
2357 memset(&link_status, 0, sizeof(link_status));
2358 rte_i40e_dev_atomic_read_link_status(dev, &old);
2361 /* Get link status information from hardware */
2362 status = i40e_aq_get_link_info(hw, enable_lse,
2363 &link_status, NULL);
2364 if (status != I40E_SUCCESS) {
2365 link.link_speed = ETH_SPEED_NUM_100M;
2366 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2367 PMD_DRV_LOG(ERR, "Failed to get link info");
2371 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2372 if (!wait_to_complete || link.link_status)
2375 rte_delay_ms(CHECK_INTERVAL);
2376 } while (--rep_cnt);
2378 if (!link.link_status)
2381 /* i40e uses full duplex only */
2382 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2384 /* Parse the link status */
2385 switch (link_status.link_speed) {
2386 case I40E_LINK_SPEED_100MB:
2387 link.link_speed = ETH_SPEED_NUM_100M;
2389 case I40E_LINK_SPEED_1GB:
2390 link.link_speed = ETH_SPEED_NUM_1G;
2392 case I40E_LINK_SPEED_10GB:
2393 link.link_speed = ETH_SPEED_NUM_10G;
2395 case I40E_LINK_SPEED_20GB:
2396 link.link_speed = ETH_SPEED_NUM_20G;
2398 case I40E_LINK_SPEED_25GB:
2399 link.link_speed = ETH_SPEED_NUM_25G;
2401 case I40E_LINK_SPEED_40GB:
2402 link.link_speed = ETH_SPEED_NUM_40G;
2405 link.link_speed = ETH_SPEED_NUM_100M;
2409 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2410 ETH_LINK_SPEED_FIXED);
2413 rte_i40e_dev_atomic_write_link_status(dev, &link);
2414 if (link.link_status == old.link_status)
2417 i40e_notify_all_vfs_link_status(dev);
2422 /* Get all the statistics of a VSI */
2424 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2426 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2427 struct i40e_eth_stats *nes = &vsi->eth_stats;
2428 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2429 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2431 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2432 vsi->offset_loaded, &oes->rx_bytes,
2434 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2435 vsi->offset_loaded, &oes->rx_unicast,
2437 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2438 vsi->offset_loaded, &oes->rx_multicast,
2439 &nes->rx_multicast);
2440 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2441 vsi->offset_loaded, &oes->rx_broadcast,
2442 &nes->rx_broadcast);
2443 /* exclude CRC bytes */
2444 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2445 nes->rx_broadcast) * ETHER_CRC_LEN;
2447 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2448 &oes->rx_discards, &nes->rx_discards);
2449 /* GLV_REPC not supported */
2450 /* GLV_RMPC not supported */
2451 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2452 &oes->rx_unknown_protocol,
2453 &nes->rx_unknown_protocol);
2454 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2455 vsi->offset_loaded, &oes->tx_bytes,
2457 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2458 vsi->offset_loaded, &oes->tx_unicast,
2460 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2461 vsi->offset_loaded, &oes->tx_multicast,
2462 &nes->tx_multicast);
2463 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2464 vsi->offset_loaded, &oes->tx_broadcast,
2465 &nes->tx_broadcast);
2466 /* GLV_TDPC not supported */
2467 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2468 &oes->tx_errors, &nes->tx_errors);
2469 vsi->offset_loaded = true;
2471 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2473 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2474 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2475 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2476 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2477 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2478 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2479 nes->rx_unknown_protocol);
2480 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2481 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2482 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2483 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2484 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2485 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2486 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2491 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2494 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2495 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2497 /* Get rx/tx bytes of internal transfer packets */
2498 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2499 I40E_GLV_GORCL(hw->port),
2501 &pf->internal_stats_offset.rx_bytes,
2502 &pf->internal_stats.rx_bytes);
2504 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2505 I40E_GLV_GOTCL(hw->port),
2507 &pf->internal_stats_offset.tx_bytes,
2508 &pf->internal_stats.tx_bytes);
2509 /* Get total internal rx packet count */
2510 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2511 I40E_GLV_UPRCL(hw->port),
2513 &pf->internal_stats_offset.rx_unicast,
2514 &pf->internal_stats.rx_unicast);
2515 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2516 I40E_GLV_MPRCL(hw->port),
2518 &pf->internal_stats_offset.rx_multicast,
2519 &pf->internal_stats.rx_multicast);
2520 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2521 I40E_GLV_BPRCL(hw->port),
2523 &pf->internal_stats_offset.rx_broadcast,
2524 &pf->internal_stats.rx_broadcast);
2525 /* Get total internal tx packet count */
2526 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2527 I40E_GLV_UPTCL(hw->port),
2529 &pf->internal_stats_offset.tx_unicast,
2530 &pf->internal_stats.tx_unicast);
2531 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2532 I40E_GLV_MPTCL(hw->port),
2534 &pf->internal_stats_offset.tx_multicast,
2535 &pf->internal_stats.tx_multicast);
2536 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2537 I40E_GLV_BPTCL(hw->port),
2539 &pf->internal_stats_offset.tx_broadcast,
2540 &pf->internal_stats.tx_broadcast);
2542 /* exclude CRC size */
2543 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2544 pf->internal_stats.rx_multicast +
2545 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2547 /* Get statistics of struct i40e_eth_stats */
2548 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2549 I40E_GLPRT_GORCL(hw->port),
2550 pf->offset_loaded, &os->eth.rx_bytes,
2552 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2553 I40E_GLPRT_UPRCL(hw->port),
2554 pf->offset_loaded, &os->eth.rx_unicast,
2555 &ns->eth.rx_unicast);
2556 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2557 I40E_GLPRT_MPRCL(hw->port),
2558 pf->offset_loaded, &os->eth.rx_multicast,
2559 &ns->eth.rx_multicast);
2560 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2561 I40E_GLPRT_BPRCL(hw->port),
2562 pf->offset_loaded, &os->eth.rx_broadcast,
2563 &ns->eth.rx_broadcast);
2564 /* Workaround: CRC size should not be included in byte statistics,
2565 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2567 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2568 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2570 /* exclude internal rx bytes
2571 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2572 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2574 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2576 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2577 ns->eth.rx_bytes = 0;
2579 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2581 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2582 ns->eth.rx_unicast = 0;
2584 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2586 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2587 ns->eth.rx_multicast = 0;
2589 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2591 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2592 ns->eth.rx_broadcast = 0;
2594 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2596 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2597 pf->offset_loaded, &os->eth.rx_discards,
2598 &ns->eth.rx_discards);
2599 /* GLPRT_REPC not supported */
2600 /* GLPRT_RMPC not supported */
2601 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2603 &os->eth.rx_unknown_protocol,
2604 &ns->eth.rx_unknown_protocol);
2605 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2606 I40E_GLPRT_GOTCL(hw->port),
2607 pf->offset_loaded, &os->eth.tx_bytes,
2609 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2610 I40E_GLPRT_UPTCL(hw->port),
2611 pf->offset_loaded, &os->eth.tx_unicast,
2612 &ns->eth.tx_unicast);
2613 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2614 I40E_GLPRT_MPTCL(hw->port),
2615 pf->offset_loaded, &os->eth.tx_multicast,
2616 &ns->eth.tx_multicast);
2617 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2618 I40E_GLPRT_BPTCL(hw->port),
2619 pf->offset_loaded, &os->eth.tx_broadcast,
2620 &ns->eth.tx_broadcast);
2621 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2622 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2624 /* exclude internal tx bytes
2625 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2626 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2628 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2630 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2631 ns->eth.tx_bytes = 0;
2633 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2635 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2636 ns->eth.tx_unicast = 0;
2638 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2640 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2641 ns->eth.tx_multicast = 0;
2643 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2645 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2646 ns->eth.tx_broadcast = 0;
2648 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2650 /* GLPRT_TEPC not supported */
2652 /* additional port specific stats */
2653 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2654 pf->offset_loaded, &os->tx_dropped_link_down,
2655 &ns->tx_dropped_link_down);
2656 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2657 pf->offset_loaded, &os->crc_errors,
2659 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2660 pf->offset_loaded, &os->illegal_bytes,
2661 &ns->illegal_bytes);
2662 /* GLPRT_ERRBC not supported */
2663 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2664 pf->offset_loaded, &os->mac_local_faults,
2665 &ns->mac_local_faults);
2666 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2667 pf->offset_loaded, &os->mac_remote_faults,
2668 &ns->mac_remote_faults);
2669 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2670 pf->offset_loaded, &os->rx_length_errors,
2671 &ns->rx_length_errors);
2672 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2673 pf->offset_loaded, &os->link_xon_rx,
2675 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2676 pf->offset_loaded, &os->link_xoff_rx,
2678 for (i = 0; i < 8; i++) {
2679 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2681 &os->priority_xon_rx[i],
2682 &ns->priority_xon_rx[i]);
2683 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2685 &os->priority_xoff_rx[i],
2686 &ns->priority_xoff_rx[i]);
2688 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2689 pf->offset_loaded, &os->link_xon_tx,
2691 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2692 pf->offset_loaded, &os->link_xoff_tx,
2694 for (i = 0; i < 8; i++) {
2695 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2697 &os->priority_xon_tx[i],
2698 &ns->priority_xon_tx[i]);
2699 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2701 &os->priority_xoff_tx[i],
2702 &ns->priority_xoff_tx[i]);
2703 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2705 &os->priority_xon_2_xoff[i],
2706 &ns->priority_xon_2_xoff[i]);
2708 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2709 I40E_GLPRT_PRC64L(hw->port),
2710 pf->offset_loaded, &os->rx_size_64,
2712 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2713 I40E_GLPRT_PRC127L(hw->port),
2714 pf->offset_loaded, &os->rx_size_127,
2716 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2717 I40E_GLPRT_PRC255L(hw->port),
2718 pf->offset_loaded, &os->rx_size_255,
2720 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2721 I40E_GLPRT_PRC511L(hw->port),
2722 pf->offset_loaded, &os->rx_size_511,
2724 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2725 I40E_GLPRT_PRC1023L(hw->port),
2726 pf->offset_loaded, &os->rx_size_1023,
2728 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2729 I40E_GLPRT_PRC1522L(hw->port),
2730 pf->offset_loaded, &os->rx_size_1522,
2732 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2733 I40E_GLPRT_PRC9522L(hw->port),
2734 pf->offset_loaded, &os->rx_size_big,
2736 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2737 pf->offset_loaded, &os->rx_undersize,
2739 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2740 pf->offset_loaded, &os->rx_fragments,
2742 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2743 pf->offset_loaded, &os->rx_oversize,
2745 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2746 pf->offset_loaded, &os->rx_jabber,
2748 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2749 I40E_GLPRT_PTC64L(hw->port),
2750 pf->offset_loaded, &os->tx_size_64,
2752 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2753 I40E_GLPRT_PTC127L(hw->port),
2754 pf->offset_loaded, &os->tx_size_127,
2756 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2757 I40E_GLPRT_PTC255L(hw->port),
2758 pf->offset_loaded, &os->tx_size_255,
2760 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2761 I40E_GLPRT_PTC511L(hw->port),
2762 pf->offset_loaded, &os->tx_size_511,
2764 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2765 I40E_GLPRT_PTC1023L(hw->port),
2766 pf->offset_loaded, &os->tx_size_1023,
2768 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2769 I40E_GLPRT_PTC1522L(hw->port),
2770 pf->offset_loaded, &os->tx_size_1522,
2772 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2773 I40E_GLPRT_PTC9522L(hw->port),
2774 pf->offset_loaded, &os->tx_size_big,
2776 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2778 &os->fd_sb_match, &ns->fd_sb_match);
2779 /* GLPRT_MSPDC not supported */
2780 /* GLPRT_XEC not supported */
2782 pf->offset_loaded = true;
2785 i40e_update_vsi_stats(pf->main_vsi);
2788 /* Get all statistics of a port */
2790 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2792 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2793 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2797 /* call read registers - updates values, now write them to struct */
2798 i40e_read_stats_registers(pf, hw);
2800 stats->ipackets = ns->eth.rx_unicast +
2801 ns->eth.rx_multicast +
2802 ns->eth.rx_broadcast -
2803 ns->eth.rx_discards -
2804 pf->main_vsi->eth_stats.rx_discards;
2805 stats->opackets = ns->eth.tx_unicast +
2806 ns->eth.tx_multicast +
2807 ns->eth.tx_broadcast;
2808 stats->ibytes = ns->eth.rx_bytes;
2809 stats->obytes = ns->eth.tx_bytes;
2810 stats->oerrors = ns->eth.tx_errors +
2811 pf->main_vsi->eth_stats.tx_errors;
2814 stats->imissed = ns->eth.rx_discards +
2815 pf->main_vsi->eth_stats.rx_discards;
2816 stats->ierrors = ns->crc_errors +
2817 ns->rx_length_errors + ns->rx_undersize +
2818 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2820 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2821 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2822 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2823 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2824 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2825 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2826 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2827 ns->eth.rx_unknown_protocol);
2828 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2829 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2830 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2831 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2832 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2833 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2835 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2836 ns->tx_dropped_link_down);
2837 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2838 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2840 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2841 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2842 ns->mac_local_faults);
2843 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2844 ns->mac_remote_faults);
2845 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2846 ns->rx_length_errors);
2847 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2848 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2849 for (i = 0; i < 8; i++) {
2850 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2851 i, ns->priority_xon_rx[i]);
2852 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2853 i, ns->priority_xoff_rx[i]);
2855 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2856 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2857 for (i = 0; i < 8; i++) {
2858 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2859 i, ns->priority_xon_tx[i]);
2860 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2861 i, ns->priority_xoff_tx[i]);
2862 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2863 i, ns->priority_xon_2_xoff[i]);
2865 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2866 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2867 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2868 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2869 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2870 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2871 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2872 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2873 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2874 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2875 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2876 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2877 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2878 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2879 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2880 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2881 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2882 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2883 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2884 ns->mac_short_packet_dropped);
2885 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2886 ns->checksum_error);
2887 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2888 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2892 /* Reset the statistics */
2894 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2896 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2897 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2899 /* Mark PF and VSI stats to update the offset, aka "reset" */
2900 pf->offset_loaded = false;
2902 pf->main_vsi->offset_loaded = false;
2904 /* read the stats, reading current register values into offset */
2905 i40e_read_stats_registers(pf, hw);
2909 i40e_xstats_calc_num(void)
2911 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2912 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2913 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2916 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2917 struct rte_eth_xstat_name *xstats_names,
2918 __rte_unused unsigned limit)
2923 if (xstats_names == NULL)
2924 return i40e_xstats_calc_num();
2926 /* Note: limit checked in rte_eth_xstats_names() */
2928 /* Get stats from i40e_eth_stats struct */
2929 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2930 snprintf(xstats_names[count].name,
2931 sizeof(xstats_names[count].name),
2932 "%s", rte_i40e_stats_strings[i].name);
2936 /* Get individiual stats from i40e_hw_port struct */
2937 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2938 snprintf(xstats_names[count].name,
2939 sizeof(xstats_names[count].name),
2940 "%s", rte_i40e_hw_port_strings[i].name);
2944 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2945 for (prio = 0; prio < 8; prio++) {
2946 snprintf(xstats_names[count].name,
2947 sizeof(xstats_names[count].name),
2948 "rx_priority%u_%s", prio,
2949 rte_i40e_rxq_prio_strings[i].name);
2954 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2955 for (prio = 0; prio < 8; prio++) {
2956 snprintf(xstats_names[count].name,
2957 sizeof(xstats_names[count].name),
2958 "tx_priority%u_%s", prio,
2959 rte_i40e_txq_prio_strings[i].name);
2967 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2970 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2971 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2972 unsigned i, count, prio;
2973 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2975 count = i40e_xstats_calc_num();
2979 i40e_read_stats_registers(pf, hw);
2986 /* Get stats from i40e_eth_stats struct */
2987 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2988 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2989 rte_i40e_stats_strings[i].offset);
2990 xstats[count].id = count;
2994 /* Get individiual stats from i40e_hw_port struct */
2995 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2996 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2997 rte_i40e_hw_port_strings[i].offset);
2998 xstats[count].id = count;
3002 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3003 for (prio = 0; prio < 8; prio++) {
3004 xstats[count].value =
3005 *(uint64_t *)(((char *)hw_stats) +
3006 rte_i40e_rxq_prio_strings[i].offset +
3007 (sizeof(uint64_t) * prio));
3008 xstats[count].id = count;
3013 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3014 for (prio = 0; prio < 8; prio++) {
3015 xstats[count].value =
3016 *(uint64_t *)(((char *)hw_stats) +
3017 rte_i40e_txq_prio_strings[i].offset +
3018 (sizeof(uint64_t) * prio));
3019 xstats[count].id = count;
3028 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3029 __rte_unused uint16_t queue_id,
3030 __rte_unused uint8_t stat_idx,
3031 __rte_unused uint8_t is_rx)
3033 PMD_INIT_FUNC_TRACE();
3039 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3041 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3047 full_ver = hw->nvm.oem_ver;
3048 ver = (u8)(full_ver >> 24);
3049 build = (u16)((full_ver >> 8) & 0xffff);
3050 patch = (u8)(full_ver & 0xff);
3052 ret = snprintf(fw_version, fw_size,
3053 "%d.%d%d 0x%08x %d.%d.%d",
3054 ((hw->nvm.version >> 12) & 0xf),
3055 ((hw->nvm.version >> 4) & 0xff),
3056 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3059 ret += 1; /* add the size of '\0' */
3060 if (fw_size < (u32)ret)
3067 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3069 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3070 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3071 struct i40e_vsi *vsi = pf->main_vsi;
3072 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3074 dev_info->pci_dev = pci_dev;
3075 dev_info->max_rx_queues = vsi->nb_qps;
3076 dev_info->max_tx_queues = vsi->nb_qps;
3077 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3078 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3079 dev_info->max_mac_addrs = vsi->max_macaddrs;
3080 dev_info->max_vfs = pci_dev->max_vfs;
3081 dev_info->rx_offload_capa =
3082 DEV_RX_OFFLOAD_VLAN_STRIP |
3083 DEV_RX_OFFLOAD_QINQ_STRIP |
3084 DEV_RX_OFFLOAD_IPV4_CKSUM |
3085 DEV_RX_OFFLOAD_UDP_CKSUM |
3086 DEV_RX_OFFLOAD_TCP_CKSUM;
3087 dev_info->tx_offload_capa =
3088 DEV_TX_OFFLOAD_VLAN_INSERT |
3089 DEV_TX_OFFLOAD_QINQ_INSERT |
3090 DEV_TX_OFFLOAD_IPV4_CKSUM |
3091 DEV_TX_OFFLOAD_UDP_CKSUM |
3092 DEV_TX_OFFLOAD_TCP_CKSUM |
3093 DEV_TX_OFFLOAD_SCTP_CKSUM |
3094 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3095 DEV_TX_OFFLOAD_TCP_TSO |
3096 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3097 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3098 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3099 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3100 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3102 dev_info->reta_size = pf->hash_lut_size;
3103 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3105 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3107 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3108 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3109 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3111 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3115 dev_info->default_txconf = (struct rte_eth_txconf) {
3117 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3118 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3119 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3121 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3122 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3123 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3124 ETH_TXQ_FLAGS_NOOFFLOADS,
3127 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3128 .nb_max = I40E_MAX_RING_DESC,
3129 .nb_min = I40E_MIN_RING_DESC,
3130 .nb_align = I40E_ALIGN_RING_DESC,
3133 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3134 .nb_max = I40E_MAX_RING_DESC,
3135 .nb_min = I40E_MIN_RING_DESC,
3136 .nb_align = I40E_ALIGN_RING_DESC,
3137 .nb_seg_max = I40E_TX_MAX_SEG,
3138 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3141 if (pf->flags & I40E_FLAG_VMDQ) {
3142 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3143 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3144 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3145 pf->max_nb_vmdq_vsi;
3146 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3147 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3148 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3151 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3153 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3154 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3156 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3159 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3163 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3165 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3166 struct i40e_vsi *vsi = pf->main_vsi;
3167 PMD_INIT_FUNC_TRACE();
3170 return i40e_vsi_add_vlan(vsi, vlan_id);
3172 return i40e_vsi_delete_vlan(vsi, vlan_id);
3176 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3177 enum rte_vlan_type vlan_type,
3178 uint16_t tpid, int qinq)
3180 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183 uint16_t reg_id = 3;
3187 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3191 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3193 if (ret != I40E_SUCCESS) {
3195 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3200 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3203 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3204 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3205 if (reg_r == reg_w) {
3206 PMD_DRV_LOG(DEBUG, "No need to write");
3210 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3212 if (ret != I40E_SUCCESS) {
3214 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3219 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3226 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3227 enum rte_vlan_type vlan_type,
3230 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3231 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3234 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3235 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3236 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3238 "Unsupported vlan type.");
3241 /* 802.1ad frames ability is added in NVM API 1.7*/
3242 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3244 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3245 hw->first_tag = rte_cpu_to_le_16(tpid);
3246 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3247 hw->second_tag = rte_cpu_to_le_16(tpid);
3249 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3250 hw->second_tag = rte_cpu_to_le_16(tpid);
3252 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3253 if (ret != I40E_SUCCESS) {
3255 "Set switch config failed aq_err: %d",
3256 hw->aq.asq_last_status);
3260 /* If NVM API < 1.7, keep the register setting */
3261 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3268 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3270 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3271 struct i40e_vsi *vsi = pf->main_vsi;
3273 if (mask & ETH_VLAN_FILTER_MASK) {
3274 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3275 i40e_vsi_config_vlan_filter(vsi, TRUE);
3277 i40e_vsi_config_vlan_filter(vsi, FALSE);
3280 if (mask & ETH_VLAN_STRIP_MASK) {
3281 /* Enable or disable VLAN stripping */
3282 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3283 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3285 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3288 if (mask & ETH_VLAN_EXTEND_MASK) {
3289 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3290 i40e_vsi_config_double_vlan(vsi, TRUE);
3291 /* Set global registers with default ethertype. */
3292 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3294 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3298 i40e_vsi_config_double_vlan(vsi, FALSE);
3305 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3306 __rte_unused uint16_t queue,
3307 __rte_unused int on)
3309 PMD_INIT_FUNC_TRACE();
3313 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3315 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3316 struct i40e_vsi *vsi = pf->main_vsi;
3317 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3318 struct i40e_vsi_vlan_pvid_info info;
3320 memset(&info, 0, sizeof(info));
3323 info.config.pvid = pvid;
3325 info.config.reject.tagged =
3326 data->dev_conf.txmode.hw_vlan_reject_tagged;
3327 info.config.reject.untagged =
3328 data->dev_conf.txmode.hw_vlan_reject_untagged;
3331 return i40e_vsi_vlan_pvid_set(vsi, &info);
3335 i40e_dev_led_on(struct rte_eth_dev *dev)
3337 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3338 uint32_t mode = i40e_led_get(hw);
3341 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3347 i40e_dev_led_off(struct rte_eth_dev *dev)
3349 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3350 uint32_t mode = i40e_led_get(hw);
3353 i40e_led_set(hw, 0, false);
3359 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3361 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3362 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3364 fc_conf->pause_time = pf->fc_conf.pause_time;
3366 /* read out from register, in case they are modified by other port */
3367 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3368 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3369 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3370 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3372 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3373 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3375 /* Return current mode according to actual setting*/
3376 switch (hw->fc.current_mode) {
3378 fc_conf->mode = RTE_FC_FULL;
3380 case I40E_FC_TX_PAUSE:
3381 fc_conf->mode = RTE_FC_TX_PAUSE;
3383 case I40E_FC_RX_PAUSE:
3384 fc_conf->mode = RTE_FC_RX_PAUSE;
3388 fc_conf->mode = RTE_FC_NONE;
3395 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3397 uint32_t mflcn_reg, fctrl_reg, reg;
3398 uint32_t max_high_water;
3399 uint8_t i, aq_failure;
3403 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3404 [RTE_FC_NONE] = I40E_FC_NONE,
3405 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3406 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3407 [RTE_FC_FULL] = I40E_FC_FULL
3410 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3412 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3413 if ((fc_conf->high_water > max_high_water) ||
3414 (fc_conf->high_water < fc_conf->low_water)) {
3416 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3421 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3422 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3423 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3425 pf->fc_conf.pause_time = fc_conf->pause_time;
3426 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3427 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3429 PMD_INIT_FUNC_TRACE();
3431 /* All the link flow control related enable/disable register
3432 * configuration is handle by the F/W
3434 err = i40e_set_fc(hw, &aq_failure, true);
3438 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3439 /* Configure flow control refresh threshold,
3440 * the value for stat_tx_pause_refresh_timer[8]
3441 * is used for global pause operation.
3445 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3446 pf->fc_conf.pause_time);
3448 /* configure the timer value included in transmitted pause
3450 * the value for stat_tx_pause_quanta[8] is used for global
3453 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3454 pf->fc_conf.pause_time);
3456 fctrl_reg = I40E_READ_REG(hw,
3457 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3459 if (fc_conf->mac_ctrl_frame_fwd != 0)
3460 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3462 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3464 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3467 /* Configure pause time (2 TCs per register) */
3468 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3469 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3470 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3472 /* Configure flow control refresh threshold value */
3473 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3474 pf->fc_conf.pause_time / 2);
3476 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3478 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3479 *depending on configuration
3481 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3482 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3483 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3485 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3486 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3489 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3492 /* config the water marker both based on the packets and bytes */
3493 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3494 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3495 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3496 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3497 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3498 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3499 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3500 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3502 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3503 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3506 I40E_WRITE_FLUSH(hw);
3512 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3513 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3515 PMD_INIT_FUNC_TRACE();
3520 /* Add a MAC address, and update filters */
3522 i40e_macaddr_add(struct rte_eth_dev *dev,
3523 struct ether_addr *mac_addr,
3524 __rte_unused uint32_t index,
3527 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3528 struct i40e_mac_filter_info mac_filter;
3529 struct i40e_vsi *vsi;
3532 /* If VMDQ not enabled or configured, return */
3533 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3534 !pf->nb_cfg_vmdq_vsi)) {
3535 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3536 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3541 if (pool > pf->nb_cfg_vmdq_vsi) {
3542 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3543 pool, pf->nb_cfg_vmdq_vsi);
3547 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3548 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3549 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3551 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3556 vsi = pf->vmdq[pool - 1].vsi;
3558 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3559 if (ret != I40E_SUCCESS) {
3560 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3566 /* Remove a MAC address, and update filters */
3568 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3571 struct i40e_vsi *vsi;
3572 struct rte_eth_dev_data *data = dev->data;
3573 struct ether_addr *macaddr;
3578 macaddr = &(data->mac_addrs[index]);
3580 pool_sel = dev->data->mac_pool_sel[index];
3582 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3583 if (pool_sel & (1ULL << i)) {
3587 /* No VMDQ pool enabled or configured */
3588 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3589 (i > pf->nb_cfg_vmdq_vsi)) {
3591 "No VMDQ pool enabled/configured");
3594 vsi = pf->vmdq[i - 1].vsi;
3596 ret = i40e_vsi_delete_mac(vsi, macaddr);
3599 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3606 /* Set perfect match or hash match of MAC and VLAN for a VF */
3608 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3609 struct rte_eth_mac_filter *filter,
3613 struct i40e_mac_filter_info mac_filter;
3614 struct ether_addr old_mac;
3615 struct ether_addr *new_mac;
3616 struct i40e_pf_vf *vf = NULL;
3621 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3624 hw = I40E_PF_TO_HW(pf);
3626 if (filter == NULL) {
3627 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3631 new_mac = &filter->mac_addr;
3633 if (is_zero_ether_addr(new_mac)) {
3634 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3638 vf_id = filter->dst_id;
3640 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3641 PMD_DRV_LOG(ERR, "Invalid argument.");
3644 vf = &pf->vfs[vf_id];
3646 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3647 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3652 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3653 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3655 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3658 mac_filter.filter_type = filter->filter_type;
3659 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3660 if (ret != I40E_SUCCESS) {
3661 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3664 ether_addr_copy(new_mac, &pf->dev_addr);
3666 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3668 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3669 if (ret != I40E_SUCCESS) {
3670 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3674 /* Clear device address as it has been removed */
3675 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3676 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3682 /* MAC filter handle */
3684 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3687 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3688 struct rte_eth_mac_filter *filter;
3689 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3690 int ret = I40E_NOT_SUPPORTED;
3692 filter = (struct rte_eth_mac_filter *)(arg);
3694 switch (filter_op) {
3695 case RTE_ETH_FILTER_NOP:
3698 case RTE_ETH_FILTER_ADD:
3699 i40e_pf_disable_irq0(hw);
3701 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3702 i40e_pf_enable_irq0(hw);
3704 case RTE_ETH_FILTER_DELETE:
3705 i40e_pf_disable_irq0(hw);
3707 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3708 i40e_pf_enable_irq0(hw);
3711 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3712 ret = I40E_ERR_PARAM;
3720 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3722 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3723 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3730 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3731 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3734 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3738 uint32_t *lut_dw = (uint32_t *)lut;
3739 uint16_t i, lut_size_dw = lut_size / 4;
3741 if (vsi->type == I40E_VSI_SRIOV) {
3742 for (i = 0; i <= lut_size_dw; i++) {
3743 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3744 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3747 for (i = 0; i < lut_size_dw; i++)
3748 lut_dw[i] = I40E_READ_REG(hw,
3757 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3766 pf = I40E_VSI_TO_PF(vsi);
3767 hw = I40E_VSI_TO_HW(vsi);
3769 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3770 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3773 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3777 uint32_t *lut_dw = (uint32_t *)lut;
3778 uint16_t i, lut_size_dw = lut_size / 4;
3780 if (vsi->type == I40E_VSI_SRIOV) {
3781 for (i = 0; i < lut_size_dw; i++)
3784 I40E_VFQF_HLUT1(i, vsi->user_param),
3787 for (i = 0; i < lut_size_dw; i++)
3788 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3791 I40E_WRITE_FLUSH(hw);
3798 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3799 struct rte_eth_rss_reta_entry64 *reta_conf,
3802 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3803 uint16_t i, lut_size = pf->hash_lut_size;
3804 uint16_t idx, shift;
3808 if (reta_size != lut_size ||
3809 reta_size > ETH_RSS_RETA_SIZE_512) {
3811 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3812 reta_size, lut_size);
3816 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3818 PMD_DRV_LOG(ERR, "No memory can be allocated");
3821 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3824 for (i = 0; i < reta_size; i++) {
3825 idx = i / RTE_RETA_GROUP_SIZE;
3826 shift = i % RTE_RETA_GROUP_SIZE;
3827 if (reta_conf[idx].mask & (1ULL << shift))
3828 lut[i] = reta_conf[idx].reta[shift];
3830 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3839 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3840 struct rte_eth_rss_reta_entry64 *reta_conf,
3843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3844 uint16_t i, lut_size = pf->hash_lut_size;
3845 uint16_t idx, shift;
3849 if (reta_size != lut_size ||
3850 reta_size > ETH_RSS_RETA_SIZE_512) {
3852 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3853 reta_size, lut_size);
3857 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3859 PMD_DRV_LOG(ERR, "No memory can be allocated");
3863 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3866 for (i = 0; i < reta_size; i++) {
3867 idx = i / RTE_RETA_GROUP_SIZE;
3868 shift = i % RTE_RETA_GROUP_SIZE;
3869 if (reta_conf[idx].mask & (1ULL << shift))
3870 reta_conf[idx].reta[shift] = lut[i];
3880 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3881 * @hw: pointer to the HW structure
3882 * @mem: pointer to mem struct to fill out
3883 * @size: size of memory requested
3884 * @alignment: what to align the allocation to
3886 enum i40e_status_code
3887 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3888 struct i40e_dma_mem *mem,
3892 const struct rte_memzone *mz = NULL;
3893 char z_name[RTE_MEMZONE_NAMESIZE];
3896 return I40E_ERR_PARAM;
3898 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3899 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3900 alignment, RTE_PGSIZE_2M);
3902 return I40E_ERR_NO_MEMORY;
3907 mem->zone = (const void *)mz;
3909 "memzone %s allocated with physical address: %"PRIu64,
3912 return I40E_SUCCESS;
3916 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3917 * @hw: pointer to the HW structure
3918 * @mem: ptr to mem struct to free
3920 enum i40e_status_code
3921 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3922 struct i40e_dma_mem *mem)
3925 return I40E_ERR_PARAM;
3928 "memzone %s to be freed with physical address: %"PRIu64,
3929 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3930 rte_memzone_free((const struct rte_memzone *)mem->zone);
3935 return I40E_SUCCESS;
3939 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3940 * @hw: pointer to the HW structure
3941 * @mem: pointer to mem struct to fill out
3942 * @size: size of memory requested
3944 enum i40e_status_code
3945 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3946 struct i40e_virt_mem *mem,
3950 return I40E_ERR_PARAM;
3953 mem->va = rte_zmalloc("i40e", size, 0);
3956 return I40E_SUCCESS;
3958 return I40E_ERR_NO_MEMORY;
3962 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3963 * @hw: pointer to the HW structure
3964 * @mem: pointer to mem struct to free
3966 enum i40e_status_code
3967 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3968 struct i40e_virt_mem *mem)
3971 return I40E_ERR_PARAM;
3976 return I40E_SUCCESS;
3980 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3982 rte_spinlock_init(&sp->spinlock);
3986 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3988 rte_spinlock_lock(&sp->spinlock);
3992 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3994 rte_spinlock_unlock(&sp->spinlock);
3998 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4004 * Get the hardware capabilities, which will be parsed
4005 * and saved into struct i40e_hw.
4008 i40e_get_cap(struct i40e_hw *hw)
4010 struct i40e_aqc_list_capabilities_element_resp *buf;
4011 uint16_t len, size = 0;
4014 /* Calculate a huge enough buff for saving response data temporarily */
4015 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4016 I40E_MAX_CAP_ELE_NUM;
4017 buf = rte_zmalloc("i40e", len, 0);
4019 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4020 return I40E_ERR_NO_MEMORY;
4023 /* Get, parse the capabilities and save it to hw */
4024 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4025 i40e_aqc_opc_list_func_capabilities, NULL);
4026 if (ret != I40E_SUCCESS)
4027 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4029 /* Free the temporary buffer after being used */
4035 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4036 #define QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
4037 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16");
4039 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4047 pf = (struct i40e_pf *)opaque;
4051 num = strtoul(value, &end, 0);
4052 if (errno != 0 || end == value || *end != 0) {
4053 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4054 "kept the value = %hu", value, pf->vf_nb_qp_max);
4058 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4059 pf->vf_nb_qp_max = (uint16_t)num;
4061 /* here return 0 to make next valid same argument work */
4062 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4063 "power of 2 and equal or less than 16 !, Now it is "
4064 "kept the value = %hu", num, pf->vf_nb_qp_max);
4069 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4071 static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4072 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4073 struct rte_kvargs *kvlist;
4075 /* set default queue number per VF as 4 */
4076 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4078 if (dev->device->devargs == NULL)
4081 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4085 if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4086 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4087 "the first invalid or last valid one is used !",
4088 QUEUE_NUM_PER_VF_ARG);
4090 rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4091 i40e_pf_parse_vf_queue_number_handler, pf);
4093 rte_kvargs_free(kvlist);
4099 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4101 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4102 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4103 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4104 uint16_t qp_count = 0, vsi_count = 0;
4106 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4107 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4111 i40e_pf_config_vf_rxq_number(dev);
4113 /* Add the parameter init for LFC */
4114 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4115 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4116 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4118 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4119 pf->max_num_vsi = hw->func_caps.num_vsis;
4120 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4121 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4123 /* FDir queue/VSI allocation */
4124 pf->fdir_qp_offset = 0;
4125 if (hw->func_caps.fd) {
4126 pf->flags |= I40E_FLAG_FDIR;
4127 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4129 pf->fdir_nb_qps = 0;
4131 qp_count += pf->fdir_nb_qps;
4134 /* LAN queue/VSI allocation */
4135 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4136 if (!hw->func_caps.rss) {
4139 pf->flags |= I40E_FLAG_RSS;
4140 if (hw->mac.type == I40E_MAC_X722)
4141 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4142 pf->lan_nb_qps = pf->lan_nb_qp_max;
4144 qp_count += pf->lan_nb_qps;
4147 /* VF queue/VSI allocation */
4148 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4149 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4150 pf->flags |= I40E_FLAG_SRIOV;
4151 pf->vf_nb_qps = pf->vf_nb_qp_max;
4152 pf->vf_num = pci_dev->max_vfs;
4154 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4155 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4160 qp_count += pf->vf_nb_qps * pf->vf_num;
4161 vsi_count += pf->vf_num;
4163 /* VMDq queue/VSI allocation */
4164 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4165 pf->vmdq_nb_qps = 0;
4166 pf->max_nb_vmdq_vsi = 0;
4167 if (hw->func_caps.vmdq) {
4168 if (qp_count < hw->func_caps.num_tx_qp &&
4169 vsi_count < hw->func_caps.num_vsis) {
4170 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4171 qp_count) / pf->vmdq_nb_qp_max;
4173 /* Limit the maximum number of VMDq vsi to the maximum
4174 * ethdev can support
4176 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4177 hw->func_caps.num_vsis - vsi_count);
4178 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4180 if (pf->max_nb_vmdq_vsi) {
4181 pf->flags |= I40E_FLAG_VMDQ;
4182 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4184 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4185 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4186 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4189 "No enough queues left for VMDq");
4192 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4195 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4196 vsi_count += pf->max_nb_vmdq_vsi;
4198 if (hw->func_caps.dcb)
4199 pf->flags |= I40E_FLAG_DCB;
4201 if (qp_count > hw->func_caps.num_tx_qp) {
4203 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4204 qp_count, hw->func_caps.num_tx_qp);
4207 if (vsi_count > hw->func_caps.num_vsis) {
4209 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4210 vsi_count, hw->func_caps.num_vsis);
4218 i40e_pf_get_switch_config(struct i40e_pf *pf)
4220 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4221 struct i40e_aqc_get_switch_config_resp *switch_config;
4222 struct i40e_aqc_switch_config_element_resp *element;
4223 uint16_t start_seid = 0, num_reported;
4226 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4227 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4228 if (!switch_config) {
4229 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4233 /* Get the switch configurations */
4234 ret = i40e_aq_get_switch_config(hw, switch_config,
4235 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4236 if (ret != I40E_SUCCESS) {
4237 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4240 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4241 if (num_reported != 1) { /* The number should be 1 */
4242 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4246 /* Parse the switch configuration elements */
4247 element = &(switch_config->element[0]);
4248 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4249 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4250 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4252 PMD_DRV_LOG(INFO, "Unknown element type");
4255 rte_free(switch_config);
4261 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4264 struct pool_entry *entry;
4266 if (pool == NULL || num == 0)
4269 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4270 if (entry == NULL) {
4271 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4275 /* queue heap initialize */
4276 pool->num_free = num;
4277 pool->num_alloc = 0;
4279 LIST_INIT(&pool->alloc_list);
4280 LIST_INIT(&pool->free_list);
4282 /* Initialize element */
4286 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4291 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4293 struct pool_entry *entry, *next_entry;
4298 for (entry = LIST_FIRST(&pool->alloc_list);
4299 entry && (next_entry = LIST_NEXT(entry, next), 1);
4300 entry = next_entry) {
4301 LIST_REMOVE(entry, next);
4305 for (entry = LIST_FIRST(&pool->free_list);
4306 entry && (next_entry = LIST_NEXT(entry, next), 1);
4307 entry = next_entry) {
4308 LIST_REMOVE(entry, next);
4313 pool->num_alloc = 0;
4315 LIST_INIT(&pool->alloc_list);
4316 LIST_INIT(&pool->free_list);
4320 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4323 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4324 uint32_t pool_offset;
4328 PMD_DRV_LOG(ERR, "Invalid parameter");
4332 pool_offset = base - pool->base;
4333 /* Lookup in alloc list */
4334 LIST_FOREACH(entry, &pool->alloc_list, next) {
4335 if (entry->base == pool_offset) {
4336 valid_entry = entry;
4337 LIST_REMOVE(entry, next);
4342 /* Not find, return */
4343 if (valid_entry == NULL) {
4344 PMD_DRV_LOG(ERR, "Failed to find entry");
4349 * Found it, move it to free list and try to merge.
4350 * In order to make merge easier, always sort it by qbase.
4351 * Find adjacent prev and last entries.
4354 LIST_FOREACH(entry, &pool->free_list, next) {
4355 if (entry->base > valid_entry->base) {
4363 /* Try to merge with next one*/
4365 /* Merge with next one */
4366 if (valid_entry->base + valid_entry->len == next->base) {
4367 next->base = valid_entry->base;
4368 next->len += valid_entry->len;
4369 rte_free(valid_entry);
4376 /* Merge with previous one */
4377 if (prev->base + prev->len == valid_entry->base) {
4378 prev->len += valid_entry->len;
4379 /* If it merge with next one, remove next node */
4381 LIST_REMOVE(valid_entry, next);
4382 rte_free(valid_entry);
4384 rte_free(valid_entry);
4390 /* Not find any entry to merge, insert */
4393 LIST_INSERT_AFTER(prev, valid_entry, next);
4394 else if (next != NULL)
4395 LIST_INSERT_BEFORE(next, valid_entry, next);
4396 else /* It's empty list, insert to head */
4397 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4400 pool->num_free += valid_entry->len;
4401 pool->num_alloc -= valid_entry->len;
4407 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4410 struct pool_entry *entry, *valid_entry;
4412 if (pool == NULL || num == 0) {
4413 PMD_DRV_LOG(ERR, "Invalid parameter");
4417 if (pool->num_free < num) {
4418 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4419 num, pool->num_free);
4424 /* Lookup in free list and find most fit one */
4425 LIST_FOREACH(entry, &pool->free_list, next) {
4426 if (entry->len >= num) {
4428 if (entry->len == num) {
4429 valid_entry = entry;
4432 if (valid_entry == NULL || valid_entry->len > entry->len)
4433 valid_entry = entry;
4437 /* Not find one to satisfy the request, return */
4438 if (valid_entry == NULL) {
4439 PMD_DRV_LOG(ERR, "No valid entry found");
4443 * The entry have equal queue number as requested,
4444 * remove it from alloc_list.
4446 if (valid_entry->len == num) {
4447 LIST_REMOVE(valid_entry, next);
4450 * The entry have more numbers than requested,
4451 * create a new entry for alloc_list and minus its
4452 * queue base and number in free_list.
4454 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4455 if (entry == NULL) {
4457 "Failed to allocate memory for resource pool");
4460 entry->base = valid_entry->base;
4462 valid_entry->base += num;
4463 valid_entry->len -= num;
4464 valid_entry = entry;
4467 /* Insert it into alloc list, not sorted */
4468 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4470 pool->num_free -= valid_entry->len;
4471 pool->num_alloc += valid_entry->len;
4473 return valid_entry->base + pool->base;
4477 * bitmap_is_subset - Check whether src2 is subset of src1
4480 bitmap_is_subset(uint8_t src1, uint8_t src2)
4482 return !((src1 ^ src2) & src2);
4485 static enum i40e_status_code
4486 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4488 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4490 /* If DCB is not supported, only default TC is supported */
4491 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4492 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4493 return I40E_NOT_SUPPORTED;
4496 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4498 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4499 hw->func_caps.enabled_tcmap, enabled_tcmap);
4500 return I40E_NOT_SUPPORTED;
4502 return I40E_SUCCESS;
4506 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4507 struct i40e_vsi_vlan_pvid_info *info)
4510 struct i40e_vsi_context ctxt;
4511 uint8_t vlan_flags = 0;
4514 if (vsi == NULL || info == NULL) {
4515 PMD_DRV_LOG(ERR, "invalid parameters");
4516 return I40E_ERR_PARAM;
4520 vsi->info.pvid = info->config.pvid;
4522 * If insert pvid is enabled, only tagged pkts are
4523 * allowed to be sent out.
4525 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4526 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4529 if (info->config.reject.tagged == 0)
4530 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4532 if (info->config.reject.untagged == 0)
4533 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4535 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4536 I40E_AQ_VSI_PVLAN_MODE_MASK);
4537 vsi->info.port_vlan_flags |= vlan_flags;
4538 vsi->info.valid_sections =
4539 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4540 memset(&ctxt, 0, sizeof(ctxt));
4541 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4542 ctxt.seid = vsi->seid;
4544 hw = I40E_VSI_TO_HW(vsi);
4545 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4546 if (ret != I40E_SUCCESS)
4547 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4553 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4555 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4557 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4559 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4560 if (ret != I40E_SUCCESS)
4564 PMD_DRV_LOG(ERR, "seid not valid");
4568 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4569 tc_bw_data.tc_valid_bits = enabled_tcmap;
4570 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4571 tc_bw_data.tc_bw_credits[i] =
4572 (enabled_tcmap & (1 << i)) ? 1 : 0;
4574 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4575 if (ret != I40E_SUCCESS) {
4576 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4580 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4581 sizeof(vsi->info.qs_handle));
4582 return I40E_SUCCESS;
4585 static enum i40e_status_code
4586 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4587 struct i40e_aqc_vsi_properties_data *info,
4588 uint8_t enabled_tcmap)
4590 enum i40e_status_code ret;
4591 int i, total_tc = 0;
4592 uint16_t qpnum_per_tc, bsf, qp_idx;
4594 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4595 if (ret != I40E_SUCCESS)
4598 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4599 if (enabled_tcmap & (1 << i))
4603 vsi->enabled_tc = enabled_tcmap;
4605 /* Number of queues per enabled TC */
4606 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4607 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4608 bsf = rte_bsf32(qpnum_per_tc);
4610 /* Adjust the queue number to actual queues that can be applied */
4611 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4612 vsi->nb_qps = qpnum_per_tc * total_tc;
4615 * Configure TC and queue mapping parameters, for enabled TC,
4616 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4617 * default queue will serve it.
4620 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4621 if (vsi->enabled_tc & (1 << i)) {
4622 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4623 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4624 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4625 qp_idx += qpnum_per_tc;
4627 info->tc_mapping[i] = 0;
4630 /* Associate queue number with VSI */
4631 if (vsi->type == I40E_VSI_SRIOV) {
4632 info->mapping_flags |=
4633 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4634 for (i = 0; i < vsi->nb_qps; i++)
4635 info->queue_mapping[i] =
4636 rte_cpu_to_le_16(vsi->base_queue + i);
4638 info->mapping_flags |=
4639 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4640 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4642 info->valid_sections |=
4643 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4645 return I40E_SUCCESS;
4649 i40e_veb_release(struct i40e_veb *veb)
4651 struct i40e_vsi *vsi;
4657 if (!TAILQ_EMPTY(&veb->head)) {
4658 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4661 /* associate_vsi field is NULL for floating VEB */
4662 if (veb->associate_vsi != NULL) {
4663 vsi = veb->associate_vsi;
4664 hw = I40E_VSI_TO_HW(vsi);
4666 vsi->uplink_seid = veb->uplink_seid;
4669 veb->associate_pf->main_vsi->floating_veb = NULL;
4670 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4673 i40e_aq_delete_element(hw, veb->seid, NULL);
4675 return I40E_SUCCESS;
4679 static struct i40e_veb *
4680 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4682 struct i40e_veb *veb;
4688 "veb setup failed, associated PF shouldn't null");
4691 hw = I40E_PF_TO_HW(pf);
4693 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4695 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4699 veb->associate_vsi = vsi;
4700 veb->associate_pf = pf;
4701 TAILQ_INIT(&veb->head);
4702 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4704 /* create floating veb if vsi is NULL */
4706 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4707 I40E_DEFAULT_TCMAP, false,
4708 &veb->seid, false, NULL);
4710 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4711 true, &veb->seid, false, NULL);
4714 if (ret != I40E_SUCCESS) {
4715 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4716 hw->aq.asq_last_status);
4719 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4721 /* get statistics index */
4722 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4723 &veb->stats_idx, NULL, NULL, NULL);
4724 if (ret != I40E_SUCCESS) {
4725 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4726 hw->aq.asq_last_status);
4729 /* Get VEB bandwidth, to be implemented */
4730 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4732 vsi->uplink_seid = veb->seid;
4741 i40e_vsi_release(struct i40e_vsi *vsi)
4745 struct i40e_vsi_list *vsi_list;
4748 struct i40e_mac_filter *f;
4749 uint16_t user_param;
4752 return I40E_SUCCESS;
4757 user_param = vsi->user_param;
4759 pf = I40E_VSI_TO_PF(vsi);
4760 hw = I40E_VSI_TO_HW(vsi);
4762 /* VSI has child to attach, release child first */
4764 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4765 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4768 i40e_veb_release(vsi->veb);
4771 if (vsi->floating_veb) {
4772 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4773 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4778 /* Remove all macvlan filters of the VSI */
4779 i40e_vsi_remove_all_macvlan_filter(vsi);
4780 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4783 if (vsi->type != I40E_VSI_MAIN &&
4784 ((vsi->type != I40E_VSI_SRIOV) ||
4785 !pf->floating_veb_list[user_param])) {
4786 /* Remove vsi from parent's sibling list */
4787 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4788 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4789 return I40E_ERR_PARAM;
4791 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4792 &vsi->sib_vsi_list, list);
4794 /* Remove all switch element of the VSI */
4795 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4796 if (ret != I40E_SUCCESS)
4797 PMD_DRV_LOG(ERR, "Failed to delete element");
4800 if ((vsi->type == I40E_VSI_SRIOV) &&
4801 pf->floating_veb_list[user_param]) {
4802 /* Remove vsi from parent's sibling list */
4803 if (vsi->parent_vsi == NULL ||
4804 vsi->parent_vsi->floating_veb == NULL) {
4805 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4806 return I40E_ERR_PARAM;
4808 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4809 &vsi->sib_vsi_list, list);
4811 /* Remove all switch element of the VSI */
4812 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4813 if (ret != I40E_SUCCESS)
4814 PMD_DRV_LOG(ERR, "Failed to delete element");
4817 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4819 if (vsi->type != I40E_VSI_SRIOV)
4820 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4823 return I40E_SUCCESS;
4827 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4829 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4830 struct i40e_aqc_remove_macvlan_element_data def_filter;
4831 struct i40e_mac_filter_info filter;
4834 if (vsi->type != I40E_VSI_MAIN)
4835 return I40E_ERR_CONFIG;
4836 memset(&def_filter, 0, sizeof(def_filter));
4837 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4839 def_filter.vlan_tag = 0;
4840 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4841 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4842 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4843 if (ret != I40E_SUCCESS) {
4844 struct i40e_mac_filter *f;
4845 struct ether_addr *mac;
4848 "Cannot remove the default macvlan filter");
4849 /* It needs to add the permanent mac into mac list */
4850 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4852 PMD_DRV_LOG(ERR, "failed to allocate memory");
4853 return I40E_ERR_NO_MEMORY;
4855 mac = &f->mac_info.mac_addr;
4856 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4858 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4859 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4864 rte_memcpy(&filter.mac_addr,
4865 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4866 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4867 return i40e_vsi_add_mac(vsi, &filter);
4871 * i40e_vsi_get_bw_config - Query VSI BW Information
4872 * @vsi: the VSI to be queried
4874 * Returns 0 on success, negative value on failure
4876 static enum i40e_status_code
4877 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4879 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4880 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4881 struct i40e_hw *hw = &vsi->adapter->hw;
4886 memset(&bw_config, 0, sizeof(bw_config));
4887 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4888 if (ret != I40E_SUCCESS) {
4889 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4890 hw->aq.asq_last_status);
4894 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4895 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4896 &ets_sla_config, NULL);
4897 if (ret != I40E_SUCCESS) {
4899 "VSI failed to get TC bandwdith configuration %u",
4900 hw->aq.asq_last_status);
4904 /* store and print out BW info */
4905 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4906 vsi->bw_info.bw_max = bw_config.max_bw;
4907 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4908 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4909 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4910 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4912 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4913 vsi->bw_info.bw_ets_share_credits[i] =
4914 ets_sla_config.share_credits[i];
4915 vsi->bw_info.bw_ets_credits[i] =
4916 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4917 /* 4 bits per TC, 4th bit is reserved */
4918 vsi->bw_info.bw_ets_max[i] =
4919 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4920 RTE_LEN2MASK(3, uint8_t));
4921 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4922 vsi->bw_info.bw_ets_share_credits[i]);
4923 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4924 vsi->bw_info.bw_ets_credits[i]);
4925 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4926 vsi->bw_info.bw_ets_max[i]);
4929 return I40E_SUCCESS;
4932 /* i40e_enable_pf_lb
4933 * @pf: pointer to the pf structure
4935 * allow loopback on pf
4938 i40e_enable_pf_lb(struct i40e_pf *pf)
4940 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4941 struct i40e_vsi_context ctxt;
4944 /* Use the FW API if FW >= v5.0 */
4945 if (hw->aq.fw_maj_ver < 5) {
4946 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4950 memset(&ctxt, 0, sizeof(ctxt));
4951 ctxt.seid = pf->main_vsi_seid;
4952 ctxt.pf_num = hw->pf_id;
4953 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4955 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4956 ret, hw->aq.asq_last_status);
4959 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4960 ctxt.info.valid_sections =
4961 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4962 ctxt.info.switch_id |=
4963 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4965 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4967 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4968 hw->aq.asq_last_status);
4973 i40e_vsi_setup(struct i40e_pf *pf,
4974 enum i40e_vsi_type type,
4975 struct i40e_vsi *uplink_vsi,
4976 uint16_t user_param)
4978 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4979 struct i40e_vsi *vsi;
4980 struct i40e_mac_filter_info filter;
4982 struct i40e_vsi_context ctxt;
4983 struct ether_addr broadcast =
4984 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4986 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4987 uplink_vsi == NULL) {
4989 "VSI setup failed, VSI link shouldn't be NULL");
4993 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4995 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5000 * 1.type is not MAIN and uplink vsi is not NULL
5001 * If uplink vsi didn't setup VEB, create one first under veb field
5002 * 2.type is SRIOV and the uplink is NULL
5003 * If floating VEB is NULL, create one veb under floating veb field
5006 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5007 uplink_vsi->veb == NULL) {
5008 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5010 if (uplink_vsi->veb == NULL) {
5011 PMD_DRV_LOG(ERR, "VEB setup failed");
5014 /* set ALLOWLOOPBACk on pf, when veb is created */
5015 i40e_enable_pf_lb(pf);
5018 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5019 pf->main_vsi->floating_veb == NULL) {
5020 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5022 if (pf->main_vsi->floating_veb == NULL) {
5023 PMD_DRV_LOG(ERR, "VEB setup failed");
5028 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5030 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5033 TAILQ_INIT(&vsi->mac_list);
5035 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5036 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5037 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5038 vsi->user_param = user_param;
5039 vsi->vlan_anti_spoof_on = 0;
5040 vsi->vlan_filter_on = 0;
5041 /* Allocate queues */
5042 switch (vsi->type) {
5043 case I40E_VSI_MAIN :
5044 vsi->nb_qps = pf->lan_nb_qps;
5046 case I40E_VSI_SRIOV :
5047 vsi->nb_qps = pf->vf_nb_qps;
5049 case I40E_VSI_VMDQ2:
5050 vsi->nb_qps = pf->vmdq_nb_qps;
5053 vsi->nb_qps = pf->fdir_nb_qps;
5059 * The filter status descriptor is reported in rx queue 0,
5060 * while the tx queue for fdir filter programming has no
5061 * such constraints, can be non-zero queues.
5062 * To simplify it, choose FDIR vsi use queue 0 pair.
5063 * To make sure it will use queue 0 pair, queue allocation
5064 * need be done before this function is called
5066 if (type != I40E_VSI_FDIR) {
5067 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5069 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5073 vsi->base_queue = ret;
5075 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5077 /* VF has MSIX interrupt in VF range, don't allocate here */
5078 if (type == I40E_VSI_MAIN) {
5079 ret = i40e_res_pool_alloc(&pf->msix_pool,
5080 RTE_MIN(vsi->nb_qps,
5081 RTE_MAX_RXTX_INTR_VEC_ID));
5083 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
5085 goto fail_queue_alloc;
5087 vsi->msix_intr = ret;
5088 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
5089 } else if (type != I40E_VSI_SRIOV) {
5090 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5092 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5093 goto fail_queue_alloc;
5095 vsi->msix_intr = ret;
5103 if (type == I40E_VSI_MAIN) {
5104 /* For main VSI, no need to add since it's default one */
5105 vsi->uplink_seid = pf->mac_seid;
5106 vsi->seid = pf->main_vsi_seid;
5107 /* Bind queues with specific MSIX interrupt */
5109 * Needs 2 interrupt at least, one for misc cause which will
5110 * enabled from OS side, Another for queues binding the
5111 * interrupt from device side only.
5114 /* Get default VSI parameters from hardware */
5115 memset(&ctxt, 0, sizeof(ctxt));
5116 ctxt.seid = vsi->seid;
5117 ctxt.pf_num = hw->pf_id;
5118 ctxt.uplink_seid = vsi->uplink_seid;
5120 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5121 if (ret != I40E_SUCCESS) {
5122 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5123 goto fail_msix_alloc;
5125 rte_memcpy(&vsi->info, &ctxt.info,
5126 sizeof(struct i40e_aqc_vsi_properties_data));
5127 vsi->vsi_id = ctxt.vsi_number;
5128 vsi->info.valid_sections = 0;
5130 /* Configure tc, enabled TC0 only */
5131 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5133 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5134 goto fail_msix_alloc;
5137 /* TC, queue mapping */
5138 memset(&ctxt, 0, sizeof(ctxt));
5139 vsi->info.valid_sections |=
5140 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5141 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5142 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5143 rte_memcpy(&ctxt.info, &vsi->info,
5144 sizeof(struct i40e_aqc_vsi_properties_data));
5145 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5146 I40E_DEFAULT_TCMAP);
5147 if (ret != I40E_SUCCESS) {
5149 "Failed to configure TC queue mapping");
5150 goto fail_msix_alloc;
5152 ctxt.seid = vsi->seid;
5153 ctxt.pf_num = hw->pf_id;
5154 ctxt.uplink_seid = vsi->uplink_seid;
5157 /* Update VSI parameters */
5158 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5159 if (ret != I40E_SUCCESS) {
5160 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5161 goto fail_msix_alloc;
5164 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5165 sizeof(vsi->info.tc_mapping));
5166 rte_memcpy(&vsi->info.queue_mapping,
5167 &ctxt.info.queue_mapping,
5168 sizeof(vsi->info.queue_mapping));
5169 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5170 vsi->info.valid_sections = 0;
5172 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5176 * Updating default filter settings are necessary to prevent
5177 * reception of tagged packets.
5178 * Some old firmware configurations load a default macvlan
5179 * filter which accepts both tagged and untagged packets.
5180 * The updating is to use a normal filter instead if needed.
5181 * For NVM 4.2.2 or after, the updating is not needed anymore.
5182 * The firmware with correct configurations load the default
5183 * macvlan filter which is expected and cannot be removed.
5185 i40e_update_default_filter_setting(vsi);
5186 i40e_config_qinq(hw, vsi);
5187 } else if (type == I40E_VSI_SRIOV) {
5188 memset(&ctxt, 0, sizeof(ctxt));
5190 * For other VSI, the uplink_seid equals to uplink VSI's
5191 * uplink_seid since they share same VEB
5193 if (uplink_vsi == NULL)
5194 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5196 vsi->uplink_seid = uplink_vsi->uplink_seid;
5197 ctxt.pf_num = hw->pf_id;
5198 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5199 ctxt.uplink_seid = vsi->uplink_seid;
5200 ctxt.connection_type = 0x1;
5201 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5203 /* Use the VEB configuration if FW >= v5.0 */
5204 if (hw->aq.fw_maj_ver >= 5) {
5205 /* Configure switch ID */
5206 ctxt.info.valid_sections |=
5207 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5208 ctxt.info.switch_id =
5209 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5212 /* Configure port/vlan */
5213 ctxt.info.valid_sections |=
5214 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5215 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5216 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5217 hw->func_caps.enabled_tcmap);
5218 if (ret != I40E_SUCCESS) {
5220 "Failed to configure TC queue mapping");
5221 goto fail_msix_alloc;
5224 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5225 ctxt.info.valid_sections |=
5226 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5228 * Since VSI is not created yet, only configure parameter,
5229 * will add vsi below.
5232 i40e_config_qinq(hw, vsi);
5233 } else if (type == I40E_VSI_VMDQ2) {
5234 memset(&ctxt, 0, sizeof(ctxt));
5236 * For other VSI, the uplink_seid equals to uplink VSI's
5237 * uplink_seid since they share same VEB
5239 vsi->uplink_seid = uplink_vsi->uplink_seid;
5240 ctxt.pf_num = hw->pf_id;
5242 ctxt.uplink_seid = vsi->uplink_seid;
5243 ctxt.connection_type = 0x1;
5244 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5246 ctxt.info.valid_sections |=
5247 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5248 /* user_param carries flag to enable loop back */
5250 ctxt.info.switch_id =
5251 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5252 ctxt.info.switch_id |=
5253 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5256 /* Configure port/vlan */
5257 ctxt.info.valid_sections |=
5258 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5259 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5260 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5261 I40E_DEFAULT_TCMAP);
5262 if (ret != I40E_SUCCESS) {
5264 "Failed to configure TC queue mapping");
5265 goto fail_msix_alloc;
5267 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5268 ctxt.info.valid_sections |=
5269 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5270 } else if (type == I40E_VSI_FDIR) {
5271 memset(&ctxt, 0, sizeof(ctxt));
5272 vsi->uplink_seid = uplink_vsi->uplink_seid;
5273 ctxt.pf_num = hw->pf_id;
5275 ctxt.uplink_seid = vsi->uplink_seid;
5276 ctxt.connection_type = 0x1; /* regular data port */
5277 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5278 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5279 I40E_DEFAULT_TCMAP);
5280 if (ret != I40E_SUCCESS) {
5282 "Failed to configure TC queue mapping.");
5283 goto fail_msix_alloc;
5285 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5286 ctxt.info.valid_sections |=
5287 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5289 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5290 goto fail_msix_alloc;
5293 if (vsi->type != I40E_VSI_MAIN) {
5294 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5295 if (ret != I40E_SUCCESS) {
5296 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5297 hw->aq.asq_last_status);
5298 goto fail_msix_alloc;
5300 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5301 vsi->info.valid_sections = 0;
5302 vsi->seid = ctxt.seid;
5303 vsi->vsi_id = ctxt.vsi_number;
5304 vsi->sib_vsi_list.vsi = vsi;
5305 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5306 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5307 &vsi->sib_vsi_list, list);
5309 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5310 &vsi->sib_vsi_list, list);
5314 /* MAC/VLAN configuration */
5315 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5316 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5318 ret = i40e_vsi_add_mac(vsi, &filter);
5319 if (ret != I40E_SUCCESS) {
5320 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5321 goto fail_msix_alloc;
5324 /* Get VSI BW information */
5325 i40e_vsi_get_bw_config(vsi);
5328 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5330 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5336 /* Configure vlan filter on or off */
5338 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5341 struct i40e_mac_filter *f;
5343 struct i40e_mac_filter_info *mac_filter;
5344 enum rte_mac_filter_type desired_filter;
5345 int ret = I40E_SUCCESS;
5348 /* Filter to match MAC and VLAN */
5349 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5351 /* Filter to match only MAC */
5352 desired_filter = RTE_MAC_PERFECT_MATCH;
5357 mac_filter = rte_zmalloc("mac_filter_info_data",
5358 num * sizeof(*mac_filter), 0);
5359 if (mac_filter == NULL) {
5360 PMD_DRV_LOG(ERR, "failed to allocate memory");
5361 return I40E_ERR_NO_MEMORY;
5366 /* Remove all existing mac */
5367 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5368 mac_filter[i] = f->mac_info;
5369 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5371 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5372 on ? "enable" : "disable");
5378 /* Override with new filter */
5379 for (i = 0; i < num; i++) {
5380 mac_filter[i].filter_type = desired_filter;
5381 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5383 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5384 on ? "enable" : "disable");
5390 rte_free(mac_filter);
5394 /* Configure vlan stripping on or off */
5396 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5398 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5399 struct i40e_vsi_context ctxt;
5401 int ret = I40E_SUCCESS;
5403 /* Check if it has been already on or off */
5404 if (vsi->info.valid_sections &
5405 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5407 if ((vsi->info.port_vlan_flags &
5408 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5409 return 0; /* already on */
5411 if ((vsi->info.port_vlan_flags &
5412 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5413 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5414 return 0; /* already off */
5419 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5421 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5422 vsi->info.valid_sections =
5423 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5424 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5425 vsi->info.port_vlan_flags |= vlan_flags;
5426 ctxt.seid = vsi->seid;
5427 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5428 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5430 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5431 on ? "enable" : "disable");
5437 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5439 struct rte_eth_dev_data *data = dev->data;
5443 /* Apply vlan offload setting */
5444 mask = ETH_VLAN_STRIP_MASK |
5445 ETH_VLAN_FILTER_MASK |
5446 ETH_VLAN_EXTEND_MASK;
5447 ret = i40e_vlan_offload_set(dev, mask);
5449 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5453 /* Apply pvid setting */
5454 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5455 data->dev_conf.txmode.hw_vlan_insert_pvid);
5457 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5463 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5465 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5467 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5471 i40e_update_flow_control(struct i40e_hw *hw)
5473 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5474 struct i40e_link_status link_status;
5475 uint32_t rxfc = 0, txfc = 0, reg;
5479 memset(&link_status, 0, sizeof(link_status));
5480 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5481 if (ret != I40E_SUCCESS) {
5482 PMD_DRV_LOG(ERR, "Failed to get link status information");
5483 goto write_reg; /* Disable flow control */
5486 an_info = hw->phy.link_info.an_info;
5487 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5488 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5489 ret = I40E_ERR_NOT_READY;
5490 goto write_reg; /* Disable flow control */
5493 * If link auto negotiation is enabled, flow control needs to
5494 * be configured according to it
5496 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5497 case I40E_LINK_PAUSE_RXTX:
5500 hw->fc.current_mode = I40E_FC_FULL;
5502 case I40E_AQ_LINK_PAUSE_RX:
5504 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5506 case I40E_AQ_LINK_PAUSE_TX:
5508 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5511 hw->fc.current_mode = I40E_FC_NONE;
5516 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5517 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5518 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5519 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5520 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5521 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5528 i40e_pf_setup(struct i40e_pf *pf)
5530 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5531 struct i40e_filter_control_settings settings;
5532 struct i40e_vsi *vsi;
5535 /* Clear all stats counters */
5536 pf->offset_loaded = FALSE;
5537 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5538 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5539 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5540 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5542 ret = i40e_pf_get_switch_config(pf);
5543 if (ret != I40E_SUCCESS) {
5544 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5547 if (pf->flags & I40E_FLAG_FDIR) {
5548 /* make queue allocated first, let FDIR use queue pair 0*/
5549 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5550 if (ret != I40E_FDIR_QUEUE_ID) {
5552 "queue allocation fails for FDIR: ret =%d",
5554 pf->flags &= ~I40E_FLAG_FDIR;
5557 /* main VSI setup */
5558 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5560 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5561 return I40E_ERR_NOT_READY;
5565 /* Configure filter control */
5566 memset(&settings, 0, sizeof(settings));
5567 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5568 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5569 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5570 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5572 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5573 hw->func_caps.rss_table_size);
5574 return I40E_ERR_PARAM;
5576 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5577 hw->func_caps.rss_table_size);
5578 pf->hash_lut_size = hw->func_caps.rss_table_size;
5580 /* Enable ethtype and macvlan filters */
5581 settings.enable_ethtype = TRUE;
5582 settings.enable_macvlan = TRUE;
5583 ret = i40e_set_filter_control(hw, &settings);
5585 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5588 /* Update flow control according to the auto negotiation */
5589 i40e_update_flow_control(hw);
5591 return I40E_SUCCESS;
5595 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5601 * Set or clear TX Queue Disable flags,
5602 * which is required by hardware.
5604 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5605 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5607 /* Wait until the request is finished */
5608 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5609 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5610 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5611 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5612 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5618 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5619 return I40E_SUCCESS; /* already on, skip next steps */
5621 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5622 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5624 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5625 return I40E_SUCCESS; /* already off, skip next steps */
5626 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5628 /* Write the register */
5629 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5630 /* Check the result */
5631 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5632 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5633 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5635 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5636 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5639 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5640 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5644 /* Check if it is timeout */
5645 if (j >= I40E_CHK_Q_ENA_COUNT) {
5646 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5647 (on ? "enable" : "disable"), q_idx);
5648 return I40E_ERR_TIMEOUT;
5651 return I40E_SUCCESS;
5654 /* Swith on or off the tx queues */
5656 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5658 struct rte_eth_dev_data *dev_data = pf->dev_data;
5659 struct i40e_tx_queue *txq;
5660 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5664 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5665 txq = dev_data->tx_queues[i];
5666 /* Don't operate the queue if not configured or
5667 * if starting only per queue */
5668 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5671 ret = i40e_dev_tx_queue_start(dev, i);
5673 ret = i40e_dev_tx_queue_stop(dev, i);
5674 if ( ret != I40E_SUCCESS)
5678 return I40E_SUCCESS;
5682 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5687 /* Wait until the request is finished */
5688 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5689 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5690 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5691 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5692 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5697 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5698 return I40E_SUCCESS; /* Already on, skip next steps */
5699 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5701 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5702 return I40E_SUCCESS; /* Already off, skip next steps */
5703 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5706 /* Write the register */
5707 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5708 /* Check the result */
5709 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5710 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5711 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5713 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5714 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5717 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5718 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5723 /* Check if it is timeout */
5724 if (j >= I40E_CHK_Q_ENA_COUNT) {
5725 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5726 (on ? "enable" : "disable"), q_idx);
5727 return I40E_ERR_TIMEOUT;
5730 return I40E_SUCCESS;
5732 /* Switch on or off the rx queues */
5734 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5736 struct rte_eth_dev_data *dev_data = pf->dev_data;
5737 struct i40e_rx_queue *rxq;
5738 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5742 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5743 rxq = dev_data->rx_queues[i];
5744 /* Don't operate the queue if not configured or
5745 * if starting only per queue */
5746 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5749 ret = i40e_dev_rx_queue_start(dev, i);
5751 ret = i40e_dev_rx_queue_stop(dev, i);
5752 if (ret != I40E_SUCCESS)
5756 return I40E_SUCCESS;
5759 /* Switch on or off all the rx/tx queues */
5761 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5766 /* enable rx queues before enabling tx queues */
5767 ret = i40e_dev_switch_rx_queues(pf, on);
5769 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5772 ret = i40e_dev_switch_tx_queues(pf, on);
5774 /* Stop tx queues before stopping rx queues */
5775 ret = i40e_dev_switch_tx_queues(pf, on);
5777 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5780 ret = i40e_dev_switch_rx_queues(pf, on);
5786 /* Initialize VSI for TX */
5788 i40e_dev_tx_init(struct i40e_pf *pf)
5790 struct rte_eth_dev_data *data = pf->dev_data;
5792 uint32_t ret = I40E_SUCCESS;
5793 struct i40e_tx_queue *txq;
5795 for (i = 0; i < data->nb_tx_queues; i++) {
5796 txq = data->tx_queues[i];
5797 if (!txq || !txq->q_set)
5799 ret = i40e_tx_queue_init(txq);
5800 if (ret != I40E_SUCCESS)
5803 if (ret == I40E_SUCCESS)
5804 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5810 /* Initialize VSI for RX */
5812 i40e_dev_rx_init(struct i40e_pf *pf)
5814 struct rte_eth_dev_data *data = pf->dev_data;
5815 int ret = I40E_SUCCESS;
5817 struct i40e_rx_queue *rxq;
5819 i40e_pf_config_mq_rx(pf);
5820 for (i = 0; i < data->nb_rx_queues; i++) {
5821 rxq = data->rx_queues[i];
5822 if (!rxq || !rxq->q_set)
5825 ret = i40e_rx_queue_init(rxq);
5826 if (ret != I40E_SUCCESS) {
5828 "Failed to do RX queue initialization");
5832 if (ret == I40E_SUCCESS)
5833 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5840 i40e_dev_rxtx_init(struct i40e_pf *pf)
5844 err = i40e_dev_tx_init(pf);
5846 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5849 err = i40e_dev_rx_init(pf);
5851 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5859 i40e_vmdq_setup(struct rte_eth_dev *dev)
5861 struct rte_eth_conf *conf = &dev->data->dev_conf;
5862 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5863 int i, err, conf_vsis, j, loop;
5864 struct i40e_vsi *vsi;
5865 struct i40e_vmdq_info *vmdq_info;
5866 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5867 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5870 * Disable interrupt to avoid message from VF. Furthermore, it will
5871 * avoid race condition in VSI creation/destroy.
5873 i40e_pf_disable_irq0(hw);
5875 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5876 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5880 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5881 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5882 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5883 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5884 pf->max_nb_vmdq_vsi);
5888 if (pf->vmdq != NULL) {
5889 PMD_INIT_LOG(INFO, "VMDQ already configured");
5893 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5894 sizeof(*vmdq_info) * conf_vsis, 0);
5896 if (pf->vmdq == NULL) {
5897 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5901 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5903 /* Create VMDQ VSI */
5904 for (i = 0; i < conf_vsis; i++) {
5905 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5906 vmdq_conf->enable_loop_back);
5908 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5912 vmdq_info = &pf->vmdq[i];
5914 vmdq_info->vsi = vsi;
5916 pf->nb_cfg_vmdq_vsi = conf_vsis;
5918 /* Configure Vlan */
5919 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5920 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5921 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5922 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5923 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5924 vmdq_conf->pool_map[i].vlan_id, j);
5926 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5927 vmdq_conf->pool_map[i].vlan_id);
5929 PMD_INIT_LOG(ERR, "Failed to add vlan");
5937 i40e_pf_enable_irq0(hw);
5942 for (i = 0; i < conf_vsis; i++)
5943 if (pf->vmdq[i].vsi == NULL)
5946 i40e_vsi_release(pf->vmdq[i].vsi);
5950 i40e_pf_enable_irq0(hw);
5955 i40e_stat_update_32(struct i40e_hw *hw,
5963 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5967 if (new_data >= *offset)
5968 *stat = (uint64_t)(new_data - *offset);
5970 *stat = (uint64_t)((new_data +
5971 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5975 i40e_stat_update_48(struct i40e_hw *hw,
5984 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5985 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5986 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5991 if (new_data >= *offset)
5992 *stat = new_data - *offset;
5994 *stat = (uint64_t)((new_data +
5995 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5997 *stat &= I40E_48_BIT_MASK;
6002 i40e_pf_disable_irq0(struct i40e_hw *hw)
6004 /* Disable all interrupt types */
6005 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
6006 I40E_WRITE_FLUSH(hw);
6011 i40e_pf_enable_irq0(struct i40e_hw *hw)
6013 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6014 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6015 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6016 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6017 I40E_WRITE_FLUSH(hw);
6021 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6023 /* read pending request and disable first */
6024 i40e_pf_disable_irq0(hw);
6025 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6026 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6027 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6030 /* Link no queues with irq0 */
6031 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6032 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6036 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6038 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6039 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6042 uint32_t index, offset, val;
6047 * Try to find which VF trigger a reset, use absolute VF id to access
6048 * since the reg is global register.
6050 for (i = 0; i < pf->vf_num; i++) {
6051 abs_vf_id = hw->func_caps.vf_base_id + i;
6052 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6053 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6054 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6055 /* VFR event occurred */
6056 if (val & (0x1 << offset)) {
6059 /* Clear the event first */
6060 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6062 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6064 * Only notify a VF reset event occurred,
6065 * don't trigger another SW reset
6067 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6068 if (ret != I40E_SUCCESS)
6069 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6075 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6077 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6080 for (i = 0; i < pf->vf_num; i++)
6081 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6085 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6087 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6088 struct i40e_arq_event_info info;
6089 uint16_t pending, opcode;
6092 info.buf_len = I40E_AQ_BUF_SZ;
6093 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6094 if (!info.msg_buf) {
6095 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6101 ret = i40e_clean_arq_element(hw, &info, &pending);
6103 if (ret != I40E_SUCCESS) {
6105 "Failed to read msg from AdminQ, aq_err: %u",
6106 hw->aq.asq_last_status);
6109 opcode = rte_le_to_cpu_16(info.desc.opcode);
6112 case i40e_aqc_opc_send_msg_to_pf:
6113 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6114 i40e_pf_host_handle_vf_msg(dev,
6115 rte_le_to_cpu_16(info.desc.retval),
6116 rte_le_to_cpu_32(info.desc.cookie_high),
6117 rte_le_to_cpu_32(info.desc.cookie_low),
6121 case i40e_aqc_opc_get_link_status:
6122 ret = i40e_dev_link_update(dev, 0);
6124 _rte_eth_dev_callback_process(dev,
6125 RTE_ETH_EVENT_INTR_LSC, NULL);
6128 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6133 rte_free(info.msg_buf);
6137 * Interrupt handler triggered by NIC for handling
6138 * specific interrupt.
6141 * Pointer to interrupt handle.
6143 * The address of parameter (struct rte_eth_dev *) regsitered before.
6149 i40e_dev_interrupt_handler(void *param)
6151 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6152 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155 /* Disable interrupt */
6156 i40e_pf_disable_irq0(hw);
6158 /* read out interrupt causes */
6159 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6161 /* No interrupt event indicated */
6162 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6163 PMD_DRV_LOG(INFO, "No interrupt event");
6166 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6167 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6168 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6169 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6170 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6171 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6172 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6173 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6174 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6175 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6176 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6177 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6178 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6179 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6181 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6182 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6183 i40e_dev_handle_vfr_event(dev);
6185 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6186 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6187 i40e_dev_handle_aq_msg(dev);
6191 /* Enable interrupt */
6192 i40e_pf_enable_irq0(hw);
6193 rte_intr_enable(dev->intr_handle);
6197 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6198 struct i40e_macvlan_filter *filter,
6201 int ele_num, ele_buff_size;
6202 int num, actual_num, i;
6204 int ret = I40E_SUCCESS;
6205 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6206 struct i40e_aqc_add_macvlan_element_data *req_list;
6208 if (filter == NULL || total == 0)
6209 return I40E_ERR_PARAM;
6210 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6211 ele_buff_size = hw->aq.asq_buf_size;
6213 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6214 if (req_list == NULL) {
6215 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6216 return I40E_ERR_NO_MEMORY;
6221 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6222 memset(req_list, 0, ele_buff_size);
6224 for (i = 0; i < actual_num; i++) {
6225 rte_memcpy(req_list[i].mac_addr,
6226 &filter[num + i].macaddr, ETH_ADDR_LEN);
6227 req_list[i].vlan_tag =
6228 rte_cpu_to_le_16(filter[num + i].vlan_id);
6230 switch (filter[num + i].filter_type) {
6231 case RTE_MAC_PERFECT_MATCH:
6232 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6233 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6235 case RTE_MACVLAN_PERFECT_MATCH:
6236 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6238 case RTE_MAC_HASH_MATCH:
6239 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6240 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6242 case RTE_MACVLAN_HASH_MATCH:
6243 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6246 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6247 ret = I40E_ERR_PARAM;
6251 req_list[i].queue_number = 0;
6253 req_list[i].flags = rte_cpu_to_le_16(flags);
6256 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6258 if (ret != I40E_SUCCESS) {
6259 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6263 } while (num < total);
6271 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6272 struct i40e_macvlan_filter *filter,
6275 int ele_num, ele_buff_size;
6276 int num, actual_num, i;
6278 int ret = I40E_SUCCESS;
6279 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6280 struct i40e_aqc_remove_macvlan_element_data *req_list;
6282 if (filter == NULL || total == 0)
6283 return I40E_ERR_PARAM;
6285 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6286 ele_buff_size = hw->aq.asq_buf_size;
6288 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6289 if (req_list == NULL) {
6290 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6291 return I40E_ERR_NO_MEMORY;
6296 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6297 memset(req_list, 0, ele_buff_size);
6299 for (i = 0; i < actual_num; i++) {
6300 rte_memcpy(req_list[i].mac_addr,
6301 &filter[num + i].macaddr, ETH_ADDR_LEN);
6302 req_list[i].vlan_tag =
6303 rte_cpu_to_le_16(filter[num + i].vlan_id);
6305 switch (filter[num + i].filter_type) {
6306 case RTE_MAC_PERFECT_MATCH:
6307 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6308 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6310 case RTE_MACVLAN_PERFECT_MATCH:
6311 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6313 case RTE_MAC_HASH_MATCH:
6314 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6315 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6317 case RTE_MACVLAN_HASH_MATCH:
6318 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6321 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6322 ret = I40E_ERR_PARAM;
6325 req_list[i].flags = rte_cpu_to_le_16(flags);
6328 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6330 if (ret != I40E_SUCCESS) {
6331 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6335 } while (num < total);
6342 /* Find out specific MAC filter */
6343 static struct i40e_mac_filter *
6344 i40e_find_mac_filter(struct i40e_vsi *vsi,
6345 struct ether_addr *macaddr)
6347 struct i40e_mac_filter *f;
6349 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6350 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6358 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6361 uint32_t vid_idx, vid_bit;
6363 if (vlan_id > ETH_VLAN_ID_MAX)
6366 vid_idx = I40E_VFTA_IDX(vlan_id);
6367 vid_bit = I40E_VFTA_BIT(vlan_id);
6369 if (vsi->vfta[vid_idx] & vid_bit)
6376 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6377 uint16_t vlan_id, bool on)
6379 uint32_t vid_idx, vid_bit;
6381 vid_idx = I40E_VFTA_IDX(vlan_id);
6382 vid_bit = I40E_VFTA_BIT(vlan_id);
6385 vsi->vfta[vid_idx] |= vid_bit;
6387 vsi->vfta[vid_idx] &= ~vid_bit;
6391 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6392 uint16_t vlan_id, bool on)
6394 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6395 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6398 if (vlan_id > ETH_VLAN_ID_MAX)
6401 i40e_store_vlan_filter(vsi, vlan_id, on);
6403 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6406 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6409 ret = i40e_aq_add_vlan(hw, vsi->seid,
6410 &vlan_data, 1, NULL);
6411 if (ret != I40E_SUCCESS)
6412 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6414 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6415 &vlan_data, 1, NULL);
6416 if (ret != I40E_SUCCESS)
6418 "Failed to remove vlan filter");
6423 * Find all vlan options for specific mac addr,
6424 * return with actual vlan found.
6427 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6428 struct i40e_macvlan_filter *mv_f,
6429 int num, struct ether_addr *addr)
6435 * Not to use i40e_find_vlan_filter to decrease the loop time,
6436 * although the code looks complex.
6438 if (num < vsi->vlan_num)
6439 return I40E_ERR_PARAM;
6442 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6444 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6445 if (vsi->vfta[j] & (1 << k)) {
6448 "vlan number doesn't match");
6449 return I40E_ERR_PARAM;
6451 rte_memcpy(&mv_f[i].macaddr,
6452 addr, ETH_ADDR_LEN);
6454 j * I40E_UINT32_BIT_SIZE + k;
6460 return I40E_SUCCESS;
6464 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6465 struct i40e_macvlan_filter *mv_f,
6470 struct i40e_mac_filter *f;
6472 if (num < vsi->mac_num)
6473 return I40E_ERR_PARAM;
6475 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6477 PMD_DRV_LOG(ERR, "buffer number not match");
6478 return I40E_ERR_PARAM;
6480 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6482 mv_f[i].vlan_id = vlan;
6483 mv_f[i].filter_type = f->mac_info.filter_type;
6487 return I40E_SUCCESS;
6491 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6494 struct i40e_mac_filter *f;
6495 struct i40e_macvlan_filter *mv_f;
6496 int ret = I40E_SUCCESS;
6498 if (vsi == NULL || vsi->mac_num == 0)
6499 return I40E_ERR_PARAM;
6501 /* Case that no vlan is set */
6502 if (vsi->vlan_num == 0)
6505 num = vsi->mac_num * vsi->vlan_num;
6507 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6509 PMD_DRV_LOG(ERR, "failed to allocate memory");
6510 return I40E_ERR_NO_MEMORY;
6514 if (vsi->vlan_num == 0) {
6515 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6516 rte_memcpy(&mv_f[i].macaddr,
6517 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6518 mv_f[i].filter_type = f->mac_info.filter_type;
6519 mv_f[i].vlan_id = 0;
6523 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6524 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6525 vsi->vlan_num, &f->mac_info.mac_addr);
6526 if (ret != I40E_SUCCESS)
6528 for (j = i; j < i + vsi->vlan_num; j++)
6529 mv_f[j].filter_type = f->mac_info.filter_type;
6534 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6542 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6544 struct i40e_macvlan_filter *mv_f;
6546 int ret = I40E_SUCCESS;
6548 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6549 return I40E_ERR_PARAM;
6551 /* If it's already set, just return */
6552 if (i40e_find_vlan_filter(vsi,vlan))
6553 return I40E_SUCCESS;
6555 mac_num = vsi->mac_num;
6558 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6559 return I40E_ERR_PARAM;
6562 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6565 PMD_DRV_LOG(ERR, "failed to allocate memory");
6566 return I40E_ERR_NO_MEMORY;
6569 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6571 if (ret != I40E_SUCCESS)
6574 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6576 if (ret != I40E_SUCCESS)
6579 i40e_set_vlan_filter(vsi, vlan, 1);
6589 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6591 struct i40e_macvlan_filter *mv_f;
6593 int ret = I40E_SUCCESS;
6596 * Vlan 0 is the generic filter for untagged packets
6597 * and can't be removed.
6599 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6600 return I40E_ERR_PARAM;
6602 /* If can't find it, just return */
6603 if (!i40e_find_vlan_filter(vsi, vlan))
6604 return I40E_ERR_PARAM;
6606 mac_num = vsi->mac_num;
6609 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6610 return I40E_ERR_PARAM;
6613 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6616 PMD_DRV_LOG(ERR, "failed to allocate memory");
6617 return I40E_ERR_NO_MEMORY;
6620 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6622 if (ret != I40E_SUCCESS)
6625 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6627 if (ret != I40E_SUCCESS)
6630 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6631 if (vsi->vlan_num == 1) {
6632 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6633 if (ret != I40E_SUCCESS)
6636 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6637 if (ret != I40E_SUCCESS)
6641 i40e_set_vlan_filter(vsi, vlan, 0);
6651 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6653 struct i40e_mac_filter *f;
6654 struct i40e_macvlan_filter *mv_f;
6655 int i, vlan_num = 0;
6656 int ret = I40E_SUCCESS;
6658 /* If it's add and we've config it, return */
6659 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6661 return I40E_SUCCESS;
6662 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6663 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6666 * If vlan_num is 0, that's the first time to add mac,
6667 * set mask for vlan_id 0.
6669 if (vsi->vlan_num == 0) {
6670 i40e_set_vlan_filter(vsi, 0, 1);
6673 vlan_num = vsi->vlan_num;
6674 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6675 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6678 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6680 PMD_DRV_LOG(ERR, "failed to allocate memory");
6681 return I40E_ERR_NO_MEMORY;
6684 for (i = 0; i < vlan_num; i++) {
6685 mv_f[i].filter_type = mac_filter->filter_type;
6686 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6690 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6691 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6692 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6693 &mac_filter->mac_addr);
6694 if (ret != I40E_SUCCESS)
6698 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6699 if (ret != I40E_SUCCESS)
6702 /* Add the mac addr into mac list */
6703 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6705 PMD_DRV_LOG(ERR, "failed to allocate memory");
6706 ret = I40E_ERR_NO_MEMORY;
6709 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6711 f->mac_info.filter_type = mac_filter->filter_type;
6712 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6723 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6725 struct i40e_mac_filter *f;
6726 struct i40e_macvlan_filter *mv_f;
6728 enum rte_mac_filter_type filter_type;
6729 int ret = I40E_SUCCESS;
6731 /* Can't find it, return an error */
6732 f = i40e_find_mac_filter(vsi, addr);
6734 return I40E_ERR_PARAM;
6736 vlan_num = vsi->vlan_num;
6737 filter_type = f->mac_info.filter_type;
6738 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6739 filter_type == RTE_MACVLAN_HASH_MATCH) {
6740 if (vlan_num == 0) {
6741 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6742 return I40E_ERR_PARAM;
6744 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6745 filter_type == RTE_MAC_HASH_MATCH)
6748 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6750 PMD_DRV_LOG(ERR, "failed to allocate memory");
6751 return I40E_ERR_NO_MEMORY;
6754 for (i = 0; i < vlan_num; i++) {
6755 mv_f[i].filter_type = filter_type;
6756 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6759 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6760 filter_type == RTE_MACVLAN_HASH_MATCH) {
6761 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6762 if (ret != I40E_SUCCESS)
6766 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6767 if (ret != I40E_SUCCESS)
6770 /* Remove the mac addr into mac list */
6771 TAILQ_REMOVE(&vsi->mac_list, f, next);
6781 /* Configure hash enable flags for RSS */
6783 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6791 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6792 if (flags & (1ULL << i))
6793 hena |= adapter->pctypes_tbl[i];
6799 /* Parse the hash enable flags */
6801 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6803 uint64_t rss_hf = 0;
6809 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6810 if (flags & adapter->pctypes_tbl[i])
6811 rss_hf |= (1ULL << i);
6818 i40e_pf_disable_rss(struct i40e_pf *pf)
6820 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6822 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6823 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6824 I40E_WRITE_FLUSH(hw);
6828 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6830 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6831 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6832 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
6833 I40E_VFQF_HKEY_MAX_INDEX :
6834 I40E_PFQF_HKEY_MAX_INDEX;
6837 if (!key || key_len == 0) {
6838 PMD_DRV_LOG(DEBUG, "No key to be configured");
6840 } else if (key_len != (key_idx + 1) *
6842 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6846 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6847 struct i40e_aqc_get_set_rss_key_data *key_dw =
6848 (struct i40e_aqc_get_set_rss_key_data *)key;
6850 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6852 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6854 uint32_t *hash_key = (uint32_t *)key;
6857 if (vsi->type == I40E_VSI_SRIOV) {
6858 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
6861 I40E_VFQF_HKEY1(i, vsi->user_param),
6865 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6866 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
6869 I40E_WRITE_FLUSH(hw);
6876 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6878 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6879 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6883 if (!key || !key_len)
6886 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6887 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6888 (struct i40e_aqc_get_set_rss_key_data *)key);
6890 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6894 uint32_t *key_dw = (uint32_t *)key;
6897 if (vsi->type == I40E_VSI_SRIOV) {
6898 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
6899 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
6900 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6902 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
6905 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
6906 reg = I40E_PFQF_HKEY(i);
6907 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6909 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6917 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6919 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6923 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6924 rss_conf->rss_key_len);
6928 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6929 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6930 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6931 I40E_WRITE_FLUSH(hw);
6937 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6938 struct rte_eth_rss_conf *rss_conf)
6940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6941 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6942 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6945 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6946 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6948 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6949 if (rss_hf != 0) /* Enable RSS */
6951 return 0; /* Nothing to do */
6954 if (rss_hf == 0) /* Disable RSS */
6957 return i40e_hw_rss_hash_set(pf, rss_conf);
6961 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6962 struct rte_eth_rss_conf *rss_conf)
6964 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6965 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6968 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6969 &rss_conf->rss_key_len);
6971 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6972 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6973 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6979 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6981 switch (filter_type) {
6982 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6983 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6985 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6986 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6988 case RTE_TUNNEL_FILTER_IMAC_TENID:
6989 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6991 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6992 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6994 case ETH_TUNNEL_FILTER_IMAC:
6995 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6997 case ETH_TUNNEL_FILTER_OIP:
6998 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7000 case ETH_TUNNEL_FILTER_IIP:
7001 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7004 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7011 /* Convert tunnel filter structure */
7013 i40e_tunnel_filter_convert(
7014 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7015 struct i40e_tunnel_filter *tunnel_filter)
7017 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7018 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7019 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7020 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7021 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7022 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7023 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7024 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7025 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7027 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7028 tunnel_filter->input.flags = cld_filter->element.flags;
7029 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7030 tunnel_filter->queue = cld_filter->element.queue_number;
7031 rte_memcpy(tunnel_filter->input.general_fields,
7032 cld_filter->general_fields,
7033 sizeof(cld_filter->general_fields));
7038 /* Check if there exists the tunnel filter */
7039 struct i40e_tunnel_filter *
7040 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7041 const struct i40e_tunnel_filter_input *input)
7045 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7049 return tunnel_rule->hash_map[ret];
7052 /* Add a tunnel filter into the SW list */
7054 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7055 struct i40e_tunnel_filter *tunnel_filter)
7057 struct i40e_tunnel_rule *rule = &pf->tunnel;
7060 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7063 "Failed to insert tunnel filter to hash table %d!",
7067 rule->hash_map[ret] = tunnel_filter;
7069 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7074 /* Delete a tunnel filter from the SW list */
7076 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7077 struct i40e_tunnel_filter_input *input)
7079 struct i40e_tunnel_rule *rule = &pf->tunnel;
7080 struct i40e_tunnel_filter *tunnel_filter;
7083 ret = rte_hash_del_key(rule->hash_table, input);
7086 "Failed to delete tunnel filter to hash table %d!",
7090 tunnel_filter = rule->hash_map[ret];
7091 rule->hash_map[ret] = NULL;
7093 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7094 rte_free(tunnel_filter);
7100 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7101 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7105 uint32_t ipv4_addr, ipv4_addr_le;
7106 uint8_t i, tun_type = 0;
7107 /* internal varialbe to convert ipv6 byte order */
7108 uint32_t convert_ipv6[4];
7110 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7111 struct i40e_vsi *vsi = pf->main_vsi;
7112 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7113 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7114 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7115 struct i40e_tunnel_filter *tunnel, *node;
7116 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7118 cld_filter = rte_zmalloc("tunnel_filter",
7119 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7122 if (NULL == cld_filter) {
7123 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7126 pfilter = cld_filter;
7128 ether_addr_copy(&tunnel_filter->outer_mac,
7129 (struct ether_addr *)&pfilter->element.outer_mac);
7130 ether_addr_copy(&tunnel_filter->inner_mac,
7131 (struct ether_addr *)&pfilter->element.inner_mac);
7133 pfilter->element.inner_vlan =
7134 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7135 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7136 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7137 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7138 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7139 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7141 sizeof(pfilter->element.ipaddr.v4.data));
7143 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7144 for (i = 0; i < 4; i++) {
7146 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7148 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7150 sizeof(pfilter->element.ipaddr.v6.data));
7153 /* check tunneled type */
7154 switch (tunnel_filter->tunnel_type) {
7155 case RTE_TUNNEL_TYPE_VXLAN:
7156 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7158 case RTE_TUNNEL_TYPE_NVGRE:
7159 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7161 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7162 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7165 /* Other tunnel types is not supported. */
7166 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7167 rte_free(cld_filter);
7171 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7172 &pfilter->element.flags);
7174 rte_free(cld_filter);
7178 pfilter->element.flags |= rte_cpu_to_le_16(
7179 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7180 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7181 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7182 pfilter->element.queue_number =
7183 rte_cpu_to_le_16(tunnel_filter->queue_id);
7185 /* Check if there is the filter in SW list */
7186 memset(&check_filter, 0, sizeof(check_filter));
7187 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7188 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7190 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7194 if (!add && !node) {
7195 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7200 ret = i40e_aq_add_cloud_filters(hw,
7201 vsi->seid, &cld_filter->element, 1);
7203 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7206 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7207 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7208 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7210 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7211 &cld_filter->element, 1);
7213 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7216 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7219 rte_free(cld_filter);
7223 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7224 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7225 #define I40E_TR_GENEVE_KEY_MASK 0x8
7226 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7227 #define I40E_TR_GRE_KEY_MASK 0x400
7228 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7229 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7232 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7234 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7235 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7236 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7237 enum i40e_status_code status = I40E_SUCCESS;
7239 memset(&filter_replace, 0,
7240 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7241 memset(&filter_replace_buf, 0,
7242 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7244 /* create L1 filter */
7245 filter_replace.old_filter_type =
7246 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7247 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7248 filter_replace.tr_bit = 0;
7250 /* Prepare the buffer, 3 entries */
7251 filter_replace_buf.data[0] =
7252 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7253 filter_replace_buf.data[0] |=
7254 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7255 filter_replace_buf.data[2] = 0xFF;
7256 filter_replace_buf.data[3] = 0xFF;
7257 filter_replace_buf.data[4] =
7258 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7259 filter_replace_buf.data[4] |=
7260 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7261 filter_replace_buf.data[7] = 0xF0;
7262 filter_replace_buf.data[8]
7263 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7264 filter_replace_buf.data[8] |=
7265 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7266 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7267 I40E_TR_GENEVE_KEY_MASK |
7268 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7269 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7270 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7271 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7273 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7274 &filter_replace_buf);
7279 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7281 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7282 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7283 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7284 enum i40e_status_code status = I40E_SUCCESS;
7287 memset(&filter_replace, 0,
7288 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7289 memset(&filter_replace_buf, 0,
7290 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7291 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7292 I40E_AQC_MIRROR_CLOUD_FILTER;
7293 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7294 filter_replace.new_filter_type =
7295 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7296 /* Prepare the buffer, 2 entries */
7297 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7298 filter_replace_buf.data[0] |=
7299 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7300 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7301 filter_replace_buf.data[4] |=
7302 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7303 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7304 &filter_replace_buf);
7309 memset(&filter_replace, 0,
7310 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7311 memset(&filter_replace_buf, 0,
7312 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7314 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7315 I40E_AQC_MIRROR_CLOUD_FILTER;
7316 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7317 filter_replace.new_filter_type =
7318 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7319 /* Prepare the buffer, 2 entries */
7320 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7321 filter_replace_buf.data[0] |=
7322 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7323 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7324 filter_replace_buf.data[4] |=
7325 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7327 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7328 &filter_replace_buf);
7332 static enum i40e_status_code
7333 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7335 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7336 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7337 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7338 enum i40e_status_code status = I40E_SUCCESS;
7341 memset(&filter_replace, 0,
7342 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7343 memset(&filter_replace_buf, 0,
7344 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7345 /* create L1 filter */
7346 filter_replace.old_filter_type =
7347 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7348 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7349 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7350 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7351 /* Prepare the buffer, 2 entries */
7352 filter_replace_buf.data[0] =
7353 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7354 filter_replace_buf.data[0] |=
7355 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7356 filter_replace_buf.data[2] = 0xFF;
7357 filter_replace_buf.data[3] = 0xFF;
7358 filter_replace_buf.data[4] =
7359 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7360 filter_replace_buf.data[4] |=
7361 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7362 filter_replace_buf.data[6] = 0xFF;
7363 filter_replace_buf.data[7] = 0xFF;
7364 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7365 &filter_replace_buf);
7370 memset(&filter_replace, 0,
7371 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7372 memset(&filter_replace_buf, 0,
7373 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7374 /* create L1 filter */
7375 filter_replace.old_filter_type =
7376 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7377 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7378 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7379 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7380 /* Prepare the buffer, 2 entries */
7381 filter_replace_buf.data[0] =
7382 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7383 filter_replace_buf.data[0] |=
7384 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7385 filter_replace_buf.data[2] = 0xFF;
7386 filter_replace_buf.data[3] = 0xFF;
7387 filter_replace_buf.data[4] =
7388 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7389 filter_replace_buf.data[4] |=
7390 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7391 filter_replace_buf.data[6] = 0xFF;
7392 filter_replace_buf.data[7] = 0xFF;
7394 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7395 &filter_replace_buf);
7400 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7402 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7403 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7404 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7405 enum i40e_status_code status = I40E_SUCCESS;
7408 memset(&filter_replace, 0,
7409 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7410 memset(&filter_replace_buf, 0,
7411 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7412 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7413 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7414 filter_replace.new_filter_type =
7415 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7416 /* Prepare the buffer, 2 entries */
7417 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7418 filter_replace_buf.data[0] |=
7419 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7420 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7421 filter_replace_buf.data[4] |=
7422 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7423 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7424 &filter_replace_buf);
7429 memset(&filter_replace, 0,
7430 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7431 memset(&filter_replace_buf, 0,
7432 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7433 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7434 filter_replace.old_filter_type =
7435 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7436 filter_replace.new_filter_type =
7437 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7438 /* Prepare the buffer, 2 entries */
7439 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7440 filter_replace_buf.data[0] |=
7441 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7442 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7443 filter_replace_buf.data[4] |=
7444 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7446 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7447 &filter_replace_buf);
7452 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7453 struct i40e_tunnel_filter_conf *tunnel_filter,
7457 uint32_t ipv4_addr, ipv4_addr_le;
7458 uint8_t i, tun_type = 0;
7459 /* internal variable to convert ipv6 byte order */
7460 uint32_t convert_ipv6[4];
7462 struct i40e_pf_vf *vf = NULL;
7463 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7464 struct i40e_vsi *vsi;
7465 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7466 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7467 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7468 struct i40e_tunnel_filter *tunnel, *node;
7469 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7471 bool big_buffer = 0;
7473 cld_filter = rte_zmalloc("tunnel_filter",
7474 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7477 if (cld_filter == NULL) {
7478 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7481 pfilter = cld_filter;
7483 ether_addr_copy(&tunnel_filter->outer_mac,
7484 (struct ether_addr *)&pfilter->element.outer_mac);
7485 ether_addr_copy(&tunnel_filter->inner_mac,
7486 (struct ether_addr *)&pfilter->element.inner_mac);
7488 pfilter->element.inner_vlan =
7489 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7490 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7491 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7492 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7493 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7494 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7496 sizeof(pfilter->element.ipaddr.v4.data));
7498 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7499 for (i = 0; i < 4; i++) {
7501 rte_cpu_to_le_32(rte_be_to_cpu_32(
7502 tunnel_filter->ip_addr.ipv6_addr[i]));
7504 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7506 sizeof(pfilter->element.ipaddr.v6.data));
7509 /* check tunneled type */
7510 switch (tunnel_filter->tunnel_type) {
7511 case I40E_TUNNEL_TYPE_VXLAN:
7512 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7514 case I40E_TUNNEL_TYPE_NVGRE:
7515 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7517 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7518 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7520 case I40E_TUNNEL_TYPE_MPLSoUDP:
7521 if (!pf->mpls_replace_flag) {
7522 i40e_replace_mpls_l1_filter(pf);
7523 i40e_replace_mpls_cloud_filter(pf);
7524 pf->mpls_replace_flag = 1;
7526 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7527 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7529 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7530 (teid_le & 0xF) << 12;
7531 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7534 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7536 case I40E_TUNNEL_TYPE_MPLSoGRE:
7537 if (!pf->mpls_replace_flag) {
7538 i40e_replace_mpls_l1_filter(pf);
7539 i40e_replace_mpls_cloud_filter(pf);
7540 pf->mpls_replace_flag = 1;
7542 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7543 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7545 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7546 (teid_le & 0xF) << 12;
7547 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7550 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7552 case I40E_TUNNEL_TYPE_GTPC:
7553 if (!pf->gtp_replace_flag) {
7554 i40e_replace_gtp_l1_filter(pf);
7555 i40e_replace_gtp_cloud_filter(pf);
7556 pf->gtp_replace_flag = 1;
7558 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7559 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7560 (teid_le >> 16) & 0xFFFF;
7561 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7563 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7567 case I40E_TUNNEL_TYPE_GTPU:
7568 if (!pf->gtp_replace_flag) {
7569 i40e_replace_gtp_l1_filter(pf);
7570 i40e_replace_gtp_cloud_filter(pf);
7571 pf->gtp_replace_flag = 1;
7573 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7574 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7575 (teid_le >> 16) & 0xFFFF;
7576 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7578 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7582 case I40E_TUNNEL_TYPE_QINQ:
7583 if (!pf->qinq_replace_flag) {
7584 ret = i40e_cloud_filter_qinq_create(pf);
7587 "QinQ tunnel filter already created.");
7588 pf->qinq_replace_flag = 1;
7590 /* Add in the General fields the values of
7591 * the Outer and Inner VLAN
7592 * Big Buffer should be set, see changes in
7593 * i40e_aq_add_cloud_filters
7595 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7596 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7600 /* Other tunnel types is not supported. */
7601 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7602 rte_free(cld_filter);
7606 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7607 pfilter->element.flags =
7608 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7609 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7610 pfilter->element.flags =
7611 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7612 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7613 pfilter->element.flags =
7614 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7615 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7616 pfilter->element.flags =
7617 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7618 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7619 pfilter->element.flags |=
7620 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7622 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7623 &pfilter->element.flags);
7625 rte_free(cld_filter);
7630 pfilter->element.flags |= rte_cpu_to_le_16(
7631 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7632 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7633 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7634 pfilter->element.queue_number =
7635 rte_cpu_to_le_16(tunnel_filter->queue_id);
7637 if (!tunnel_filter->is_to_vf)
7640 if (tunnel_filter->vf_id >= pf->vf_num) {
7641 PMD_DRV_LOG(ERR, "Invalid argument.");
7644 vf = &pf->vfs[tunnel_filter->vf_id];
7648 /* Check if there is the filter in SW list */
7649 memset(&check_filter, 0, sizeof(check_filter));
7650 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7651 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7652 check_filter.vf_id = tunnel_filter->vf_id;
7653 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7655 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7659 if (!add && !node) {
7660 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7666 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7667 vsi->seid, cld_filter, 1);
7669 ret = i40e_aq_add_cloud_filters(hw,
7670 vsi->seid, &cld_filter->element, 1);
7672 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7675 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7676 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7677 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7680 ret = i40e_aq_remove_cloud_filters_big_buffer(
7681 hw, vsi->seid, cld_filter, 1);
7683 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7684 &cld_filter->element, 1);
7686 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7689 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7692 rte_free(cld_filter);
7697 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7701 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7702 if (pf->vxlan_ports[i] == port)
7710 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7714 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7716 idx = i40e_get_vxlan_port_idx(pf, port);
7718 /* Check if port already exists */
7720 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7724 /* Now check if there is space to add the new port */
7725 idx = i40e_get_vxlan_port_idx(pf, 0);
7728 "Maximum number of UDP ports reached, not adding port %d",
7733 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7736 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7740 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7743 /* New port: add it and mark its index in the bitmap */
7744 pf->vxlan_ports[idx] = port;
7745 pf->vxlan_bitmap |= (1 << idx);
7747 if (!(pf->flags & I40E_FLAG_VXLAN))
7748 pf->flags |= I40E_FLAG_VXLAN;
7754 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7757 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7759 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7760 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7764 idx = i40e_get_vxlan_port_idx(pf, port);
7767 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7771 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7772 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7776 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7779 pf->vxlan_ports[idx] = 0;
7780 pf->vxlan_bitmap &= ~(1 << idx);
7782 if (!pf->vxlan_bitmap)
7783 pf->flags &= ~I40E_FLAG_VXLAN;
7788 /* Add UDP tunneling port */
7790 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7791 struct rte_eth_udp_tunnel *udp_tunnel)
7794 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7796 if (udp_tunnel == NULL)
7799 switch (udp_tunnel->prot_type) {
7800 case RTE_TUNNEL_TYPE_VXLAN:
7801 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7804 case RTE_TUNNEL_TYPE_GENEVE:
7805 case RTE_TUNNEL_TYPE_TEREDO:
7806 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7811 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7819 /* Remove UDP tunneling port */
7821 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7822 struct rte_eth_udp_tunnel *udp_tunnel)
7825 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7827 if (udp_tunnel == NULL)
7830 switch (udp_tunnel->prot_type) {
7831 case RTE_TUNNEL_TYPE_VXLAN:
7832 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7834 case RTE_TUNNEL_TYPE_GENEVE:
7835 case RTE_TUNNEL_TYPE_TEREDO:
7836 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7840 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7848 /* Calculate the maximum number of contiguous PF queues that are configured */
7850 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7852 struct rte_eth_dev_data *data = pf->dev_data;
7854 struct i40e_rx_queue *rxq;
7857 for (i = 0; i < pf->lan_nb_qps; i++) {
7858 rxq = data->rx_queues[i];
7859 if (rxq && rxq->q_set)
7870 i40e_pf_config_rss(struct i40e_pf *pf)
7872 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7873 struct rte_eth_rss_conf rss_conf;
7874 uint32_t i, lut = 0;
7878 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7879 * It's necessary to calculate the actual PF queues that are configured.
7881 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7882 num = i40e_pf_calc_configured_queues_num(pf);
7884 num = pf->dev_data->nb_rx_queues;
7886 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7887 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7891 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7895 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7898 lut = (lut << 8) | (j & ((0x1 <<
7899 hw->func_caps.rss_table_entry_width) - 1));
7901 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7904 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7905 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7906 i40e_pf_disable_rss(pf);
7909 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7910 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7911 /* Random default keys */
7912 static uint32_t rss_key_default[] = {0x6b793944,
7913 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7914 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7915 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7917 rss_conf.rss_key = (uint8_t *)rss_key_default;
7918 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7922 return i40e_hw_rss_hash_set(pf, &rss_conf);
7926 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7927 struct rte_eth_tunnel_filter_conf *filter)
7929 if (pf == NULL || filter == NULL) {
7930 PMD_DRV_LOG(ERR, "Invalid parameter");
7934 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7935 PMD_DRV_LOG(ERR, "Invalid queue ID");
7939 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7940 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7944 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7945 (is_zero_ether_addr(&filter->outer_mac))) {
7946 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7950 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7951 (is_zero_ether_addr(&filter->inner_mac))) {
7952 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7959 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7960 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7962 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7967 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7968 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7971 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7972 } else if (len == 4) {
7973 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7975 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7980 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7987 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7988 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7994 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8001 switch (cfg->cfg_type) {
8002 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8003 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8006 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8014 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8015 enum rte_filter_op filter_op,
8018 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8019 int ret = I40E_ERR_PARAM;
8021 switch (filter_op) {
8022 case RTE_ETH_FILTER_SET:
8023 ret = i40e_dev_global_config_set(hw,
8024 (struct rte_eth_global_cfg *)arg);
8027 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8035 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8036 enum rte_filter_op filter_op,
8039 struct rte_eth_tunnel_filter_conf *filter;
8040 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8041 int ret = I40E_SUCCESS;
8043 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8045 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8046 return I40E_ERR_PARAM;
8048 switch (filter_op) {
8049 case RTE_ETH_FILTER_NOP:
8050 if (!(pf->flags & I40E_FLAG_VXLAN))
8051 ret = I40E_NOT_SUPPORTED;
8053 case RTE_ETH_FILTER_ADD:
8054 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8056 case RTE_ETH_FILTER_DELETE:
8057 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8060 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8061 ret = I40E_ERR_PARAM;
8069 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8072 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8075 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8076 ret = i40e_pf_config_rss(pf);
8078 i40e_pf_disable_rss(pf);
8083 /* Get the symmetric hash enable configurations per port */
8085 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8087 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8089 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8092 /* Set the symmetric hash enable configurations per port */
8094 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8096 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8099 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8101 "Symmetric hash has already been enabled");
8104 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8106 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8108 "Symmetric hash has already been disabled");
8111 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8113 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8114 I40E_WRITE_FLUSH(hw);
8118 * Get global configurations of hash function type and symmetric hash enable
8119 * per flow type (pctype). Note that global configuration means it affects all
8120 * the ports on the same NIC.
8123 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8124 struct rte_eth_hash_global_conf *g_cfg)
8126 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8130 memset(g_cfg, 0, sizeof(*g_cfg));
8131 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8132 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8133 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8135 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8136 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8137 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8140 * As i40e supports less than 64 flow types, only first 64 bits need to
8143 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8144 g_cfg->valid_bit_mask[i] = 0ULL;
8145 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8148 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8150 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8151 if (!adapter->pctypes_tbl[i])
8153 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8154 j < I40E_FILTER_PCTYPE_MAX; j++) {
8155 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8156 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8157 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8158 g_cfg->sym_hash_enable_mask[0] |=
8169 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8170 const struct rte_eth_hash_global_conf *g_cfg)
8173 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8175 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8176 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8177 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8178 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8184 * As i40e supports less than 64 flow types, only first 64 bits need to
8187 mask0 = g_cfg->valid_bit_mask[0];
8188 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8190 /* Check if any unsupported flow type configured */
8191 if ((mask0 | i40e_mask) ^ i40e_mask)
8194 if (g_cfg->valid_bit_mask[i])
8202 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8208 * Set global configurations of hash function type and symmetric hash enable
8209 * per flow type (pctype). Note any modifying global configuration will affect
8210 * all the ports on the same NIC.
8213 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8214 struct rte_eth_hash_global_conf *g_cfg)
8216 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8220 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8222 /* Check the input parameters */
8223 ret = i40e_hash_global_config_check(adapter, g_cfg);
8228 * As i40e supports less than 64 flow types, only first 64 bits need to
8231 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8232 if (mask0 & (1UL << i)) {
8233 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8234 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8236 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8237 j < I40E_FILTER_PCTYPE_MAX; j++) {
8238 if (adapter->pctypes_tbl[i] & (1ULL << j))
8239 i40e_write_rx_ctl(hw,
8246 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8247 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8249 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8251 "Hash function already set to Toeplitz");
8254 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8255 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8257 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8259 "Hash function already set to Simple XOR");
8262 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8264 /* Use the default, and keep it as it is */
8267 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8270 I40E_WRITE_FLUSH(hw);
8276 * Valid input sets for hash and flow director filters per PCTYPE
8279 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8280 enum rte_filter_type filter)
8284 static const uint64_t valid_hash_inset_table[] = {
8285 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8286 I40E_INSET_DMAC | I40E_INSET_SMAC |
8287 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8288 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8289 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8290 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8291 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8292 I40E_INSET_FLEX_PAYLOAD,
8293 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8294 I40E_INSET_DMAC | I40E_INSET_SMAC |
8295 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8296 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8297 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8298 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8299 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8300 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8301 I40E_INSET_FLEX_PAYLOAD,
8302 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8303 I40E_INSET_DMAC | I40E_INSET_SMAC |
8304 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8305 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8306 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8307 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8308 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8309 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8310 I40E_INSET_FLEX_PAYLOAD,
8311 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8312 I40E_INSET_DMAC | I40E_INSET_SMAC |
8313 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8314 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8315 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8316 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8317 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8318 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8319 I40E_INSET_FLEX_PAYLOAD,
8320 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8321 I40E_INSET_DMAC | I40E_INSET_SMAC |
8322 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8323 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8324 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8325 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8326 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8327 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8328 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8329 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8330 I40E_INSET_DMAC | I40E_INSET_SMAC |
8331 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8332 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8333 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8334 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8335 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8336 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8337 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8338 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8339 I40E_INSET_DMAC | I40E_INSET_SMAC |
8340 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8341 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8342 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8343 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8344 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8345 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8346 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8347 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8348 I40E_INSET_DMAC | I40E_INSET_SMAC |
8349 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8350 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8351 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8352 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8353 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8354 I40E_INSET_FLEX_PAYLOAD,
8355 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8356 I40E_INSET_DMAC | I40E_INSET_SMAC |
8357 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8358 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8359 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8360 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8361 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8362 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8363 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8364 I40E_INSET_DMAC | I40E_INSET_SMAC |
8365 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8366 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8367 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8368 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8369 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8370 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8371 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8372 I40E_INSET_DMAC | I40E_INSET_SMAC |
8373 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8374 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8375 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8376 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8377 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8378 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8379 I40E_INSET_FLEX_PAYLOAD,
8380 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8381 I40E_INSET_DMAC | I40E_INSET_SMAC |
8382 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8383 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8384 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8385 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8386 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8387 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8388 I40E_INSET_FLEX_PAYLOAD,
8389 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8390 I40E_INSET_DMAC | I40E_INSET_SMAC |
8391 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8392 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8393 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8394 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8395 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8396 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8397 I40E_INSET_FLEX_PAYLOAD,
8398 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8399 I40E_INSET_DMAC | I40E_INSET_SMAC |
8400 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8401 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8402 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8403 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8404 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8405 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8406 I40E_INSET_FLEX_PAYLOAD,
8407 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8408 I40E_INSET_DMAC | I40E_INSET_SMAC |
8409 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8410 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8411 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8412 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8413 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8414 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8415 I40E_INSET_FLEX_PAYLOAD,
8416 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8417 I40E_INSET_DMAC | I40E_INSET_SMAC |
8418 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8419 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8420 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8421 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8422 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8423 I40E_INSET_FLEX_PAYLOAD,
8424 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8425 I40E_INSET_DMAC | I40E_INSET_SMAC |
8426 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8427 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8428 I40E_INSET_FLEX_PAYLOAD,
8432 * Flow director supports only fields defined in
8433 * union rte_eth_fdir_flow.
8435 static const uint64_t valid_fdir_inset_table[] = {
8436 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8437 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8438 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8439 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8440 I40E_INSET_IPV4_TTL,
8441 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8442 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8443 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8444 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8445 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8446 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8447 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8448 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8449 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8450 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8451 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8452 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8453 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8454 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8455 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8456 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8457 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8458 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8459 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8460 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8461 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8462 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8463 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8464 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8465 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8466 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8467 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8468 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8469 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8470 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8472 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8473 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8474 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8475 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8476 I40E_INSET_IPV4_TTL,
8477 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8478 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8479 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8480 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8481 I40E_INSET_IPV6_HOP_LIMIT,
8482 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8483 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8484 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8485 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8486 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8487 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8488 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8489 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8490 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8491 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8492 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8493 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8494 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8495 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8496 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8497 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8498 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8499 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8500 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8501 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8502 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8503 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8504 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8505 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8506 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8507 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8508 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8509 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8510 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8511 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8513 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8514 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8515 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8516 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8517 I40E_INSET_IPV6_HOP_LIMIT,
8518 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8519 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8520 I40E_INSET_LAST_ETHER_TYPE,
8523 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8525 if (filter == RTE_ETH_FILTER_HASH)
8526 valid = valid_hash_inset_table[pctype];
8528 valid = valid_fdir_inset_table[pctype];
8534 * Validate if the input set is allowed for a specific PCTYPE
8537 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8538 enum rte_filter_type filter, uint64_t inset)
8542 valid = i40e_get_valid_input_set(pctype, filter);
8543 if (inset & (~valid))
8549 /* default input set fields combination per pctype */
8551 i40e_get_default_input_set(uint16_t pctype)
8553 static const uint64_t default_inset_table[] = {
8554 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8555 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8556 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8557 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8558 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8559 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8560 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8561 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8562 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8563 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8564 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8565 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8566 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8567 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8568 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8569 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8570 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8571 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8572 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8573 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8575 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8576 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8577 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8578 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8579 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8580 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8581 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8582 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8583 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8584 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8585 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8586 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8587 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8588 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8589 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8590 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8591 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8592 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8593 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8594 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8595 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8596 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8598 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8599 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8600 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8601 I40E_INSET_LAST_ETHER_TYPE,
8604 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8607 return default_inset_table[pctype];
8611 * Parse the input set from index to logical bit masks
8614 i40e_parse_input_set(uint64_t *inset,
8615 enum i40e_filter_pctype pctype,
8616 enum rte_eth_input_set_field *field,
8622 static const struct {
8623 enum rte_eth_input_set_field field;
8625 } inset_convert_table[] = {
8626 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8627 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8628 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8629 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8630 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8631 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8632 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8633 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8634 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8635 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8636 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8637 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8638 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8639 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8640 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8641 I40E_INSET_IPV6_NEXT_HDR},
8642 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8643 I40E_INSET_IPV6_HOP_LIMIT},
8644 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8645 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8646 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8647 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8648 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8649 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8650 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8651 I40E_INSET_SCTP_VT},
8652 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8653 I40E_INSET_TUNNEL_DMAC},
8654 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8655 I40E_INSET_VLAN_TUNNEL},
8656 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8657 I40E_INSET_TUNNEL_ID},
8658 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8659 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8660 I40E_INSET_FLEX_PAYLOAD_W1},
8661 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8662 I40E_INSET_FLEX_PAYLOAD_W2},
8663 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8664 I40E_INSET_FLEX_PAYLOAD_W3},
8665 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8666 I40E_INSET_FLEX_PAYLOAD_W4},
8667 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8668 I40E_INSET_FLEX_PAYLOAD_W5},
8669 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8670 I40E_INSET_FLEX_PAYLOAD_W6},
8671 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8672 I40E_INSET_FLEX_PAYLOAD_W7},
8673 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8674 I40E_INSET_FLEX_PAYLOAD_W8},
8677 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8680 /* Only one item allowed for default or all */
8682 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8683 *inset = i40e_get_default_input_set(pctype);
8685 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8686 *inset = I40E_INSET_NONE;
8691 for (i = 0, *inset = 0; i < size; i++) {
8692 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8693 if (field[i] == inset_convert_table[j].field) {
8694 *inset |= inset_convert_table[j].inset;
8699 /* It contains unsupported input set, return immediately */
8700 if (j == RTE_DIM(inset_convert_table))
8708 * Translate the input set from bit masks to register aware bit masks
8712 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8722 static const struct inset_map inset_map_common[] = {
8723 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8724 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8725 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8726 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8727 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8728 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8729 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8730 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8731 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8732 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8733 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8734 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8735 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8736 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8737 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8738 {I40E_INSET_TUNNEL_DMAC,
8739 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8740 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8741 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8742 {I40E_INSET_TUNNEL_SRC_PORT,
8743 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8744 {I40E_INSET_TUNNEL_DST_PORT,
8745 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8746 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8747 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8748 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8749 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8750 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8751 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8752 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8753 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8754 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8757 /* some different registers map in x722*/
8758 static const struct inset_map inset_map_diff_x722[] = {
8759 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8760 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8761 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8762 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8765 static const struct inset_map inset_map_diff_not_x722[] = {
8766 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8767 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8768 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8769 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8775 /* Translate input set to register aware inset */
8776 if (type == I40E_MAC_X722) {
8777 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8778 if (input & inset_map_diff_x722[i].inset)
8779 val |= inset_map_diff_x722[i].inset_reg;
8782 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8783 if (input & inset_map_diff_not_x722[i].inset)
8784 val |= inset_map_diff_not_x722[i].inset_reg;
8788 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8789 if (input & inset_map_common[i].inset)
8790 val |= inset_map_common[i].inset_reg;
8797 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8800 uint64_t inset_need_mask = inset;
8802 static const struct {
8805 } inset_mask_map[] = {
8806 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8807 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8808 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8809 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8810 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8811 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8812 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8813 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8816 if (!inset || !mask || !nb_elem)
8819 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8820 /* Clear the inset bit, if no MASK is required,
8821 * for example proto + ttl
8823 if ((inset & inset_mask_map[i].inset) ==
8824 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8825 inset_need_mask &= ~inset_mask_map[i].inset;
8826 if (!inset_need_mask)
8829 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8830 if ((inset_need_mask & inset_mask_map[i].inset) ==
8831 inset_mask_map[i].inset) {
8832 if (idx >= nb_elem) {
8833 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8836 mask[idx] = inset_mask_map[i].mask;
8845 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8847 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8849 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8851 i40e_write_rx_ctl(hw, addr, val);
8852 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8853 (uint32_t)i40e_read_rx_ctl(hw, addr));
8857 i40e_filter_input_set_init(struct i40e_pf *pf)
8859 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8860 enum i40e_filter_pctype pctype;
8861 uint64_t input_set, inset_reg;
8862 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8866 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8867 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8868 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8870 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8873 input_set = i40e_get_default_input_set(pctype);
8875 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8876 I40E_INSET_MASK_NUM_REG);
8879 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8882 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8883 (uint32_t)(inset_reg & UINT32_MAX));
8884 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8885 (uint32_t)((inset_reg >>
8886 I40E_32_BIT_WIDTH) & UINT32_MAX));
8887 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8888 (uint32_t)(inset_reg & UINT32_MAX));
8889 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8890 (uint32_t)((inset_reg >>
8891 I40E_32_BIT_WIDTH) & UINT32_MAX));
8893 for (i = 0; i < num; i++) {
8894 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8896 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8899 /*clear unused mask registers of the pctype */
8900 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8901 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8903 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8906 I40E_WRITE_FLUSH(hw);
8908 /* store the default input set */
8909 pf->hash_input_set[pctype] = input_set;
8910 pf->fdir.input_set[pctype] = input_set;
8915 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8916 struct rte_eth_input_set_conf *conf)
8918 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8919 enum i40e_filter_pctype pctype;
8920 uint64_t input_set, inset_reg = 0;
8921 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8925 PMD_DRV_LOG(ERR, "Invalid pointer");
8928 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8929 conf->op != RTE_ETH_INPUT_SET_ADD) {
8930 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8934 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8935 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8936 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8940 if (hw->mac.type == I40E_MAC_X722) {
8941 /* get translated pctype value in fd pctype register */
8942 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8943 I40E_GLQF_FD_PCTYPES((int)pctype));
8946 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8949 PMD_DRV_LOG(ERR, "Failed to parse input set");
8953 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8954 /* get inset value in register */
8955 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8956 inset_reg <<= I40E_32_BIT_WIDTH;
8957 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8958 input_set |= pf->hash_input_set[pctype];
8960 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8961 I40E_INSET_MASK_NUM_REG);
8965 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8967 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8968 (uint32_t)(inset_reg & UINT32_MAX));
8969 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8970 (uint32_t)((inset_reg >>
8971 I40E_32_BIT_WIDTH) & UINT32_MAX));
8973 for (i = 0; i < num; i++)
8974 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8976 /*clear unused mask registers of the pctype */
8977 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8978 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8980 I40E_WRITE_FLUSH(hw);
8982 pf->hash_input_set[pctype] = input_set;
8987 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8988 struct rte_eth_input_set_conf *conf)
8990 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8991 enum i40e_filter_pctype pctype;
8992 uint64_t input_set, inset_reg = 0;
8993 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8997 PMD_DRV_LOG(ERR, "Invalid pointer");
9000 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9001 conf->op != RTE_ETH_INPUT_SET_ADD) {
9002 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9006 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9008 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9009 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9013 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9016 PMD_DRV_LOG(ERR, "Failed to parse input set");
9020 /* get inset value in register */
9021 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9022 inset_reg <<= I40E_32_BIT_WIDTH;
9023 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9025 /* Can not change the inset reg for flex payload for fdir,
9026 * it is done by writing I40E_PRTQF_FD_FLXINSET
9027 * in i40e_set_flex_mask_on_pctype.
9029 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9030 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9032 input_set |= pf->fdir.input_set[pctype];
9033 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9034 I40E_INSET_MASK_NUM_REG);
9038 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9040 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9041 (uint32_t)(inset_reg & UINT32_MAX));
9042 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9043 (uint32_t)((inset_reg >>
9044 I40E_32_BIT_WIDTH) & UINT32_MAX));
9046 for (i = 0; i < num; i++)
9047 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9049 /*clear unused mask registers of the pctype */
9050 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9051 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9053 I40E_WRITE_FLUSH(hw);
9055 pf->fdir.input_set[pctype] = input_set;
9060 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9065 PMD_DRV_LOG(ERR, "Invalid pointer");
9069 switch (info->info_type) {
9070 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9071 i40e_get_symmetric_hash_enable_per_port(hw,
9072 &(info->info.enable));
9074 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9075 ret = i40e_get_hash_filter_global_config(hw,
9076 &(info->info.global_conf));
9079 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9089 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9094 PMD_DRV_LOG(ERR, "Invalid pointer");
9098 switch (info->info_type) {
9099 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9100 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9102 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9103 ret = i40e_set_hash_filter_global_config(hw,
9104 &(info->info.global_conf));
9106 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9107 ret = i40e_hash_filter_inset_select(hw,
9108 &(info->info.input_set_conf));
9112 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9121 /* Operations for hash function */
9123 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9124 enum rte_filter_op filter_op,
9127 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9130 switch (filter_op) {
9131 case RTE_ETH_FILTER_NOP:
9133 case RTE_ETH_FILTER_GET:
9134 ret = i40e_hash_filter_get(hw,
9135 (struct rte_eth_hash_filter_info *)arg);
9137 case RTE_ETH_FILTER_SET:
9138 ret = i40e_hash_filter_set(hw,
9139 (struct rte_eth_hash_filter_info *)arg);
9142 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9151 /* Convert ethertype filter structure */
9153 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9154 struct i40e_ethertype_filter *filter)
9156 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9157 filter->input.ether_type = input->ether_type;
9158 filter->flags = input->flags;
9159 filter->queue = input->queue;
9164 /* Check if there exists the ehtertype filter */
9165 struct i40e_ethertype_filter *
9166 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9167 const struct i40e_ethertype_filter_input *input)
9171 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9175 return ethertype_rule->hash_map[ret];
9178 /* Add ethertype filter in SW list */
9180 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9181 struct i40e_ethertype_filter *filter)
9183 struct i40e_ethertype_rule *rule = &pf->ethertype;
9186 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9189 "Failed to insert ethertype filter"
9190 " to hash table %d!",
9194 rule->hash_map[ret] = filter;
9196 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9201 /* Delete ethertype filter in SW list */
9203 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9204 struct i40e_ethertype_filter_input *input)
9206 struct i40e_ethertype_rule *rule = &pf->ethertype;
9207 struct i40e_ethertype_filter *filter;
9210 ret = rte_hash_del_key(rule->hash_table, input);
9213 "Failed to delete ethertype filter"
9214 " to hash table %d!",
9218 filter = rule->hash_map[ret];
9219 rule->hash_map[ret] = NULL;
9221 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9228 * Configure ethertype filter, which can director packet by filtering
9229 * with mac address and ether_type or only ether_type
9232 i40e_ethertype_filter_set(struct i40e_pf *pf,
9233 struct rte_eth_ethertype_filter *filter,
9236 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9237 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9238 struct i40e_ethertype_filter *ethertype_filter, *node;
9239 struct i40e_ethertype_filter check_filter;
9240 struct i40e_control_filter_stats stats;
9244 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9245 PMD_DRV_LOG(ERR, "Invalid queue ID");
9248 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9249 filter->ether_type == ETHER_TYPE_IPv6) {
9251 "unsupported ether_type(0x%04x) in control packet filter.",
9252 filter->ether_type);
9255 if (filter->ether_type == ETHER_TYPE_VLAN)
9256 PMD_DRV_LOG(WARNING,
9257 "filter vlan ether_type in first tag is not supported.");
9259 /* Check if there is the filter in SW list */
9260 memset(&check_filter, 0, sizeof(check_filter));
9261 i40e_ethertype_filter_convert(filter, &check_filter);
9262 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9263 &check_filter.input);
9265 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9269 if (!add && !node) {
9270 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9274 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9275 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9276 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9277 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9278 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9280 memset(&stats, 0, sizeof(stats));
9281 ret = i40e_aq_add_rem_control_packet_filter(hw,
9282 filter->mac_addr.addr_bytes,
9283 filter->ether_type, flags,
9285 filter->queue, add, &stats, NULL);
9288 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9289 ret, stats.mac_etype_used, stats.etype_used,
9290 stats.mac_etype_free, stats.etype_free);
9294 /* Add or delete a filter in SW list */
9296 ethertype_filter = rte_zmalloc("ethertype_filter",
9297 sizeof(*ethertype_filter), 0);
9298 rte_memcpy(ethertype_filter, &check_filter,
9299 sizeof(check_filter));
9300 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9302 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9309 * Handle operations for ethertype filter.
9312 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9313 enum rte_filter_op filter_op,
9316 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9319 if (filter_op == RTE_ETH_FILTER_NOP)
9323 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9328 switch (filter_op) {
9329 case RTE_ETH_FILTER_ADD:
9330 ret = i40e_ethertype_filter_set(pf,
9331 (struct rte_eth_ethertype_filter *)arg,
9334 case RTE_ETH_FILTER_DELETE:
9335 ret = i40e_ethertype_filter_set(pf,
9336 (struct rte_eth_ethertype_filter *)arg,
9340 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9348 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9349 enum rte_filter_type filter_type,
9350 enum rte_filter_op filter_op,
9358 switch (filter_type) {
9359 case RTE_ETH_FILTER_NONE:
9360 /* For global configuration */
9361 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9363 case RTE_ETH_FILTER_HASH:
9364 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9366 case RTE_ETH_FILTER_MACVLAN:
9367 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9369 case RTE_ETH_FILTER_ETHERTYPE:
9370 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9372 case RTE_ETH_FILTER_TUNNEL:
9373 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9375 case RTE_ETH_FILTER_FDIR:
9376 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9378 case RTE_ETH_FILTER_GENERIC:
9379 if (filter_op != RTE_ETH_FILTER_GET)
9381 *(const void **)arg = &i40e_flow_ops;
9384 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9394 * Check and enable Extended Tag.
9395 * Enabling Extended Tag is important for 40G performance.
9398 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9400 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9404 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9407 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9411 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9412 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9417 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9420 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9424 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9425 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9428 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9429 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9432 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9439 * As some registers wouldn't be reset unless a global hardware reset,
9440 * hardware initialization is needed to put those registers into an
9441 * expected initial state.
9444 i40e_hw_init(struct rte_eth_dev *dev)
9446 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9448 i40e_enable_extended_tag(dev);
9450 /* clear the PF Queue Filter control register */
9451 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9453 /* Disable symmetric hash per port */
9454 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9458 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9459 * however this function will return only one highest pctype index,
9460 * which is not quite correct. This is known problem of i40e driver
9461 * and needs to be fixed later.
9463 enum i40e_filter_pctype
9464 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9467 uint64_t pctype_mask;
9469 if (flow_type < I40E_FLOW_TYPE_MAX) {
9470 pctype_mask = adapter->pctypes_tbl[flow_type];
9471 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9472 if (pctype_mask & (1ULL << i))
9473 return (enum i40e_filter_pctype)i;
9476 return I40E_FILTER_PCTYPE_INVALID;
9480 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9481 enum i40e_filter_pctype pctype)
9484 uint64_t pctype_mask = 1ULL << pctype;
9486 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9488 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9492 return RTE_ETH_FLOW_UNKNOWN;
9496 * On X710, performance number is far from the expectation on recent firmware
9497 * versions; on XL710, performance number is also far from the expectation on
9498 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9499 * mode is enabled and port MAC address is equal to the packet destination MAC
9500 * address. The fix for this issue may not be integrated in the following
9501 * firmware version. So the workaround in software driver is needed. It needs
9502 * to modify the initial values of 3 internal only registers for both X710 and
9503 * XL710. Note that the values for X710 or XL710 could be different, and the
9504 * workaround can be removed when it is fixed in firmware in the future.
9507 /* For both X710 and XL710 */
9508 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9509 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
9510 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9512 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9513 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9516 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9517 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9520 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9522 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9523 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9526 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9528 enum i40e_status_code status;
9529 struct i40e_aq_get_phy_abilities_resp phy_ab;
9533 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9537 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9540 rte_delay_us(100000);
9542 status = i40e_aq_get_phy_capabilities(hw, false,
9543 true, &phy_ab, NULL);
9551 i40e_configure_registers(struct i40e_hw *hw)
9557 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9558 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9559 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9565 for (i = 0; i < RTE_DIM(reg_table); i++) {
9566 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9567 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9569 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9570 else /* For X710/XL710/XXV710 */
9571 if (hw->aq.fw_maj_ver < 6)
9573 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9576 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9579 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9580 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9582 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9583 else /* For X710/XL710/XXV710 */
9585 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9588 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9589 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9590 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9592 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9595 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9598 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9601 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9605 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9606 reg_table[i].addr, reg);
9607 if (reg == reg_table[i].val)
9610 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9611 reg_table[i].val, NULL);
9614 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9615 reg_table[i].val, reg_table[i].addr);
9618 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9619 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9623 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9624 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9625 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9626 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9628 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9633 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9634 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9638 /* Configure for double VLAN RX stripping */
9639 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9640 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9641 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9642 ret = i40e_aq_debug_write_register(hw,
9643 I40E_VSI_TSR(vsi->vsi_id),
9646 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9648 return I40E_ERR_CONFIG;
9652 /* Configure for double VLAN TX insertion */
9653 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9654 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9655 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9656 ret = i40e_aq_debug_write_register(hw,
9657 I40E_VSI_L2TAGSTXVALID(
9658 vsi->vsi_id), reg, NULL);
9661 "Failed to update VSI_L2TAGSTXVALID[%d]",
9663 return I40E_ERR_CONFIG;
9671 * i40e_aq_add_mirror_rule
9672 * @hw: pointer to the hardware structure
9673 * @seid: VEB seid to add mirror rule to
9674 * @dst_id: destination vsi seid
9675 * @entries: Buffer which contains the entities to be mirrored
9676 * @count: number of entities contained in the buffer
9677 * @rule_id:the rule_id of the rule to be added
9679 * Add a mirror rule for a given veb.
9682 static enum i40e_status_code
9683 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9684 uint16_t seid, uint16_t dst_id,
9685 uint16_t rule_type, uint16_t *entries,
9686 uint16_t count, uint16_t *rule_id)
9688 struct i40e_aq_desc desc;
9689 struct i40e_aqc_add_delete_mirror_rule cmd;
9690 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9691 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9694 enum i40e_status_code status;
9696 i40e_fill_default_direct_cmd_desc(&desc,
9697 i40e_aqc_opc_add_mirror_rule);
9698 memset(&cmd, 0, sizeof(cmd));
9700 buff_len = sizeof(uint16_t) * count;
9701 desc.datalen = rte_cpu_to_le_16(buff_len);
9703 desc.flags |= rte_cpu_to_le_16(
9704 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9705 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9706 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9707 cmd.num_entries = rte_cpu_to_le_16(count);
9708 cmd.seid = rte_cpu_to_le_16(seid);
9709 cmd.destination = rte_cpu_to_le_16(dst_id);
9711 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9712 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9714 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9715 hw->aq.asq_last_status, resp->rule_id,
9716 resp->mirror_rules_used, resp->mirror_rules_free);
9717 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9723 * i40e_aq_del_mirror_rule
9724 * @hw: pointer to the hardware structure
9725 * @seid: VEB seid to add mirror rule to
9726 * @entries: Buffer which contains the entities to be mirrored
9727 * @count: number of entities contained in the buffer
9728 * @rule_id:the rule_id of the rule to be delete
9730 * Delete a mirror rule for a given veb.
9733 static enum i40e_status_code
9734 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9735 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9736 uint16_t count, uint16_t rule_id)
9738 struct i40e_aq_desc desc;
9739 struct i40e_aqc_add_delete_mirror_rule cmd;
9740 uint16_t buff_len = 0;
9741 enum i40e_status_code status;
9744 i40e_fill_default_direct_cmd_desc(&desc,
9745 i40e_aqc_opc_delete_mirror_rule);
9746 memset(&cmd, 0, sizeof(cmd));
9747 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9748 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9750 cmd.num_entries = count;
9751 buff_len = sizeof(uint16_t) * count;
9752 desc.datalen = rte_cpu_to_le_16(buff_len);
9753 buff = (void *)entries;
9755 /* rule id is filled in destination field for deleting mirror rule */
9756 cmd.destination = rte_cpu_to_le_16(rule_id);
9758 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9759 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9760 cmd.seid = rte_cpu_to_le_16(seid);
9762 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9763 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9769 * i40e_mirror_rule_set
9770 * @dev: pointer to the hardware structure
9771 * @mirror_conf: mirror rule info
9772 * @sw_id: mirror rule's sw_id
9773 * @on: enable/disable
9775 * set a mirror rule.
9779 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9780 struct rte_eth_mirror_conf *mirror_conf,
9781 uint8_t sw_id, uint8_t on)
9783 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9784 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9785 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9786 struct i40e_mirror_rule *parent = NULL;
9787 uint16_t seid, dst_seid, rule_id;
9791 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9793 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9795 "mirror rule can not be configured without veb or vfs.");
9798 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9799 PMD_DRV_LOG(ERR, "mirror table is full.");
9802 if (mirror_conf->dst_pool > pf->vf_num) {
9803 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9804 mirror_conf->dst_pool);
9808 seid = pf->main_vsi->veb->seid;
9810 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9811 if (sw_id <= it->index) {
9817 if (mirr_rule && sw_id == mirr_rule->index) {
9819 PMD_DRV_LOG(ERR, "mirror rule exists.");
9822 ret = i40e_aq_del_mirror_rule(hw, seid,
9823 mirr_rule->rule_type,
9825 mirr_rule->num_entries, mirr_rule->id);
9828 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9829 ret, hw->aq.asq_last_status);
9832 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9833 rte_free(mirr_rule);
9834 pf->nb_mirror_rule--;
9838 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9842 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9843 sizeof(struct i40e_mirror_rule) , 0);
9845 PMD_DRV_LOG(ERR, "failed to allocate memory");
9846 return I40E_ERR_NO_MEMORY;
9848 switch (mirror_conf->rule_type) {
9849 case ETH_MIRROR_VLAN:
9850 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9851 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9852 mirr_rule->entries[j] =
9853 mirror_conf->vlan.vlan_id[i];
9858 PMD_DRV_LOG(ERR, "vlan is not specified.");
9859 rte_free(mirr_rule);
9862 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9864 case ETH_MIRROR_VIRTUAL_POOL_UP:
9865 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9866 /* check if the specified pool bit is out of range */
9867 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9868 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9869 rte_free(mirr_rule);
9872 for (i = 0, j = 0; i < pf->vf_num; i++) {
9873 if (mirror_conf->pool_mask & (1ULL << i)) {
9874 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9878 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9879 /* add pf vsi to entries */
9880 mirr_rule->entries[j] = pf->main_vsi_seid;
9884 PMD_DRV_LOG(ERR, "pool is not specified.");
9885 rte_free(mirr_rule);
9888 /* egress and ingress in aq commands means from switch but not port */
9889 mirr_rule->rule_type =
9890 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9891 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9892 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9894 case ETH_MIRROR_UPLINK_PORT:
9895 /* egress and ingress in aq commands means from switch but not port*/
9896 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9898 case ETH_MIRROR_DOWNLINK_PORT:
9899 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9902 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9903 mirror_conf->rule_type);
9904 rte_free(mirr_rule);
9908 /* If the dst_pool is equal to vf_num, consider it as PF */
9909 if (mirror_conf->dst_pool == pf->vf_num)
9910 dst_seid = pf->main_vsi_seid;
9912 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9914 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9915 mirr_rule->rule_type, mirr_rule->entries,
9919 "failed to add mirror rule: ret = %d, aq_err = %d.",
9920 ret, hw->aq.asq_last_status);
9921 rte_free(mirr_rule);
9925 mirr_rule->index = sw_id;
9926 mirr_rule->num_entries = j;
9927 mirr_rule->id = rule_id;
9928 mirr_rule->dst_vsi_seid = dst_seid;
9931 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9933 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9935 pf->nb_mirror_rule++;
9940 * i40e_mirror_rule_reset
9941 * @dev: pointer to the device
9942 * @sw_id: mirror rule's sw_id
9944 * reset a mirror rule.
9948 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9950 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9951 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9952 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9956 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9958 seid = pf->main_vsi->veb->seid;
9960 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9961 if (sw_id == it->index) {
9967 ret = i40e_aq_del_mirror_rule(hw, seid,
9968 mirr_rule->rule_type,
9970 mirr_rule->num_entries, mirr_rule->id);
9973 "failed to remove mirror rule: status = %d, aq_err = %d.",
9974 ret, hw->aq.asq_last_status);
9977 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9978 rte_free(mirr_rule);
9979 pf->nb_mirror_rule--;
9981 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9988 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9990 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9991 uint64_t systim_cycles;
9993 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9994 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9997 return systim_cycles;
10001 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10003 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10004 uint64_t rx_tstamp;
10006 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10007 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10014 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10016 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10017 uint64_t tx_tstamp;
10019 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10020 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10027 i40e_start_timecounters(struct rte_eth_dev *dev)
10029 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10030 struct i40e_adapter *adapter =
10031 (struct i40e_adapter *)dev->data->dev_private;
10032 struct rte_eth_link link;
10033 uint32_t tsync_inc_l;
10034 uint32_t tsync_inc_h;
10036 /* Get current link speed. */
10037 memset(&link, 0, sizeof(link));
10038 i40e_dev_link_update(dev, 1);
10039 rte_i40e_dev_atomic_read_link_status(dev, &link);
10041 switch (link.link_speed) {
10042 case ETH_SPEED_NUM_40G:
10043 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10044 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10046 case ETH_SPEED_NUM_10G:
10047 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10048 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10050 case ETH_SPEED_NUM_1G:
10051 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10052 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10059 /* Set the timesync increment value. */
10060 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10061 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10063 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10064 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10065 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10067 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10068 adapter->systime_tc.cc_shift = 0;
10069 adapter->systime_tc.nsec_mask = 0;
10071 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10072 adapter->rx_tstamp_tc.cc_shift = 0;
10073 adapter->rx_tstamp_tc.nsec_mask = 0;
10075 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10076 adapter->tx_tstamp_tc.cc_shift = 0;
10077 adapter->tx_tstamp_tc.nsec_mask = 0;
10081 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10083 struct i40e_adapter *adapter =
10084 (struct i40e_adapter *)dev->data->dev_private;
10086 adapter->systime_tc.nsec += delta;
10087 adapter->rx_tstamp_tc.nsec += delta;
10088 adapter->tx_tstamp_tc.nsec += delta;
10094 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10097 struct i40e_adapter *adapter =
10098 (struct i40e_adapter *)dev->data->dev_private;
10100 ns = rte_timespec_to_ns(ts);
10102 /* Set the timecounters to a new value. */
10103 adapter->systime_tc.nsec = ns;
10104 adapter->rx_tstamp_tc.nsec = ns;
10105 adapter->tx_tstamp_tc.nsec = ns;
10111 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10113 uint64_t ns, systime_cycles;
10114 struct i40e_adapter *adapter =
10115 (struct i40e_adapter *)dev->data->dev_private;
10117 systime_cycles = i40e_read_systime_cyclecounter(dev);
10118 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10119 *ts = rte_ns_to_timespec(ns);
10125 i40e_timesync_enable(struct rte_eth_dev *dev)
10127 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10128 uint32_t tsync_ctl_l;
10129 uint32_t tsync_ctl_h;
10131 /* Stop the timesync system time. */
10132 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10133 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10134 /* Reset the timesync system time value. */
10135 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10136 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10138 i40e_start_timecounters(dev);
10140 /* Clear timesync registers. */
10141 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10142 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10143 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10144 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10145 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10146 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10148 /* Enable timestamping of PTP packets. */
10149 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10150 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10152 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10153 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10154 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10156 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10157 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10163 i40e_timesync_disable(struct rte_eth_dev *dev)
10165 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10166 uint32_t tsync_ctl_l;
10167 uint32_t tsync_ctl_h;
10169 /* Disable timestamping of transmitted PTP packets. */
10170 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10171 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10173 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10174 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10176 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10177 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10179 /* Reset the timesync increment value. */
10180 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10181 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10187 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10188 struct timespec *timestamp, uint32_t flags)
10190 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10191 struct i40e_adapter *adapter =
10192 (struct i40e_adapter *)dev->data->dev_private;
10194 uint32_t sync_status;
10195 uint32_t index = flags & 0x03;
10196 uint64_t rx_tstamp_cycles;
10199 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10200 if ((sync_status & (1 << index)) == 0)
10203 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10204 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10205 *timestamp = rte_ns_to_timespec(ns);
10211 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10212 struct timespec *timestamp)
10214 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10215 struct i40e_adapter *adapter =
10216 (struct i40e_adapter *)dev->data->dev_private;
10218 uint32_t sync_status;
10219 uint64_t tx_tstamp_cycles;
10222 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10223 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10226 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10227 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10228 *timestamp = rte_ns_to_timespec(ns);
10234 * i40e_parse_dcb_configure - parse dcb configure from user
10235 * @dev: the device being configured
10236 * @dcb_cfg: pointer of the result of parse
10237 * @*tc_map: bit map of enabled traffic classes
10239 * Returns 0 on success, negative value on failure
10242 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10243 struct i40e_dcbx_config *dcb_cfg,
10246 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10247 uint8_t i, tc_bw, bw_lf;
10249 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10251 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10252 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10253 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10257 /* assume each tc has the same bw */
10258 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10259 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10260 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10261 /* to ensure the sum of tcbw is equal to 100 */
10262 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10263 for (i = 0; i < bw_lf; i++)
10264 dcb_cfg->etscfg.tcbwtable[i]++;
10266 /* assume each tc has the same Transmission Selection Algorithm */
10267 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10268 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10270 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10271 dcb_cfg->etscfg.prioritytable[i] =
10272 dcb_rx_conf->dcb_tc[i];
10274 /* FW needs one App to configure HW */
10275 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10276 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10277 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10278 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10280 if (dcb_rx_conf->nb_tcs == 0)
10281 *tc_map = 1; /* tc0 only */
10283 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10285 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10286 dcb_cfg->pfc.willing = 0;
10287 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10288 dcb_cfg->pfc.pfcenable = *tc_map;
10294 static enum i40e_status_code
10295 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10296 struct i40e_aqc_vsi_properties_data *info,
10297 uint8_t enabled_tcmap)
10299 enum i40e_status_code ret;
10300 int i, total_tc = 0;
10301 uint16_t qpnum_per_tc, bsf, qp_idx;
10302 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10303 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10304 uint16_t used_queues;
10306 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10307 if (ret != I40E_SUCCESS)
10310 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10311 if (enabled_tcmap & (1 << i))
10316 vsi->enabled_tc = enabled_tcmap;
10318 /* different VSI has different queues assigned */
10319 if (vsi->type == I40E_VSI_MAIN)
10320 used_queues = dev_data->nb_rx_queues -
10321 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10322 else if (vsi->type == I40E_VSI_VMDQ2)
10323 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10325 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10326 return I40E_ERR_NO_AVAILABLE_VSI;
10329 qpnum_per_tc = used_queues / total_tc;
10330 /* Number of queues per enabled TC */
10331 if (qpnum_per_tc == 0) {
10332 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10333 return I40E_ERR_INVALID_QP_ID;
10335 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10336 I40E_MAX_Q_PER_TC);
10337 bsf = rte_bsf32(qpnum_per_tc);
10340 * Configure TC and queue mapping parameters, for enabled TC,
10341 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10342 * default queue will serve it.
10345 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10346 if (vsi->enabled_tc & (1 << i)) {
10347 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10348 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10349 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10350 qp_idx += qpnum_per_tc;
10352 info->tc_mapping[i] = 0;
10355 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10356 if (vsi->type == I40E_VSI_SRIOV) {
10357 info->mapping_flags |=
10358 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10359 for (i = 0; i < vsi->nb_qps; i++)
10360 info->queue_mapping[i] =
10361 rte_cpu_to_le_16(vsi->base_queue + i);
10363 info->mapping_flags |=
10364 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10365 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10367 info->valid_sections |=
10368 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10370 return I40E_SUCCESS;
10374 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10375 * @veb: VEB to be configured
10376 * @tc_map: enabled TC bitmap
10378 * Returns 0 on success, negative value on failure
10380 static enum i40e_status_code
10381 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10383 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10384 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10385 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10386 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10387 enum i40e_status_code ret = I40E_SUCCESS;
10391 /* Check if enabled_tc is same as existing or new TCs */
10392 if (veb->enabled_tc == tc_map)
10395 /* configure tc bandwidth */
10396 memset(&veb_bw, 0, sizeof(veb_bw));
10397 veb_bw.tc_valid_bits = tc_map;
10398 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10399 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10400 if (tc_map & BIT_ULL(i))
10401 veb_bw.tc_bw_share_credits[i] = 1;
10403 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10407 "AQ command Config switch_comp BW allocation per TC failed = %d",
10408 hw->aq.asq_last_status);
10412 memset(&ets_query, 0, sizeof(ets_query));
10413 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10415 if (ret != I40E_SUCCESS) {
10417 "Failed to get switch_comp ETS configuration %u",
10418 hw->aq.asq_last_status);
10421 memset(&bw_query, 0, sizeof(bw_query));
10422 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10424 if (ret != I40E_SUCCESS) {
10426 "Failed to get switch_comp bandwidth configuration %u",
10427 hw->aq.asq_last_status);
10431 /* store and print out BW info */
10432 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10433 veb->bw_info.bw_max = ets_query.tc_bw_max;
10434 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10435 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10436 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10437 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10438 I40E_16_BIT_WIDTH);
10439 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10440 veb->bw_info.bw_ets_share_credits[i] =
10441 bw_query.tc_bw_share_credits[i];
10442 veb->bw_info.bw_ets_credits[i] =
10443 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10444 /* 4 bits per TC, 4th bit is reserved */
10445 veb->bw_info.bw_ets_max[i] =
10446 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10447 RTE_LEN2MASK(3, uint8_t));
10448 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10449 veb->bw_info.bw_ets_share_credits[i]);
10450 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10451 veb->bw_info.bw_ets_credits[i]);
10452 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10453 veb->bw_info.bw_ets_max[i]);
10456 veb->enabled_tc = tc_map;
10463 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10464 * @vsi: VSI to be configured
10465 * @tc_map: enabled TC bitmap
10467 * Returns 0 on success, negative value on failure
10469 static enum i40e_status_code
10470 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10472 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10473 struct i40e_vsi_context ctxt;
10474 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10475 enum i40e_status_code ret = I40E_SUCCESS;
10478 /* Check if enabled_tc is same as existing or new TCs */
10479 if (vsi->enabled_tc == tc_map)
10482 /* configure tc bandwidth */
10483 memset(&bw_data, 0, sizeof(bw_data));
10484 bw_data.tc_valid_bits = tc_map;
10485 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10486 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10487 if (tc_map & BIT_ULL(i))
10488 bw_data.tc_bw_credits[i] = 1;
10490 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10493 "AQ command Config VSI BW allocation per TC failed = %d",
10494 hw->aq.asq_last_status);
10497 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10498 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10500 /* Update Queue Pairs Mapping for currently enabled UPs */
10501 ctxt.seid = vsi->seid;
10502 ctxt.pf_num = hw->pf_id;
10504 ctxt.uplink_seid = vsi->uplink_seid;
10505 ctxt.info = vsi->info;
10507 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10511 /* Update the VSI after updating the VSI queue-mapping information */
10512 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10514 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10515 hw->aq.asq_last_status);
10518 /* update the local VSI info with updated queue map */
10519 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10520 sizeof(vsi->info.tc_mapping));
10521 rte_memcpy(&vsi->info.queue_mapping,
10522 &ctxt.info.queue_mapping,
10523 sizeof(vsi->info.queue_mapping));
10524 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10525 vsi->info.valid_sections = 0;
10527 /* query and update current VSI BW information */
10528 ret = i40e_vsi_get_bw_config(vsi);
10531 "Failed updating vsi bw info, err %s aq_err %s",
10532 i40e_stat_str(hw, ret),
10533 i40e_aq_str(hw, hw->aq.asq_last_status));
10537 vsi->enabled_tc = tc_map;
10544 * i40e_dcb_hw_configure - program the dcb setting to hw
10545 * @pf: pf the configuration is taken on
10546 * @new_cfg: new configuration
10547 * @tc_map: enabled TC bitmap
10549 * Returns 0 on success, negative value on failure
10551 static enum i40e_status_code
10552 i40e_dcb_hw_configure(struct i40e_pf *pf,
10553 struct i40e_dcbx_config *new_cfg,
10556 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10557 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10558 struct i40e_vsi *main_vsi = pf->main_vsi;
10559 struct i40e_vsi_list *vsi_list;
10560 enum i40e_status_code ret;
10564 /* Use the FW API if FW > v4.4*/
10565 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10566 (hw->aq.fw_maj_ver >= 5))) {
10568 "FW < v4.4, can not use FW LLDP API to configure DCB");
10569 return I40E_ERR_FIRMWARE_API_VERSION;
10572 /* Check if need reconfiguration */
10573 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10574 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10575 return I40E_SUCCESS;
10578 /* Copy the new config to the current config */
10579 *old_cfg = *new_cfg;
10580 old_cfg->etsrec = old_cfg->etscfg;
10581 ret = i40e_set_dcb_config(hw);
10583 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10584 i40e_stat_str(hw, ret),
10585 i40e_aq_str(hw, hw->aq.asq_last_status));
10588 /* set receive Arbiter to RR mode and ETS scheme by default */
10589 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10590 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10591 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10592 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10593 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10594 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10595 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10596 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10597 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10598 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10599 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10600 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10601 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10603 /* get local mib to check whether it is configured correctly */
10605 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10606 /* Get Local DCB Config */
10607 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10608 &hw->local_dcbx_config);
10610 /* if Veb is created, need to update TC of it at first */
10611 if (main_vsi->veb) {
10612 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10614 PMD_INIT_LOG(WARNING,
10615 "Failed configuring TC for VEB seid=%d",
10616 main_vsi->veb->seid);
10618 /* Update each VSI */
10619 i40e_vsi_config_tc(main_vsi, tc_map);
10620 if (main_vsi->veb) {
10621 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10622 /* Beside main VSI and VMDQ VSIs, only enable default
10623 * TC for other VSIs
10625 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10626 ret = i40e_vsi_config_tc(vsi_list->vsi,
10629 ret = i40e_vsi_config_tc(vsi_list->vsi,
10630 I40E_DEFAULT_TCMAP);
10632 PMD_INIT_LOG(WARNING,
10633 "Failed configuring TC for VSI seid=%d",
10634 vsi_list->vsi->seid);
10638 return I40E_SUCCESS;
10642 * i40e_dcb_init_configure - initial dcb config
10643 * @dev: device being configured
10644 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10646 * Returns 0 on success, negative value on failure
10649 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10651 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10652 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10655 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10656 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10660 /* DCB initialization:
10661 * Update DCB configuration from the Firmware and configure
10662 * LLDP MIB change event.
10664 if (sw_dcb == TRUE) {
10665 ret = i40e_init_dcb(hw);
10666 /* If lldp agent is stopped, the return value from
10667 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10668 * adminq status. Otherwise, it should return success.
10670 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10671 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10672 memset(&hw->local_dcbx_config, 0,
10673 sizeof(struct i40e_dcbx_config));
10674 /* set dcb default configuration */
10675 hw->local_dcbx_config.etscfg.willing = 0;
10676 hw->local_dcbx_config.etscfg.maxtcs = 0;
10677 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10678 hw->local_dcbx_config.etscfg.tsatable[0] =
10680 /* all UPs mapping to TC0 */
10681 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10682 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10683 hw->local_dcbx_config.etsrec =
10684 hw->local_dcbx_config.etscfg;
10685 hw->local_dcbx_config.pfc.willing = 0;
10686 hw->local_dcbx_config.pfc.pfccap =
10687 I40E_MAX_TRAFFIC_CLASS;
10688 /* FW needs one App to configure HW */
10689 hw->local_dcbx_config.numapps = 1;
10690 hw->local_dcbx_config.app[0].selector =
10691 I40E_APP_SEL_ETHTYPE;
10692 hw->local_dcbx_config.app[0].priority = 3;
10693 hw->local_dcbx_config.app[0].protocolid =
10694 I40E_APP_PROTOID_FCOE;
10695 ret = i40e_set_dcb_config(hw);
10698 "default dcb config fails. err = %d, aq_err = %d.",
10699 ret, hw->aq.asq_last_status);
10704 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10705 ret, hw->aq.asq_last_status);
10709 ret = i40e_aq_start_lldp(hw, NULL);
10710 if (ret != I40E_SUCCESS)
10711 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10713 ret = i40e_init_dcb(hw);
10715 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10717 "HW doesn't support DCBX offload.");
10722 "DCBX configuration failed, err = %d, aq_err = %d.",
10723 ret, hw->aq.asq_last_status);
10731 * i40e_dcb_setup - setup dcb related config
10732 * @dev: device being configured
10734 * Returns 0 on success, negative value on failure
10737 i40e_dcb_setup(struct rte_eth_dev *dev)
10739 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10740 struct i40e_dcbx_config dcb_cfg;
10741 uint8_t tc_map = 0;
10744 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10745 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10749 if (pf->vf_num != 0)
10750 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10752 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10754 PMD_INIT_LOG(ERR, "invalid dcb config");
10757 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10759 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10767 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10768 struct rte_eth_dcb_info *dcb_info)
10770 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10771 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10772 struct i40e_vsi *vsi = pf->main_vsi;
10773 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10774 uint16_t bsf, tc_mapping;
10777 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10778 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10780 dcb_info->nb_tcs = 1;
10781 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10782 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10783 for (i = 0; i < dcb_info->nb_tcs; i++)
10784 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10786 /* get queue mapping if vmdq is disabled */
10787 if (!pf->nb_cfg_vmdq_vsi) {
10788 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10789 if (!(vsi->enabled_tc & (1 << i)))
10791 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10792 dcb_info->tc_queue.tc_rxq[j][i].base =
10793 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10794 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10795 dcb_info->tc_queue.tc_txq[j][i].base =
10796 dcb_info->tc_queue.tc_rxq[j][i].base;
10797 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10798 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10799 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10800 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10801 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10806 /* get queue mapping if vmdq is enabled */
10808 vsi = pf->vmdq[j].vsi;
10809 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10810 if (!(vsi->enabled_tc & (1 << i)))
10812 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10813 dcb_info->tc_queue.tc_rxq[j][i].base =
10814 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10815 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10816 dcb_info->tc_queue.tc_txq[j][i].base =
10817 dcb_info->tc_queue.tc_rxq[j][i].base;
10818 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10819 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10820 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10821 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10822 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10825 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10830 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10832 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10833 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10834 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10835 uint16_t interval =
10836 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10837 uint16_t msix_intr;
10839 msix_intr = intr_handle->intr_vec[queue_id];
10840 if (msix_intr == I40E_MISC_VEC_ID)
10841 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10842 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10843 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10844 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10846 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10849 I40E_PFINT_DYN_CTLN(msix_intr -
10850 I40E_RX_VEC_START),
10851 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10852 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10853 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10855 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10857 I40E_WRITE_FLUSH(hw);
10858 rte_intr_enable(&pci_dev->intr_handle);
10864 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10866 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10867 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10868 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10869 uint16_t msix_intr;
10871 msix_intr = intr_handle->intr_vec[queue_id];
10872 if (msix_intr == I40E_MISC_VEC_ID)
10873 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10876 I40E_PFINT_DYN_CTLN(msix_intr -
10877 I40E_RX_VEC_START),
10879 I40E_WRITE_FLUSH(hw);
10884 static int i40e_get_regs(struct rte_eth_dev *dev,
10885 struct rte_dev_reg_info *regs)
10887 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10888 uint32_t *ptr_data = regs->data;
10889 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10890 const struct i40e_reg_info *reg_info;
10892 if (ptr_data == NULL) {
10893 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10894 regs->width = sizeof(uint32_t);
10898 /* The first few registers have to be read using AQ operations */
10900 while (i40e_regs_adminq[reg_idx].name) {
10901 reg_info = &i40e_regs_adminq[reg_idx++];
10902 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10904 arr_idx2 <= reg_info->count2;
10906 reg_offset = arr_idx * reg_info->stride1 +
10907 arr_idx2 * reg_info->stride2;
10908 reg_offset += reg_info->base_addr;
10909 ptr_data[reg_offset >> 2] =
10910 i40e_read_rx_ctl(hw, reg_offset);
10914 /* The remaining registers can be read using primitives */
10916 while (i40e_regs_others[reg_idx].name) {
10917 reg_info = &i40e_regs_others[reg_idx++];
10918 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10920 arr_idx2 <= reg_info->count2;
10922 reg_offset = arr_idx * reg_info->stride1 +
10923 arr_idx2 * reg_info->stride2;
10924 reg_offset += reg_info->base_addr;
10925 ptr_data[reg_offset >> 2] =
10926 I40E_READ_REG(hw, reg_offset);
10933 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10937 /* Convert word count to byte count */
10938 return hw->nvm.sr_size << 1;
10941 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10942 struct rte_dev_eeprom_info *eeprom)
10944 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10945 uint16_t *data = eeprom->data;
10946 uint16_t offset, length, cnt_words;
10949 offset = eeprom->offset >> 1;
10950 length = eeprom->length >> 1;
10951 cnt_words = length;
10953 if (offset > hw->nvm.sr_size ||
10954 offset + length > hw->nvm.sr_size) {
10955 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10959 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10961 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10962 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10963 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10970 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10971 struct ether_addr *mac_addr)
10973 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10974 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10975 struct i40e_vsi *vsi = pf->main_vsi;
10976 struct i40e_mac_filter_info mac_filter;
10977 struct i40e_mac_filter *f;
10980 if (!is_valid_assigned_ether_addr(mac_addr)) {
10981 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10985 TAILQ_FOREACH(f, &vsi->mac_list, next) {
10986 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
10991 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
10995 mac_filter = f->mac_info;
10996 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
10997 if (ret != I40E_SUCCESS) {
10998 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11001 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11002 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11003 if (ret != I40E_SUCCESS) {
11004 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11007 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11009 i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11010 mac_addr->addr_bytes, NULL);
11014 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11016 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11017 struct rte_eth_dev_data *dev_data = pf->dev_data;
11018 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11021 /* check if mtu is within the allowed range */
11022 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11025 /* mtu setting is forbidden if port is start */
11026 if (dev_data->dev_started) {
11027 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11028 dev_data->port_id);
11032 if (frame_size > ETHER_MAX_LEN)
11033 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11035 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11037 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11042 /* Restore ethertype filter */
11044 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11046 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11047 struct i40e_ethertype_filter_list
11048 *ethertype_list = &pf->ethertype.ethertype_list;
11049 struct i40e_ethertype_filter *f;
11050 struct i40e_control_filter_stats stats;
11053 TAILQ_FOREACH(f, ethertype_list, rules) {
11055 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11056 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11057 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11058 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11059 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11061 memset(&stats, 0, sizeof(stats));
11062 i40e_aq_add_rem_control_packet_filter(hw,
11063 f->input.mac_addr.addr_bytes,
11064 f->input.ether_type,
11065 flags, pf->main_vsi->seid,
11066 f->queue, 1, &stats, NULL);
11068 PMD_DRV_LOG(INFO, "Ethertype filter:"
11069 " mac_etype_used = %u, etype_used = %u,"
11070 " mac_etype_free = %u, etype_free = %u",
11071 stats.mac_etype_used, stats.etype_used,
11072 stats.mac_etype_free, stats.etype_free);
11075 /* Restore tunnel filter */
11077 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11079 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11080 struct i40e_vsi *vsi;
11081 struct i40e_pf_vf *vf;
11082 struct i40e_tunnel_filter_list
11083 *tunnel_list = &pf->tunnel.tunnel_list;
11084 struct i40e_tunnel_filter *f;
11085 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11086 bool big_buffer = 0;
11088 TAILQ_FOREACH(f, tunnel_list, rules) {
11090 vsi = pf->main_vsi;
11092 vf = &pf->vfs[f->vf_id];
11095 memset(&cld_filter, 0, sizeof(cld_filter));
11096 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11097 (struct ether_addr *)&cld_filter.element.outer_mac);
11098 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11099 (struct ether_addr *)&cld_filter.element.inner_mac);
11100 cld_filter.element.inner_vlan = f->input.inner_vlan;
11101 cld_filter.element.flags = f->input.flags;
11102 cld_filter.element.tenant_id = f->input.tenant_id;
11103 cld_filter.element.queue_number = f->queue;
11104 rte_memcpy(cld_filter.general_fields,
11105 f->input.general_fields,
11106 sizeof(f->input.general_fields));
11108 if (((f->input.flags &
11109 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11110 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11112 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11113 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11115 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11116 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11120 i40e_aq_add_cloud_filters_big_buffer(hw,
11121 vsi->seid, &cld_filter, 1);
11123 i40e_aq_add_cloud_filters(hw, vsi->seid,
11124 &cld_filter.element, 1);
11128 /* Restore rss filter */
11130 i40e_rss_filter_restore(struct i40e_pf *pf)
11132 struct i40e_rte_flow_rss_conf *conf =
11135 i40e_config_rss_filter(pf, conf, TRUE);
11139 i40e_filter_restore(struct i40e_pf *pf)
11141 i40e_ethertype_filter_restore(pf);
11142 i40e_tunnel_filter_restore(pf);
11143 i40e_fdir_filter_restore(pf);
11144 i40e_rss_filter_restore(pf);
11148 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11150 if (strcmp(dev->device->driver->name, drv->driver.name))
11157 is_i40e_supported(struct rte_eth_dev *dev)
11159 return is_device_supported(dev, &rte_i40e_pmd);
11162 struct i40e_customized_pctype*
11163 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11167 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11168 if (pf->customized_pctype[i].index == index)
11169 return &pf->customized_pctype[i];
11175 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11176 uint32_t pkg_size, uint32_t proto_num,
11177 struct rte_pmd_i40e_proto_info *proto)
11179 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11180 uint32_t pctype_num;
11181 struct rte_pmd_i40e_ptype_info *pctype;
11182 uint32_t buff_size;
11183 struct i40e_customized_pctype *new_pctype = NULL;
11185 uint8_t pctype_value;
11190 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11191 (uint8_t *)&pctype_num, sizeof(pctype_num),
11192 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11194 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11198 PMD_DRV_LOG(INFO, "No new pctype added");
11202 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11203 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11205 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11208 /* get information about new pctype list */
11209 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11210 (uint8_t *)pctype, buff_size,
11211 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11213 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11218 /* Update customized pctype. */
11219 for (i = 0; i < pctype_num; i++) {
11220 pctype_value = pctype[i].ptype_id;
11221 memset(name, 0, sizeof(name));
11222 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11223 proto_id = pctype[i].protocols[j];
11224 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11226 for (n = 0; n < proto_num; n++) {
11227 if (proto[n].proto_id != proto_id)
11229 strcat(name, proto[n].name);
11234 name[strlen(name) - 1] = '\0';
11235 if (!strcmp(name, "GTPC"))
11237 i40e_find_customized_pctype(pf,
11238 I40E_CUSTOMIZED_GTPC);
11239 else if (!strcmp(name, "GTPU_IPV4"))
11241 i40e_find_customized_pctype(pf,
11242 I40E_CUSTOMIZED_GTPU_IPV4);
11243 else if (!strcmp(name, "GTPU_IPV6"))
11245 i40e_find_customized_pctype(pf,
11246 I40E_CUSTOMIZED_GTPU_IPV6);
11247 else if (!strcmp(name, "GTPU"))
11249 i40e_find_customized_pctype(pf,
11250 I40E_CUSTOMIZED_GTPU);
11252 new_pctype->pctype = pctype_value;
11253 new_pctype->valid = true;
11262 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11263 uint32_t pkg_size, uint32_t proto_num,
11264 struct rte_pmd_i40e_proto_info *proto)
11266 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11267 uint16_t port_id = dev->data->port_id;
11268 uint32_t ptype_num;
11269 struct rte_pmd_i40e_ptype_info *ptype;
11270 uint32_t buff_size;
11272 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11277 /* get information about new ptype num */
11278 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11279 (uint8_t *)&ptype_num, sizeof(ptype_num),
11280 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11282 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11286 PMD_DRV_LOG(INFO, "No new ptype added");
11290 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11291 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11293 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11297 /* get information about new ptype list */
11298 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11299 (uint8_t *)ptype, buff_size,
11300 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11302 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11307 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11308 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11309 if (!ptype_mapping) {
11310 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11315 /* Update ptype mapping table. */
11316 for (i = 0; i < ptype_num; i++) {
11317 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11318 ptype_mapping[i].sw_ptype = 0;
11320 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11321 proto_id = ptype[i].protocols[j];
11322 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11324 for (n = 0; n < proto_num; n++) {
11325 if (proto[n].proto_id != proto_id)
11327 memset(name, 0, sizeof(name));
11328 strcpy(name, proto[n].name);
11329 if (!strncmp(name, "PPPOE", 5))
11330 ptype_mapping[i].sw_ptype |=
11331 RTE_PTYPE_L2_ETHER_PPPOE;
11332 else if (!strncmp(name, "OIPV4", 5)) {
11333 ptype_mapping[i].sw_ptype |=
11334 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11336 } else if (!strncmp(name, "IPV4", 4) &&
11338 ptype_mapping[i].sw_ptype |=
11339 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11340 else if (!strncmp(name, "IPV4FRAG", 8) &&
11342 ptype_mapping[i].sw_ptype |=
11343 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11344 ptype_mapping[i].sw_ptype |=
11345 RTE_PTYPE_INNER_L4_FRAG;
11346 } else if (!strncmp(name, "IPV4", 4) &&
11348 ptype_mapping[i].sw_ptype |=
11349 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11350 else if (!strncmp(name, "OIPV6", 5)) {
11351 ptype_mapping[i].sw_ptype |=
11352 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11354 } else if (!strncmp(name, "IPV6", 4) &&
11356 ptype_mapping[i].sw_ptype |=
11357 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11358 else if (!strncmp(name, "IPV6FRAG", 8) &&
11360 ptype_mapping[i].sw_ptype |=
11361 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11362 ptype_mapping[i].sw_ptype |=
11363 RTE_PTYPE_INNER_L4_FRAG;
11364 } else if (!strncmp(name, "IPV6", 4) &&
11366 ptype_mapping[i].sw_ptype |=
11367 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11368 else if (!strncmp(name, "UDP", 3) && !in_tunnel)
11369 ptype_mapping[i].sw_ptype |=
11371 else if (!strncmp(name, "UDP", 3) && in_tunnel)
11372 ptype_mapping[i].sw_ptype |=
11373 RTE_PTYPE_INNER_L4_UDP;
11374 else if (!strncmp(name, "TCP", 3) && !in_tunnel)
11375 ptype_mapping[i].sw_ptype |=
11377 else if (!strncmp(name, "TCP", 3) && in_tunnel)
11378 ptype_mapping[i].sw_ptype |=
11379 RTE_PTYPE_INNER_L4_TCP;
11380 else if (!strncmp(name, "SCTP", 4) &&
11382 ptype_mapping[i].sw_ptype |=
11384 else if (!strncmp(name, "SCTP", 4) && in_tunnel)
11385 ptype_mapping[i].sw_ptype |=
11386 RTE_PTYPE_INNER_L4_SCTP;
11387 else if ((!strncmp(name, "ICMP", 4) ||
11388 !strncmp(name, "ICMPV6", 6)) &&
11390 ptype_mapping[i].sw_ptype |=
11392 else if ((!strncmp(name, "ICMP", 4) ||
11393 !strncmp(name, "ICMPV6", 6)) &&
11395 ptype_mapping[i].sw_ptype |=
11396 RTE_PTYPE_INNER_L4_ICMP;
11397 else if (!strncmp(name, "GTPC", 4)) {
11398 ptype_mapping[i].sw_ptype |=
11399 RTE_PTYPE_TUNNEL_GTPC;
11401 } else if (!strncmp(name, "GTPU", 4)) {
11402 ptype_mapping[i].sw_ptype |=
11403 RTE_PTYPE_TUNNEL_GTPU;
11405 } else if (!strncmp(name, "GRENAT", 6)) {
11406 ptype_mapping[i].sw_ptype |=
11407 RTE_PTYPE_TUNNEL_GRENAT;
11409 } else if (!strncmp(name, "L2TPv2CTL", 9)) {
11410 ptype_mapping[i].sw_ptype |=
11411 RTE_PTYPE_TUNNEL_L2TP;
11420 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11423 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11425 rte_free(ptype_mapping);
11431 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11434 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11435 uint32_t proto_num;
11436 struct rte_pmd_i40e_proto_info *proto;
11437 uint32_t buff_size;
11441 /* get information about protocol number */
11442 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11443 (uint8_t *)&proto_num, sizeof(proto_num),
11444 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11446 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11450 PMD_DRV_LOG(INFO, "No new protocol added");
11454 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11455 proto = rte_zmalloc("new_proto", buff_size, 0);
11457 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11461 /* get information about protocol list */
11462 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11463 (uint8_t *)proto, buff_size,
11464 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11466 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11471 /* Check if GTP is supported. */
11472 for (i = 0; i < proto_num; i++) {
11473 if (!strncmp(proto[i].name, "GTP", 3)) {
11474 pf->gtp_support = true;
11479 /* Update customized pctype info */
11480 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11483 PMD_DRV_LOG(INFO, "No pctype is updated.");
11485 /* Update customized ptype info */
11486 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11489 PMD_DRV_LOG(INFO, "No ptype is updated.");
11494 /* Create a QinQ cloud filter
11496 * The Fortville NIC has limited resources for tunnel filters,
11497 * so we can only reuse existing filters.
11499 * In step 1 we define which Field Vector fields can be used for
11501 * As we do not have the inner tag defined as a field,
11502 * we have to define it first, by reusing one of L1 entries.
11504 * In step 2 we are replacing one of existing filter types with
11505 * a new one for QinQ.
11506 * As we reusing L1 and replacing L2, some of the default filter
11507 * types will disappear,which depends on L1 and L2 entries we reuse.
11509 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11511 * 1. Create L1 filter of outer vlan (12b) which will be in use
11512 * later when we define the cloud filter.
11513 * a. Valid_flags.replace_cloud = 0
11514 * b. Old_filter = 10 (Stag_Inner_Vlan)
11515 * c. New_filter = 0x10
11516 * d. TR bit = 0xff (optional, not used here)
11517 * e. Buffer – 2 entries:
11518 * i. Byte 0 = 8 (outer vlan FV index).
11520 * Byte 2-3 = 0x0fff
11521 * ii. Byte 0 = 37 (inner vlan FV index).
11523 * Byte 2-3 = 0x0fff
11526 * 2. Create cloud filter using two L1 filters entries: stag and
11527 * new filter(outer vlan+ inner vlan)
11528 * a. Valid_flags.replace_cloud = 1
11529 * b. Old_filter = 1 (instead of outer IP)
11530 * c. New_filter = 0x10
11531 * d. Buffer – 2 entries:
11532 * i. Byte 0 = 0x80 | 7 (valid | Stag).
11533 * Byte 1-3 = 0 (rsv)
11534 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11535 * Byte 9-11 = 0 (rsv)
11538 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11540 int ret = -ENOTSUP;
11541 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
11542 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
11543 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11546 memset(&filter_replace, 0,
11547 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11548 memset(&filter_replace_buf, 0,
11549 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11551 /* create L1 filter */
11552 filter_replace.old_filter_type =
11553 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11554 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11555 filter_replace.tr_bit = 0;
11557 /* Prepare the buffer, 2 entries */
11558 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11559 filter_replace_buf.data[0] |=
11560 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11561 /* Field Vector 12b mask */
11562 filter_replace_buf.data[2] = 0xff;
11563 filter_replace_buf.data[3] = 0x0f;
11564 filter_replace_buf.data[4] =
11565 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11566 filter_replace_buf.data[4] |=
11567 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11568 /* Field Vector 12b mask */
11569 filter_replace_buf.data[6] = 0xff;
11570 filter_replace_buf.data[7] = 0x0f;
11571 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11572 &filter_replace_buf);
11573 if (ret != I40E_SUCCESS)
11576 /* Apply the second L2 cloud filter */
11577 memset(&filter_replace, 0,
11578 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11579 memset(&filter_replace_buf, 0,
11580 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11582 /* create L2 filter, input for L2 filter will be L1 filter */
11583 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11584 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11585 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11587 /* Prepare the buffer, 2 entries */
11588 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11589 filter_replace_buf.data[0] |=
11590 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11591 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11592 filter_replace_buf.data[4] |=
11593 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11594 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11595 &filter_replace_buf);
11600 i40e_config_rss_filter(struct i40e_pf *pf,
11601 struct i40e_rte_flow_rss_conf *conf, bool add)
11603 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11604 uint32_t i, lut = 0;
11606 struct rte_eth_rss_conf rss_conf = conf->rss_conf;
11607 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
11610 if (memcmp(conf, rss_info,
11611 sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
11612 i40e_pf_disable_rss(pf);
11613 memset(rss_info, 0,
11614 sizeof(struct i40e_rte_flow_rss_conf));
11623 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
11624 * It's necessary to calculate the actual PF queues that are configured.
11626 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
11627 num = i40e_pf_calc_configured_queues_num(pf);
11629 num = pf->dev_data->nb_rx_queues;
11631 num = RTE_MIN(num, conf->num);
11632 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
11636 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
11640 /* Fill in redirection table */
11641 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
11644 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
11645 hw->func_caps.rss_table_entry_width) - 1));
11647 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
11650 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
11651 i40e_pf_disable_rss(pf);
11654 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
11655 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
11656 /* Random default keys */
11657 static uint32_t rss_key_default[] = {0x6b793944,
11658 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
11659 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
11660 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
11662 rss_conf.rss_key = (uint8_t *)rss_key_default;
11663 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
11667 return i40e_hw_rss_hash_set(pf, &rss_conf);
11669 rte_memcpy(rss_info,
11670 conf, sizeof(struct i40e_rte_flow_rss_conf));
11675 RTE_INIT(i40e_init_log);
11677 i40e_init_log(void)
11679 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11680 if (i40e_logtype_init >= 0)
11681 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11682 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11683 if (i40e_logtype_driver >= 0)
11684 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);