4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
67 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
69 #define I40E_CLEAR_PXE_WAIT_MS 200
71 /* Maximun number of capability elements */
72 #define I40E_MAX_CAP_ELE_NUM 128
74 /* Wait count and inteval */
75 #define I40E_CHK_Q_ENA_COUNT 1000
76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
78 /* Maximun number of VSI */
79 #define I40E_MAX_NUM_VSIS (384UL)
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Flow control default timer */
84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
86 /* Flow control default high water */
87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
89 /* Flow control default low water */
90 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
92 /* Flow control enable fwd bit */
93 #define I40E_PRTMAC_FWD_CTRL 0x00000001
95 /* Receive Packet Buffer size */
96 #define I40E_RXPBSIZE (968 * 1024)
99 #define I40E_KILOSHIFT 10
101 /* Receive Average Packet Size in Byte*/
102 #define I40E_PACKET_AVERAGE_SIZE 128
104 /* Mask of PF interrupt causes */
105 #define I40E_PFINT_ICR0_ENA_MASK ( \
106 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
107 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_GRST_MASK | \
109 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
110 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
112 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
113 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
114 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
115 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
117 #define I40E_FLOW_TYPES ( \
118 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
123 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
128 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
130 /* Additional timesync values. */
131 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
132 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
133 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
134 #define I40E_PRTTSYN_TSYNENA 0x80000000
135 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
136 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
138 #define I40E_MAX_PERCENT 100
139 #define I40E_DEFAULT_DCB_APP_NUM 1
140 #define I40E_DEFAULT_DCB_APP_PRIO 3
142 #define I40E_INSET_NONE 0x00000000000000000ULL
145 #define I40E_INSET_DMAC 0x0000000000000001ULL
146 #define I40E_INSET_SMAC 0x0000000000000002ULL
147 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
148 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
149 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
152 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
153 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
154 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
155 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
156 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
157 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
158 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
160 /* bit 16 ~ bit 31 */
161 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
162 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
163 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
164 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
165 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
166 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
167 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
168 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
170 /* bit 32 ~ bit 47, tunnel fields */
171 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
172 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
173 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
174 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
175 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
176 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
178 /* bit 48 ~ bit 55 */
179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
181 /* bit 56 ~ bit 63, Flex Payload */
182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
190 #define I40E_INSET_FLEX_PAYLOAD \
191 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
192 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
193 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
194 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
197 * Below are values for writing un-exposed registers suggested
200 /* Destination MAC address */
201 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
202 /* Source MAC address */
203 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
205 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
207 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
208 /* Single VLAN tag in the inner L2 header */
209 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
210 /* Source IPv4 address */
211 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
212 /* Destination IPv4 address */
213 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
214 /* IPv4 Type of Service (TOS) */
215 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
217 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
218 /* IPv4 Time to Live */
219 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
220 /* Source IPv6 address */
221 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
222 /* Destination IPv6 address */
223 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
224 /* IPv6 Traffic Class (TC) */
225 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
226 /* IPv6 Next Header */
227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
231 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
232 /* Destination L4 port */
233 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
234 /* SCTP verification tag */
235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
238 /* Source port of tunneling UDP */
239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
240 /* Destination port of tunneling UDP */
241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
242 /* UDP Tunneling ID, NVGRE/GRE key */
243 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
244 /* Last ether type */
245 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
246 /* Tunneling outer destination IPv4 address */
247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
248 /* Tunneling outer destination IPv6 address */
249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
250 /* 1st word of flex payload */
251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
252 /* 2nd word of flex payload */
253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
254 /* 3rd word of flex payload */
255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
256 /* 4th word of flex payload */
257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
258 /* 5th word of flex payload */
259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
260 /* 6th word of flex payload */
261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
262 /* 7th word of flex payload */
263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
264 /* 8th word of flex payload */
265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
266 /* all 8 words flex payload */
267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
268 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
270 #define I40E_TRANSLATE_INSET 0
271 #define I40E_TRANSLATE_REG 1
273 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
274 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
275 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
276 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
278 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
280 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
283 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
285 /* PCI offset for querying capability */
286 #define PCI_DEV_CAP_REG 0xA4
287 /* PCI offset for enabling/disabling Extended Tag */
288 #define PCI_DEV_CTRL_REG 0xA8
289 /* Bit mask of Extended Tag capability */
290 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
291 /* Bit shift of Extended Tag enable/disable */
292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
293 /* Bit mask of Extended Tag enable/disable */
294 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
298 static int i40e_dev_configure(struct rte_eth_dev *dev);
299 static int i40e_dev_start(struct rte_eth_dev *dev);
300 static void i40e_dev_stop(struct rte_eth_dev *dev);
301 static void i40e_dev_close(struct rte_eth_dev *dev);
302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
309 struct rte_eth_stats *stats);
310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
311 struct rte_eth_xstat *xstats, unsigned n);
312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
313 struct rte_eth_xstat_name *xstats_names,
315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
321 struct rte_eth_dev_info *dev_info);
322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
326 enum rte_vlan_type vlan_type,
328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
336 struct rte_eth_fc_conf *fc_conf);
337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
338 struct rte_eth_fc_conf *fc_conf);
339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
340 struct rte_eth_pfc_conf *pfc_conf);
341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
342 struct ether_addr *mac_addr,
345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
347 struct rte_eth_rss_reta_entry64 *reta_conf,
349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
350 struct rte_eth_rss_reta_entry64 *reta_conf,
353 static int i40e_get_cap(struct i40e_hw *hw);
354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
355 static int i40e_pf_setup(struct i40e_pf *pf);
356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
361 bool offset_loaded, uint64_t *offset, uint64_t *stat);
362 static void i40e_stat_update_48(struct i40e_hw *hw,
368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
369 static void i40e_dev_interrupt_handler(
370 __rte_unused struct rte_intr_handle *handle, void *param);
371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
372 uint32_t base, uint32_t num);
373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
379 static int i40e_veb_release(struct i40e_veb *veb);
380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
381 struct i40e_vsi *vsi);
382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
385 struct i40e_macvlan_filter *mv_f,
387 struct ether_addr *addr);
388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
389 struct i40e_macvlan_filter *mv_f,
392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
394 struct rte_eth_rss_conf *rss_conf);
395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
396 struct rte_eth_rss_conf *rss_conf);
397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
398 struct rte_eth_udp_tunnel *udp_tunnel);
399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
400 struct rte_eth_udp_tunnel *udp_tunnel);
401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
403 struct rte_eth_ethertype_filter *filter,
405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
406 enum rte_filter_op filter_op,
408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
409 enum rte_filter_type filter_type,
410 enum rte_filter_op filter_op,
412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
413 struct rte_eth_dcb_info *dcb_info);
414 static void i40e_configure_registers(struct i40e_hw *hw);
415 static void i40e_hw_init(struct rte_eth_dev *dev);
416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
418 struct rte_eth_mirror_conf *mirror_conf,
419 uint8_t sw_id, uint8_t on);
420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
425 struct timespec *timestamp,
427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
428 struct timespec *timestamp);
429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
434 struct timespec *timestamp);
435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
436 const struct timespec *timestamp);
438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
443 static int i40e_get_reg_length(struct rte_eth_dev *dev);
445 static int i40e_get_regs(struct rte_eth_dev *dev,
446 struct rte_dev_reg_info *regs);
448 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
450 static int i40e_get_eeprom(struct rte_eth_dev *dev,
451 struct rte_dev_eeprom_info *eeprom);
453 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
454 struct ether_addr *mac_addr);
456 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
458 static const struct rte_pci_id pci_id_i40e_map[] = {
459 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
460 #include "rte_pci_dev_ids.h"
461 { .vendor_id = 0, /* sentinel */ },
464 static const struct eth_dev_ops i40e_eth_dev_ops = {
465 .dev_configure = i40e_dev_configure,
466 .dev_start = i40e_dev_start,
467 .dev_stop = i40e_dev_stop,
468 .dev_close = i40e_dev_close,
469 .promiscuous_enable = i40e_dev_promiscuous_enable,
470 .promiscuous_disable = i40e_dev_promiscuous_disable,
471 .allmulticast_enable = i40e_dev_allmulticast_enable,
472 .allmulticast_disable = i40e_dev_allmulticast_disable,
473 .dev_set_link_up = i40e_dev_set_link_up,
474 .dev_set_link_down = i40e_dev_set_link_down,
475 .link_update = i40e_dev_link_update,
476 .stats_get = i40e_dev_stats_get,
477 .xstats_get = i40e_dev_xstats_get,
478 .xstats_get_names = i40e_dev_xstats_get_names,
479 .stats_reset = i40e_dev_stats_reset,
480 .xstats_reset = i40e_dev_stats_reset,
481 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
482 .dev_infos_get = i40e_dev_info_get,
483 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
484 .vlan_filter_set = i40e_vlan_filter_set,
485 .vlan_tpid_set = i40e_vlan_tpid_set,
486 .vlan_offload_set = i40e_vlan_offload_set,
487 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
488 .vlan_pvid_set = i40e_vlan_pvid_set,
489 .rx_queue_start = i40e_dev_rx_queue_start,
490 .rx_queue_stop = i40e_dev_rx_queue_stop,
491 .tx_queue_start = i40e_dev_tx_queue_start,
492 .tx_queue_stop = i40e_dev_tx_queue_stop,
493 .rx_queue_setup = i40e_dev_rx_queue_setup,
494 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
495 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
496 .rx_queue_release = i40e_dev_rx_queue_release,
497 .rx_queue_count = i40e_dev_rx_queue_count,
498 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
499 .tx_queue_setup = i40e_dev_tx_queue_setup,
500 .tx_queue_release = i40e_dev_tx_queue_release,
501 .dev_led_on = i40e_dev_led_on,
502 .dev_led_off = i40e_dev_led_off,
503 .flow_ctrl_get = i40e_flow_ctrl_get,
504 .flow_ctrl_set = i40e_flow_ctrl_set,
505 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
506 .mac_addr_add = i40e_macaddr_add,
507 .mac_addr_remove = i40e_macaddr_remove,
508 .reta_update = i40e_dev_rss_reta_update,
509 .reta_query = i40e_dev_rss_reta_query,
510 .rss_hash_update = i40e_dev_rss_hash_update,
511 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
512 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
513 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
514 .filter_ctrl = i40e_dev_filter_ctrl,
515 .rxq_info_get = i40e_rxq_info_get,
516 .txq_info_get = i40e_txq_info_get,
517 .mirror_rule_set = i40e_mirror_rule_set,
518 .mirror_rule_reset = i40e_mirror_rule_reset,
519 .timesync_enable = i40e_timesync_enable,
520 .timesync_disable = i40e_timesync_disable,
521 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
522 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
523 .get_dcb_info = i40e_dev_get_dcb_info,
524 .timesync_adjust_time = i40e_timesync_adjust_time,
525 .timesync_read_time = i40e_timesync_read_time,
526 .timesync_write_time = i40e_timesync_write_time,
527 .get_reg_length = i40e_get_reg_length,
528 .get_reg = i40e_get_regs,
529 .get_eeprom_length = i40e_get_eeprom_length,
530 .get_eeprom = i40e_get_eeprom,
531 .mac_addr_set = i40e_set_default_mac_addr,
532 .mtu_set = i40e_dev_mtu_set,
535 /* store statistics names and its offset in stats structure */
536 struct rte_i40e_xstats_name_off {
537 char name[RTE_ETH_XSTATS_NAME_SIZE];
541 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
542 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
543 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
544 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
545 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
546 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
547 rx_unknown_protocol)},
548 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
549 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
550 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
551 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
554 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
555 sizeof(rte_i40e_stats_strings[0]))
557 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
558 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
559 tx_dropped_link_down)},
560 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
561 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
563 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
564 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
566 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
568 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
570 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
571 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
572 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
573 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
574 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
575 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
581 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
583 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
585 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
587 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
589 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
591 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
592 mac_short_packet_dropped)},
593 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
595 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
596 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
597 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
599 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
601 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
603 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
605 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
607 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
609 {"rx_flow_director_atr_match_packets",
610 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
611 {"rx_flow_director_sb_match_packets",
612 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
613 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
615 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
617 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
619 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
623 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
624 sizeof(rte_i40e_hw_port_strings[0]))
626 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
627 {"xon_packets", offsetof(struct i40e_hw_port_stats,
629 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
633 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
634 sizeof(rte_i40e_rxq_prio_strings[0]))
636 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
637 {"xon_packets", offsetof(struct i40e_hw_port_stats,
639 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
641 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
642 priority_xon_2_xoff)},
645 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
646 sizeof(rte_i40e_txq_prio_strings[0]))
648 static struct eth_driver rte_i40e_pmd = {
650 .name = "rte_i40e_pmd",
651 .id_table = pci_id_i40e_map,
652 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
653 RTE_PCI_DRV_DETACHABLE,
655 .eth_dev_init = eth_i40e_dev_init,
656 .eth_dev_uninit = eth_i40e_dev_uninit,
657 .dev_private_size = sizeof(struct i40e_adapter),
661 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
662 struct rte_eth_link *link)
664 struct rte_eth_link *dst = link;
665 struct rte_eth_link *src = &(dev->data->dev_link);
667 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
668 *(uint64_t *)src) == 0)
675 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
676 struct rte_eth_link *link)
678 struct rte_eth_link *dst = &(dev->data->dev_link);
679 struct rte_eth_link *src = link;
681 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
682 *(uint64_t *)src) == 0)
689 * Driver initialization routine.
690 * Invoked once at EAL init time.
691 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
694 rte_i40e_pmd_init(const char *name __rte_unused,
695 const char *params __rte_unused)
697 PMD_INIT_FUNC_TRACE();
698 rte_eth_driver_register(&rte_i40e_pmd);
703 static struct rte_driver rte_i40e_driver = {
705 .init = rte_i40e_pmd_init,
708 PMD_REGISTER_DRIVER(rte_i40e_driver);
711 * Initialize registers for flexible payload, which should be set by NVM.
712 * This should be removed from code once it is fixed in NVM.
714 #ifndef I40E_GLQF_ORT
715 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
717 #ifndef I40E_GLQF_PIT
718 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
721 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
723 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
724 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
725 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
726 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
727 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
728 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
729 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
730 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
731 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
732 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
734 /* GLQF_PIT Registers */
735 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
736 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
739 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
742 * Add a ethertype filter to drop all flow control frames transmitted
746 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
748 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
749 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
750 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
751 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
754 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
755 I40E_FLOW_CONTROL_ETHERTYPE, flags,
756 pf->main_vsi_seid, 0,
759 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
760 " frames from VSIs.");
764 floating_veb_list_handler(__rte_unused const char *key,
765 const char *floating_veb_value,
769 unsigned int count = 0;
772 bool *vf_floating_veb = opaque;
774 while (isblank(*floating_veb_value))
775 floating_veb_value++;
777 /* Reset floating VEB configuration for VFs */
778 for (idx = 0; idx < I40E_MAX_VF; idx++)
779 vf_floating_veb[idx] = false;
783 while (isblank(*floating_veb_value))
784 floating_veb_value++;
785 if (*floating_veb_value == '\0')
788 idx = strtoul(floating_veb_value, &end, 10);
789 if (errno || end == NULL)
791 while (isblank(*end))
795 } else if ((*end == ';') || (*end == '\0')) {
797 if (min == I40E_MAX_VF)
799 if (max >= I40E_MAX_VF)
800 max = I40E_MAX_VF - 1;
801 for (idx = min; idx <= max; idx++) {
802 vf_floating_veb[idx] = true;
809 floating_veb_value = end + 1;
810 } while (*end != '\0');
819 config_vf_floating_veb(struct rte_devargs *devargs,
820 uint16_t floating_veb,
821 bool *vf_floating_veb)
823 struct rte_kvargs *kvlist;
825 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
829 /* All the VFs attach to the floating VEB by default
830 * when the floating VEB is enabled.
832 for (i = 0; i < I40E_MAX_VF; i++)
833 vf_floating_veb[i] = true;
838 kvlist = rte_kvargs_parse(devargs->args, NULL);
842 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
843 rte_kvargs_free(kvlist);
846 /* When the floating_veb_list parameter exists, all the VFs
847 * will attach to the legacy VEB firstly, then configure VFs
848 * to the floating VEB according to the floating_veb_list.
850 if (rte_kvargs_process(kvlist, floating_veb_list,
851 floating_veb_list_handler,
852 vf_floating_veb) < 0) {
853 rte_kvargs_free(kvlist);
856 rte_kvargs_free(kvlist);
860 i40e_check_floating_handler(__rte_unused const char *key,
862 __rte_unused void *opaque)
864 if (strcmp(value, "1"))
871 is_floating_veb_supported(struct rte_devargs *devargs)
873 struct rte_kvargs *kvlist;
874 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
879 kvlist = rte_kvargs_parse(devargs->args, NULL);
883 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
884 rte_kvargs_free(kvlist);
887 /* Floating VEB is enabled when there's key-value:
888 * enable_floating_veb=1
890 if (rte_kvargs_process(kvlist, floating_veb_key,
891 i40e_check_floating_handler, NULL) < 0) {
892 rte_kvargs_free(kvlist);
895 rte_kvargs_free(kvlist);
901 config_floating_veb(struct rte_eth_dev *dev)
903 struct rte_pci_device *pci_dev = dev->pci_dev;
904 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
905 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
907 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
909 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
910 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
911 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
912 pf->floating_veb_list);
914 pf->floating_veb = false;
919 eth_i40e_dev_init(struct rte_eth_dev *dev)
921 struct rte_pci_device *pci_dev;
922 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
923 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
924 struct i40e_vsi *vsi;
929 PMD_INIT_FUNC_TRACE();
931 dev->dev_ops = &i40e_eth_dev_ops;
932 dev->rx_pkt_burst = i40e_recv_pkts;
933 dev->tx_pkt_burst = i40e_xmit_pkts;
935 /* for secondary processes, we don't initialise any further as primary
936 * has already done this work. Only check we don't need a different
938 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
939 i40e_set_rx_function(dev);
940 i40e_set_tx_function(dev);
943 pci_dev = dev->pci_dev;
945 rte_eth_copy_pci_info(dev, pci_dev);
947 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
948 pf->adapter->eth_dev = dev;
949 pf->dev_data = dev->data;
951 hw->back = I40E_PF_TO_ADAPTER(pf);
952 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
954 PMD_INIT_LOG(ERR, "Hardware is not available, "
955 "as address is NULL");
959 hw->vendor_id = pci_dev->id.vendor_id;
960 hw->device_id = pci_dev->id.device_id;
961 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
962 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
963 hw->bus.device = pci_dev->addr.devid;
964 hw->bus.func = pci_dev->addr.function;
965 hw->adapter_stopped = 0;
967 /* Make sure all is clean before doing PF reset */
970 /* Initialize the hardware */
973 /* Reset here to make sure all is clean for each PF */
974 ret = i40e_pf_reset(hw);
976 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
980 /* Initialize the shared code (base driver) */
981 ret = i40e_init_shared_code(hw);
983 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
988 * To work around the NVM issue,initialize registers
989 * for flexible payload by software.
990 * It should be removed once issues are fixed in NVM.
992 i40e_flex_payload_reg_init(hw);
994 /* Initialize the input set for filters (hash and fd) to default value */
995 i40e_filter_input_set_init(pf);
997 /* Initialize the parameters for adminq */
998 i40e_init_adminq_parameter(hw);
999 ret = i40e_init_adminq(hw);
1000 if (ret != I40E_SUCCESS) {
1001 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1004 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1005 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1006 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1007 ((hw->nvm.version >> 12) & 0xf),
1008 ((hw->nvm.version >> 4) & 0xff),
1009 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1011 /* Need the special FW version to support floating VEB */
1012 config_floating_veb(dev);
1013 /* Clear PXE mode */
1014 i40e_clear_pxe_mode(hw);
1017 * On X710, performance number is far from the expectation on recent
1018 * firmware versions. The fix for this issue may not be integrated in
1019 * the following firmware version. So the workaround in software driver
1020 * is needed. It needs to modify the initial values of 3 internal only
1021 * registers. Note that the workaround can be removed when it is fixed
1022 * in firmware in the future.
1024 i40e_configure_registers(hw);
1026 /* Get hw capabilities */
1027 ret = i40e_get_cap(hw);
1028 if (ret != I40E_SUCCESS) {
1029 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1030 goto err_get_capabilities;
1033 /* Initialize parameters for PF */
1034 ret = i40e_pf_parameter_init(dev);
1036 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1037 goto err_parameter_init;
1040 /* Initialize the queue management */
1041 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1043 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1044 goto err_qp_pool_init;
1046 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1047 hw->func_caps.num_msix_vectors - 1);
1049 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1050 goto err_msix_pool_init;
1053 /* Initialize lan hmc */
1054 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1055 hw->func_caps.num_rx_qp, 0, 0);
1056 if (ret != I40E_SUCCESS) {
1057 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1058 goto err_init_lan_hmc;
1061 /* Configure lan hmc */
1062 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1063 if (ret != I40E_SUCCESS) {
1064 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1065 goto err_configure_lan_hmc;
1068 /* Get and check the mac address */
1069 i40e_get_mac_addr(hw, hw->mac.addr);
1070 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1071 PMD_INIT_LOG(ERR, "mac address is not valid");
1073 goto err_get_mac_addr;
1075 /* Copy the permanent MAC address */
1076 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1077 (struct ether_addr *) hw->mac.perm_addr);
1079 /* Disable flow control */
1080 hw->fc.requested_mode = I40E_FC_NONE;
1081 i40e_set_fc(hw, &aq_fail, TRUE);
1083 /* Set the global registers with default ether type value */
1084 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1085 if (ret != I40E_SUCCESS) {
1086 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1088 goto err_setup_pf_switch;
1091 /* PF setup, which includes VSI setup */
1092 ret = i40e_pf_setup(pf);
1094 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1095 goto err_setup_pf_switch;
1098 /* reset all stats of the device, including pf and main vsi */
1099 i40e_dev_stats_reset(dev);
1103 /* Disable double vlan by default */
1104 i40e_vsi_config_double_vlan(vsi, FALSE);
1106 if (!vsi->max_macaddrs)
1107 len = ETHER_ADDR_LEN;
1109 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1111 /* Should be after VSI initialized */
1112 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1113 if (!dev->data->mac_addrs) {
1114 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1115 "for storing mac address");
1118 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1119 &dev->data->mac_addrs[0]);
1121 /* initialize pf host driver to setup SRIOV resource if applicable */
1122 i40e_pf_host_init(dev);
1124 /* register callback func to eal lib */
1125 rte_intr_callback_register(&(pci_dev->intr_handle),
1126 i40e_dev_interrupt_handler, (void *)dev);
1128 /* configure and enable device interrupt */
1129 i40e_pf_config_irq0(hw, TRUE);
1130 i40e_pf_enable_irq0(hw);
1132 /* enable uio intr after callback register */
1133 rte_intr_enable(&(pci_dev->intr_handle));
1135 * Add an ethertype filter to drop all flow control frames transmitted
1136 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1139 i40e_add_tx_flow_control_drop_filter(pf);
1141 /* Set the max frame size to 0x2600 by default,
1142 * in case other drivers changed the default value.
1144 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1146 /* initialize mirror rule list */
1147 TAILQ_INIT(&pf->mirror_list);
1149 /* Init dcb to sw mode by default */
1150 ret = i40e_dcb_init_configure(dev, TRUE);
1151 if (ret != I40E_SUCCESS) {
1152 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1153 pf->flags &= ~I40E_FLAG_DCB;
1159 i40e_vsi_release(pf->main_vsi);
1160 err_setup_pf_switch:
1162 err_configure_lan_hmc:
1163 (void)i40e_shutdown_lan_hmc(hw);
1165 i40e_res_pool_destroy(&pf->msix_pool);
1167 i40e_res_pool_destroy(&pf->qp_pool);
1170 err_get_capabilities:
1171 (void)i40e_shutdown_adminq(hw);
1177 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1179 struct rte_pci_device *pci_dev;
1181 struct i40e_filter_control_settings settings;
1183 uint8_t aq_fail = 0;
1185 PMD_INIT_FUNC_TRACE();
1187 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1190 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1191 pci_dev = dev->pci_dev;
1193 if (hw->adapter_stopped == 0)
1194 i40e_dev_close(dev);
1196 dev->dev_ops = NULL;
1197 dev->rx_pkt_burst = NULL;
1198 dev->tx_pkt_burst = NULL;
1201 ret = i40e_aq_stop_lldp(hw, true, NULL);
1202 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1203 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1205 /* Clear PXE mode */
1206 i40e_clear_pxe_mode(hw);
1208 /* Unconfigure filter control */
1209 memset(&settings, 0, sizeof(settings));
1210 ret = i40e_set_filter_control(hw, &settings);
1212 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1215 /* Disable flow control */
1216 hw->fc.requested_mode = I40E_FC_NONE;
1217 i40e_set_fc(hw, &aq_fail, TRUE);
1219 /* uninitialize pf host driver */
1220 i40e_pf_host_uninit(dev);
1222 rte_free(dev->data->mac_addrs);
1223 dev->data->mac_addrs = NULL;
1225 /* disable uio intr before callback unregister */
1226 rte_intr_disable(&(pci_dev->intr_handle));
1228 /* register callback func to eal lib */
1229 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1230 i40e_dev_interrupt_handler, (void *)dev);
1236 i40e_dev_configure(struct rte_eth_dev *dev)
1238 struct i40e_adapter *ad =
1239 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1240 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1241 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1244 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1245 * bulk allocation or vector Rx preconditions we will reset it.
1247 ad->rx_bulk_alloc_allowed = true;
1248 ad->rx_vec_allowed = true;
1249 ad->tx_simple_allowed = true;
1250 ad->tx_vec_allowed = true;
1252 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1253 ret = i40e_fdir_setup(pf);
1254 if (ret != I40E_SUCCESS) {
1255 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1258 ret = i40e_fdir_configure(dev);
1260 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1264 i40e_fdir_teardown(pf);
1266 ret = i40e_dev_init_vlan(dev);
1271 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1272 * RSS setting have different requirements.
1273 * General PMD driver call sequence are NIC init, configure,
1274 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1275 * will try to lookup the VSI that specific queue belongs to if VMDQ
1276 * applicable. So, VMDQ setting has to be done before
1277 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1278 * For RSS setting, it will try to calculate actual configured RX queue
1279 * number, which will be available after rx_queue_setup(). dev_start()
1280 * function is good to place RSS setup.
1282 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1283 ret = i40e_vmdq_setup(dev);
1288 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1289 ret = i40e_dcb_setup(dev);
1291 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1299 /* need to release vmdq resource if exists */
1300 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1301 i40e_vsi_release(pf->vmdq[i].vsi);
1302 pf->vmdq[i].vsi = NULL;
1307 /* need to release fdir resource if exists */
1308 i40e_fdir_teardown(pf);
1313 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1315 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1316 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1317 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1318 uint16_t msix_vect = vsi->msix_intr;
1321 for (i = 0; i < vsi->nb_qps; i++) {
1322 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1323 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1327 if (vsi->type != I40E_VSI_SRIOV) {
1328 if (!rte_intr_allow_others(intr_handle)) {
1329 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1330 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1332 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1335 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1336 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1338 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1343 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1344 vsi->user_param + (msix_vect - 1);
1346 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1347 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1349 I40E_WRITE_FLUSH(hw);
1353 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1354 int base_queue, int nb_queue)
1358 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1360 /* Bind all RX queues to allocated MSIX interrupt */
1361 for (i = 0; i < nb_queue; i++) {
1362 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1363 I40E_QINT_RQCTL_ITR_INDX_MASK |
1364 ((base_queue + i + 1) <<
1365 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1366 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1367 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1369 if (i == nb_queue - 1)
1370 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1371 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1374 /* Write first RX queue to Link list register as the head element */
1375 if (vsi->type != I40E_VSI_SRIOV) {
1377 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1379 if (msix_vect == I40E_MISC_VEC_ID) {
1380 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1382 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1384 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1386 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1389 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1391 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1393 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1395 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1402 if (msix_vect == I40E_MISC_VEC_ID) {
1404 I40E_VPINT_LNKLST0(vsi->user_param),
1406 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1408 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1410 /* num_msix_vectors_vf needs to minus irq0 */
1411 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1412 vsi->user_param + (msix_vect - 1);
1414 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1416 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1418 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1422 I40E_WRITE_FLUSH(hw);
1426 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1428 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1429 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1430 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1431 uint16_t msix_vect = vsi->msix_intr;
1432 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1433 uint16_t queue_idx = 0;
1438 for (i = 0; i < vsi->nb_qps; i++) {
1439 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1440 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1443 /* INTENA flag is not auto-cleared for interrupt */
1444 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1445 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1446 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1447 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1448 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1450 /* VF bind interrupt */
1451 if (vsi->type == I40E_VSI_SRIOV) {
1452 __vsi_queues_bind_intr(vsi, msix_vect,
1453 vsi->base_queue, vsi->nb_qps);
1457 /* PF & VMDq bind interrupt */
1458 if (rte_intr_dp_is_en(intr_handle)) {
1459 if (vsi->type == I40E_VSI_MAIN) {
1462 } else if (vsi->type == I40E_VSI_VMDQ2) {
1463 struct i40e_vsi *main_vsi =
1464 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1465 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1470 for (i = 0; i < vsi->nb_used_qps; i++) {
1472 if (!rte_intr_allow_others(intr_handle))
1473 /* allow to share MISC_VEC_ID */
1474 msix_vect = I40E_MISC_VEC_ID;
1476 /* no enough msix_vect, map all to one */
1477 __vsi_queues_bind_intr(vsi, msix_vect,
1478 vsi->base_queue + i,
1479 vsi->nb_used_qps - i);
1480 for (; !!record && i < vsi->nb_used_qps; i++)
1481 intr_handle->intr_vec[queue_idx + i] =
1485 /* 1:1 queue/msix_vect mapping */
1486 __vsi_queues_bind_intr(vsi, msix_vect,
1487 vsi->base_queue + i, 1);
1489 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1497 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1499 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1500 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1501 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1502 uint16_t interval = i40e_calc_itr_interval(\
1503 RTE_LIBRTE_I40E_ITR_INTERVAL);
1504 uint16_t msix_intr, i;
1506 if (rte_intr_allow_others(intr_handle))
1507 for (i = 0; i < vsi->nb_msix; i++) {
1508 msix_intr = vsi->msix_intr + i;
1509 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1510 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1511 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1512 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1514 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1517 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1518 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1519 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1520 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1522 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1524 I40E_WRITE_FLUSH(hw);
1528 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1530 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1531 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1532 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1533 uint16_t msix_intr, i;
1535 if (rte_intr_allow_others(intr_handle))
1536 for (i = 0; i < vsi->nb_msix; i++) {
1537 msix_intr = vsi->msix_intr + i;
1538 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1542 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1544 I40E_WRITE_FLUSH(hw);
1547 static inline uint8_t
1548 i40e_parse_link_speeds(uint16_t link_speeds)
1550 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1552 if (link_speeds & ETH_LINK_SPEED_40G)
1553 link_speed |= I40E_LINK_SPEED_40GB;
1554 if (link_speeds & ETH_LINK_SPEED_20G)
1555 link_speed |= I40E_LINK_SPEED_20GB;
1556 if (link_speeds & ETH_LINK_SPEED_10G)
1557 link_speed |= I40E_LINK_SPEED_10GB;
1558 if (link_speeds & ETH_LINK_SPEED_1G)
1559 link_speed |= I40E_LINK_SPEED_1GB;
1560 if (link_speeds & ETH_LINK_SPEED_100M)
1561 link_speed |= I40E_LINK_SPEED_100MB;
1567 i40e_phy_conf_link(struct i40e_hw *hw,
1569 uint8_t force_speed)
1571 enum i40e_status_code status;
1572 struct i40e_aq_get_phy_abilities_resp phy_ab;
1573 struct i40e_aq_set_phy_config phy_conf;
1574 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1575 I40E_AQ_PHY_FLAG_PAUSE_RX |
1576 I40E_AQ_PHY_FLAG_PAUSE_RX |
1577 I40E_AQ_PHY_FLAG_LOW_POWER;
1578 const uint8_t advt = I40E_LINK_SPEED_40GB |
1579 I40E_LINK_SPEED_10GB |
1580 I40E_LINK_SPEED_1GB |
1581 I40E_LINK_SPEED_100MB;
1585 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1590 memset(&phy_conf, 0, sizeof(phy_conf));
1592 /* bits 0-2 use the values from get_phy_abilities_resp */
1594 abilities |= phy_ab.abilities & mask;
1596 /* update ablities and speed */
1597 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1598 phy_conf.link_speed = advt;
1600 phy_conf.link_speed = force_speed;
1602 phy_conf.abilities = abilities;
1604 /* use get_phy_abilities_resp value for the rest */
1605 phy_conf.phy_type = phy_ab.phy_type;
1606 phy_conf.eee_capability = phy_ab.eee_capability;
1607 phy_conf.eeer = phy_ab.eeer_val;
1608 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1610 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1611 phy_ab.abilities, phy_ab.link_speed);
1612 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1613 phy_conf.abilities, phy_conf.link_speed);
1615 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1619 return I40E_SUCCESS;
1623 i40e_apply_link_speed(struct rte_eth_dev *dev)
1626 uint8_t abilities = 0;
1627 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628 struct rte_eth_conf *conf = &dev->data->dev_conf;
1630 speed = i40e_parse_link_speeds(conf->link_speeds);
1631 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1632 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1633 abilities |= I40E_AQ_PHY_AN_ENABLED;
1634 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1636 /* Skip changing speed on 40G interfaces, FW does not support */
1637 if (i40e_is_40G_device(hw->device_id)) {
1638 speed = I40E_LINK_SPEED_UNKNOWN;
1639 abilities |= I40E_AQ_PHY_AN_ENABLED;
1642 return i40e_phy_conf_link(hw, abilities, speed);
1646 i40e_dev_start(struct rte_eth_dev *dev)
1648 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1649 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650 struct i40e_vsi *main_vsi = pf->main_vsi;
1652 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1653 uint32_t intr_vector = 0;
1655 hw->adapter_stopped = 0;
1657 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1658 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1659 dev->data->port_id);
1663 rte_intr_disable(intr_handle);
1665 if ((rte_intr_cap_multiple(intr_handle) ||
1666 !RTE_ETH_DEV_SRIOV(dev).active) &&
1667 dev->data->dev_conf.intr_conf.rxq != 0) {
1668 intr_vector = dev->data->nb_rx_queues;
1669 if (rte_intr_efd_enable(intr_handle, intr_vector))
1673 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1674 intr_handle->intr_vec =
1675 rte_zmalloc("intr_vec",
1676 dev->data->nb_rx_queues * sizeof(int),
1678 if (!intr_handle->intr_vec) {
1679 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1680 " intr_vec\n", dev->data->nb_rx_queues);
1685 /* Initialize VSI */
1686 ret = i40e_dev_rxtx_init(pf);
1687 if (ret != I40E_SUCCESS) {
1688 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1692 /* Map queues with MSIX interrupt */
1693 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1694 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1695 i40e_vsi_queues_bind_intr(main_vsi);
1696 i40e_vsi_enable_queues_intr(main_vsi);
1698 /* Map VMDQ VSI queues with MSIX interrupt */
1699 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1700 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1701 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1702 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1705 /* enable FDIR MSIX interrupt */
1706 if (pf->fdir.fdir_vsi) {
1707 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1708 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1711 /* Enable all queues which have been configured */
1712 ret = i40e_dev_switch_queues(pf, TRUE);
1713 if (ret != I40E_SUCCESS) {
1714 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1718 /* Enable receiving broadcast packets */
1719 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1720 if (ret != I40E_SUCCESS)
1721 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1723 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1724 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1726 if (ret != I40E_SUCCESS)
1727 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1730 /* Apply link configure */
1731 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1732 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1733 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1734 PMD_DRV_LOG(ERR, "Invalid link setting");
1737 ret = i40e_apply_link_speed(dev);
1738 if (I40E_SUCCESS != ret) {
1739 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1743 if (!rte_intr_allow_others(intr_handle)) {
1744 rte_intr_callback_unregister(intr_handle,
1745 i40e_dev_interrupt_handler,
1747 /* configure and enable device interrupt */
1748 i40e_pf_config_irq0(hw, FALSE);
1749 i40e_pf_enable_irq0(hw);
1751 if (dev->data->dev_conf.intr_conf.lsc != 0)
1752 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1753 " no intr multiplex\n");
1756 /* enable uio intr after callback register */
1757 rte_intr_enable(intr_handle);
1759 return I40E_SUCCESS;
1762 i40e_dev_switch_queues(pf, FALSE);
1763 i40e_dev_clear_queues(dev);
1769 i40e_dev_stop(struct rte_eth_dev *dev)
1771 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1772 struct i40e_vsi *main_vsi = pf->main_vsi;
1773 struct i40e_mirror_rule *p_mirror;
1774 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1777 /* Disable all queues */
1778 i40e_dev_switch_queues(pf, FALSE);
1780 /* un-map queues with interrupt registers */
1781 i40e_vsi_disable_queues_intr(main_vsi);
1782 i40e_vsi_queues_unbind_intr(main_vsi);
1784 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1785 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1786 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1789 if (pf->fdir.fdir_vsi) {
1790 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1791 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1793 /* Clear all queues and release memory */
1794 i40e_dev_clear_queues(dev);
1797 i40e_dev_set_link_down(dev);
1799 /* Remove all mirror rules */
1800 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1801 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1804 pf->nb_mirror_rule = 0;
1806 if (!rte_intr_allow_others(intr_handle))
1807 /* resume to the default handler */
1808 rte_intr_callback_register(intr_handle,
1809 i40e_dev_interrupt_handler,
1812 /* Clean datapath event and queue/vec mapping */
1813 rte_intr_efd_disable(intr_handle);
1814 if (intr_handle->intr_vec) {
1815 rte_free(intr_handle->intr_vec);
1816 intr_handle->intr_vec = NULL;
1821 i40e_dev_close(struct rte_eth_dev *dev)
1823 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1824 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1828 PMD_INIT_FUNC_TRACE();
1831 hw->adapter_stopped = 1;
1832 i40e_dev_free_queues(dev);
1834 /* Disable interrupt */
1835 i40e_pf_disable_irq0(hw);
1836 rte_intr_disable(&(dev->pci_dev->intr_handle));
1838 /* shutdown and destroy the HMC */
1839 i40e_shutdown_lan_hmc(hw);
1841 /* release all the existing VSIs and VEBs */
1842 i40e_fdir_teardown(pf);
1843 i40e_vsi_release(pf->main_vsi);
1845 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1846 i40e_vsi_release(pf->vmdq[i].vsi);
1847 pf->vmdq[i].vsi = NULL;
1853 /* shutdown the adminq */
1854 i40e_aq_queue_shutdown(hw, true);
1855 i40e_shutdown_adminq(hw);
1857 i40e_res_pool_destroy(&pf->qp_pool);
1858 i40e_res_pool_destroy(&pf->msix_pool);
1860 /* force a PF reset to clean anything leftover */
1861 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1862 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1863 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1864 I40E_WRITE_FLUSH(hw);
1868 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1870 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872 struct i40e_vsi *vsi = pf->main_vsi;
1875 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1877 if (status != I40E_SUCCESS)
1878 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1880 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1882 if (status != I40E_SUCCESS)
1883 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1888 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1890 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1891 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1892 struct i40e_vsi *vsi = pf->main_vsi;
1895 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1897 if (status != I40E_SUCCESS)
1898 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1900 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1902 if (status != I40E_SUCCESS)
1903 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1907 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1909 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1910 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911 struct i40e_vsi *vsi = pf->main_vsi;
1914 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1915 if (ret != I40E_SUCCESS)
1916 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1920 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1922 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1923 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 struct i40e_vsi *vsi = pf->main_vsi;
1927 if (dev->data->promiscuous == 1)
1928 return; /* must remain in all_multicast mode */
1930 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1931 vsi->seid, FALSE, NULL);
1932 if (ret != I40E_SUCCESS)
1933 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1937 * Set device link up.
1940 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1942 /* re-apply link speed setting */
1943 return i40e_apply_link_speed(dev);
1947 * Set device link down.
1950 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1952 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1953 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1954 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1956 return i40e_phy_conf_link(hw, abilities, speed);
1960 i40e_dev_link_update(struct rte_eth_dev *dev,
1961 int wait_to_complete)
1963 #define CHECK_INTERVAL 100 /* 100ms */
1964 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1965 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1966 struct i40e_link_status link_status;
1967 struct rte_eth_link link, old;
1969 unsigned rep_cnt = MAX_REPEAT_TIME;
1971 memset(&link, 0, sizeof(link));
1972 memset(&old, 0, sizeof(old));
1973 memset(&link_status, 0, sizeof(link_status));
1974 rte_i40e_dev_atomic_read_link_status(dev, &old);
1977 /* Get link status information from hardware */
1978 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1979 if (status != I40E_SUCCESS) {
1980 link.link_speed = ETH_SPEED_NUM_100M;
1981 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1982 PMD_DRV_LOG(ERR, "Failed to get link info");
1986 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1987 if (!wait_to_complete)
1990 rte_delay_ms(CHECK_INTERVAL);
1991 } while (!link.link_status && rep_cnt--);
1993 if (!link.link_status)
1996 /* i40e uses full duplex only */
1997 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1999 /* Parse the link status */
2000 switch (link_status.link_speed) {
2001 case I40E_LINK_SPEED_100MB:
2002 link.link_speed = ETH_SPEED_NUM_100M;
2004 case I40E_LINK_SPEED_1GB:
2005 link.link_speed = ETH_SPEED_NUM_1G;
2007 case I40E_LINK_SPEED_10GB:
2008 link.link_speed = ETH_SPEED_NUM_10G;
2010 case I40E_LINK_SPEED_20GB:
2011 link.link_speed = ETH_SPEED_NUM_20G;
2013 case I40E_LINK_SPEED_40GB:
2014 link.link_speed = ETH_SPEED_NUM_40G;
2017 link.link_speed = ETH_SPEED_NUM_100M;
2021 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2022 ETH_LINK_SPEED_FIXED);
2025 rte_i40e_dev_atomic_write_link_status(dev, &link);
2026 if (link.link_status == old.link_status)
2032 /* Get all the statistics of a VSI */
2034 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2036 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2037 struct i40e_eth_stats *nes = &vsi->eth_stats;
2038 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2039 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2041 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2042 vsi->offset_loaded, &oes->rx_bytes,
2044 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2045 vsi->offset_loaded, &oes->rx_unicast,
2047 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2048 vsi->offset_loaded, &oes->rx_multicast,
2049 &nes->rx_multicast);
2050 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2051 vsi->offset_loaded, &oes->rx_broadcast,
2052 &nes->rx_broadcast);
2053 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2054 &oes->rx_discards, &nes->rx_discards);
2055 /* GLV_REPC not supported */
2056 /* GLV_RMPC not supported */
2057 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2058 &oes->rx_unknown_protocol,
2059 &nes->rx_unknown_protocol);
2060 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2061 vsi->offset_loaded, &oes->tx_bytes,
2063 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2064 vsi->offset_loaded, &oes->tx_unicast,
2066 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2067 vsi->offset_loaded, &oes->tx_multicast,
2068 &nes->tx_multicast);
2069 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2070 vsi->offset_loaded, &oes->tx_broadcast,
2071 &nes->tx_broadcast);
2072 /* GLV_TDPC not supported */
2073 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2074 &oes->tx_errors, &nes->tx_errors);
2075 vsi->offset_loaded = true;
2077 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2079 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2080 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2081 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2082 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2083 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2084 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2085 nes->rx_unknown_protocol);
2086 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2087 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2088 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2089 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2090 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2091 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2092 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2097 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2100 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2101 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2103 /* Get statistics of struct i40e_eth_stats */
2104 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2105 I40E_GLPRT_GORCL(hw->port),
2106 pf->offset_loaded, &os->eth.rx_bytes,
2108 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2109 I40E_GLPRT_UPRCL(hw->port),
2110 pf->offset_loaded, &os->eth.rx_unicast,
2111 &ns->eth.rx_unicast);
2112 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2113 I40E_GLPRT_MPRCL(hw->port),
2114 pf->offset_loaded, &os->eth.rx_multicast,
2115 &ns->eth.rx_multicast);
2116 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2117 I40E_GLPRT_BPRCL(hw->port),
2118 pf->offset_loaded, &os->eth.rx_broadcast,
2119 &ns->eth.rx_broadcast);
2120 /* Workaround: CRC size should not be included in byte statistics,
2121 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2123 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2124 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2126 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2127 pf->offset_loaded, &os->eth.rx_discards,
2128 &ns->eth.rx_discards);
2129 /* GLPRT_REPC not supported */
2130 /* GLPRT_RMPC not supported */
2131 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2133 &os->eth.rx_unknown_protocol,
2134 &ns->eth.rx_unknown_protocol);
2135 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2136 I40E_GLPRT_GOTCL(hw->port),
2137 pf->offset_loaded, &os->eth.tx_bytes,
2139 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2140 I40E_GLPRT_UPTCL(hw->port),
2141 pf->offset_loaded, &os->eth.tx_unicast,
2142 &ns->eth.tx_unicast);
2143 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2144 I40E_GLPRT_MPTCL(hw->port),
2145 pf->offset_loaded, &os->eth.tx_multicast,
2146 &ns->eth.tx_multicast);
2147 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2148 I40E_GLPRT_BPTCL(hw->port),
2149 pf->offset_loaded, &os->eth.tx_broadcast,
2150 &ns->eth.tx_broadcast);
2151 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2152 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2153 /* GLPRT_TEPC not supported */
2155 /* additional port specific stats */
2156 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2157 pf->offset_loaded, &os->tx_dropped_link_down,
2158 &ns->tx_dropped_link_down);
2159 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2160 pf->offset_loaded, &os->crc_errors,
2162 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2163 pf->offset_loaded, &os->illegal_bytes,
2164 &ns->illegal_bytes);
2165 /* GLPRT_ERRBC not supported */
2166 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2167 pf->offset_loaded, &os->mac_local_faults,
2168 &ns->mac_local_faults);
2169 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2170 pf->offset_loaded, &os->mac_remote_faults,
2171 &ns->mac_remote_faults);
2172 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2173 pf->offset_loaded, &os->rx_length_errors,
2174 &ns->rx_length_errors);
2175 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2176 pf->offset_loaded, &os->link_xon_rx,
2178 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2179 pf->offset_loaded, &os->link_xoff_rx,
2181 for (i = 0; i < 8; i++) {
2182 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2184 &os->priority_xon_rx[i],
2185 &ns->priority_xon_rx[i]);
2186 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2188 &os->priority_xoff_rx[i],
2189 &ns->priority_xoff_rx[i]);
2191 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2192 pf->offset_loaded, &os->link_xon_tx,
2194 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2195 pf->offset_loaded, &os->link_xoff_tx,
2197 for (i = 0; i < 8; i++) {
2198 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2200 &os->priority_xon_tx[i],
2201 &ns->priority_xon_tx[i]);
2202 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2204 &os->priority_xoff_tx[i],
2205 &ns->priority_xoff_tx[i]);
2206 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2208 &os->priority_xon_2_xoff[i],
2209 &ns->priority_xon_2_xoff[i]);
2211 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2212 I40E_GLPRT_PRC64L(hw->port),
2213 pf->offset_loaded, &os->rx_size_64,
2215 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2216 I40E_GLPRT_PRC127L(hw->port),
2217 pf->offset_loaded, &os->rx_size_127,
2219 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2220 I40E_GLPRT_PRC255L(hw->port),
2221 pf->offset_loaded, &os->rx_size_255,
2223 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2224 I40E_GLPRT_PRC511L(hw->port),
2225 pf->offset_loaded, &os->rx_size_511,
2227 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2228 I40E_GLPRT_PRC1023L(hw->port),
2229 pf->offset_loaded, &os->rx_size_1023,
2231 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2232 I40E_GLPRT_PRC1522L(hw->port),
2233 pf->offset_loaded, &os->rx_size_1522,
2235 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2236 I40E_GLPRT_PRC9522L(hw->port),
2237 pf->offset_loaded, &os->rx_size_big,
2239 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2240 pf->offset_loaded, &os->rx_undersize,
2242 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2243 pf->offset_loaded, &os->rx_fragments,
2245 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2246 pf->offset_loaded, &os->rx_oversize,
2248 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2249 pf->offset_loaded, &os->rx_jabber,
2251 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2252 I40E_GLPRT_PTC64L(hw->port),
2253 pf->offset_loaded, &os->tx_size_64,
2255 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2256 I40E_GLPRT_PTC127L(hw->port),
2257 pf->offset_loaded, &os->tx_size_127,
2259 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2260 I40E_GLPRT_PTC255L(hw->port),
2261 pf->offset_loaded, &os->tx_size_255,
2263 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2264 I40E_GLPRT_PTC511L(hw->port),
2265 pf->offset_loaded, &os->tx_size_511,
2267 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2268 I40E_GLPRT_PTC1023L(hw->port),
2269 pf->offset_loaded, &os->tx_size_1023,
2271 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2272 I40E_GLPRT_PTC1522L(hw->port),
2273 pf->offset_loaded, &os->tx_size_1522,
2275 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2276 I40E_GLPRT_PTC9522L(hw->port),
2277 pf->offset_loaded, &os->tx_size_big,
2279 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2281 &os->fd_sb_match, &ns->fd_sb_match);
2282 /* GLPRT_MSPDC not supported */
2283 /* GLPRT_XEC not supported */
2285 pf->offset_loaded = true;
2288 i40e_update_vsi_stats(pf->main_vsi);
2291 /* Get all statistics of a port */
2293 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2295 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2296 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2300 /* call read registers - updates values, now write them to struct */
2301 i40e_read_stats_registers(pf, hw);
2303 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2304 pf->main_vsi->eth_stats.rx_multicast +
2305 pf->main_vsi->eth_stats.rx_broadcast -
2306 pf->main_vsi->eth_stats.rx_discards;
2307 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2308 pf->main_vsi->eth_stats.tx_multicast +
2309 pf->main_vsi->eth_stats.tx_broadcast;
2310 stats->ibytes = ns->eth.rx_bytes;
2311 stats->obytes = ns->eth.tx_bytes;
2312 stats->oerrors = ns->eth.tx_errors +
2313 pf->main_vsi->eth_stats.tx_errors;
2316 stats->imissed = ns->eth.rx_discards +
2317 pf->main_vsi->eth_stats.rx_discards;
2318 stats->ierrors = ns->crc_errors +
2319 ns->rx_length_errors + ns->rx_undersize +
2320 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2322 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2323 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2324 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2325 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2326 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2327 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2328 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2329 ns->eth.rx_unknown_protocol);
2330 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2331 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2332 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2333 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2334 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2335 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2337 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2338 ns->tx_dropped_link_down);
2339 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2340 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2342 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2343 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2344 ns->mac_local_faults);
2345 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2346 ns->mac_remote_faults);
2347 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2348 ns->rx_length_errors);
2349 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2350 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2351 for (i = 0; i < 8; i++) {
2352 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2353 i, ns->priority_xon_rx[i]);
2354 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2355 i, ns->priority_xoff_rx[i]);
2357 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2358 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2359 for (i = 0; i < 8; i++) {
2360 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2361 i, ns->priority_xon_tx[i]);
2362 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2363 i, ns->priority_xoff_tx[i]);
2364 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2365 i, ns->priority_xon_2_xoff[i]);
2367 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2368 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2369 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2370 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2371 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2372 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2373 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2374 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2375 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2376 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2377 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2378 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2379 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2380 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2381 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2382 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2383 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2384 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2385 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2386 ns->mac_short_packet_dropped);
2387 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2388 ns->checksum_error);
2389 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2390 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2393 /* Reset the statistics */
2395 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2397 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2398 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400 /* Mark PF and VSI stats to update the offset, aka "reset" */
2401 pf->offset_loaded = false;
2403 pf->main_vsi->offset_loaded = false;
2405 /* read the stats, reading current register values into offset */
2406 i40e_read_stats_registers(pf, hw);
2410 i40e_xstats_calc_num(void)
2412 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2413 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2414 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2417 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2418 struct rte_eth_xstat_name *xstats_names,
2419 __rte_unused unsigned limit)
2424 if (xstats_names == NULL)
2425 return i40e_xstats_calc_num();
2427 /* Note: limit checked in rte_eth_xstats_names() */
2429 /* Get stats from i40e_eth_stats struct */
2430 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2431 snprintf(xstats_names[count].name,
2432 sizeof(xstats_names[count].name),
2433 "%s", rte_i40e_stats_strings[i].name);
2434 xstats_names[count].id = count;
2438 /* Get individiual stats from i40e_hw_port struct */
2439 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2440 snprintf(xstats_names[count].name,
2441 sizeof(xstats_names[count].name),
2442 "%s", rte_i40e_hw_port_strings[i].name);
2443 xstats_names[count].id = count;
2447 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2448 for (prio = 0; prio < 8; prio++) {
2449 snprintf(xstats_names[count].name,
2450 sizeof(xstats_names[count].name),
2451 "rx_priority%u_%s", prio,
2452 rte_i40e_rxq_prio_strings[i].name);
2453 xstats_names[count].id = count;
2458 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2459 for (prio = 0; prio < 8; prio++) {
2460 snprintf(xstats_names[count].name,
2461 sizeof(xstats_names[count].name),
2462 "tx_priority%u_%s", prio,
2463 rte_i40e_txq_prio_strings[i].name);
2464 xstats_names[count].id = count;
2472 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2475 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2476 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477 unsigned i, count, prio;
2478 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2480 count = i40e_xstats_calc_num();
2484 i40e_read_stats_registers(pf, hw);
2491 /* Get stats from i40e_eth_stats struct */
2492 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2493 xstats[count].id = count;
2494 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2495 rte_i40e_stats_strings[i].offset);
2499 /* Get individiual stats from i40e_hw_port struct */
2500 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2501 xstats[count].id = count;
2502 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2503 rte_i40e_hw_port_strings[i].offset);
2507 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2508 for (prio = 0; prio < 8; prio++) {
2509 xstats[count].id = count;
2510 xstats[count].value =
2511 *(uint64_t *)(((char *)hw_stats) +
2512 rte_i40e_rxq_prio_strings[i].offset +
2513 (sizeof(uint64_t) * prio));
2518 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2519 for (prio = 0; prio < 8; prio++) {
2520 xstats[count].id = count;
2521 xstats[count].value =
2522 *(uint64_t *)(((char *)hw_stats) +
2523 rte_i40e_txq_prio_strings[i].offset +
2524 (sizeof(uint64_t) * prio));
2533 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2534 __rte_unused uint16_t queue_id,
2535 __rte_unused uint8_t stat_idx,
2536 __rte_unused uint8_t is_rx)
2538 PMD_INIT_FUNC_TRACE();
2544 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2546 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2547 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2548 struct i40e_vsi *vsi = pf->main_vsi;
2550 dev_info->max_rx_queues = vsi->nb_qps;
2551 dev_info->max_tx_queues = vsi->nb_qps;
2552 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2553 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2554 dev_info->max_mac_addrs = vsi->max_macaddrs;
2555 dev_info->max_vfs = dev->pci_dev->max_vfs;
2556 dev_info->rx_offload_capa =
2557 DEV_RX_OFFLOAD_VLAN_STRIP |
2558 DEV_RX_OFFLOAD_QINQ_STRIP |
2559 DEV_RX_OFFLOAD_IPV4_CKSUM |
2560 DEV_RX_OFFLOAD_UDP_CKSUM |
2561 DEV_RX_OFFLOAD_TCP_CKSUM;
2562 dev_info->tx_offload_capa =
2563 DEV_TX_OFFLOAD_VLAN_INSERT |
2564 DEV_TX_OFFLOAD_QINQ_INSERT |
2565 DEV_TX_OFFLOAD_IPV4_CKSUM |
2566 DEV_TX_OFFLOAD_UDP_CKSUM |
2567 DEV_TX_OFFLOAD_TCP_CKSUM |
2568 DEV_TX_OFFLOAD_SCTP_CKSUM |
2569 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2570 DEV_TX_OFFLOAD_TCP_TSO;
2571 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2573 dev_info->reta_size = pf->hash_lut_size;
2574 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2576 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2578 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2579 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2580 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2582 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2586 dev_info->default_txconf = (struct rte_eth_txconf) {
2588 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2589 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2590 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2592 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2593 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2594 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2595 ETH_TXQ_FLAGS_NOOFFLOADS,
2598 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2599 .nb_max = I40E_MAX_RING_DESC,
2600 .nb_min = I40E_MIN_RING_DESC,
2601 .nb_align = I40E_ALIGN_RING_DESC,
2604 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2605 .nb_max = I40E_MAX_RING_DESC,
2606 .nb_min = I40E_MIN_RING_DESC,
2607 .nb_align = I40E_ALIGN_RING_DESC,
2610 if (pf->flags & I40E_FLAG_VMDQ) {
2611 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2612 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2613 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2614 pf->max_nb_vmdq_vsi;
2615 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2616 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2617 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2620 if (i40e_is_40G_device(hw->device_id))
2622 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2625 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2629 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2631 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2632 struct i40e_vsi *vsi = pf->main_vsi;
2633 PMD_INIT_FUNC_TRACE();
2636 return i40e_vsi_add_vlan(vsi, vlan_id);
2638 return i40e_vsi_delete_vlan(vsi, vlan_id);
2642 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2643 enum rte_vlan_type vlan_type,
2646 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647 uint64_t reg_r = 0, reg_w = 0;
2648 uint16_t reg_id = 0;
2650 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2652 switch (vlan_type) {
2653 case ETH_VLAN_TYPE_OUTER:
2659 case ETH_VLAN_TYPE_INNER:
2665 "Unsupported vlan type in single vlan.\n");
2671 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2674 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2676 if (ret != I40E_SUCCESS) {
2677 PMD_DRV_LOG(ERR, "Fail to debug read from "
2678 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2682 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2683 "0x%08"PRIx64"", reg_id, reg_r);
2685 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2686 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2687 if (reg_r == reg_w) {
2689 PMD_DRV_LOG(DEBUG, "No need to write");
2693 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2695 if (ret != I40E_SUCCESS) {
2697 PMD_DRV_LOG(ERR, "Fail to debug write to "
2698 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2701 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2702 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2708 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2710 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2711 struct i40e_vsi *vsi = pf->main_vsi;
2713 if (mask & ETH_VLAN_FILTER_MASK) {
2714 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2715 i40e_vsi_config_vlan_filter(vsi, TRUE);
2717 i40e_vsi_config_vlan_filter(vsi, FALSE);
2720 if (mask & ETH_VLAN_STRIP_MASK) {
2721 /* Enable or disable VLAN stripping */
2722 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2723 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2725 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2728 if (mask & ETH_VLAN_EXTEND_MASK) {
2729 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2730 i40e_vsi_config_double_vlan(vsi, TRUE);
2731 /* Set global registers with default ether type value */
2732 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2734 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2738 i40e_vsi_config_double_vlan(vsi, FALSE);
2743 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2744 __rte_unused uint16_t queue,
2745 __rte_unused int on)
2747 PMD_INIT_FUNC_TRACE();
2751 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2753 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2754 struct i40e_vsi *vsi = pf->main_vsi;
2755 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2756 struct i40e_vsi_vlan_pvid_info info;
2758 memset(&info, 0, sizeof(info));
2761 info.config.pvid = pvid;
2763 info.config.reject.tagged =
2764 data->dev_conf.txmode.hw_vlan_reject_tagged;
2765 info.config.reject.untagged =
2766 data->dev_conf.txmode.hw_vlan_reject_untagged;
2769 return i40e_vsi_vlan_pvid_set(vsi, &info);
2773 i40e_dev_led_on(struct rte_eth_dev *dev)
2775 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2776 uint32_t mode = i40e_led_get(hw);
2779 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2785 i40e_dev_led_off(struct rte_eth_dev *dev)
2787 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788 uint32_t mode = i40e_led_get(hw);
2791 i40e_led_set(hw, 0, false);
2797 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2800 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2802 fc_conf->pause_time = pf->fc_conf.pause_time;
2803 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2804 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2806 /* Return current mode according to actual setting*/
2807 switch (hw->fc.current_mode) {
2809 fc_conf->mode = RTE_FC_FULL;
2811 case I40E_FC_TX_PAUSE:
2812 fc_conf->mode = RTE_FC_TX_PAUSE;
2814 case I40E_FC_RX_PAUSE:
2815 fc_conf->mode = RTE_FC_RX_PAUSE;
2819 fc_conf->mode = RTE_FC_NONE;
2826 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2828 uint32_t mflcn_reg, fctrl_reg, reg;
2829 uint32_t max_high_water;
2830 uint8_t i, aq_failure;
2834 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2835 [RTE_FC_NONE] = I40E_FC_NONE,
2836 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2837 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2838 [RTE_FC_FULL] = I40E_FC_FULL
2841 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2843 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2844 if ((fc_conf->high_water > max_high_water) ||
2845 (fc_conf->high_water < fc_conf->low_water)) {
2846 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2847 "High_water must <= %d.", max_high_water);
2851 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2852 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2853 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2855 pf->fc_conf.pause_time = fc_conf->pause_time;
2856 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2857 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2859 PMD_INIT_FUNC_TRACE();
2861 /* All the link flow control related enable/disable register
2862 * configuration is handle by the F/W
2864 err = i40e_set_fc(hw, &aq_failure, true);
2868 if (i40e_is_40G_device(hw->device_id)) {
2869 /* Configure flow control refresh threshold,
2870 * the value for stat_tx_pause_refresh_timer[8]
2871 * is used for global pause operation.
2875 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2876 pf->fc_conf.pause_time);
2878 /* configure the timer value included in transmitted pause
2880 * the value for stat_tx_pause_quanta[8] is used for global
2883 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2884 pf->fc_conf.pause_time);
2886 fctrl_reg = I40E_READ_REG(hw,
2887 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2889 if (fc_conf->mac_ctrl_frame_fwd != 0)
2890 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2892 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2894 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2897 /* Configure pause time (2 TCs per register) */
2898 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2899 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2900 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2902 /* Configure flow control refresh threshold value */
2903 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2904 pf->fc_conf.pause_time / 2);
2906 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2908 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2909 *depending on configuration
2911 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2912 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2913 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2915 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2916 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2919 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2922 /* config the water marker both based on the packets and bytes */
2923 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2924 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2925 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2926 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2927 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2928 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2929 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2930 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2932 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2933 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2936 I40E_WRITE_FLUSH(hw);
2942 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2943 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2945 PMD_INIT_FUNC_TRACE();
2950 /* Add a MAC address, and update filters */
2952 i40e_macaddr_add(struct rte_eth_dev *dev,
2953 struct ether_addr *mac_addr,
2954 __rte_unused uint32_t index,
2957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2958 struct i40e_mac_filter_info mac_filter;
2959 struct i40e_vsi *vsi;
2962 /* If VMDQ not enabled or configured, return */
2963 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2964 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2965 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2970 if (pool > pf->nb_cfg_vmdq_vsi) {
2971 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2972 pool, pf->nb_cfg_vmdq_vsi);
2976 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2977 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2978 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2980 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2985 vsi = pf->vmdq[pool - 1].vsi;
2987 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2988 if (ret != I40E_SUCCESS) {
2989 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2994 /* Remove a MAC address, and update filters */
2996 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2998 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2999 struct i40e_vsi *vsi;
3000 struct rte_eth_dev_data *data = dev->data;
3001 struct ether_addr *macaddr;
3006 macaddr = &(data->mac_addrs[index]);
3008 pool_sel = dev->data->mac_pool_sel[index];
3010 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3011 if (pool_sel & (1ULL << i)) {
3015 /* No VMDQ pool enabled or configured */
3016 if (!(pf->flags | I40E_FLAG_VMDQ) ||
3017 (i > pf->nb_cfg_vmdq_vsi)) {
3018 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3022 vsi = pf->vmdq[i - 1].vsi;
3024 ret = i40e_vsi_delete_mac(vsi, macaddr);
3027 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3034 /* Set perfect match or hash match of MAC and VLAN for a VF */
3036 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3037 struct rte_eth_mac_filter *filter,
3041 struct i40e_mac_filter_info mac_filter;
3042 struct ether_addr old_mac;
3043 struct ether_addr *new_mac;
3044 struct i40e_pf_vf *vf = NULL;
3049 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3052 hw = I40E_PF_TO_HW(pf);
3054 if (filter == NULL) {
3055 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3059 new_mac = &filter->mac_addr;
3061 if (is_zero_ether_addr(new_mac)) {
3062 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3066 vf_id = filter->dst_id;
3068 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3069 PMD_DRV_LOG(ERR, "Invalid argument.");
3072 vf = &pf->vfs[vf_id];
3074 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3075 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3080 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3081 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3083 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3086 mac_filter.filter_type = filter->filter_type;
3087 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3088 if (ret != I40E_SUCCESS) {
3089 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3092 ether_addr_copy(new_mac, &pf->dev_addr);
3094 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3096 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3097 if (ret != I40E_SUCCESS) {
3098 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3102 /* Clear device address as it has been removed */
3103 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3104 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3110 /* MAC filter handle */
3112 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3115 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3116 struct rte_eth_mac_filter *filter;
3117 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3118 int ret = I40E_NOT_SUPPORTED;
3120 filter = (struct rte_eth_mac_filter *)(arg);
3122 switch (filter_op) {
3123 case RTE_ETH_FILTER_NOP:
3126 case RTE_ETH_FILTER_ADD:
3127 i40e_pf_disable_irq0(hw);
3129 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3130 i40e_pf_enable_irq0(hw);
3132 case RTE_ETH_FILTER_DELETE:
3133 i40e_pf_disable_irq0(hw);
3135 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3136 i40e_pf_enable_irq0(hw);
3139 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3140 ret = I40E_ERR_PARAM;
3148 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3150 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3151 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3157 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3158 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3161 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3165 uint32_t *lut_dw = (uint32_t *)lut;
3166 uint16_t i, lut_size_dw = lut_size / 4;
3168 for (i = 0; i < lut_size_dw; i++)
3169 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3176 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3178 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3179 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3185 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3186 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3189 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3193 uint32_t *lut_dw = (uint32_t *)lut;
3194 uint16_t i, lut_size_dw = lut_size / 4;
3196 for (i = 0; i < lut_size_dw; i++)
3197 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3198 I40E_WRITE_FLUSH(hw);
3205 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3206 struct rte_eth_rss_reta_entry64 *reta_conf,
3209 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3210 uint16_t i, lut_size = pf->hash_lut_size;
3211 uint16_t idx, shift;
3215 if (reta_size != lut_size ||
3216 reta_size > ETH_RSS_RETA_SIZE_512) {
3217 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3218 "(%d) doesn't match the number hardware can supported "
3219 "(%d)\n", reta_size, lut_size);
3223 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3225 PMD_DRV_LOG(ERR, "No memory can be allocated");
3228 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3231 for (i = 0; i < reta_size; i++) {
3232 idx = i / RTE_RETA_GROUP_SIZE;
3233 shift = i % RTE_RETA_GROUP_SIZE;
3234 if (reta_conf[idx].mask & (1ULL << shift))
3235 lut[i] = reta_conf[idx].reta[shift];
3237 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3246 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3247 struct rte_eth_rss_reta_entry64 *reta_conf,
3250 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3251 uint16_t i, lut_size = pf->hash_lut_size;
3252 uint16_t idx, shift;
3256 if (reta_size != lut_size ||
3257 reta_size > ETH_RSS_RETA_SIZE_512) {
3258 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3259 "(%d) doesn't match the number hardware can supported "
3260 "(%d)\n", reta_size, lut_size);
3264 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3266 PMD_DRV_LOG(ERR, "No memory can be allocated");
3270 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3273 for (i = 0; i < reta_size; i++) {
3274 idx = i / RTE_RETA_GROUP_SIZE;
3275 shift = i % RTE_RETA_GROUP_SIZE;
3276 if (reta_conf[idx].mask & (1ULL << shift))
3277 reta_conf[idx].reta[shift] = lut[i];
3287 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3288 * @hw: pointer to the HW structure
3289 * @mem: pointer to mem struct to fill out
3290 * @size: size of memory requested
3291 * @alignment: what to align the allocation to
3293 enum i40e_status_code
3294 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3295 struct i40e_dma_mem *mem,
3299 const struct rte_memzone *mz = NULL;
3300 char z_name[RTE_MEMZONE_NAMESIZE];
3303 return I40E_ERR_PARAM;
3305 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3306 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3307 alignment, RTE_PGSIZE_2M);
3309 return I40E_ERR_NO_MEMORY;
3313 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3314 mem->zone = (const void *)mz;
3315 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3316 "%"PRIu64, mz->name, mem->pa);
3318 return I40E_SUCCESS;
3322 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3323 * @hw: pointer to the HW structure
3324 * @mem: ptr to mem struct to free
3326 enum i40e_status_code
3327 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3328 struct i40e_dma_mem *mem)
3331 return I40E_ERR_PARAM;
3333 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3334 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3336 rte_memzone_free((const struct rte_memzone *)mem->zone);
3341 return I40E_SUCCESS;
3345 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3346 * @hw: pointer to the HW structure
3347 * @mem: pointer to mem struct to fill out
3348 * @size: size of memory requested
3350 enum i40e_status_code
3351 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3352 struct i40e_virt_mem *mem,
3356 return I40E_ERR_PARAM;
3359 mem->va = rte_zmalloc("i40e", size, 0);
3362 return I40E_SUCCESS;
3364 return I40E_ERR_NO_MEMORY;
3368 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3369 * @hw: pointer to the HW structure
3370 * @mem: pointer to mem struct to free
3372 enum i40e_status_code
3373 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3374 struct i40e_virt_mem *mem)
3377 return I40E_ERR_PARAM;
3382 return I40E_SUCCESS;
3386 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3388 rte_spinlock_init(&sp->spinlock);
3392 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3394 rte_spinlock_lock(&sp->spinlock);
3398 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3400 rte_spinlock_unlock(&sp->spinlock);
3404 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3410 * Get the hardware capabilities, which will be parsed
3411 * and saved into struct i40e_hw.
3414 i40e_get_cap(struct i40e_hw *hw)
3416 struct i40e_aqc_list_capabilities_element_resp *buf;
3417 uint16_t len, size = 0;
3420 /* Calculate a huge enough buff for saving response data temporarily */
3421 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3422 I40E_MAX_CAP_ELE_NUM;
3423 buf = rte_zmalloc("i40e", len, 0);
3425 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3426 return I40E_ERR_NO_MEMORY;
3429 /* Get, parse the capabilities and save it to hw */
3430 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3431 i40e_aqc_opc_list_func_capabilities, NULL);
3432 if (ret != I40E_SUCCESS)
3433 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3435 /* Free the temporary buffer after being used */
3442 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3444 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3445 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3446 uint16_t qp_count = 0, vsi_count = 0;
3448 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3449 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3452 /* Add the parameter init for LFC */
3453 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3454 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3455 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3457 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3458 pf->max_num_vsi = hw->func_caps.num_vsis;
3459 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3460 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3461 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3463 /* FDir queue/VSI allocation */
3464 pf->fdir_qp_offset = 0;
3465 if (hw->func_caps.fd) {
3466 pf->flags |= I40E_FLAG_FDIR;
3467 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3469 pf->fdir_nb_qps = 0;
3471 qp_count += pf->fdir_nb_qps;
3474 /* LAN queue/VSI allocation */
3475 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3476 if (!hw->func_caps.rss) {
3479 pf->flags |= I40E_FLAG_RSS;
3480 if (hw->mac.type == I40E_MAC_X722)
3481 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3482 pf->lan_nb_qps = pf->lan_nb_qp_max;
3484 qp_count += pf->lan_nb_qps;
3487 /* VF queue/VSI allocation */
3488 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3489 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3490 pf->flags |= I40E_FLAG_SRIOV;
3491 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3492 pf->vf_num = dev->pci_dev->max_vfs;
3493 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3494 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3495 pf->vf_nb_qps * pf->vf_num);
3500 qp_count += pf->vf_nb_qps * pf->vf_num;
3501 vsi_count += pf->vf_num;
3503 /* VMDq queue/VSI allocation */
3504 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3505 pf->vmdq_nb_qps = 0;
3506 pf->max_nb_vmdq_vsi = 0;
3507 if (hw->func_caps.vmdq) {
3508 if (qp_count < hw->func_caps.num_tx_qp &&
3509 vsi_count < hw->func_caps.num_vsis) {
3510 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3511 qp_count) / pf->vmdq_nb_qp_max;
3513 /* Limit the maximum number of VMDq vsi to the maximum
3514 * ethdev can support
3516 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3517 hw->func_caps.num_vsis - vsi_count);
3518 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3520 if (pf->max_nb_vmdq_vsi) {
3521 pf->flags |= I40E_FLAG_VMDQ;
3522 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3523 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3524 "per VMDQ VSI, in total %u queues",
3525 pf->max_nb_vmdq_vsi,
3526 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3527 pf->max_nb_vmdq_vsi);
3529 PMD_DRV_LOG(INFO, "No enough queues left for "
3533 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3536 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3537 vsi_count += pf->max_nb_vmdq_vsi;
3539 if (hw->func_caps.dcb)
3540 pf->flags |= I40E_FLAG_DCB;
3542 if (qp_count > hw->func_caps.num_tx_qp) {
3543 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3544 "the hardware maximum %u", qp_count,
3545 hw->func_caps.num_tx_qp);
3548 if (vsi_count > hw->func_caps.num_vsis) {
3549 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3550 "the hardware maximum %u", vsi_count,
3551 hw->func_caps.num_vsis);
3559 i40e_pf_get_switch_config(struct i40e_pf *pf)
3561 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3562 struct i40e_aqc_get_switch_config_resp *switch_config;
3563 struct i40e_aqc_switch_config_element_resp *element;
3564 uint16_t start_seid = 0, num_reported;
3567 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3568 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3569 if (!switch_config) {
3570 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3574 /* Get the switch configurations */
3575 ret = i40e_aq_get_switch_config(hw, switch_config,
3576 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3577 if (ret != I40E_SUCCESS) {
3578 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3581 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3582 if (num_reported != 1) { /* The number should be 1 */
3583 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3587 /* Parse the switch configuration elements */
3588 element = &(switch_config->element[0]);
3589 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3590 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3591 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3593 PMD_DRV_LOG(INFO, "Unknown element type");
3596 rte_free(switch_config);
3602 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3605 struct pool_entry *entry;
3607 if (pool == NULL || num == 0)
3610 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3611 if (entry == NULL) {
3612 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3616 /* queue heap initialize */
3617 pool->num_free = num;
3618 pool->num_alloc = 0;
3620 LIST_INIT(&pool->alloc_list);
3621 LIST_INIT(&pool->free_list);
3623 /* Initialize element */
3627 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3632 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3634 struct pool_entry *entry, *next_entry;
3639 for (entry = LIST_FIRST(&pool->alloc_list);
3640 entry && (next_entry = LIST_NEXT(entry, next), 1);
3641 entry = next_entry) {
3642 LIST_REMOVE(entry, next);
3646 for (entry = LIST_FIRST(&pool->free_list);
3647 entry && (next_entry = LIST_NEXT(entry, next), 1);
3648 entry = next_entry) {
3649 LIST_REMOVE(entry, next);
3654 pool->num_alloc = 0;
3656 LIST_INIT(&pool->alloc_list);
3657 LIST_INIT(&pool->free_list);
3661 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3664 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3665 uint32_t pool_offset;
3669 PMD_DRV_LOG(ERR, "Invalid parameter");
3673 pool_offset = base - pool->base;
3674 /* Lookup in alloc list */
3675 LIST_FOREACH(entry, &pool->alloc_list, next) {
3676 if (entry->base == pool_offset) {
3677 valid_entry = entry;
3678 LIST_REMOVE(entry, next);
3683 /* Not find, return */
3684 if (valid_entry == NULL) {
3685 PMD_DRV_LOG(ERR, "Failed to find entry");
3690 * Found it, move it to free list and try to merge.
3691 * In order to make merge easier, always sort it by qbase.
3692 * Find adjacent prev and last entries.
3695 LIST_FOREACH(entry, &pool->free_list, next) {
3696 if (entry->base > valid_entry->base) {
3704 /* Try to merge with next one*/
3706 /* Merge with next one */
3707 if (valid_entry->base + valid_entry->len == next->base) {
3708 next->base = valid_entry->base;
3709 next->len += valid_entry->len;
3710 rte_free(valid_entry);
3717 /* Merge with previous one */
3718 if (prev->base + prev->len == valid_entry->base) {
3719 prev->len += valid_entry->len;
3720 /* If it merge with next one, remove next node */
3722 LIST_REMOVE(valid_entry, next);
3723 rte_free(valid_entry);
3725 rte_free(valid_entry);
3731 /* Not find any entry to merge, insert */
3734 LIST_INSERT_AFTER(prev, valid_entry, next);
3735 else if (next != NULL)
3736 LIST_INSERT_BEFORE(next, valid_entry, next);
3737 else /* It's empty list, insert to head */
3738 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3741 pool->num_free += valid_entry->len;
3742 pool->num_alloc -= valid_entry->len;
3748 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3751 struct pool_entry *entry, *valid_entry;
3753 if (pool == NULL || num == 0) {
3754 PMD_DRV_LOG(ERR, "Invalid parameter");
3758 if (pool->num_free < num) {
3759 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3760 num, pool->num_free);
3765 /* Lookup in free list and find most fit one */
3766 LIST_FOREACH(entry, &pool->free_list, next) {
3767 if (entry->len >= num) {
3769 if (entry->len == num) {
3770 valid_entry = entry;
3773 if (valid_entry == NULL || valid_entry->len > entry->len)
3774 valid_entry = entry;
3778 /* Not find one to satisfy the request, return */
3779 if (valid_entry == NULL) {
3780 PMD_DRV_LOG(ERR, "No valid entry found");
3784 * The entry have equal queue number as requested,
3785 * remove it from alloc_list.
3787 if (valid_entry->len == num) {
3788 LIST_REMOVE(valid_entry, next);
3791 * The entry have more numbers than requested,
3792 * create a new entry for alloc_list and minus its
3793 * queue base and number in free_list.
3795 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3796 if (entry == NULL) {
3797 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3801 entry->base = valid_entry->base;
3803 valid_entry->base += num;
3804 valid_entry->len -= num;
3805 valid_entry = entry;
3808 /* Insert it into alloc list, not sorted */
3809 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3811 pool->num_free -= valid_entry->len;
3812 pool->num_alloc += valid_entry->len;
3814 return valid_entry->base + pool->base;
3818 * bitmap_is_subset - Check whether src2 is subset of src1
3821 bitmap_is_subset(uint8_t src1, uint8_t src2)
3823 return !((src1 ^ src2) & src2);
3826 static enum i40e_status_code
3827 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3829 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3831 /* If DCB is not supported, only default TC is supported */
3832 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3833 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3834 return I40E_NOT_SUPPORTED;
3837 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3838 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3839 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3841 return I40E_NOT_SUPPORTED;
3843 return I40E_SUCCESS;
3847 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3848 struct i40e_vsi_vlan_pvid_info *info)
3851 struct i40e_vsi_context ctxt;
3852 uint8_t vlan_flags = 0;
3855 if (vsi == NULL || info == NULL) {
3856 PMD_DRV_LOG(ERR, "invalid parameters");
3857 return I40E_ERR_PARAM;
3861 vsi->info.pvid = info->config.pvid;
3863 * If insert pvid is enabled, only tagged pkts are
3864 * allowed to be sent out.
3866 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3867 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3870 if (info->config.reject.tagged == 0)
3871 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3873 if (info->config.reject.untagged == 0)
3874 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3876 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3877 I40E_AQ_VSI_PVLAN_MODE_MASK);
3878 vsi->info.port_vlan_flags |= vlan_flags;
3879 vsi->info.valid_sections =
3880 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3881 memset(&ctxt, 0, sizeof(ctxt));
3882 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3883 ctxt.seid = vsi->seid;
3885 hw = I40E_VSI_TO_HW(vsi);
3886 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3887 if (ret != I40E_SUCCESS)
3888 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3894 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3896 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3898 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3900 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3901 if (ret != I40E_SUCCESS)
3905 PMD_DRV_LOG(ERR, "seid not valid");
3909 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3910 tc_bw_data.tc_valid_bits = enabled_tcmap;
3911 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3912 tc_bw_data.tc_bw_credits[i] =
3913 (enabled_tcmap & (1 << i)) ? 1 : 0;
3915 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3916 if (ret != I40E_SUCCESS) {
3917 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3921 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3922 sizeof(vsi->info.qs_handle));
3923 return I40E_SUCCESS;
3926 static enum i40e_status_code
3927 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3928 struct i40e_aqc_vsi_properties_data *info,
3929 uint8_t enabled_tcmap)
3931 enum i40e_status_code ret;
3932 int i, total_tc = 0;
3933 uint16_t qpnum_per_tc, bsf, qp_idx;
3935 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3936 if (ret != I40E_SUCCESS)
3939 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3940 if (enabled_tcmap & (1 << i))
3942 vsi->enabled_tc = enabled_tcmap;
3944 /* Number of queues per enabled TC */
3945 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3946 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3947 bsf = rte_bsf32(qpnum_per_tc);
3949 /* Adjust the queue number to actual queues that can be applied */
3950 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3951 vsi->nb_qps = qpnum_per_tc * total_tc;
3954 * Configure TC and queue mapping parameters, for enabled TC,
3955 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3956 * default queue will serve it.
3959 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3960 if (vsi->enabled_tc & (1 << i)) {
3961 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3962 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3963 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3964 qp_idx += qpnum_per_tc;
3966 info->tc_mapping[i] = 0;
3969 /* Associate queue number with VSI */
3970 if (vsi->type == I40E_VSI_SRIOV) {
3971 info->mapping_flags |=
3972 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3973 for (i = 0; i < vsi->nb_qps; i++)
3974 info->queue_mapping[i] =
3975 rte_cpu_to_le_16(vsi->base_queue + i);
3977 info->mapping_flags |=
3978 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3979 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3981 info->valid_sections |=
3982 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3984 return I40E_SUCCESS;
3988 i40e_veb_release(struct i40e_veb *veb)
3990 struct i40e_vsi *vsi;
3996 if (!TAILQ_EMPTY(&veb->head)) {
3997 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4000 /* associate_vsi field is NULL for floating VEB */
4001 if (veb->associate_vsi != NULL) {
4002 vsi = veb->associate_vsi;
4003 hw = I40E_VSI_TO_HW(vsi);
4005 vsi->uplink_seid = veb->uplink_seid;
4008 veb->associate_pf->main_vsi->floating_veb = NULL;
4009 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4012 i40e_aq_delete_element(hw, veb->seid, NULL);
4014 return I40E_SUCCESS;
4018 static struct i40e_veb *
4019 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4021 struct i40e_veb *veb;
4027 "veb setup failed, associated PF shouldn't null");
4030 hw = I40E_PF_TO_HW(pf);
4032 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4034 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4038 veb->associate_vsi = vsi;
4039 veb->associate_pf = pf;
4040 TAILQ_INIT(&veb->head);
4041 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4043 /* create floating veb if vsi is NULL */
4045 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4046 I40E_DEFAULT_TCMAP, false,
4047 &veb->seid, false, NULL);
4049 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4050 true, &veb->seid, false, NULL);
4053 if (ret != I40E_SUCCESS) {
4054 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4055 hw->aq.asq_last_status);
4059 /* get statistics index */
4060 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4061 &veb->stats_idx, NULL, NULL, NULL);
4062 if (ret != I40E_SUCCESS) {
4063 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4064 hw->aq.asq_last_status);
4067 /* Get VEB bandwidth, to be implemented */
4068 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4070 vsi->uplink_seid = veb->seid;
4079 i40e_vsi_release(struct i40e_vsi *vsi)
4083 struct i40e_vsi_list *vsi_list;
4085 struct i40e_mac_filter *f;
4086 uint16_t user_param = vsi->user_param;
4089 return I40E_SUCCESS;
4091 pf = I40E_VSI_TO_PF(vsi);
4092 hw = I40E_VSI_TO_HW(vsi);
4094 /* VSI has child to attach, release child first */
4096 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
4097 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4099 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
4101 i40e_veb_release(vsi->veb);
4104 if (vsi->floating_veb) {
4105 TAILQ_FOREACH(vsi_list, &vsi->floating_veb->head, list) {
4106 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4108 TAILQ_REMOVE(&vsi->floating_veb->head, vsi_list, list);
4112 /* Remove all macvlan filters of the VSI */
4113 i40e_vsi_remove_all_macvlan_filter(vsi);
4114 TAILQ_FOREACH(f, &vsi->mac_list, next)
4117 if (vsi->type != I40E_VSI_MAIN &&
4118 ((vsi->type != I40E_VSI_SRIOV) ||
4119 !pf->floating_veb_list[user_param])) {
4120 /* Remove vsi from parent's sibling list */
4121 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4122 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4123 return I40E_ERR_PARAM;
4125 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4126 &vsi->sib_vsi_list, list);
4128 /* Remove all switch element of the VSI */
4129 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4130 if (ret != I40E_SUCCESS)
4131 PMD_DRV_LOG(ERR, "Failed to delete element");
4134 if ((vsi->type == I40E_VSI_SRIOV) &&
4135 pf->floating_veb_list[user_param]) {
4136 /* Remove vsi from parent's sibling list */
4137 if (vsi->parent_vsi == NULL ||
4138 vsi->parent_vsi->floating_veb == NULL) {
4139 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4140 return I40E_ERR_PARAM;
4142 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4143 &vsi->sib_vsi_list, list);
4145 /* Remove all switch element of the VSI */
4146 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4147 if (ret != I40E_SUCCESS)
4148 PMD_DRV_LOG(ERR, "Failed to delete element");
4151 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4153 if (vsi->type != I40E_VSI_SRIOV)
4154 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4157 return I40E_SUCCESS;
4161 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4163 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4164 struct i40e_aqc_remove_macvlan_element_data def_filter;
4165 struct i40e_mac_filter_info filter;
4168 if (vsi->type != I40E_VSI_MAIN)
4169 return I40E_ERR_CONFIG;
4170 memset(&def_filter, 0, sizeof(def_filter));
4171 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4173 def_filter.vlan_tag = 0;
4174 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4175 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4176 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4177 if (ret != I40E_SUCCESS) {
4178 struct i40e_mac_filter *f;
4179 struct ether_addr *mac;
4181 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4183 /* It needs to add the permanent mac into mac list */
4184 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4186 PMD_DRV_LOG(ERR, "failed to allocate memory");
4187 return I40E_ERR_NO_MEMORY;
4189 mac = &f->mac_info.mac_addr;
4190 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4192 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4193 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4198 (void)rte_memcpy(&filter.mac_addr,
4199 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4200 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4201 return i40e_vsi_add_mac(vsi, &filter);
4205 * i40e_vsi_get_bw_config - Query VSI BW Information
4206 * @vsi: the VSI to be queried
4208 * Returns 0 on success, negative value on failure
4210 static enum i40e_status_code
4211 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4213 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4214 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4215 struct i40e_hw *hw = &vsi->adapter->hw;
4220 memset(&bw_config, 0, sizeof(bw_config));
4221 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4222 if (ret != I40E_SUCCESS) {
4223 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4224 hw->aq.asq_last_status);
4228 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4229 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4230 &ets_sla_config, NULL);
4231 if (ret != I40E_SUCCESS) {
4232 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4233 "configuration %u", hw->aq.asq_last_status);
4237 /* store and print out BW info */
4238 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4239 vsi->bw_info.bw_max = bw_config.max_bw;
4240 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4241 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4242 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4243 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4245 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4246 vsi->bw_info.bw_ets_share_credits[i] =
4247 ets_sla_config.share_credits[i];
4248 vsi->bw_info.bw_ets_credits[i] =
4249 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4250 /* 4 bits per TC, 4th bit is reserved */
4251 vsi->bw_info.bw_ets_max[i] =
4252 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4253 RTE_LEN2MASK(3, uint8_t));
4254 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4255 vsi->bw_info.bw_ets_share_credits[i]);
4256 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4257 vsi->bw_info.bw_ets_credits[i]);
4258 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4259 vsi->bw_info.bw_ets_max[i]);
4262 return I40E_SUCCESS;
4265 /* i40e_enable_pf_lb
4266 * @pf: pointer to the pf structure
4268 * allow loopback on pf
4271 i40e_enable_pf_lb(struct i40e_pf *pf)
4273 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4274 struct i40e_vsi_context ctxt;
4277 /* Use the FW API if FW >= v5.0 */
4278 if (hw->aq.fw_maj_ver < 5) {
4279 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4283 memset(&ctxt, 0, sizeof(ctxt));
4284 ctxt.seid = pf->main_vsi_seid;
4285 ctxt.pf_num = hw->pf_id;
4286 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4288 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4289 ret, hw->aq.asq_last_status);
4292 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4293 ctxt.info.valid_sections =
4294 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4295 ctxt.info.switch_id |=
4296 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4298 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4300 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4301 hw->aq.asq_last_status);
4306 i40e_vsi_setup(struct i40e_pf *pf,
4307 enum i40e_vsi_type type,
4308 struct i40e_vsi *uplink_vsi,
4309 uint16_t user_param)
4311 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4312 struct i40e_vsi *vsi;
4313 struct i40e_mac_filter_info filter;
4315 struct i40e_vsi_context ctxt;
4316 struct ether_addr broadcast =
4317 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4319 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4320 uplink_vsi == NULL) {
4321 PMD_DRV_LOG(ERR, "VSI setup failed, "
4322 "VSI link shouldn't be NULL");
4326 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4327 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4328 "uplink VSI should be NULL");
4333 * 1.type is not MAIN and uplink vsi is not NULL
4334 * If uplink vsi didn't setup VEB, create one first under veb field
4335 * 2.type is SRIOV and the uplink is NULL
4336 * If floating VEB is NULL, create one veb under floating veb field
4339 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4340 uplink_vsi->veb == NULL) {
4341 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4343 if (uplink_vsi->veb == NULL) {
4344 PMD_DRV_LOG(ERR, "VEB setup failed");
4347 /* set ALLOWLOOPBACk on pf, when veb is created */
4348 i40e_enable_pf_lb(pf);
4351 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4352 pf->main_vsi->floating_veb == NULL) {
4353 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4355 if (pf->main_vsi->floating_veb == NULL) {
4356 PMD_DRV_LOG(ERR, "VEB setup failed");
4361 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4363 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4366 TAILQ_INIT(&vsi->mac_list);
4368 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4369 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4370 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4371 vsi->user_param = user_param;
4372 /* Allocate queues */
4373 switch (vsi->type) {
4374 case I40E_VSI_MAIN :
4375 vsi->nb_qps = pf->lan_nb_qps;
4377 case I40E_VSI_SRIOV :
4378 vsi->nb_qps = pf->vf_nb_qps;
4380 case I40E_VSI_VMDQ2:
4381 vsi->nb_qps = pf->vmdq_nb_qps;
4384 vsi->nb_qps = pf->fdir_nb_qps;
4390 * The filter status descriptor is reported in rx queue 0,
4391 * while the tx queue for fdir filter programming has no
4392 * such constraints, can be non-zero queues.
4393 * To simplify it, choose FDIR vsi use queue 0 pair.
4394 * To make sure it will use queue 0 pair, queue allocation
4395 * need be done before this function is called
4397 if (type != I40E_VSI_FDIR) {
4398 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4400 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4404 vsi->base_queue = ret;
4406 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4408 /* VF has MSIX interrupt in VF range, don't allocate here */
4409 if (type == I40E_VSI_MAIN) {
4410 ret = i40e_res_pool_alloc(&pf->msix_pool,
4411 RTE_MIN(vsi->nb_qps,
4412 RTE_MAX_RXTX_INTR_VEC_ID));
4414 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4416 goto fail_queue_alloc;
4418 vsi->msix_intr = ret;
4419 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4420 } else if (type != I40E_VSI_SRIOV) {
4421 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4423 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4424 goto fail_queue_alloc;
4426 vsi->msix_intr = ret;
4434 if (type == I40E_VSI_MAIN) {
4435 /* For main VSI, no need to add since it's default one */
4436 vsi->uplink_seid = pf->mac_seid;
4437 vsi->seid = pf->main_vsi_seid;
4438 /* Bind queues with specific MSIX interrupt */
4440 * Needs 2 interrupt at least, one for misc cause which will
4441 * enabled from OS side, Another for queues binding the
4442 * interrupt from device side only.
4445 /* Get default VSI parameters from hardware */
4446 memset(&ctxt, 0, sizeof(ctxt));
4447 ctxt.seid = vsi->seid;
4448 ctxt.pf_num = hw->pf_id;
4449 ctxt.uplink_seid = vsi->uplink_seid;
4451 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4452 if (ret != I40E_SUCCESS) {
4453 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4454 goto fail_msix_alloc;
4456 (void)rte_memcpy(&vsi->info, &ctxt.info,
4457 sizeof(struct i40e_aqc_vsi_properties_data));
4458 vsi->vsi_id = ctxt.vsi_number;
4459 vsi->info.valid_sections = 0;
4461 /* Configure tc, enabled TC0 only */
4462 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4464 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4465 goto fail_msix_alloc;
4468 /* TC, queue mapping */
4469 memset(&ctxt, 0, sizeof(ctxt));
4470 vsi->info.valid_sections |=
4471 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4472 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4473 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4474 (void)rte_memcpy(&ctxt.info, &vsi->info,
4475 sizeof(struct i40e_aqc_vsi_properties_data));
4476 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4477 I40E_DEFAULT_TCMAP);
4478 if (ret != I40E_SUCCESS) {
4479 PMD_DRV_LOG(ERR, "Failed to configure "
4480 "TC queue mapping");
4481 goto fail_msix_alloc;
4483 ctxt.seid = vsi->seid;
4484 ctxt.pf_num = hw->pf_id;
4485 ctxt.uplink_seid = vsi->uplink_seid;
4488 /* Update VSI parameters */
4489 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4490 if (ret != I40E_SUCCESS) {
4491 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4492 goto fail_msix_alloc;
4495 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4496 sizeof(vsi->info.tc_mapping));
4497 (void)rte_memcpy(&vsi->info.queue_mapping,
4498 &ctxt.info.queue_mapping,
4499 sizeof(vsi->info.queue_mapping));
4500 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4501 vsi->info.valid_sections = 0;
4503 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4507 * Updating default filter settings are necessary to prevent
4508 * reception of tagged packets.
4509 * Some old firmware configurations load a default macvlan
4510 * filter which accepts both tagged and untagged packets.
4511 * The updating is to use a normal filter instead if needed.
4512 * For NVM 4.2.2 or after, the updating is not needed anymore.
4513 * The firmware with correct configurations load the default
4514 * macvlan filter which is expected and cannot be removed.
4516 i40e_update_default_filter_setting(vsi);
4517 i40e_config_qinq(hw, vsi);
4518 } else if (type == I40E_VSI_SRIOV) {
4519 memset(&ctxt, 0, sizeof(ctxt));
4521 * For other VSI, the uplink_seid equals to uplink VSI's
4522 * uplink_seid since they share same VEB
4524 if (uplink_vsi == NULL)
4525 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4527 vsi->uplink_seid = uplink_vsi->uplink_seid;
4528 ctxt.pf_num = hw->pf_id;
4529 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4530 ctxt.uplink_seid = vsi->uplink_seid;
4531 ctxt.connection_type = 0x1;
4532 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4534 /* Use the VEB configuration if FW >= v5.0 */
4535 if (hw->aq.fw_maj_ver >= 5) {
4536 /* Configure switch ID */
4537 ctxt.info.valid_sections |=
4538 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4539 ctxt.info.switch_id =
4540 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4543 /* Configure port/vlan */
4544 ctxt.info.valid_sections |=
4545 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4546 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4547 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4548 I40E_DEFAULT_TCMAP);
4549 if (ret != I40E_SUCCESS) {
4550 PMD_DRV_LOG(ERR, "Failed to configure "
4551 "TC queue mapping");
4552 goto fail_msix_alloc;
4554 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4555 ctxt.info.valid_sections |=
4556 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4558 * Since VSI is not created yet, only configure parameter,
4559 * will add vsi below.
4562 i40e_config_qinq(hw, vsi);
4563 } else if (type == I40E_VSI_VMDQ2) {
4564 memset(&ctxt, 0, sizeof(ctxt));
4566 * For other VSI, the uplink_seid equals to uplink VSI's
4567 * uplink_seid since they share same VEB
4569 vsi->uplink_seid = uplink_vsi->uplink_seid;
4570 ctxt.pf_num = hw->pf_id;
4572 ctxt.uplink_seid = vsi->uplink_seid;
4573 ctxt.connection_type = 0x1;
4574 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4576 ctxt.info.valid_sections |=
4577 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4578 /* user_param carries flag to enable loop back */
4580 ctxt.info.switch_id =
4581 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4582 ctxt.info.switch_id |=
4583 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4586 /* Configure port/vlan */
4587 ctxt.info.valid_sections |=
4588 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4589 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4590 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4591 I40E_DEFAULT_TCMAP);
4592 if (ret != I40E_SUCCESS) {
4593 PMD_DRV_LOG(ERR, "Failed to configure "
4594 "TC queue mapping");
4595 goto fail_msix_alloc;
4597 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4598 ctxt.info.valid_sections |=
4599 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4600 } else if (type == I40E_VSI_FDIR) {
4601 memset(&ctxt, 0, sizeof(ctxt));
4602 vsi->uplink_seid = uplink_vsi->uplink_seid;
4603 ctxt.pf_num = hw->pf_id;
4605 ctxt.uplink_seid = vsi->uplink_seid;
4606 ctxt.connection_type = 0x1; /* regular data port */
4607 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4608 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4609 I40E_DEFAULT_TCMAP);
4610 if (ret != I40E_SUCCESS) {
4611 PMD_DRV_LOG(ERR, "Failed to configure "
4612 "TC queue mapping.");
4613 goto fail_msix_alloc;
4615 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4616 ctxt.info.valid_sections |=
4617 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4619 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4620 goto fail_msix_alloc;
4623 if (vsi->type != I40E_VSI_MAIN) {
4624 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4625 if (ret != I40E_SUCCESS) {
4626 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4627 hw->aq.asq_last_status);
4628 goto fail_msix_alloc;
4630 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4631 vsi->info.valid_sections = 0;
4632 vsi->seid = ctxt.seid;
4633 vsi->vsi_id = ctxt.vsi_number;
4634 vsi->sib_vsi_list.vsi = vsi;
4635 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4636 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4637 &vsi->sib_vsi_list, list);
4639 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4640 &vsi->sib_vsi_list, list);
4644 /* MAC/VLAN configuration */
4645 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4646 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4648 ret = i40e_vsi_add_mac(vsi, &filter);
4649 if (ret != I40E_SUCCESS) {
4650 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4651 goto fail_msix_alloc;
4654 /* Get VSI BW information */
4655 i40e_vsi_get_bw_config(vsi);
4658 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4660 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4666 /* Configure vlan filter on or off */
4668 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4671 struct i40e_mac_filter *f;
4672 struct i40e_mac_filter_info *mac_filter;
4673 enum rte_mac_filter_type desired_filter;
4674 int ret = I40E_SUCCESS;
4677 /* Filter to match MAC and VLAN */
4678 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4680 /* Filter to match only MAC */
4681 desired_filter = RTE_MAC_PERFECT_MATCH;
4686 mac_filter = rte_zmalloc("mac_filter_info_data",
4687 num * sizeof(*mac_filter), 0);
4688 if (mac_filter == NULL) {
4689 PMD_DRV_LOG(ERR, "failed to allocate memory");
4690 return I40E_ERR_NO_MEMORY;
4695 /* Remove all existing mac */
4696 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4697 mac_filter[i] = f->mac_info;
4698 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4700 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4701 on ? "enable" : "disable");
4707 /* Override with new filter */
4708 for (i = 0; i < num; i++) {
4709 mac_filter[i].filter_type = desired_filter;
4710 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4712 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4713 on ? "enable" : "disable");
4719 rte_free(mac_filter);
4723 /* Configure vlan stripping on or off */
4725 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4727 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4728 struct i40e_vsi_context ctxt;
4730 int ret = I40E_SUCCESS;
4732 /* Check if it has been already on or off */
4733 if (vsi->info.valid_sections &
4734 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4736 if ((vsi->info.port_vlan_flags &
4737 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4738 return 0; /* already on */
4740 if ((vsi->info.port_vlan_flags &
4741 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4742 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4743 return 0; /* already off */
4748 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4750 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4751 vsi->info.valid_sections =
4752 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4753 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4754 vsi->info.port_vlan_flags |= vlan_flags;
4755 ctxt.seid = vsi->seid;
4756 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4757 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4759 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4760 on ? "enable" : "disable");
4766 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4768 struct rte_eth_dev_data *data = dev->data;
4772 /* Apply vlan offload setting */
4773 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4774 i40e_vlan_offload_set(dev, mask);
4776 /* Apply double-vlan setting, not implemented yet */
4778 /* Apply pvid setting */
4779 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4780 data->dev_conf.txmode.hw_vlan_insert_pvid);
4782 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4788 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4790 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4792 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4796 i40e_update_flow_control(struct i40e_hw *hw)
4798 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4799 struct i40e_link_status link_status;
4800 uint32_t rxfc = 0, txfc = 0, reg;
4804 memset(&link_status, 0, sizeof(link_status));
4805 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4806 if (ret != I40E_SUCCESS) {
4807 PMD_DRV_LOG(ERR, "Failed to get link status information");
4808 goto write_reg; /* Disable flow control */
4811 an_info = hw->phy.link_info.an_info;
4812 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4813 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4814 ret = I40E_ERR_NOT_READY;
4815 goto write_reg; /* Disable flow control */
4818 * If link auto negotiation is enabled, flow control needs to
4819 * be configured according to it
4821 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4822 case I40E_LINK_PAUSE_RXTX:
4825 hw->fc.current_mode = I40E_FC_FULL;
4827 case I40E_AQ_LINK_PAUSE_RX:
4829 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4831 case I40E_AQ_LINK_PAUSE_TX:
4833 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4836 hw->fc.current_mode = I40E_FC_NONE;
4841 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4842 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4843 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4844 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4845 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4846 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4853 i40e_pf_setup(struct i40e_pf *pf)
4855 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4856 struct i40e_filter_control_settings settings;
4857 struct i40e_vsi *vsi;
4860 /* Clear all stats counters */
4861 pf->offset_loaded = FALSE;
4862 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4863 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4865 ret = i40e_pf_get_switch_config(pf);
4866 if (ret != I40E_SUCCESS) {
4867 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4870 if (pf->flags & I40E_FLAG_FDIR) {
4871 /* make queue allocated first, let FDIR use queue pair 0*/
4872 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4873 if (ret != I40E_FDIR_QUEUE_ID) {
4874 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4876 pf->flags &= ~I40E_FLAG_FDIR;
4879 /* main VSI setup */
4880 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4882 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4883 return I40E_ERR_NOT_READY;
4887 /* Configure filter control */
4888 memset(&settings, 0, sizeof(settings));
4889 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4890 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4891 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4892 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4894 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4895 hw->func_caps.rss_table_size);
4896 return I40E_ERR_PARAM;
4898 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4899 "size: %u\n", hw->func_caps.rss_table_size);
4900 pf->hash_lut_size = hw->func_caps.rss_table_size;
4902 /* Enable ethtype and macvlan filters */
4903 settings.enable_ethtype = TRUE;
4904 settings.enable_macvlan = TRUE;
4905 ret = i40e_set_filter_control(hw, &settings);
4907 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4910 /* Update flow control according to the auto negotiation */
4911 i40e_update_flow_control(hw);
4913 return I40E_SUCCESS;
4917 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4923 * Set or clear TX Queue Disable flags,
4924 * which is required by hardware.
4926 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4927 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4929 /* Wait until the request is finished */
4930 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4931 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4932 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4933 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4934 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4940 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4941 return I40E_SUCCESS; /* already on, skip next steps */
4943 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4944 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4946 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4947 return I40E_SUCCESS; /* already off, skip next steps */
4948 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4950 /* Write the register */
4951 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4952 /* Check the result */
4953 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4954 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4955 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4957 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4958 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4961 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4962 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4966 /* Check if it is timeout */
4967 if (j >= I40E_CHK_Q_ENA_COUNT) {
4968 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4969 (on ? "enable" : "disable"), q_idx);
4970 return I40E_ERR_TIMEOUT;
4973 return I40E_SUCCESS;
4976 /* Swith on or off the tx queues */
4978 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4980 struct rte_eth_dev_data *dev_data = pf->dev_data;
4981 struct i40e_tx_queue *txq;
4982 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4986 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4987 txq = dev_data->tx_queues[i];
4988 /* Don't operate the queue if not configured or
4989 * if starting only per queue */
4990 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4993 ret = i40e_dev_tx_queue_start(dev, i);
4995 ret = i40e_dev_tx_queue_stop(dev, i);
4996 if ( ret != I40E_SUCCESS)
5000 return I40E_SUCCESS;
5004 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5009 /* Wait until the request is finished */
5010 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5011 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5012 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5013 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5014 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5019 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5020 return I40E_SUCCESS; /* Already on, skip next steps */
5021 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5023 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5024 return I40E_SUCCESS; /* Already off, skip next steps */
5025 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5028 /* Write the register */
5029 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5030 /* Check the result */
5031 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5032 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5033 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5035 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5036 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5039 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5040 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5045 /* Check if it is timeout */
5046 if (j >= I40E_CHK_Q_ENA_COUNT) {
5047 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5048 (on ? "enable" : "disable"), q_idx);
5049 return I40E_ERR_TIMEOUT;
5052 return I40E_SUCCESS;
5054 /* Switch on or off the rx queues */
5056 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5058 struct rte_eth_dev_data *dev_data = pf->dev_data;
5059 struct i40e_rx_queue *rxq;
5060 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5064 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5065 rxq = dev_data->rx_queues[i];
5066 /* Don't operate the queue if not configured or
5067 * if starting only per queue */
5068 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5071 ret = i40e_dev_rx_queue_start(dev, i);
5073 ret = i40e_dev_rx_queue_stop(dev, i);
5074 if (ret != I40E_SUCCESS)
5078 return I40E_SUCCESS;
5081 /* Switch on or off all the rx/tx queues */
5083 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5088 /* enable rx queues before enabling tx queues */
5089 ret = i40e_dev_switch_rx_queues(pf, on);
5091 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5094 ret = i40e_dev_switch_tx_queues(pf, on);
5096 /* Stop tx queues before stopping rx queues */
5097 ret = i40e_dev_switch_tx_queues(pf, on);
5099 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5102 ret = i40e_dev_switch_rx_queues(pf, on);
5108 /* Initialize VSI for TX */
5110 i40e_dev_tx_init(struct i40e_pf *pf)
5112 struct rte_eth_dev_data *data = pf->dev_data;
5114 uint32_t ret = I40E_SUCCESS;
5115 struct i40e_tx_queue *txq;
5117 for (i = 0; i < data->nb_tx_queues; i++) {
5118 txq = data->tx_queues[i];
5119 if (!txq || !txq->q_set)
5121 ret = i40e_tx_queue_init(txq);
5122 if (ret != I40E_SUCCESS)
5125 if (ret == I40E_SUCCESS)
5126 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5132 /* Initialize VSI for RX */
5134 i40e_dev_rx_init(struct i40e_pf *pf)
5136 struct rte_eth_dev_data *data = pf->dev_data;
5137 int ret = I40E_SUCCESS;
5139 struct i40e_rx_queue *rxq;
5141 i40e_pf_config_mq_rx(pf);
5142 for (i = 0; i < data->nb_rx_queues; i++) {
5143 rxq = data->rx_queues[i];
5144 if (!rxq || !rxq->q_set)
5147 ret = i40e_rx_queue_init(rxq);
5148 if (ret != I40E_SUCCESS) {
5149 PMD_DRV_LOG(ERR, "Failed to do RX queue "
5154 if (ret == I40E_SUCCESS)
5155 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5162 i40e_dev_rxtx_init(struct i40e_pf *pf)
5166 err = i40e_dev_tx_init(pf);
5168 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5171 err = i40e_dev_rx_init(pf);
5173 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5181 i40e_vmdq_setup(struct rte_eth_dev *dev)
5183 struct rte_eth_conf *conf = &dev->data->dev_conf;
5184 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5185 int i, err, conf_vsis, j, loop;
5186 struct i40e_vsi *vsi;
5187 struct i40e_vmdq_info *vmdq_info;
5188 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5189 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5192 * Disable interrupt to avoid message from VF. Furthermore, it will
5193 * avoid race condition in VSI creation/destroy.
5195 i40e_pf_disable_irq0(hw);
5197 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5198 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5202 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5203 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5204 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5205 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5206 pf->max_nb_vmdq_vsi);
5210 if (pf->vmdq != NULL) {
5211 PMD_INIT_LOG(INFO, "VMDQ already configured");
5215 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5216 sizeof(*vmdq_info) * conf_vsis, 0);
5218 if (pf->vmdq == NULL) {
5219 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5223 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5225 /* Create VMDQ VSI */
5226 for (i = 0; i < conf_vsis; i++) {
5227 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5228 vmdq_conf->enable_loop_back);
5230 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5234 vmdq_info = &pf->vmdq[i];
5236 vmdq_info->vsi = vsi;
5238 pf->nb_cfg_vmdq_vsi = conf_vsis;
5240 /* Configure Vlan */
5241 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5242 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5243 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5244 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5245 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5246 vmdq_conf->pool_map[i].vlan_id, j);
5248 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5249 vmdq_conf->pool_map[i].vlan_id);
5251 PMD_INIT_LOG(ERR, "Failed to add vlan");
5259 i40e_pf_enable_irq0(hw);
5264 for (i = 0; i < conf_vsis; i++)
5265 if (pf->vmdq[i].vsi == NULL)
5268 i40e_vsi_release(pf->vmdq[i].vsi);
5272 i40e_pf_enable_irq0(hw);
5277 i40e_stat_update_32(struct i40e_hw *hw,
5285 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5289 if (new_data >= *offset)
5290 *stat = (uint64_t)(new_data - *offset);
5292 *stat = (uint64_t)((new_data +
5293 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5297 i40e_stat_update_48(struct i40e_hw *hw,
5306 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5307 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5308 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5313 if (new_data >= *offset)
5314 *stat = new_data - *offset;
5316 *stat = (uint64_t)((new_data +
5317 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5319 *stat &= I40E_48_BIT_MASK;
5324 i40e_pf_disable_irq0(struct i40e_hw *hw)
5326 /* Disable all interrupt types */
5327 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5328 I40E_WRITE_FLUSH(hw);
5333 i40e_pf_enable_irq0(struct i40e_hw *hw)
5335 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5336 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5337 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5338 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5339 I40E_WRITE_FLUSH(hw);
5343 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5345 /* read pending request and disable first */
5346 i40e_pf_disable_irq0(hw);
5347 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5348 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5349 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5352 /* Link no queues with irq0 */
5353 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5354 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5358 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5360 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5361 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5364 uint32_t index, offset, val;
5369 * Try to find which VF trigger a reset, use absolute VF id to access
5370 * since the reg is global register.
5372 for (i = 0; i < pf->vf_num; i++) {
5373 abs_vf_id = hw->func_caps.vf_base_id + i;
5374 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5375 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5376 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5377 /* VFR event occured */
5378 if (val & (0x1 << offset)) {
5381 /* Clear the event first */
5382 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5384 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5386 * Only notify a VF reset event occured,
5387 * don't trigger another SW reset
5389 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5390 if (ret != I40E_SUCCESS)
5391 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5397 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5399 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5400 struct i40e_arq_event_info info;
5401 uint16_t pending, opcode;
5404 info.buf_len = I40E_AQ_BUF_SZ;
5405 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5406 if (!info.msg_buf) {
5407 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5413 ret = i40e_clean_arq_element(hw, &info, &pending);
5415 if (ret != I40E_SUCCESS) {
5416 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5417 "aq_err: %u", hw->aq.asq_last_status);
5420 opcode = rte_le_to_cpu_16(info.desc.opcode);
5423 case i40e_aqc_opc_send_msg_to_pf:
5424 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5425 i40e_pf_host_handle_vf_msg(dev,
5426 rte_le_to_cpu_16(info.desc.retval),
5427 rte_le_to_cpu_32(info.desc.cookie_high),
5428 rte_le_to_cpu_32(info.desc.cookie_low),
5433 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5438 rte_free(info.msg_buf);
5442 * Interrupt handler is registered as the alarm callback for handling LSC
5443 * interrupt in a definite of time, in order to wait the NIC into a stable
5444 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5445 * no need for link down interrupt.
5448 i40e_dev_interrupt_delayed_handler(void *param)
5450 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5451 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5454 /* read interrupt causes again */
5455 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5457 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5458 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5459 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5460 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5461 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5462 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5463 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5464 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5465 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5466 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5467 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5469 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5470 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5471 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5472 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5473 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5475 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5476 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5477 i40e_dev_handle_vfr_event(dev);
5479 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5480 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5481 i40e_dev_handle_aq_msg(dev);
5484 /* handle the link up interrupt in an alarm callback */
5485 i40e_dev_link_update(dev, 0);
5486 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5488 i40e_pf_enable_irq0(hw);
5489 rte_intr_enable(&(dev->pci_dev->intr_handle));
5493 * Interrupt handler triggered by NIC for handling
5494 * specific interrupt.
5497 * Pointer to interrupt handle.
5499 * The address of parameter (struct rte_eth_dev *) regsitered before.
5505 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5508 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5509 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5512 /* Disable interrupt */
5513 i40e_pf_disable_irq0(hw);
5515 /* read out interrupt causes */
5516 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5518 /* No interrupt event indicated */
5519 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5520 PMD_DRV_LOG(INFO, "No interrupt event");
5523 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5524 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5525 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5526 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5527 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5528 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5529 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5530 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5531 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5532 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5533 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5534 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5535 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5536 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5537 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5538 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5540 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5541 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5542 i40e_dev_handle_vfr_event(dev);
5544 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5545 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5546 i40e_dev_handle_aq_msg(dev);
5549 /* Link Status Change interrupt */
5550 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5551 #define I40E_US_PER_SECOND 1000000
5552 struct rte_eth_link link;
5554 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5555 memset(&link, 0, sizeof(link));
5556 rte_i40e_dev_atomic_read_link_status(dev, &link);
5557 i40e_dev_link_update(dev, 0);
5560 * For link up interrupt, it needs to wait 1 second to let the
5561 * hardware be a stable state. Otherwise several consecutive
5562 * interrupts can be observed.
5563 * For link down interrupt, no need to wait.
5565 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5566 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5569 _rte_eth_dev_callback_process(dev,
5570 RTE_ETH_EVENT_INTR_LSC);
5574 /* Enable interrupt */
5575 i40e_pf_enable_irq0(hw);
5576 rte_intr_enable(&(dev->pci_dev->intr_handle));
5580 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5581 struct i40e_macvlan_filter *filter,
5584 int ele_num, ele_buff_size;
5585 int num, actual_num, i;
5587 int ret = I40E_SUCCESS;
5588 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5589 struct i40e_aqc_add_macvlan_element_data *req_list;
5591 if (filter == NULL || total == 0)
5592 return I40E_ERR_PARAM;
5593 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5594 ele_buff_size = hw->aq.asq_buf_size;
5596 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5597 if (req_list == NULL) {
5598 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5599 return I40E_ERR_NO_MEMORY;
5604 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5605 memset(req_list, 0, ele_buff_size);
5607 for (i = 0; i < actual_num; i++) {
5608 (void)rte_memcpy(req_list[i].mac_addr,
5609 &filter[num + i].macaddr, ETH_ADDR_LEN);
5610 req_list[i].vlan_tag =
5611 rte_cpu_to_le_16(filter[num + i].vlan_id);
5613 switch (filter[num + i].filter_type) {
5614 case RTE_MAC_PERFECT_MATCH:
5615 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5616 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5618 case RTE_MACVLAN_PERFECT_MATCH:
5619 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5621 case RTE_MAC_HASH_MATCH:
5622 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5623 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5625 case RTE_MACVLAN_HASH_MATCH:
5626 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5629 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5630 ret = I40E_ERR_PARAM;
5634 req_list[i].queue_number = 0;
5636 req_list[i].flags = rte_cpu_to_le_16(flags);
5639 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5641 if (ret != I40E_SUCCESS) {
5642 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5646 } while (num < total);
5654 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5655 struct i40e_macvlan_filter *filter,
5658 int ele_num, ele_buff_size;
5659 int num, actual_num, i;
5661 int ret = I40E_SUCCESS;
5662 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5663 struct i40e_aqc_remove_macvlan_element_data *req_list;
5665 if (filter == NULL || total == 0)
5666 return I40E_ERR_PARAM;
5668 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5669 ele_buff_size = hw->aq.asq_buf_size;
5671 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5672 if (req_list == NULL) {
5673 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5674 return I40E_ERR_NO_MEMORY;
5679 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5680 memset(req_list, 0, ele_buff_size);
5682 for (i = 0; i < actual_num; i++) {
5683 (void)rte_memcpy(req_list[i].mac_addr,
5684 &filter[num + i].macaddr, ETH_ADDR_LEN);
5685 req_list[i].vlan_tag =
5686 rte_cpu_to_le_16(filter[num + i].vlan_id);
5688 switch (filter[num + i].filter_type) {
5689 case RTE_MAC_PERFECT_MATCH:
5690 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5691 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5693 case RTE_MACVLAN_PERFECT_MATCH:
5694 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5696 case RTE_MAC_HASH_MATCH:
5697 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5698 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5700 case RTE_MACVLAN_HASH_MATCH:
5701 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5704 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5705 ret = I40E_ERR_PARAM;
5708 req_list[i].flags = rte_cpu_to_le_16(flags);
5711 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5713 if (ret != I40E_SUCCESS) {
5714 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5718 } while (num < total);
5725 /* Find out specific MAC filter */
5726 static struct i40e_mac_filter *
5727 i40e_find_mac_filter(struct i40e_vsi *vsi,
5728 struct ether_addr *macaddr)
5730 struct i40e_mac_filter *f;
5732 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5733 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5741 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5744 uint32_t vid_idx, vid_bit;
5746 if (vlan_id > ETH_VLAN_ID_MAX)
5749 vid_idx = I40E_VFTA_IDX(vlan_id);
5750 vid_bit = I40E_VFTA_BIT(vlan_id);
5752 if (vsi->vfta[vid_idx] & vid_bit)
5759 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5760 uint16_t vlan_id, bool on)
5762 uint32_t vid_idx, vid_bit;
5764 if (vlan_id > ETH_VLAN_ID_MAX)
5767 vid_idx = I40E_VFTA_IDX(vlan_id);
5768 vid_bit = I40E_VFTA_BIT(vlan_id);
5771 vsi->vfta[vid_idx] |= vid_bit;
5773 vsi->vfta[vid_idx] &= ~vid_bit;
5777 * Find all vlan options for specific mac addr,
5778 * return with actual vlan found.
5781 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5782 struct i40e_macvlan_filter *mv_f,
5783 int num, struct ether_addr *addr)
5789 * Not to use i40e_find_vlan_filter to decrease the loop time,
5790 * although the code looks complex.
5792 if (num < vsi->vlan_num)
5793 return I40E_ERR_PARAM;
5796 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5798 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5799 if (vsi->vfta[j] & (1 << k)) {
5801 PMD_DRV_LOG(ERR, "vlan number "
5803 return I40E_ERR_PARAM;
5805 (void)rte_memcpy(&mv_f[i].macaddr,
5806 addr, ETH_ADDR_LEN);
5808 j * I40E_UINT32_BIT_SIZE + k;
5814 return I40E_SUCCESS;
5818 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5819 struct i40e_macvlan_filter *mv_f,
5824 struct i40e_mac_filter *f;
5826 if (num < vsi->mac_num)
5827 return I40E_ERR_PARAM;
5829 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5831 PMD_DRV_LOG(ERR, "buffer number not match");
5832 return I40E_ERR_PARAM;
5834 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5836 mv_f[i].vlan_id = vlan;
5837 mv_f[i].filter_type = f->mac_info.filter_type;
5841 return I40E_SUCCESS;
5845 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5848 struct i40e_mac_filter *f;
5849 struct i40e_macvlan_filter *mv_f;
5850 int ret = I40E_SUCCESS;
5852 if (vsi == NULL || vsi->mac_num == 0)
5853 return I40E_ERR_PARAM;
5855 /* Case that no vlan is set */
5856 if (vsi->vlan_num == 0)
5859 num = vsi->mac_num * vsi->vlan_num;
5861 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5863 PMD_DRV_LOG(ERR, "failed to allocate memory");
5864 return I40E_ERR_NO_MEMORY;
5868 if (vsi->vlan_num == 0) {
5869 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5870 (void)rte_memcpy(&mv_f[i].macaddr,
5871 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5872 mv_f[i].vlan_id = 0;
5876 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5877 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5878 vsi->vlan_num, &f->mac_info.mac_addr);
5879 if (ret != I40E_SUCCESS)
5885 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5893 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5895 struct i40e_macvlan_filter *mv_f;
5897 int ret = I40E_SUCCESS;
5899 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5900 return I40E_ERR_PARAM;
5902 /* If it's already set, just return */
5903 if (i40e_find_vlan_filter(vsi,vlan))
5904 return I40E_SUCCESS;
5906 mac_num = vsi->mac_num;
5909 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5910 return I40E_ERR_PARAM;
5913 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5916 PMD_DRV_LOG(ERR, "failed to allocate memory");
5917 return I40E_ERR_NO_MEMORY;
5920 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5922 if (ret != I40E_SUCCESS)
5925 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5927 if (ret != I40E_SUCCESS)
5930 i40e_set_vlan_filter(vsi, vlan, 1);
5940 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5942 struct i40e_macvlan_filter *mv_f;
5944 int ret = I40E_SUCCESS;
5947 * Vlan 0 is the generic filter for untagged packets
5948 * and can't be removed.
5950 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5951 return I40E_ERR_PARAM;
5953 /* If can't find it, just return */
5954 if (!i40e_find_vlan_filter(vsi, vlan))
5955 return I40E_ERR_PARAM;
5957 mac_num = vsi->mac_num;
5960 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5961 return I40E_ERR_PARAM;
5964 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5967 PMD_DRV_LOG(ERR, "failed to allocate memory");
5968 return I40E_ERR_NO_MEMORY;
5971 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5973 if (ret != I40E_SUCCESS)
5976 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5978 if (ret != I40E_SUCCESS)
5981 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5982 if (vsi->vlan_num == 1) {
5983 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5984 if (ret != I40E_SUCCESS)
5987 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5988 if (ret != I40E_SUCCESS)
5992 i40e_set_vlan_filter(vsi, vlan, 0);
6002 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6004 struct i40e_mac_filter *f;
6005 struct i40e_macvlan_filter *mv_f;
6006 int i, vlan_num = 0;
6007 int ret = I40E_SUCCESS;
6009 /* If it's add and we've config it, return */
6010 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6012 return I40E_SUCCESS;
6013 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6014 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6017 * If vlan_num is 0, that's the first time to add mac,
6018 * set mask for vlan_id 0.
6020 if (vsi->vlan_num == 0) {
6021 i40e_set_vlan_filter(vsi, 0, 1);
6024 vlan_num = vsi->vlan_num;
6025 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6026 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6029 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6031 PMD_DRV_LOG(ERR, "failed to allocate memory");
6032 return I40E_ERR_NO_MEMORY;
6035 for (i = 0; i < vlan_num; i++) {
6036 mv_f[i].filter_type = mac_filter->filter_type;
6037 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6041 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6042 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6043 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6044 &mac_filter->mac_addr);
6045 if (ret != I40E_SUCCESS)
6049 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6050 if (ret != I40E_SUCCESS)
6053 /* Add the mac addr into mac list */
6054 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6056 PMD_DRV_LOG(ERR, "failed to allocate memory");
6057 ret = I40E_ERR_NO_MEMORY;
6060 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6062 f->mac_info.filter_type = mac_filter->filter_type;
6063 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6074 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6076 struct i40e_mac_filter *f;
6077 struct i40e_macvlan_filter *mv_f;
6079 enum rte_mac_filter_type filter_type;
6080 int ret = I40E_SUCCESS;
6082 /* Can't find it, return an error */
6083 f = i40e_find_mac_filter(vsi, addr);
6085 return I40E_ERR_PARAM;
6087 vlan_num = vsi->vlan_num;
6088 filter_type = f->mac_info.filter_type;
6089 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6090 filter_type == RTE_MACVLAN_HASH_MATCH) {
6091 if (vlan_num == 0) {
6092 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6093 return I40E_ERR_PARAM;
6095 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6096 filter_type == RTE_MAC_HASH_MATCH)
6099 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6101 PMD_DRV_LOG(ERR, "failed to allocate memory");
6102 return I40E_ERR_NO_MEMORY;
6105 for (i = 0; i < vlan_num; i++) {
6106 mv_f[i].filter_type = filter_type;
6107 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6110 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6111 filter_type == RTE_MACVLAN_HASH_MATCH) {
6112 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6113 if (ret != I40E_SUCCESS)
6117 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6118 if (ret != I40E_SUCCESS)
6121 /* Remove the mac addr into mac list */
6122 TAILQ_REMOVE(&vsi->mac_list, f, next);
6132 /* Configure hash enable flags for RSS */
6134 i40e_config_hena(uint64_t flags)
6141 if (flags & ETH_RSS_FRAG_IPV4)
6142 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6143 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6144 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6145 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6146 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6147 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6148 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6149 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6150 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6151 if (flags & ETH_RSS_FRAG_IPV6)
6152 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6153 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6154 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6155 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6156 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6157 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6158 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6159 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6160 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6161 if (flags & ETH_RSS_L2_PAYLOAD)
6162 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6167 /* Parse the hash enable flags */
6169 i40e_parse_hena(uint64_t flags)
6171 uint64_t rss_hf = 0;
6175 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6176 rss_hf |= ETH_RSS_FRAG_IPV4;
6177 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6178 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6179 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6180 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6181 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6182 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6183 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6184 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6185 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6186 rss_hf |= ETH_RSS_FRAG_IPV6;
6187 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6188 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6189 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6190 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6191 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6192 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6193 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6194 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6195 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6196 rss_hf |= ETH_RSS_L2_PAYLOAD;
6203 i40e_pf_disable_rss(struct i40e_pf *pf)
6205 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6208 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6209 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6210 hena &= ~I40E_RSS_HENA_ALL;
6211 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6212 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6213 I40E_WRITE_FLUSH(hw);
6217 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6219 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6220 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6223 if (!key || key_len == 0) {
6224 PMD_DRV_LOG(DEBUG, "No key to be configured");
6226 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6228 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6232 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6233 struct i40e_aqc_get_set_rss_key_data *key_dw =
6234 (struct i40e_aqc_get_set_rss_key_data *)key;
6236 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6238 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6241 uint32_t *hash_key = (uint32_t *)key;
6244 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6245 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6246 I40E_WRITE_FLUSH(hw);
6253 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6255 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6256 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6259 if (!key || !key_len)
6262 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6263 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6264 (struct i40e_aqc_get_set_rss_key_data *)key);
6266 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6270 uint32_t *key_dw = (uint32_t *)key;
6273 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6274 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6276 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6282 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6284 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6289 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6290 rss_conf->rss_key_len);
6294 rss_hf = rss_conf->rss_hf;
6295 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6296 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6297 hena &= ~I40E_RSS_HENA_ALL;
6298 hena |= i40e_config_hena(rss_hf);
6299 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6300 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6301 I40E_WRITE_FLUSH(hw);
6307 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6308 struct rte_eth_rss_conf *rss_conf)
6310 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6311 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6312 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6315 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6316 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6317 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6318 if (rss_hf != 0) /* Enable RSS */
6320 return 0; /* Nothing to do */
6323 if (rss_hf == 0) /* Disable RSS */
6326 return i40e_hw_rss_hash_set(pf, rss_conf);
6330 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6331 struct rte_eth_rss_conf *rss_conf)
6333 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6334 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6337 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6338 &rss_conf->rss_key_len);
6340 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6341 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6342 rss_conf->rss_hf = i40e_parse_hena(hena);
6348 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6350 switch (filter_type) {
6351 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6352 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6354 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6355 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6357 case RTE_TUNNEL_FILTER_IMAC_TENID:
6358 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6360 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6361 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6363 case ETH_TUNNEL_FILTER_IMAC:
6364 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6366 case ETH_TUNNEL_FILTER_OIP:
6367 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6369 case ETH_TUNNEL_FILTER_IIP:
6370 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6373 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6381 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6382 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6387 uint8_t i, tun_type = 0;
6388 /* internal varialbe to convert ipv6 byte order */
6389 uint32_t convert_ipv6[4];
6391 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6392 struct i40e_vsi *vsi = pf->main_vsi;
6393 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6394 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6396 cld_filter = rte_zmalloc("tunnel_filter",
6397 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6400 if (NULL == cld_filter) {
6401 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6404 pfilter = cld_filter;
6406 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6407 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6409 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6410 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6411 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6412 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6413 rte_memcpy(&pfilter->ipaddr.v4.data,
6414 &rte_cpu_to_le_32(ipv4_addr),
6415 sizeof(pfilter->ipaddr.v4.data));
6417 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6418 for (i = 0; i < 4; i++) {
6420 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6422 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6423 sizeof(pfilter->ipaddr.v6.data));
6426 /* check tunneled type */
6427 switch (tunnel_filter->tunnel_type) {
6428 case RTE_TUNNEL_TYPE_VXLAN:
6429 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6431 case RTE_TUNNEL_TYPE_NVGRE:
6432 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6434 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6435 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6438 /* Other tunnel types is not supported. */
6439 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6440 rte_free(cld_filter);
6444 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6447 rte_free(cld_filter);
6451 pfilter->flags |= rte_cpu_to_le_16(
6452 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6453 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6454 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6455 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6458 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6460 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6463 rte_free(cld_filter);
6468 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6472 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6473 if (pf->vxlan_ports[i] == port)
6481 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6485 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6487 idx = i40e_get_vxlan_port_idx(pf, port);
6489 /* Check if port already exists */
6491 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6495 /* Now check if there is space to add the new port */
6496 idx = i40e_get_vxlan_port_idx(pf, 0);
6498 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6499 "not adding port %d", port);
6503 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6506 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6510 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6513 /* New port: add it and mark its index in the bitmap */
6514 pf->vxlan_ports[idx] = port;
6515 pf->vxlan_bitmap |= (1 << idx);
6517 if (!(pf->flags & I40E_FLAG_VXLAN))
6518 pf->flags |= I40E_FLAG_VXLAN;
6524 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6527 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6529 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6530 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6534 idx = i40e_get_vxlan_port_idx(pf, port);
6537 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6541 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6542 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6546 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6549 pf->vxlan_ports[idx] = 0;
6550 pf->vxlan_bitmap &= ~(1 << idx);
6552 if (!pf->vxlan_bitmap)
6553 pf->flags &= ~I40E_FLAG_VXLAN;
6558 /* Add UDP tunneling port */
6560 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6561 struct rte_eth_udp_tunnel *udp_tunnel)
6564 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6566 if (udp_tunnel == NULL)
6569 switch (udp_tunnel->prot_type) {
6570 case RTE_TUNNEL_TYPE_VXLAN:
6571 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6574 case RTE_TUNNEL_TYPE_GENEVE:
6575 case RTE_TUNNEL_TYPE_TEREDO:
6576 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6581 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6589 /* Remove UDP tunneling port */
6591 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6592 struct rte_eth_udp_tunnel *udp_tunnel)
6595 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6597 if (udp_tunnel == NULL)
6600 switch (udp_tunnel->prot_type) {
6601 case RTE_TUNNEL_TYPE_VXLAN:
6602 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6604 case RTE_TUNNEL_TYPE_GENEVE:
6605 case RTE_TUNNEL_TYPE_TEREDO:
6606 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6610 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6618 /* Calculate the maximum number of contiguous PF queues that are configured */
6620 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6622 struct rte_eth_dev_data *data = pf->dev_data;
6624 struct i40e_rx_queue *rxq;
6627 for (i = 0; i < pf->lan_nb_qps; i++) {
6628 rxq = data->rx_queues[i];
6629 if (rxq && rxq->q_set)
6640 i40e_pf_config_rss(struct i40e_pf *pf)
6642 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6643 struct rte_eth_rss_conf rss_conf;
6644 uint32_t i, lut = 0;
6648 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6649 * It's necessary to calulate the actual PF queues that are configured.
6651 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6652 num = i40e_pf_calc_configured_queues_num(pf);
6654 num = pf->dev_data->nb_rx_queues;
6656 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6657 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6661 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6665 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6668 lut = (lut << 8) | (j & ((0x1 <<
6669 hw->func_caps.rss_table_entry_width) - 1));
6671 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6674 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6675 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6676 i40e_pf_disable_rss(pf);
6679 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6680 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6681 /* Random default keys */
6682 static uint32_t rss_key_default[] = {0x6b793944,
6683 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6684 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6685 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6687 rss_conf.rss_key = (uint8_t *)rss_key_default;
6688 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6692 return i40e_hw_rss_hash_set(pf, &rss_conf);
6696 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6697 struct rte_eth_tunnel_filter_conf *filter)
6699 if (pf == NULL || filter == NULL) {
6700 PMD_DRV_LOG(ERR, "Invalid parameter");
6704 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6705 PMD_DRV_LOG(ERR, "Invalid queue ID");
6709 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6710 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6714 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6715 (is_zero_ether_addr(&filter->outer_mac))) {
6716 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6720 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6721 (is_zero_ether_addr(&filter->inner_mac))) {
6722 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6729 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6730 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6732 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6737 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6738 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6741 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6742 } else if (len == 4) {
6743 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6745 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6750 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6757 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6758 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6764 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6771 switch (cfg->cfg_type) {
6772 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6773 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6776 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6784 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6785 enum rte_filter_op filter_op,
6788 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6789 int ret = I40E_ERR_PARAM;
6791 switch (filter_op) {
6792 case RTE_ETH_FILTER_SET:
6793 ret = i40e_dev_global_config_set(hw,
6794 (struct rte_eth_global_cfg *)arg);
6797 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6805 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6806 enum rte_filter_op filter_op,
6809 struct rte_eth_tunnel_filter_conf *filter;
6810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6811 int ret = I40E_SUCCESS;
6813 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6815 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6816 return I40E_ERR_PARAM;
6818 switch (filter_op) {
6819 case RTE_ETH_FILTER_NOP:
6820 if (!(pf->flags & I40E_FLAG_VXLAN))
6821 ret = I40E_NOT_SUPPORTED;
6823 case RTE_ETH_FILTER_ADD:
6824 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6826 case RTE_ETH_FILTER_DELETE:
6827 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6830 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6831 ret = I40E_ERR_PARAM;
6839 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6842 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6845 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6846 ret = i40e_pf_config_rss(pf);
6848 i40e_pf_disable_rss(pf);
6853 /* Get the symmetric hash enable configurations per port */
6855 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6857 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6859 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6862 /* Set the symmetric hash enable configurations per port */
6864 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6866 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6869 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6870 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6874 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6876 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6877 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6881 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6883 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6884 I40E_WRITE_FLUSH(hw);
6888 * Get global configurations of hash function type and symmetric hash enable
6889 * per flow type (pctype). Note that global configuration means it affects all
6890 * the ports on the same NIC.
6893 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6894 struct rte_eth_hash_global_conf *g_cfg)
6896 uint32_t reg, mask = I40E_FLOW_TYPES;
6898 enum i40e_filter_pctype pctype;
6900 memset(g_cfg, 0, sizeof(*g_cfg));
6901 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6902 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6903 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6905 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6906 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6907 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6909 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6910 if (!(mask & (1UL << i)))
6912 mask &= ~(1UL << i);
6913 /* Bit set indicats the coresponding flow type is supported */
6914 g_cfg->valid_bit_mask[0] |= (1UL << i);
6915 pctype = i40e_flowtype_to_pctype(i);
6916 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6917 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6918 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6925 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6928 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6930 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6931 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6932 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6933 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6939 * As i40e supports less than 32 flow types, only first 32 bits need to
6942 mask0 = g_cfg->valid_bit_mask[0];
6943 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6945 /* Check if any unsupported flow type configured */
6946 if ((mask0 | i40e_mask) ^ i40e_mask)
6949 if (g_cfg->valid_bit_mask[i])
6957 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6963 * Set global configurations of hash function type and symmetric hash enable
6964 * per flow type (pctype). Note any modifying global configuration will affect
6965 * all the ports on the same NIC.
6968 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6969 struct rte_eth_hash_global_conf *g_cfg)
6974 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6975 enum i40e_filter_pctype pctype;
6977 /* Check the input parameters */
6978 ret = i40e_hash_global_config_check(g_cfg);
6982 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6983 if (!(mask0 & (1UL << i)))
6985 mask0 &= ~(1UL << i);
6986 pctype = i40e_flowtype_to_pctype(i);
6987 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6988 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6989 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6992 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6993 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6995 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6996 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7000 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7001 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7003 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7004 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7008 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7010 /* Use the default, and keep it as it is */
7013 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7016 I40E_WRITE_FLUSH(hw);
7022 * Valid input sets for hash and flow director filters per PCTYPE
7025 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7026 enum rte_filter_type filter)
7030 static const uint64_t valid_hash_inset_table[] = {
7031 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7032 I40E_INSET_DMAC | I40E_INSET_SMAC |
7033 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7034 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7035 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7036 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7037 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7038 I40E_INSET_FLEX_PAYLOAD,
7039 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7040 I40E_INSET_DMAC | I40E_INSET_SMAC |
7041 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7042 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7043 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7044 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7045 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7046 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7047 I40E_INSET_FLEX_PAYLOAD,
7048 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7049 I40E_INSET_DMAC | I40E_INSET_SMAC |
7050 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7051 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7052 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7053 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7054 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7055 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7056 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7057 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7058 I40E_INSET_DMAC | I40E_INSET_SMAC |
7059 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7060 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7061 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7062 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7063 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7064 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7065 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7066 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7067 I40E_INSET_DMAC | I40E_INSET_SMAC |
7068 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7069 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7070 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7071 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7072 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7073 I40E_INSET_FLEX_PAYLOAD,
7074 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7075 I40E_INSET_DMAC | I40E_INSET_SMAC |
7076 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7077 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7078 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7079 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7080 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7081 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7082 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7083 I40E_INSET_DMAC | I40E_INSET_SMAC |
7084 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7085 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7086 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7087 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7088 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7089 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7090 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7091 I40E_INSET_DMAC | I40E_INSET_SMAC |
7092 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7093 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7094 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7095 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7096 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7097 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7098 I40E_INSET_FLEX_PAYLOAD,
7099 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7100 I40E_INSET_DMAC | I40E_INSET_SMAC |
7101 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7102 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7103 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7104 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7105 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7106 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7107 I40E_INSET_FLEX_PAYLOAD,
7108 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7109 I40E_INSET_DMAC | I40E_INSET_SMAC |
7110 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7111 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7112 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7113 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7114 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7115 I40E_INSET_FLEX_PAYLOAD,
7116 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7117 I40E_INSET_DMAC | I40E_INSET_SMAC |
7118 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7119 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7120 I40E_INSET_FLEX_PAYLOAD,
7124 * Flow director supports only fields defined in
7125 * union rte_eth_fdir_flow.
7127 static const uint64_t valid_fdir_inset_table[] = {
7128 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7129 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7130 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7131 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7132 I40E_INSET_IPV4_TTL,
7133 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7134 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7135 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7136 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7137 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7138 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7139 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7140 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7141 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7142 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7143 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7144 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7145 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7146 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7147 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7149 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7150 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7151 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7152 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7153 I40E_INSET_IPV4_TTL,
7154 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7155 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7156 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7157 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7158 I40E_INSET_IPV6_HOP_LIMIT,
7159 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7160 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7161 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7162 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7163 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7164 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7165 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7166 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7167 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7168 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7169 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7170 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7171 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7172 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7173 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7175 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7176 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7177 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7178 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7179 I40E_INSET_IPV6_HOP_LIMIT,
7180 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7181 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7182 I40E_INSET_LAST_ETHER_TYPE,
7185 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7187 if (filter == RTE_ETH_FILTER_HASH)
7188 valid = valid_hash_inset_table[pctype];
7190 valid = valid_fdir_inset_table[pctype];
7196 * Validate if the input set is allowed for a specific PCTYPE
7199 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7200 enum rte_filter_type filter, uint64_t inset)
7204 valid = i40e_get_valid_input_set(pctype, filter);
7205 if (inset & (~valid))
7211 /* default input set fields combination per pctype */
7213 i40e_get_default_input_set(uint16_t pctype)
7215 static const uint64_t default_inset_table[] = {
7216 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7217 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7218 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7219 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7220 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7221 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7222 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7223 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7224 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7225 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7226 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7228 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7229 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7230 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7231 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7232 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7233 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7234 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7235 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7236 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7237 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7238 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7239 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7240 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7242 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7243 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7244 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7245 I40E_INSET_LAST_ETHER_TYPE,
7248 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7251 return default_inset_table[pctype];
7255 * Parse the input set from index to logical bit masks
7258 i40e_parse_input_set(uint64_t *inset,
7259 enum i40e_filter_pctype pctype,
7260 enum rte_eth_input_set_field *field,
7266 static const struct {
7267 enum rte_eth_input_set_field field;
7269 } inset_convert_table[] = {
7270 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7271 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7272 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7273 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7274 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7275 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7276 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7277 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7278 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7279 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7280 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7281 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7282 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7283 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7284 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7285 I40E_INSET_IPV6_NEXT_HDR},
7286 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7287 I40E_INSET_IPV6_HOP_LIMIT},
7288 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7289 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7290 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7291 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7292 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7293 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7294 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7295 I40E_INSET_SCTP_VT},
7296 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7297 I40E_INSET_TUNNEL_DMAC},
7298 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7299 I40E_INSET_VLAN_TUNNEL},
7300 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7301 I40E_INSET_TUNNEL_ID},
7302 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7303 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7304 I40E_INSET_FLEX_PAYLOAD_W1},
7305 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7306 I40E_INSET_FLEX_PAYLOAD_W2},
7307 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7308 I40E_INSET_FLEX_PAYLOAD_W3},
7309 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7310 I40E_INSET_FLEX_PAYLOAD_W4},
7311 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7312 I40E_INSET_FLEX_PAYLOAD_W5},
7313 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7314 I40E_INSET_FLEX_PAYLOAD_W6},
7315 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7316 I40E_INSET_FLEX_PAYLOAD_W7},
7317 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7318 I40E_INSET_FLEX_PAYLOAD_W8},
7321 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7324 /* Only one item allowed for default or all */
7326 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7327 *inset = i40e_get_default_input_set(pctype);
7329 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7330 *inset = I40E_INSET_NONE;
7335 for (i = 0, *inset = 0; i < size; i++) {
7336 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7337 if (field[i] == inset_convert_table[j].field) {
7338 *inset |= inset_convert_table[j].inset;
7343 /* It contains unsupported input set, return immediately */
7344 if (j == RTE_DIM(inset_convert_table))
7352 * Translate the input set from bit masks to register aware bit masks
7356 i40e_translate_input_set_reg(uint64_t input)
7361 static const struct {
7365 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7366 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7367 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7368 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7369 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7370 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7371 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7372 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7373 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7374 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7375 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7376 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7377 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7378 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7379 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7380 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7381 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7382 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7383 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7384 {I40E_INSET_TUNNEL_DMAC,
7385 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7386 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7387 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7388 {I40E_INSET_TUNNEL_SRC_PORT,
7389 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7390 {I40E_INSET_TUNNEL_DST_PORT,
7391 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7392 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7393 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7394 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7395 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7396 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7397 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7398 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7399 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7400 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7406 /* Translate input set to register aware inset */
7407 for (i = 0; i < RTE_DIM(inset_map); i++) {
7408 if (input & inset_map[i].inset)
7409 val |= inset_map[i].inset_reg;
7416 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7419 uint64_t inset_need_mask = inset;
7421 static const struct {
7424 } inset_mask_map[] = {
7425 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7426 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7427 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7428 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7429 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7430 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7431 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7432 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7435 if (!inset || !mask || !nb_elem)
7438 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7439 /* Clear the inset bit, if no MASK is required,
7440 * for example proto + ttl
7442 if ((inset & inset_mask_map[i].inset) ==
7443 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7444 inset_need_mask &= ~inset_mask_map[i].inset;
7445 if (!inset_need_mask)
7448 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7449 if ((inset_need_mask & inset_mask_map[i].inset) ==
7450 inset_mask_map[i].inset) {
7451 if (idx >= nb_elem) {
7452 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7455 mask[idx] = inset_mask_map[i].mask;
7464 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7466 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7468 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7470 i40e_write_rx_ctl(hw, addr, val);
7471 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7472 (uint32_t)i40e_read_rx_ctl(hw, addr));
7476 i40e_filter_input_set_init(struct i40e_pf *pf)
7478 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7479 enum i40e_filter_pctype pctype;
7480 uint64_t input_set, inset_reg;
7481 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7484 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7485 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7486 if (!I40E_VALID_PCTYPE(pctype))
7488 input_set = i40e_get_default_input_set(pctype);
7490 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7491 I40E_INSET_MASK_NUM_REG);
7494 inset_reg = i40e_translate_input_set_reg(input_set);
7496 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7497 (uint32_t)(inset_reg & UINT32_MAX));
7498 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7499 (uint32_t)((inset_reg >>
7500 I40E_32_BIT_WIDTH) & UINT32_MAX));
7501 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7502 (uint32_t)(inset_reg & UINT32_MAX));
7503 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7504 (uint32_t)((inset_reg >>
7505 I40E_32_BIT_WIDTH) & UINT32_MAX));
7507 for (i = 0; i < num; i++) {
7508 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7510 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7513 /*clear unused mask registers of the pctype */
7514 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7515 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7517 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7520 I40E_WRITE_FLUSH(hw);
7522 /* store the default input set */
7523 pf->hash_input_set[pctype] = input_set;
7524 pf->fdir.input_set[pctype] = input_set;
7529 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7530 struct rte_eth_input_set_conf *conf)
7532 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7533 enum i40e_filter_pctype pctype;
7534 uint64_t input_set, inset_reg = 0;
7535 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7539 PMD_DRV_LOG(ERR, "Invalid pointer");
7542 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7543 conf->op != RTE_ETH_INPUT_SET_ADD) {
7544 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7548 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7549 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7550 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7555 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7558 PMD_DRV_LOG(ERR, "Failed to parse input set");
7561 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7563 PMD_DRV_LOG(ERR, "Invalid input set");
7566 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7567 /* get inset value in register */
7568 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7569 inset_reg <<= I40E_32_BIT_WIDTH;
7570 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7571 input_set |= pf->hash_input_set[pctype];
7573 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7574 I40E_INSET_MASK_NUM_REG);
7578 inset_reg |= i40e_translate_input_set_reg(input_set);
7580 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7581 (uint32_t)(inset_reg & UINT32_MAX));
7582 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7583 (uint32_t)((inset_reg >>
7584 I40E_32_BIT_WIDTH) & UINT32_MAX));
7586 for (i = 0; i < num; i++)
7587 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7589 /*clear unused mask registers of the pctype */
7590 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7591 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7593 I40E_WRITE_FLUSH(hw);
7595 pf->hash_input_set[pctype] = input_set;
7600 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7601 struct rte_eth_input_set_conf *conf)
7603 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7604 enum i40e_filter_pctype pctype;
7605 uint64_t input_set, inset_reg = 0;
7606 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7610 PMD_DRV_LOG(ERR, "Invalid pointer");
7613 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7614 conf->op != RTE_ETH_INPUT_SET_ADD) {
7615 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7619 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7620 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7621 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7625 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7628 PMD_DRV_LOG(ERR, "Failed to parse input set");
7631 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7633 PMD_DRV_LOG(ERR, "Invalid input set");
7637 /* get inset value in register */
7638 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7639 inset_reg <<= I40E_32_BIT_WIDTH;
7640 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7642 /* Can not change the inset reg for flex payload for fdir,
7643 * it is done by writing I40E_PRTQF_FD_FLXINSET
7644 * in i40e_set_flex_mask_on_pctype.
7646 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7647 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7649 input_set |= pf->fdir.input_set[pctype];
7650 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7651 I40E_INSET_MASK_NUM_REG);
7655 inset_reg |= i40e_translate_input_set_reg(input_set);
7657 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7658 (uint32_t)(inset_reg & UINT32_MAX));
7659 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7660 (uint32_t)((inset_reg >>
7661 I40E_32_BIT_WIDTH) & UINT32_MAX));
7663 for (i = 0; i < num; i++)
7664 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7666 /*clear unused mask registers of the pctype */
7667 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7668 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7670 I40E_WRITE_FLUSH(hw);
7672 pf->fdir.input_set[pctype] = input_set;
7677 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7682 PMD_DRV_LOG(ERR, "Invalid pointer");
7686 switch (info->info_type) {
7687 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7688 i40e_get_symmetric_hash_enable_per_port(hw,
7689 &(info->info.enable));
7691 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7692 ret = i40e_get_hash_filter_global_config(hw,
7693 &(info->info.global_conf));
7696 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7706 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7711 PMD_DRV_LOG(ERR, "Invalid pointer");
7715 switch (info->info_type) {
7716 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7717 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7719 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7720 ret = i40e_set_hash_filter_global_config(hw,
7721 &(info->info.global_conf));
7723 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7724 ret = i40e_hash_filter_inset_select(hw,
7725 &(info->info.input_set_conf));
7729 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7738 /* Operations for hash function */
7740 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7741 enum rte_filter_op filter_op,
7744 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7747 switch (filter_op) {
7748 case RTE_ETH_FILTER_NOP:
7750 case RTE_ETH_FILTER_GET:
7751 ret = i40e_hash_filter_get(hw,
7752 (struct rte_eth_hash_filter_info *)arg);
7754 case RTE_ETH_FILTER_SET:
7755 ret = i40e_hash_filter_set(hw,
7756 (struct rte_eth_hash_filter_info *)arg);
7759 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7769 * Configure ethertype filter, which can director packet by filtering
7770 * with mac address and ether_type or only ether_type
7773 i40e_ethertype_filter_set(struct i40e_pf *pf,
7774 struct rte_eth_ethertype_filter *filter,
7777 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7778 struct i40e_control_filter_stats stats;
7782 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7783 PMD_DRV_LOG(ERR, "Invalid queue ID");
7786 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7787 filter->ether_type == ETHER_TYPE_IPv6) {
7788 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7789 " control packet filter.", filter->ether_type);
7792 if (filter->ether_type == ETHER_TYPE_VLAN)
7793 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7796 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7797 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7798 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7799 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7800 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7802 memset(&stats, 0, sizeof(stats));
7803 ret = i40e_aq_add_rem_control_packet_filter(hw,
7804 filter->mac_addr.addr_bytes,
7805 filter->ether_type, flags,
7807 filter->queue, add, &stats, NULL);
7809 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7810 " mac_etype_used = %u, etype_used = %u,"
7811 " mac_etype_free = %u, etype_free = %u\n",
7812 ret, stats.mac_etype_used, stats.etype_used,
7813 stats.mac_etype_free, stats.etype_free);
7820 * Handle operations for ethertype filter.
7823 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7824 enum rte_filter_op filter_op,
7827 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7830 if (filter_op == RTE_ETH_FILTER_NOP)
7834 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7839 switch (filter_op) {
7840 case RTE_ETH_FILTER_ADD:
7841 ret = i40e_ethertype_filter_set(pf,
7842 (struct rte_eth_ethertype_filter *)arg,
7845 case RTE_ETH_FILTER_DELETE:
7846 ret = i40e_ethertype_filter_set(pf,
7847 (struct rte_eth_ethertype_filter *)arg,
7851 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7859 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7860 enum rte_filter_type filter_type,
7861 enum rte_filter_op filter_op,
7869 switch (filter_type) {
7870 case RTE_ETH_FILTER_NONE:
7871 /* For global configuration */
7872 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7874 case RTE_ETH_FILTER_HASH:
7875 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7877 case RTE_ETH_FILTER_MACVLAN:
7878 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7880 case RTE_ETH_FILTER_ETHERTYPE:
7881 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7883 case RTE_ETH_FILTER_TUNNEL:
7884 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7886 case RTE_ETH_FILTER_FDIR:
7887 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7890 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7900 * Check and enable Extended Tag.
7901 * Enabling Extended Tag is important for 40G performance.
7904 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7909 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7912 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7916 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7917 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7922 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7925 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7929 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7930 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7933 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7934 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7937 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7944 * As some registers wouldn't be reset unless a global hardware reset,
7945 * hardware initialization is needed to put those registers into an
7946 * expected initial state.
7949 i40e_hw_init(struct rte_eth_dev *dev)
7951 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7953 i40e_enable_extended_tag(dev);
7955 /* clear the PF Queue Filter control register */
7956 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7958 /* Disable symmetric hash per port */
7959 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7962 enum i40e_filter_pctype
7963 i40e_flowtype_to_pctype(uint16_t flow_type)
7965 static const enum i40e_filter_pctype pctype_table[] = {
7966 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7967 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7968 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7969 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7970 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7971 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7972 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7973 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7974 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7975 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7976 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7977 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7978 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7979 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7980 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7981 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7982 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7983 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7984 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7987 return pctype_table[flow_type];
7991 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7993 static const uint16_t flowtype_table[] = {
7994 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7995 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7996 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7997 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7998 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7999 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8000 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8001 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8002 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8003 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8004 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8005 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8006 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8007 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8008 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8009 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8010 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8011 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8012 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8015 return flowtype_table[pctype];
8019 * On X710, performance number is far from the expectation on recent firmware
8020 * versions; on XL710, performance number is also far from the expectation on
8021 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8022 * mode is enabled and port MAC address is equal to the packet destination MAC
8023 * address. The fix for this issue may not be integrated in the following
8024 * firmware version. So the workaround in software driver is needed. It needs
8025 * to modify the initial values of 3 internal only registers for both X710 and
8026 * XL710. Note that the values for X710 or XL710 could be different, and the
8027 * workaround can be removed when it is fixed in firmware in the future.
8030 /* For both X710 and XL710 */
8031 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8032 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8034 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8035 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8038 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8040 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8041 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8044 i40e_configure_registers(struct i40e_hw *hw)
8050 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8051 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8052 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8058 for (i = 0; i < RTE_DIM(reg_table); i++) {
8059 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8060 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8062 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8065 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8068 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8071 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8075 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8076 reg_table[i].addr, reg);
8077 if (reg == reg_table[i].val)
8080 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8081 reg_table[i].val, NULL);
8083 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8084 "address of 0x%"PRIx32, reg_table[i].val,
8088 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8089 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8093 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8094 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8095 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8096 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8098 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8103 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8104 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8108 /* Configure for double VLAN RX stripping */
8109 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8110 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8111 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8112 ret = i40e_aq_debug_write_register(hw,
8113 I40E_VSI_TSR(vsi->vsi_id),
8116 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8118 return I40E_ERR_CONFIG;
8122 /* Configure for double VLAN TX insertion */
8123 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8124 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8125 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8126 ret = i40e_aq_debug_write_register(hw,
8127 I40E_VSI_L2TAGSTXVALID(
8128 vsi->vsi_id), reg, NULL);
8130 PMD_DRV_LOG(ERR, "Failed to update "
8131 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8132 return I40E_ERR_CONFIG;
8140 * i40e_aq_add_mirror_rule
8141 * @hw: pointer to the hardware structure
8142 * @seid: VEB seid to add mirror rule to
8143 * @dst_id: destination vsi seid
8144 * @entries: Buffer which contains the entities to be mirrored
8145 * @count: number of entities contained in the buffer
8146 * @rule_id:the rule_id of the rule to be added
8148 * Add a mirror rule for a given veb.
8151 static enum i40e_status_code
8152 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8153 uint16_t seid, uint16_t dst_id,
8154 uint16_t rule_type, uint16_t *entries,
8155 uint16_t count, uint16_t *rule_id)
8157 struct i40e_aq_desc desc;
8158 struct i40e_aqc_add_delete_mirror_rule cmd;
8159 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8160 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8163 enum i40e_status_code status;
8165 i40e_fill_default_direct_cmd_desc(&desc,
8166 i40e_aqc_opc_add_mirror_rule);
8167 memset(&cmd, 0, sizeof(cmd));
8169 buff_len = sizeof(uint16_t) * count;
8170 desc.datalen = rte_cpu_to_le_16(buff_len);
8172 desc.flags |= rte_cpu_to_le_16(
8173 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8174 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8175 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8176 cmd.num_entries = rte_cpu_to_le_16(count);
8177 cmd.seid = rte_cpu_to_le_16(seid);
8178 cmd.destination = rte_cpu_to_le_16(dst_id);
8180 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8181 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8182 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8184 " mirror_rules_used = %u, mirror_rules_free = %u,",
8185 hw->aq.asq_last_status, resp->rule_id,
8186 resp->mirror_rules_used, resp->mirror_rules_free);
8187 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8193 * i40e_aq_del_mirror_rule
8194 * @hw: pointer to the hardware structure
8195 * @seid: VEB seid to add mirror rule to
8196 * @entries: Buffer which contains the entities to be mirrored
8197 * @count: number of entities contained in the buffer
8198 * @rule_id:the rule_id of the rule to be delete
8200 * Delete a mirror rule for a given veb.
8203 static enum i40e_status_code
8204 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8205 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8206 uint16_t count, uint16_t rule_id)
8208 struct i40e_aq_desc desc;
8209 struct i40e_aqc_add_delete_mirror_rule cmd;
8210 uint16_t buff_len = 0;
8211 enum i40e_status_code status;
8214 i40e_fill_default_direct_cmd_desc(&desc,
8215 i40e_aqc_opc_delete_mirror_rule);
8216 memset(&cmd, 0, sizeof(cmd));
8217 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8218 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8220 cmd.num_entries = count;
8221 buff_len = sizeof(uint16_t) * count;
8222 desc.datalen = rte_cpu_to_le_16(buff_len);
8223 buff = (void *)entries;
8225 /* rule id is filled in destination field for deleting mirror rule */
8226 cmd.destination = rte_cpu_to_le_16(rule_id);
8228 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8229 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8230 cmd.seid = rte_cpu_to_le_16(seid);
8232 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8233 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8239 * i40e_mirror_rule_set
8240 * @dev: pointer to the hardware structure
8241 * @mirror_conf: mirror rule info
8242 * @sw_id: mirror rule's sw_id
8243 * @on: enable/disable
8245 * set a mirror rule.
8249 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8250 struct rte_eth_mirror_conf *mirror_conf,
8251 uint8_t sw_id, uint8_t on)
8253 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8254 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8255 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8256 struct i40e_mirror_rule *parent = NULL;
8257 uint16_t seid, dst_seid, rule_id;
8261 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8263 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8264 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8265 " without veb or vfs.");
8268 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8269 PMD_DRV_LOG(ERR, "mirror table is full.");
8272 if (mirror_conf->dst_pool > pf->vf_num) {
8273 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8274 mirror_conf->dst_pool);
8278 seid = pf->main_vsi->veb->seid;
8280 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8281 if (sw_id <= it->index) {
8287 if (mirr_rule && sw_id == mirr_rule->index) {
8289 PMD_DRV_LOG(ERR, "mirror rule exists.");
8292 ret = i40e_aq_del_mirror_rule(hw, seid,
8293 mirr_rule->rule_type,
8295 mirr_rule->num_entries, mirr_rule->id);
8297 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8298 " ret = %d, aq_err = %d.",
8299 ret, hw->aq.asq_last_status);
8302 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8303 rte_free(mirr_rule);
8304 pf->nb_mirror_rule--;
8308 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8312 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8313 sizeof(struct i40e_mirror_rule) , 0);
8315 PMD_DRV_LOG(ERR, "failed to allocate memory");
8316 return I40E_ERR_NO_MEMORY;
8318 switch (mirror_conf->rule_type) {
8319 case ETH_MIRROR_VLAN:
8320 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8321 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8322 mirr_rule->entries[j] =
8323 mirror_conf->vlan.vlan_id[i];
8328 PMD_DRV_LOG(ERR, "vlan is not specified.");
8329 rte_free(mirr_rule);
8332 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8334 case ETH_MIRROR_VIRTUAL_POOL_UP:
8335 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8336 /* check if the specified pool bit is out of range */
8337 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8338 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8339 rte_free(mirr_rule);
8342 for (i = 0, j = 0; i < pf->vf_num; i++) {
8343 if (mirror_conf->pool_mask & (1ULL << i)) {
8344 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8348 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8349 /* add pf vsi to entries */
8350 mirr_rule->entries[j] = pf->main_vsi_seid;
8354 PMD_DRV_LOG(ERR, "pool is not specified.");
8355 rte_free(mirr_rule);
8358 /* egress and ingress in aq commands means from switch but not port */
8359 mirr_rule->rule_type =
8360 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8361 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8362 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8364 case ETH_MIRROR_UPLINK_PORT:
8365 /* egress and ingress in aq commands means from switch but not port*/
8366 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8368 case ETH_MIRROR_DOWNLINK_PORT:
8369 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8372 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8373 mirror_conf->rule_type);
8374 rte_free(mirr_rule);
8378 /* If the dst_pool is equal to vf_num, consider it as PF */
8379 if (mirror_conf->dst_pool == pf->vf_num)
8380 dst_seid = pf->main_vsi_seid;
8382 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8384 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8385 mirr_rule->rule_type, mirr_rule->entries,
8388 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8389 " ret = %d, aq_err = %d.",
8390 ret, hw->aq.asq_last_status);
8391 rte_free(mirr_rule);
8395 mirr_rule->index = sw_id;
8396 mirr_rule->num_entries = j;
8397 mirr_rule->id = rule_id;
8398 mirr_rule->dst_vsi_seid = dst_seid;
8401 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8403 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8405 pf->nb_mirror_rule++;
8410 * i40e_mirror_rule_reset
8411 * @dev: pointer to the device
8412 * @sw_id: mirror rule's sw_id
8414 * reset a mirror rule.
8418 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8420 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8421 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8422 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8426 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8428 seid = pf->main_vsi->veb->seid;
8430 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8431 if (sw_id == it->index) {
8437 ret = i40e_aq_del_mirror_rule(hw, seid,
8438 mirr_rule->rule_type,
8440 mirr_rule->num_entries, mirr_rule->id);
8442 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8443 " status = %d, aq_err = %d.",
8444 ret, hw->aq.asq_last_status);
8447 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8448 rte_free(mirr_rule);
8449 pf->nb_mirror_rule--;
8451 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8458 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8460 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8461 uint64_t systim_cycles;
8463 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8464 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8467 return systim_cycles;
8471 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8473 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8476 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8477 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8484 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8486 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8489 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8490 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8497 i40e_start_timecounters(struct rte_eth_dev *dev)
8499 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8500 struct i40e_adapter *adapter =
8501 (struct i40e_adapter *)dev->data->dev_private;
8502 struct rte_eth_link link;
8503 uint32_t tsync_inc_l;
8504 uint32_t tsync_inc_h;
8506 /* Get current link speed. */
8507 memset(&link, 0, sizeof(link));
8508 i40e_dev_link_update(dev, 1);
8509 rte_i40e_dev_atomic_read_link_status(dev, &link);
8511 switch (link.link_speed) {
8512 case ETH_SPEED_NUM_40G:
8513 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8514 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8516 case ETH_SPEED_NUM_10G:
8517 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8518 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8520 case ETH_SPEED_NUM_1G:
8521 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8522 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8529 /* Set the timesync increment value. */
8530 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8531 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8533 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8534 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8535 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8537 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8538 adapter->systime_tc.cc_shift = 0;
8539 adapter->systime_tc.nsec_mask = 0;
8541 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8542 adapter->rx_tstamp_tc.cc_shift = 0;
8543 adapter->rx_tstamp_tc.nsec_mask = 0;
8545 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8546 adapter->tx_tstamp_tc.cc_shift = 0;
8547 adapter->tx_tstamp_tc.nsec_mask = 0;
8551 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8553 struct i40e_adapter *adapter =
8554 (struct i40e_adapter *)dev->data->dev_private;
8556 adapter->systime_tc.nsec += delta;
8557 adapter->rx_tstamp_tc.nsec += delta;
8558 adapter->tx_tstamp_tc.nsec += delta;
8564 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8567 struct i40e_adapter *adapter =
8568 (struct i40e_adapter *)dev->data->dev_private;
8570 ns = rte_timespec_to_ns(ts);
8572 /* Set the timecounters to a new value. */
8573 adapter->systime_tc.nsec = ns;
8574 adapter->rx_tstamp_tc.nsec = ns;
8575 adapter->tx_tstamp_tc.nsec = ns;
8581 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8583 uint64_t ns, systime_cycles;
8584 struct i40e_adapter *adapter =
8585 (struct i40e_adapter *)dev->data->dev_private;
8587 systime_cycles = i40e_read_systime_cyclecounter(dev);
8588 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8589 *ts = rte_ns_to_timespec(ns);
8595 i40e_timesync_enable(struct rte_eth_dev *dev)
8597 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8598 uint32_t tsync_ctl_l;
8599 uint32_t tsync_ctl_h;
8601 /* Stop the timesync system time. */
8602 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8603 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8604 /* Reset the timesync system time value. */
8605 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8606 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8608 i40e_start_timecounters(dev);
8610 /* Clear timesync registers. */
8611 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8612 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8613 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8614 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8615 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8616 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8618 /* Enable timestamping of PTP packets. */
8619 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8620 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8622 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8623 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8624 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8626 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8627 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8633 i40e_timesync_disable(struct rte_eth_dev *dev)
8635 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8636 uint32_t tsync_ctl_l;
8637 uint32_t tsync_ctl_h;
8639 /* Disable timestamping of transmitted PTP packets. */
8640 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8641 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8643 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8644 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8646 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8647 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8649 /* Reset the timesync increment value. */
8650 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8651 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8657 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8658 struct timespec *timestamp, uint32_t flags)
8660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8661 struct i40e_adapter *adapter =
8662 (struct i40e_adapter *)dev->data->dev_private;
8664 uint32_t sync_status;
8665 uint32_t index = flags & 0x03;
8666 uint64_t rx_tstamp_cycles;
8669 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8670 if ((sync_status & (1 << index)) == 0)
8673 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8674 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8675 *timestamp = rte_ns_to_timespec(ns);
8681 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8682 struct timespec *timestamp)
8684 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8685 struct i40e_adapter *adapter =
8686 (struct i40e_adapter *)dev->data->dev_private;
8688 uint32_t sync_status;
8689 uint64_t tx_tstamp_cycles;
8692 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8693 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8696 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8697 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8698 *timestamp = rte_ns_to_timespec(ns);
8704 * i40e_parse_dcb_configure - parse dcb configure from user
8705 * @dev: the device being configured
8706 * @dcb_cfg: pointer of the result of parse
8707 * @*tc_map: bit map of enabled traffic classes
8709 * Returns 0 on success, negative value on failure
8712 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8713 struct i40e_dcbx_config *dcb_cfg,
8716 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8717 uint8_t i, tc_bw, bw_lf;
8719 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8721 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8722 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8723 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8727 /* assume each tc has the same bw */
8728 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8729 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8730 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8731 /* to ensure the sum of tcbw is equal to 100 */
8732 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8733 for (i = 0; i < bw_lf; i++)
8734 dcb_cfg->etscfg.tcbwtable[i]++;
8736 /* assume each tc has the same Transmission Selection Algorithm */
8737 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8738 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8740 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8741 dcb_cfg->etscfg.prioritytable[i] =
8742 dcb_rx_conf->dcb_tc[i];
8744 /* FW needs one App to configure HW */
8745 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8746 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8747 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8748 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8750 if (dcb_rx_conf->nb_tcs == 0)
8751 *tc_map = 1; /* tc0 only */
8753 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8755 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8756 dcb_cfg->pfc.willing = 0;
8757 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8758 dcb_cfg->pfc.pfcenable = *tc_map;
8764 static enum i40e_status_code
8765 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8766 struct i40e_aqc_vsi_properties_data *info,
8767 uint8_t enabled_tcmap)
8769 enum i40e_status_code ret;
8770 int i, total_tc = 0;
8771 uint16_t qpnum_per_tc, bsf, qp_idx;
8772 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8773 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8774 uint16_t used_queues;
8776 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8777 if (ret != I40E_SUCCESS)
8780 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8781 if (enabled_tcmap & (1 << i))
8786 vsi->enabled_tc = enabled_tcmap;
8788 /* different VSI has different queues assigned */
8789 if (vsi->type == I40E_VSI_MAIN)
8790 used_queues = dev_data->nb_rx_queues -
8791 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8792 else if (vsi->type == I40E_VSI_VMDQ2)
8793 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8795 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8796 return I40E_ERR_NO_AVAILABLE_VSI;
8799 qpnum_per_tc = used_queues / total_tc;
8800 /* Number of queues per enabled TC */
8801 if (qpnum_per_tc == 0) {
8802 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8803 return I40E_ERR_INVALID_QP_ID;
8805 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8807 bsf = rte_bsf32(qpnum_per_tc);
8810 * Configure TC and queue mapping parameters, for enabled TC,
8811 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8812 * default queue will serve it.
8815 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8816 if (vsi->enabled_tc & (1 << i)) {
8817 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8818 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8819 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8820 qp_idx += qpnum_per_tc;
8822 info->tc_mapping[i] = 0;
8825 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8826 if (vsi->type == I40E_VSI_SRIOV) {
8827 info->mapping_flags |=
8828 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8829 for (i = 0; i < vsi->nb_qps; i++)
8830 info->queue_mapping[i] =
8831 rte_cpu_to_le_16(vsi->base_queue + i);
8833 info->mapping_flags |=
8834 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8835 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8837 info->valid_sections |=
8838 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8840 return I40E_SUCCESS;
8844 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8845 * @veb: VEB to be configured
8846 * @tc_map: enabled TC bitmap
8848 * Returns 0 on success, negative value on failure
8850 static enum i40e_status_code
8851 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8853 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8854 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8855 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8856 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8857 enum i40e_status_code ret = I40E_SUCCESS;
8861 /* Check if enabled_tc is same as existing or new TCs */
8862 if (veb->enabled_tc == tc_map)
8865 /* configure tc bandwidth */
8866 memset(&veb_bw, 0, sizeof(veb_bw));
8867 veb_bw.tc_valid_bits = tc_map;
8868 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8869 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8870 if (tc_map & BIT_ULL(i))
8871 veb_bw.tc_bw_share_credits[i] = 1;
8873 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8876 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8877 " per TC failed = %d",
8878 hw->aq.asq_last_status);
8882 memset(&ets_query, 0, sizeof(ets_query));
8883 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8885 if (ret != I40E_SUCCESS) {
8886 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8887 " configuration %u", hw->aq.asq_last_status);
8890 memset(&bw_query, 0, sizeof(bw_query));
8891 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8893 if (ret != I40E_SUCCESS) {
8894 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8895 " configuration %u", hw->aq.asq_last_status);
8899 /* store and print out BW info */
8900 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8901 veb->bw_info.bw_max = ets_query.tc_bw_max;
8902 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8903 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8904 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8905 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8907 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8908 veb->bw_info.bw_ets_share_credits[i] =
8909 bw_query.tc_bw_share_credits[i];
8910 veb->bw_info.bw_ets_credits[i] =
8911 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8912 /* 4 bits per TC, 4th bit is reserved */
8913 veb->bw_info.bw_ets_max[i] =
8914 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8915 RTE_LEN2MASK(3, uint8_t));
8916 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8917 veb->bw_info.bw_ets_share_credits[i]);
8918 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8919 veb->bw_info.bw_ets_credits[i]);
8920 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8921 veb->bw_info.bw_ets_max[i]);
8924 veb->enabled_tc = tc_map;
8931 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8932 * @vsi: VSI to be configured
8933 * @tc_map: enabled TC bitmap
8935 * Returns 0 on success, negative value on failure
8937 static enum i40e_status_code
8938 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8940 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8941 struct i40e_vsi_context ctxt;
8942 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8943 enum i40e_status_code ret = I40E_SUCCESS;
8946 /* Check if enabled_tc is same as existing or new TCs */
8947 if (vsi->enabled_tc == tc_map)
8950 /* configure tc bandwidth */
8951 memset(&bw_data, 0, sizeof(bw_data));
8952 bw_data.tc_valid_bits = tc_map;
8953 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8954 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8955 if (tc_map & BIT_ULL(i))
8956 bw_data.tc_bw_credits[i] = 1;
8958 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8960 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8961 " per TC failed = %d",
8962 hw->aq.asq_last_status);
8965 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8966 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8968 /* Update Queue Pairs Mapping for currently enabled UPs */
8969 ctxt.seid = vsi->seid;
8970 ctxt.pf_num = hw->pf_id;
8972 ctxt.uplink_seid = vsi->uplink_seid;
8973 ctxt.info = vsi->info;
8975 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8979 /* Update the VSI after updating the VSI queue-mapping information */
8980 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8982 PMD_INIT_LOG(ERR, "Failed to configure "
8983 "TC queue mapping = %d",
8984 hw->aq.asq_last_status);
8987 /* update the local VSI info with updated queue map */
8988 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8989 sizeof(vsi->info.tc_mapping));
8990 (void)rte_memcpy(&vsi->info.queue_mapping,
8991 &ctxt.info.queue_mapping,
8992 sizeof(vsi->info.queue_mapping));
8993 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8994 vsi->info.valid_sections = 0;
8996 /* query and update current VSI BW information */
8997 ret = i40e_vsi_get_bw_config(vsi);
9000 "Failed updating vsi bw info, err %s aq_err %s",
9001 i40e_stat_str(hw, ret),
9002 i40e_aq_str(hw, hw->aq.asq_last_status));
9006 vsi->enabled_tc = tc_map;
9013 * i40e_dcb_hw_configure - program the dcb setting to hw
9014 * @pf: pf the configuration is taken on
9015 * @new_cfg: new configuration
9016 * @tc_map: enabled TC bitmap
9018 * Returns 0 on success, negative value on failure
9020 static enum i40e_status_code
9021 i40e_dcb_hw_configure(struct i40e_pf *pf,
9022 struct i40e_dcbx_config *new_cfg,
9025 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9026 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9027 struct i40e_vsi *main_vsi = pf->main_vsi;
9028 struct i40e_vsi_list *vsi_list;
9029 enum i40e_status_code ret;
9033 /* Use the FW API if FW > v4.4*/
9034 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9035 (hw->aq.fw_maj_ver >= 5))) {
9036 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9037 " to configure DCB");
9038 return I40E_ERR_FIRMWARE_API_VERSION;
9041 /* Check if need reconfiguration */
9042 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9043 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9044 return I40E_SUCCESS;
9047 /* Copy the new config to the current config */
9048 *old_cfg = *new_cfg;
9049 old_cfg->etsrec = old_cfg->etscfg;
9050 ret = i40e_set_dcb_config(hw);
9053 "Set DCB Config failed, err %s aq_err %s\n",
9054 i40e_stat_str(hw, ret),
9055 i40e_aq_str(hw, hw->aq.asq_last_status));
9058 /* set receive Arbiter to RR mode and ETS scheme by default */
9059 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9060 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9061 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9062 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9063 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9064 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9065 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9066 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9067 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9068 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9069 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9070 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9071 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9073 /* get local mib to check whether it is configured correctly */
9075 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9076 /* Get Local DCB Config */
9077 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9078 &hw->local_dcbx_config);
9080 /* if Veb is created, need to update TC of it at first */
9081 if (main_vsi->veb) {
9082 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9084 PMD_INIT_LOG(WARNING,
9085 "Failed configuring TC for VEB seid=%d\n",
9086 main_vsi->veb->seid);
9088 /* Update each VSI */
9089 i40e_vsi_config_tc(main_vsi, tc_map);
9090 if (main_vsi->veb) {
9091 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9092 /* Beside main VSI and VMDQ VSIs, only enable default
9095 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9096 ret = i40e_vsi_config_tc(vsi_list->vsi,
9099 ret = i40e_vsi_config_tc(vsi_list->vsi,
9100 I40E_DEFAULT_TCMAP);
9102 PMD_INIT_LOG(WARNING,
9103 "Failed configuring TC for VSI seid=%d\n",
9104 vsi_list->vsi->seid);
9108 return I40E_SUCCESS;
9112 * i40e_dcb_init_configure - initial dcb config
9113 * @dev: device being configured
9114 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9116 * Returns 0 on success, negative value on failure
9119 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9121 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9122 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9125 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9126 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9130 /* DCB initialization:
9131 * Update DCB configuration from the Firmware and configure
9132 * LLDP MIB change event.
9134 if (sw_dcb == TRUE) {
9135 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9136 if (ret != I40E_SUCCESS)
9137 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9139 ret = i40e_init_dcb(hw);
9140 /* if sw_dcb, lldp agent is stopped, the return from
9141 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9144 if (ret != I40E_SUCCESS &&
9145 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9146 memset(&hw->local_dcbx_config, 0,
9147 sizeof(struct i40e_dcbx_config));
9148 /* set dcb default configuration */
9149 hw->local_dcbx_config.etscfg.willing = 0;
9150 hw->local_dcbx_config.etscfg.maxtcs = 0;
9151 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9152 hw->local_dcbx_config.etscfg.tsatable[0] =
9154 hw->local_dcbx_config.etsrec =
9155 hw->local_dcbx_config.etscfg;
9156 hw->local_dcbx_config.pfc.willing = 0;
9157 hw->local_dcbx_config.pfc.pfccap =
9158 I40E_MAX_TRAFFIC_CLASS;
9159 /* FW needs one App to configure HW */
9160 hw->local_dcbx_config.numapps = 1;
9161 hw->local_dcbx_config.app[0].selector =
9162 I40E_APP_SEL_ETHTYPE;
9163 hw->local_dcbx_config.app[0].priority = 3;
9164 hw->local_dcbx_config.app[0].protocolid =
9165 I40E_APP_PROTOID_FCOE;
9166 ret = i40e_set_dcb_config(hw);
9168 PMD_INIT_LOG(ERR, "default dcb config fails."
9169 " err = %d, aq_err = %d.", ret,
9170 hw->aq.asq_last_status);
9174 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9175 " aq_err = %d.", ret,
9176 hw->aq.asq_last_status);
9180 ret = i40e_aq_start_lldp(hw, NULL);
9181 if (ret != I40E_SUCCESS)
9182 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9184 ret = i40e_init_dcb(hw);
9186 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9187 PMD_INIT_LOG(ERR, "HW doesn't support"
9192 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9193 " aq_err = %d.", ret,
9194 hw->aq.asq_last_status);
9202 * i40e_dcb_setup - setup dcb related config
9203 * @dev: device being configured
9205 * Returns 0 on success, negative value on failure
9208 i40e_dcb_setup(struct rte_eth_dev *dev)
9210 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9211 struct i40e_dcbx_config dcb_cfg;
9215 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9216 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9220 if (pf->vf_num != 0)
9221 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9223 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9225 PMD_INIT_LOG(ERR, "invalid dcb config");
9228 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9230 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9238 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9239 struct rte_eth_dcb_info *dcb_info)
9241 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9242 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9243 struct i40e_vsi *vsi = pf->main_vsi;
9244 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9245 uint16_t bsf, tc_mapping;
9248 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9249 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9251 dcb_info->nb_tcs = 1;
9252 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9253 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9254 for (i = 0; i < dcb_info->nb_tcs; i++)
9255 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9257 /* get queue mapping if vmdq is disabled */
9258 if (!pf->nb_cfg_vmdq_vsi) {
9259 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9260 if (!(vsi->enabled_tc & (1 << i)))
9262 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9263 dcb_info->tc_queue.tc_rxq[j][i].base =
9264 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9265 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9266 dcb_info->tc_queue.tc_txq[j][i].base =
9267 dcb_info->tc_queue.tc_rxq[j][i].base;
9268 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9269 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9270 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9271 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9272 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9277 /* get queue mapping if vmdq is enabled */
9279 vsi = pf->vmdq[j].vsi;
9280 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9281 if (!(vsi->enabled_tc & (1 << i)))
9283 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9284 dcb_info->tc_queue.tc_rxq[j][i].base =
9285 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9286 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9287 dcb_info->tc_queue.tc_txq[j][i].base =
9288 dcb_info->tc_queue.tc_rxq[j][i].base;
9289 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9290 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9291 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9292 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9293 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9296 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9301 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9303 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9304 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9306 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9309 msix_intr = intr_handle->intr_vec[queue_id];
9310 if (msix_intr == I40E_MISC_VEC_ID)
9311 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9312 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9313 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9314 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9316 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9319 I40E_PFINT_DYN_CTLN(msix_intr -
9321 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9322 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9323 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9325 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9327 I40E_WRITE_FLUSH(hw);
9328 rte_intr_enable(&dev->pci_dev->intr_handle);
9334 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9336 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9337 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9340 msix_intr = intr_handle->intr_vec[queue_id];
9341 if (msix_intr == I40E_MISC_VEC_ID)
9342 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9345 I40E_PFINT_DYN_CTLN(msix_intr -
9348 I40E_WRITE_FLUSH(hw);
9353 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9355 /* Highest base addr + 32-bit word */
9356 return I40E_GLGEN_STAT_CLEAR + 4;
9359 static int i40e_get_regs(struct rte_eth_dev *dev,
9360 struct rte_dev_reg_info *regs)
9362 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9363 uint32_t *ptr_data = regs->data;
9364 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9365 const struct i40e_reg_info *reg_info;
9367 /* The first few registers have to be read using AQ operations */
9369 while (i40e_regs_adminq[reg_idx].name) {
9370 reg_info = &i40e_regs_adminq[reg_idx++];
9371 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9373 arr_idx2 <= reg_info->count2;
9375 reg_offset = arr_idx * reg_info->stride1 +
9376 arr_idx2 * reg_info->stride2;
9377 reg_offset += reg_info->base_addr;
9378 ptr_data[reg_offset >> 2] =
9379 i40e_read_rx_ctl(hw, reg_offset);
9383 /* The remaining registers can be read using primitives */
9385 while (i40e_regs_others[reg_idx].name) {
9386 reg_info = &i40e_regs_others[reg_idx++];
9387 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9389 arr_idx2 <= reg_info->count2;
9391 reg_offset = arr_idx * reg_info->stride1 +
9392 arr_idx2 * reg_info->stride2;
9393 reg_offset += reg_info->base_addr;
9394 ptr_data[reg_offset >> 2] =
9395 I40E_READ_REG(hw, reg_offset);
9402 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9404 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9406 /* Convert word count to byte count */
9407 return hw->nvm.sr_size << 1;
9410 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9411 struct rte_dev_eeprom_info *eeprom)
9413 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9414 uint16_t *data = eeprom->data;
9415 uint16_t offset, length, cnt_words;
9418 offset = eeprom->offset >> 1;
9419 length = eeprom->length >> 1;
9422 if (offset > hw->nvm.sr_size ||
9423 offset + length > hw->nvm.sr_size) {
9424 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9428 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9430 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9431 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9432 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9439 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9440 struct ether_addr *mac_addr)
9442 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9444 if (!is_valid_assigned_ether_addr(mac_addr)) {
9445 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9449 /* Flags: 0x3 updates port address */
9450 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9454 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9456 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9457 struct rte_eth_dev_data *dev_data = pf->dev_data;
9458 uint32_t frame_size = mtu + ETHER_HDR_LEN
9459 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9462 /* check if mtu is within the allowed range */
9463 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9466 /* mtu setting is forbidden if port is start */
9467 if (dev_data->dev_started) {
9469 "port %d must be stopped before configuration\n",
9474 if (frame_size > ETHER_MAX_LEN)
9475 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9477 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9479 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;